ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.

Incorrect value causes clock inaccuracy as huge as 1/60.

Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 47363

diff --git a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
index 761eda4df5adff7997cdbe6bc87e7f9345a9d6fc..ca92d0ec87cbd7b98624f0af5c4bce9c8429f88e 100644 (file)
--- a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
@@ -529,7 +529,7 @@
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT         0
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK          0x1f
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT         5
-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK          0x3fff
++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK          0x1fff
 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT            18
 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK             0x1ff
 +
@@ -541,7 +541,7 @@
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT         0
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK          0x1f
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT         5
-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK          0x3fff
++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK          0x1fff
 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT            18
 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK             0x1ff
 +