ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
authorFelix Fietkau <nbd@openwrt.org>
Mon, 2 Nov 2015 18:20:51 +0000 (18:20 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Mon, 2 Nov 2015 18:20:51 +0000 (18:20 +0000)
Incorrect value causes clock inaccuracy as huge as 1/60.

Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 47363

target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch

index 761eda4..ca92d0e 100644 (file)
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT         0
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK          0x1f
 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT         5
-+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK          0x3fff
++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK          0x1fff
 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT            18
 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK             0x1ff
 +
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT         0
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK          0x1f
 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT         5
-+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK          0x3fff
++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK          0x1fff
 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT            18
 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK             0x1ff
 +