--- /dev/null
+From b5057e498da8211ac3cc8ff5780034e5da61d077 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 23 Aug 2016 08:40:32 +0200
+Subject: [PATCH] ARM: BCM5301X: Add DT for Netgear R8500
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Netgear R8500 is another BCM47094 device, it just has three BCM4366
+wireless chipsets. It's a very standard DT with mostly GPIO devices.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 104 +++++++++++++++++++++++++++
+ 2 files changed, 105 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm4709-netgear-r7000.dtb \
+ bcm4709-netgear-r8000.dtb \
+ bcm47094-dlink-dir-885l.dtb \
++ bcm47094-netgear-r8500.dtb \
+ bcm94708.dtb \
+ bcm94709.dtb \
+ bcm953012er.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+@@ -0,0 +1,104 @@
++/*
++ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
++ *
++ * Licensed under the ISC license.
++ */
++
++/dts-v1/;
++
++#include "bcm4708.dtsi"
++#include "bcm5301x-nand-cs0-bch8.dtsi"
++
++/ {
++ compatible = "netgear,r8500", "brcm,bcm47094", "brcm,bcm4708";
++ model = "Netgear R8500";
++
++ chosen {
++ bootargs = "console=ttyS0,115200";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ power0 {
++ label = "bcm53xx:white:power";
++ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-on";
++ };
++
++ power1 {
++ label = "bcm53xx:amber:power";
++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ 5ghz-1 {
++ label = "bcm53xx:white:5ghz-1";
++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ 5ghz-2 {
++ label = "bcm53xx:white:5ghz-2";
++ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ 2ghz {
++ label = "bcm53xx:white:2ghz";
++ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ usb2 {
++ label = "bcm53xx:white:usb2";
++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ usb3 {
++ label = "bcm53xx:white:usb3";
++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ brightness {
++ label = "Backlight";
++ linux,code = <KEY_BRIGHTNESS_ZERO>;
++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
++ };
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
++ };
++
++ wps {
++ label = "WPS";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
++ };
++
++ rfkill {
++ label = "WiFi";
++ linux,code = <KEY_RFKILL>;
++ gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&uart0 {
++ status = "okay";
++ clock-frequency = <125000000>;
++};
--- /dev/null
+From 21c29be6a69d3ef4f5a2e16272deb4845f8208ad Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Tue, 23 Aug 2016 07:37:43 +0200
+Subject: [PATCH] ARM: BCM5301X: Add basic dts for BCM53573 based Tenda AC9
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM53573 seems to be low priced alternative for Northstar chipsts. It
+uses single core Cortex-A7 and doesn't have SDU or local (TWD) timer. It
+was also stripped out of independent SPI controller and 2 GMACs.
+
+DTS for Tenda AC9 isn't completed yet. It misses e.g. switch entry (we
+still need some b53 fixes) and probably some clocks. It adds support for
+basic features however and can be improved later.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 2 +
+ arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 74 ++++++++++++++++
+ arch/arm/boot/dts/bcm53573.dtsi | 147 +++++++++++++++++++++++++++++++
+ 3 files changed, 223 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm47189-tenda-ac9.dts
+ create mode 100644 arch/arm/boot/dts/bcm53573.dtsi
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -82,6 +82,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm94709.dtb \
+ bcm953012er.dtb \
+ bcm953012k.dtb
++dtb-$(CONFIG_ARCH_BCM_53573) += \
++ bcm47189-tenda-ac9.dtb
+ dtb-$(CONFIG_ARCH_BCM_63XX) += \
+ bcm963138dvt.dtb
+ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
+@@ -0,0 +1,74 @@
++/*
++ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
++ *
++ * Licensed under the ISC license.
++ */
++
++/dts-v1/;
++
++#include "bcm53573.dtsi"
++
++/ {
++ compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573";
++ model = "Tenda AC9";
++
++ chosen {
++ bootargs = "console=ttyS0,115200 earlycon";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ usb {
++ label = "bcm53xx:blue:usb";
++ gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ wps {
++ label = "bcm53xx:blue:wps";
++ gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ 5ghz {
++ label = "bcm53xx:blue:5ghz";
++ gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ system {
++ label = "bcm53xx:blue:system";
++ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "timer";
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rfkill {
++ label = "WiFi";
++ linux,code = <KEY_RFKILL>;
++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
++ };
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
++ };
++
++ wps {
++ label = "WPS";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm53573.dtsi
+@@ -0,0 +1,147 @@
++/*
++ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
++ *
++ * Licensed under the ISC license.
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include "skeleton.dtsi"
++
++/ {
++ interrupt-parent = <&gic>;
++
++ chosen {
++ stdout-path = &uart0;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0x0>;
++ };
++ };
++
++ mpcore {
++ compatible = "simple-bus";
++ ranges = <0x00000000 0x18310000 0x00008000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,cortex-a7-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0x1000 0x1000>,
++ <0x2000 0x0100>;
++ };
++ };
++
++ clocks {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ alp: oscillator {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <40000000>;
++ };
++ };
++
++ axi@18000000 {
++ compatible = "brcm,bus-axi";
++ reg = <0x18000000 0x1000>;
++ ranges = <0x00000000 0x18000000 0x00100000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0x000fffff 0xffff>;
++ interrupt-map =
++ /* ChipCommon */
++ <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++
++ /* IEEE 802.11 0 */
++ <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++
++ /* PCIe Controller 0 */
++ <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++
++ /* USB 2.0 Controller */
++ <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
++
++ /* Ethernet Controller 0 */
++ <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
++
++ /* IEEE 802.11 1 */
++ <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
++
++ /* Ethernet Controller 1 */
++ <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++
++ chipcommon: chipcommon@0 {
++ compatible = "simple-bus";
++ reg = <0x00000000 0x1000>;
++ ranges;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ uart0: serial@0300 {
++ compatible = "ns16550a";
++ reg = <0x0300 0x100>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&alp>;
++ status = "okay";
++ };
++ };
++
++ usb2: usb2@4000 {
++ reg = <0x4000 0x1000>;
++ ranges;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ ehci: ehci@4000 {
++ compatible = "generic-ehci";
++ reg = <0x4000 0x1000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ ohci: ohci@d000 {
++ #usb-cells = <0>;
++
++ compatible = "generic-ohci";
++ reg = <0xd000 0x1000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++ };
++ };
++
++ gmac0: ethernet@5000 {
++ reg = <0x5000 0x1000>;
++ };
++
++ gmac1: ethernet@b000 {
++ reg = <0xb000 0x1000>;
++ };
++ };
++};
--- /dev/null
+From 345fd105ff676ef672d1e41b31165b47aa040dab Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 21 Sep 2016 22:58:32 +0200
+Subject: [PATCH] ARM: BCM5301X: Add separated DTS include file for BCM47094
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use it to store BCM47094 specific properties/values and avoid repeating
+them in device DTS files.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 3 +--
+ arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 3 +--
+ arch/arm/boot/dts/bcm47094.dtsi | 11 +++++++++++
+ 3 files changed, 13 insertions(+), 4 deletions(-)
+ create mode 100644 arch/arm/boot/dts/bcm47094.dtsi
+
+--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+@@ -9,7 +9,7 @@
+
+ /dts-v1/;
+
+-#include "bcm4708.dtsi"
++#include "bcm47094.dtsi"
+ #include "bcm5301x-nand-cs0-bch1.dtsi"
+
+ / {
+@@ -107,7 +107,6 @@
+
+ &uart0 {
+ status = "okay";
+- clock-frequency = <125000000>;
+ };
+
+ &usb3 {
+--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
++++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+@@ -6,7 +6,7 @@
+
+ /dts-v1/;
+
+-#include "bcm4708.dtsi"
++#include "bcm47094.dtsi"
+ #include "bcm5301x-nand-cs0-bch8.dtsi"
+
+ / {
+@@ -100,5 +100,4 @@
+
+ &uart0 {
+ status = "okay";
+- clock-frequency = <125000000>;
+ };
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm47094.dtsi
+@@ -0,0 +1,11 @@
++/*
++ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
++ *
++ * Licensed under the ISC license.
++ */
++
++#include "bcm4708.dtsi"
++
++&uart0 {
++ clock-frequency = <125000000>;
++};
--- /dev/null
+From 3ede027b3dce2fca07350b7587c7c8f44706c94c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 21 Sep 2016 22:58:33 +0200
+Subject: [PATCH] ARM: BCM5301X: Enable UART on Netgear R8000
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It was tested by LEDE users, all we need is to adjust clock frequency.
+While we're at it create a separated DTS include file to share code with
+other BCM4709 devices easier.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 2 +-
+ arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 2 +-
+ arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 2 +-
+ arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 6 +++++-
+ arch/arm/boot/dts/bcm4709.dtsi | 11 +++++++++++
+ 5 files changed, 19 insertions(+), 4 deletions(-)
+ create mode 100644 arch/arm/boot/dts/bcm4709.dtsi
+
+--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+@@ -9,7 +9,7 @@
+
+ /dts-v1/;
+
+-#include "bcm4708.dtsi"
++#include "bcm4709.dtsi"
+ #include "bcm5301x-nand-cs0-bch8.dtsi"
+
+ / {
+--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+@@ -9,7 +9,7 @@
+
+ /dts-v1/;
+
+-#include "bcm4708.dtsi"
++#include "bcm4709.dtsi"
+ #include "bcm5301x-nand-cs0-bch8.dtsi"
+
+ / {
+--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+@@ -9,7 +9,7 @@
+
+ /dts-v1/;
+
+-#include "bcm4708.dtsi"
++#include "bcm4709.dtsi"
+ #include "bcm5301x-nand-cs0-bch8.dtsi"
+
+ / {
+--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+@@ -9,7 +9,7 @@
+
+ /dts-v1/;
+
+-#include "bcm4708.dtsi"
++#include "bcm4709.dtsi"
+ #include "bcm5301x-nand-cs0-bch8.dtsi"
+
+ / {
+@@ -107,6 +107,10 @@
+ };
+ };
+
++&uart0 {
++ status = "okay";
++};
++
+ &usb2 {
+ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
+ };
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm4709.dtsi
+@@ -0,0 +1,11 @@
++/*
++ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
++ *
++ * Licensed under the ISC license.
++ */
++
++#include "bcm4708.dtsi"
++
++&uart0 {
++ clock-frequency = <125000000>;
++};
--- /dev/null
+From 5b92db97f4ae345bd6f045c9427471680a7fe2e7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 21 Sep 2016 22:58:34 +0200
+Subject: [PATCH] ARM: BCM5301X: Specify USB 3.0 PHY in DT
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Driver for Northstar USB 3.0 PHY has been recently added under the name
+phy-bcm-ns-usb3. Add binding for it into the DT files.
+The only slightly tricky part is BCM47094 which uses different PHY
+version and requires different compatible value.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm47094.dtsi | 6 ++++++
+ arch/arm/boot/dts/bcm5301x.dtsi | 7 +++++++
+ 2 files changed, 13 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm47094.dtsi
++++ b/arch/arm/boot/dts/bcm47094.dtsi
+@@ -6,6 +6,12 @@
+
+ #include "bcm4708.dtsi"
+
++/ {
++ usb3_phy: usb3-phy {
++ compatible = "brcm,ns-bx-usb3-phy";
++ };
++};
++
+ &uart0 {
+ clock-frequency = <125000000>;
+ };
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -149,6 +149,13 @@
+ clock-names = "phy-ref-clk";
+ };
+
++ usb3_phy: usb3-phy {
++ compatible = "brcm,ns-ax-usb3-phy";
++ reg = <0x18105000 0x1000>, <0x18003000 0x1000>;
++ reg-names = "dmp", "ccb-mii";
++ #phy-cells = <0>;
++ };
++
+ axi@18000000 {
+ compatible = "brcm,bus-axi";
+ reg = <0x18000000 0x1000>;
--- /dev/null
+From 46daccf62d1651bf8b09978478ca6465a7a81f47 Mon Sep 17 00:00:00 2001
+From: Dan Haab <dhaab@luxul.com>
+Date: Tue, 27 Sep 2016 11:27:10 -0600
+Subject: [PATCH] ARM: BCM5301X: Add DT for Luxul XAP-1510
+
+Luxul XAP-1510 is an AP device based on BCM4708 SoC with 2 x BCM4360
+chipsets on PCB connected using PCIe.
+
+Signed-off-by: Dan Haab <dhaab@luxul.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 64 ++++++++++++++++++++++++++++
+ 2 files changed, 65 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -65,6 +65,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm4708-asus-rt-ac56u.dtb \
+ bcm4708-asus-rt-ac68u.dtb \
+ bcm4708-buffalo-wzr-1750dhp.dtb \
++ bcm4708-luxul-xap-1510.dtb \
+ bcm4708-luxul-xwc-1000.dtb \
+ bcm4708-netgear-r6250.dtb \
+ bcm4708-netgear-r6300-v2.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
+@@ -0,0 +1,64 @@
++/*
++ * Copyright 2016 Luxul Inc.
++ *
++ * Licensed under the ISC license.
++ */
++
++/dts-v1/;
++
++#include "bcm4708.dtsi"
++
++/ {
++ compatible = "luxul,xap-1510v1", "brcm,bcm4708";
++ model = "Luxul XAP-1510 V1";
++
++ chosen {
++ bootargs = "console=ttyS0,115200 earlycon";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ 5ghz {
++ label = "bcm53xx:blue:5ghz";
++ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ 2ghz {
++ label = "bcm53xx:blue:2ghz";
++ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ status {
++ label = "bcm53xx:green:status";
++ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "timer";
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&spi_nor {
++ status = "okay";
++};
--- /dev/null
+From ef3bc318adeb15b38688df6a583bafea2befce43 Mon Sep 17 00:00:00 2001
+From: Dan Haab <dhaab@luxul.com>
+Date: Tue, 27 Sep 2016 11:27:11 -0600
+Subject: [PATCH] ARM: BCM5301X: Add DT for Luxul XWR-3100
+
+Luxul XWR-3100 is a wireless router based on BCM47094 SoC with two
+4366c0 FullMAC PCIe cards on the PCB. It uses NAND with BCH-4 ECC
+algorithm.
+
+Signed-off-by: Dan Haab <dhaab@luxul.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 111 ++++++++++++++++++++++++++
+ arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi | 13 +++
+ 3 files changed, 125 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+ create mode 100644 arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm4709-netgear-r7000.dtb \
+ bcm4709-netgear-r8000.dtb \
+ bcm47094-dlink-dir-885l.dtb \
++ bcm47094-luxul-xwr-3100.dtb \
+ bcm47094-netgear-r8500.dtb \
+ bcm94708.dtb \
+ bcm94709.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+@@ -0,0 +1,111 @@
++/*
++ * Copyright 2016 Luxul Inc.
++ *
++ * Licensed under the ISC license.
++ */
++
++/dts-v1/;
++
++#include "bcm47094.dtsi"
++#include "bcm5301x-nand-cs0-bch4.dtsi"
++
++/ {
++ compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708";
++ model = "Luxul XWR-3100 V1";
++
++ chosen {
++ bootargs = "console=ttyS0,115200 earlycon";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ power {
++ label = "bcm53xx:green:power";
++ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-on";
++ };
++
++ lan3 {
++ label = "bcm53xx:green:lan1";
++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ lan4 {
++ label = "bcm53xx:green:lan0";
++ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ wan {
++ label = "bcm53xx:green:wan";
++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ lan1 {
++ label = "bcm53xx:green:lan3";
++ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ lan2 {
++ label = "bcm53xx:green:lan2";
++ gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ usb3 {
++ label = "bcm53xx:green:usb3";
++ gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ status {
++ label = "bcm53xx:green:status";
++ gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "timer";
++ };
++
++ 2ghz {
++ label = "bcm53xx:green:2ghz";
++ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++
++ 5ghz {
++ label = "bcm53xx:green:5ghz";
++ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-off";
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&usb3 {
++ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
++};
++
++&spi_nor {
++ status = "okay";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi
+@@ -0,0 +1,13 @@
++/*
++ * Copyright 2016 Luxul Inc.
++ *
++ * Licensed under the ISC license.
++ */
++
++#include "bcm5301x-nand-cs0.dtsi"
++
++&nandcs {
++ nand-ecc-algo = "bch";
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++};
--- /dev/null
+From 547f23183d9d77b51754689a71e3e58d085ccaec Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sat, 17 Sep 2016 22:13:46 +0200
+Subject: [PATCH] ARM: BCM53573: Specify PMU and its ILP clock in the DT
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+ILP clock (sometimes called a "slow clock") is a part of PMU (Power
+Management Unit). There has been recently added a driver for it, so add
+a proper entry in the DT as well.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm53573.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm53573.dtsi
++++ b/arch/arm/boot/dts/bcm53573.dtsi
+@@ -143,5 +143,17 @@
+ gmac1: ethernet@b000 {
+ reg = <0xb000 0x1000>;
+ };
++
++ pmu@12000 {
++ compatible = "simple-mfd", "syscon";
++ reg = <0x00012000 0x00001000>;
++
++ ilp: ilp {
++ compatible = "brcm,bcm53573-ilp";
++ clocks = <&alp>;
++ #clock-cells = <0>;
++ clock-output-names = "ilp";
++ };
++ };
+ };
+ };
--- /dev/null
+From 41182beb217c47cfbaaf26a60f22a8b3943faa61 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sun, 13 Nov 2016 11:12:09 +0100
+Subject: [PATCH] ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's BCM4709A0 based device with 16 MiB flash, 128 MiB of RAM and two
+PCIe based on-PCB BCM4360 chipsets.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 114 ++++++++++++++++++++++
+ 2 files changed, 115 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm4709-buffalo-wxr-1900dhp.dtb \
+ bcm4709-netgear-r7000.dtb \
+ bcm4709-netgear-r8000.dtb \
++ bcm4709-tplink-archer-c9-v1.dtb \
+ bcm47094-dlink-dir-885l.dtb \
+ bcm47094-luxul-xwr-3100.dtb \
+ bcm47094-netgear-r8500.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
+@@ -0,0 +1,114 @@
++/*
++ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
++ *
++ * Licensed under the ISC license.
++ */
++
++/dts-v1/;
++
++#include "bcm4709.dtsi"
++
++/ {
++ compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708";
++ model = "TP-LINK Archer C9 V1";
++
++ chosen {
++ bootargs = "console=ttyS0,115200 earlycon";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ lan {
++ label = "bcm53xx:blue:lan";
++ gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ wps {
++ label = "bcm53xx:blue:wps";
++ gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ 2ghz {
++ label = "bcm53xx:blue:2ghz";
++ gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ 5ghz {
++ label = "bcm53xx:blue:5ghz";
++ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ usb3 {
++ label = "bcm53xx:blue:usb3";
++ gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ usb2 {
++ label = "bcm53xx:blue:usb2";
++ gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ wan-blue {
++ label = "bcm53xx:blue:wan";
++ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ wan-amber {
++ label = "bcm53xx:amber:wan";
++ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-off";
++ };
++
++ power {
++ label = "bcm53xx:blue:power";
++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-on";
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ wps {
++ label = "WPS";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
++ };
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&usb2 {
++ vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
++};
++
++&usb3 {
++ vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
++};
++
++&spi_nor {
++ status = "okay";
++};
--- /dev/null
+From 09f3510fb70a46c8921f2cf4a90dbcae460a6820 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sat, 29 Oct 2016 13:12:29 +0200
+Subject: [PATCH] ARM: BCM5301X: Add back handler ignoring external imprecise
+ aborts
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Since early BCM5301X days we got abort handler that was removed by
+commit 937b12306ea79 ("ARM: BCM5301X: remove workaround imprecise abort
+fault handler"). It assumed we need to deal only with pending aborts
+left by the bootloader. Unfortunately this isn't true for BCM5301X.
+
+When probing PCI config space (device enumeration) it is expected to
+have master aborts on the PCI bus. Most bridges don't forward (or they
+allow disabling it) these errors onto the AXI/AMBA bus but not the
+Northstar (BCM5301X) one.
+
+iProc PCIe controller on Northstar seems to be some older one, without
+a control register for errors forwarding. It means we need to workaround
+this at platform level. All newer platforms are not affected by this
+issue.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/mach-bcm/bcm_5301x.c | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/arch/arm/mach-bcm/bcm_5301x.c
++++ b/arch/arm/mach-bcm/bcm_5301x.c
+@@ -9,14 +9,42 @@
+ #include <asm/hardware/cache-l2x0.h>
+
+ #include <asm/mach/arch.h>
++#include <asm/siginfo.h>
++#include <asm/signal.h>
++
++#define FSR_EXTERNAL (1 << 12)
++#define FSR_READ (0 << 10)
++#define FSR_IMPRECISE 0x0406
+
+ static const char *const bcm5301x_dt_compat[] __initconst = {
+ "brcm,bcm4708",
+ NULL,
+ };
+
++static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
++ struct pt_regs *regs)
++{
++ /*
++ * We want to ignore aborts forwarded from the PCIe bus that are
++ * expected and shouldn't really be passed by the PCIe controller.
++ * The biggest disadvantage is the same FSR code may be reported when
++ * reading non-existing APB register and we shouldn't ignore that.
++ */
++ if (fsr == (FSR_EXTERNAL | FSR_READ | FSR_IMPRECISE))
++ return 0;
++
++ return 1;
++}
++
++static void __init bcm5301x_init_early(void)
++{
++ hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
++ "imprecise external abort");
++}
++
+ DT_MACHINE_START(BCM5301X, "BCM5301X")
+ .l2c_aux_val = 0,
+ .l2c_aux_mask = ~0,
+ .dt_compat = bcm5301x_dt_compat,
++ .init_early = bcm5301x_init_early,
+ MACHINE_END
--- /dev/null
+From 2b354a7c56f375ba414b9b9c96f160f5749e5e64 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 1 Dec 2016 18:40:51 +0100
+Subject: [PATCH 1/6] ARM: BCM5301X: Enable UART by default for BCM4708(1),
+ BCM4709(4) & BCM53012
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Every device tested so far got UART0 (at 0x18000300) working as serial
+console. It's most likely part of reference design and all vendors use
+it that way.
+
+It seems to be easier to enable it by default and just disable it if we
+ever see a device with different hardware design.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Jon Mason <jon.mason@broadcom.com>
+Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 4 ----
+ arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 4 ----
+ arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 4 ----
+ arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 4 ----
+ arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 4 ----
+ arch/arm/boot/dts/bcm4708.dtsi | 4 ++++
+ arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 4 ----
+ arch/arm/boot/dts/bcm47081.dtsi | 4 ++++
+ arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 4 ----
+ arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 4 ----
+ arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 4 ----
+ arch/arm/boot/dts/bcm4709.dtsi | 1 +
+ arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 4 ----
+ arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 4 ----
+ arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 4 ----
+ arch/arm/boot/dts/bcm47094.dtsi | 1 +
+ arch/arm/boot/dts/bcm94708.dts | 4 ----
+ arch/arm/boot/dts/bcm94709.dts | 4 ----
+ arch/arm/boot/dts/bcm953012er.dts | 4 ----
+ arch/arm/boot/dts/bcm953012k.dts | 1 -
+ 20 files changed, 10 insertions(+), 61 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+@@ -136,10 +136,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &usb2 {
+ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
+ };
+--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
++++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
+@@ -55,10 +55,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &spi_nor {
+ status = "okay";
+ };
+--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
++++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
+@@ -56,10 +56,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &spi_nor {
+ status = "okay";
+ };
+--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+@@ -83,10 +83,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &usb3 {
+ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
+ };
+--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+@@ -119,10 +119,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &spi_nor {
+ status = "okay";
+ };
+--- a/arch/arm/boot/dts/bcm4708.dtsi
++++ b/arch/arm/boot/dts/bcm4708.dtsi
+@@ -34,3 +34,7 @@
+ };
+
+ };
++
++&uart0 {
++ status = "okay";
++};
+--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+@@ -122,7 +122,3 @@
+ };
+ };
+ };
+-
+-&uart0 {
+- status = "okay";
+-};
+--- a/arch/arm/boot/dts/bcm47081.dtsi
++++ b/arch/arm/boot/dts/bcm47081.dtsi
+@@ -24,3 +24,7 @@
+ };
+ };
+ };
++
++&uart0 {
++ status = "okay";
++};
+--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+@@ -100,7 +100,3 @@
+ };
+ };
+ };
+-
+-&uart0 {
+- status = "okay";
+-};
+--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+@@ -107,10 +107,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &usb2 {
+ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
+ };
+--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
++++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
+@@ -97,10 +97,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &usb2 {
+ vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+ };
+--- a/arch/arm/boot/dts/bcm4709.dtsi
++++ b/arch/arm/boot/dts/bcm4709.dtsi
+@@ -8,4 +8,5 @@
+
+ &uart0 {
+ clock-frequency = <125000000>;
++ status = "okay";
+ };
+--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+@@ -105,10 +105,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &usb3 {
+ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
+ };
+--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+@@ -98,10 +98,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &usb3 {
+ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
+ };
+--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
++++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+@@ -97,7 +97,3 @@
+ };
+ };
+ };
+-
+-&uart0 {
+- status = "okay";
+-};
+--- a/arch/arm/boot/dts/bcm47094.dtsi
++++ b/arch/arm/boot/dts/bcm47094.dtsi
+@@ -14,4 +14,5 @@
+
+ &uart0 {
+ clock-frequency = <125000000>;
++ status = "okay";
+ };
+--- a/arch/arm/boot/dts/bcm94708.dts
++++ b/arch/arm/boot/dts/bcm94708.dts
+@@ -50,7 +50,3 @@
+ reg = <0x00000000 0x08000000>;
+ };
+ };
+-
+-&uart0 {
+- status = "okay";
+-};
+--- a/arch/arm/boot/dts/bcm94709.dts
++++ b/arch/arm/boot/dts/bcm94709.dts
+@@ -50,7 +50,3 @@
+ reg = <0x00000000 0x08000000>;
+ };
+ };
+-
+-&uart0 {
+- status = "okay";
+-};
+--- a/arch/arm/boot/dts/bcm953012er.dts
++++ b/arch/arm/boot/dts/bcm953012er.dts
+@@ -70,10 +70,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ &spi_nor {
+ status = "okay";
+ };
+--- a/arch/arm/boot/dts/bcm953012k.dts
++++ b/arch/arm/boot/dts/bcm953012k.dts
+@@ -54,7 +54,6 @@
+
+ &uart0 {
+ clock-frequency = <62499840>;
+- status = "okay";
+ };
+
+ &uart1 {
--- /dev/null
+From 24e24f72379638d598aec5d0525ef57d5bfc5c51 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 7 Dec 2016 08:56:51 +0100
+Subject: [PATCH 2/6] ARM: BCM5301X: Fix LAN LED labels for Luxul XWR-3100
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+They were named incorrectly most likely due to copy & paste mistake.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+@@ -31,13 +31,13 @@
+ };
+
+ lan3 {
+- label = "bcm53xx:green:lan1";
++ label = "bcm53xx:green:lan3";
+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+
+ lan4 {
+- label = "bcm53xx:green:lan0";
++ label = "bcm53xx:green:lan4";
+ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
+@@ -49,7 +49,7 @@
+ };
+
+ lan1 {
+- label = "bcm53xx:green:lan3";
++ label = "bcm53xx:green:lan1";
+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-off";
+ };
--- /dev/null
+From 45d2567b4b80a3f267502419aaad3d74b745dae7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 7 Dec 2016 08:56:52 +0100
+Subject: [PATCH 3/6] ARM: BCM5301X: Specify USB controllers in DT
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are 3 separated controllers, one per USB /standard/. With PHY
+drivers in place they can be simply supported with generic drivers.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Ray Jui <ray.jui@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm5301x.dtsi | 33 ++++++++++++++++++++++++++++++++-
+ 1 file changed, 32 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -248,8 +248,26 @@
+
+ #address-cells = <1>;
+ #size-cells = <1>;
++ ranges;
+
+- phys = <&usb2_phy>;
++ interrupt-parent = <&gic>;
++
++ ehci: ehci@21000 {
++ #usb-cells = <0>;
++
++ compatible = "generic-ehci";
++ reg = <0x00021000 0x1000>;
++ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb2_phy>;
++ };
++
++ ohci: ohci@22000 {
++ #usb-cells = <0>;
++
++ compatible = "generic-ohci";
++ reg = <0x00022000 0x1000>;
++ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++ };
+ };
+
+ usb3: usb3@23000 {
+@@ -257,6 +275,19 @@
+
+ #address-cells = <1>;
+ #size-cells = <1>;
++ ranges;
++
++ interrupt-parent = <&gic>;
++
++ xhci: xhci@23000 {
++ #usb-cells = <0>;
++
++ compatible = "generic-xhci";
++ reg = <0x00023000 0x1000>;
++ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb3_phy>;
++ phy-names = "usb";
++ };
+ };
+
+ spi@29000 {
--- /dev/null
+From 1aca202b721ce8643f87a8f85a686595c1be6b60 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 7 Dec 2016 08:56:53 +0100
+Subject: [PATCH 4/6] ARM: BCM5301X: Set GPIO enabling USB power on Netgear
+ R7000
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There is one GPIO controlling power for both USB ports.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+@@ -100,3 +100,11 @@
+ };
+ };
+ };
++
++&usb2 {
++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
++};
++
++&usb3 {
++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
++};
--- /dev/null
+From 94afd3b99c65072b76edd25f73bad89587b83261 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 7 Dec 2016 08:56:54 +0100
+Subject: [PATCH 5/6] ARM: BCM5301X: Specify all RAM by including an extra
+ block
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The first 128 MiB of RAM can be accessed using an alias at address 0x0.
+
+In theory we could access whole RAM using 0x80000000 - 0xbfffffff range
+(up to 1 GiB) but it doesn't seem to work on Northstar. For some reason
+(hardware setup left by the bootloader maybe?) 0x80000000 - 0x87ffffff
+range can't be used. I reproduced this problem on:
+1) Buffalo WZR-600DHP2 (BCM47081)
+2) Netgear R6250 (BCM4708)
+3) D-Link DIR-885L (BCM47094)
+
+So it seems we're forced to access first 128 MiB using alias at 0x0 and
+the rest using real base address + 128 MiB offset which is 0x88000000.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Jon Mason <jon.mason@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 3 ++-
+ arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 3 ++-
+ arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 3 ++-
+ arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 3 ++-
+ arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 3 ++-
+ arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 3 ++-
+ arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 3 ++-
+ arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 3 ++-
+ arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 3 ++-
+ arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 3 ++-
+ arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 3 ++-
+ arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 3 ++-
+ arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 3 ++-
+ arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 3 ++-
+ arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 3 ++-
+ arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 3 ++-
+ 16 files changed, 32 insertions(+), 16 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x18000000>;
+ };
+
+ spi {
+--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ spi {
+--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ gpio-keys {
+--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x18000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+@@ -21,7 +21,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ nand: nand@18028000 {
+--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+@@ -18,7 +18,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
+ };
+
+ leds {
+--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
++++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+@@ -18,7 +18,8 @@
+ };
+
+ memory {
+- reg = <0x00000000 0x08000000>;
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x18000000>;
+ };
+
+ leds {
--- /dev/null
+From 92c6f000cb3a4280166d812d88cda3011717b548 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 7 Dec 2016 08:56:55 +0100
+Subject: [PATCH 6/6] ARM: BCM53573: Specify USB ports of on-SoC controllers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Broadcom OHCI and EHCI controllers always have 2 ports each on the root
+hub. Describe them in DT to allow specifying extra info or referencing
+port nodes.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm53573.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm53573.dtsi
++++ b/arch/arm/boot/dts/bcm53573.dtsi
+@@ -124,6 +124,17 @@
+ reg = <0x4000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ehci_port1: port@1 {
++ reg = <1>;
++ };
++
++ ehci_port2: port@2 {
++ reg = <2>;
++ };
+ };
+
+ ohci: ohci@d000 {
+@@ -133,6 +144,17 @@
+ reg = <0xd000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ohci_port1: port@1 {
++ reg = <1>;
++ };
++
++ ohci_port2: port@2 {
++ reg = <2>;
++ };
+ };
+ };
+
--- /dev/null
+From d3af86018715ebb19f4111f80e545405b208f09b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sat, 14 Jan 2017 00:58:57 +0100
+Subject: [PATCH] ARM: BCM5301X: Set 5 GHz wireless frequency limits on Netgear
+ R8000
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Netgear R8000 is a tri-band home router. It has three BCM43602 chipsets
+two of them for 5 GHz band. Both seem the same and their firmwares
+report the same set of channels. The problem is due to hardware / board
+design there are extra limitations that should be respected.
+
+First PHY should be used for U-NII-2 and U-NII-3. Third PHY should be
+used for U-NII-1. Using them in a different way may result in wireless
+not working or in noticeably reduced performance. Basic version of this
+info was provided by Broadcom employee, then it has been verified by me
+using original vendor firmware (which has limitations hardcoded in UI).
+
+This patch uses recently introduced ieee80211-freq-limit property to
+describe these limitations at DT level.
+
+Referencing PCIe devices in DT required specifying all related bridges.
+Below you can see (a bit complex) PCI tree from R8000 that explains all
+entries that I needed to put in DT.
+
+0000:00:00.0 14e4:8012 Bridge Device
+└─ 0000:01:00.0 14e4:aa52 Network Controller
+
+0001:00:00.0 14e4:8012 Bridge Device
+└─ 0001:01:00.0 10b5:8603 Bridge Device
+ ├─ 0001:02:01.0 10b5:8603 Bridge Device
+ │ └─ 0001:03:00.0 14e4:aa52 Network Controller
+ ├─ 0001:02:02.0 10b5:8603 Bridge Device
+ │ └─ 0001:04:00.0 14e4:aa52 Network Controller
+ ├─ 0001:02:03.0 000d:0000 0x000000
+ ├─ 0001:02:04.0 000d:0000 0x000000
+ ├─ 0001:02:05.0 000d:0000 0x000000
+ ├─ 0001:02:06.0 000d:0000 0x000000
+ ├─ (...)
+ ├─ 0001:02:1d.0 000d:0000 0x000000
+ ├─ 0001:02:1e.0 000d:0000 0x000000
+ └─ 0001:02:1f.0 000d:0000 0x000000
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 48 +++++++++++++++++++++++++++++
+ arch/arm/boot/dts/bcm5301x.dtsi | 8 +++++
+ 2 files changed, 56 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+@@ -108,6 +108,54 @@
+ };
+ };
+
++&pcie0 {
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ bridge@0,0,0 {
++ reg = <0x0000 0 0 0 0>;
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ wifi@0,1,0 {
++ reg = <0x0000 0 0 0 0>;
++ ieee80211-freq-limit = <5735000 5835000>;
++ };
++ };
++};
++
++&pcie1 {
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ bridge@1,0,0 {
++ reg = <0x0000 0 0 0 0>;
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ bridge@1,1,0 {
++ reg = <0x0000 0 0 0 0>;
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ bridge@1,2,2 {
++ reg = <0x1000 0 0 0 0>;
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ wifi@1,4,0 {
++ reg = <0x0000 0 0 0 0>;
++ ieee80211-freq-limit = <5170000 5730000>;
++ };
++ };
++ };
++ };
++};
++
+ &usb2 {
+ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
+ };
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -243,6 +243,14 @@
+ #gpio-cells = <2>;
+ };
+
++ pcie0: pcie@12000 {
++ reg = <0x00012000 0x1000>;
++ };
++
++ pcie1: pcie@13000 {
++ reg = <0x00013000 0x1000>;
++ };
++
+ usb2: usb2@21000 {
+ reg = <0x00021000 0x1000>;
+
--- /dev/null
+From eeacbb3e30f220d5d775c61421f813d4e186a325 Mon Sep 17 00:00:00 2001
+From: Dan Haab <dhaab@luxul.com>
+Date: Sat, 14 Jan 2017 19:29:27 -0700
+Subject: [PATCH] ARM: BCM5301X: Add DT for Luxul XAP-1410
+
+Luxul XAP-1410 in a dual-band access point device based on BCM47081 with
+serial flash. It has 3 LEDs and just one (reset) button.
+
+Signed-off-by: Dan Haab <dhaab@luxul.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 60 +++++++++++++++++++++++++++
+ 2 files changed, 61 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm47081-asus-rt-n18u.dtb \
+ bcm47081-buffalo-wzr-600dhp2.dtb \
+ bcm47081-buffalo-wzr-900dhp.dtb \
++ bcm47081-luxul-xap-1410.dtb \
+ bcm4709-asus-rt-ac87u.dtb \
+ bcm4709-buffalo-wxr-1900dhp.dtb \
+ bcm4709-netgear-r7000.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
+@@ -0,0 +1,60 @@
++/*
++ * Copyright 2017 Luxul Inc.
++ *
++ * Licensed under the ISC license.
++ */
++
++/dts-v1/;
++
++#include "bcm47081.dtsi"
++
++/ {
++ compatible = "luxul,xap-1410v1", "brcm,bcm47081", "brcm,bcm4708";
++ model = "Luxul XAP-1410 V1";
++
++ chosen {
++ bootargs = "console=ttyS0,115200";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ 5ghz {
++ label = "bcm53xx:blue:5ghz";
++ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ 2ghz {
++ label = "bcm53xx:blue:2ghz";
++ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ status {
++ label = "bcm53xx:green:status";
++ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "timer";
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&spi_nor {
++ status = "okay";
++};
--- /dev/null
+From 514647c9af870bd2df2e579134a26bff8d17b6b9 Mon Sep 17 00:00:00 2001
+From: Dan Haab <dhaab@luxul.com>
+Date: Sat, 14 Jan 2017 19:29:28 -0700
+Subject: [PATCH] ARM: BCM5301X: Add DT for Luxul XWR-1200
+
+Luxul XWR-1200 in a dual-band router based on BCM47081. It uses serial
+flash (for bootloader and NVRAM) and NAND flash (for firmware).
+
+Signed-off-by: Dan Haab <dhaab@luxul.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 107 ++++++++++++++++++++++++++
+ 2 files changed, 108 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm47081-buffalo-wzr-600dhp2.dtb \
+ bcm47081-buffalo-wzr-900dhp.dtb \
+ bcm47081-luxul-xap-1410.dtb \
++ bcm47081-luxul-xwr-1200.dtb \
+ bcm4709-asus-rt-ac87u.dtb \
+ bcm4709-buffalo-wxr-1900dhp.dtb \
+ bcm4709-netgear-r7000.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
+@@ -0,0 +1,107 @@
++/*
++ * Copyright 2017 Luxul Inc.
++ *
++ * Licensed under the ISC license.
++ */
++
++/dts-v1/;
++
++#include "bcm47081.dtsi"
++#include "bcm5301x-nand-cs0-bch4.dtsi"
++
++/ {
++ compatible = "luxul,xwr-1200v1", "brcm,bcm47081", "brcm,bcm4708";
++ model = "Luxul XWR-1200 V1";
++
++ chosen {
++ bootargs = "console=ttyS0,115200";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ power {
++ label = "bcm53xx:green:power";
++ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-on";
++ };
++
++ lan3 {
++ label = "bcm53xx:green:lan3";
++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ lan4 {
++ label = "bcm53xx:green:lan4";
++ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ wan {
++ label = "bcm53xx:green:wan";
++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ lan2 {
++ label = "bcm53xx:green:lan2";
++ gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ usb {
++ label = "bcm53xx:green:usb";
++ gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ status {
++ label = "bcm53xx:green:status";
++ gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "timer";
++ };
++
++ 2ghz {
++ label = "bcm53xx:green:2ghz";
++ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ 5ghz {
++ label = "bcm53xx:green:5ghz";
++ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++
++ lan1 {
++ label = "bcm53xx:green:lan1";
++ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "none";
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&usb2 {
++ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
++};
++
++&spi_nor {
++ status = "okay";
++};
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Subject: [PATCH] ARM: dts: BCM5301X: Add basic DT for Linksys EA9200
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's tri-band wireless home router based on BCM4709A0 with 3 x BCM43602
+chipsets. LEDs will be hopefully added later to the DT.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/bcm4709-linksys-ea9200.dts | 42 ++++++++++++++++++++++++++++
+ 2 files changed, 43 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm47081-luxul-xwr-1200.dtb \
+ bcm4709-asus-rt-ac87u.dtb \
+ bcm4709-buffalo-wxr-1900dhp.dtb \
++ bcm4709-linksys-ea9200.dtb \
+ bcm4709-netgear-r7000.dtb \
+ bcm4709-netgear-r8000.dtb \
+ bcm4709-tplink-archer-c9-v1.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
+@@ -0,0 +1,42 @@
++/*
++ * Copyright (C) 2017 Rafał Miłecki <rafal@milecki.pl>
++ *
++ * Licensed under the ISC license.
++ */
++
++/dts-v1/;
++
++#include "bcm4709.dtsi"
++#include "bcm5301x-nand-cs0-bch8.dtsi"
++
++/ {
++ compatible = "linksys,ea9200", "brcm,bcm4709", "brcm,bcm4708";
++ model = "Linksys EA9200";
++
++ chosen {
++ bootargs = "console=ttyS0,115200";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ wps {
++ label = "WPS";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
++ };
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Subject: [PATCH] ARM: dts: BCM5301X: Add basic DT for Linksys EA6300 V1
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's wireless home router based on BCM4708A0 with BCM4360 + BCM43217
+wireless chipsets. LEDs will be hopefully added later to the DT.
+According to some sources it may use the same board as EA6400 and just
+differ by an original vendor firmware.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts | 41 +++++++++++++++++++++++++
+ 2 files changed, 42 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -65,6 +65,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm4708-asus-rt-ac56u.dtb \
+ bcm4708-asus-rt-ac68u.dtb \
+ bcm4708-buffalo-wzr-1750dhp.dtb \
++ bcm4708-linksys-ea6300-v1.dtb \
+ bcm4708-luxul-xap-1510.dtb \
+ bcm4708-luxul-xwc-1000.dtb \
+ bcm4708-netgear-r6250.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
+@@ -0,0 +1,41 @@
++/*
++ * Copyright (C) 2017 Rafał Miłecki <rafal@milecki.pl>
++ *
++ * Licensed under the ISC license.
++ */
++
++/dts-v1/;
++
++#include "bcm4708.dtsi"
++#include "bcm5301x-nand-cs0-bch8.dtsi"
++
++/ {
++ compatible = "linksys,ea6300-v1", "brcm,bcm4708";
++ model = "Linksys EA6300 V1";
++
++ chosen {
++ bootargs = "console=ttyS0,115200";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000>;
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ wps {
++ label = "WPS";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
++ };
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
--- /dev/null
+From 78d759daceaf0a7058f37c4142bdca9948b6d987 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 29 Dec 2016 17:27:55 +0100
+Subject: [PATCH] spi: bcm53xx: set of_node to let DT specify device(s)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Setting of_node of master's dev seems to be a common way of letting it
+work nicely with DT. This allows specifying device there instead of
+hardcoding one in the driver code.
+
+This was successfully tested with commit 1b47b98acce2 ("ARM: BCM5301X:
+Add DT entry for SPI controller and NOR flash")
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ drivers/spi/spi-bcm53xx.c | 8 +-------
+ 1 file changed, 1 insertion(+), 7 deletions(-)
+
+--- a/drivers/spi/spi-bcm53xx.c
++++ b/drivers/spi/spi-bcm53xx.c
+@@ -275,10 +275,6 @@ static int bcm53xxspi_flash_read(struct
+ * BCMA
+ **************************************************/
+
+-static struct spi_board_info bcm53xx_info = {
+- .modalias = "bcm53xxspiflash",
+-};
+-
+ static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = {
+ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS),
+ {},
+@@ -311,6 +307,7 @@ static int bcm53xxspi_bcma_probe(struct
+ b53spi->bspi = true;
+ bcm53xxspi_disable_bspi(b53spi);
+
++ master->dev.of_node = dev->of_node;
+ master->transfer_one = bcm53xxspi_transfer_one;
+ if (b53spi->mmio_base)
+ master->spi_flash_read = bcm53xxspi_flash_read;
+@@ -324,9 +321,6 @@ static int bcm53xxspi_bcma_probe(struct
+ return err;
+ }
+
+- /* Broadcom SoCs (at least with the CC rev 42) use SPI for flash only */
+- spi_new_device(master, &bcm53xx_info);
+-
+ return 0;
+ }
+
--- /dev/null
+From e360e72e715f228e426edf0fc99ffa34027ab0ad Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 29 Dec 2016 20:13:13 +0100
+Subject: [PATCH] spi: bcm53xx: (re)license code to the GPL v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+My intention was to release this code under GPL v2 license. For some
+reason my initial commit 0fc6a323e191 ("spi: bcm53xx: driver for SPI
+controller on Broadcom bcma SoC") totally missed licensing info.
+MODULE_LICENSE was later added by Axel specifying "GNU Public License
+v2 or later".
+
+This patch clarifies situation by adding a proper header (with Copyright
+line) and adjusting MODULE_LICENSE. It should be acked by every driver
+contributor.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Nicholas Mc Guire <hofrat@osadl.org>
+Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
+Acked-by: Jingoo Han <jingoohan1@gmail.com>
+Acked-by: Joe Perches <joe@perches.com>
+Acked-by: Axel Lin <axel.lin@ingics.com>
+Acked-by: Vaishali Thakkar <vaishali.thakkar@oracle.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ drivers/spi/spi-bcm53xx.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+--- a/drivers/spi/spi-bcm53xx.c
++++ b/drivers/spi/spi-bcm53xx.c
+@@ -1,3 +1,11 @@
++/*
++ * Copyright (C) 2014-2016 Rafał Miłecki <rafal@milecki.pl>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+ #include <linux/kernel.h>
+@@ -355,4 +363,4 @@ module_exit(bcm53xxspi_module_exit);
+
+ MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver");
+ MODULE_AUTHOR("Rafał Miłecki <zajec5@gmail.com>");
+-MODULE_LICENSE("GPL");
++MODULE_LICENSE("GPL v2");
--- /dev/null
+--- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
++++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
+@@ -13,6 +13,8 @@
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
++
++ linux,part-probe = "ofpart", "bcm47xxpart";
+ };
+ };
+ };
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sat, 1 Oct 2016 22:54:48 +0200
+Subject: [PATCH] usb: xhci: add support for performing fake doorbell
+
+Broadcom's Northstar XHCI controllers seem to need a special start
+procedure to work correctly. There isn't any official documentation of
+this, the problem is that controller doesn't detect any connected
+devices with default setup. Moreover connecting USB device to controller
+that doesn't run properly can cause SoC's watchdog issues.
+
+A workaround that was successfully tested on multiple devices is to
+perform a fake doorbell. This patch adds code for doing this and enables
+it on BCM4708 family.
+---
+ drivers/usb/host/xhci-plat.c | 6 +++++
+ drivers/usb/host/xhci.c | 63 +++++++++++++++++++++++++++++++++++++++++---
+ drivers/usb/host/xhci.h | 1 +
+ 3 files changed, 67 insertions(+), 3 deletions(-)
+
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -38,12 +38,18 @@ static const struct xhci_driver_override
+
+ static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
+ {
++ struct platform_device *pdev = to_platform_device(dev);
++ struct device_node *node = pdev->dev.of_node;
++
+ /*
+ * As of now platform drivers don't provide MSI support so we ensure
+ * here that the generic code does not try to make a pci_dev from our
+ * dev struct in order to setup MSI
+ */
+ xhci->quirks |= XHCI_PLAT;
++
++ if (node && of_machine_is_compatible("brcm,bcm4708"))
++ xhci->quirks |= XHCI_FAKE_DOORBELL;
+ }
+
+ /* called during probe() after chip reset completes */
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -152,6 +152,49 @@ static int xhci_start(struct xhci_hcd *x
+ return ret;
+ }
+
++/**
++ * xhci_fake_doorbell - Perform a fake doorbell on a specified slot
++ *
++ * Some controllers require a fake doorbell to start correctly. Without that
++ * they simply don't detect any devices.
++ */
++static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id)
++{
++ u32 temp;
++
++ /* Alloc a virt device for that slot */
++ if (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) {
++ xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
++ return -ENOMEM;
++ }
++
++ /* Ring fake doorbell for slot_id ep 0 */
++ xhci_ring_ep_doorbell(xhci, slot_id, 0, 0);
++ usleep_range(1000, 1500);
++
++ /* Read the status to check if HSE is set or not */
++ temp = readl(&xhci->op_regs->status);
++
++ /* Clear HSE if set */
++ if (temp & STS_FATAL) {
++ xhci_dbg(xhci, "HSE problem detected, status: 0x%08x\n", temp);
++ temp &= ~0x1fff;
++ temp |= STS_FATAL;
++ writel(temp, &xhci->op_regs->status);
++ usleep_range(1000, 1500);
++ readl(&xhci->op_regs->status);
++ }
++
++ /* Free virt device */
++ xhci_free_virt_device(xhci, slot_id);
++
++ /* We're done if controller is already running */
++ if (readl(&xhci->op_regs->command) & CMD_RUN)
++ return 0;
++
++ return xhci_start(xhci);
++}
++
+ /*
+ * Reset a halted HC.
+ *
+@@ -568,10 +611,20 @@ int xhci_init(struct usb_hcd *hcd)
+
+ static int xhci_run_finished(struct xhci_hcd *xhci)
+ {
+- if (xhci_start(xhci)) {
+- xhci_halt(xhci);
+- return -ENODEV;
++ int err;
++
++ err = xhci_start(xhci);
++ if (err) {
++ err = -ENODEV;
++ goto err_halt;
++ }
++
++ if (xhci->quirks & XHCI_FAKE_DOORBELL) {
++ err = xhci_fake_doorbell(xhci, 1);
++ if (err)
++ goto err_halt;
+ }
++
+ xhci->shared_hcd->state = HC_STATE_RUNNING;
+ xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
+
+@@ -581,6 +634,10 @@ static int xhci_run_finished(struct xhci
+ xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+ "Finished xhci_run for USB3 roothub");
+ return 0;
++
++err_halt:
++ xhci_halt(xhci);
++ return err;
+ }
+
+ /*
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1635,6 +1635,7 @@ struct xhci_hcd {
+ #define XHCI_BROKEN_STREAMS (1 << 19)
+ #define XHCI_PME_STUCK_QUIRK (1 << 20)
+ #define XHCI_MISSING_CAS (1 << 24)
++#define XHCI_FAKE_DOORBELL (1 << 25)
+ unsigned int num_active_eps;
+ unsigned int limit_active_eps;
+ /* There are two roothubs to keep track of bus suspend info for */
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 24 Sep 2014 22:14:07 +0200
+Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache during decompression
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Broadcom devices have broken CFE (bootloader) that leaves hardware in an
+invalid state. It causes problems with booting Linux. On Northstar
+devices kernel was randomly hanging in ~25% of tries during early init.
+Hangs used to happen at random places in the start_kernel. On BCM53573
+kernel doesn't even seem to start booting.
+
+To workaround this problem we need to do following very early:
+1) Clear 2 following bits in the SCTLR register:
+#define CR_M (1 << 0) /* MMU enable */
+#define CR_C (1 << 2) /* Dcache enable */
+2) Flush the whole D-cache
+3) Disable L2 cache
+
+Unfortunately this patch is not upstreamable as it does above things
+unconditionally. We can't check if we are running on Broadcom platform
+in any safe way and doing such hacks with ARCH_MULTI_V7 is unacceptable
+as it could break other devices support.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/arch/arm/boot/compressed/Makefile
++++ b/arch/arm/boot/compressed/Makefile
+@@ -31,6 +31,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
+ OBJS += ll_char_wr.o font.o
+ endif
+
++ifeq ($(CONFIG_ARCH_BCM_5301X),y)
++OBJS += head-bcm_5301x-mpcore.o
++OBJS += cache-v7-min.o
++endif
++
+ ifeq ($(CONFIG_ARCH_SA1100),y)
+ OBJS += head-sa1100.o
+ endif
+--- /dev/null
++++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
+@@ -0,0 +1,37 @@
++/*
++ *
++ * Platform specific tweaks. This is merged into head.S by the linker.
++ *
++ */
++
++#include <linux/linkage.h>
++#include <asm/assembler.h>
++#include <asm/cp15.h>
++
++ .section ".start", "ax"
++
++/*
++ * This code section is spliced into the head code by the linker
++ */
++
++__plat_uncompress_start:
++
++ @ Preserve r8/r7 i.e. kernel entry values
++ mov r12, r8
++
++ @ Clear MMU enable and Dcache enable bits
++ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
++ bic r0, #CR_C|CR_M
++ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR
++ nop
++
++ @ Call the cache invalidation routine
++ bl v7_flush_dcache_all
++ nop
++ mov r0,#0
++ ldr r3, =0x19022000 @ L2 cache controller, control reg
++ str r0, [r3, #0x100] @ Disable L2 cache
++ nop
++
++ @ Restore
++ mov r8, r12
+--- a/arch/arm/boot/compressed/cache-v7-min.S
++++ b/arch/arm/boot/compressed/cache-v7-min.S
+@@ -12,6 +12,7 @@
+
+ #include <linux/linkage.h>
+ #include <linux/init.h>
++#include <asm/assembler.h>
+
+ __INIT
+
+@@ -63,7 +64,7 @@ loop2:
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
++ mcr p15, 0, r11, c7, c6, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge loop2
+ subs r4, r4, #1 @ decrement the way
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Subject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7900
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm4709-buffalo-wxr-1900dhp.dtb \
+ bcm4709-linksys-ea9200.dtb \
+ bcm4709-netgear-r7000.dtb \
++ bcm4709-netgear-r7900.dtb \
+ bcm4709-netgear-r8000.dtb \
+ bcm4709-tplink-archer-c9-v1.dtb \
+ bcm47094-dlink-dir-885l.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm4709-netgear-r7900.dts
+@@ -0,0 +1,42 @@
++/*
++ * Broadcom BCM470X / BCM5301X ARM platform code.
++ * DTS for Netgear R7900
++ *
++ * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++/dts-v1/;
++
++#include "bcm4709.dtsi"
++#include "bcm5301x-nand-cs0-bch8.dtsi"
++
++/ {
++ compatible = "netgear,r7900", "brcm,bcm4709", "brcm,bcm4708";
++ model = "Netgear R7900";
++
++ chosen {
++ bootargs = "console=ttyS0,115200";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
++ };
++
++ axi@18000000 {
++ usb3@23000 {
++ reg = <0x00023000 0x1000>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
++ };
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Subject: [PATCH] ARM: BCM5301X: Add power button for Buffalo WZR-1750DHP
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+@@ -103,6 +103,12 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
++ power {
++ label = "Power";
++ linux,code = <KEY_POWER>;
++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
++ };
++
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Subject: [PATCH] mtd: spi-nor: detect JEDEC incompatible w25q128 using 0x90
+ command
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Some w25q128 chipsets don't support RDID (0x9f) command, they reply with
+0xff-s only. To suppose such flashes fallback to the 0x90 command.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -875,6 +875,18 @@ static const struct flash_info *spi_nor_
+ }
+ dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
+ id[0], id[1], id[2]);
++
++ tmp = nor->read_reg(nor, 0x90, id, SPI_NOR_MAX_ID_LEN);
++ if (tmp < 0) {
++ dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
++ return ERR_PTR(tmp);
++ }
++ dev_info(nor->dev, "using Read Manufacturer / Device ID command (0x%02x) returned %02x %02x\n",
++ 0x90, id[0x03], id[0x04]);
++ if (id[0x03] == 0xef && id[0x04] == 0x17) {
++ return spi_nor_match_id("w25q128");
++ }
++
+ return ERR_PTR(-ENODEV);
+ }
+
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Subject: [PATCH] mtd: m25p80: use single SPI message for writing data
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On all 3 tested Northstar devices with following flash memories:
+mx25l6405d (8192 Kbytes)
+mx25l12805d (16384 Kbytes)
+mx25l25635e (32768 Kbytes)
+I noticed writing to be broken. Not a single bit was changed leaving all
+bytes set to 0xff.
+
+This is most likely some problem related to the SPI controller or its
+driver. Using a single SPI message seems to workaround this. Of course
+it's not perfect solution as copying whole data into a new buffer makes
+writing slower.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -78,6 +78,7 @@ static ssize_t m25p80_write(struct spi_n
+ {
+ struct m25p *flash = nor->priv;
+ struct spi_device *spi = flash->spi;
++ u8 *command = kzalloc(MAX_CMD_SIZE + len, GFP_KERNEL);
+ struct spi_transfer t[2] = {};
+ struct spi_message m;
+ int cmd_sz = m25p_cmdsz(nor);
+@@ -88,24 +89,26 @@ static ssize_t m25p80_write(struct spi_n
+ if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
+ cmd_sz = 1;
+
+- flash->command[0] = nor->program_opcode;
+- m25p_addr2cmd(nor, to, flash->command);
++ command[0] = nor->program_opcode;
++ m25p_addr2cmd(nor, to, command);
++ memcpy(&command[cmd_sz], buf, len);
+
+- t[0].tx_buf = flash->command;
+- t[0].len = cmd_sz;
++ t[0].tx_buf = command;
++ t[0].len = cmd_sz + len;
+ spi_message_add_tail(&t[0], &m);
+
+- t[1].tx_buf = buf;
+- t[1].len = len;
+- spi_message_add_tail(&t[1], &m);
+-
+ ret = spi_sync(spi, &m);
+- if (ret)
++ if (ret) {
++ kfree(command);
+ return ret;
++ }
+
+ ret = m.actual_length - cmd_sz;
+- if (ret < 0)
++ if (ret < 0) {
++ kfree(command);
+ return -EIO;
++ }
++ kfree(command);
+ return ret;
+ }
+
--- /dev/null
+From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Thu, 16 Oct 2014 20:52:16 +0200
+Subject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+ drivers/mtd/ubi/attach.c | 5 +++++
+ drivers/mtd/ubi/io.c | 4 ++++
+ drivers/mtd/ubi/ubi.h | 1 +
+ 3 files changed, 10 insertions(+)
+
+--- a/drivers/mtd/ubi/attach.c
++++ b/drivers/mtd/ubi/attach.c
+@@ -95,6 +95,9 @@ static int self_check_ai(struct ubi_devi
+ #define AV_ADD BIT(1)
+ #define AV_FIND_OR_ADD (AV_FIND | AV_ADD)
+
++/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */
++bool erase_all_next;
++
+ /**
+ * find_or_add_av - internal function to find a volume, add a volume or do
+ * both (find and add if missing).
+@@ -1592,6 +1595,8 @@ int ubi_attach(struct ubi_device *ubi, i
+ if (!ai)
+ return -ENOMEM;
+
++ erase_all_next = false;
++
+ #ifdef CONFIG_MTD_UBI_FASTMAP
+ /* On small flash devices we disable fastmap in any case. */
+ if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) {
+--- a/drivers/mtd/ubi/io.c
++++ b/drivers/mtd/ubi/io.c
+@@ -759,6 +759,10 @@ int ubi_io_read_ec_hdr(struct ubi_device
+ }
+
+ magic = be32_to_cpu(ec_hdr->magic);
++ if (magic == 0xdeadc0de)
++ erase_all_next = true;
++ if (erase_all_next)
++ return read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF;
+ if (magic != UBI_EC_HDR_MAGIC) {
+ if (mtd_is_eccerr(read_err))
+ return UBI_IO_BAD_HDR_EBADMSG;
+--- a/drivers/mtd/ubi/ubi.h
++++ b/drivers/mtd/ubi/ubi.h
+@@ -823,6 +823,7 @@ extern struct mutex ubi_devices_mutex;
+ extern struct blocking_notifier_head ubi_notifiers;
+
+ /* attach.c */
++extern bool erase_all_next;
+ struct ubi_ainf_peb *ubi_alloc_aeb(struct ubi_attach_info *ai, int pnum,
+ int ec);
+ void ubi_free_aeb(struct ubi_attach_info *ai, struct ubi_ainf_peb *aeb);
--- /dev/null
+From 4abdde3ad6bc0b3b157c4bf6ec0bf139d11d07e8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 13 May 2015 14:13:28 +0200
+Subject: [PATCH] b53: add hacky CPU port fixes for devices not using port 5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+ drivers/net/phy/b53/b53_common.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/net/phy/b53/b53_common.c
++++ b/drivers/net/phy/b53/b53_common.c
+@@ -25,6 +25,7 @@
+ #include <linux/module.h>
+ #include <linux/switch.h>
+ #include <linux/platform_data/b53.h>
++#include <linux/of.h>
+
+ #include "b53_regs.h"
+ #include "b53_priv.h"
+@@ -1383,6 +1384,28 @@ static int b53_switch_init(struct b53_de
+ sw_dev->cpu_port = 5;
+ }
+
++ /* Set correct CPU port */
++ if (of_machine_is_compatible("asus,rt-ac87u"))
++ sw_dev->cpu_port = 7;
++ else if (of_machine_is_compatible("netgear,r7900"))
++ sw_dev->cpu_port = 8;
++ else if (of_machine_is_compatible("netgear,r8000"))
++ sw_dev->cpu_port = 8;
++ else if (of_machine_is_compatible("netgear,r8500"))
++ sw_dev->cpu_port = 8;
++
++ /* Enable extra ports */
++ if (of_machine_is_compatible("tenda,ac9"))
++ dev->enabled_ports |= BIT(5);
++
++ /*
++ * Workaround for devices using port 8 (connected to the 3rd iface).
++ * For some reason it doesn't work (no packets on eth2).
++ */
++ if (of_machine_is_compatible("netgear,r7900") ||
++ of_machine_is_compatible("netgear,r8000"))
++ sw_dev->cpu_port = 5;
++
+ dev->enabled_ports |= BIT(sw_dev->cpu_port);
+ sw_dev->ports = fls(dev->enabled_ports);
+
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Subject: [PATCH] mtd: bcm47xxpart: add device specific workarounds
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/drivers/mtd/bcm47xxpart.c
++++ b/drivers/mtd/bcm47xxpart.c
+@@ -15,6 +15,7 @@
+ #include <linux/slab.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
++#include <linux/of.h>
+
+ #include <uapi/linux/magic.h>
+
+@@ -249,6 +250,28 @@ static int bcm47xxpart_parse(struct mtd_
+ break;
+ }
+
++ /*
++ * Device specific workarounds (hacks). We should use DT to
++ * define partitions but we need a working TRX firmware splitter
++ * first.
++ */
++ if (of_machine_is_compatible("asus,rt-ac87u") && offset == 0x7ec0000) {
++ /*
++ * "asus" partition uses JFFS2 which we don't detect and
++ * we don't want to as this could affect other devices.
++ */
++ bcm47xxpart_add_part(&parts[curr_part++], "asus", offset, MTD_WRITEABLE);
++ continue;
++ } else if (of_machine_is_compatible("tplink,archer-c9-v1") && offset == 0xe40000) {
++ /*
++ * There is a whole set of partitions (not even listed
++ * by original firmware): "default-mac", "pin",
++ * "partition-table", etc.
++ */
++ bcm47xxpart_add_part(&parts[curr_part++], "tplink", offset, MTD_WRITEABLE);
++ continue;
++ }
++
+ /* Read beginning of the block */
+ err = mtd_read(master, offset, BCM47XXPART_BYTES_TO_READ,
+ &bytes_read, (uint8_t *)buf);
--- /dev/null
+From 6f1c62440eb6846cb8045d7a5480ec7bbe47c96f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 15 Aug 2016 10:30:41 +0200
+Subject: [PATCH] BCM53573 minor hacks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/arch/arm/boot/dts/bcm53573.dtsi
++++ b/arch/arm/boot/dts/bcm53573.dtsi
+@@ -44,6 +44,15 @@
+ };
+ };
+
++ timer {
++ compatible = "arm,armv7-timer";
++ interrupts = <GIC_PPI 13 0>,
++ <GIC_PPI 14 0>,
++ <GIC_PPI 11 0>,
++ <GIC_PPI 10 0>;
++ clocks = <&ilp>;
++ };
++
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+--- a/drivers/bcma/main.c
++++ b/drivers/bcma/main.c
+@@ -352,14 +352,6 @@ static int bcma_register_devices(struct
+ }
+ #endif
+
+-#ifdef CONFIG_BCMA_SFLASH
+- if (bus->drv_cc.sflash.present) {
+- err = platform_device_register(&bcma_sflash_dev);
+- if (err)
+- bcma_err(bus, "Error registering serial flash\n");
+- }
+-#endif
+-
+ #ifdef CONFIG_BCMA_NFLASH
+ if (bus->drv_cc.nflash.present) {
+ err = platform_device_register(&bcma_nflash_dev);
+@@ -440,6 +432,14 @@ int bcma_bus_register(struct bcma_bus *b
+ bcma_register_core(bus, core);
+ }
+
++#ifdef CONFIG_BCMA_SFLASH
++ if (bus->drv_cc.sflash.present) {
++ err = platform_device_register(&bcma_sflash_dev);
++ if (err)
++ bcma_err(bus, "Error registering serial flash\n");
++ }
++#endif
++
+ /* Try to get SPROM */
+ err = bcma_sprom_get(bus);
+ if (err == -ENOENT) {
+--- a/drivers/clocksource/arm_arch_timer.c
++++ b/drivers/clocksource/arm_arch_timer.c
+@@ -14,6 +14,7 @@
+ #include <linux/smp.h>
+ #include <linux/cpu.h>
+ #include <linux/cpu_pm.h>
++#include <linux/clk.h>
+ #include <linux/clockchips.h>
+ #include <linux/clocksource.h>
+ #include <linux/interrupt.h>
+@@ -376,6 +377,16 @@ arch_timer_detect_rate(void __iomem *cnt
+ arch_timer_rate = arch_timer_get_cntfrq();
+ }
+
++ /* Get clk rate through clk driver if present */
++ if (!arch_timer_rate) {
++ struct clk *clk = of_clk_get(np, 0);
++
++ if (!IS_ERR(clk)) {
++ if (!clk_prepare_enable(clk))
++ arch_timer_rate = clk_get_rate(clk);
++ }
++ }
++
+ /* Check the timer frequency. */
+ if (arch_timer_rate == 0)
+ pr_warn("Architected timer frequency not available\n");
projects / openwrt / staging / yousong.git / commitdiff