ag71xx: replace delay with sleep calls

I don't see that we're in an atomic context so there's no need to
busy-wait. Therefore replace the delay with sleep calls.
See also Documentation/timers/timers-howto.txt. It states:
"In general, use of mdelay is discouraged and code should
be refactored to allow for the use of msleep."

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43539

diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
index 7f26196f3daa5e0ad4584e497a988696339a0939..8dfff3b6eb837ece11158b03085ca99d44ba794f 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
@@ -445,7 +445,7 @@ static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
                if ((t & mask) == val)
                        return 0;
 
-               msleep(1);
+               usleep_range(1000, 2000);
        }
 
        return -ETIMEDOUT;
@@ -654,7 +654,7 @@ static int ar7240sw_reset(struct ar7240sw *as)
                ar7240sw_disable_port(as, i);
 
        /* Wait for transmit queues to drain. */
-       msleep(2);
+       usleep_range(2000, 3000);
 
        /* Reset the switch. */
        ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,

diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
index 892d5e69e928ef4677998aabc949f14ab3e94492..259cc205cb57c90040a3ca21a7d3d2974236b5d2 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@@ -470,18 +470,18 @@ static void ag71xx_hw_init(struct ag71xx *ag)
                reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
 
                ath79_device_reset_set(reset_phy);
-               mdelay(50);
+               msleep(50);
                ath79_device_reset_clear(reset_phy);
-               mdelay(200);
+               msleep(200);
        }
 
        ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
        udelay(20);
 
        ath79_device_reset_set(reset_mask);
-       mdelay(100);
+       msleep(100);
        ath79_device_reset_clear(reset_mask);
-       mdelay(200);
+       msleep(200);
 
        ag71xx_hw_setup(ag);