From: Birger Koblitz Date: Thu, 21 Jan 2021 14:14:56 +0000 (+0100) Subject: realtek: add switch driver support for the RTL93XX based switches X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fstaging%2Fzorun.git;a=commitdiff_plain;h=27029277f98ddd0006175bdc5beec8b0b150f187 realtek: add switch driver support for the RTL93XX based switches Adds support for the RTL9300 and RTL9310 series of switches with 10GBit per port and up to 56 ports. Signed-off-by: Birger Koblitz --- diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c index a0717e1d9a..e0832c42b8 100644 --- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c @@ -10,29 +10,6 @@ extern struct rtl83xx_soc_info soc_info; -static void rtl83xx_print_matrix(void) -{ - unsigned volatile int *ptr8; - volatile u64 *ptr9; - int i; - - if (soc_info.family == RTL8380_FAMILY_ID) { - ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0); - for (i = 0; i < 28; i += 8) - pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n", - ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3], - ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]); - pr_debug("CPU_PORT> %8x\n", ptr8[28]); - } else { - ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); - for (i = 0; i < 52; i += 4) - pr_debug("> %16llx %16llx %16llx %16llx\n", - ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]); - pr_debug("CPU_PORT> %16llx\n", ptr9[52]); - } - -} - static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv) { mutex_lock(&priv->reg_mutex); @@ -66,10 +43,17 @@ static void rtl83xx_write_cam(int idx, u32 *r) static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid) { - if (priv->family_id == RTL8380_FAMILY_ID) + switch (priv->family_id) { + case RTL8380_FAMILY_ID: return rtl838x_hash(priv, mac << 12 | vid); - else + case RTL8390_FAMILY_ID: return rtl839x_hash(priv, mac << 12 | vid); + case RTL9300_FAMILY_ID: + return rtl930x_hash(priv, ((u64)vid) << 48 | mac); + default: + pr_err("Hash not implemented\n"); + } + return 0; } static void rtl83xx_write_hash(int idx, u32 *r) @@ -101,10 +85,10 @@ static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv) pr_debug("%s: %16llx\n", __func__, v); priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl); - /* PHY update complete */ + /* PHY update complete, there is no global PHY polling enable bit on the 9300 */ if (priv->family_id == RTL8390_FAMILY_ID) sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL); - else + else if(priv->family_id == RTL9300_FAMILY_ID) sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL); } @@ -197,7 +181,10 @@ static int rtl83xx_setup(struct dsa_switch *ds) } priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port)); - rtl83xx_print_matrix(); + if (priv->family_id == RTL8380_FAMILY_ID) + rtl838x_print_matrix(); + else + rtl839x_print_matrix(); rtl83xx_init_stats(priv); @@ -210,6 +197,44 @@ static int rtl83xx_setup(struct dsa_switch *ds) return 0; } +static int rtl930x_setup(struct dsa_switch *ds) +{ + int i; + struct rtl838x_switch_priv *priv = ds->priv; + u32 port_bitmap = BIT(priv->cpu_port); + + pr_info("%s called\n", __func__); + + // Enable CSTI STP mode +// sw_w32(1, RTL930X_ST_CTRL); + + /* Disable MAC polling the PHY so that we can start configuration */ + sw_w32(0, RTL930X_SMI_POLL_CTRL); + + // Disable all ports except CPU port + for (i = 0; i < ds->num_ports; i++) + priv->ports[i].enable = false; + priv->ports[priv->cpu_port].enable = true; + + for (i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) { + priv->r->traffic_set(i, BIT(priv->cpu_port) | BIT(i)); + port_bitmap |= 1ULL << i; + } + } + priv->r->traffic_set(priv->cpu_port, port_bitmap); + + rtl930x_print_matrix(); + + // TODO: Initialize statistics + + ds->configure_vlan_while_not_filtering = true; + + rtl83xx_enable_phy_polling(priv); + + return 0; +} + static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port, unsigned long *supported, struct phylink_link_state *state) @@ -269,13 +294,24 @@ static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port, { struct rtl838x_switch_priv *priv = ds->priv; u64 speed; + u64 link; if (port < 0 || port > priv->cpu_port) return -EINVAL; + /* + * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link + * state needs to be read twice in order to read a correct result. + * This would not be necessary for ports connected e.g. to RTL8218D + * PHYs. + */ state->link = 0; - if (priv->r->get_port_reg_le(priv->r->mac_link_sts) & BIT_ULL(port)) + link = priv->r->get_port_reg_le(priv->r->mac_link_sts); + link = priv->r->get_port_reg_le(priv->r->mac_link_sts); + if (link & BIT_ULL(port)) state->link = 1; + pr_info("%s: link state: %llx\n", __func__, link & BIT_ULL(port)); + state->duplex = 0; if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port)) state->duplex = 1; @@ -317,6 +353,10 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port, pr_debug("%s port %d, mode %x\n", __func__, port, mode); + // BUG: Make this work on RTL93XX + if (priv->family_id >= RTL9300_FAMILY_ID) + return; + if (port == priv->cpu_port) { /* Set Speed, duplex, flow control * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL @@ -422,15 +462,15 @@ static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port, struct rtl838x_switch_priv *priv = ds->priv; const struct rtl83xx_mib_desc *mib; int i; - u64 high; + u64 h; for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) { mib = &rtl83xx_mib[i]; - data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset); + data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset); if (mib->size == 2) { - high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4); - data[i] |= high << 32; + h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset); + data[i] |= h << 32; } } } @@ -447,21 +487,30 @@ static int rtl83xx_port_enable(struct dsa_switch *ds, int port, struct phy_device *phydev) { struct rtl838x_switch_priv *priv = ds->priv; + u64 v; pr_debug("%s: %x %d", __func__, (u32) priv, port); priv->ports[port].enable = true; /* enable inner tagging on egress, do not keep any tags */ - sw_w32(1, priv->r->vlan_port_tag_sts_ctrl(port)); + if (priv->family_id == RTL9310_FAMILY_ID) + sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2)); + else + sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2)); if (dsa_is_cpu_port(ds, port)) return 0; /* add port to switch mask of CPU_PORT */ - priv->r->mask_port_reg_be(0ULL, BIT_ULL(port), priv->r->port_iso_ctrl(priv->cpu_port)); + priv->r->traffic_enable(priv->cpu_port, port); /* add all other ports in the same bridge to switch mask of port */ - priv->r->mask_port_reg_be(0ULL, priv->ports[port].pm, priv->r->port_iso_ctrl(port)); + v = priv->r->traffic_get(port); + v |= priv->ports[port].pm; + priv->r->traffic_set(port, v); + + sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL); + sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL); return 0; } @@ -469,17 +518,21 @@ static int rtl83xx_port_enable(struct dsa_switch *ds, int port, static void rtl83xx_port_disable(struct dsa_switch *ds, int port) { struct rtl838x_switch_priv *priv = ds->priv; + u64 v; pr_debug("%s %x: %d", __func__, (u32)priv, port); /* you can only disable user ports */ if (!dsa_is_user_port(ds, port)) return; + // BUG: This does not work on RTL931X /* remove port from switch mask of CPU_PORT */ - priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->port_iso_ctrl(priv->cpu_port)); + priv->r->traffic_disable(priv->cpu_port, port); /* remove all other ports in the same bridge from switch mask of port */ - priv->r->mask_port_reg_be(priv->ports[port].pm, 0LL, priv->r->port_iso_ctrl(port)); + v = priv->r->traffic_get(port); + v &= ~priv->ports[port].pm; + priv->r->traffic_set(port, v); priv->ports[port].enable = false; } @@ -565,7 +618,7 @@ static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *bridge) { struct rtl838x_switch_priv *priv = ds->priv; - u64 port_bitmap = BIT_ULL(priv->cpu_port); + u64 port_bitmap = 1ULL << priv->cpu_port, v; int i; pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap); @@ -579,20 +632,19 @@ static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port, if (dsa_to_port(ds, i)->bridge_dev != bridge) continue; if (priv->ports[i].enable) - priv->r->mask_port_reg_be(0, BIT_ULL(port), - priv->r->port_iso_ctrl(i)); - priv->ports[i].pm |= BIT_ULL(port); + priv->r->traffic_enable(i, port); - port_bitmap |= BIT_ULL(i); + priv->ports[i].pm |= 1ULL << port; + port_bitmap |= 1ULL << i; } } /* Add all other ports to this port matrix. */ if (priv->ports[port].enable) { - priv->r->mask_port_reg_be(0, BIT_ULL(port), - priv->r->port_iso_ctrl(priv->cpu_port)); - priv->r->mask_port_reg_be(0, port_bitmap, - priv->r->port_iso_ctrl(port)); + priv->r->traffic_enable(priv->cpu_port, port); + v = priv->r->traffic_get(port); + v |= port_bitmap; + priv->r->traffic_set(port, v); } priv->ports[port].pm |= port_bitmap; mutex_unlock(&priv->reg_mutex); @@ -604,7 +656,7 @@ static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *bridge) { struct rtl838x_switch_priv *priv = ds->priv; - u64 port_bitmap = BIT_ULL(priv->cpu_port); + u64 port_bitmap = 1ULL << priv->cpu_port, v; int i; pr_debug("%s %x: %d", __func__, (u32)priv, port); @@ -620,62 +672,53 @@ static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port, if (dsa_to_port(ds, i)->bridge_dev != bridge) continue; if (priv->ports[i].enable) - priv->r->mask_port_reg_be(BIT_ULL(port), 0, - priv->r->port_iso_ctrl(i)); - priv->ports[i].pm &= ~BIT_ULL(port); + priv->r->traffic_disable(i, port); + priv->ports[i].pm |= 1ULL << port; port_bitmap &= ~BIT_ULL(i); } } /* Add all other ports to this port matrix. */ - if (priv->ports[port].enable) - priv->r->mask_port_reg_be(0, port_bitmap, priv->r->port_iso_ctrl(port)); + if (priv->ports[port].enable) { + v = priv->r->traffic_get(port); + v |= port_bitmap; + priv->r->traffic_set(port, v); + } priv->ports[port].pm &= ~port_bitmap; mutex_unlock(&priv->reg_mutex); } -static void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, - u8 state) +void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { - u32 cmd, msti = 0; + u32 msti = 0; u32 port_state[4]; - int index, bit, i; + int index, bit; int pos = port; struct rtl838x_switch_priv *priv = ds->priv; - int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4; + int n = priv->port_width << 1; - pr_debug("%s: port %d state %2x\n", __func__, port, state); - - /* CPU PORT can only be configured on RTL838x */ - if (port >= priv->cpu_port || port > 51) + /* Ports above or equal CPU port can never be configured */ + if (port >= priv->cpu_port) return; mutex_lock(&priv->reg_mutex); - /* For the RTL839x, the bits are left-aligned in the 128 bit field */ + /* For the RTL839x and following, the bits are left-aligned, 838x and 930x + * have 64 bit fields, 839x and 931x have 128 bit fields + */ if (priv->family_id == RTL8390_FAMILY_ID) pos += 12; + if (priv->family_id == RTL9300_FAMILY_ID) + pos += 3; + if (priv->family_id == RTL9310_FAMILY_ID) + pos += 8; index = n - (pos >> 4) - 1; bit = (pos << 1) % 32; - if (priv->family_id == RTL8380_FAMILY_ID) { - cmd = BIT(15) /* Execute cmd */ - | BIT(14) /* Read */ - | 2 << 12 /* Table type 0b10 */ - | (msti & 0xfff); - } else { - cmd = BIT(16) /* Execute cmd */ - | 0 << 15 /* Read */ - | 5 << 12 /* Table type 0b101 */ - | (msti & 0xfff); - } - priv->r->exec_tbl0_cmd(cmd); - - for (i = 0; i < n; i++) - port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); + priv->r->stp_get(priv, msti, port_state); pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3); port_state[index] &= ~(3 << bit); @@ -697,25 +740,12 @@ static void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, break; } - if (priv->family_id == RTL8380_FAMILY_ID) { - cmd = BIT(15) /* Execute cmd */ - | 0 << 14 /* Write */ - | 2 << 12 /* Table type 0b10 */ - | (msti & 0xfff); - } else { - cmd = 1 << 16 /* Execute cmd */ - | BIT(15) /* Write */ - | 5 << 12 /* Table type 0b101 */ - | (msti & 0xfff); - } - for (i = 0; i < n; i++) - sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); - priv->r->exec_tbl0_cmd(cmd); + priv->r->stp_set(priv, msti, port_state); mutex_unlock(&priv->reg_mutex); } -static void rtl83xx_fast_age(struct dsa_switch *ds, int port) +void rtl83xx_fast_age(struct dsa_switch *ds, int port) { struct rtl838x_switch_priv *priv = ds->priv; int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0; @@ -735,7 +765,22 @@ static void rtl83xx_fast_age(struct dsa_switch *ds, int port) */ sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl); - do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s))); + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s)); + + mutex_unlock(&priv->reg_mutex); +} + +void rtl930x_fast_age(struct dsa_switch *ds, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("FAST AGE port %d\n", port); + mutex_lock(&priv->reg_mutex); + sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4); + + sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL); + + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30)); mutex_unlock(&priv->reg_mutex); } @@ -749,17 +794,24 @@ static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port, mutex_lock(&priv->reg_mutex); if (vlan_filtering) { - /* Enable ingress and egress filtering */ + /* Enable ingress and egress filtering + * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define + * the filter action: + * 0: Always Forward + * 1: Drop packet + * 2: Trap packet to CPU port + * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED) + */ if (port != priv->cpu_port) sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1), - priv->r->vlan_port_igr_filter(port)); - sw_w32_mask(0, 1 << (port % 32), priv->r->vlan_port_egr_filter(port)); + priv->r->vlan_port_igr_filter + ((port >> 5) << 2)); + sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 4) << 2)); } else { /* Disable ingress and egress filtering */ if (port != priv->cpu_port) sw_w32_mask(0b11 << ((port % 16) << 1), 0, - priv->r->vlan_port_igr_filter(port)); - sw_w32_mask(1 << (port % 32), 0, priv->r->vlan_port_egr_filter(port)); + priv->r->vlan_port_igr_filter + ((port >> 5) << 2)); + sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 4) << 2)); } /* Do we need to do something to the CPU-Port, too? */ @@ -774,21 +826,23 @@ static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port, struct rtl838x_vlan_info info; struct rtl838x_switch_priv *priv = ds->priv; - pr_debug("%s: port %d\n", __func__, port); + pr_info("%s: port %d\n", __func__, port); mutex_lock(&priv->reg_mutex); - if (priv->family_id == RTL8380_FAMILY_ID) - rtl838x_vlan_profile_dump(0); - else - rtl839x_vlan_profile_dump(0); - - priv->r->vlan_tables_read(0, &info); + priv->r->vlan_profile_dump(1); + priv->r->vlan_tables_read(1, &info); - pr_debug("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n", + pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n", info.tagged_ports, info.untagged_ports, info.profile_id, info.hash_mc_fid, info.hash_uc_fid, info.fid); + priv->r->vlan_set_untagged(1, info.untagged_ports); + pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports); + + priv->r->vlan_set_tagged(1, &info); + pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports); + mutex_unlock(&priv->reg_mutex); return 0; } @@ -796,11 +850,11 @@ static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port, static void rtl83xx_vlan_add(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan) { - struct rtl838x_vlan_info info = {}; + struct rtl838x_vlan_info info; struct rtl838x_switch_priv *priv = ds->priv; int v; - pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__, + pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__, port, vlan->vid_begin, vlan->vid_end, vlan->flags); if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) { @@ -812,12 +866,19 @@ static void rtl83xx_vlan_add(struct dsa_switch *ds, int port, mutex_lock(&priv->reg_mutex); if (vlan->flags & BRIDGE_VLAN_INFO_PVID) { - /* Set both inner and outer PVID of the port */ - sw_w32((vlan->vid_end << 16) | vlan->vid_end << 2, priv->r->vlan_port_pb(port)); - priv->ports[port].pvid = vlan->vid_end; + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + if (!v) + continue; + /* Set both inner and outer PVID of the port */ + sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2)); + priv->ports[port].pvid = vlan->vid_end; + } } for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + if (!v) + continue; + /* Get port memberships of this vlan */ priv->r->vlan_tables_read(v, &info); @@ -838,10 +899,10 @@ static void rtl83xx_vlan_add(struct dsa_switch *ds, int port, info.untagged_ports |= BIT_ULL(port); priv->r->vlan_set_untagged(v, info.untagged_ports); - pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports); + pr_info("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports); priv->r->vlan_set_tagged(v, &info); - pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports); + pr_info("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports); } mutex_unlock(&priv->reg_mutex); @@ -870,7 +931,7 @@ static int rtl83xx_vlan_del(struct dsa_switch *ds, int port, for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { /* Reset to default if removing the current PVID */ if (v == pvid) - sw_w32(0, priv->r->vlan_port_pb(port)); + sw_w32(0, priv->r->vlan_port_pb + (port << 2)); /* Get port memberships of this vlan */ priv->r->vlan_tables_read(v, &info); @@ -962,7 +1023,7 @@ static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port, u64 entry; int idx = -1, err = 0, i; - pr_debug("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key); + pr_debug("In %s, mac %llx, vid: %d, key: %x08x\n", __func__, mac, vid, key); mutex_lock(&priv->reg_mutex); for (i = 0; i < 4; i++) { entry = priv->r->read_l2_entry_using_hash(key, i, &e); @@ -1048,6 +1109,7 @@ static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port, /* We support 4 mirror groups, one destination port per group */ int group; struct rtl838x_switch_priv *priv = ds->priv; + int ctrl_reg, dpm_reg, spm_reg; pr_debug("In %s\n", __func__); @@ -1065,30 +1127,34 @@ static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port, if (group >= 4) return -ENOSPC; + ctrl_reg = priv->r->mir_ctrl + group * 4; + dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width; + spm_reg = priv->r->mir_spm + group * 4 * priv->port_width; + pr_debug("Using group %d\n", group); mutex_lock(&priv->reg_mutex); if (priv->family_id == RTL8380_FAMILY_ID) { /* Enable mirroring to port across VLANs (bit 11) */ - sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group)); + sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg); } else { /* Enable mirroring to destination port */ - sw_w32((mirror->to_local_port << 4) | 1, RTL839X_MIR_CTRL(group)); + sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg); } - if (ingress && (priv->r->get_port_reg_be(priv->r->mir_spm(group)) & (1ULL << port))) { + if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) { mutex_unlock(&priv->reg_mutex); return -EEXIST; } - if ((!ingress) && (priv->r->get_port_reg_be(priv->r->mir_dpm(group)) & (1ULL << port))) { + if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) { mutex_unlock(&priv->reg_mutex); return -EEXIST; } if (ingress) - priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_spm(group)); + priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg); else - priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_dpm(group)); + priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg); priv->mirror_group_ports[group] = mirror->to_local_port; mutex_unlock(&priv->reg_mutex); @@ -1100,6 +1166,7 @@ static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port, { int group = 0; struct rtl838x_switch_priv *priv = ds->priv; + int ctrl_reg, dpm_reg, spm_reg; pr_debug("In %s\n", __func__); for (group = 0; group < 4; group++) { @@ -1109,29 +1176,66 @@ static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port, if (group >= 4) return; + ctrl_reg = priv->r->mir_ctrl + group * 4; + dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width; + spm_reg = priv->r->mir_spm + group * 4 * priv->port_width; + mutex_lock(&priv->reg_mutex); if (mirror->ingress) { /* Ingress, clear source port matrix */ - priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_spm(group)); + priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg); } else { /* Egress, clear destination port matrix */ - priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_dpm(group)); + priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg); } - if (!(sw_r32(priv->r->mir_spm(group)) || sw_r32(priv->r->mir_dpm(group)))) { + if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) { priv->mirror_group_ports[group] = -1; - sw_w32(0, priv->r->mir_ctrl(group)); + sw_w32(0, ctrl_reg); } mutex_unlock(&priv->reg_mutex); } +int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg) +{ + u32 val; + u32 offset = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + if (phy_addr >= 24 && phy_addr <= 27 + && priv->ports[24].phy == PHY_RTL838X_SDS) { + if (phy_addr == 26) + offset = 0x100; + val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff; + return val; + } + + read_phy(phy_addr, 0, phy_reg, &val); + return val; +} + +int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val) +{ + u32 offset = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + if (phy_addr >= 24 && phy_addr <= 27 + && priv->ports[24].phy == PHY_RTL838X_SDS) { + if (phy_addr == 26) + offset = 0x100; + sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)); + return 0; + } + return write_phy(phy_addr, 0, phy_reg, val); +} + const struct dsa_switch_ops rtl83xx_switch_ops = { .get_tag_protocol = rtl83xx_get_tag_protocol, .setup = rtl83xx_setup, - .phy_read = rtl83xx_dsa_phy_read, - .phy_write = rtl83xx_dsa_phy_write, + .phy_read = dsa_phy_read, + .phy_write = dsa_phy_write, .phylink_validate = rtl83xx_phylink_validate, .phylink_mac_link_state = rtl83xx_phylink_mac_link_state, @@ -1168,3 +1272,38 @@ const struct dsa_switch_ops rtl83xx_switch_ops = { .port_mirror_del = rtl83xx_port_mirror_del, }; +const struct dsa_switch_ops rtl930x_switch_ops = { + .get_tag_protocol = rtl83xx_get_tag_protocol, + .setup = rtl930x_setup, + + .phy_read = dsa_phy_read, + .phy_write = dsa_phy_write, + + .phylink_validate = rtl83xx_phylink_validate, + .phylink_mac_link_state = rtl83xx_phylink_mac_link_state, + .phylink_mac_config = rtl83xx_phylink_mac_config, + .phylink_mac_link_down = rtl83xx_phylink_mac_link_down, + .phylink_mac_link_up = rtl83xx_phylink_mac_link_up, + + .get_strings = rtl83xx_get_strings, + .get_ethtool_stats = rtl83xx_get_ethtool_stats, + .get_sset_count = rtl83xx_get_sset_count, + + .port_enable = rtl83xx_port_enable, + .port_disable = rtl83xx_port_disable, + + .set_ageing_time = rtl83xx_set_l2aging, + .port_bridge_join = rtl83xx_port_bridge_join, + .port_bridge_leave = rtl83xx_port_bridge_leave, + .port_stp_state_set = rtl83xx_port_stp_state_set, + .port_fast_age = rtl930x_fast_age, + + .port_vlan_filtering = rtl83xx_vlan_filtering, + .port_vlan_prepare = rtl83xx_vlan_prepare, + .port_vlan_add = rtl83xx_vlan_add, + .port_vlan_del = rtl83xx_vlan_del, + + .port_fdb_add = rtl83xx_port_fdb_add, + .port_fdb_del = rtl83xx_port_fdb_del, + .port_fdb_dump = rtl83xx_port_fdb_dump, +}; diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c index c7b5873e99..de9e83bb8d 100644 --- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c @@ -5,25 +5,17 @@ extern struct mutex smi_lock; - -static inline void rtl838x_mask_port_reg(u64 clear, u64 set, int reg) -{ - sw_w32_mask((u32)clear, (u32)set, reg); -} - -static inline void rtl838x_set_port_reg(u64 set, int reg) -{ - sw_w32(set, reg); -} - -static inline u64 rtl838x_get_port_reg(int reg) +void rtl838x_print_matrix(void) { - return ((u64) sw_r32(reg)); -} + unsigned volatile int *ptr8; + int i; -static inline int rtl838x_stat_port_std_mib(int p) -{ - return RTL838X_STAT_PORT_STD_MIB + (p << 8); + ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0); + for (i = 0; i < 28; i += 8) + pr_info("> %8x %8x %8x %8x %8x %8x %8x %8x\n", + ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3], + ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]); + pr_info("CPU_PORT> %8x\n", ptr8[28]); } static inline int rtl838x_port_iso_ctrl(int p) @@ -122,24 +114,14 @@ static inline int rtl838x_l2_port_new_sa_fwd(int p) return RTL838X_L2_PORT_NEW_SA_FWD(p); } -static inline int rtl838x_mir_ctrl(int group) -{ - return RTL838X_MIR_CTRL(group); -} - -static inline int rtl838x_mir_dpm(int group) -{ - return RTL838X_MIR_DPM_CTRL(group); -} - -static inline int rtl838x_mir_spm(int group) +static inline int rtl838x_mac_link_spd_sts(int p) { - return RTL838X_MIR_SPM_CTRL(group); + return RTL838X_MAC_LINK_SPD_STS(p); } -static inline int rtl838x_mac_link_spd_sts(int p) +inline static int rtl838x_trk_mbr_ctr(int group) { - return RTL838X_MAC_LINK_SPD_STS(p); + return RTL838X_TRK_MBR_CTR + (group << 2); } static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e) @@ -235,14 +217,50 @@ static inline int rtl838x_vlan_port_igr_filter(int port) return RTL838X_VLAN_PORT_IGR_FLTR(port); } -static inline int rtl838x_vlan_port_pb(int port) +static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - return RTL838X_VLAN_PORT_PB_VLAN(port); + int i; + u32 cmd = 1 << 15 /* Execute cmd */ + | 1 << 14 /* Read */ + | 2 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + priv->r->exec_tbl0_cmd(cmd); + + for (i = 0; i < 2; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); } -static inline int rtl838x_vlan_port_tag_sts_ctrl(int port) +static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) { - return RTL838X_VLAN_PORT_TAG_STS_CTRL(port); + int i; + u32 cmd = 1 << 15 /* Execute cmd */ + | 0 << 14 /* Write */ + | 2 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + + for (i = 0; i < 2; i++) + sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); + priv->r->exec_tbl0_cmd(cmd); +} + +u64 rtl838x_traffic_get(int source) +{ + return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source)); +} + +void rtl838x_traffic_set(int source, u64 dest_matrix) +{ + rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source)); +} + +void rtl838x_traffic_enable(int source, int dest) +{ + rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source)); +} + +void rtl838x_traffic_disable(int source, int dest) +{ + rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source)); } const struct rtl838x_reg rtl838x_reg = { @@ -254,8 +272,12 @@ const struct rtl838x_reg rtl838x_reg = { .get_port_reg_le = rtl838x_get_port_reg, .stat_port_rst = RTL838X_STAT_PORT_RST, .stat_rst = RTL838X_STAT_RST, - .stat_port_std_mib = rtl838x_stat_port_std_mib, + .stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB, .port_iso_ctrl = rtl838x_port_iso_ctrl, + .traffic_enable = rtl838x_traffic_enable, + .traffic_disable = rtl838x_traffic_disable, + .traffic_get = rtl838x_traffic_get, + .traffic_set = rtl838x_traffic_set, .l2_ctrl_0 = RTL838X_L2_CTRL_0, .l2_ctrl_1 = RTL838X_L2_CTRL_1, .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT, @@ -272,12 +294,15 @@ const struct rtl838x_reg rtl838x_reg = { .vlan_set_tagged = rtl838x_vlan_set_tagged, .vlan_set_untagged = rtl838x_vlan_set_untagged, .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl, + .vlan_profile_dump = rtl838x_vlan_profile_dump, + .stp_get = rtl838x_stp_get, + .stp_set = rtl838x_stp_set, .mac_port_ctrl = rtl838x_mac_port_ctrl, .l2_port_new_salrn = rtl838x_l2_port_new_salrn, .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd, - .mir_ctrl = rtl838x_mir_ctrl, - .mir_dpm = rtl838x_mir_dpm, - .mir_spm = rtl838x_mir_spm, + .mir_ctrl = RTL838X_MIR_CTRL, + .mir_dpm = RTL838X_MIR_DPM_CTRL, + .mir_spm = RTL838X_MIR_SPM_CTRL, .mac_link_sts = RTL838X_MAC_LINK_STS, .mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS, .mac_link_spd_sts = rtl838x_mac_link_spd_sts, @@ -285,11 +310,13 @@ const struct rtl838x_reg rtl838x_reg = { .mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS, .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash, .read_cam = rtl838x_read_cam, - .vlan_profile = rtl838x_vlan_profile, - .vlan_port_egr_filter = rtl838x_vlan_port_egr_filter, - .vlan_port_igr_filter = rtl838x_vlan_port_igr_filter, - .vlan_port_pb = rtl838x_vlan_port_pb, - .vlan_port_tag_sts_ctrl = rtl838x_vlan_port_tag_sts_ctrl, + .vlan_port_egr_filter = RTL838X_VLAN_PORT_EGR_FLTR, + .vlan_port_igr_filter = RTL838X_VLAN_PORT_IGR_FLTR(0), + .vlan_port_pb = RTL838X_VLAN_PORT_PB_VLAN, + .vlan_port_tag_sts_ctrl = RTL838X_VLAN_PORT_TAG_STS_CTRL, + .trk_mbr_ctr = rtl838x_trk_mbr_ctr, + .rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK, + .spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL, }; irqreturn_t rtl838x_switch_irq(int irq, void *dev_id) @@ -302,7 +329,7 @@ irqreturn_t rtl838x_switch_irq(int irq, void *dev_id) /* Clear status */ sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG); - pr_debug("RTL8380 Link change: status: %x, ports %x\n", status, ports); + pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports); for (i = 0; i < 28; i++) { if (ports & BIT(i)) { @@ -469,8 +496,37 @@ void rtl838x_vlan_profile_dump(int index) profile = sw_r32(RTL838X_VLAN_PROFILE(index)); - pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \ + pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \ IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x", index, profile & 1, (profile >> 1) & 0x1ff, (profile >> 10) & 0x1ff, (profile >> 19) & 0x1ff); } + +void rtl8380_sds_rst(int mac) +{ + u32 offset = (mac == 24) ? 0 : 0x100; + + sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset); + sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset); + sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset); + sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset); + sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset); + pr_debug("SERDES reset: %d\n", mac); +} + +int rtl8380_sds_power(int mac, int val) +{ + u32 mode = (val == 1) ? 0x4 : 0x9; + u32 offset = (mac == 24) ? 5 : 0; + + if ((mac != 24) && (mac != 26)) { + pr_err("%s: not a fibre port: %d\n", __func__, mac); + return -1; + } + + sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL); + + rtl8380_sds_rst(mac); + + return 0; +} diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl930x.c new file mode 100644 index 0000000000..59c283903b --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl930x.c @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include "rtl83xx.h" + +extern struct mutex smi_lock; +extern struct rtl83xx_soc_info soc_info; + +void rtl930x_print_matrix(void) +{ + int i; + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); + + for (i = 0; i < 29; i++) { + rtl_table_read(r, i); + pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0))); + } + rtl_table_release(r); +} + +inline void rtl930x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17)); +} + +inline void rtl930x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17)); +} + +inline int rtl930x_tbl_access_data_0(int i) +{ + return RTL930X_TBL_ACCESS_DATA_0(i); +} + +static inline int rtl930x_l2_port_new_salrn(int p) +{ + return RTL930X_L2_PORT_SALRN(p); +} + +static inline int rtl930x_l2_port_new_sa_fwd(int p) +{ + // TODO: The definition of the fields changed, because of the master-cpu in a stack + return RTL930X_L2_PORT_NEW_SA_FWD(p); +} + +inline static int rtl930x_trk_mbr_ctr(int group) +{ + return RTL930X_TRK_MBR_CTRL + (group << 2); +} + +static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 v, w; + // Read VLAN table (0) via register 0 + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); + + rtl_table_read(r, vlan); + v = sw_r32(rtl_table_data(r, 0)); + w = sw_r32(rtl_table_data(r, 1)); + pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w); + rtl_table_release(r); + + info->tagged_ports = v >> 3; + info->profile_id = (w >> 24) & 7; + info->hash_mc_fid = !!(w & BIT(27)); + info->hash_uc_fid = !!(w & BIT(28)); + info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7); + + // Read UNTAG table via table register 2 + r = rtl_table_get(RTL9300_TBL_2, 0); + rtl_table_read(r, vlan); + v = sw_r32(rtl_table_data(r, 0)); + rtl_table_release(r); + + info->untagged_ports = v >> 3; +} + +static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 v, w; + // Access VLAN table (1) via register 0 + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); + + v = info->tagged_ports << 3; + v |= ((u32)info->fid) >> 3; + + w = ((u32)info->fid) << 29; + w |= info->hash_mc_fid ? BIT(27) : 0; + w |= info->hash_uc_fid ? BIT(28) : 0; + w |= info->profile_id << 24; + + sw_w32(v, rtl_table_data(r, 0)); + sw_w32(w, rtl_table_data(r, 1)); + + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +void rtl930x_vlan_profile_dump(int index) +{ + u32 profile[5]; + + if (index < 0 || index > 7) + return; + + profile[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(index)); + profile[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(index) + 4); + profile[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(index) + 8) & 0x1FFFFFFF; + profile[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(index) + 12) & 0x1FFFFFFF; + profile[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(index) + 16) & 0x1FFFFFFF; + + pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \ + IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x", + index, profile[0] & (3 << 21), profile[2], profile[3], profile[4]); +} + +static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0); + + sw_w32(portmask << 3, rtl_table_data(r, 0)); + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) +{ + int i; + u32 cmd = 1 << 17 /* Execute cmd */ + | 0 << 16 /* Read */ + | 4 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + priv->r->exec_tbl0_cmd(cmd); + + for (i = 0; i < 2; i++) + port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i)); + pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]); +} + +static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) +{ + int i; + u32 cmd = 1 << 17 /* Execute cmd */ + | 1 << 16 /* Write */ + | 4 << 12 /* Table type 4 */ + | (msti & 0xfff); + + for (i = 0; i < 2; i++) + sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i)); + priv->r->exec_tbl0_cmd(cmd); +} + +static inline int rtl930x_mac_force_mode_ctrl(int p) +{ + return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl930x_mac_port_ctrl(int p) +{ + return RTL930X_MAC_L2_PORT_CTRL(p); +} + +static inline int rtl930x_mac_link_spd_sts(int p) +{ + return RTL930X_MAC_LINK_SPD_STS(p); +} + +static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) +{ + e->valid = !!(r[2] & BIT(31)); + if (!e->valid) + return; + + // TODO: Is there not a function to copy directly MAC memory? + e->mac[0] = (r[0] >> 24); + e->mac[1] = (r[0] >> 16); + e->mac[2] = (r[0] >> 8); + e->mac[3] = r[0]; + e->mac[4] = (r[1] >> 24); + e->mac[5] = (r[1] >> 16); + + /* Is it a unicast entry? check multicast bit */ + if (!(e->mac[0] & 1)) { + e->type = L2_UNICAST; + e->is_static = !!(r[2] & BIT(14)); + e->vid = r[2] & 0xfff; + e->rvid = r[1] & 0xfff; + e->port = (r[2] >> 20) & 0x3ff; + // Check for trunk port + if (r[2] & BIT(30)) { + e->stackDev = (e->port >> 9) & 1; + e->trunk = e->port & 0x3f; + } else { + e->stackDev = (e->port >> 6) & 0xf; + e->port = e->port & 0x3f; + } + + e->block_da = !!(r[2] & BIT(15)); + e->block_sa = !!(r[2] & BIT(16)); + e->suspended = !!(r[2] & BIT(13)); + e->next_hop = !!(r[2] & BIT(12)); + e->age = (r[2] >> 17) & 3; + e->valid = true; + + } else { + e->valid = true; + e->type = L2_MULTICAST; + e->mc_portmask_index = (r[2]>>6) & 0xfff; + } +} + +static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e) +{ + u64 entry; + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0); + u32 idx = (0 << 14) | (hash << 2) | position; + int i; + + rtl_table_read(q, idx); + for (i= 0; i < 3; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl930x_fill_l2_entry(r, e); + if (!e->valid) + return 0; + + entry = ((u64)r[0] << 32) | (r[1] & 0xffff0000) | e->vid; + return entry; +} + +static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e) +{ + u64 entry; + u32 r[3]; + struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); + int i; + + rtl_table_read(q, idx); + for (i= 0; i < 3; i++) + r[i] = sw_r32(rtl_table_data(q, i)); + + rtl_table_release(q); + + rtl930x_fill_l2_entry(r, e); + if (!e->valid) + return 0; + + entry = ((u64)r[0] << 32) | (r[1] & 0xffff0000) | e->vid; + + return entry; +} + +u64 rtl930x_traffic_get(int source) +{ + u32 v; + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); + + rtl_table_read(r, source); + v = sw_r32(rtl_table_data(r, 0)); + rtl_table_release(r); + return v >> 3; +} + +/* + * Enable traffic between a source port and a destination port matrix + */ +void rtl930x_traffic_set(int source, u64 dest_matrix) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); + + sw_w32((dest_matrix << 3), rtl_table_data(r, 0)); + rtl_table_write(r, source); + rtl_table_release(r); +} + +void rtl930x_traffic_enable(int source, int dest) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); + rtl_table_read(r, source); + sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0)); + rtl_table_write(r, source); + rtl_table_release(r); +} + +void rtl930x_traffic_disable(int source, int dest) +{ + struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); + rtl_table_read(r, source); + sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0)); + rtl_table_write(r, source); + rtl_table_release(r); +} + +void rtl9300_dump_debug(void) +{ + int i; + u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0; + + for (i = 0; i < 10; i ++) { + pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8, + sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), + sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28)); + r += 32; + } + pr_info("# %08x %08x %08x %08x %08x\n", + sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16)); + rtl930x_print_matrix(); + pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n", + sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL) + + ); +} + +irqreturn_t rtl930x_switch_irq(int irq, void *dev_id) +{ + struct dsa_switch *ds = dev_id; + u32 status = sw_r32(RTL930X_ISR_GLB); + u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG); + u32 link; + int i; + + /* Clear status */ + sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG); + pr_info("RTL9300 Link change: status: %x, ports %x\n", status, ports); + + rtl9300_dump_debug(); + + for (i = 0; i < 28; i++) { + if (ports & BIT(i)) { + /* Read the register twice because of issues with latency at least + * with the external RTL8226 PHY on the XGS1210 */ + link = sw_r32(RTL930X_MAC_LINK_STS); + link = sw_r32(RTL930X_MAC_LINK_STS); + if (link & BIT(i)) + dsa_port_phylink_mac_change(ds, i, true); + else + dsa_port_phylink_mac_change(ds, i, false); + } + } + + return IRQ_HANDLED; +} + +int rtl9300_sds_power(int mac, int val) +{ + int sds_num; + u32 mode; + + // TODO: these numbers are hard-coded for the Zyxel XGS1210 12 Switch + pr_info("SerDes: %s %d\n", __func__, mac); + switch (mac) { + case 24: + sds_num = 6; + mode = 0x12; // HISGMII + break; + case 25: + sds_num = 7; + mode = 0x12; // HISGMII + break; + case 26: + sds_num = 8; + mode = 0x1b; // 10GR/1000BX auto + break; + case 27: + sds_num = 9; + mode = 0x1b; // 10GR/1000BX auto + break; + default: + return -1; + } + if (!val) + mode = 0x1f; // OFF + + rtl9300_sds_rst(sds_num, mode); + + return 0; +} + + +int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + u32 v; + int err = 0; + + pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, val); + + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + val &= 0xffff; + mutex_lock(&smi_lock); + + sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0); + sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); + v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0); + sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); + + do { + v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); + } while (v & 0x1); + + if (v & 0x2) + err = -EIO; + + mutex_unlock(&smi_lock); + + return err; +} + +int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + u32 v; + int err = 0; + +// pr_info("In %s\n", __func__); + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + + sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); + v = reg << 20 | page << 3 | 0x1f << 15 | 1; + sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); + + do { + v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); + } while ( v & 0x1); + + if (v & BIT(25)) { + pr_debug("Error reading phy %d, register %d\n", port, reg); + err = -EIO; + } + *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff); + + pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val); + + mutex_unlock(&smi_lock); + + return err; +} + + +/* + * Write to an mmd register of the PHY + */ +int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) +{ + int err = 0; + u32 v; + + mutex_lock(&smi_lock); + + // Set PHY to access + sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0); + + // Set data to write + sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); + + // Set MMD device number and register to write to + sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3); + + v = BIT(2)| BIT(1)| BIT(0); // WRITE | MMD-access | EXEC + sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); + + do { + v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); + } while ( v & BIT(0)); + + pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err); + mutex_unlock(&smi_lock); + return err; +} + +/* + * Read an mmd register of the PHY + */ +int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) +{ + int err = 0; + u32 v; + + mutex_lock(&smi_lock); + + // Set PHY to access + sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); + + // Set MMD device number and register to write to + sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3); + + v = BIT(1)| BIT(0); // MMD-access | EXEC + sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); + + do { + v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); + } while ( v & 0x1); + // There is no error-checking via BIT 25 of v, as it does not seem to be set correctly + *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff); + pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err); + + mutex_unlock(&smi_lock); + + return err; +} + + +/* + * Calculate both the block 0 and the block 1 hash, and return in + * lower and higher word of the return value since only 12 bit of + * the hash are significant + */ +u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 k0, k1, h1, h2, h; + + k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) + ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) + ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff)); + + h1 = (seed >> 11) & 0x7ff; + h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); + + h2 = (seed >> 33) & 0x7ff; + h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f); + + k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2 + ^ ((seed >> 22) & 0x7ff) ^ h1 + ^ (seed & 0x7ff)); + + // Algorithm choice for block 0 + if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) + h = k1; + else + h = k0; + + /* Algorithm choice for block 1 + * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second + * half of hash-space + * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket + * divided by 2 to divide the hash space in 2 + */ + if (sw_r32(RTL930X_L2_CTRL) & BIT(1)) + h |= (k1 + 2048) << 16; + else + h |= (k0 + 2048) << 16; + + return h; +} + +const struct rtl838x_reg rtl930x_reg = { + .mask_port_reg_be = rtl838x_mask_port_reg, + .set_port_reg_be = rtl838x_set_port_reg, + .get_port_reg_be = rtl838x_get_port_reg, + .mask_port_reg_le = rtl838x_mask_port_reg, + .set_port_reg_le = rtl838x_set_port_reg, + .get_port_reg_le = rtl838x_get_port_reg, + .stat_port_rst = RTL930X_STAT_PORT_RST, + .stat_rst = RTL930X_STAT_RST, + .stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR, + .traffic_enable = rtl930x_traffic_enable, + .traffic_disable = rtl930x_traffic_disable, + .traffic_get = rtl930x_traffic_get, + .traffic_set = rtl930x_traffic_set, + .l2_ctrl_0 = RTL930X_L2_CTRL, + .l2_ctrl_1 = RTL930X_L2_AGE_CTRL, + .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL, + .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, // TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL + .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl930x_tbl_access_data_0, + .isr_glb_src = RTL930X_ISR_GLB, + .isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL930X_IMR_GLB, + .vlan_tables_read = rtl930x_vlan_tables_read, + .vlan_set_tagged = rtl930x_vlan_set_tagged, + .vlan_set_untagged = rtl930x_vlan_set_untagged, + .vlan_profile_dump = rtl930x_vlan_profile_dump, + .stp_get = rtl930x_stp_get, + .stp_set = rtl930x_stp_set, + .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl, + .mac_port_ctrl = rtl930x_mac_port_ctrl, + .l2_port_new_salrn = rtl930x_l2_port_new_salrn, + .l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd, + .mir_ctrl = RTL930X_MIR_CTRL, + .mir_dpm = RTL930X_MIR_DPM_CTRL, + .mir_spm = RTL930X_MIR_SPM_CTRL, + .mac_link_sts = RTL930X_MAC_LINK_STS, + .mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS, + .mac_link_spd_sts = rtl930x_mac_link_spd_sts, + .mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS, + .mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS, + .read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash, + .read_cam = rtl930x_read_cam, + .vlan_port_egr_filter = RTL930X_VLAN_PORT_EGR_FLTR, + .vlan_port_igr_filter = RTL930X_VLAN_PORT_IGR_FLTR(0), + .vlan_port_pb = RTL930X_VLAN_PORT_PB_VLAN, + .vlan_port_tag_sts_ctrl = RTL930X_VLAN_PORT_TAG_STS_CTRL, + .trk_mbr_ctr = rtl930x_trk_mbr_ctr, + .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK, +}; diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl931x.c new file mode 100644 index 0000000000..a33941a0eb --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl931x.c @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include "rtl83xx.h" + +extern struct mutex smi_lock; +extern struct rtl83xx_soc_info soc_info; + +inline void rtl931x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_0) & (1 << 20)); +} + +inline void rtl931x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_1) & (1 << 17)); +} + +inline int rtl931x_tbl_access_data_0(int i) +{ + return RTL931X_TBL_ACCESS_DATA_0(i); +} + +void rtl931x_vlan_profile_dump(int index) +{ + u64 profile[4]; + + if (index < 0 || index > 15) + return; + + profile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index)); + profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32 + | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF); + profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0xFFFFFFFFULL) << 32 + | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0x1FFFFFFULL); + profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 + | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF); + + pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \ + IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx", + index, (u32) (profile[0] & (3 << 14)), profile[1], profile[2], profile[3]); +} + +static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) +{ + int i; + u32 cmd = 1 << 20 /* Execute cmd */ + | 0 << 19 /* Read */ + | 2 << 15 /* Table type 0b10 */ + | (msti & 0x3fff); + priv->r->exec_tbl0_cmd(cmd); + + for (i = 0; i < 4; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); +} + +static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) +{ + int i; + u32 cmd = 1 << 20 /* Execute cmd */ + | 1 << 19 /* Write */ + | 5 << 15 /* Table type 0b101 */ + | (msti & 0x3fff); + for (i = 0; i < 4; i++) + sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); + priv->r->exec_tbl0_cmd(cmd); +} + +inline static int rtl931x_trk_mbr_ctr(int group) +{ + return RTL931X_TRK_MBR_CTRL + (group << 2); +} + +static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 v, w, x, y; + // Read VLAN table (3) via register 0 + struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3); + + rtl_table_read(r, vlan); + v = sw_r32(rtl_table_data(r, 0)); + w = sw_r32(rtl_table_data(r, 1)); + x = sw_r32(rtl_table_data(r, 2)); + y = sw_r32(rtl_table_data(r, 3)); + pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w); + rtl_table_release(r); + + info->tagged_ports = ((u64) v) << 25 | (w >> 7); + info->profile_id = (x >> 16) & 0xf; + info->hash_mc_fid = !!(x & BIT(30)); + info->hash_uc_fid = !!(x & BIT(31)); + info->fid = w & 0x7f; + // TODO: use also info in 4th register + + // Read UNTAG table via table register 3 + r = rtl_table_get(RTL9310_TBL_3, 0); + rtl_table_read(r, vlan); + v = ((u64)sw_r32(rtl_table_data(r, 0))) << 25; + v |= sw_r32(rtl_table_data(r, 1)) >> 7; + rtl_table_release(r); + + info->untagged_ports = v; +} + +static void rtl931x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 v, w, x; + // Access VLAN table (1) via register 0 + struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3); + + v = info->tagged_ports << 7; + w = (info->tagged_ports & 0x7f000000) << 25; + w |= (u32)info->fid; + x = info->profile_id << 16; + w |= info->hash_mc_fid ? BIT(30) : 0; + w |= info->hash_uc_fid ? BIT(31) : 0; + // TODO: use also info in 4th register + + sw_w32(v, rtl_table_data(r, 0)); + sw_w32(w, rtl_table_data(r, 1)); + sw_w32(x, rtl_table_data(r, 2)); + + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +static void rtl931x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + struct table_reg *r = rtl_table_get(RTL9310_TBL_3, 0); + + rtl839x_set_port_reg_be(portmask << 7, rtl_table_data(r, 0)); + rtl_table_write(r, vlan); + rtl_table_release(r); +} + +static inline int rtl931x_mac_force_mode_ctrl(int p) +{ + return RTL931X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl931x_mac_link_spd_sts(int p) +{ + return RTL931X_MAC_LINK_SPD_STS(p); +} + +static inline int rtl931x_mac_port_ctrl(int p) +{ + return RTL931X_MAC_PORT_CTRL(p); +} + +static inline int rtl931x_l2_port_new_salrn(int p) +{ + return RTL931X_L2_PORT_NEW_SALRN(p); +} + +static inline int rtl931x_l2_port_new_sa_fwd(int p) +{ + return RTL931X_L2_PORT_NEW_SA_FWD(p); +} + +static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e) +{ + u64 entry = 0; + + // TODO: Implement + return entry; +} + +static u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e) +{ + u64 entry = 0; + + // TODO: Implement + return entry; +} +irqreturn_t rtl931x_switch_irq(int irq, void *dev_id) +{ + struct dsa_switch *ds = dev_id; + u32 status = sw_r32(RTL931X_ISR_GLB_SRC); + u64 ports = rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG); + u64 link; + int i; + + /* Clear status */ + rtl839x_set_port_reg_le(ports, RTL931X_ISR_PORT_LINK_STS_CHG); + pr_info("RTL9310 Link change: status: %x, ports %llx\n", status, ports); + + for (i = 0; i < 56; i++) { + if (ports & BIT_ULL(i)) { + link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS); + if (link & BIT_ULL(i)) + dsa_port_phylink_mac_change(ds, i, true); + else + dsa_port_phylink_mac_change(ds, i, false); + } + } + return IRQ_HANDLED; +} + + +int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + u32 v; + int err = 0; + + val &= 0xffff; + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + /* Clear both port registers */ + sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2); + sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4); + sw_w32_mask(0, BIT(port), RTL931X_SMI_INDRT_ACCESS_CTRL_2+ (port % 32) * 4); + + sw_w32_mask(0xffff0000, val << 16, RTL931X_SMI_INDRT_ACCESS_CTRL_3); + + v = reg << 6 | page << 11 ; + sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); + + sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1); + + v |= 1 << 3 | 1; /* Write operation and execute */ + sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); + + do { + } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1); + + if (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x2) + err = -EIO; + + mutex_unlock(&smi_lock); + return err; +} + +int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + u32 v; + + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + + sw_w32_mask(0xffff, port, RTL931X_SMI_INDRT_ACCESS_CTRL_3); + v = reg << 6 | page << 11; // TODO: ACCESS Offset? Park page + sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); + + sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1); + + v |= 1; + sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); + + do { + } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1); + + *val = (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) & 0xffff0000) >> 16; + + pr_info("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val); + + mutex_unlock(&smi_lock); + return 0; +} + +void rtl931x_print_matrix(void) +{ + volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); + int i; + + for (i = 0; i < 52; i += 4) + pr_info("> %16llx %16llx %16llx %16llx\n", + ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]); + pr_info("CPU_PORT> %16llx\n", ptr[52]); +} + +const struct rtl838x_reg rtl931x_reg = { + .mask_port_reg_be = rtl839x_mask_port_reg_be, + .set_port_reg_be = rtl839x_set_port_reg_be, + .get_port_reg_be = rtl839x_get_port_reg_be, + .mask_port_reg_le = rtl839x_mask_port_reg_le, + .set_port_reg_le = rtl839x_set_port_reg_le, + .get_port_reg_le = rtl839x_get_port_reg_le, + .stat_port_rst = RTL931X_STAT_PORT_RST, + .stat_rst = RTL931X_STAT_RST, + .stat_port_std_mib = 0, // Not defined + .l2_ctrl_0 = RTL931X_L2_CTRL, + .l2_ctrl_1 = RTL931X_L2_AGE_CTRL, + .l2_port_aging_out = RTL931X_L2_PORT_AGE_CTRL, + // .smi_poll_ctrl does not exist + .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl931x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl931x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl931x_tbl_access_data_0, + .isr_glb_src = RTL931X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL931X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL931X_IMR_PORT_LINK_STS_CHG, + // imr_glb does not exist on RTL931X + .vlan_tables_read = rtl931x_vlan_tables_read, + .vlan_set_tagged = rtl931x_vlan_set_tagged, + .vlan_set_untagged = rtl931x_vlan_set_untagged, + .vlan_profile_dump = rtl931x_vlan_profile_dump, + .stp_get = rtl931x_stp_get, + .stp_set = rtl931x_stp_set, + .mac_force_mode_ctrl = rtl931x_mac_force_mode_ctrl, + .mac_port_ctrl = rtl931x_mac_port_ctrl, + .l2_port_new_salrn = rtl931x_l2_port_new_salrn, + .l2_port_new_sa_fwd = rtl931x_l2_port_new_sa_fwd, + .mir_ctrl = RTL931X_MIR_CTRL, + .mir_dpm = RTL931X_MIR_DPM_CTRL, + .mir_spm = RTL931X_MIR_SPM_CTRL, + .mac_link_sts = RTL931X_MAC_LINK_STS, + .mac_link_dup_sts = RTL931X_MAC_LINK_DUP_STS, + .mac_link_spd_sts = rtl931x_mac_link_spd_sts, + .mac_rx_pause_sts = RTL931X_MAC_RX_PAUSE_STS, + .mac_tx_pause_sts = RTL931X_MAC_TX_PAUSE_STS, + .read_l2_entry_using_hash = rtl931x_read_l2_entry_using_hash, + .read_cam = rtl931x_read_cam, + .vlan_port_egr_filter = RTL931X_VLAN_PORT_EGR_FLTR(0), + .vlan_port_igr_filter = RTL931X_VLAN_PORT_IGR_FLTR(0), +// .vlan_port_pb = does not exist + .vlan_port_tag_sts_ctrl = RTL931X_VLAN_PORT_TAG_CTRL, + .trk_mbr_ctr = rtl931x_trk_mbr_ctr, +}; + diff --git a/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h index 4366e6b64f..d7b4317cbb 100644 --- a/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h +++ b/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h @@ -7,37 +7,85 @@ * Register definition */ -#define RTL838X_CPU_PORT 28 -#define RTL839X_CPU_PORT 52 - +/* Per port MAC control */ #define RTL838X_MAC_PORT_CTRL (0xd560) #define RTL839X_MAC_PORT_CTRL (0x8004) +#define RTL930X_MAC_L2_PORT_CTRL (0x3268) +#define RTL930X_MAC_PORT_CTRL (0x3260) +#define RTL931X_MAC_L2_PORT_CTRL (0x6000) +#define RTL931X_MAC_PORT_CTRL (0x6004) + +/* DMA interrupt control and status registers */ +#define RTL838X_DMA_IF_CTRL (0x9f58) #define RTL838X_DMA_IF_INTR_STS (0x9f54) -#define RTL839X_DMA_IF_INTR_STS (0x7868) #define RTL838X_DMA_IF_INTR_MSK (0x9f50) -#define RTL839X_DMA_IF_INTR_MSK (0x7864) -#define RTL838X_DMA_IF_CTRL (0x9f58) + #define RTL839X_DMA_IF_CTRL (0x786c) -#define RTL838X_RST_GLB_CTRL_0 (0x003c) +#define RTL839X_DMA_IF_INTR_STS (0x7868) +#define RTL839X_DMA_IF_INTR_MSK (0x7864) + +#define RTL930X_DMA_IF_CTRL (0xe028) +#define RTL930X_DMA_IF_INTR_RX_RUNOUT_STS (0xe01C) +#define RTL930X_DMA_IF_INTR_RX_DONE_STS (0xe020) +#define RTL930X_DMA_IF_INTR_TX_DONE_STS (0xe024) +#define RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK (0xe010) +#define RTL930X_DMA_IF_INTR_RX_DONE_MSK (0xe014) +#define RTL930X_DMA_IF_INTR_TX_DONE_MSK (0xe018) +#define RTL930X_L2_NTFY_IF_INTR_MSK (0xe04C) +#define RTL930X_L2_NTFY_IF_INTR_STS (0xe050) + +/* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */ +#define RTL931X_DMA_IF_CTRL (0x0928) +#define RTL931X_DMA_IF_INTR_RX_RUNOUT_STS (0x091c) +#define RTL931X_DMA_IF_INTR_RX_DONE_STS (0x0920) +#define RTL931X_DMA_IF_INTR_TX_DONE_STS (0x0924) +#define RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK (0x0910) +#define RTL931X_DMA_IF_INTR_RX_DONE_MSK (0x0914) +#define RTL931X_DMA_IF_INTR_TX_DONE_MSK (0x0918) +#define RTL931X_L2_NTFY_IF_INTR_MSK (0x09E4) +#define RTL931X_L2_NTFY_IF_INTR_STS (0x09E8) + #define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) #define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) +#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) +#define RTL931X_MAC_FORCE_MODE_CTRL (0x0ddc) /* MAC address settings */ #define RTL838X_MAC (0xa9ec) #define RTL839X_MAC (0x02b4) #define RTL838X_MAC_ALE (0x6b04) #define RTL838X_MAC2 (0xa320) +#define RTL930X_MAC_L2_ADDR_CTRL (0xC714) +#define RTL931X_MAC_L2_ADDR_CTRL (0x135c) +/* Ringbuffer setup */ #define RTL838X_DMA_RX_BASE (0x9f00) #define RTL839X_DMA_RX_BASE (0x780c) +#define RTL930X_DMA_RX_BASE (0xdf00) +#define RTL931X_DMA_RX_BASE (0x0800) + #define RTL838X_DMA_TX_BASE (0x9f40) #define RTL839X_DMA_TX_BASE (0x784c) +#define RTL930X_DMA_TX_BASE (0xe000) +#define RTL931X_DMA_TX_BASE (0x0900) + #define RTL838X_DMA_IF_RX_RING_SIZE (0xB7E4) #define RTL839X_DMA_IF_RX_RING_SIZE (0x6038) +#define RTL930X_DMA_IF_RX_RING_SIZE (0x7C60) +#define RTL931X_DMA_IF_RX_RING_SIZE (0x2080) + #define RTL838X_DMA_IF_RX_RING_CNTR (0xB7E8) #define RTL839X_DMA_IF_RX_RING_CNTR (0x603c) +#define RTL930X_DMA_IF_RX_RING_CNTR (0x7C8C) +#define RTL931X_DMA_IF_RX_RING_CNTR (0x20AC) + #define RTL838X_DMA_IF_RX_CUR (0x9F20) #define RTL839X_DMA_IF_RX_CUR (0x782c) +#define RTL930X_DMA_IF_RX_CUR (0xdf80) +#define RTL931X_DMA_IF_RX_CUR (0x0880) + +#define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0x9F48) +#define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0xE008) #define RTL838X_DMY_REG31 (0x3b28) #define RTL838X_SDS_MODE_SEL (0x0028) @@ -47,50 +95,56 @@ #define RTL838X_SDS4_REG28 (0xef80) #define RTL838X_SDS4_DUMMY0 (0xef8c) #define RTL838X_SDS5_EXT_REG6 (0xf18c) -#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) -#define RTL838X_STAT_PORT_STD_MIB(port) (0x1200 + (((port) << 8))) -#define RTL838X_STAT_RST (0x3100) -#define RTL838X_STAT_CTRL (0x3108) -/* Registers of the internal Serdes of the 8380 */ -#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28 -#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100) -#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0 -#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100) -#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880) -#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980) - -/* VLAN registers */ -#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) -#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) -#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2)) -#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C) -#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4) -#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) -#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) -#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) -#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) +/* L2 features */ #define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) #define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) -/* MAC handling */ +#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) +#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) + +/* MAC-side link state handling */ #define RTL838X_MAC_LINK_STS (0xa188) #define RTL839X_MAC_LINK_STS (0x0390) +#define RTL930X_MAC_LINK_STS (0xCB10) +#define RTL931X_MAC_LINK_STS (0x0ec0) + #define RTL838X_MAC_LINK_SPD_STS (0xa190) #define RTL839X_MAC_LINK_SPD_STS (0x03a0) +#define RTL930X_MAC_LINK_SPD_STS (0xCB18) +#define RTL931X_MAC_LINK_SPD_STS (0x0ed0) + #define RTL838X_MAC_LINK_DUP_STS (0xa19c) #define RTL839X_MAC_LINK_DUP_STS (0x03b0) +#define RTL930X_MAC_LINK_DUP_STS (0xCB28) +#define RTL931X_MAC_LINK_DUP_STS (0x0ef0) + // TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ??? + #define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) #define RTL839X_MAC_TX_PAUSE_STS (0x03b8) +#define RTL930X_MAC_TX_PAUSE_STS (0xCB2C) +#define RTL931X_MAC_TX_PAUSE_STS (0x0ef8) + #define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) -#define RTL839X_MAC_RX_PAUSE_STS (0x03c0) +#define RTL839X_MAC_RX_PAUSE_STS (0xCB30) +#define RTL930X_MAC_RX_PAUSE_STS (0xC2F8) +#define RTL931X_MAC_RX_PAUSE_STS (0x0f00) + #define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) #define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) + +#define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064) + #define RTL839X_MAC_GLB_CTRL (0x02a8) #define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60f8) #define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) #define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) +#define RTL930X_L2_TBL_FLUSH_CTRL (0x9404) +#define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C) + +#define RTL930X_L2_PORT_SABLK_CTRL (0x905c) +#define RTL930X_L2_PORT_DABLK_CTRL (0x9060) /* MAC link state bits */ #define FORCE_EN (1 << 0) @@ -100,25 +154,48 @@ #define TX_PAUSE_EN (1 << 6) #define RX_PAUSE_EN (1 << 7) -/* RTL839X L2 Notification DMA interface */ +/* L2 Notification DMA interface */ #define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL (0x785C) #define RTL839X_L2_NOTIFICATION_CTRL (0x7808) +#define RTL931X_L2_NTFY_RING_BASE_ADDR (0x09DC) +#define RTL931X_L2_NTFY_RING_CUR_ADDR (0x09E0) +#define RTL839X_L2_NOTIFICATION_CTRL (0x7808) +#define RTL931X_L2_NTFY_CTRL (0xCDC8) #define RTL838X_L2_CTRL_0 (0x3200) #define RTL839X_L2_CTRL_0 (0x3800) +#define RTL930X_L2_CTRL (0x8FD8) +#define RTL931X_L2_CTRL (0xC800) /* TRAPPING to CPU-PORT */ #define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984) -#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058) #define RTL838X_RMA_CTRL_0 (0x4300) #define RTL838X_RMA_CTRL_1 (0x4304) #define RTL839X_RMA_CTRL_0 (0x1200) + +#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058) #define RTL839X_RMA_CTRL_1 (0x1204) #define RTL839X_RMA_CTRL_2 (0x1208) #define RTL839X_RMA_CTRL_3 (0x120C) +#define RTL930X_RMA_CTRL_0 (0x9E60) +#define RTL930X_RMA_CTRL_1 (0x9E64) +#define RTL930X_RMA_CTRL_2 (0x9E68) + +#define RTL931X_RMA_CTRL_0 (0x8800) +#define RTL931X_RMA_CTRL_1 (0x8804) +#define RTL931X_RMA_CTRL_2 (0x8808) + +/* Advanced SMI control for clause 45 PHYs */ +#define RTL930X_SMI_MAC_TYPE_CTRL (0xCA04) +#define RTL930X_SMI_PORT24_27_ADDR_CTRL (0xCB90) +#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08) +#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C) + /* Registers of the internal Serdes of the 8390 */ #define RTL839X_SDS12_13_XSG0 (0xB800) +/* Registers of the internal Serdes of the 8380 */ +#define RTL838X_SDS4_FIB_REG0 (0xF800) inline int rtl838x_mac_port_ctrl(int p) { @@ -130,44 +207,39 @@ inline int rtl839x_mac_port_ctrl(int p) return RTL839X_MAC_PORT_CTRL + (p << 7); } -static inline int rtl838x_mac_force_mode_ctrl(int p) -{ - return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2); -} - -static inline int rtl839x_mac_force_mode_ctrl(int p) -{ - return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2); -} +/* On the RTL931XX, the functionality of the MAC port control register is split up + * into RTL931X_MAC_L2_PORT_CTRL and RTL931X_MAC_PORT_CTRL the functionality used + * by the Ethernet driver is in the same bits now in RTL931X_MAC_L2_PORT_CTRL + */ -inline int rtl838x_dma_rx_base(int i) +inline int rtl930x_mac_port_ctrl(int p) { - return RTL838X_DMA_RX_BASE + (i << 2); + return RTL930X_MAC_L2_PORT_CTRL + (p << 6); } -inline int rtl839x_dma_rx_base(int i) +inline int rtl931x_mac_port_ctrl(int p) { - return RTL839X_DMA_RX_BASE + (i << 2); + return RTL931X_MAC_L2_PORT_CTRL + (p << 7); } -inline int rtl838x_dma_tx_base(int i) +inline int rtl838x_dma_if_rx_ring_size(int i) { - return RTL838X_DMA_TX_BASE + (i << 2); + return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); } -inline int rtl839x_dma_tx_base(int i) +inline int rtl839x_dma_if_rx_ring_size(int i) { - return RTL839X_DMA_TX_BASE + (i << 2); + return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); } -inline int rtl838x_dma_if_rx_ring_size(int i) +inline int rtl930x_dma_if_rx_ring_size(int i) { - return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); + return RTL930X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2); } -inline int rtl839x_dma_if_rx_ring_size(int i) +inline int rtl931x_dma_if_rx_ring_size(int i) { - return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); + return RTL931X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2); } inline int rtl838x_dma_if_rx_ring_cntr(int i) @@ -180,35 +252,54 @@ inline int rtl839x_dma_if_rx_ring_cntr(int i) return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2); } - -inline int rtl838x_dma_if_rx_cur(int i) +inline int rtl930x_dma_if_rx_ring_cntr(int i) { - return RTL838X_DMA_IF_RX_CUR + (i << 2); + return RTL930X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2); } -inline int rtl839x_dma_if_rx_cur(int i) +inline int rtl931x_dma_if_rx_ring_cntr(int i) { - return RTL839X_DMA_IF_RX_CUR + (i << 2); + return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2); } inline u32 rtl838x_get_mac_link_sts(int port) { - return (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port)); + return (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port)); } inline u32 rtl839x_get_mac_link_sts(int p) { - return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & (1 << p)); + return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32)); +} + +inline u32 rtl930x_get_mac_link_sts(int port) +{ + return (sw_r32(RTL930X_MAC_LINK_STS) & BIT(port)); +} + +inline u32 rtl931x_get_mac_link_sts(int p) +{ + return (sw_r32(RTL931X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32)); } inline u32 rtl838x_get_mac_link_dup_sts(int port) { - return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port)); + return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port)); } inline u32 rtl839x_get_mac_link_dup_sts(int p) { - return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & (1 << p)); + return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32)); +} + +inline u32 rtl930x_get_mac_link_dup_sts(int port) +{ + return (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port)); +} + +inline u32 rtl931x_get_mac_link_dup_sts(int p) +{ + return (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32)); } inline u32 rtl838x_get_mac_link_spd_sts(int port) @@ -229,6 +320,25 @@ inline u32 rtl839x_get_mac_link_spd_sts(int port) return (speed & 0x3); } + +inline u32 rtl930x_get_mac_link_spd_sts(int port) +{ + int r = RTL930X_MAC_LINK_SPD_STS + ((port / 10) << 2); + u32 speed = sw_r32(r); + + speed >>= (port % 10) * 3; + return (speed & 0x7); +} + +inline u32 rtl931x_get_mac_link_spd_sts(int port) +{ + int r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2); + u32 speed = sw_r32(r); + + speed >>= (port % 8) << 2; + return (speed & 0xf); +} + inline u32 rtl838x_get_mac_rx_pause_sts(int port) { return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port)); @@ -236,7 +346,17 @@ inline u32 rtl838x_get_mac_rx_pause_sts(int port) inline u32 rtl839x_get_mac_rx_pause_sts(int p) { - return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p)); + return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); +} + +inline u32 rtl930x_get_mac_rx_pause_sts(int port) +{ + return (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port)); +} + +inline u32 rtl931x_get_mac_rx_pause_sts(int p) +{ + return (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); } inline u32 rtl838x_get_mac_tx_pause_sts(int port) @@ -246,21 +366,42 @@ inline u32 rtl838x_get_mac_tx_pause_sts(int port) inline u32 rtl839x_get_mac_tx_pause_sts(int p) { - return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p)); + return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); +} + +inline u32 rtl930x_get_mac_tx_pause_sts(int port) +{ + return (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port)); +} + +inline u32 rtl931x_get_mac_tx_pause_sts(int p) +{ + return (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); } +struct p_hdr; +struct dsa_tag; struct rtl838x_reg { + irqreturn_t (*net_irq)(int irq, void *dev_id); int (*mac_port_ctrl)(int port); int dma_if_intr_sts; int dma_if_intr_msk; + int dma_if_intr_rx_runout_sts; + int dma_if_intr_rx_done_sts; + int dma_if_intr_tx_done_sts; + int dma_if_intr_rx_runout_msk; + int dma_if_intr_rx_done_msk; + int dma_if_intr_tx_done_msk; + int l2_ntfy_if_intr_sts; + int l2_ntfy_if_intr_msk; int dma_if_ctrl; - int (*mac_force_mode_ctrl)(int port); - int (*dma_rx_base)(int ring); - int (*dma_tx_base)(int ring); - int (*dma_if_rx_ring_size)(int ring); - int (*dma_if_rx_ring_cntr)(int ring); - int (*dma_if_rx_cur)(int ring); + int mac_force_mode_ctrl; + int dma_rx_base; + int dma_tx_base; + int (*dma_if_rx_ring_size)(int ring); + int (*dma_if_rx_ring_cntr)(int ring); + int dma_if_rx_cur; int rst_glb_ctrl; u32 (*get_mac_link_sts)(int port); u32 (*get_mac_link_dup_sts)(int port); @@ -269,11 +410,19 @@ struct rtl838x_reg { u32 (*get_mac_tx_pause_sts)(int port); int mac; int l2_tbl_flush_ctrl; + void (*update_cntr)(int r, int work_done); + void (*create_tx_header)(struct p_hdr *h, int dest_port, int prio); + bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag); }; int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val); int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val); int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val); int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val); +int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val); +int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +void rtl9300_sds_power(int sds_num, int val); #endif /* _RTL838X_ETH_H */