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add another wrapper (like g++-uc) to link against both uClibc++ and libstdc++, remove...
[openwrt/svn-archive/archive.git] / XOrg / server / xorg-kdrive-X11R7.2 / patches / w100.patch
1 Index: git/hw/kdrive/w100/ati.c
2 ===================================================================
3 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4 +++ git/hw/kdrive/w100/ati.c 2006-09-02 12:12:14.000000000 +0200
5 @@ -0,0 +1,434 @@
6 +/*
7 + * Copyright © 2006 Alberto Mardegan <mardy@users.sourceforge.net>
8 + *
9 + * Permission to use, copy, modify, distribute, and sell this software and its
10 + * documentation for any purpose is hereby granted without fee, provided that
11 + * the above copyright notice appear in all copies and that both that
12 + * copyright notice and this permission notice appear in supporting
13 + * documentation, and that the name of Alberto Mardegan not be used in
14 + * advertising or publicity pertaining to distribution of the software without
15 + * specific, written prior permission. Alberto Mardegan makes no
16 + * representations about the suitability of this software for any purpose. It
17 + * is provided "as is" without express or implied warranty.
18 + *
19 + * ALBERTO MARDEGAN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
20 + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
21 + * EVENT SHALL ALBERTO MARDEGAN BE LIABLE FOR ANY SPECIAL, INDIRECT OR
22 + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
23 + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
24 + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
25 + * PERFORMANCE OF THIS SOFTWARE.
26 + */
27 +
28 +#ifdef HAVE_CONFIG_H
29 +#include <kdrive-config.h>
30 +#endif
31 +#include "ati.h"
32 +#include "w100_regs.h"
33 +
34 +
35 +struct pci_id_entry ati_pci_ids[] = {
36 + {0x1002, 0x5644, 0, "ATI Imageon 3200"},
37 + {0x1002, 0x5741, 0, "ATI Imageon 100"},
38 + {0x1002, 0x5744, 0, "ATI Imageon 3220"},
39 + {0, 0, 0, NULL}
40 +};
41 +
42 +
43 +static Bool
44 +ATICardInit(KdCardInfo * card)
45 +{
46 + ATICardInfo *atic;
47 + int i;
48 + Bool initialized = FALSE;
49 +
50 + atic = xcalloc(sizeof(ATICardInfo), 1);
51 + if (atic == NULL)
52 + return FALSE;
53 +
54 +#ifdef KDRIVEFBDEV
55 + if (!initialized && fbdevInitialize(card, &atic->backend_priv.fbdev)) {
56 + atic->use_fbdev = TRUE;
57 + initialized = TRUE;
58 + atic->backend_funcs.cardfini = fbdevCardFini;
59 + atic->backend_funcs.scrfini = fbdevScreenFini;
60 + atic->backend_funcs.initScreen = fbdevInitScreen;
61 + atic->backend_funcs.finishInitScreen = fbdevFinishInitScreen;
62 + atic->backend_funcs.createRes = fbdevCreateResources;
63 + atic->backend_funcs.preserve = fbdevPreserve;
64 + atic->backend_funcs.restore = fbdevRestore;
65 + atic->backend_funcs.dpms = fbdevDPMS;
66 + atic->backend_funcs.enable = fbdevEnable;
67 + atic->backend_funcs.disable = fbdevDisable;
68 + atic->backend_funcs.getColors = fbdevGetColors;
69 + atic->backend_funcs.putColors = fbdevPutColors;
70 +#ifdef RANDR
71 + atic->backend_funcs.randrSetConfig = fbdevRandRSetConfig;
72 +#endif
73 + }
74 +#endif
75 +#ifdef KDRIVEVESA
76 + if (!initialized && vesaInitialize(card, &atic->backend_priv.vesa)) {
77 + atic->use_vesa = TRUE;
78 + initialized = TRUE;
79 + atic->backend_funcs.cardfini = vesaCardFini;
80 + atic->backend_funcs.scrfini = vesaScreenFini;
81 + atic->backend_funcs.initScreen = vesaInitScreen;
82 + atic->backend_funcs.finishInitScreen = vesaFinishInitScreen;
83 + atic->backend_funcs.createRes = vesaCreateResources;
84 + atic->backend_funcs.preserve = vesaPreserve;
85 + atic->backend_funcs.restore = vesaRestore;
86 + atic->backend_funcs.dpms = vesaDPMS;
87 + atic->backend_funcs.enable = vesaEnable;
88 + atic->backend_funcs.disable = vesaDisable;
89 + atic->backend_funcs.getColors = vesaGetColors;
90 + atic->backend_funcs.putColors = vesaPutColors;
91 +#ifdef RANDR
92 + atic->backend_funcs.randrSetConfig = vesaRandRSetConfig;
93 +#endif
94 + }
95 +#endif
96 +
97 + if (!initialized || !ATIMap(card, atic)) {
98 + xfree(atic);
99 + return FALSE;
100 + }
101 +
102 + card->driver = atic;
103 +
104 + for (i = 0; ati_pci_ids[i].name != NULL; i++) {
105 + if (ati_pci_ids[i].device == card->attr.deviceID) {
106 + atic->pci_id = &ati_pci_ids[i];
107 + break;
108 + }
109 + }
110 +
111 + ErrorF("Using ATI card: %s\n", atic->pci_id->name);
112 +
113 + return TRUE;
114 +}
115 +
116 +static void
117 +ATICardFini(KdCardInfo * card)
118 +{
119 + ATICardInfo *atic = (ATICardInfo *) card->driver;
120 +
121 + ATIUnmap(card, atic);
122 + atic->backend_funcs.cardfini(card);
123 +}
124 +
125 +/*
126 + * Once screen->off_screen_base is set, this function
127 + * allocates the remaining memory appropriately
128 + */
129 +
130 +static void
131 +ATISetOffscreen(KdScreenInfo * screen)
132 +{
133 + ATICardInfo(screen);
134 + int screen_size;
135 + char *mmio = atic->reg_base;
136 +
137 + /* check (and adjust) pitch */
138 + if (mmio) {
139 + int byteStride = screen->fb[0].byteStride;
140 + int bitStride;
141 + int pixelStride;
142 + int bpp = screen->fb[0].bitsPerPixel;
143 +
144 + /*
145 + * Ensure frame buffer is correctly aligned
146 + */
147 + if (byteStride & 0x3f) {
148 + byteStride = (byteStride + 0x3f) & ~0x3f;
149 + bitStride = byteStride * 8;
150 + pixelStride = bitStride / bpp;
151 +
152 + screen->fb[0].byteStride = byteStride;
153 + screen->fb[0].pixelStride = pixelStride;
154 + }
155 + }
156 +
157 + screen_size = screen->fb[0].byteStride * screen->height;
158 +
159 + screen->off_screen_base = screen_size;
160 +
161 +}
162 +
163 +static Bool
164 +ATIScreenInit(KdScreenInfo * screen)
165 +{
166 + ATIScreenInfo *atis;
167 + ATICardInfo(screen);
168 + Bool success = FALSE;
169 +
170 + atis = xcalloc(sizeof(ATIScreenInfo), 1);
171 + if (atis == NULL)
172 + return FALSE;
173 +
174 + atis->atic = atic;
175 + atis->screen = screen;
176 + screen->driver = atis;
177 +
178 + if (screen->fb[0].depth == 0)
179 + screen->fb[0].depth = 16;
180 +#ifdef KDRIVEFBDEV
181 + if (atic->use_fbdev) {
182 + success = fbdevScreenInitialize(screen, &atis->backend_priv.fbdev);
183 + }
184 +#endif
185 +#ifdef KDRIVEVESA
186 + if (atic->use_vesa) {
187 + success = vesaScreenInitialize(screen, &atis->backend_priv.vesa);
188 + }
189 +#endif
190 +
191 + if (!success) {
192 + screen->driver = NULL;
193 + xfree(atis);
194 + return FALSE;
195 + }
196 +
197 + ErrorF
198 + ("Offscreen memory at offset %08x, memory base %08x, size %08x\n",
199 + screen->off_screen_base, screen->memory_base,
200 + screen->memory_size);
201 + ATISetOffscreen(screen);
202 +
203 + return TRUE;
204 +}
205 +
206 +#ifdef RANDR
207 +static Bool
208 +ATIRandRSetConfig(ScreenPtr pScreen,
209 + Rotation randr, int rate, RRScreenSizePtr pSize)
210 +{
211 + KdScreenPriv(pScreen);
212 + KdScreenInfo *screen = pScreenPriv->screen;
213 + ATICardInfo *atic = screen->card->driver;
214 + Bool ret;
215 +
216 + ATIDrawDisable(pScreen);
217 + ret = atic->backend_funcs.randrSetConfig(pScreen, randr, rate, pSize);
218 + ATISetOffscreen(screen);
219 + /*
220 + * Set frame buffer mapping
221 + */
222 + (*pScreen->ModifyPixmapHeader) (fbGetScreenPixmap(pScreen),
223 + pScreen->width,
224 + pScreen->height,
225 + screen->fb[0].depth,
226 + screen->fb[0].bitsPerPixel,
227 + screen->fb[0].byteStride,
228 + screen->fb[0].frameBuffer);
229 +
230 + ATIDrawEnable(pScreen);
231 + return ret;
232 +}
233 +
234 +static Bool
235 +ATIRandRInit(ScreenPtr pScreen)
236 +{
237 + rrScrPrivPtr pScrPriv;
238 +
239 + pScrPriv = rrGetScrPriv(pScreen);
240 + pScrPriv->rrSetConfig = ATIRandRSetConfig;
241 + return TRUE;
242 +}
243 +#endif
244 +
245 +static void
246 +ATIScreenFini(KdScreenInfo * screen)
247 +{
248 + ATIScreenInfo *atis = (ATIScreenInfo *) screen->driver;
249 + ATICardInfo *atic = screen->card->driver;
250 +
251 + atic->backend_funcs.scrfini(screen);
252 + xfree(atis);
253 + screen->driver = 0;
254 +}
255 +
256 +Bool
257 +ATIMap(KdCardInfo * card, ATICardInfo * atic)
258 +{
259 + atic->mem_base = (CARD8 *) KdMapDevice(ATI_MEM_BASE(card),
260 + ATI_MEM_SIZE(card));
261 +
262 + if (atic->mem_base == NULL)
263 + return FALSE;
264 + atic->reg_base = atic->mem_base + 0x10000; /* XXX */
265 +
266 + KdSetMappedMode(ATI_MEM_BASE(card), ATI_MEM_SIZE(card),
267 + KD_MAPPED_MODE_REGISTERS);
268 +
269 + return TRUE;
270 +}
271 +
272 +void
273 +ATIUnmap(KdCardInfo * card, ATICardInfo * atic)
274 +{
275 + if (atic->reg_base) {
276 + KdResetMappedMode(ATI_REG_BASE(card), ATI_REG_SIZE(card),
277 + KD_MAPPED_MODE_REGISTERS);
278 + KdUnmapDevice((void *) atic->reg_base, ATI_REG_SIZE(card));
279 + atic->reg_base = 0;
280 + }
281 +}
282 +
283 +static Bool
284 +ATIInitScreen(ScreenPtr pScreen)
285 +{
286 + KdScreenPriv(pScreen);
287 + ATICardInfo(pScreenPriv);
288 +
289 + return atic->backend_funcs.initScreen(pScreen);
290 +}
291 +
292 +static Bool
293 +ATIFinishInitScreen(ScreenPtr pScreen)
294 +{
295 + KdScreenPriv(pScreen);
296 + ATICardInfo(pScreenPriv);
297 +
298 + if (!atic->backend_funcs.finishInitScreen(pScreen))
299 + return FALSE;
300 +#ifdef RANDR
301 + if (!ATIRandRInit(pScreen))
302 + return FALSE;
303 +#endif
304 + return TRUE;
305 +}
306 +
307 +static Bool
308 +ATICreateResources(ScreenPtr pScreen)
309 +{
310 + KdScreenPriv(pScreen);
311 + ATICardInfo(pScreenPriv);
312 +
313 + return atic->backend_funcs.createRes(pScreen);
314 +}
315 +
316 +static void
317 +ATIPreserve(KdCardInfo * card)
318 +{
319 + ATICardInfo *atic = card->driver;
320 +
321 + atic->backend_funcs.preserve(card);
322 +}
323 +
324 +static void
325 +ATIRestore(KdCardInfo * card)
326 +{
327 + ATICardInfo *atic = card->driver;
328 +
329 + ATIUnmap(card, atic);
330 +
331 + atic->backend_funcs.restore(card);
332 +}
333 +
334 +static Bool
335 +ATIDPMS(ScreenPtr pScreen, int mode)
336 +{
337 + KdScreenPriv(pScreen);
338 + ATICardInfo(pScreenPriv);
339 +
340 + return atic->backend_funcs.dpms(pScreen, mode);
341 +}
342 +
343 +static Bool
344 +ATIEnable(ScreenPtr pScreen)
345 +{
346 + KdScreenPriv(pScreen);
347 + ATICardInfo(pScreenPriv);
348 + mc_ext_mem_location_u eml;
349 + char *mmio;
350 +
351 + if (!atic->backend_funcs.enable(pScreen))
352 + return FALSE;
353 +
354 + if ((atic->reg_base == NULL)
355 + && !ATIMap(pScreenPriv->screen->card, atic))
356 + return FALSE;
357 +
358 + mmio = atic->reg_base;
359 + eml.val = MMIO_IN32(mmio, mmMC_EXT_MEM_LOCATION);
360 + atic->ext_mem_location = eml.f.mc_ext_mem_start << 8;
361 + ATISetOffscreen(pScreenPriv->screen);
362 +
363 + return TRUE;
364 +}
365 +
366 +static void
367 +ATIDisable(ScreenPtr pScreen)
368 +{
369 + KdScreenPriv(pScreen);
370 + ATICardInfo(pScreenPriv);
371 +
372 + ATIUnmap(pScreenPriv->card, atic);
373 +
374 + atic->backend_funcs.disable(pScreen);
375 +}
376 +
377 +static void
378 +ATIGetColors(ScreenPtr pScreen, int fb, int n, xColorItem * pdefs)
379 +{
380 + KdScreenPriv(pScreen);
381 + ATICardInfo(pScreenPriv);
382 +
383 + atic->backend_funcs.getColors(pScreen, fb, n, pdefs);
384 +}
385 +
386 +static void
387 +ATIPutColors(ScreenPtr pScreen, int fb, int n, xColorItem * pdefs)
388 +{
389 + KdScreenPriv(pScreen);
390 + ATICardInfo(pScreenPriv);
391 +
392 + atic->backend_funcs.putColors(pScreen, fb, n, pdefs);
393 +}
394 +
395 +/* Compute log base 2 of val. */
396 +int
397 +ATILog2(int val)
398 +{
399 + int bits;
400 +
401 + for (bits = 0; val != 0; val >>= 1, ++bits);
402 + return bits - 1;
403 +}
404 +
405 +
406 +
407 +KdCardFuncs ATIFuncs = {
408 + ATICardInit, /* cardinit */
409 + ATIScreenInit, /* scrinit */
410 + ATIInitScreen, /* initScreen */
411 + ATIFinishInitScreen, /* finishInitScreen */
412 + ATICreateResources, /* createRes */
413 + ATIPreserve, /* preserve */
414 + ATIEnable, /* enable */
415 + ATIDPMS, /* dpms */
416 + ATIDisable, /* disable */
417 + ATIRestore, /* restore */
418 + ATIScreenFini, /* scrfini */
419 + ATICardFini, /* cardfini */
420 +
421 +#define ATICursorInit 0
422 +#define ATICursorEnable 0
423 +#define ATICursorDisable 0
424 +#define ATICursorFini 0
425 +#define ATIRecolorCursor 0
426 + ATICursorInit, /* initCursor */
427 + ATICursorEnable, /* enableCursor */
428 + ATICursorDisable, /* disableCursor */
429 + ATICursorFini, /* finiCursor */
430 + ATIRecolorCursor, /* recolorCursor */
431 +
432 + ATIDrawInit, /* initAccel */
433 + ATIDrawEnable, /* enableAccel */
434 + ATIDrawDisable, /* disableAccel */
435 + ATIDrawFini, /* finiAccel */
436 +
437 + ATIGetColors, /* getColors */
438 + ATIPutColors, /* putColors */
439 +};
440 Index: git/hw/kdrive/w100/ati_cursor.c
441 ===================================================================
442 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
443 +++ git/hw/kdrive/w100/ati_cursor.c 2006-09-02 12:12:14.000000000 +0200
444 @@ -0,0 +1,93 @@
445 +/*
446 + * Copyright © 2006 Alberto Mardegan <mardy@users.sourceforge.net>
447 + *
448 + * Permission to use, copy, modify, distribute, and sell this software and its
449 + * documentation for any purpose is hereby granted without fee, provided that
450 + * the above copyright notice appear in all copies and that both that
451 + * copyright notice and this permission notice appear in supporting
452 + * documentation, and that the name of Alberto Mardegan not be used in
453 + * advertising or publicity pertaining to distribution of the software without
454 + * specific, written prior permission. Alberto Mardegan makes no
455 + * representations about the suitability of this software for any purpose. It
456 + * is provided "as is" without express or implied warranty.
457 + *
458 + * ALBERTO MARDEGAN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
459 + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
460 + * EVENT SHALL ALBERTO MARDEGAN BE LIABLE FOR ANY SPECIAL, INDIRECT OR
461 + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
462 + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
463 + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
464 + * PERFORMANCE OF THIS SOFTWARE.
465 + */
466 +
467 +#ifdef HAVE_CONFIG_H
468 +#include <kdrive-config.h>
469 +#endif
470 +#include "ati.h"
471 +#include "cursorstr.h"
472 +#include "ati_draw.h"
473 +
474 +static void
475 +ATIMoveCursor(ScreenPtr pScreen, int x, int y)
476 +{
477 +}
478 +
479 +
480 +static Bool
481 +ATIRealizeCursor(ScreenPtr pScreen, CursorPtr pCursor)
482 +{
483 + return FALSE;
484 +}
485 +
486 +
487 +static Bool
488 +ATIUnrealizeCursor(ScreenPtr pScreen, CursorPtr pCursor)
489 +{
490 + return TRUE;
491 +}
492 +
493 +
494 +static void
495 +ATISetCursor(ScreenPtr pScreen, CursorPtr pCursor, int x, int y)
496 +{
497 +}
498 +
499 +
500 +miPointerSpriteFuncRec ATIPointerSpriteFuncs = {
501 + ATIRealizeCursor,
502 + ATIUnrealizeCursor,
503 + ATISetCursor,
504 + ATIMoveCursor,
505 +};
506 +
507 +
508 +void
509 +ATICursorEnable(ScreenPtr pScreen)
510 +{
511 +}
512 +
513 +
514 +void
515 +ATICursorDisable(ScreenPtr pScreen)
516 +{
517 +}
518 +
519 +
520 +Bool
521 +ATICursorInit(ScreenPtr pScreen)
522 +{
523 + return FALSE;
524 +}
525 +
526 +
527 +void
528 +ATIRecolorCursor(ScreenPtr pScreen, int ndef, xColorItem * pdef)
529 +{
530 + return;
531 +}
532 +
533 +
534 +void
535 +ATICursorFini(ScreenPtr pScreen)
536 +{
537 +}
538 Index: git/hw/kdrive/w100/ati_dma.c
539 ===================================================================
540 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
541 +++ git/hw/kdrive/w100/ati_dma.c 2006-09-02 12:12:14.000000000 +0200
542 @@ -0,0 +1,333 @@
543 +/*
544 + * Copyright © 2006 Alberto Mardegan <mardy@users.sourceforge.net>
545 + *
546 + * Permission to use, copy, modify, distribute, and sell this software and its
547 + * documentation for any purpose is hereby granted without fee, provided that
548 + * the above copyright notice appear in all copies and that both that
549 + * copyright notice and this permission notice appear in supporting
550 + * documentation, and that the name of Alberto Mardegan not be used in
551 + * advertising or publicity pertaining to distribution of the software without
552 + * specific, written prior permission. Alberto Mardegan makes no
553 + * representations about the suitability of this software for any purpose. It
554 + * is provided "as is" without express or implied warranty.
555 + *
556 + * ALBERTO MARDEGAN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
557 + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
558 + * EVENT SHALL ALBERTO MARDEGAN BE LIABLE FOR ANY SPECIAL, INDIRECT OR
559 + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
560 + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
561 + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
562 + * PERFORMANCE OF THIS SOFTWARE.
563 + */
564 +
565 +#include <sys/time.h>
566 +
567 +#include "ati.h"
568 +#include "w100_regs.h"
569 +#include "w100_const.h"
570 +#include "ati_dma.h"
571 +#include "ati_draw.h"
572 +
573 +
574 +#define DEBUG_FIFO 0
575 +
576 +extern CARD32 w100_microcode[][2];
577 +
578 +#if DEBUG_FIFO
579 +static void
580 +ATIDebugFifo(ATIScreenInfo * atis)
581 +{
582 + ATICardInfo *atic = atis->atic;
583 + char *mmio = atic->reg_base;
584 +
585 + ErrorF("mmCP_CSQ_CNTL: 0x%08x\n", MMIO_IN32(mmio, mmCP_CSQ_CNTL));
586 + ErrorF("mmCP_CSQ_STAT: 0x%08x\n", MMIO_IN32(mmio, mmCP_CSQ_STAT));
587 + ErrorF("mmRBBM_STATUS: 0x%08x\n", MMIO_IN32(mmio, mmRBBM_STATUS));
588 +}
589 +#endif
590 +
591 +static void
592 +ATIUploadMicrocode(ATIScreenInfo * atis)
593 +{
594 + ATICardInfo *atic = atis->atic;
595 + char *mmio = atic->reg_base;
596 + int i;
597 +
598 + MMIO_OUT32(mmio, mmCP_ME_RAM_ADDR, 0);
599 + for (i = 0; i < 256; i++) {
600 + MMIO_OUT32(mmio, mmCP_ME_RAM_DATAH, w100_microcode[i][1]);
601 + MMIO_OUT32(mmio, mmCP_ME_RAM_DATAL, w100_microcode[i][0]);
602 + }
603 +}
604 +
605 +/* Required when reading from video memory after acceleration to make sure all
606 + * data has been flushed to video memory from the pixel cache.
607 + */
608 +static void
609 +ATIFlushPixelCache(ATIScreenInfo * atis)
610 +{
611 + ATICardInfo *atic = atis->atic;
612 + char *mmio = atic->reg_base;
613 + rbbm_status_u rs;
614 + TIMEOUT_LOCALS;
615 +
616 + WHILE_NOT_TIMEOUT(.2) {
617 + rs.val = MMIO_IN32(mmio, mmRBBM_STATUS);
618 + if (!rs.f.gui_active)
619 + break;
620 + }
621 + if (TIMEDOUT())
622 + ErrorF("Timeout flushing pixel cache.\n");
623 +}
624 +
625 +static void
626 +ATIEngineReset(ATIScreenInfo * atis)
627 +{
628 + ATICardInfo *atic = atis->atic;
629 + char *mmio = atic->reg_base;
630 + CARD32 sclk_cntl;
631 + sclk_cntl_u sc;
632 + rbbm_soft_reset_u rsr;
633 +
634 +#if DEBUG_FIFO
635 + ErrorF("Engine Reset!\n");
636 + ATIDebugFifo(atis);
637 +#endif
638 +
639 + ATIFlushPixelCache(atis);
640 +
641 + sc.val = sclk_cntl = MMIO_IN32(mmio, mmSCLK_CNTL);
642 + sc.f.sclk_force_e2 = sc.f.sclk_force_e3 = sc.f.sclk_force_idct = 1;
643 + MMIO_OUT32(mmio, mmSCLK_CNTL, sc.val);
644 +
645 + rsr.val = 0;
646 + rsr.f.soft_reset_e2 = 1;
647 + MMIO_OUT32(mmio, mmRBBM_SOFT_RESET, rsr.val);
648 + MMIO_OUT32(mmio, mmRBBM_SOFT_RESET, 0);
649 +
650 + MMIO_OUT32(mmio, mmSCLK_CNTL, sclk_cntl);
651 +}
652 +
653 +inline void
654 +ATIWaitAvailMMIO(ATIScreenInfo * atis, int n)
655 +{
656 + ATICardInfo *atic = atis->atic;
657 + char *mmio = atic->reg_base;
658 + rbbm_status_u rs;
659 + TIMEOUT_LOCALS;
660 +
661 + if (atis->mmio_avail >= n) {
662 + atis->mmio_avail -= n;
663 + return;
664 + }
665 + WHILE_NOT_TIMEOUT(.2) {
666 + rs.val = MMIO_IN32(mmio, mmRBBM_STATUS);
667 + atis->mmio_avail = rs.f.cmdfifo_avail;
668 + if (atis->mmio_avail >= n)
669 + break;
670 + ErrorF("Available %d slots.\n", atis->mmio_avail);
671 + }
672 + if (TIMEDOUT()) {
673 + ErrorF("Timeout waiting for %d MMIO slots.\n", n);
674 + ATIEngineReset(atis);
675 + ATIDrawSetup(atis->screen->pScreen);
676 + }
677 + atis->mmio_avail -= n;
678 +}
679 +
680 +
681 +void
682 +ATIWaitIdle(ATIScreenInfo * atis)
683 +{
684 + ATICardInfo *atic = atis->atic;
685 + char *mmio = atic->reg_base;
686 + rbbm_status_u rs;
687 + TIMEOUT_LOCALS;
688 +
689 + /* Empty the fifo */
690 + ATIWaitAvailMMIO(atis, 16);
691 +
692 + WHILE_NOT_TIMEOUT(.2) {
693 + rs.val = MMIO_IN32(mmio, mmRBBM_STATUS);
694 + if (!rs.f.gui_active)
695 + break;
696 +#if DEBUG_FIFO
697 + ATIDebugFifo(atis);
698 +#endif
699 + /* don't know if this is needed, but it's in aticore */
700 + MMIO_IN32(mmio, mmCP_RB_RPTR);
701 + }
702 + if (TIMEDOUT()) {
703 + ErrorF("Timeout idling accelerator, resetting...\n");
704 + ATIEngineReset(atis);
705 + ATIDrawSetup(atis->screen->pScreen);
706 + }
707 +
708 + ATIFlushPixelCache(atis);
709 +
710 +#if DEBUG_FIFO
711 + ErrorF("Idle?\n");
712 + ATIDebugFifo(atis);
713 +#endif
714 +}
715 +
716 +
717 +static Bool
718 +ATIDMAInit(ScreenPtr pScreen, Bool use_agp)
719 +{
720 + KdScreenPriv(pScreen);
721 + ATIScreenInfo(pScreenPriv);
722 + ATICardInfo(pScreenPriv);
723 + char *mmio = atic->reg_base;
724 + int dma_offset, rbsize = 10;
725 + wrap_start_dir_u wsd;
726 + wrap_buf_a_u wba;
727 + cp_rb_cntl_u rc;
728 + cp_csq_cntl_u cc;
729 + CARD32 mem_offset;
730 +
731 + /* with rbsize = 10, DMA buffer will be of 0x2000 (8192) bytes */
732 + atis->ring_count = 1 << (rbsize + 1);
733 + atis->ring_mask = atis->ring_count - 1;
734 + atis->ring_len = atis->ring_count * 4;
735 + atis->dma_space = KdOffscreenAlloc(pScreen, atis->ring_len,
736 + 16, TRUE, NULL, NULL);
737 + if (atis->dma_space == NULL)
738 + return FALSE;
739 +
740 + wsd.val = MMIO_IN32(mmio, mmWRAP_START_DIR);
741 + atis->ring_addr =
742 + (CARD32 *) (atic->mem_base + (wsd.f.start_addr << 1));
743 + dma_offset = atis->dma_space->offset;
744 +
745 + ATIUploadMicrocode(atis);
746 + ATIEngineReset(atis);
747 +
748 + atis->ring_read = 0;
749 + atis->ring_write = 0;
750 + atis->ring_free = atis->ring_count;
751 +
752 + mem_offset = atic->ext_mem_location + atis->dma_space->offset;
753 + MMIO_OUT32(mmio, mmCP_RB_BASE, mem_offset);
754 + MMIO_OUT32(mmio, mmCP_RB_WPTR, atis->ring_write);
755 + MMIO_OUT32(mmio, mmCP_RB_RPTR, atis->ring_read);
756 + MMIO_OUT32(mmio, mmCP_RB_RPTR_ADDR, 0);
757 +
758 + wba.val = 0;
759 + wba.f.offset_addr_a = mem_offset;
760 + switch (rbsize) {
761 + case 9:
762 + wba.f.block_size_a = WB_BLOCK_SIZE_A_0;
763 + break;
764 + case 10:
765 + wba.f.block_size_a = WB_BLOCK_SIZE_A_1;
766 + break;
767 + case 11:
768 + wba.f.block_size_a = WB_BLOCK_SIZE_A_2;
769 + break;
770 + case 12:
771 + wba.f.block_size_a = WB_BLOCK_SIZE_A_3;
772 + break;
773 + case 13:
774 + wba.f.block_size_a = WB_BLOCK_SIZE_A_4;
775 + break;
776 + }
777 + MMIO_OUT32(mmio, mmWRAP_BUF_A, wba.val);
778 +
779 + rc.val = 0;
780 + rc.f.rb_no_update = 1;
781 + rc.f.rb_bufsz = rbsize;
782 + MMIO_OUT32(mmio, mmCP_RB_CNTL, rc.val);
783 +
784 + cc.val = 0;
785 + cc.f.csq_mode = CSQ_CNTL_MODE_FREERUN;
786 + MMIO_OUT32(mmio, mmCP_CSQ_CNTL, cc.val);
787 +
788 + return TRUE;
789 +}
790 +
791 +static Bool
792 +ATIDMAFini(ScreenPtr pScreen)
793 +{
794 + KdScreenPriv(pScreen);
795 + ATIScreenInfo(pScreenPriv);
796 + ATICardInfo(pScreenPriv);
797 + char *mmio = atic->reg_base;
798 +
799 + MMIO_OUT32(mmio, mmCP_CSQ_CNTL, 0);
800 +
801 + ATIEngineReset(atis);
802 +
803 + //KdOffscreenFree(pScreen, atis->dma_space);
804 +
805 + return TRUE;
806 +}
807 +
808 +void
809 +ATIDMASetup(ScreenPtr pScreen)
810 +{
811 + KdScreenPriv(pScreen);
812 + ATIScreenInfo(pScreenPriv);
813 +
814 + atis->using_dma = FALSE;
815 + atis->using_pio = FALSE;
816 + if (ATIDMAInit(pScreen, FALSE))
817 + atis->using_dma = TRUE;
818 +
819 + if (atis->using_dma)
820 + ErrorF("Initialized DMA\n");
821 +}
822 +
823 +void
824 +ATIDMATeardown(ScreenPtr pScreen)
825 +{
826 + KdScreenPriv(pScreen);
827 + ATIScreenInfo(pScreenPriv);
828 +
829 + ATIWaitIdle(atis);
830 +
831 + if (atis->using_dma)
832 + ATIDMAFini(pScreen);
833 +
834 + atis->using_pio = FALSE;
835 + atis->using_dma = FALSE;
836 +}
837 +
838 +
839 +CARD32 *
840 +ATIRequestEntries(ATIScreenInfo * atis, int n)
841 +{
842 + char *mmio = atis->atic->reg_base;
843 + CARD32 *ptr;
844 + TIMEOUT_LOCALS;
845 +
846 + WHILE_NOT_TIMEOUT(1) {
847 + if (atis->ring_free > n) {
848 + ptr = atis->ring_addr + atis->ring_write;
849 + return ptr;
850 + }
851 + atis->ring_read = MMIO_IN32(mmio, mmCP_RB_RPTR);
852 + atis->ring_write = MMIO_IN32(mmio, mmCP_RB_WPTR);
853 +
854 + if (atis->ring_read == atis->ring_write) {
855 + atis->ring_free = atis->ring_count;
856 + } else {
857 + atis->ring_free =
858 + (atis->ring_count +
859 + atis->ring_read - atis->ring_write) & atis->ring_mask;
860 + }
861 + }
862 + if (TIMEDOUT())
863 + ErrorF("Timeout waiting for %d entries.\n", n);
864 + return NULL;
865 +}
866 +
867 +void
868 +ATISubmitEntries(ATIScreenInfo * atis, int n)
869 +{
870 + char *mmio = atis->atic->reg_base;
871 + atis->ring_free -= n;
872 + atis->ring_write += n;
873 + atis->ring_write &= atis->ring_mask;
874 + MMIO_OUT32(mmio, mmCP_RB_WPTR, atis->ring_write);
875 +}
876 Index: git/hw/kdrive/w100/ati_dma.h
877 ===================================================================
878 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
879 +++ git/hw/kdrive/w100/ati_dma.h 2006-09-02 12:12:14.000000000 +0200
880 @@ -0,0 +1,176 @@
881 +/*
882 + * Copyright © 2004 Eric Anholt
883 + *
884 + * Permission to use, copy, modify, distribute, and sell this software and its
885 + * documentation for any purpose is hereby granted without fee, provided that
886 + * the above copyright notice appear in all copies and that both that
887 + * copyright notice and this permission notice appear in supporting
888 + * documentation, and that the name of Eric Anholt not be used in
889 + * advertising or publicity pertaining to distribution of the software without
890 + * specific, written prior permission. Eric Anholt makes no
891 + * representations about the suitability of this software for any purpose. It
892 + * is provided "as is" without express or implied warranty.
893 + *
894 + * ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
895 + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
896 + * EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
897 + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
898 + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
899 + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
900 + * PERFORMANCE OF THIS SOFTWARE.
901 + */
902 +/* $Header: /cvs/xserver/xserver/hw/kdrive/ati/ati_dma.h,v 1.5 2005-01-27 05:25:57 anholt Exp $ */
903 +
904 +#ifndef _ATI_DMA_H_
905 +#define _ATI_DMA_H_
906 +
907 +#define CCE_DEBUG 1
908 +
909 +/* CCE packet defines */
910 +
911 +#define ATI_CCE_PACKETTYPE_MASK 0xc0000000
912 +#define ATI_CCE_PACKET0 0x00000000
913 +#define ATI_CCE_PACKET0_COUNT_MASK 0x3fff0000
914 +#define ATI_CCE_PACKET0_ONE_REG_WR 0x00008000
915 +#define ATI_CCE_PACKET0_REG_MASK 0x000007ff
916 +#define ATI_CCE_PACKET1 0x40000000
917 +#define ATI_CCE_PACKET1_REG_1 0x000007ff
918 +#define ATI_CCE_PACKET1_REG_2 0x003ff800
919 +#define ATI_CCE_PACKET1_REG_2_SHIFT 10
920 +#define ATI_CCE_PACKET2 0x80000000
921 +#define ATI_CCE_PACKET3 0xc0000000
922 +#define ATI_CCE_PACKET3_COUNT_MASK 0x3fff0000
923 +#define ATI_CCE_PACKET3_IT_OPCODE_MASK 0x0000ff00
924 +
925 +
926 +#if !CCE_DEBUG
927 +#define DMA_PACKET0(reg, count) \
928 + (ATI_CCE_PACKET0 | (((count) - 1) << 16) | ((reg) >> 2))
929 +#else
930 +#define DMA_PACKET0(reg, count) \
931 + (__packet0count = (count), __reg = (reg), \
932 + ATI_CCE_PACKET0 | (((count) - 1) << 16) | ((reg) >> 2))
933 +#endif
934 +#define DMA_PACKET1(reg1, reg2) \
935 + (ATI_CCE_PACKET1 | \
936 + (((reg2) >> 2) << ATI_CCE_PACKET1_REG_2_SHIFT) | ((reg1) >> 2))
937 +#define DMA_PACKET3(type, count) \
938 + ((type) | (((count) - 1) << 16))
939 +
940 +
941 +
942 +#ifdef USE_DMA
943 +
944 +#if !CCE_DEBUG
945 +
946 +#define RING_LOCALS \
947 + CARD32 *__head; int __count
948 +#define BEGIN_DMA(n) \
949 +do { \
950 + __head = ATIRequestEntries(atis, n); \
951 + __count = 0; \
952 +} while (0)
953 +#define END_DMA() do { \
954 + ATISubmitEntries(atis, __count); \
955 +} while (0)
956 +
957 +#else /* CCE_DEBUG */
958 +#define RING_LOCALS \
959 + CARD32 *__head; int __count, __total, __reg, __packet0count
960 +#define BEGIN_DMA(n) \
961 +do { \
962 + __head = ATIRequestEntries(atis, n); \
963 + __count = 0; \
964 + __total = n; \
965 + __reg = 0; \
966 + __packet0count = 0; \
967 +} while (0)
968 +#define END_DMA() do { \
969 + if (__count != __total) \
970 + FatalError("count != total (%d vs %d) at %s:%d\n", \
971 + __count, __total, __FILE__, __LINE__); \
972 + ATISubmitEntries(atis, __count); \
973 +} while (0)
974 +
975 +#endif /* CCE_DEBUG */
976 +
977 +#define BEGIN_DMA_REG(n) BEGIN_DMA(n * 2)
978 +#define END_DMA_REG() END_DMA()
979 +
980 +#define OUT_REG(reg, val) \
981 +do { \
982 + OUT_RING(DMA_PACKET0(reg, 1)); \
983 + OUT_RING(val); \
984 +} while (0)
985 +
986 +
987 +#else /* USE_DMA */
988 +
989 +
990 +#define RING_LOCALS char *__mmio = atis->atic->reg_base
991 +#define BEGIN_DMA_REG(n) \
992 +do { \
993 + ATIWaitAvailMMIO(atis, n); \
994 +} while (0)
995 +#define END_DMA_REG() do {} while (0)
996 +#define OUT_REG(reg, val) MMIO_OUT32(__mmio, reg, val)
997 +#endif /* USE_DMA */
998 +
999 +
1000 +#define OUT_RING(val) do { \
1001 + __head[__count++] = (val); \
1002 +} while (0)
1003 +
1004 +#define OUT_RING_REG(reg, val) do { \
1005 + if (__reg != reg) \
1006 + FatalError("unexpected reg (0x%x vs 0x%x) at %s:%d\n", \
1007 + reg, __reg, __FILE__, __LINE__); \
1008 + if (__packet0count-- <= 0) \
1009 + FatalError("overrun of packet0 at %s:%d\n", \
1010 + __FILE__, __LINE__); \
1011 + __head[__count++] = (val); \
1012 + __reg += 4; \
1013 +} while (0)
1014 +
1015 +#define OUT_RING_F(x) OUT_RING(GET_FLOAT_BITS(x))
1016 +
1017 +#define TIMEOUT_LOCALS struct timeval _target, _curtime
1018 +
1019 +static inline Bool
1020 +tv_le(struct timeval *tv1, struct timeval *tv2)
1021 +{
1022 + if (tv1->tv_sec < tv2->tv_sec ||
1023 + (tv1->tv_sec == tv2->tv_sec && tv1->tv_usec < tv2->tv_usec))
1024 + return TRUE;
1025 + else
1026 + return FALSE;
1027 +}
1028 +
1029 +#define WHILE_NOT_TIMEOUT(_timeout) \
1030 + gettimeofday(&_target, NULL); \
1031 + _target.tv_usec += ((_timeout) * 1000000); \
1032 + _target.tv_sec += _target.tv_usec / 1000000; \
1033 + _target.tv_usec = _target.tv_usec % 1000000; \
1034 + while (gettimeofday(&_curtime, NULL), tv_le(&_curtime, &_target))
1035 +
1036 +#define TIMEDOUT() (!tv_le(&_curtime, &_target))
1037 +
1038 +
1039 +void
1040 +ATIFlushIndirect(ATIScreenInfo *atis, Bool discard);
1041 +
1042 +void
1043 +ATIDMASetup(ScreenPtr pScreen);
1044 +
1045 +void
1046 +ATIDMATeardown(ScreenPtr pScreen);
1047 +
1048 +CARD32 *
1049 +ATIRequestEntries(ATIScreenInfo *atis, int n);
1050 +
1051 +void
1052 +ATISubmitEntries(ATIScreenInfo *atis, int n);
1053 +
1054 +inline void
1055 +ATIWaitAvailMMIO(ATIScreenInfo *atis, int n);
1056 +#endif /* _ATI_DMA_H_ */
1057 Index: git/hw/kdrive/w100/ati_draw.c
1058 ===================================================================
1059 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1060 +++ git/hw/kdrive/w100/ati_draw.c 2006-09-02 12:12:14.000000000 +0200
1061 @@ -0,0 +1,477 @@
1062 +/*
1063 + * Copyright © 2006 Alberto Mardegan <mardy@users.sourceforge.net>
1064 + *
1065 + * Permission to use, copy, modify, distribute, and sell this software and its
1066 + * documentation for any purpose is hereby granted without fee, provided that
1067 + * the above copyright notice appear in all copies and that both that
1068 + * copyright notice and this permission notice appear in supporting
1069 + * documentation, and that the name of Alberto Mardegan not be used in
1070 + * advertising or publicity pertaining to distribution of the software without
1071 + * specific, written prior permission. Alberto Mardegan makes no
1072 + * representations about the suitability of this software for any purpose. It
1073 + * is provided "as is" without express or implied warranty.
1074 + *
1075 + * ALBERTO MARDEGAN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
1076 + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
1077 + * EVENT SHALL ALBERTO MARDEGAN BE LIABLE FOR ANY SPECIAL, INDIRECT OR
1078 + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
1079 + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
1080 + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
1081 + * PERFORMANCE OF THIS SOFTWARE.
1082 + */
1083 +
1084 +#define USE_DMA
1085 +#define DRAW_USING_PACKET3
1086 +
1087 +#ifdef HAVE_CONFIG_H
1088 +#include <kdrive-config.h>
1089 +#endif
1090 +#include "ati.h"
1091 +#include "w100_regs.h"
1092 +#include "w100_const.h"
1093 +#include "ati_dma.h"
1094 +#include "ati_draw.h"
1095 +#include "kaa.h"
1096 +
1097 +
1098 +CARD8 ATISolidRop[16] = {
1099 + /* GXclear */ 0x00,
1100 + /* 0 */
1101 + /* GXand */ 0xa0,
1102 + /* src AND dst */
1103 + /* GXandReverse */ 0x50,
1104 + /* src AND NOT dst */
1105 + /* GXcopy */ 0xf0,
1106 + /* src */
1107 + /* GXandInverted */ 0x0a,
1108 + /* NOT src AND dst */
1109 + /* GXnoop */ 0xaa,
1110 + /* dst */
1111 + /* GXxor */ 0x5a,
1112 + /* src XOR dst */
1113 + /* GXor */ 0xfa,
1114 + /* src OR dst */
1115 + /* GXnor */ 0x05,
1116 + /* NOT src AND NOT dst */
1117 + /* GXequiv */ 0xa5,
1118 + /* NOT src XOR dst */
1119 + /* GXinvert */ 0x55,
1120 + /* NOT dst */
1121 + /* GXorReverse */ 0xf5,
1122 + /* src OR NOT dst */
1123 + /* GXcopyInverted */ 0x0f,
1124 + /* NOT src */
1125 + /* GXorInverted */ 0xaf,
1126 + /* NOT src OR dst */
1127 + /* GXnand */ 0x5f,
1128 + /* NOT src OR NOT dst */
1129 + /* GXset */ 0xff,
1130 + /* 1 */
1131 +};
1132 +
1133 +CARD8 ATIBltRop[16] = {
1134 + /* GXclear */ 0x00,
1135 + /* 0 */
1136 + /* GXand */ 0x88,
1137 + /* src AND dst */
1138 + /* GXandReverse */ 0x44,
1139 + /* src AND NOT dst */
1140 + /* GXcopy */ 0xcc,
1141 + /* src */
1142 + /* GXandInverted */ 0x22,
1143 + /* NOT src AND dst */
1144 + /* GXnoop */ 0xaa,
1145 + /* dst */
1146 + /* GXxor */ 0x66,
1147 + /* src XOR dst */
1148 + /* GXor */ 0xee,
1149 + /* src OR dst */
1150 + /* GXnor */ 0x11,
1151 + /* NOT src AND NOT dst */
1152 + /* GXequiv */ 0x99,
1153 + /* NOT src XOR dst */
1154 + /* GXinvert */ 0x55,
1155 + /* NOT dst */
1156 + /* GXorReverse */ 0xdd,
1157 + /* src OR NOT dst */
1158 + /* GXcopyInverted */ 0x33,
1159 + /* NOT src */
1160 + /* GXorInverted */ 0xbb,
1161 + /* NOT src OR dst */
1162 + /* GXnand */ 0x77,
1163 + /* NOT src OR NOT dst */
1164 + /* GXset */ 0xff,
1165 + /* 1 */
1166 +};
1167 +
1168 +static int copydx, copydy;
1169 +static ATIScreenInfo *accel_atis;
1170 +static char *accel_mmio;
1171 +
1172 +
1173 +void
1174 +ATIDrawSetup(ScreenPtr pScreen)
1175 +{
1176 + KdScreenPriv(pScreen);
1177 + ATIScreenInfo(pScreenPriv);
1178 + default_sc_bottom_right_u dsbr;
1179 + RING_LOCALS;
1180 +
1181 + dsbr.val = 0;
1182 + dsbr.f.default_sc_right = dsbr.f.default_sc_bottom = W100_MAXINT;
1183 +
1184 + BEGIN_DMA_REG(2);
1185 + OUT_REG(mmDEFAULT_SC_BOTTOM_RIGHT, dsbr.val);
1186 + OUT_REG(mmSRC_SC_BOTTOM_RIGHT, dsbr.val);
1187 + END_DMA_REG();
1188 +}
1189 +
1190 +static void
1191 +ATIWaitMarker(ScreenPtr pScreen, int marker)
1192 +{
1193 + KdScreenPriv(pScreen);
1194 + ATIScreenInfo(pScreenPriv);
1195 +
1196 + ENTER_DRAW(0);
1197 + ATIWaitIdle(atis);
1198 + LEAVE_DRAW(0);
1199 +}
1200 +
1201 +
1202 +#if ATI_TRACE_DRAW
1203 +void
1204 +ATIEnterDraw(PixmapPtr pPix, const char *function)
1205 +{
1206 + if (pPix != NULL) {
1207 + KdScreenPriv(pPix->drawable.pScreen);
1208 + CARD32 offset;
1209 +
1210 + offset = ((CARD8 *) pPix->devPrivate.ptr -
1211 + pScreenPriv->screen->memory_base);
1212 +
1213 + ErrorF("Enter %s 0x%x (%dx%dx%d/%d)\n", function, offset,
1214 + pPix->drawable.width, pPix->drawable.height,
1215 + pPix->drawable.depth, pPix->drawable.bitsPerPixel);
1216 + } else
1217 + ErrorF("Enter %s\n", function);
1218 +}
1219 +
1220 +void
1221 +ATILeaveDraw(PixmapPtr pPix, const char *function)
1222 +{
1223 + if (pPix != NULL) {
1224 + KdScreenPriv(pPix->drawable.pScreen);
1225 + CARD32 offset;
1226 +
1227 + offset = ((CARD8 *) pPix->devPrivate.ptr -
1228 + pScreenPriv->screen->memory_base);
1229 +
1230 + ErrorF("Leave %s 0x%x\n", function, offset);
1231 + } else
1232 + ErrorF("Leave %s\n", function);
1233 +}
1234 +#endif
1235 +
1236 +/* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we
1237 + * require src and dest datatypes to be equal.
1238 + */
1239 +static Bool
1240 +ATIGetDatatypeBpp(int bpp, CARD32 * type)
1241 +{
1242 + switch (bpp) {
1243 + case 8:
1244 + *type = DATATYPE_8BPP;
1245 + return TRUE;
1246 + case 16:
1247 + *type = DATATYPE_ARGB1555;
1248 + return TRUE;
1249 + default:
1250 + ATI_FALLBACK(("Unsupported bpp: %d\n", bpp));
1251 + return FALSE;
1252 + }
1253 +}
1254 +
1255 +
1256 +Bool
1257 +ATIGetPixmapOffsetPitch(PixmapPtr pPix, CARD32 * pitch, CARD32 * offset)
1258 +{
1259 + KdScreenPriv(pPix->drawable.pScreen);
1260 + ATICardInfo(pScreenPriv);
1261 +
1262 + /* XXX this only works for surfaces allocated in external memory */
1263 + *offset = ((CARD8 *) pPix->devPrivate.ptr -
1264 + pScreenPriv->screen->memory_base) + atic->ext_mem_location;
1265 + *pitch = pPix->devKind >> 1;
1266 +
1267 + return TRUE;
1268 +}
1269 +
1270 +
1271 +static Bool
1272 +ATIPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
1273 +{
1274 + KdScreenPriv(pPix->drawable.pScreen);
1275 + ATIScreenInfo(pScreenPriv);
1276 + ATICardInfo(pScreenPriv);
1277 + CARD32 datatype, dst_pitch, dst_offset;
1278 + dp_gui_master_cntl_u gmc;
1279 + dp_cntl_u dp_cntl;
1280 + RING_LOCALS;
1281 +
1282 + accel_atis = atis;
1283 + accel_mmio = atic->reg_base;
1284 +
1285 + if (!ATIGetDatatypeBpp(pPix->drawable.bitsPerPixel, &datatype))
1286 + return FALSE;
1287 + if (!ATIGetPixmapOffsetPitch(pPix, &dst_pitch, &dst_offset))
1288 + return FALSE;
1289 +
1290 + ENTER_DRAW(pPix);
1291 +
1292 + gmc.val = 0;
1293 + gmc.f.gmc_dst_pitch_offset_cntl = 1;
1294 + gmc.f.gmc_dst_clipping = 1;
1295 + gmc.f.gmc_brush_datatype = BRUSH_SOLIDCOLOR;
1296 + gmc.f.gmc_dst_datatype = datatype;
1297 + gmc.f.gmc_src_datatype = datatype;
1298 + gmc.f.gmc_byte_pix_order = 1;
1299 + gmc.f.gmc_rop3 = ATISolidRop[alu];
1300 + gmc.f.gmc_dp_src_source = SOURCE_MEM_RECTANGULAR;
1301 + gmc.f.gmc_clr_cmp_fcn_dis = 1;
1302 + gmc.f.gmc_dp_op = OP_ROP;
1303 +
1304 + dp_cntl.val = 0;
1305 + dp_cntl.f.dst_x_dir = 1;
1306 + dp_cntl.f.dst_y_dir = 1;
1307 +
1308 + BEGIN_DMA_REG(6);
1309 + OUT_REG(mmDST_PITCH, dst_pitch);
1310 + OUT_REG(mmDST_OFFSET, dst_offset);
1311 + OUT_REG(mmDP_GUI_MASTER_CNTL, gmc.val);
1312 + OUT_REG(mmDP_BRUSH_FRGD_CLR, fg);
1313 + OUT_REG(mmDP_WRITE_MSK, pm);
1314 + OUT_REG(mmDP_CNTL, dp_cntl.val);
1315 + END_DMA_REG();
1316 +
1317 + LEAVE_DRAW(pPix);
1318 + return TRUE;
1319 +}
1320 +
1321 +static void
1322 +ATISolid(int x1, int y1, int x2, int y2)
1323 +{
1324 + ENTER_DRAW(0);
1325 + ATIScreenInfo *atis = accel_atis;
1326 + RING_LOCALS;
1327 +
1328 +#ifdef DRAW_USING_PACKET3
1329 + BEGIN_DMA(3);
1330 + OUT_RING(DMA_PACKET3(W100_CCE_PACKET3_PAINT_MULTI, 2));
1331 + OUT_RING((x1 << 16) | y1);
1332 + OUT_RING(((x2 - x1) << 16) | (y2 - y1));
1333 + END_DMA();
1334 +#elif defined DRAW_USING_PACKET0
1335 + BEGIN_DMA(3);
1336 + OUT_RING(DMA_PACKET0(mmDST_Y_X, 2));
1337 + OUT_RING_REG(mmDST_Y_X, (y1 << 16) | x1);
1338 + OUT_RING_REG(mmDST_HEIGHT_WIDTH, ((y2 - y1) << 16) | (x2 - x1));
1339 + END_DMA();
1340 +#else
1341 + BEGIN_DMA_REG(2);
1342 + OUT_REG(mmDST_Y_X, (y1 << 16) | x1);
1343 + OUT_REG(mmDST_HEIGHT_WIDTH, ((y2 - y1) << 16) | (x2 - x1));
1344 + END_DMA_REG();
1345 +#endif
1346 + LEAVE_DRAW(0);
1347 +}
1348 +
1349 +
1350 +static void
1351 +ATIDoneSolid(void)
1352 +{
1353 + ENTER_DRAW(0);
1354 + LEAVE_DRAW(0);
1355 +}
1356 +
1357 +
1358 +static Bool
1359 +ATIPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, int dx, int dy, int alu,
1360 + Pixel pm)
1361 +{
1362 + KdScreenPriv(pDst->drawable.pScreen);
1363 + ATIScreenInfo(pScreenPriv);
1364 + ATICardInfo(pScreenPriv);
1365 + CARD32 datatype, src_pitch, src_offset, dst_pitch, dst_offset;
1366 + dp_gui_master_cntl_u gmc;
1367 + dp_cntl_u dp_cntl;
1368 + dp_datatype_u dpdt;
1369 + RING_LOCALS;
1370 +
1371 + accel_mmio = atic->reg_base;
1372 + copydx = dx;
1373 + copydy = dy;
1374 + accel_atis = atis;
1375 +
1376 + if (!ATIGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype))
1377 + return FALSE;
1378 + if (!ATIGetPixmapOffsetPitch(pSrc, &src_pitch, &src_offset))
1379 + return FALSE;
1380 + if (!ATIGetPixmapOffsetPitch(pDst, &dst_pitch, &dst_offset))
1381 + return FALSE;
1382 +
1383 + ENTER_DRAW(pDst);
1384 +
1385 + gmc.val = 0;
1386 + gmc.f.gmc_src_pitch_offset_cntl = 1;
1387 + gmc.f.gmc_dst_pitch_offset_cntl = 1;
1388 + gmc.f.gmc_src_clipping = 1;
1389 + gmc.f.gmc_dst_clipping = 1;
1390 + gmc.f.gmc_brush_datatype = BRUSH_NONE;
1391 + gmc.f.gmc_dst_datatype = datatype;
1392 + gmc.f.gmc_src_datatype = datatype;
1393 + gmc.f.gmc_byte_pix_order = 1;
1394 + gmc.f.gmc_rop3 = ATIBltRop[alu];
1395 + gmc.f.gmc_dp_src_source = SOURCE_MEM_RECTANGULAR;
1396 + gmc.f.gmc_clr_cmp_fcn_dis = 1;
1397 + gmc.f.gmc_dp_op = OP_ROP;
1398 +
1399 + dp_cntl.val = 0;
1400 + if (dx >= 0)
1401 + dp_cntl.f.dst_x_dir = 1;
1402 + if (dy >= 0)
1403 + dp_cntl.f.dst_y_dir = 1;
1404 +
1405 + dpdt.val = 0;
1406 + dpdt.f.dp_dst_datatype = datatype;
1407 + dpdt.f.dp_src_datatype = datatype;
1408 + dpdt.f.dp_byte_pix_order = 1;
1409 +
1410 + BEGIN_DMA_REG(8);
1411 + OUT_REG(mmSRC_PITCH, src_pitch);
1412 + OUT_REG(mmSRC_OFFSET, src_offset);
1413 + OUT_REG(mmDST_PITCH, dst_pitch);
1414 + OUT_REG(mmDST_OFFSET, dst_offset);
1415 + OUT_REG(mmDP_GUI_MASTER_CNTL, gmc.val);
1416 + OUT_REG(mmDP_WRITE_MSK, pm);
1417 + OUT_REG(mmDP_CNTL, dp_cntl.val);
1418 + OUT_REG(mmDP_DATATYPE, dpdt.val);
1419 + END_DMA_REG();
1420 +
1421 + LEAVE_DRAW(pDst);
1422 + return TRUE;
1423 +}
1424 +
1425 +static void
1426 +ATICopy(int srcX, int srcY, int dstX, int dstY, int w, int h)
1427 +{
1428 + ATIScreenInfo *atis = accel_atis;
1429 + RING_LOCALS;
1430 +
1431 + ENTER_DRAW(0);
1432 +#ifndef DRAW_USING_PACKET3
1433 + if (copydx < 0) {
1434 + srcX += w - 1;
1435 + dstX += w - 1;
1436 + }
1437 + if (copydy < 0) {
1438 + srcY += h - 1;
1439 + dstY += h - 1;
1440 + }
1441 +#endif
1442 +
1443 +#ifdef DRAW_USING_PACKET3
1444 + BEGIN_DMA(4);
1445 + OUT_RING(DMA_PACKET3(W100_CCE_PACKET3_BITBLT_MULTI, 3));
1446 + OUT_RING((srcX << 16) | srcY);
1447 + OUT_RING((dstX << 16) | dstY);
1448 + OUT_RING((w << 16) | h);
1449 + END_DMA();
1450 +#elif defined DRAW_USING_PACKET0
1451 + BEGIN_DMA(4);
1452 + OUT_RING(DMA_PACKET0(mmSRC_Y_X, 3));
1453 + OUT_RING_REG(mmSRC_Y_X, (srcY << 16) | srcX);
1454 + OUT_RING_REG(mmDST_Y_X, (dstY << 16) | dstX);
1455 + OUT_RING_REG(mmDST_HEIGHT_WIDTH, (h << 16) | w);
1456 + END_DMA();
1457 +#else
1458 + BEGIN_DMA_REG(3);
1459 + OUT_REG(mmSRC_Y_X, (srcY << 16) | srcX);
1460 + OUT_REG(mmDST_Y_X, (dstY << 16) | dstX);
1461 + OUT_REG(mmDST_HEIGHT_WIDTH, (h << 16) | w);
1462 + END_DMA_REG();
1463 +#endif
1464 + LEAVE_DRAW(0);
1465 +}
1466 +
1467 +
1468 +static void
1469 +ATIDoneCopy(void)
1470 +{
1471 + ENTER_DRAW(0);
1472 + LEAVE_DRAW(0);
1473 +}
1474 +
1475 +
1476 +Bool
1477 +ATIDrawInit(ScreenPtr pScreen)
1478 +{
1479 + KdScreenPriv(pScreen);
1480 + ATIScreenInfo(pScreenPriv);
1481 +
1482 + ErrorF("Screen: %d/%d depth/bpp\n", pScreenPriv->screen->fb[0].depth,
1483 + pScreenPriv->screen->fb[0].bitsPerPixel);
1484 +
1485 + memset(&atis->kaa, 0, sizeof(KaaScreenInfoRec));
1486 + atis->kaa.waitMarker = ATIWaitMarker;
1487 + atis->kaa.PrepareSolid = ATIPrepareSolid;
1488 + atis->kaa.Solid = ATISolid;
1489 + atis->kaa.DoneSolid = ATIDoneSolid;
1490 + atis->kaa.PrepareCopy = ATIPrepareCopy;
1491 + atis->kaa.Copy = ATICopy;
1492 + atis->kaa.DoneCopy = ATIDoneCopy;
1493 + /* XXX if this flag isn't specified, Kdrive crashes in kaaPixmapUseMemory
1494 + * or kaaPixmapUseScreen. But this is probably caused by some bug in this
1495 + * driver... */
1496 + atis->kaa.flags |= KAA_OFFSCREEN_PIXMAPS;
1497 + if (!kaaDrawInit(pScreen, &atis->kaa))
1498 + return FALSE;
1499 +
1500 + return TRUE;
1501 +}
1502 +
1503 +
1504 +void
1505 +ATIDrawEnable(ScreenPtr pScreen)
1506 +{
1507 + KdScreenPriv(pScreen);
1508 + ATIScreenInfo(pScreenPriv);
1509 +
1510 + ATIDMASetup(pScreen);
1511 + ATIDrawSetup(pScreen);
1512 +
1513 + atis->scratch_area = NULL;
1514 + atis->kaa.PrepareBlend = NULL;
1515 + atis->kaa.Blend = NULL;
1516 + atis->kaa.DoneBlend = NULL;
1517 + atis->kaa.CheckComposite = NULL;
1518 + atis->kaa.PrepareComposite = NULL;
1519 + atis->kaa.Composite = NULL;
1520 + atis->kaa.DoneComposite = NULL;
1521 + atis->kaa.UploadToScreen = NULL;
1522 + atis->kaa.UploadToScratch = NULL;
1523 +
1524 +
1525 + kaaMarkSync(pScreen);
1526 +}
1527 +
1528 +void
1529 +ATIDrawDisable(ScreenPtr pScreen)
1530 +{
1531 + ATIDMATeardown(pScreen);
1532 +}
1533 +
1534 +void
1535 +ATIDrawFini(ScreenPtr pScreen)
1536 +{
1537 + kaaDrawFini(pScreen);
1538 +}
1539 Index: git/hw/kdrive/w100/ati_draw.h
1540 ===================================================================
1541 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1542 +++ git/hw/kdrive/w100/ati_draw.h 2006-09-02 12:12:14.000000000 +0200
1543 @@ -0,0 +1,107 @@
1544 +/*
1545 + * Copyright © 2004 Eric Anholt
1546 + *
1547 + * Permission to use, copy, modify, distribute, and sell this software and its
1548 + * documentation for any purpose is hereby granted without fee, provided that
1549 + * the above copyright notice appear in all copies and that both that
1550 + * copyright notice and this permission notice appear in supporting
1551 + * documentation, and that the name of Eric Anholt not be used in
1552 + * advertising or publicity pertaining to distribution of the software without
1553 + * specific, written prior permission. Eric Anholt makes no
1554 + * representations about the suitability of this software for any purpose. It
1555 + * is provided "as is" without express or implied warranty.
1556 + *
1557 + * ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
1558 + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
1559 + * EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
1560 + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
1561 + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
1562 + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
1563 + * PERFORMANCE OF THIS SOFTWARE.
1564 + */
1565 +/* $Header: /cvs/xserver/xserver/hw/kdrive/ati/ati_draw.h,v 1.9 2005-02-21 03:44:10 anholt Exp $ */
1566 +
1567 +#ifndef _ATI_DRAW_H_
1568 +#define _ATI_DRAW_H_
1569 +
1570 +Bool ATIGetOffsetPitch(ATIScreenInfo *atis, int bpp, CARD32 *pitch_offset,
1571 + int offset, int pitch);
1572 +Bool ATIGetPixmapOffsetPitch(PixmapPtr pPix, CARD32 *pitch, CARD32 *offset);
1573 +
1574 +Bool R128CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
1575 + PicturePtr pDstPicture);
1576 +Bool R128PrepareComposite(int op, PicturePtr pSrcPicture,
1577 + PicturePtr pMaskPicture, PicturePtr pDstPicture, PixmapPtr pSrc,
1578 + PixmapPtr pMask, PixmapPtr pDst);
1579 +void R128Composite(int srcX, int srcY, int maskX, int maskY, int dstX, int dstY,
1580 + int w, int h);
1581 +void R128DoneComposite(void);
1582 +
1583 +Bool R128PrepareTrapezoids(PicturePtr pDstPicture, PixmapPtr pDst);
1584 +void R128Trapezoids(KaaTrapezoid *traps, int ntraps);
1585 +void R128DoneTrapezoids(void);
1586 +
1587 +Bool R100CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
1588 + PicturePtr pDstPicture);
1589 +Bool R100PrepareComposite(int op, PicturePtr pSrcPicture,
1590 + PicturePtr pMaskPicture, PicturePtr pDstPicture, PixmapPtr pSrc,
1591 + PixmapPtr pMask, PixmapPtr pDst);
1592 +Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
1593 + PicturePtr pDstPicture);
1594 +Bool R200PrepareComposite(int op, PicturePtr pSrcPicture,
1595 + PicturePtr pMaskPicture, PicturePtr pDstPicture, PixmapPtr pSrc,
1596 + PixmapPtr pMask, PixmapPtr pDst);
1597 +void RadeonComposite(int srcX, int srcY, int maskX, int maskY, int dstX,
1598 + int dstY, int w, int h);
1599 +void RadeonDoneComposite(void);
1600 +
1601 +Bool RadeonPrepareTrapezoids(PicturePtr pDstPicture, PixmapPtr pDst);
1602 +void RadeonTrapezoids(KaaTrapezoid *traps, int ntraps);
1603 +void RadeonDoneTrapezoids(void);
1604 +
1605 +void RadeonSwitchTo2D(ATIScreenInfo *atis);
1606 +void RadeonSwitchTo3D(ATIScreenInfo *atis);
1607 +void ATIWaitIdle(ATIScreenInfo *atis);
1608 +
1609 +#define ATI_TRACE_FALL 0
1610 +#define ATI_TRACE_DRAW 1
1611 +
1612 +#if ATI_TRACE_FALL
1613 +#define ATI_FALLBACK(x) \
1614 +do { \
1615 + ErrorF("%s: ", __FUNCTION__); \
1616 + ErrorF x; \
1617 + return FALSE; \
1618 +} while (0)
1619 +#else
1620 +#define ATI_FALLBACK(x) return FALSE
1621 +#endif
1622 +
1623 +#if ATI_TRACE_DRAW
1624 +#define ENTER_DRAW(pix) ATIEnterDraw(pix, __FUNCTION__)
1625 +#define LEAVE_DRAW(pix) ATILeaveDraw(pix, __FUNCTION__)
1626 +
1627 +void
1628 +ATIEnterDraw (PixmapPtr pPixmap, const char *function);
1629 +
1630 +void
1631 +ATILeaveDraw (PixmapPtr pPixmap, const char *function);
1632 +#else /* ATI_TRACE */
1633 +#define ENTER_DRAW(pix)
1634 +#define LEAVE_DRAW(pix)
1635 +#endif /* !ATI_TRACE */
1636 +
1637 +#ifndef USE_DMA
1638 +/* if DMA is not going to be used, drawing using PACKET3 or PACKET0 won't
1639 + * be possible */
1640 +#ifdef DRAW_USING_PACKET3
1641 +#undef DRAW_USING_PACKET3
1642 +#endif
1643 +
1644 +#ifdef DRAW_USING_PACKET0
1645 +#undef DRAW_USING_PACKET0
1646 +#endif
1647 +
1648 +#endif /* USE_DMA */
1649 +
1650 +#endif /* _ATI_DRAW_H_ */
1651 Index: git/hw/kdrive/w100/ati.h
1652 ===================================================================
1653 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1654 +++ git/hw/kdrive/w100/ati.h 2006-09-02 12:12:14.000000000 +0200
1655 @@ -0,0 +1,256 @@
1656 +/*
1657 + * $Id: ati.h,v 1.18 2005-06-10 02:14:44 anholt Exp $
1658 + *
1659 + * Copyright © 2003 Eric Anholt
1660 + *
1661 + * Permission to use, copy, modify, distribute, and sell this software and its
1662 + * documentation for any purpose is hereby granted without fee, provided that
1663 + * the above copyright notice appear in all copies and that both that
1664 + * copyright notice and this permission notice appear in supporting
1665 + * documentation, and that the name of Eric Anholt not be used in
1666 + * advertising or publicity pertaining to distribution of the software without
1667 + * specific, written prior permission. Eric Anholt makes no
1668 + * representations about the suitability of this software for any purpose. It
1669 + * is provided "as is" without express or implied warranty.
1670 + *
1671 + * ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
1672 + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
1673 + * EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
1674 + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
1675 + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
1676 + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
1677 + * PERFORMANCE OF THIS SOFTWARE.
1678 + */
1679 +/* $Header: /cvs/xserver/xserver/hw/kdrive/ati/ati.h,v 1.18 2005-06-10 02:14:44 anholt Exp $ */
1680 +
1681 +#ifndef _ATI_H_
1682 +#define _ATI_H_
1683 +
1684 +#ifdef HAVE_CONFIG_H
1685 +#include <kdrive-config.h>
1686 +#endif
1687 +
1688 +#ifdef KDRIVEFBDEV
1689 +#include <fbdev.h>
1690 +#endif
1691 +#ifdef KDRIVEVESA
1692 +#include <vesa.h>
1693 +#endif
1694 +
1695 +#include "kxv.h"
1696 +
1697 +
1698 +#define ATI_MEM_BASE(c) (0x08000000)
1699 +#define ATI_MEM_SIZE(c) (0x01000000)
1700 +#define ATI_REG_BASE(c) (ATI_MEM_BASE(c) + 0x10000) /* the 0x08000000 must be obtained from /proc/iomem, the 0x10000 from ReadCfgReg(cfgREG_BASE) << 16) & 0xff0000 */
1701 +#define ATI_REG_SIZE(c) (0x2000)
1702 +
1703 +#ifdef __powerpc__
1704 +
1705 +static __inline__ void
1706 +MMIO_OUT32(__volatile__ void *base, const unsigned long offset,
1707 + const unsigned int val)
1708 +{
1709 + __asm__ __volatile__(
1710 + "stwbrx %1,%2,%3\n\t"
1711 + "eieio"
1712 + : "=m" (*((volatile unsigned char *)base+offset))
1713 + : "r" (val), "b" (base), "r" (offset));
1714 +}
1715 +
1716 +static __inline__ CARD32
1717 +MMIO_IN32(__volatile__ void *base, const unsigned long offset)
1718 +{
1719 + register unsigned int val;
1720 + __asm__ __volatile__(
1721 + "lwbrx %0,%1,%2\n\t"
1722 + "eieio"
1723 + : "=r" (val)
1724 + : "b" (base), "r" (offset),
1725 + "m" (*((volatile unsigned char *)base+offset)));
1726 + return val;
1727 +}
1728 +
1729 +#else
1730 +
1731 +#define MMIO_OUT32(mmio, a, v) (*(VOL32 *)((mmio) + (a)) = (v))
1732 +#define MMIO_IN32(mmio, a) (*(VOL32 *)((mmio) + (a)))
1733 +
1734 +#endif
1735 +
1736 +#define MMIO_OUT8(mmio, a, v) (*(VOL8 *)((mmio) + (a)) = (v))
1737 +#define MMIO_IN8(mmio, a, v) (*(VOL8 *)((mmio) + (a)))
1738 +
1739 +
1740 +typedef volatile CARD8 VOL8;
1741 +typedef volatile CARD16 VOL16;
1742 +typedef volatile CARD32 VOL32;
1743 +
1744 +struct pci_id_entry {
1745 + CARD16 vendor;
1746 + CARD16 device;
1747 + CARD8 caps;
1748 + char *name;
1749 +};
1750 +
1751 +struct backend_funcs {
1752 + void (*cardfini)(KdCardInfo *);
1753 + void (*scrfini)(KdScreenInfo *);
1754 + Bool (*initScreen)(ScreenPtr);
1755 + Bool (*finishInitScreen)(ScreenPtr pScreen);
1756 + Bool (*createRes)(ScreenPtr);
1757 + void (*preserve)(KdCardInfo *);
1758 + void (*restore)(KdCardInfo *);
1759 + Bool (*dpms)(ScreenPtr, int);
1760 + Bool (*enable)(ScreenPtr);
1761 + void (*disable)(ScreenPtr);
1762 + void (*getColors)(ScreenPtr, int, int, xColorItem *);
1763 + void (*putColors)(ScreenPtr, int, int, xColorItem *);
1764 +#ifdef RANDR
1765 + Bool (*randrSetConfig) (ScreenPtr, Rotation, int, RRScreenSizePtr);
1766 +#endif
1767 +};
1768 +
1769 +typedef struct _ATICardInfo {
1770 + union {
1771 +#ifdef KDRIVEFBDEV
1772 + FbdevPriv fbdev;
1773 +#endif
1774 +#ifdef KDRIVEVESA
1775 + VesaCardPrivRec vesa;
1776 +#endif
1777 + } backend_priv;
1778 + struct backend_funcs backend_funcs;
1779 +
1780 + struct pci_id_entry *pci_id;
1781 + CARD8 *mem_base;
1782 + CARD8 *reg_base;
1783 + CARD32 fb_location;
1784 + CARD32 ext_mem_location;
1785 + Bool use_fbdev, use_vesa;
1786 +} ATICardInfo;
1787 +
1788 +#define getATICardInfo(kd) ((ATICardInfo *) ((kd)->card->driver))
1789 +#define ATICardInfo(kd) ATICardInfo *atic = getATICardInfo(kd)
1790 +
1791 +typedef struct _ATICursor {
1792 + int width, height;
1793 + int xhot, yhot;
1794 +
1795 + Bool has_cursor;
1796 + CursorPtr pCursor;
1797 + Pixel source, mask;
1798 + KdOffscreenArea *area;
1799 +} ATICursor;
1800 +
1801 +typedef struct _ATIPortPriv {
1802 + int brightness;
1803 + int saturation;
1804 + RegionRec clip;
1805 + CARD32 size;
1806 + KdOffscreenArea *off_screen;
1807 + DrawablePtr pDraw;
1808 + PixmapPtr pPixmap;
1809 +
1810 + CARD32 src_offset;
1811 + CARD32 src_pitch;
1812 + CARD8 *src_addr;
1813 +
1814 + int id;
1815 + int src_x1, src_y1, src_x2, src_y2;
1816 + int dst_x1, dst_y1, dst_x2, dst_y2;
1817 + int src_w, src_h, dst_w, dst_h;
1818 +} ATIPortPrivRec, *ATIPortPrivPtr;
1819 +
1820 +typedef struct _ATIScreenInfo {
1821 + union {
1822 +#ifdef KDRIVEFBDEV
1823 + FbdevScrPriv fbdev;
1824 +#endif
1825 +#ifdef KDRIVEVESA
1826 + VesaScreenPrivRec vesa;
1827 +#endif
1828 + } backend_priv;
1829 + KaaScreenInfoRec kaa;
1830 +
1831 + ATICardInfo *atic;
1832 + KdScreenInfo *screen;
1833 +
1834 + int scratch_offset;
1835 + int scratch_next;
1836 + KdOffscreenArea *scratch_area;
1837 +
1838 + ATICursor cursor;
1839 +
1840 + KdVideoAdaptorPtr pAdaptor;
1841 + int num_texture_ports;
1842 +
1843 + Bool using_pio; /* If we use decode DMA packets to MMIO. */
1844 + Bool using_dma; /* If we use non-DRI DMA to submit packets. */
1845 +
1846 + KdOffscreenArea *dma_space; /* For "DMA" from framebuffer. */
1847 + CARD32 *ring_addr; /* Beginning of ring buffer. */
1848 + int ring_write; /* Index of write ptr in ring. */
1849 + int ring_read; /* Index of read ptr in ring. */
1850 + int ring_len;
1851 + int ring_mask;
1852 + int ring_count;
1853 + int ring_free;
1854 +
1855 +
1856 + int mmio_avail;
1857 +} ATIScreenInfo;
1858 +
1859 +#define getATIScreenInfo(kd) ((ATIScreenInfo *) ((kd)->screen->driver))
1860 +#define ATIScreenInfo(kd) ATIScreenInfo *atis = getATIScreenInfo(kd)
1861 +
1862 +typedef union { float f; CARD32 i; } fi_type;
1863 +
1864 +
1865 +/* ati.c */
1866 +Bool
1867 +ATIMap(KdCardInfo *card, ATICardInfo *atic);
1868 +
1869 +void
1870 +ATIUnmap(KdCardInfo *card, ATICardInfo *atic);
1871 +
1872 +/* ati_draw.c */
1873 +void
1874 +ATIDrawSetup(ScreenPtr pScreen);
1875 +
1876 +Bool
1877 +ATIDrawInit(ScreenPtr pScreen);
1878 +
1879 +void
1880 +ATIDrawEnable(ScreenPtr pScreen);
1881 +
1882 +void
1883 +ATIDrawDisable(ScreenPtr pScreen);
1884 +
1885 +void
1886 +ATIDrawFini(ScreenPtr pScreen);
1887 +
1888 +
1889 +/* ati_cursor.c */
1890 +Bool
1891 +ATICursorInit(ScreenPtr pScreen);
1892 +
1893 +void
1894 +ATICursorEnable(ScreenPtr pScreen);
1895 +
1896 +void
1897 +ATICursorDisable(ScreenPtr pScreen);
1898 +
1899 +void
1900 +ATICursorFini(ScreenPtr pScreen);
1901 +
1902 +void
1903 +ATIRecolorCursor(ScreenPtr pScreen, int ndef, xColorItem *pdef);
1904 +
1905 +int
1906 +ATILog2(int val);
1907 +
1908 +
1909 +extern KdCardFuncs ATIFuncs;
1910 +
1911 +#endif /* _ATI_H_ */
1912 Index: git/hw/kdrive/w100/ati_microcode.c
1913 ===================================================================
1914 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1915 +++ git/hw/kdrive/w100/ati_microcode.c 2006-09-02 12:12:14.000000000 +0200
1916 @@ -0,0 +1,412 @@
1917 +/*
1918 + * Copyright © 2006 Alberto Mardegan <mardy@users.sourceforge.net>
1919 + *
1920 + * Permission to use, copy, modify, distribute, and sell this software and its
1921 + * documentation for any purpose is hereby granted without fee, provided that
1922 + * the above copyright notice appear in all copies and that both that
1923 + * copyright notice and this permission notice appear in supporting
1924 + * documentation, and that the name of Alberto Mardegan not be used in
1925 + * advertising or publicity pertaining to distribution of the software without
1926 + * specific, written prior permission. Alberto Mardegan makes no
1927 + * representations about the suitability of this software for any purpose. It
1928 + * is provided "as is" without express or implied warranty.
1929 + *
1930 + * ALBERTO MARDEGAN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
1931 + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
1932 + * EVENT SHALL ALBERTO MARDEGAN BE LIABLE FOR ANY SPECIAL, INDIRECT OR
1933 + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
1934 + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
1935 + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
1936 + * PERFORMANCE OF THIS SOFTWARE.
1937 + */
1938 +
1939 +/* CCE microcode (from ATI) */
1940 +
1941 +#include "ati.h"
1942 +
1943 +
1944 +CARD32 w100_microcode[][2] = {
1945 + {0x21007000, 0x00000000}
1946 + ,
1947 + {0x20007000, 0x00000000}
1948 + ,
1949 + {0x00000098, 0x00000004}
1950 + ,
1951 + {0x0000009c, 0x00000004}
1952 + ,
1953 + {0x66544a49, 0x00000000}
1954 + ,
1955 + {0x49494174, 0x00000000}
1956 + ,
1957 + {0x54517d83, 0x00000000}
1958 + ,
1959 + {0x498d8b64, 0x00000000}
1960 + ,
1961 + {0x49494949, 0x00000000}
1962 + ,
1963 + {0x49b6493c, 0x00000000}
1964 + ,
1965 + {0x49494949, 0x00000000}
1966 + ,
1967 + {0x49494949, 0x00000000}
1968 + ,
1969 + {0x49490d10, 0x00000000}
1970 + ,
1971 + {0x000f0000, 0x00000016}
1972 + ,
1973 + {0x30292027, 0x00000000}
1974 + ,
1975 + {0x00000012, 0x00000004}
1976 + ,
1977 + {0x000f0000, 0x00000016}
1978 + ,
1979 + {0x30292427, 0x00000000}
1980 + ,
1981 + {0x0000730f, 0x00000002}
1982 + , /* mmIDCT_CONTROL */
1983 + {0x00061000, 0x00000002}
1984 + ,
1985 + {0x0000001d, 0x0000001a}
1986 + ,
1987 + {0x00004000, 0x0000001e}
1988 + ,
1989 + {0x00061000, 0x00000002}
1990 + ,
1991 + {0x0000001d, 0x0000001a}
1992 + ,
1993 + {0x00004000, 0x0000001e}
1994 + ,
1995 + {0x00061000, 0x00000002}
1996 + ,
1997 + {0x0000001d, 0x0000001a}
1998 + ,
1999 + {0x00004000, 0x0000001e}
2000 + ,
2001 + {0x00000013, 0x00000004}
2002 + ,
2003 + {0x0003803a, 0x00000002}
2004 + ,
2005 + {0x04006300, 0x00000002}
2006 + , /* mmIDCT_RUNS */
2007 + {0x00000013, 0x00000004}
2008 + ,
2009 + {0x00007300, 0x00000002}
2010 + , /* mmIDCT_RUNS */
2011 + {0x00065000, 0x00000002}
2012 + ,
2013 + {0x00003301, 0x00000002}
2014 + , /* mmIDCT_LEVELS */
2015 + {0x04006301, 0x00000006}
2016 + , /* mmIDCT_LEVELS */
2017 + {0x00007300, 0x00000002}
2018 + , /* mmIDCT_RUNS */
2019 + {0x00007301, 0x00000002}
2020 + , /* mmIDCT_LEVELS */
2021 + {0x00007301, 0x00000006}
2022 + , /* mmIDCT_LEVELS */
2023 + {0x0003803a, 0x00000002}
2024 + ,
2025 + {0x04006300, 0x00000006}
2026 + , /* mmIDCT_RUNS */
2027 + {0x00a05000, 0x00000002}
2028 + ,
2029 + {0x00000039, 0x0000000c}
2030 + ,
2031 + {0x00000000, 0x00000002}
2032 + ,
2033 + {0x00007300, 0x00000002}
2034 + , /* mmIDCT_RUNS */
2035 + {0x00007301, 0x00000002}
2036 + , /* mmIDCT_LEVELS */
2037 + {0x00007301, 0x00000002}
2038 + , /* mmIDCT_LEVELS */
2039 + {0x0060002a, 0x00000004}
2040 + ,
2041 + {0x00007488, 0x00000002}
2042 + , /* mmE2_ARITHMETIC_CNTL */
2043 + {0x0003803b, 0x00000002}
2044 + ,
2045 + {0x00098000, 0x00000002}
2046 + ,
2047 + {0x00200000, 0x00000002}
2048 + ,
2049 + {0x00000039, 0x0000000c}
2050 + ,
2051 + {0x00007465, 0x00000002}
2052 + , /* mmDST_X_Y */
2053 + {0x00007464, 0x00000002}
2054 + , /* mmSRC_X_Y */
2055 + {0x00007478, 0x00000002}
2056 + , /* mmMVC_CNTL_START */
2057 + {0x00600034, 0x00000004}
2058 + ,
2059 + {0x00000000, 0x00000006}
2060 + ,
2061 + {0xffffffff, 0x00000000}
2062 + ,
2063 + {0x00000006, 0x00000000}
2064 + ,
2065 + {0x01605000, 0x00000002}
2066 + ,
2067 + {0x00065000, 0x00000002}
2068 + ,
2069 + {0x00098000, 0x00000002}
2070 + ,
2071 + {0x00061000, 0x00000002}
2072 + ,
2073 + {0x64c0603d, 0x00000004}
2074 + ,
2075 + {0x00080000, 0x00000016}
2076 + ,
2077 + {0x00000000, 0x00000000}
2078 + ,
2079 + {0x0400241d, 0x00000002}
2080 + , /* mmBRUSH_Y_X */
2081 + {0x00007424, 0x00000002}
2082 + , /* mmDST_LINE_START */
2083 + {0x00067425, 0x00000002}
2084 + , /* mmDST_LINE_END */
2085 + {0x04002424, 0x00000002}
2086 + , /* mmDST_LINE_START */
2087 + {0x00067425, 0x00000002}
2088 + , /* mmDST_LINE_END */
2089 + {0x00000046, 0x00000004}
2090 + ,
2091 + {0x00005000, 0x00000000}
2092 + ,
2093 + {0x00061000, 0x00000002}
2094 + ,
2095 + {0x0000740e, 0x00000002}
2096 + , /* mmDST_Y_X */
2097 + {0x00019000, 0x00000002}
2098 + ,
2099 + {0x00011050, 0x00000014}
2100 + ,
2101 + {0x00000050, 0x00000012}
2102 + ,
2103 + {0x0400240f, 0x00000002}
2104 + , /* mmDST_HEIGHT_WIDTH */
2105 + {0x0000504a, 0x00000004}
2106 + ,
2107 + {0x00007465, 0x00000002}
2108 + , /* mmDST_X_Y */
2109 + {0x00007466, 0x00000002}
2110 + , /* mmDST_WIDTH_HEIGHT */
2111 + {0x00000051, 0x00000004}
2112 + ,
2113 + {0x01e65473, 0x00000002}
2114 + , /* mmDP_CNTL_DST_DIR */
2115 + {0x4401b0b9, 0x00000002}
2116 + ,
2117 + {0x01c110b9, 0x00000002}
2118 + ,
2119 + {0x2666705d, 0x00000018}
2120 + ,
2121 + {0x040c2465, 0x00000002}
2122 + , /* mmDST_X_Y */
2123 + {0x0000005d, 0x00000018}
2124 + ,
2125 + {0x04002464, 0x00000002}
2126 + , /* mmSRC_X_Y */
2127 + {0x00007466, 0x00000002}
2128 + , /* mmDST_WIDTH_HEIGHT */
2129 + {0x00000054, 0x00000004}
2130 + ,
2131 + {0x00401060, 0x00000008}
2132 + ,
2133 + {0x00101000, 0x00000002}
2134 + ,
2135 + {0x000d80ff, 0x00000002}
2136 + ,
2137 + {0x00800063, 0x00000008}
2138 + ,
2139 + {0x000f9000, 0x00000002}
2140 + ,
2141 + {0x000e00ff, 0x00000002}
2142 + ,
2143 + {0x00000000, 0x00000006}
2144 + ,
2145 + {0x00000080, 0x00000018}
2146 + ,
2147 + {0x00000054, 0x00000004}
2148 + ,
2149 + {0x00007490, 0x00000002}
2150 + , /* mmDP_SRC_FRGD_CLR */
2151 + {0x00065000, 0x00000002}
2152 + ,
2153 + {0x00009000, 0x00000002}
2154 + ,
2155 + {0x00041000, 0x00000002}
2156 + ,
2157 + {0x0c00340e, 0x00000002}
2158 + , /* mmDST_Y_X */
2159 + {0x00049000, 0x00000002}
2160 + ,
2161 + {0x00051000, 0x00000002}
2162 + ,
2163 + {0x01e784f8, 0x00000002}
2164 + ,
2165 + {0x00200000, 0x00000002}
2166 + ,
2167 + {0x00600073, 0x0000000c}
2168 + ,
2169 + {0x00007463, 0x00000002}
2170 + , /* mmDST_HEIGHT_WIDTH_8 */
2171 + {0x006074f0, 0x00000021}
2172 + , /* mmHOST_DATA0 */
2173 + {0x20007068, 0x00000004}
2174 + ,
2175 + {0x00005068, 0x00000004}
2176 + ,
2177 + {0x00007490, 0x00000002}
2178 + , /* mmDP_SRC_FRGD_CLR */
2179 + {0x00007491, 0x00000002}
2180 + , /* mmDP_SRC_BKGD_CLR */
2181 + {0x0000740e, 0x00000002}
2182 + , /* mmDST_Y_X */
2183 + {0x0000740f, 0x00000002}
2184 + , /* mmDST_HEIGHT_WIDTH */
2185 + {0x00a05000, 0x00000002}
2186 + ,
2187 + {0x00600076, 0x0000000c}
2188 + ,
2189 + {0x006074f0, 0x00000021}
2190 + , /* mmHOST_DATA0 */
2191 + {0x000074f8, 0x00000002}
2192 + , /* mmHOST_DATA_LAST */
2193 + {0x00000076, 0x00000004}
2194 + ,
2195 + {0x000a740e, 0x00000002}
2196 + , /* mmDST_Y_X */
2197 + {0x0020740f, 0x00000002}
2198 + , /* mmDST_HEIGHT_WIDTH */
2199 + {0x00600079, 0x00000004}
2200 + ,
2201 + {0x0000748c, 0x00000002}
2202 + , /* mmCLR_CMP_CNTL */
2203 + {0x0000748d, 0x00000002}
2204 + , /* mmCLR_CMP_CLR_SRC */
2205 + {0x0000748e, 0x00000006}
2206 + , /* mmCLR_CMP_CLR_DST */
2207 + {0x00005000, 0x00000002}
2208 + ,
2209 + {0x00a05000, 0x00000002}
2210 + ,
2211 + {0x00007468, 0x00000002}
2212 + , /* mmDST_HEIGHT_Y */
2213 + {0x00061000, 0x00000002}
2214 + ,
2215 + {0x00000084, 0x0000000c}
2216 + ,
2217 + {0x00058000, 0x00000002}
2218 + ,
2219 + {0x0c607462, 0x00000002}
2220 + , /* mmDST_WIDTH_X */
2221 + {0x00000086, 0x00000004}
2222 + ,
2223 + {0x00600085, 0x00000004}
2224 + ,
2225 + {0x400070ba, 0x00000000}
2226 + ,
2227 + {0x000380ba, 0x00000002}
2228 + ,
2229 + {0x00000093, 0x0000001c}
2230 + ,
2231 + {0x00065095, 0x00000018}
2232 + ,
2233 + {0x0400246f, 0x00000002}
2234 + , /* mmSC_TOP_LEFT */
2235 + {0x00061096, 0x00000018}
2236 + ,
2237 + {0x04007470, 0x00000000}
2238 + , /* mmSC_BOTTOM_RIGHT */
2239 + {0x0000746f, 0x00000002}
2240 + , /* mmSC_TOP_LEFT */
2241 + {0x00007470, 0x00000000}
2242 + , /* mmSC_BOTTOM_RIGHT */
2243 + {0x00090000, 0x00000006}
2244 + ,
2245 + {0x00090000, 0x00000002}
2246 + ,
2247 + {0x000d8002, 0x00000006}
2248 + ,
2249 + {0x01200000, 0x00000002}
2250 + ,
2251 + {0x20077000, 0x00000002}
2252 + ,
2253 + {0x01200000, 0x00000002}
2254 + ,
2255 + {0x20007000, 0x00000002}
2256 + ,
2257 + {0x00061000, 0x00000002}
2258 + ,
2259 + {0x0120741b, 0x00000002}
2260 + , /* mmDP_GUI_MASTER_CNTL */
2261 + {0x8040740a, 0x00000002}
2262 + , /* mmSRC_PITCH_OFFSET */
2263 + {0x8040740b, 0x00000002}
2264 + , /* mmDST_PITCH_OFFSET */
2265 + {0x00110000, 0x00000002}
2266 + ,
2267 + {0x000380ba, 0x00000002}
2268 + ,
2269 + {0x000000aa, 0x0000001c}
2270 + ,
2271 + {0x00061096, 0x00000018}
2272 + ,
2273 + {0x84407471, 0x00000002}
2274 + , /* mmSRC_SC_BOTTOM_RIGHT */
2275 + {0x00061095, 0x00000018}
2276 + ,
2277 + {0x8400746f, 0x00000002}
2278 + , /* mmSC_TOP_LEFT */
2279 + {0x00061096, 0x00000018}
2280 + ,
2281 + {0x84407470, 0x00000002}
2282 + , /* mmSC_BOTTOM_RIGHT */
2283 + {0x000000ad, 0x00000004}
2284 + ,
2285 + {0x80407471, 0x00000002}
2286 + , /* mmSRC_SC_BOTTOM_RIGHT */
2287 + {0x8000746f, 0x00000002}
2288 + , /* mmSC_TOP_LEFT */
2289 + {0x80407470, 0x00000002}
2290 + , /* mmSC_BOTTOM_RIGHT */
2291 + {0x00108000, 0x00000002}
2292 + ,
2293 + {0x01400000, 0x00000002}
2294 + ,
2295 + {0x006000b1, 0x0000000c}
2296 + ,
2297 + {0x20c07000, 0x00000020}
2298 + ,
2299 + {0x000000b3, 0x00000012}
2300 + ,
2301 + {0x00800000, 0x00000006}
2302 + ,
2303 + {0x0080741d, 0x00000006}
2304 + , /* mmBRUSH_Y_X */
2305 + {0x00000000, 0x00000000}
2306 + ,
2307 + {0x00000001, 0x00000000}
2308 + ,
2309 + {0x000380b5, 0x00000002}
2310 + ,
2311 + {0x04002054, 0x00000002}
2312 + , /* mmNQWAIT_UNTIL */
2313 + {0x00005000, 0x00000000}
2314 + ,
2315 + {0x00000000, 0x00000000}
2316 + ,
2317 + {0x00000000, 0x00000000}
2318 + ,
2319 + {0x00000000, 0x00000000}
2320 + ,
2321 + {0x00000000, 0x00000000}
2322 + ,
2323 + {0x00000000, 0x00000000}
2324 + ,
2325 + {0x00000000, 0x00000000}
2326 + ,
2327 + {0x00000000, 0x00000000}
2328 +};
2329 Index: git/hw/kdrive/w100/ati_stub.c
2330 ===================================================================
2331 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2332 +++ git/hw/kdrive/w100/ati_stub.c 2006-09-02 12:12:14.000000000 +0200
2333 @@ -0,0 +1,103 @@
2334 +/*
2335 + * Copyright © 2006 Alberto Mardegan <mardy@users.sourceforge.net>
2336 + *
2337 + * Permission to use, copy, modify, distribute, and sell this software and its
2338 + * documentation for any purpose is hereby granted without fee, provided that
2339 + * the above copyright notice appear in all copies and that both that
2340 + * copyright notice and this permission notice appear in supporting
2341 + * documentation, and that the name of Alberto Mardegan not be used in
2342 + * advertising or publicity pertaining to distribution of the software without
2343 + * specific, written prior permission. Alberto Mardegan makes no
2344 + * representations about the suitability of this software for any purpose. It
2345 + * is provided "as is" without express or implied warranty.
2346 + *
2347 + * ALBERTO MARDEGAN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
2348 + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
2349 + * EVENT SHALL ALBERTO MARDEGAN BE LIABLE FOR ANY SPECIAL, INDIRECT OR
2350 + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
2351 + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
2352 + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
2353 + * PERFORMANCE OF THIS SOFTWARE.
2354 + */
2355 +
2356 +#ifdef HAVE_CONFIG_H
2357 +#include <kdrive-config.h>
2358 +#endif
2359 +#include "ati.h"
2360 +#include "w100_regs.h"
2361 +#include "klinux.h"
2362 +
2363 +extern struct pci_id_entry ati_pci_ids[];
2364 +
2365 +static Bool
2366 +FindW100(CARD16 vendor, CARD16 device, CARD32 count, KdCardAttr * attr)
2367 +{
2368 + char *mmio;
2369 + CARD32 chip_id;
2370 + Bool found = FALSE;
2371 +
2372 + mmio = KdMapDevice(ATI_REG_BASE(0), ATI_REG_SIZE(0));
2373 + KdSetMappedMode((CARD32) mmio, ATI_REG_SIZE(0),
2374 + KD_MAPPED_MODE_REGISTERS);
2375 +
2376 + chip_id = MMIO_IN32(mmio, mmCHIP_ID);
2377 + if ((vendor | (device << 16)) == chip_id) {
2378 + ErrorF("Found Chip ID: %08x\n\n", chip_id);
2379 + attr->deviceID = device;
2380 + attr->vendorID = vendor;
2381 + found = TRUE;
2382 + }
2383 + KdUnmapDevice(mmio, ATI_REG_SIZE(0));
2384 + return found;
2385 +}
2386 +
2387 +
2388 +void
2389 +InitCard(char *name)
2390 +{
2391 + struct pci_id_entry *id;
2392 + KdCardAttr attr;
2393 +
2394 + for (id = ati_pci_ids; id->name != NULL; id++) {
2395 + int j = 0;
2396 + if (FindW100(id->vendor, id->device, j++, &attr))
2397 + KdCardInfoAdd(&ATIFuncs, &attr, 0);
2398 + }
2399 +}
2400 +
2401 +void
2402 +InitOutput(ScreenInfo * pScreenInfo, int argc, char **argv)
2403 +{
2404 + KdInitOutput(pScreenInfo, argc, argv);
2405 +}
2406 +
2407 +void
2408 +InitInput(int argc, char **argv)
2409 +{
2410 + KdInitInput(&LinuxMouseFuncs, &LinuxKeyboardFuncs);
2411 +#ifdef TOUCHSCREEN
2412 + KdAddMouseDriver(&TsFuncs);
2413 +#endif
2414 +}
2415 +
2416 +void
2417 +ddxUseMsg(void)
2418 +{
2419 + KdUseMsg();
2420 +#ifdef KDRIVEVESA
2421 + vesaUseMsg();
2422 +#endif
2423 +}
2424 +
2425 +int
2426 +ddxProcessArgument(int argc, char **argv, int i)
2427 +{
2428 + int ret;
2429 +
2430 +#ifdef KDRIVEVESA
2431 + if (!(ret = vesaProcessArgument(argc, argv, i)))
2432 +#endif
2433 + ret = KdProcessArgument(argc, argv, i);
2434 +
2435 + return ret;
2436 +}
2437 Index: git/hw/kdrive/w100/Makefile.am
2438 ===================================================================
2439 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2440 +++ git/hw/kdrive/w100/Makefile.am 2006-09-02 12:42:38.000000000 +0200
2441 @@ -0,0 +1,56 @@
2442 +if KDRIVEFBDEV
2443 +FBDEV_INCLUDES =-I$(top_srcdir)/hw/kdrive/fbdev
2444 +FBDEV_LIBS = $(top_builddir)/hw/kdrive/fbdev/libfbdev.a
2445 +endif
2446 +
2447 +if KDRIVEVESA
2448 +VESA_INCLUDES = -I$(top_srcdir)/hw/kdrive/vesa
2449 +VESA_LIBS = $(top_builddir)/hw/kdrive/vesa/libvesa.a
2450 +endif
2451 +
2452 +INCLUDES = \
2453 + @KDRIVE_INCS@ \
2454 + $(FBDEV_INCLUDES) \
2455 + $(VESA_INCLUDES) \
2456 + @KDRIVE_CFLAGS@
2457 +
2458 +bin_PROGRAMS = Xw100
2459 +
2460 +if TSLIB
2461 +TSLIB_FLAG = -lts
2462 +endif
2463 +
2464 +noinst_LIBRARIES = libw100.a
2465 +
2466 +libw100_a_SOURCES = \
2467 + ati_cursor.c \
2468 + ati_dma.c \
2469 + ati_dma.h \
2470 + ati_draw.c \
2471 + ati_draw.h \
2472 + ati_microcode.c \
2473 + ati.c \
2474 + ati.h \
2475 + w100_regs.h \
2476 + w100_const.h
2477 +
2478 +Xw100_SOURCES = \
2479 + ati_stub.c
2480 +
2481 +W100_LIBS = \
2482 + libw100.a \
2483 + $(FBDEV_LIBS) \
2484 + $(VESA_LIBS) \
2485 + $(DRI_LIBS) \
2486 + @KDRIVE_LIBS@
2487 +
2488 +Xw100_LDADD = \
2489 + $(W100_LIBS) \
2490 + @XSERVER_LIBS@ \
2491 + $(TSLIB_FLAG)
2492 +
2493 +
2494 +Xw100_DEPENDENCIES = \
2495 + libw100.a \
2496 + $(FBDEV_LIBS) \
2497 + $(VESA_LIBS)
2498 Index: git/hw/kdrive/w100/w100_const.h
2499 ===================================================================
2500 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2501 +++ git/hw/kdrive/w100/w100_const.h 2006-09-02 12:12:14.000000000 +0200
2502 @@ -0,0 +1,25 @@
2503 +#define CSQ_CNTL_MODE_FREERUN 0x8
2504 +
2505 +#define WB_BLOCK_SIZE_A_0 0
2506 +#define WB_BLOCK_SIZE_A_1 1
2507 +#define WB_BLOCK_SIZE_A_2 2
2508 +#define WB_BLOCK_SIZE_A_3 3
2509 +#define WB_BLOCK_SIZE_A_4 4
2510 +
2511 +#define DATATYPE_8BPP 2
2512 +#define DATATYPE_ARGB1555 3
2513 +#define DATATYPE_ARGB4444 5
2514 +
2515 +#define BRUSH_SOLIDCOLOR 13
2516 +#define BRUSH_NONE 15
2517 +
2518 +#define OP_ROP 0
2519 +#define OP_ARITHMETIC 1
2520 +
2521 +#define SOURCE_MEM_RECTANGULAR 2
2522 +
2523 +#define W100_MAXINT 0x1fff
2524 +
2525 +#define W100_CCE_PACKET3_PAINT_MULTI 0xc0001a00
2526 +#define W100_CCE_PACKET3_BITBLT_MULTI 0xc0001b00
2527 +
2528 Index: git/hw/kdrive/w100/w100_regs.h
2529 ===================================================================
2530 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2531 +++ git/hw/kdrive/w100/w100_regs.h 2006-09-02 12:12:14.000000000 +0200
2532 @@ -0,0 +1,3802 @@
2533 +#ifndef _W100_REGS_H_
2534 +#define _W100_REGS_H_
2535 +
2536 +/* Block CIF Start: */
2537 +#define mmCHIP_ID 0x0000
2538 +#define mmREVISION_ID 0x0004
2539 +#define mmWRAP_BUF_A 0x0008
2540 +#define mmWRAP_BUF_B 0x000C
2541 +#define mmWRAP_TOP_DIR 0x0010
2542 +#define mmWRAP_START_DIR 0x0014
2543 +#define mmCIF_CNTL 0x0018
2544 +#define mmCFGREG_BASE 0x001C
2545 +#define mmCIF_IO 0x0020
2546 +#define mmCIF_READ_DBG 0x0024
2547 +#define mmCIF_WRITE_DBG 0x0028
2548 +#define cfgIND_ADDR_A_0 0x0000
2549 +#define cfgIND_ADDR_A_1 0x0001
2550 +#define cfgIND_ADDR_A_2 0x0002
2551 +#define cfgIND_DATA_A 0x0003
2552 +#define cfgREG_BASE 0x0004
2553 +#define cfgINTF_CNTL 0x0005
2554 +#define cfgSTATUS 0x0006
2555 +#define cfgCPU_DEFAULTS 0x0007
2556 +#define cfgIND_ADDR_B_0 0x0008
2557 +#define cfgIND_ADDR_B_1 0x0009
2558 +#define cfgIND_ADDR_B_2 0x000A
2559 +#define cfgIND_DATA_B 0x000B
2560 +#define cfgPM4_RPTR 0x000C
2561 +#define cfgSCRATCH 0x000D
2562 +#define cfgPM4_WRPTR_0 0x000E
2563 +#define cfgPM4_WRPTR_1 0x000F
2564 +/* Block CIF End: */
2565 +
2566 +/* Block CP Start: */
2567 +#define mmCP_RB_CNTL 0x0210
2568 +#define mmCP_RB_BASE 0x0214
2569 +#define mmCP_RB_RPTR_ADDR 0x0218
2570 +#define mmCP_RB_RPTR 0x021C
2571 +#define mmCP_RB_RPTR_WR 0x02F8
2572 +#define mmCP_RB_WPTR 0x0220
2573 +#define mmCP_IB_BASE 0x0228
2574 +#define mmCP_IB_BUFSZ 0x022C
2575 +#define mmCP_CSQ_CNTL 0x0230
2576 +#define mmCP_CSQ_APER_PRIMARY 0x0300
2577 +#define mmCP_CSQ_APER_INDIRECT 0x0340
2578 +#define mmCP_ME_CNTL 0x0240
2579 +#define mmCP_ME_RAM_ADDR 0x0244
2580 +#define mmCP_ME_RAM_RADDR 0x0248
2581 +#define mmCP_ME_RAM_DATAH 0x024C
2582 +#define mmCP_ME_RAM_DATAL 0x0250
2583 +#define mmCP_DEBUG 0x025C
2584 +#define mmSCRATCH_REG0 0x0260
2585 +#define mmSCRATCH_REG1 0x0264
2586 +#define mmSCRATCH_REG2 0x0268
2587 +#define mmSCRATCH_REG3 0x026C
2588 +#define mmSCRATCH_REG4 0x0270
2589 +#define mmSCRATCH_REG5 0x0274
2590 +#define mmSCRATCH_UMSK 0x0280
2591 +#define mmSCRATCH_ADDR 0x0284
2592 +#define mmCP_CSQ_ADDR 0x02E4
2593 +#define mmCP_CSQ_DATA 0x02E8
2594 +#define mmCP_CSQ_STAT 0x02EC
2595 +#define mmCP_STAT 0x02F0
2596 +#define mmGEN_INT_CNTL 0x0200
2597 +#define mmGEN_INT_STATUS 0x0204
2598 +/* Block CP End: */
2599 +
2600 +/* Block DISPLAY Start: */
2601 +#define mmLCD_FORMAT 0x0410
2602 +#define mmGRAPHIC_CTRL 0x0414
2603 +#define mmGRAPHIC_OFFSET 0x0418
2604 +#define mmGRAPHIC_PITCH 0x041C
2605 +#define mmCRTC_TOTAL 0x0420
2606 +#define mmACTIVE_H_DISP 0x0424
2607 +#define mmACTIVE_V_DISP 0x0428
2608 +#define mmGRAPHIC_H_DISP 0x042C
2609 +#define mmGRAPHIC_V_DISP 0x0430
2610 +#define mmVIDEO_CTRL 0x0434
2611 +#define mmGRAPHIC_KEY 0x0438
2612 +#define mmVIDEO_Y_OFFSET 0x043C
2613 +#define mmVIDEO_Y_PITCH 0x0440
2614 +#define mmVIDEO_U_OFFSET 0x0444
2615 +#define mmVIDEO_U_PITCH 0x0448
2616 +#define mmVIDEO_V_OFFSET 0x044C
2617 +#define mmVIDEO_V_PITCH 0x0450
2618 +#define mmVIDEO_H_POS 0x0454
2619 +#define mmVIDEO_V_POS 0x0458
2620 +#define mmBRIGHTNESS_CNTL 0x045C
2621 +#define mmCURSOR1_OFFSET 0x0460
2622 +#define mmCURSOR1_H_POS 0x0464
2623 +#define mmCURSOR1_V_POS 0x0468
2624 +#define mmCURSOR1_COLOR0 0x046C
2625 +#define mmCURSOR1_COLOR1 0x0470
2626 +#define mmCURSOR2_OFFSET 0x0474
2627 +#define mmCURSOR2_H_POS 0x0478
2628 +#define mmCURSOR2_V_POS 0x047C
2629 +#define mmCURSOR2_COLOR0 0x0480
2630 +#define mmCURSOR2_COLOR1 0x0484
2631 +#define mmDISP_INT_CNTL 0x0488
2632 +#define mmCRTC_SS 0x048C
2633 +#define mmCRTC_LS 0x0490
2634 +#define mmCRTC_REV 0x0494
2635 +#define mmCRTC_DCLK 0x049C
2636 +#define mmCRTC_GS 0x04A0
2637 +#define mmCRTC_VPOS_GS 0x04A4
2638 +#define mmCRTC_GCLK 0x04A8
2639 +#define mmCRTC_GOE 0x04AC
2640 +#define mmCRTC_FRAME 0x04B0
2641 +#define mmCRTC_FRAME_VPOS 0x04B4
2642 +#define mmGPIO_DATA 0x04B8
2643 +#define mmGPIO_CNTL1 0x04BC
2644 +#define mmGPIO_CNTL2 0x04C0
2645 +#define mmLCDD_CNTL1 0x04C4
2646 +#define mmLCDD_CNTL2 0x04C8
2647 +#define mmGENLCD_CNTL1 0x04CC
2648 +#define mmGENLCD_CNTL2 0x04D0
2649 +#define mmDISP_DEBUG 0x04D4
2650 +#define mmDISP_DB_BUF_CNTL 0x04D8
2651 +#define mmDISP_CRC_SIG 0x04DC
2652 +#define mmCRTC_DEFAULT_COUNT 0x04E0
2653 +#define mmLCD_BACKGROUND_COLOR 0x04E4
2654 +#define mmCRTC_PS2 0x04E8
2655 +#define mmCRTC_PS2_VPOS 0x04EC
2656 +#define mmCRTC_PS1_ACTIVE 0x04F0
2657 +#define mmCRTC_PS1_NACTIVE 0x04F4
2658 +#define mmCRTC_GCLK_EXT 0x04F8
2659 +#define mmCRTC_ALW 0x04FC
2660 +#define mmCRTC_ALW_VPOS 0x0500
2661 +#define mmCRTC_PSK 0x0504
2662 +#define mmCRTC_PSK_HPOS 0x0508
2663 +#define mmCRTC_CV4_START 0x050C
2664 +#define mmCRTC_CV4_END 0x0510
2665 +#define mmCRTC_CV4_HPOS 0x0514
2666 +#define mmCRTC_ECK 0x051C
2667 +#define mmREFRESH_CNTL 0x0520
2668 +#define mmGENLCD_CNTL3 0x0524
2669 +#define mmGPIO_DATA2 0x0528
2670 +#define mmGPIO_CNTL3 0x052C
2671 +#define mmGPIO_CNTL4 0x0530
2672 +#define mmCHIP_STRAP 0x0534
2673 +#define mmDISP_DEBUG2 0x0538
2674 +#define mmDEBUG_BUS_CNTL 0x053C
2675 +#define mmGAMMA_VALUE1 0x0540
2676 +#define mmGAMMA_VALUE2 0x0544
2677 +#define mmGAMMA_SLOPE 0x0548
2678 +#define mmGEN_STATUS 0x054C
2679 +#define mmHW_INT 0x0550
2680 +/* Block DISPLAY End: */
2681 +
2682 +/* Block GFX Start: */
2683 +#define mmDST_OFFSET 0x1004
2684 +#define mmDST_PITCH 0x1008
2685 +#define mmDST_PITCH_OFFSET 0x102C
2686 +#define mmDST_X 0x101C
2687 +#define mmDST_Y 0x1020
2688 +#define mmDST_X_Y 0x1194
2689 +#define mmDST_Y_X 0x1038
2690 +#define mmDST_WIDTH 0x100C
2691 +#define mmDST_HEIGHT 0x1010
2692 +#define mmDST_WIDTH_HEIGHT 0x1198
2693 +#define mmDST_HEIGHT_WIDTH 0x103C
2694 +#define mmDST_HEIGHT_WIDTH_8 0x118C
2695 +#define mmDST_HEIGHT_Y 0x11A0
2696 +#define mmDST_WIDTH_X 0x1188
2697 +#define mmDST_WIDTH_X_INCY 0x119C
2698 +#define mmDST_LINE_START 0x1090
2699 +#define mmDST_LINE_END 0x1094
2700 +#define mmBRUSH_OFFSET 0x108C
2701 +#define mmBRUSH_Y_X 0x1074
2702 +#define mmDP_BRUSH_FRGD_CLR 0x107C
2703 +#define mmDP_BRUSH_BKGD_CLR 0x1078
2704 +#define mmSRC2_OFFSET 0x1060
2705 +#define mmSRC2_PITCH 0x1064
2706 +#define mmSRC2_PITCH_OFFSET 0x1068
2707 +#define mmSRC2_X 0x1050
2708 +#define mmSRC2_Y 0x1054
2709 +#define mmSRC2_X_Y 0x1058
2710 +#define mmSRC2_WIDTH 0x1080
2711 +#define mmSRC2_HEIGHT 0x1084
2712 +#define mmSRC2_INC 0x1088
2713 +#define mmSRC_OFFSET 0x11AC
2714 +#define mmSRC_PITCH 0x11B0
2715 +#define mmSRC_PITCH_OFFSET 0x1028
2716 +#define mmSRC_X 0x1014
2717 +#define mmSRC_Y 0x1018
2718 +#define mmSRC_X_Y 0x1190
2719 +#define mmSRC_Y_X 0x1034
2720 +#define mmSRC_WIDTH 0x1040
2721 +#define mmSRC_HEIGHT 0x1044
2722 +#define mmSRC_INC 0x1048
2723 +#define mmHOST_DATA0 0x13C0
2724 +#define mmHOST_DATA1 0x13C4
2725 +#define mmHOST_DATA2 0x13C8
2726 +#define mmHOST_DATA3 0x13CC
2727 +#define mmHOST_DATA4 0x13D0
2728 +#define mmHOST_DATA5 0x13D4
2729 +#define mmHOST_DATA6 0x13D8
2730 +#define mmHOST_DATA7 0x13DC
2731 +#define mmHOST_DATA_LAST 0x13E0
2732 +#define mmDP_SRC_FRGD_CLR 0x1240
2733 +#define mmDP_SRC_BKGD_CLR 0x1244
2734 +#define mmSC_LEFT 0x1140
2735 +#define mmSC_RIGHT 0x1144
2736 +#define mmSC_TOP 0x1148
2737 +#define mmSC_BOTTOM 0x114C
2738 +#define mmSRC_SC_RIGHT 0x1154
2739 +#define mmSRC_SC_BOTTOM 0x115C
2740 +#define mmDP_CNTL 0x11C8
2741 +#define mmDP_CNTL_DST_DIR 0x11CC
2742 +#define mmDP_DATATYPE 0x12C4
2743 +#define mmDP_MIX 0x12C8
2744 +#define mmDP_WRITE_MSK 0x12CC
2745 +#define mmCLR_CMP_CLR_SRC 0x1234
2746 +#define mmCLR_CMP_CLR_DST 0x1238
2747 +#define mmCLR_CMP_CNTL 0x1230
2748 +#define mmCLR_CMP_MSK 0x123C
2749 +#define mmDEFAULT_PITCH_OFFSET 0x10A0
2750 +#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
2751 +#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
2752 +#define mmREF1_PITCH_OFFSET 0x10B8
2753 +#define mmREF2_PITCH_OFFSET 0x10BC
2754 +#define mmREF3_PITCH_OFFSET 0x10C0
2755 +#define mmREF4_PITCH_OFFSET 0x10C4
2756 +#define mmREF5_PITCH_OFFSET 0x10C8
2757 +#define mmREF6_PITCH_OFFSET 0x10CC
2758 +#define mmDP_GUI_MASTER_CNTL 0x106C
2759 +#define mmSC_TOP_LEFT 0x11BC
2760 +#define mmSC_BOTTOM_RIGHT 0x11C0
2761 +#define mmSRC_SC_BOTTOM_RIGHT 0x11C4
2762 +#define mmGLOBAL_ALPHA 0x1210
2763 +#define mmFILTER_COEF 0x1214
2764 +#define mmMVC_CNTL_START 0x11E0
2765 +#define mmE2_ARITHMETIC_CNTL 0x1220
2766 +#define mmDEBUG0 0x1280
2767 +#define mmDEBUG1 0x1284
2768 +#define mmDEBUG2 0x1288
2769 +#define mmDEBUG3 0x128C
2770 +#define mmDEBUG4 0x1290
2771 +#define mmDEBUG5 0x1294
2772 +#define mmDEBUG6 0x1298
2773 +#define mmDEBUG7 0x129C
2774 +#define mmDEBUG8 0x12A0
2775 +#define mmDEBUG9 0x12A4
2776 +#define mmDEBUG10 0x12A8
2777 +#define mmDEBUG11 0x12AC
2778 +#define mmDEBUG12 0x12B0
2779 +#define mmDEBUG13 0x12B4
2780 +#define mmDEBUG14 0x12B8
2781 +#define mmDEBUG15 0x12BC
2782 +#define mmENG_CNTL 0x13E8
2783 +#define mmENG_PERF_CNT 0x13F0
2784 +/* Block GFX End: */
2785 +
2786 +/* Block IDCT Start: */
2787 +#define mmIDCT_RUNS 0x0C00
2788 +#define mmIDCT_LEVELS 0x0C04
2789 +#define mmIDCT_CONTROL 0x0C3C
2790 +#define mmIDCT_AUTH_CONTROL 0x0C08
2791 +#define mmIDCT_AUTH 0x0C0C
2792 +/* Block IDCT End: */
2793 +
2794 +/* Block MC Start: */
2795 +#define mmMEM_CNTL 0x0180
2796 +#define mmMEM_ARB 0x0184
2797 +#define mmMC_FB_LOCATION 0x0188
2798 +#define mmMEM_EXT_CNTL 0x018C
2799 +#define mmMC_EXT_MEM_LOCATION 0x0190
2800 +#define mmMEM_EXT_TIMING_CNTL 0x0194
2801 +#define mmMEM_SDRAM_MODE_REG 0x0198
2802 +#define mmMEM_IO_CNTL 0x019C
2803 +#define mmMC_DEBUG 0x01A0
2804 +#define mmMC_BIST_CTRL 0x01A4
2805 +#define mmMC_BIST_COLLAR_READ 0x01A8
2806 +#define mmTC_MISMATCH 0x01AC
2807 +#define mmMC_PERF_MON_CNTL 0x01B0
2808 +#define mmMC_PERF_COUNTERS 0x01B4
2809 +/* Block MC End: */
2810 +
2811 +/* Block RBBM Start: */
2812 +#define mmWAIT_UNTIL 0x1400
2813 +#define mmISYNC_CNTL 0x1404
2814 +#define mmRBBM_GUICNTL 0x1408
2815 +#define mmRBBM_STATUS 0x0140
2816 +#define mmRBBM_STATUS_alt_1 0x140C
2817 +#define mmRBBM_CNTL 0x0144
2818 +#define mmRBBM_SOFT_RESET 0x0148
2819 +#define mmNQWAIT_UNTIL 0x0150
2820 +#define mmRBBM_DEBUG 0x016C
2821 +#define mmRBBM_CMDFIFO_ADDR 0x0170
2822 +#define mmRBBM_CMDFIFO_DATAL 0x0174
2823 +#define mmRBBM_CMDFIFO_DATAH 0x0178
2824 +#define mmRBBM_CMDFIFO_STAT 0x017C
2825 +/* Block RBBM End: */
2826 +
2827 +/* Block CG Start: */
2828 +#define mmCLK_PIN_CNTL 0x0080
2829 +#define mmPLL_REF_FB_DIV 0x0084
2830 +#define mmPLL_CNTL 0x0088
2831 +#define mmSCLK_CNTL 0x008C
2832 +#define mmPCLK_CNTL 0x0090
2833 +#define mmCLK_TEST_CNTL 0x0094
2834 +#define mmPWRMGT_CNTL 0x0098
2835 +#define mmPWRMGT_STATUS 0x009C
2836 +/* Block CG End: */
2837 +
2838 +
2839 +/* data structure definitions */
2840 +
2841 +typedef struct _chip_id_t {
2842 + unsigned long vendor_id : 16;
2843 + unsigned long device_id : 16;
2844 + } chip_id_t;
2845 +
2846 +typedef union {
2847 + unsigned long val : 32;
2848 + chip_id_t f;
2849 +} chip_id_u;
2850 +
2851 +typedef struct _revision_id_t {
2852 + unsigned long minor_rev_id : 4;
2853 + unsigned long major_rev_id : 4;
2854 + unsigned long : 24;
2855 + } revision_id_t;
2856 +
2857 +typedef union {
2858 + unsigned long val : 32;
2859 + revision_id_t f;
2860 +} revision_id_u;
2861 +
2862 +typedef struct _wrap_buf_a_t {
2863 + unsigned long offset_addr_a : 24;
2864 + unsigned long block_size_a : 3;
2865 + unsigned long : 5;
2866 + } wrap_buf_a_t;
2867 +
2868 +typedef union {
2869 + unsigned long val : 32;
2870 + wrap_buf_a_t f;
2871 +} wrap_buf_a_u;
2872 +
2873 +typedef struct _wrap_buf_b_t {
2874 + unsigned long offset_addr_b : 24;
2875 + unsigned long block_size_b : 3;
2876 + unsigned long : 5;
2877 + } wrap_buf_b_t;
2878 +
2879 +typedef union {
2880 + unsigned long val : 32;
2881 + wrap_buf_b_t f;
2882 +} wrap_buf_b_u;
2883 +
2884 +typedef struct _wrap_top_dir_t {
2885 + unsigned long top_addr : 23;
2886 + unsigned long : 9;
2887 + } wrap_top_dir_t;
2888 +
2889 +typedef union {
2890 + unsigned long val : 32;
2891 + wrap_top_dir_t f;
2892 +} wrap_top_dir_u;
2893 +
2894 +typedef struct _wrap_start_dir_t {
2895 + unsigned long start_addr : 23;
2896 + unsigned long : 9;
2897 + } wrap_start_dir_t;
2898 +
2899 +typedef union {
2900 + unsigned long val : 32;
2901 + wrap_start_dir_t f;
2902 +} wrap_start_dir_u;
2903 +
2904 +typedef struct _cif_cntl_t {
2905 + unsigned long swap_reg : 2;
2906 + unsigned long swap_fbuf_1 : 2;
2907 + unsigned long swap_fbuf_2 : 2;
2908 + unsigned long swap_fbuf_3 : 2;
2909 + unsigned long pmi_int_disable : 1;
2910 + unsigned long pmi_schmen_disable : 1;
2911 + unsigned long intb_oe : 1;
2912 + unsigned long en_wait_to_compensate_dq_prop_dly : 1;
2913 + unsigned long compensate_wait_rd_size : 2;
2914 + unsigned long wait_asserted_timeout_val : 2;
2915 + unsigned long wait_masked_val : 2;
2916 + unsigned long en_wait_timeout : 1;
2917 + unsigned long en_one_clk_setup_before_wait : 1;
2918 + unsigned long interrupt_active_high : 1;
2919 + unsigned long en_overwrite_straps : 1;
2920 + unsigned long strap_wait_active_hi : 1;
2921 + unsigned long lat_busy_count : 2;
2922 + unsigned long lat_rd_pm4_sclk_busy : 1;
2923 + unsigned long dis_system_bits : 1;
2924 + unsigned long dis_mr : 1;
2925 + unsigned long cif_spare_1 : 4;
2926 + } cif_cntl_t;
2927 +
2928 +typedef union {
2929 + unsigned long val : 32;
2930 + cif_cntl_t f;
2931 +} cif_cntl_u;
2932 +
2933 +typedef struct _cfgreg_base_t {
2934 + unsigned long cfgreg_base : 24;
2935 + unsigned long : 8;
2936 + } cfgreg_base_t;
2937 +
2938 +typedef union {
2939 + unsigned long val : 32;
2940 + cfgreg_base_t f;
2941 +} cfgreg_base_u;
2942 +
2943 +typedef struct _cif_io_t {
2944 + unsigned long dq_srp : 1;
2945 + unsigned long dq_srn : 1;
2946 + unsigned long dq_sp : 4;
2947 + unsigned long dq_sn : 4;
2948 + unsigned long waitb_srp : 1;
2949 + unsigned long waitb_srn : 1;
2950 + unsigned long waitb_sp : 4;
2951 + unsigned long waitb_sn : 4;
2952 + unsigned long intb_srp : 1;
2953 + unsigned long intb_srn : 1;
2954 + unsigned long intb_sp : 4;
2955 + unsigned long intb_sn : 4;
2956 + unsigned long : 2;
2957 + } cif_io_t;
2958 +
2959 +typedef union {
2960 + unsigned long val : 32;
2961 + cif_io_t f;
2962 +} cif_io_u;
2963 +
2964 +typedef struct _cif_read_dbg_t {
2965 + unsigned long unpacker_pre_fetch_trig_gen : 2;
2966 + unsigned long dly_second_rd_fetch_trig : 1;
2967 + unsigned long rst_rd_burst_id : 1;
2968 + unsigned long dis_rd_burst_id : 1;
2969 + unsigned long en_block_rd_when_packer_is_not_emp : 1;
2970 + unsigned long dis_pre_fetch_cntl_sm : 1;
2971 + unsigned long rbbm_chrncy_dis : 1;
2972 + unsigned long rbbm_rd_after_wr_lat : 2;
2973 + unsigned long dis_be_during_rd : 1;
2974 + unsigned long one_clk_invalidate_pulse : 1;
2975 + unsigned long dis_chnl_priority : 1;
2976 + unsigned long rst_read_path_a_pls : 1;
2977 + unsigned long rst_read_path_b_pls : 1;
2978 + unsigned long dis_reg_rd_fetch_trig : 1;
2979 + unsigned long dis_rd_fetch_trig_from_ind_addr : 1;
2980 + unsigned long dis_rd_same_byte_to_trig_fetch : 1;
2981 + unsigned long dis_dir_wrap : 1;
2982 + unsigned long dis_ring_buf_to_force_dec : 1;
2983 + unsigned long dis_addr_comp_in_16bit : 1;
2984 + unsigned long clr_w : 1;
2985 + unsigned long err_rd_tag_is_3 : 1;
2986 + unsigned long err_load_when_ful_a : 1;
2987 + unsigned long err_load_when_ful_b : 1;
2988 + unsigned long : 7;
2989 + } cif_read_dbg_t;
2990 +
2991 +typedef union {
2992 + unsigned long val : 32;
2993 + cif_read_dbg_t f;
2994 +} cif_read_dbg_u;
2995 +
2996 +typedef struct _cif_write_dbg_t {
2997 + unsigned long packer_timeout_count : 2;
2998 + unsigned long en_upper_load_cond : 1;
2999 + unsigned long en_chnl_change_cond : 1;
3000 + unsigned long dis_addr_comp_cond : 1;
3001 + unsigned long dis_load_same_byte_addr_cond : 1;
3002 + unsigned long dis_timeout_cond : 1;
3003 + unsigned long dis_timeout_during_rbbm : 1;
3004 + unsigned long dis_packer_ful_during_rbbm_timeout : 1;
3005 + unsigned long en_dword_split_to_rbbm : 1;
3006 + unsigned long en_dummy_val : 1;
3007 + unsigned long dummy_val_sel : 1;
3008 + unsigned long mask_pm4_wrptr_dec : 1;
3009 + unsigned long dis_mc_clean_cond : 1;
3010 + unsigned long err_two_reqi_during_ful : 1;
3011 + unsigned long err_reqi_during_idle_clk : 1;
3012 + unsigned long err_global : 1;
3013 + unsigned long en_wr_buf_dbg_load : 1;
3014 + unsigned long en_wr_buf_dbg_path : 1;
3015 + unsigned long sel_wr_buf_byte : 3;
3016 + unsigned long dis_rd_flush_wr : 1;
3017 + unsigned long dis_packer_ful_cond : 1;
3018 + unsigned long dis_invalidate_by_ops_chnl : 1;
3019 + unsigned long en_halt_when_reqi_err : 1;
3020 + unsigned long cif_spare_2 : 5;
3021 + unsigned long : 1;
3022 + } cif_write_dbg_t;
3023 +
3024 +typedef union {
3025 + unsigned long val : 32;
3026 + cif_write_dbg_t f;
3027 +} cif_write_dbg_u;
3028 +
3029 +typedef struct _ind_addr_a_0_t {
3030 + unsigned char ind_addr_a_0 : 8;
3031 + } ind_addr_a_0_t;
3032 +
3033 +typedef union {
3034 + unsigned char val : 8;
3035 + ind_addr_a_0_t f;
3036 +} ind_addr_a_0_u;
3037 +
3038 +typedef struct _ind_addr_a_1_t {
3039 + unsigned char ind_addr_a_1 : 8;
3040 + } ind_addr_a_1_t;
3041 +
3042 +typedef union {
3043 + unsigned char val : 8;
3044 + ind_addr_a_1_t f;
3045 +} ind_addr_a_1_u;
3046 +
3047 +typedef struct _ind_addr_a_2_t {
3048 + unsigned char ind_addr_a_2 : 8;
3049 + } ind_addr_a_2_t;
3050 +
3051 +typedef union {
3052 + unsigned char val : 8;
3053 + ind_addr_a_2_t f;
3054 +} ind_addr_a_2_u;
3055 +
3056 +typedef struct _ind_data_a_t {
3057 + unsigned char ind_data_a : 8;
3058 + } ind_data_a_t;
3059 +
3060 +typedef union {
3061 + unsigned char val : 8;
3062 + ind_data_a_t f;
3063 +} ind_data_a_u;
3064 +
3065 +typedef struct _reg_base_t {
3066 + unsigned char reg_base : 8;
3067 + } reg_base_t;
3068 +
3069 +typedef union {
3070 + unsigned char val : 8;
3071 + reg_base_t f;
3072 +} reg_base_u;
3073 +
3074 +typedef struct _intf_cntl_t {
3075 + unsigned char ad_inc_a : 1;
3076 + unsigned char ring_buf_a : 1;
3077 + unsigned char rd_fetch_trigger_a : 1;
3078 + unsigned char rd_data_rdy_a : 1;
3079 + unsigned char ad_inc_b : 1;
3080 + unsigned char ring_buf_b : 1;
3081 + unsigned char rd_fetch_trigger_b : 1;
3082 + unsigned char rd_data_rdy_b : 1;
3083 + } intf_cntl_t;
3084 +
3085 +typedef union {
3086 + unsigned char val : 8;
3087 + intf_cntl_t f;
3088 +} intf_cntl_u;
3089 +
3090 +typedef struct _status_t {
3091 + unsigned char wr_fifo_available_space : 2;
3092 + unsigned char fbuf_wr_pipe_emp : 1;
3093 + unsigned char soft_reset : 1;
3094 + unsigned char system_pwm_mode : 2;
3095 + unsigned char mem_access_dis : 1;
3096 + unsigned char en_pre_fetch : 1;
3097 + } status_t;
3098 +
3099 +typedef union {
3100 + unsigned char val : 8;
3101 + status_t f;
3102 +} status_u;
3103 +
3104 +typedef struct _cpu_defaults_t {
3105 + unsigned char unpack_rd_data : 1;
3106 + unsigned char access_ind_addr_a : 1;
3107 + unsigned char access_ind_addr_b : 1;
3108 + unsigned char access_scratch_reg : 1;
3109 + unsigned char pack_wr_data : 1;
3110 + unsigned char transition_size : 1;
3111 + unsigned char en_read_buf_mode : 1;
3112 + unsigned char rd_fetch_scratch : 1;
3113 + } cpu_defaults_t;
3114 +
3115 +typedef union {
3116 + unsigned char val : 8;
3117 + cpu_defaults_t f;
3118 +} cpu_defaults_u;
3119 +
3120 +typedef struct _ind_addr_b_0_t {
3121 + unsigned char ind_addr_b_0 : 8;
3122 + } ind_addr_b_0_t;
3123 +
3124 +typedef union {
3125 + unsigned char val : 8;
3126 + ind_addr_b_0_t f;
3127 +} ind_addr_b_0_u;
3128 +
3129 +typedef struct _ind_addr_b_1_t {
3130 + unsigned char ind_addr_b_1 : 8;
3131 + } ind_addr_b_1_t;
3132 +
3133 +typedef union {
3134 + unsigned char val : 8;
3135 + ind_addr_b_1_t f;
3136 +} ind_addr_b_1_u;
3137 +
3138 +typedef struct _ind_addr_b_2_t {
3139 + unsigned char ind_addr_b_2 : 8;
3140 + } ind_addr_b_2_t;
3141 +
3142 +typedef union {
3143 + unsigned char val : 8;
3144 + ind_addr_b_2_t f;
3145 +} ind_addr_b_2_u;
3146 +
3147 +typedef struct _ind_data_b_t {
3148 + unsigned char ind_data_b : 8;
3149 + } ind_data_b_t;
3150 +
3151 +typedef union {
3152 + unsigned char val : 8;
3153 + ind_data_b_t f;
3154 +} ind_data_b_u;
3155 +
3156 +typedef struct _pm4_rptr_t {
3157 + unsigned char pm4_rptr : 8;
3158 + } pm4_rptr_t;
3159 +
3160 +typedef union {
3161 + unsigned char val : 8;
3162 + pm4_rptr_t f;
3163 +} pm4_rptr_u;
3164 +
3165 +typedef struct _scratch_t {
3166 + unsigned char scratch : 8;
3167 + } scratch_t;
3168 +
3169 +typedef union {
3170 + unsigned char val : 8;
3171 + scratch_t f;
3172 +} scratch_u;
3173 +
3174 +typedef struct _pm4_wrptr_0_t {
3175 + unsigned char pm4_wrptr_0 : 8;
3176 + } pm4_wrptr_0_t;
3177 +
3178 +typedef union {
3179 + unsigned char val : 8;
3180 + pm4_wrptr_0_t f;
3181 +} pm4_wrptr_0_u;
3182 +
3183 +typedef struct _pm4_wrptr_1_t {
3184 + unsigned char pm4_wrptr_1 : 6;
3185 + unsigned char rd_fetch_pm4_rptr : 1;
3186 + unsigned char wrptr_atomic_update_w : 1;
3187 + } pm4_wrptr_1_t;
3188 +
3189 +typedef union {
3190 + unsigned char val : 8;
3191 + pm4_wrptr_1_t f;
3192 +} pm4_wrptr_1_u;
3193 +
3194 +typedef struct _cp_rb_cntl_t {
3195 + unsigned long rb_bufsz : 6;
3196 + unsigned long : 2;
3197 + unsigned long rb_blksz : 6;
3198 + unsigned long : 2;
3199 + unsigned long buf_swap : 2;
3200 + unsigned long max_fetch : 2;
3201 + unsigned long : 7;
3202 + unsigned long rb_no_update : 1;
3203 + unsigned long : 3;
3204 + unsigned long rb_rptr_wr_ena : 1;
3205 + } cp_rb_cntl_t;
3206 +
3207 +typedef union {
3208 + unsigned long val : 32;
3209 + cp_rb_cntl_t f;
3210 +} cp_rb_cntl_u;
3211 +
3212 +typedef struct _cp_rb_base_t {
3213 + unsigned long : 2;
3214 + unsigned long rb_base : 22;
3215 + unsigned long : 8;
3216 + } cp_rb_base_t;
3217 +
3218 +typedef union {
3219 + unsigned long val : 32;
3220 + cp_rb_base_t f;
3221 +} cp_rb_base_u;
3222 +
3223 +typedef struct _cp_rb_rptr_addr_t {
3224 + unsigned long rb_rptr_swap : 2;
3225 + unsigned long rb_rptr_addr : 22;
3226 + unsigned long : 8;
3227 + } cp_rb_rptr_addr_t;
3228 +
3229 +typedef union {
3230 + unsigned long val : 32;
3231 + cp_rb_rptr_addr_t f;
3232 +} cp_rb_rptr_addr_u;
3233 +
3234 +typedef struct _cp_rb_rptr_t {
3235 + unsigned long rb_rptr : 23;
3236 + unsigned long : 9;
3237 + } cp_rb_rptr_t;
3238 +
3239 +typedef union {
3240 + unsigned long val : 32;
3241 + cp_rb_rptr_t f;
3242 +} cp_rb_rptr_u;
3243 +
3244 +typedef struct _cp_rb_rptr_wr_t {
3245 + unsigned long rb_rptr_wr : 23;
3246 + unsigned long : 9;
3247 + } cp_rb_rptr_wr_t;
3248 +
3249 +typedef union {
3250 + unsigned long val : 32;
3251 + cp_rb_rptr_wr_t f;
3252 +} cp_rb_rptr_wr_u;
3253 +
3254 +typedef struct _cp_rb_wptr_t {
3255 + unsigned long rb_wptr : 23;
3256 + unsigned long : 9;
3257 + } cp_rb_wptr_t;
3258 +
3259 +typedef union {
3260 + unsigned long val : 32;
3261 + cp_rb_wptr_t f;
3262 +} cp_rb_wptr_u;
3263 +
3264 +typedef struct _cp_ib_base_t {
3265 + unsigned long : 2;
3266 + unsigned long ib_base : 22;
3267 + unsigned long : 8;
3268 + } cp_ib_base_t;
3269 +
3270 +typedef union {
3271 + unsigned long val : 32;
3272 + cp_ib_base_t f;
3273 +} cp_ib_base_u;
3274 +
3275 +typedef struct _cp_ib_bufsz_t {
3276 + unsigned long ib_bufsz : 23;
3277 + unsigned long : 9;
3278 + } cp_ib_bufsz_t;
3279 +
3280 +typedef union {
3281 + unsigned long val : 32;
3282 + cp_ib_bufsz_t f;
3283 +} cp_ib_bufsz_u;
3284 +
3285 +typedef struct _cp_csq_cntl_t {
3286 + unsigned long csq_cnt_primary : 8;
3287 + unsigned long csq_cnt_indirect : 8;
3288 + unsigned long : 12;
3289 + unsigned long csq_mode : 4;
3290 + } cp_csq_cntl_t;
3291 +
3292 +typedef union {
3293 + unsigned long val : 32;
3294 + cp_csq_cntl_t f;
3295 +} cp_csq_cntl_u;
3296 +
3297 +typedef struct _cp_csq_aper_primary_t {
3298 + unsigned long cp_csq_aper_primary : 32;
3299 + } cp_csq_aper_primary_t;
3300 +
3301 +typedef union {
3302 + unsigned long val : 32;
3303 + cp_csq_aper_primary_t f;
3304 +} cp_csq_aper_primary_u;
3305 +
3306 +typedef struct _cp_csq_aper_indirect_t {
3307 + unsigned long cp_csq_aper_indirect : 32;
3308 + } cp_csq_aper_indirect_t;
3309 +
3310 +typedef union {
3311 + unsigned long val : 32;
3312 + cp_csq_aper_indirect_t f;
3313 +} cp_csq_aper_indirect_u;
3314 +
3315 +typedef struct _cp_me_cntl_t {
3316 + unsigned long me_stat : 16;
3317 + unsigned long me_statmux : 5;
3318 + unsigned long : 8;
3319 + unsigned long me_busy : 1;
3320 + unsigned long me_mode : 1;
3321 + unsigned long me_step : 1;
3322 + } cp_me_cntl_t;
3323 +
3324 +typedef union {
3325 + unsigned long val : 32;
3326 + cp_me_cntl_t f;
3327 +} cp_me_cntl_u;
3328 +
3329 +typedef struct _cp_me_ram_addr_t {
3330 + unsigned long me_ram_addr : 8;
3331 + unsigned long : 24;
3332 + } cp_me_ram_addr_t;
3333 +
3334 +typedef union {
3335 + unsigned long val : 32;
3336 + cp_me_ram_addr_t f;
3337 +} cp_me_ram_addr_u;
3338 +
3339 +typedef struct _cp_me_ram_raddr_t {
3340 + unsigned long me_ram_raddr : 8;
3341 + unsigned long : 24;
3342 + } cp_me_ram_raddr_t;
3343 +
3344 +typedef union {
3345 + unsigned long val : 32;
3346 + cp_me_ram_raddr_t f;
3347 +} cp_me_ram_raddr_u;
3348 +
3349 +typedef struct _cp_me_ram_datah_t {
3350 + unsigned long me_ram_datah : 6;
3351 + unsigned long : 26;
3352 + } cp_me_ram_datah_t;
3353 +
3354 +typedef union {
3355 + unsigned long val : 32;
3356 + cp_me_ram_datah_t f;
3357 +} cp_me_ram_datah_u;
3358 +
3359 +typedef struct _cp_me_ram_datal_t {
3360 + unsigned long me_ram_datal : 32;
3361 + } cp_me_ram_datal_t;
3362 +
3363 +typedef union {
3364 + unsigned long val : 32;
3365 + cp_me_ram_datal_t f;
3366 +} cp_me_ram_datal_u;
3367 +
3368 +typedef struct _cp_debug_t {
3369 + unsigned long cp_debug : 32;
3370 + } cp_debug_t;
3371 +
3372 +typedef union {
3373 + unsigned long val : 32;
3374 + cp_debug_t f;
3375 +} cp_debug_u;
3376 +
3377 +typedef struct _scratch_reg0_t {
3378 + unsigned long scratch_reg0 : 32;
3379 + } scratch_reg0_t;
3380 +
3381 +typedef union {
3382 + unsigned long val : 32;
3383 + scratch_reg0_t f;
3384 +} scratch_reg0_u;
3385 +
3386 +typedef struct _scratch_reg1_t {
3387 + unsigned long scratch_reg1 : 32;
3388 + } scratch_reg1_t;
3389 +
3390 +typedef union {
3391 + unsigned long val : 32;
3392 + scratch_reg1_t f;
3393 +} scratch_reg1_u;
3394 +
3395 +typedef struct _scratch_reg2_t {
3396 + unsigned long scratch_reg2 : 32;
3397 + } scratch_reg2_t;
3398 +
3399 +typedef union {
3400 + unsigned long val : 32;
3401 + scratch_reg2_t f;
3402 +} scratch_reg2_u;
3403 +
3404 +typedef struct _scratch_reg3_t {
3405 + unsigned long scratch_reg3 : 32;
3406 + } scratch_reg3_t;
3407 +
3408 +typedef union {
3409 + unsigned long val : 32;
3410 + scratch_reg3_t f;
3411 +} scratch_reg3_u;
3412 +
3413 +typedef struct _scratch_reg4_t {
3414 + unsigned long scratch_reg4 : 32;
3415 + } scratch_reg4_t;
3416 +
3417 +typedef union {
3418 + unsigned long val : 32;
3419 + scratch_reg4_t f;
3420 +} scratch_reg4_u;
3421 +
3422 +typedef struct _scratch_reg5_t {
3423 + unsigned long scratch_reg5 : 32;
3424 + } scratch_reg5_t;
3425 +
3426 +typedef union {
3427 + unsigned long val : 32;
3428 + scratch_reg5_t f;
3429 +} scratch_reg5_u;
3430 +
3431 +typedef struct _scratch_umsk_t {
3432 + unsigned long scratch_umsk : 6;
3433 + unsigned long : 10;
3434 + unsigned long scratch_swap : 2;
3435 + unsigned long : 14;
3436 + } scratch_umsk_t;
3437 +
3438 +typedef union {
3439 + unsigned long val : 32;
3440 + scratch_umsk_t f;
3441 +} scratch_umsk_u;
3442 +
3443 +typedef struct _scratch_addr_t {
3444 + unsigned long : 5;
3445 + unsigned long scratch_addr : 27;
3446 + } scratch_addr_t;
3447 +
3448 +typedef union {
3449 + unsigned long val : 32;
3450 + scratch_addr_t f;
3451 +} scratch_addr_u;
3452 +
3453 +typedef struct _cp_csq_addr_t {
3454 + unsigned long : 2;
3455 + unsigned long csq_addr : 8;
3456 + unsigned long : 22;
3457 + } cp_csq_addr_t;
3458 +
3459 +typedef union {
3460 + unsigned long val : 32;
3461 + cp_csq_addr_t f;
3462 +} cp_csq_addr_u;
3463 +
3464 +typedef struct _cp_csq_data_t {
3465 + unsigned long csq_data : 32;
3466 + } cp_csq_data_t;
3467 +
3468 +typedef union {
3469 + unsigned long val : 32;
3470 + cp_csq_data_t f;
3471 +} cp_csq_data_u;
3472 +
3473 +typedef struct _cp_csq_stat_t {
3474 + unsigned long csq_rptr_primary : 8;
3475 + unsigned long csq_wptr_primary : 8;
3476 + unsigned long csq_rptr_indirect : 8;
3477 + unsigned long csq_wptr_indirect : 8;
3478 + } cp_csq_stat_t;
3479 +
3480 +typedef union {
3481 + unsigned long val : 32;
3482 + cp_csq_stat_t f;
3483 +} cp_csq_stat_u;
3484 +
3485 +typedef struct _cp_stat_t {
3486 + unsigned long mru_busy : 1;
3487 + unsigned long mwu_busy : 1;
3488 + unsigned long rsiu_busy : 1;
3489 + unsigned long rciu_busy : 1;
3490 + unsigned long : 5;
3491 + unsigned long csf_primary_busy : 1;
3492 + unsigned long csf_indirect_busy : 1;
3493 + unsigned long csq_primary_busy : 1;
3494 + unsigned long csq_indirect_busy : 1;
3495 + unsigned long csi_busy : 1;
3496 + unsigned long : 14;
3497 + unsigned long guidma_busy : 1;
3498 + unsigned long viddma_busy : 1;
3499 + unsigned long cmdstrm_busy : 1;
3500 + unsigned long cp_busy : 1;
3501 + } cp_stat_t;
3502 +
3503 +typedef union {
3504 + unsigned long val : 32;
3505 + cp_stat_t f;
3506 +} cp_stat_u;
3507 +
3508 +typedef struct _gen_int_cntl_t {
3509 + unsigned long crtc_vblank_mask : 1;
3510 + unsigned long crtc_vline_mask : 1;
3511 + unsigned long crtc_hwint1_mask : 1;
3512 + unsigned long crtc_hwint2_mask : 1;
3513 + unsigned long : 15;
3514 + unsigned long gui_idle_mask : 1;
3515 + unsigned long : 8;
3516 + unsigned long pm4_idle_int_mask : 1;
3517 + unsigned long dvi_i2c_int_mask : 1;
3518 + unsigned long : 2;
3519 + } gen_int_cntl_t;
3520 +
3521 +typedef union {
3522 + unsigned long val : 32;
3523 + gen_int_cntl_t f;
3524 +} gen_int_cntl_u;
3525 +
3526 +typedef struct _gen_int_status_rd_t {
3527 + unsigned long crtc_vblank_stat : 1;
3528 + unsigned long crtc_vline_stat : 1;
3529 + unsigned long crtc_hwint1_stat : 1;
3530 + unsigned long crtc_hwint2_stat : 1;
3531 + unsigned long : 15;
3532 + unsigned long gui_idle_stat : 1;
3533 + unsigned long : 8;
3534 + unsigned long pm4_idle_int_stat : 1;
3535 + unsigned long dvi_i2c_int_stat : 1;
3536 + unsigned long : 2;
3537 + } gen_int_status_rd_t;
3538 +
3539 +typedef union {
3540 + unsigned long val : 32;
3541 + gen_int_status_rd_t f;
3542 +} gen_int_status_rd_u;
3543 +
3544 +typedef struct _gen_int_status_wr_t {
3545 + unsigned long crtc_vblank_stat_ak : 1;
3546 + unsigned long crtc_vline_stat_ak : 1;
3547 + unsigned long crtc_hwint1_stat_ak : 1;
3548 + unsigned long crtc_hwint2_stat_ak : 1;
3549 + unsigned long : 15;
3550 + unsigned long gui_idle_stat_ak : 1;
3551 + unsigned long : 8;
3552 + unsigned long pm4_idle_int_ak : 1;
3553 + unsigned long dvi_i2c_int_ak : 1;
3554 + unsigned long : 2;
3555 + } gen_int_status_wr_t;
3556 +
3557 +typedef union {
3558 + unsigned long val : 32;
3559 + gen_int_status_wr_t f;
3560 +} gen_int_status_wr_u;
3561 +
3562 +typedef struct _lcd_format_t {
3563 + unsigned long lcd_type : 4;
3564 + unsigned long color_to_mono : 1;
3565 + unsigned long data_inv : 1;
3566 + unsigned long stn_fm : 2;
3567 + unsigned long tft_fm : 2;
3568 + unsigned long scan_lr_en : 1;
3569 + unsigned long scan_ud_en : 1;
3570 + unsigned long pol_inv : 1;
3571 + unsigned long rst_fm : 1;
3572 + unsigned long yuv_to_rgb : 1;
3573 + unsigned long hr_tft : 1;
3574 + unsigned long ulc_panel : 1;
3575 + unsigned long : 15;
3576 + } lcd_format_t;
3577 +
3578 +typedef union {
3579 + unsigned long val : 32;
3580 + lcd_format_t f;
3581 +} lcd_format_u;
3582 +
3583 +typedef struct _graphic_ctrl_t {
3584 + unsigned long color_depth : 3;
3585 + unsigned long portrait_mode : 2;
3586 + unsigned long low_power_on : 1;
3587 + unsigned long req_freq : 4;
3588 + unsigned long en_crtc : 1;
3589 + unsigned long en_graphic_req : 1;
3590 + unsigned long en_graphic_crtc : 1;
3591 + unsigned long total_req_graphic : 9;
3592 + unsigned long lcd_pclk_on : 1;
3593 + unsigned long lcd_sclk_on : 1;
3594 + unsigned long pclk_running : 1;
3595 + unsigned long sclk_running : 1;
3596 + unsigned long : 6;
3597 + } graphic_ctrl_t;
3598 +
3599 +typedef union {
3600 + unsigned long val : 32;
3601 + graphic_ctrl_t f;
3602 +} graphic_ctrl_u;
3603 +
3604 +typedef struct _graphic_offset_t {
3605 + unsigned long graphic_offset : 24;
3606 + unsigned long : 8;
3607 + } graphic_offset_t;
3608 +
3609 +typedef union {
3610 + unsigned long val : 32;
3611 + graphic_offset_t f;
3612 +} graphic_offset_u;
3613 +
3614 +typedef struct _graphic_pitch_t {
3615 + unsigned long graphic_pitch : 11;
3616 + unsigned long : 21;
3617 + } graphic_pitch_t;
3618 +
3619 +typedef union {
3620 + unsigned long val : 32;
3621 + graphic_pitch_t f;
3622 +} graphic_pitch_u;
3623 +
3624 +typedef struct _crtc_total_t {
3625 + unsigned long crtc_h_total : 10;
3626 + unsigned long : 6;
3627 + unsigned long crtc_v_total : 10;
3628 + unsigned long : 6;
3629 + } crtc_total_t;
3630 +
3631 +typedef union {
3632 + unsigned long val : 32;
3633 + crtc_total_t f;
3634 +} crtc_total_u;
3635 +
3636 +typedef struct _active_h_disp_t {
3637 + unsigned long active_h_start : 10;
3638 + unsigned long : 6;
3639 + unsigned long active_h_end : 10;
3640 + unsigned long : 6;
3641 + } active_h_disp_t;
3642 +
3643 +typedef union {
3644 + unsigned long val : 32;
3645 + active_h_disp_t f;
3646 +} active_h_disp_u;
3647 +
3648 +typedef struct _active_v_disp_t {
3649 + unsigned long active_v_start : 10;
3650 + unsigned long : 6;
3651 + unsigned long active_v_end : 10;
3652 + unsigned long : 6;
3653 + } active_v_disp_t;
3654 +
3655 +typedef union {
3656 + unsigned long val : 32;
3657 + active_v_disp_t f;
3658 +} active_v_disp_u;
3659 +
3660 +typedef struct _graphic_h_disp_t {
3661 + unsigned long graphic_h_start : 10;
3662 + unsigned long : 6;
3663 + unsigned long graphic_h_end : 10;
3664 + unsigned long : 6;
3665 + } graphic_h_disp_t;
3666 +
3667 +typedef union {
3668 + unsigned long val : 32;
3669 + graphic_h_disp_t f;
3670 +} graphic_h_disp_u;
3671 +
3672 +typedef struct _graphic_v_disp_t {
3673 + unsigned long graphic_v_start : 10;
3674 + unsigned long : 6;
3675 + unsigned long graphic_v_end : 10;
3676 + unsigned long : 6;
3677 + } graphic_v_disp_t;
3678 +
3679 +typedef union {
3680 + unsigned long val : 32;
3681 + graphic_v_disp_t f;
3682 +} graphic_v_disp_u;
3683 +
3684 +typedef struct _video_ctrl_t {
3685 + unsigned long video_mode : 1;
3686 + unsigned long keyer_en : 1;
3687 + unsigned long en_video_req : 1;
3688 + unsigned long en_graphic_req_video : 1;
3689 + unsigned long en_video_crtc : 1;
3690 + unsigned long video_hor_exp : 2;
3691 + unsigned long video_ver_exp : 2;
3692 + unsigned long uv_combine : 1;
3693 + unsigned long total_req_video : 9;
3694 + unsigned long video_ch_sel : 1;
3695 + unsigned long video_portrait : 2;
3696 + unsigned long yuv2rgb_en : 1;
3697 + unsigned long yuv2rgb_option : 1;
3698 + unsigned long video_inv_hor : 1;
3699 + unsigned long video_inv_ver : 1;
3700 + unsigned long gamma_sel : 2;
3701 + unsigned long dis_limit : 1;
3702 + unsigned long en_uv_hblend : 1;
3703 + unsigned long rgb_gamma_sel : 2;
3704 + } video_ctrl_t;
3705 +
3706 +typedef union {
3707 + unsigned long val : 32;
3708 + video_ctrl_t f;
3709 +} video_ctrl_u;
3710 +
3711 +typedef struct _graphic_key_t {
3712 + unsigned long keyer_color : 16;
3713 + unsigned long keyer_mask : 16;
3714 + } graphic_key_t;
3715 +
3716 +typedef union {
3717 + unsigned long val : 32;
3718 + graphic_key_t f;
3719 +} graphic_key_u;
3720 +
3721 +typedef struct _video_y_offset_t {
3722 + unsigned long y_offset : 24;
3723 + unsigned long : 8;
3724 + } video_y_offset_t;
3725 +
3726 +typedef union {
3727 + unsigned long val : 32;
3728 + video_y_offset_t f;
3729 +} video_y_offset_u;
3730 +
3731 +typedef struct _video_y_pitch_t {
3732 + unsigned long y_pitch : 11;
3733 + unsigned long : 21;
3734 + } video_y_pitch_t;
3735 +
3736 +typedef union {
3737 + unsigned long val : 32;
3738 + video_y_pitch_t f;
3739 +} video_y_pitch_u;
3740 +
3741 +typedef struct _video_u_offset_t {
3742 + unsigned long u_offset : 24;
3743 + unsigned long : 8;
3744 + } video_u_offset_t;
3745 +
3746 +typedef union {
3747 + unsigned long val : 32;
3748 + video_u_offset_t f;
3749 +} video_u_offset_u;
3750 +
3751 +typedef struct _video_u_pitch_t {
3752 + unsigned long u_pitch : 11;
3753 + unsigned long : 21;
3754 + } video_u_pitch_t;
3755 +
3756 +typedef union {
3757 + unsigned long val : 32;
3758 + video_u_pitch_t f;
3759 +} video_u_pitch_u;
3760 +
3761 +typedef struct _video_v_offset_t {
3762 + unsigned long v_offset : 24;
3763 + unsigned long : 8;
3764 + } video_v_offset_t;
3765 +
3766 +typedef union {
3767 + unsigned long val : 32;
3768 + video_v_offset_t f;
3769 +} video_v_offset_u;
3770 +
3771 +typedef struct _video_v_pitch_t {
3772 + unsigned long v_pitch : 11;
3773 + unsigned long : 21;
3774 + } video_v_pitch_t;
3775 +
3776 +typedef union {
3777 + unsigned long val : 32;
3778 + video_v_pitch_t f;
3779 +} video_v_pitch_u;
3780 +
3781 +typedef struct _video_h_pos_t {
3782 + unsigned long video_h_start : 10;
3783 + unsigned long : 6;
3784 + unsigned long video_h_end : 10;
3785 + unsigned long : 6;
3786 + } video_h_pos_t;
3787 +
3788 +typedef union {
3789 + unsigned long val : 32;
3790 + video_h_pos_t f;
3791 +} video_h_pos_u;
3792 +
3793 +typedef struct _video_v_pos_t {
3794 + unsigned long video_v_start : 10;
3795 + unsigned long : 6;
3796 + unsigned long video_v_end : 10;
3797 + unsigned long : 6;
3798 + } video_v_pos_t;
3799 +
3800 +typedef union {
3801 + unsigned long val : 32;
3802 + video_v_pos_t f;
3803 +} video_v_pos_u;
3804 +
3805 +typedef struct _brightness_cntl_t {
3806 + unsigned long brightness : 7;
3807 + unsigned long : 25;
3808 + } brightness_cntl_t;
3809 +
3810 +typedef union {
3811 + unsigned long val : 32;
3812 + brightness_cntl_t f;
3813 +} brightness_cntl_u;
3814 +
3815 +typedef struct _cursor1_offset_t {
3816 + unsigned long cur1_offset : 24;
3817 + unsigned long cur1_x_offset : 4;
3818 + unsigned long cur1_y_offset : 4;
3819 + } cursor1_offset_t;
3820 +
3821 +typedef union {
3822 + unsigned long val : 32;
3823 + cursor1_offset_t f;
3824 +} cursor1_offset_u;
3825 +
3826 +typedef struct _cursor1_h_pos_t {
3827 + unsigned long cur1_h_start : 10;
3828 + unsigned long : 6;
3829 + unsigned long cur1_h_end : 10;
3830 + unsigned long : 5;
3831 + unsigned long cur1_en : 1;
3832 + } cursor1_h_pos_t;
3833 +
3834 +typedef union {
3835 + unsigned long val : 32;
3836 + cursor1_h_pos_t f;
3837 +} cursor1_h_pos_u;
3838 +
3839 +typedef struct _cursor1_v_pos_t {
3840 + unsigned long cur1_v_start : 10;
3841 + unsigned long : 6;
3842 + unsigned long cur1_v_end : 10;
3843 + unsigned long : 6;
3844 + } cursor1_v_pos_t;
3845 +
3846 +typedef union {
3847 + unsigned long val : 32;
3848 + cursor1_v_pos_t f;
3849 +} cursor1_v_pos_u;
3850 +
3851 +typedef struct _cursor1_color0_t {
3852 + unsigned long cur1_color0_r : 8;
3853 + unsigned long cur1_color0_g : 8;
3854 + unsigned long cur1_color0_b : 8;
3855 + unsigned long : 8;
3856 + } cursor1_color0_t;
3857 +
3858 +typedef union {
3859 + unsigned long val : 32;
3860 + cursor1_color0_t f;
3861 +} cursor1_color0_u;
3862 +
3863 +typedef struct _cursor1_color1_t {
3864 + unsigned long cur1_color1_r : 8;
3865 + unsigned long cur1_color1_g : 8;
3866 + unsigned long cur1_color1_b : 8;
3867 + unsigned long : 8;
3868 + } cursor1_color1_t;
3869 +
3870 +typedef union {
3871 + unsigned long val : 32;
3872 + cursor1_color1_t f;
3873 +} cursor1_color1_u;
3874 +
3875 +typedef struct _cursor2_offset_t {
3876 + unsigned long cur2_offset : 24;
3877 + unsigned long cur2_x_offset : 4;
3878 + unsigned long cur2_y_offset : 4;
3879 + } cursor2_offset_t;
3880 +
3881 +typedef union {
3882 + unsigned long val : 32;
3883 + cursor2_offset_t f;
3884 +} cursor2_offset_u;
3885 +
3886 +typedef struct _cursor2_h_pos_t {
3887 + unsigned long cur2_h_start : 10;
3888 + unsigned long : 6;
3889 + unsigned long cur2_h_end : 10;
3890 + unsigned long : 5;
3891 + unsigned long cur2_en : 1;
3892 + } cursor2_h_pos_t;
3893 +
3894 +typedef union {
3895 + unsigned long val : 32;
3896 + cursor2_h_pos_t f;
3897 +} cursor2_h_pos_u;
3898 +
3899 +typedef struct _cursor2_v_pos_t {
3900 + unsigned long cur2_v_start : 10;
3901 + unsigned long : 6;
3902 + unsigned long cur2_v_end : 10;
3903 + unsigned long : 6;
3904 + } cursor2_v_pos_t;
3905 +
3906 +typedef union {
3907 + unsigned long val : 32;
3908 + cursor2_v_pos_t f;
3909 +} cursor2_v_pos_u;
3910 +
3911 +typedef struct _cursor2_color0_t {
3912 + unsigned long cur2_color0_r : 8;
3913 + unsigned long cur2_color0_g : 8;
3914 + unsigned long cur2_color0_b : 8;
3915 + unsigned long : 8;
3916 + } cursor2_color0_t;
3917 +
3918 +typedef union {
3919 + unsigned long val : 32;
3920 + cursor2_color0_t f;
3921 +} cursor2_color0_u;
3922 +
3923 +typedef struct _cursor2_color1_t {
3924 + unsigned long cur2_color1_r : 8;
3925 + unsigned long cur2_color1_g : 8;
3926 + unsigned long cur2_color1_b : 8;
3927 + unsigned long : 8;
3928 + } cursor2_color1_t;
3929 +
3930 +typedef union {
3931 + unsigned long val : 32;
3932 + cursor2_color1_t f;
3933 +} cursor2_color1_u;
3934 +
3935 +typedef struct _disp_int_cntl_t {
3936 + unsigned long vline_int_pos : 10;
3937 + unsigned long : 6;
3938 + unsigned long hpos_int_pos : 10;
3939 + unsigned long : 4;
3940 + unsigned long vblank_int_pol : 1;
3941 + unsigned long frame_int_pol : 1;
3942 + } disp_int_cntl_t;
3943 +
3944 +typedef union {
3945 + unsigned long val : 32;
3946 + disp_int_cntl_t f;
3947 +} disp_int_cntl_u;
3948 +
3949 +typedef struct _crtc_ss_t {
3950 + unsigned long ss_start : 10;
3951 + unsigned long : 6;
3952 + unsigned long ss_end : 10;
3953 + unsigned long : 2;
3954 + unsigned long ss_align : 1;
3955 + unsigned long ss_pol : 1;
3956 + unsigned long ss_run_mode : 1;
3957 + unsigned long ss_en : 1;
3958 + } crtc_ss_t;
3959 +
3960 +typedef union {
3961 + unsigned long val : 32;
3962 + crtc_ss_t f;
3963 +} crtc_ss_u;
3964 +
3965 +typedef struct _crtc_ls_t {
3966 + unsigned long ls_start : 10;
3967 + unsigned long : 6;
3968 + unsigned long ls_end : 10;
3969 + unsigned long : 2;
3970 + unsigned long ls_align : 1;
3971 + unsigned long ls_pol : 1;
3972 + unsigned long ls_run_mode : 1;
3973 + unsigned long ls_en : 1;
3974 + } crtc_ls_t;
3975 +
3976 +typedef union {
3977 + unsigned long val : 32;
3978 + crtc_ls_t f;
3979 +} crtc_ls_u;
3980 +
3981 +typedef struct _crtc_rev_t {
3982 + unsigned long rev_pos : 10;
3983 + unsigned long : 6;
3984 + unsigned long rev_align : 1;
3985 + unsigned long rev_freq_nref : 5;
3986 + unsigned long rev_en : 1;
3987 + unsigned long : 9;
3988 + } crtc_rev_t;
3989 +
3990 +typedef union {
3991 + unsigned long val : 32;
3992 + crtc_rev_t f;
3993 +} crtc_rev_u;
3994 +
3995 +typedef struct _crtc_dclk_t {
3996 + unsigned long dclk_start : 10;
3997 + unsigned long : 6;
3998 + unsigned long dclk_end : 10;
3999 + unsigned long : 1;
4000 + unsigned long dclk_run_mode : 2;
4001 + unsigned long dclk_pol : 1;
4002 + unsigned long dclk_align : 1;
4003 + unsigned long dclk_en : 1;
4004 + } crtc_dclk_t;
4005 +
4006 +typedef union {
4007 + unsigned long val : 32;
4008 + crtc_dclk_t f;
4009 +} crtc_dclk_u;
4010 +
4011 +typedef struct _crtc_gs_t {
4012 + unsigned long gs_start : 10;
4013 + unsigned long : 6;
4014 + unsigned long gs_end : 10;
4015 + unsigned long : 3;
4016 + unsigned long gs_align : 1;
4017 + unsigned long gs_pol : 1;
4018 + unsigned long gs_en : 1;
4019 + } crtc_gs_t;
4020 +
4021 +typedef union {
4022 + unsigned long val : 32;
4023 + crtc_gs_t f;
4024 +} crtc_gs_u;
4025 +
4026 +typedef struct _crtc_vpos_gs_t {
4027 + unsigned long gs_vpos_start : 10;
4028 + unsigned long : 6;
4029 + unsigned long gs_vpos_end : 10;
4030 + unsigned long : 6;
4031 + } crtc_vpos_gs_t;
4032 +
4033 +typedef union {
4034 + unsigned long val : 32;
4035 + crtc_vpos_gs_t f;
4036 +} crtc_vpos_gs_u;
4037 +
4038 +typedef struct _crtc_gclk_t {
4039 + unsigned long gclk_start : 10;
4040 + unsigned long : 6;
4041 + unsigned long gclk_end : 10;
4042 + unsigned long : 3;
4043 + unsigned long gclk_align : 1;
4044 + unsigned long gclk_pol : 1;
4045 + unsigned long gclk_en : 1;
4046 + } crtc_gclk_t;
4047 +
4048 +typedef union {
4049 + unsigned long val : 32;
4050 + crtc_gclk_t f;
4051 +} crtc_gclk_u;
4052 +
4053 +typedef struct _crtc_goe_t {
4054 + unsigned long goe_start : 10;
4055 + unsigned long : 6;
4056 + unsigned long goe_end : 10;
4057 + unsigned long : 3;
4058 + unsigned long goe_align : 1;
4059 + unsigned long goe_pol : 1;
4060 + unsigned long goe_en : 1;
4061 + } crtc_goe_t;
4062 +
4063 +typedef union {
4064 + unsigned long val : 32;
4065 + crtc_goe_t f;
4066 +} crtc_goe_u;
4067 +
4068 +typedef struct _crtc_frame_t {
4069 + unsigned long crtc_fr_start : 10;
4070 + unsigned long : 6;
4071 + unsigned long crtc_fr_end : 10;
4072 + unsigned long : 4;
4073 + unsigned long crtc_frame_en : 1;
4074 + unsigned long crtc_frame_align : 1;
4075 + } crtc_frame_t;
4076 +
4077 +typedef union {
4078 + unsigned long val : 32;
4079 + crtc_frame_t f;
4080 +} crtc_frame_u;
4081 +
4082 +typedef struct _crtc_frame_vpos_t {
4083 + unsigned long crtc_fr_vpos : 10;
4084 + unsigned long : 22;
4085 + } crtc_frame_vpos_t;
4086 +
4087 +typedef union {
4088 + unsigned long val : 32;
4089 + crtc_frame_vpos_t f;
4090 +} crtc_frame_vpos_u;
4091 +
4092 +typedef struct _gpio_data_t {
4093 + unsigned long gio_out : 16;
4094 + unsigned long gio_in : 16;
4095 + } gpio_data_t;
4096 +
4097 +typedef union {
4098 + unsigned long val : 32;
4099 + gpio_data_t f;
4100 +} gpio_data_u;
4101 +
4102 +typedef struct _gpio_cntl1_t {
4103 + unsigned long gio_pd : 16;
4104 + unsigned long gio_schmen : 16;
4105 + } gpio_cntl1_t;
4106 +
4107 +typedef union {
4108 + unsigned long val : 32;
4109 + gpio_cntl1_t f;
4110 +} gpio_cntl1_u;
4111 +
4112 +typedef struct _gpio_cntl2_t {
4113 + unsigned long gio_oe : 16;
4114 + unsigned long gio_srp : 1;
4115 + unsigned long gio_srn : 1;
4116 + unsigned long gio_sp : 4;
4117 + unsigned long gio_sn : 4;
4118 + unsigned long : 6;
4119 + } gpio_cntl2_t;
4120 +
4121 +typedef union {
4122 + unsigned long val : 32;
4123 + gpio_cntl2_t f;
4124 +} gpio_cntl2_u;
4125 +
4126 +typedef struct _lcdd_cntl1_t {
4127 + unsigned long lcdd_pd : 18;
4128 + unsigned long lcdd_srp : 1;
4129 + unsigned long lcdd_srn : 1;
4130 + unsigned long lcdd_sp : 4;
4131 + unsigned long lcdd_sn : 4;
4132 + unsigned long lcdd_align : 1;
4133 + unsigned long : 3;
4134 + } lcdd_cntl1_t;
4135 +
4136 +typedef union {
4137 + unsigned long val : 32;
4138 + lcdd_cntl1_t f;
4139 +} lcdd_cntl1_u;
4140 +
4141 +typedef struct _lcdd_cntl2_t {
4142 + unsigned long lcdd_oe : 18;
4143 + unsigned long : 14;
4144 + } lcdd_cntl2_t;
4145 +
4146 +typedef union {
4147 + unsigned long val : 32;
4148 + lcdd_cntl2_t f;
4149 +} lcdd_cntl2_u;
4150 +
4151 +typedef struct _genlcd_cntl1_t {
4152 + unsigned long dclk_oe : 1;
4153 + unsigned long dclk_pd : 1;
4154 + unsigned long dclk_srp : 1;
4155 + unsigned long dclk_srn : 1;
4156 + unsigned long dclk_sp : 4;
4157 + unsigned long dclk_sn : 4;
4158 + unsigned long ss_oe : 1;
4159 + unsigned long ss_pd : 1;
4160 + unsigned long ls_oe : 1;
4161 + unsigned long ls_pd : 1;
4162 + unsigned long gs_oe : 1;
4163 + unsigned long gs_pd : 1;
4164 + unsigned long goe_oe : 1;
4165 + unsigned long goe_pd : 1;
4166 + unsigned long rev_oe : 1;
4167 + unsigned long rev_pd : 1;
4168 + unsigned long frame_oe : 1;
4169 + unsigned long frame_pd : 1;
4170 + unsigned long : 8;
4171 + } genlcd_cntl1_t;
4172 +
4173 +typedef union {
4174 + unsigned long val : 32;
4175 + genlcd_cntl1_t f;
4176 +} genlcd_cntl1_u;
4177 +
4178 +typedef struct _genlcd_cntl2_t {
4179 + unsigned long gclk_oe : 1;
4180 + unsigned long gclk_pd : 1;
4181 + unsigned long gclk_srp : 1;
4182 + unsigned long gclk_srn : 1;
4183 + unsigned long gclk_sp : 4;
4184 + unsigned long gclk_sn : 4;
4185 + unsigned long genlcd_srp : 1;
4186 + unsigned long genlcd_srn : 1;
4187 + unsigned long genlcd_sp : 4;
4188 + unsigned long genlcd_sn : 4;
4189 + unsigned long : 10;
4190 + } genlcd_cntl2_t;
4191 +
4192 +typedef union {
4193 + unsigned long val : 32;
4194 + genlcd_cntl2_t f;
4195 +} genlcd_cntl2_u;
4196 +
4197 +typedef struct _disp_debug_t {
4198 + unsigned long disp_debug : 32;
4199 + } disp_debug_t;
4200 +
4201 +typedef union {
4202 + unsigned long val : 32;
4203 + disp_debug_t f;
4204 +} disp_debug_u;
4205 +
4206 +typedef struct _disp_db_buf_cntl_rd_t {
4207 + unsigned long en_db_buf : 1;
4208 + unsigned long update_db_buf_done : 1;
4209 + unsigned long db_buf_cntl : 6;
4210 + unsigned long : 24;
4211 + } disp_db_buf_cntl_rd_t;
4212 +
4213 +typedef union {
4214 + unsigned long val : 32;
4215 + disp_db_buf_cntl_rd_t f;
4216 +} disp_db_buf_cntl_rd_u;
4217 +
4218 +typedef struct _disp_db_buf_cntl_wr_t {
4219 + unsigned long en_db_buf : 1;
4220 + unsigned long update_db_buf : 1;
4221 + unsigned long db_buf_cntl : 6;
4222 + unsigned long : 24;
4223 + } disp_db_buf_cntl_wr_t;
4224 +
4225 +typedef union {
4226 + unsigned long val : 32;
4227 + disp_db_buf_cntl_wr_t f;
4228 +} disp_db_buf_cntl_wr_u;
4229 +
4230 +typedef struct _disp_crc_sig_t {
4231 + unsigned long crc_sig_r : 6;
4232 + unsigned long crc_sig_g : 6;
4233 + unsigned long crc_sig_b : 6;
4234 + unsigned long crc_cont_en : 1;
4235 + unsigned long crc_en : 1;
4236 + unsigned long crc_mask_en : 1;
4237 + unsigned long crc_sig_cntl : 6;
4238 + unsigned long : 5;
4239 + } disp_crc_sig_t;
4240 +
4241 +typedef union {
4242 + unsigned long val : 32;
4243 + disp_crc_sig_t f;
4244 +} disp_crc_sig_u;
4245 +
4246 +typedef struct _crtc_default_count_t {
4247 + unsigned long crtc_hcount_def : 10;
4248 + unsigned long : 6;
4249 + unsigned long crtc_vcount_def : 10;
4250 + unsigned long : 6;
4251 + } crtc_default_count_t;
4252 +
4253 +typedef union {
4254 + unsigned long val : 32;
4255 + crtc_default_count_t f;
4256 +} crtc_default_count_u;
4257 +
4258 +typedef struct _lcd_background_color_t {
4259 + unsigned long lcd_bg_red : 8;
4260 + unsigned long lcd_bg_green : 8;
4261 + unsigned long lcd_bg_blue : 8;
4262 + unsigned long : 8;
4263 + } lcd_background_color_t;
4264 +
4265 +typedef union {
4266 + unsigned long val : 32;
4267 + lcd_background_color_t f;
4268 +} lcd_background_color_u;
4269 +
4270 +typedef struct _crtc_ps2_t {
4271 + unsigned long ps2_start : 10;
4272 + unsigned long : 6;
4273 + unsigned long ps2_end : 10;
4274 + unsigned long : 4;
4275 + unsigned long ps2_pol : 1;
4276 + unsigned long ps2_en : 1;
4277 + } crtc_ps2_t;
4278 +
4279 +typedef union {
4280 + unsigned long val : 32;
4281 + crtc_ps2_t f;
4282 +} crtc_ps2_u;
4283 +
4284 +typedef struct _crtc_ps2_vpos_t {
4285 + unsigned long ps2_vpos_start : 10;
4286 + unsigned long : 6;
4287 + unsigned long ps2_vpos_end : 10;
4288 + unsigned long : 6;
4289 + } crtc_ps2_vpos_t;
4290 +
4291 +typedef union {
4292 + unsigned long val : 32;
4293 + crtc_ps2_vpos_t f;
4294 +} crtc_ps2_vpos_u;
4295 +
4296 +typedef struct _crtc_ps1_active_t {
4297 + unsigned long ps1_h_start : 10;
4298 + unsigned long : 6;
4299 + unsigned long ps1_h_end : 10;
4300 + unsigned long : 3;
4301 + unsigned long ps1_pol : 1;
4302 + unsigned long ps1_en : 1;
4303 + unsigned long ps1_use_nactive : 1;
4304 + } crtc_ps1_active_t;
4305 +
4306 +typedef union {
4307 + unsigned long val : 32;
4308 + crtc_ps1_active_t f;
4309 +} crtc_ps1_active_u;
4310 +
4311 +typedef struct _crtc_ps1_nactive_t {
4312 + unsigned long ps1_h_start_na : 10;
4313 + unsigned long : 6;
4314 + unsigned long ps1_h_end_na : 10;
4315 + unsigned long : 5;
4316 + unsigned long ps1_en_na : 1;
4317 + } crtc_ps1_nactive_t;
4318 +
4319 +typedef union {
4320 + unsigned long val : 32;
4321 + crtc_ps1_nactive_t f;
4322 +} crtc_ps1_nactive_u;
4323 +
4324 +typedef struct _crtc_gclk_ext_t {
4325 + unsigned long gclk_alter_start : 10;
4326 + unsigned long : 6;
4327 + unsigned long gclk_alter_width : 2;
4328 + unsigned long gclk_en_alter : 1;
4329 + unsigned long gclk_db_width : 2;
4330 + unsigned long : 11;
4331 + } crtc_gclk_ext_t;
4332 +
4333 +typedef union {
4334 + unsigned long val : 32;
4335 + crtc_gclk_ext_t f;
4336 +} crtc_gclk_ext_u;
4337 +
4338 +typedef struct _crtc_alw_t {
4339 + unsigned long alw_hstart : 10;
4340 + unsigned long : 6;
4341 + unsigned long alw_hend : 10;
4342 + unsigned long : 4;
4343 + unsigned long alw_delay : 1;
4344 + unsigned long alw_en : 1;
4345 + } crtc_alw_t;
4346 +
4347 +typedef union {
4348 + unsigned long val : 32;
4349 + crtc_alw_t f;
4350 +} crtc_alw_u;
4351 +
4352 +typedef struct _crtc_alw_vpos_t {
4353 + unsigned long alw_vstart : 10;
4354 + unsigned long : 6;
4355 + unsigned long alw_vend : 10;
4356 + unsigned long : 6;
4357 + } crtc_alw_vpos_t;
4358 +
4359 +typedef union {
4360 + unsigned long val : 32;
4361 + crtc_alw_vpos_t f;
4362 +} crtc_alw_vpos_u;
4363 +
4364 +typedef struct _crtc_psk_t {
4365 + unsigned long psk_vstart : 10;
4366 + unsigned long : 6;
4367 + unsigned long psk_vend : 10;
4368 + unsigned long : 4;
4369 + unsigned long psk_pol : 1;
4370 + unsigned long psk_en : 1;
4371 + } crtc_psk_t;
4372 +
4373 +typedef union {
4374 + unsigned long val : 32;
4375 + crtc_psk_t f;
4376 +} crtc_psk_u;
4377 +
4378 +typedef struct _crtc_psk_hpos_t {
4379 + unsigned long psk_hstart : 10;
4380 + unsigned long : 6;
4381 + unsigned long psk_hend : 10;
4382 + unsigned long : 6;
4383 + } crtc_psk_hpos_t;
4384 +
4385 +typedef union {
4386 + unsigned long val : 32;
4387 + crtc_psk_hpos_t f;
4388 +} crtc_psk_hpos_u;
4389 +
4390 +typedef struct _crtc_cv4_start_t {
4391 + unsigned long cv4_vstart : 10;
4392 + unsigned long : 20;
4393 + unsigned long cv4_pol : 1;
4394 + unsigned long cv4_en : 1;
4395 + } crtc_cv4_start_t;
4396 +
4397 +typedef union {
4398 + unsigned long val : 32;
4399 + crtc_cv4_start_t f;
4400 +} crtc_cv4_start_u;
4401 +
4402 +typedef struct _crtc_cv4_end_t {
4403 + unsigned long cv4_vend1 : 10;
4404 + unsigned long : 6;
4405 + unsigned long cv4_vend2 : 10;
4406 + unsigned long : 6;
4407 + } crtc_cv4_end_t;
4408 +
4409 +typedef union {
4410 + unsigned long val : 32;
4411 + crtc_cv4_end_t f;
4412 +} crtc_cv4_end_u;
4413 +
4414 +typedef struct _crtc_cv4_hpos_t {
4415 + unsigned long cv4_hstart : 10;
4416 + unsigned long : 6;
4417 + unsigned long cv4_hend : 10;
4418 + unsigned long : 6;
4419 + } crtc_cv4_hpos_t;
4420 +
4421 +typedef union {
4422 + unsigned long val : 32;
4423 + crtc_cv4_hpos_t f;
4424 +} crtc_cv4_hpos_u;
4425 +
4426 +typedef struct _crtc_eck_t {
4427 + unsigned long eck_freq1 : 3;
4428 + unsigned long eck_en : 1;
4429 + unsigned long : 28;
4430 + } crtc_eck_t;
4431 +
4432 +typedef union {
4433 + unsigned long val : 32;
4434 + crtc_eck_t f;
4435 +} crtc_eck_u;
4436 +
4437 +typedef struct _refresh_cntl_t {
4438 + unsigned long ref_frame : 3;
4439 + unsigned long nref_frame : 5;
4440 + unsigned long ref_cntl : 1;
4441 + unsigned long stop_sm_nref : 1;
4442 + unsigned long stop_req_nref : 1;
4443 + unsigned long : 21;
4444 + } refresh_cntl_t;
4445 +
4446 +typedef union {
4447 + unsigned long val : 32;
4448 + refresh_cntl_t f;
4449 +} refresh_cntl_u;
4450 +
4451 +typedef struct _genlcd_cntl3_t {
4452 + unsigned long ps1_oe : 1;
4453 + unsigned long ps1_pd : 1;
4454 + unsigned long ps2_oe : 1;
4455 + unsigned long ps2_pd : 1;
4456 + unsigned long rev2_oe : 1;
4457 + unsigned long rev2_pd : 1;
4458 + unsigned long awl_oe : 1;
4459 + unsigned long awl_pd : 1;
4460 + unsigned long dinv_oe : 1;
4461 + unsigned long dinv_pd : 1;
4462 + unsigned long psk_out : 1;
4463 + unsigned long psd_out : 1;
4464 + unsigned long eck_out : 1;
4465 + unsigned long cv4_out : 1;
4466 + unsigned long ps1_out : 1;
4467 + unsigned long ps2_out : 1;
4468 + unsigned long rev_out : 1;
4469 + unsigned long rev2_out : 1;
4470 + unsigned long : 14;
4471 + } genlcd_cntl3_t;
4472 +
4473 +typedef union {
4474 + unsigned long val : 32;
4475 + genlcd_cntl3_t f;
4476 +} genlcd_cntl3_u;
4477 +
4478 +typedef struct _gpio_data2_t {
4479 + unsigned long gio2_out : 16;
4480 + unsigned long gio2_in : 16;
4481 + } gpio_data2_t;
4482 +
4483 +typedef union {
4484 + unsigned long val : 32;
4485 + gpio_data2_t f;
4486 +} gpio_data2_u;
4487 +
4488 +typedef struct _gpio_cntl3_t {
4489 + unsigned long gio2_pd : 16;
4490 + unsigned long gio2_schmen : 16;
4491 + } gpio_cntl3_t;
4492 +
4493 +typedef union {
4494 + unsigned long val : 32;
4495 + gpio_cntl3_t f;
4496 +} gpio_cntl3_u;
4497 +
4498 +typedef struct _gpio_cntl4_t {
4499 + unsigned long gio2_oe : 16;
4500 + unsigned long : 16;
4501 + } gpio_cntl4_t;
4502 +
4503 +typedef union {
4504 + unsigned long val : 32;
4505 + gpio_cntl4_t f;
4506 +} gpio_cntl4_u;
4507 +
4508 +typedef struct _chip_strap_t {
4509 + unsigned long config_strap : 8;
4510 + unsigned long pkg_strap : 1;
4511 + unsigned long : 23;
4512 + } chip_strap_t;
4513 +
4514 +typedef union {
4515 + unsigned long val : 32;
4516 + chip_strap_t f;
4517 +} chip_strap_u;
4518 +
4519 +typedef struct _disp_debug2_t {
4520 + unsigned long disp_debug2 : 32;
4521 + } disp_debug2_t;
4522 +
4523 +typedef union {
4524 + unsigned long val : 32;
4525 + disp_debug2_t f;
4526 +} disp_debug2_u;
4527 +
4528 +typedef struct _debug_bus_cntl_t {
4529 + unsigned long debug_testmux : 4;
4530 + unsigned long debug_testsel : 4;
4531 + unsigned long debug_gioa_sel : 2;
4532 + unsigned long debug_giob_sel : 2;
4533 + unsigned long debug_clk_sel : 1;
4534 + unsigned long debug_clk_inv : 1;
4535 + unsigned long : 2;
4536 + unsigned long debug_bus : 16;
4537 + } debug_bus_cntl_t;
4538 +
4539 +typedef union {
4540 + unsigned long val : 32;
4541 + debug_bus_cntl_t f;
4542 +} debug_bus_cntl_u;
4543 +
4544 +typedef struct _gamma_value1_t {
4545 + unsigned long gamma1 : 8;
4546 + unsigned long gamma2 : 8;
4547 + unsigned long gamma3 : 8;
4548 + unsigned long gamma4 : 8;
4549 + } gamma_value1_t;
4550 +
4551 +typedef union {
4552 + unsigned long val : 32;
4553 + gamma_value1_t f;
4554 +} gamma_value1_u;
4555 +
4556 +typedef struct _gamma_value2_t {
4557 + unsigned long gamma5 : 8;
4558 + unsigned long gamma6 : 8;
4559 + unsigned long gamma7 : 8;
4560 + unsigned long gamma8 : 8;
4561 + } gamma_value2_t;
4562 +
4563 +typedef union {
4564 + unsigned long val : 32;
4565 + gamma_value2_t f;
4566 +} gamma_value2_u;
4567 +
4568 +typedef struct _gamma_slope_t {
4569 + unsigned long slope1 : 3;
4570 + unsigned long slope2 : 3;
4571 + unsigned long slope3 : 3;
4572 + unsigned long slope4 : 3;
4573 + unsigned long slope5 : 3;
4574 + unsigned long slope6 : 3;
4575 + unsigned long slope7 : 3;
4576 + unsigned long slope8 : 3;
4577 + unsigned long : 8;
4578 + } gamma_slope_t;
4579 +
4580 +typedef union {
4581 + unsigned long val : 32;
4582 + gamma_slope_t f;
4583 +} gamma_slope_u;
4584 +
4585 +typedef struct _gen_status_t {
4586 + unsigned long status : 16;
4587 + unsigned long : 16;
4588 + } gen_status_t;
4589 +
4590 +typedef union {
4591 + unsigned long val : 32;
4592 + gen_status_t f;
4593 +} gen_status_u;
4594 +
4595 +typedef struct _hw_int_t {
4596 + unsigned long hwint1_pos : 5;
4597 + unsigned long hwint2_pos : 5;
4598 + unsigned long hwint1_pol : 1;
4599 + unsigned long hwint2_pol : 1;
4600 + unsigned long hwint1_en_db : 1;
4601 + unsigned long hwint2_en_db : 1;
4602 + unsigned long : 18;
4603 + } hw_int_t;
4604 +
4605 +typedef union {
4606 + unsigned long val : 32;
4607 + hw_int_t f;
4608 +} hw_int_u;
4609 +
4610 +typedef struct _dst_offset_t {
4611 + unsigned long dst_offset : 24;
4612 + unsigned long : 8;
4613 + } dst_offset_t;
4614 +
4615 +typedef union {
4616 + unsigned long val : 32;
4617 + dst_offset_t f;
4618 +} dst_offset_u;
4619 +
4620 +typedef struct _dst_pitch_t {
4621 + unsigned long dst_pitch : 14;
4622 + unsigned long mc_dst_pitch_mul : 2;
4623 + unsigned long : 16;
4624 + } dst_pitch_t;
4625 +
4626 +typedef union {
4627 + unsigned long val : 32;
4628 + dst_pitch_t f;
4629 +} dst_pitch_u;
4630 +
4631 +typedef struct _dst_pitch_offset_t {
4632 + unsigned long dst_offset : 20;
4633 + unsigned long dst_pitch : 10;
4634 + unsigned long mc_dst_pitch_mul : 2;
4635 + } dst_pitch_offset_t;
4636 +
4637 +typedef union {
4638 + unsigned long val : 32;
4639 + dst_pitch_offset_t f;
4640 +} dst_pitch_offset_u;
4641 +
4642 +typedef struct _dst_x_t {
4643 + unsigned long dst_x : 14;
4644 + unsigned long : 18;
4645 + } dst_x_t;
4646 +
4647 +typedef union {
4648 + unsigned long val : 32;
4649 + dst_x_t f;
4650 +} dst_x_u;
4651 +
4652 +typedef struct _dst_y_t {
4653 + unsigned long dst_y : 14;
4654 + unsigned long : 18;
4655 + } dst_y_t;
4656 +
4657 +typedef union {
4658 + unsigned long val : 32;
4659 + dst_y_t f;
4660 +} dst_y_u;
4661 +
4662 +typedef struct _dst_x_y_t {
4663 + unsigned long dst_y : 14;
4664 + unsigned long : 2;
4665 + unsigned long dst_x : 14;
4666 + unsigned long : 2;
4667 + } dst_x_y_t;
4668 +
4669 +typedef union {
4670 + unsigned long val : 32;
4671 + dst_x_y_t f;
4672 +} dst_x_y_u;
4673 +
4674 +typedef struct _dst_y_x_t {
4675 + unsigned long dst_x : 14;
4676 + unsigned long : 2;
4677 + unsigned long dst_y : 14;
4678 + unsigned long : 2;
4679 + } dst_y_x_t;
4680 +
4681 +typedef union {
4682 + unsigned long val : 32;
4683 + dst_y_x_t f;
4684 +} dst_y_x_u;
4685 +
4686 +typedef struct _dst_width_t {
4687 + unsigned long dst_width_b0 : 8;
4688 + unsigned long dst_width_b1 : 6;
4689 + unsigned long : 18;
4690 + } dst_width_t;
4691 +
4692 +typedef union {
4693 + unsigned long val : 32;
4694 + dst_width_t f;
4695 +} dst_width_u;
4696 +
4697 +typedef struct _dst_height_t {
4698 + unsigned long dst_height : 14;
4699 + unsigned long : 18;
4700 + } dst_height_t;
4701 +
4702 +typedef union {
4703 + unsigned long val : 32;
4704 + dst_height_t f;
4705 +} dst_height_u;
4706 +
4707 +typedef struct _dst_width_height_t {
4708 + unsigned long dst_height : 14;
4709 + unsigned long : 2;
4710 + unsigned long dst_width_b0 : 8;
4711 + unsigned long dst_width_b1 : 6;
4712 + unsigned long : 2;
4713 + } dst_width_height_t;
4714 +
4715 +typedef union {
4716 + unsigned long val : 32;
4717 + dst_width_height_t f;
4718 +} dst_width_height_u;
4719 +
4720 +typedef struct _dst_height_width_t {
4721 + unsigned long dst_width_b0 : 8;
4722 + unsigned long dst_width_b1 : 6;
4723 + unsigned long : 2;
4724 + unsigned long dst_height : 14;
4725 + unsigned long : 2;
4726 + } dst_height_width_t;
4727 +
4728 +typedef union {
4729 + unsigned long val : 32;
4730 + dst_height_width_t f;
4731 +} dst_height_width_u;
4732 +
4733 +typedef struct _dst_height_width_8_t {
4734 + unsigned long : 16;
4735 + unsigned long dst_width_b0 : 8;
4736 + unsigned long dst_height : 8;
4737 + } dst_height_width_8_t;
4738 +
4739 +typedef union {
4740 + unsigned long val : 32;
4741 + dst_height_width_8_t f;
4742 +} dst_height_width_8_u;
4743 +
4744 +typedef struct _dst_height_y_t {
4745 + unsigned long dst_y : 14;
4746 + unsigned long : 2;
4747 + unsigned long dst_height : 14;
4748 + unsigned long : 2;
4749 + } dst_height_y_t;
4750 +
4751 +typedef union {
4752 + unsigned long val : 32;
4753 + dst_height_y_t f;
4754 +} dst_height_y_u;
4755 +
4756 +typedef struct _dst_width_x_t {
4757 + unsigned long dst_x : 14;
4758 + unsigned long : 2;
4759 + unsigned long dst_width_b0 : 8;
4760 + unsigned long dst_width_b1 : 6;
4761 + unsigned long : 2;
4762 + } dst_width_x_t;
4763 +
4764 +typedef union {
4765 + unsigned long val : 32;
4766 + dst_width_x_t f;
4767 +} dst_width_x_u;
4768 +
4769 +typedef struct _dst_width_x_incy_t {
4770 + unsigned long dst_x : 14;
4771 + unsigned long : 2;
4772 + unsigned long dst_width_b0 : 8;
4773 + unsigned long dst_width_b1 : 6;
4774 + unsigned long : 2;
4775 + } dst_width_x_incy_t;
4776 +
4777 +typedef union {
4778 + unsigned long val : 32;
4779 + dst_width_x_incy_t f;
4780 +} dst_width_x_incy_u;
4781 +
4782 +typedef struct _dst_line_start_t {
4783 + unsigned long dst_start_x : 14;
4784 + unsigned long : 2;
4785 + unsigned long dst_start_y : 14;
4786 + unsigned long : 2;
4787 + } dst_line_start_t;
4788 +
4789 +typedef union {
4790 + unsigned long val : 32;
4791 + dst_line_start_t f;
4792 +} dst_line_start_u;
4793 +
4794 +typedef struct _dst_line_end_t {
4795 + unsigned long dst_end_x : 14;
4796 + unsigned long : 2;
4797 + unsigned long dst_end_y_b0 : 8;
4798 + unsigned long dst_end_y_b1 : 6;
4799 + unsigned long : 2;
4800 + } dst_line_end_t;
4801 +
4802 +typedef union {
4803 + unsigned long val : 32;
4804 + dst_line_end_t f;
4805 +} dst_line_end_u;
4806 +
4807 +typedef struct _brush_offset_t {
4808 + unsigned long brush_offset : 24;
4809 + unsigned long : 8;
4810 + } brush_offset_t;
4811 +
4812 +typedef union {
4813 + unsigned long val : 32;
4814 + brush_offset_t f;
4815 +} brush_offset_u;
4816 +
4817 +typedef struct _brush_y_x_t {
4818 + unsigned long brush_x : 5;
4819 + unsigned long : 3;
4820 + unsigned long brush_y : 3;
4821 + unsigned long : 21;
4822 + } brush_y_x_t;
4823 +
4824 +typedef union {
4825 + unsigned long val : 32;
4826 + brush_y_x_t f;
4827 +} brush_y_x_u;
4828 +
4829 +typedef struct _dp_brush_frgd_clr_t {
4830 + unsigned long dp_brush_frgd_clr : 32;
4831 + } dp_brush_frgd_clr_t;
4832 +
4833 +typedef union {
4834 + unsigned long val : 32;
4835 + dp_brush_frgd_clr_t f;
4836 +} dp_brush_frgd_clr_u;
4837 +
4838 +typedef struct _dp_brush_bkgd_clr_t {
4839 + unsigned long dp_brush_bkgd_clr : 32;
4840 + } dp_brush_bkgd_clr_t;
4841 +
4842 +typedef union {
4843 + unsigned long val : 32;
4844 + dp_brush_bkgd_clr_t f;
4845 +} dp_brush_bkgd_clr_u;
4846 +
4847 +typedef struct _src2_offset_t {
4848 + unsigned long src2_offset : 24;
4849 + unsigned long : 8;
4850 + } src2_offset_t;
4851 +
4852 +typedef union {
4853 + unsigned long val : 32;
4854 + src2_offset_t f;
4855 +} src2_offset_u;
4856 +
4857 +typedef struct _src2_pitch_t {
4858 + unsigned long src2_pitch : 14;
4859 + unsigned long src2_pitch_mul : 2;
4860 + unsigned long : 16;
4861 + } src2_pitch_t;
4862 +
4863 +typedef union {
4864 + unsigned long val : 32;
4865 + src2_pitch_t f;
4866 +} src2_pitch_u;
4867 +
4868 +typedef struct _src2_pitch_offset_t {
4869 + unsigned long src2_offset : 20;
4870 + unsigned long : 2;
4871 + unsigned long src2_pitch : 8;
4872 + unsigned long src2_pitch_mul : 2;
4873 + } src2_pitch_offset_t;
4874 +
4875 +typedef union {
4876 + unsigned long val : 32;
4877 + src2_pitch_offset_t f;
4878 +} src2_pitch_offset_u;
4879 +
4880 +typedef struct _src2_x_t {
4881 + unsigned long src_x : 14;
4882 + unsigned long : 18;
4883 + } src2_x_t;
4884 +
4885 +typedef union {
4886 + unsigned long val : 32;
4887 + src2_x_t f;
4888 +} src2_x_u;
4889 +
4890 +typedef struct _src2_y_t {
4891 + unsigned long src_y : 14;
4892 + unsigned long : 18;
4893 + } src2_y_t;
4894 +
4895 +typedef union {
4896 + unsigned long val : 32;
4897 + src2_y_t f;
4898 +} src2_y_u;
4899 +
4900 +typedef struct _src2_x_y_t {
4901 + unsigned long src_y : 14;
4902 + unsigned long : 2;
4903 + unsigned long src_x : 14;
4904 + unsigned long : 2;
4905 + } src2_x_y_t;
4906 +
4907 +typedef union {
4908 + unsigned long val : 32;
4909 + src2_x_y_t f;
4910 +} src2_x_y_u;
4911 +
4912 +typedef struct _src2_width_t {
4913 + unsigned long src2_width : 14;
4914 + unsigned long : 18;
4915 + } src2_width_t;
4916 +
4917 +typedef union {
4918 + unsigned long val : 32;
4919 + src2_width_t f;
4920 +} src2_width_u;
4921 +
4922 +typedef struct _src2_height_t {
4923 + unsigned long src2_height : 14;
4924 + unsigned long : 18;
4925 + } src2_height_t;
4926 +
4927 +typedef union {
4928 + unsigned long val : 32;
4929 + src2_height_t f;
4930 +} src2_height_u;
4931 +
4932 +typedef struct _src2_inc_t {
4933 + unsigned long src2_xinc : 6;
4934 + unsigned long : 2;
4935 + unsigned long src2_yinc : 6;
4936 + unsigned long : 18;
4937 + } src2_inc_t;
4938 +
4939 +typedef union {
4940 + unsigned long val : 32;
4941 + src2_inc_t f;
4942 +} src2_inc_u;
4943 +
4944 +typedef struct _src_offset_t {
4945 + unsigned long src_offset : 24;
4946 + unsigned long : 8;
4947 + } src_offset_t;
4948 +
4949 +typedef union {
4950 + unsigned long val : 32;
4951 + src_offset_t f;
4952 +} src_offset_u;
4953 +
4954 +typedef struct _src_pitch_t {
4955 + unsigned long src_pitch : 14;
4956 + unsigned long src_pitch_mul : 2;
4957 + unsigned long : 16;
4958 + } src_pitch_t;
4959 +
4960 +typedef union {
4961 + unsigned long val : 32;
4962 + src_pitch_t f;
4963 +} src_pitch_u;
4964 +
4965 +typedef struct _src_pitch_offset_t {
4966 + unsigned long src_offset : 20;
4967 + unsigned long src_pitch : 10;
4968 + unsigned long src_pitch_mul : 2;
4969 + } src_pitch_offset_t;
4970 +
4971 +typedef union {
4972 + unsigned long val : 32;
4973 + src_pitch_offset_t f;
4974 +} src_pitch_offset_u;
4975 +
4976 +typedef struct _src_x_t {
4977 + unsigned long src_x : 14;
4978 + unsigned long : 18;
4979 + } src_x_t;
4980 +
4981 +typedef union {
4982 + unsigned long val : 32;
4983 + src_x_t f;
4984 +} src_x_u;
4985 +
4986 +typedef struct _src_y_t {
4987 + unsigned long src_y : 14;
4988 + unsigned long : 18;
4989 + } src_y_t;
4990 +
4991 +typedef union {
4992 + unsigned long val : 32;
4993 + src_y_t f;
4994 +} src_y_u;
4995 +
4996 +typedef struct _src_x_y_t {
4997 + unsigned long src_y : 14;
4998 + unsigned long : 2;
4999 + unsigned long src_x : 14;
5000 + unsigned long : 2;
5001 + } src_x_y_t;
5002 +
5003 +typedef union {
5004 + unsigned long val : 32;
5005 + src_x_y_t f;
5006 +} src_x_y_u;
5007 +
5008 +typedef struct _src_y_x_t {
5009 + unsigned long src_x : 14;
5010 + unsigned long : 2;
5011 + unsigned long src_y : 14;
5012 + unsigned long : 2;
5013 + } src_y_x_t;
5014 +
5015 +typedef union {
5016 + unsigned long val : 32;
5017 + src_y_x_t f;
5018 +} src_y_x_u;
5019 +
5020 +typedef struct _src_width_t {
5021 + unsigned long src_width : 14;
5022 + unsigned long : 18;
5023 + } src_width_t;
5024 +
5025 +typedef union {
5026 + unsigned long val : 32;
5027 + src_width_t f;
5028 +} src_width_u;
5029 +
5030 +typedef struct _src_height_t {
5031 + unsigned long src_height : 14;
5032 + unsigned long : 18;
5033 + } src_height_t;
5034 +
5035 +typedef union {
5036 + unsigned long val : 32;
5037 + src_height_t f;
5038 +} src_height_u;
5039 +
5040 +typedef struct _src_inc_t {
5041 + unsigned long src_xinc : 6;
5042 + unsigned long : 2;
5043 + unsigned long src_yinc : 6;
5044 + unsigned long : 18;
5045 + } src_inc_t;
5046 +
5047 +typedef union {
5048 + unsigned long val : 32;
5049 + src_inc_t f;
5050 +} src_inc_u;
5051 +
5052 +typedef struct _host_data0_t {
5053 + unsigned long host_data : 32;
5054 + } host_data0_t;
5055 +
5056 +typedef union {
5057 + unsigned long val : 32;
5058 + host_data0_t f;
5059 +} host_data0_u;
5060 +
5061 +typedef struct _host_data1_t {
5062 + unsigned long host_data : 32;
5063 + } host_data1_t;
5064 +
5065 +typedef union {
5066 + unsigned long val : 32;
5067 + host_data1_t f;
5068 +} host_data1_u;
5069 +
5070 +typedef struct _host_data2_t {
5071 + unsigned long host_data : 32;
5072 + } host_data2_t;
5073 +
5074 +typedef union {
5075 + unsigned long val : 32;
5076 + host_data2_t f;
5077 +} host_data2_u;
5078 +
5079 +typedef struct _host_data3_t {
5080 + unsigned long host_data : 32;
5081 + } host_data3_t;
5082 +
5083 +typedef union {
5084 + unsigned long val : 32;
5085 + host_data3_t f;
5086 +} host_data3_u;
5087 +
5088 +typedef struct _host_data4_t {
5089 + unsigned long host_data : 32;
5090 + } host_data4_t;
5091 +
5092 +typedef union {
5093 + unsigned long val : 32;
5094 + host_data4_t f;
5095 +} host_data4_u;
5096 +
5097 +typedef struct _host_data5_t {
5098 + unsigned long host_data : 32;
5099 + } host_data5_t;
5100 +
5101 +typedef union {
5102 + unsigned long val : 32;
5103 + host_data5_t f;
5104 +} host_data5_u;
5105 +
5106 +typedef struct _host_data6_t {
5107 + unsigned long host_data : 32;
5108 + } host_data6_t;
5109 +
5110 +typedef union {
5111 + unsigned long val : 32;
5112 + host_data6_t f;
5113 +} host_data6_u;
5114 +
5115 +typedef struct _host_data7_t {
5116 + unsigned long host_data : 32;
5117 + } host_data7_t;
5118 +
5119 +typedef union {
5120 + unsigned long val : 32;
5121 + host_data7_t f;
5122 +} host_data7_u;
5123 +
5124 +typedef struct _host_data_last_t {
5125 + unsigned long host_data_last : 32;
5126 + } host_data_last_t;
5127 +
5128 +typedef union {
5129 + unsigned long val : 32;
5130 + host_data_last_t f;
5131 +} host_data_last_u;
5132 +
5133 +typedef struct _dp_src_frgd_clr_t {
5134 + unsigned long dp_src_frgd_clr : 32;
5135 + } dp_src_frgd_clr_t;
5136 +
5137 +typedef union {
5138 + unsigned long val : 32;
5139 + dp_src_frgd_clr_t f;
5140 +} dp_src_frgd_clr_u;
5141 +
5142 +typedef struct _dp_src_bkgd_clr_t {
5143 + unsigned long dp_src_bkgd_clr : 32;
5144 + } dp_src_bkgd_clr_t;
5145 +
5146 +typedef union {
5147 + unsigned long val : 32;
5148 + dp_src_bkgd_clr_t f;
5149 +} dp_src_bkgd_clr_u;
5150 +
5151 +typedef struct _sc_left_t {
5152 + unsigned long sc_left : 14;
5153 + unsigned long : 18;
5154 + } sc_left_t;
5155 +
5156 +typedef union {
5157 + unsigned long val : 32;
5158 + sc_left_t f;
5159 +} sc_left_u;
5160 +
5161 +typedef struct _sc_right_t {
5162 + unsigned long sc_right : 14;
5163 + unsigned long : 18;
5164 + } sc_right_t;
5165 +
5166 +typedef union {
5167 + unsigned long val : 32;
5168 + sc_right_t f;
5169 +} sc_right_u;
5170 +
5171 +typedef struct _sc_top_t {
5172 + unsigned long sc_top : 14;
5173 + unsigned long : 18;
5174 + } sc_top_t;
5175 +
5176 +typedef union {
5177 + unsigned long val : 32;
5178 + sc_top_t f;
5179 +} sc_top_u;
5180 +
5181 +typedef struct _sc_bottom_t {
5182 + unsigned long sc_bottom : 14;
5183 + unsigned long : 18;
5184 + } sc_bottom_t;
5185 +
5186 +typedef union {
5187 + unsigned long val : 32;
5188 + sc_bottom_t f;
5189 +} sc_bottom_u;
5190 +
5191 +typedef struct _src_sc_right_t {
5192 + unsigned long sc_right : 14;
5193 + unsigned long : 18;
5194 + } src_sc_right_t;
5195 +
5196 +typedef union {
5197 + unsigned long val : 32;
5198 + src_sc_right_t f;
5199 +} src_sc_right_u;
5200 +
5201 +typedef struct _src_sc_bottom_t {
5202 + unsigned long sc_bottom : 14;
5203 + unsigned long : 18;
5204 + } src_sc_bottom_t;
5205 +
5206 +typedef union {
5207 + unsigned long val : 32;
5208 + src_sc_bottom_t f;
5209 +} src_sc_bottom_u;
5210 +
5211 +typedef struct _dp_cntl_t {
5212 + unsigned long dst_x_dir : 1;
5213 + unsigned long dst_y_dir : 1;
5214 + unsigned long src_x_dir : 1;
5215 + unsigned long src_y_dir : 1;
5216 + unsigned long dst_major_x : 1;
5217 + unsigned long src_major_x : 1;
5218 + unsigned long : 26;
5219 + } dp_cntl_t;
5220 +
5221 +typedef union {
5222 + unsigned long val : 32;
5223 + dp_cntl_t f;
5224 +} dp_cntl_u;
5225 +
5226 +typedef struct _dp_cntl_dst_dir_t {
5227 + unsigned long : 15;
5228 + unsigned long dst_y_dir : 1;
5229 + unsigned long : 15;
5230 + unsigned long dst_x_dir : 1;
5231 + } dp_cntl_dst_dir_t;
5232 +
5233 +typedef union {
5234 + unsigned long val : 32;
5235 + dp_cntl_dst_dir_t f;
5236 +} dp_cntl_dst_dir_u;
5237 +
5238 +typedef struct _dp_datatype_t {
5239 + unsigned long dp_dst_datatype : 4;
5240 + unsigned long : 4;
5241 + unsigned long dp_brush_datatype : 4;
5242 + unsigned long dp_src2_type : 1;
5243 + unsigned long dp_src2_datatype : 3;
5244 + unsigned long dp_src_datatype : 3;
5245 + unsigned long : 11;
5246 + unsigned long dp_byte_pix_order : 1;
5247 + unsigned long : 1;
5248 + } dp_datatype_t;
5249 +
5250 +typedef union {
5251 + unsigned long val : 32;
5252 + dp_datatype_t f;
5253 +} dp_datatype_u;
5254 +
5255 +typedef struct _dp_mix_t {
5256 + unsigned long : 8;
5257 + unsigned long dp_src_source : 3;
5258 + unsigned long dp_src2_source : 3;
5259 + unsigned long : 2;
5260 + unsigned long dp_rop3 : 8;
5261 + unsigned long dp_op : 1;
5262 + unsigned long : 7;
5263 + } dp_mix_t;
5264 +
5265 +typedef union {
5266 + unsigned long val : 32;
5267 + dp_mix_t f;
5268 +} dp_mix_u;
5269 +
5270 +typedef struct _dp_write_msk_t {
5271 + unsigned long dp_write_msk : 32;
5272 + } dp_write_msk_t;
5273 +
5274 +typedef union {
5275 + unsigned long val : 32;
5276 + dp_write_msk_t f;
5277 +} dp_write_msk_u;
5278 +
5279 +typedef struct _clr_cmp_clr_src_t {
5280 + unsigned long clr_cmp_clr_src : 32;
5281 + } clr_cmp_clr_src_t;
5282 +
5283 +typedef union {
5284 + unsigned long val : 32;
5285 + clr_cmp_clr_src_t f;
5286 +} clr_cmp_clr_src_u;
5287 +
5288 +typedef struct _clr_cmp_clr_dst_t {
5289 + unsigned long clr_cmp_clr_dst : 32;
5290 + } clr_cmp_clr_dst_t;
5291 +
5292 +typedef union {
5293 + unsigned long val : 32;
5294 + clr_cmp_clr_dst_t f;
5295 +} clr_cmp_clr_dst_u;
5296 +
5297 +typedef struct _clr_cmp_cntl_t {
5298 + unsigned long clr_cmp_fcn_src : 3;
5299 + unsigned long : 5;
5300 + unsigned long clr_cmp_fcn_dst : 3;
5301 + unsigned long : 13;
5302 + unsigned long clr_cmp_src : 2;
5303 + unsigned long : 6;
5304 + } clr_cmp_cntl_t;
5305 +
5306 +typedef union {
5307 + unsigned long val : 32;
5308 + clr_cmp_cntl_t f;
5309 +} clr_cmp_cntl_u;
5310 +
5311 +typedef struct _clr_cmp_msk_t {
5312 + unsigned long clr_cmp_msk : 32;
5313 + } clr_cmp_msk_t;
5314 +
5315 +typedef union {
5316 + unsigned long val : 32;
5317 + clr_cmp_msk_t f;
5318 +} clr_cmp_msk_u;
5319 +
5320 +typedef struct _default_pitch_offset_t {
5321 + unsigned long default_offset : 20;
5322 + unsigned long default_pitch : 10;
5323 + unsigned long : 2;
5324 + } default_pitch_offset_t;
5325 +
5326 +typedef union {
5327 + unsigned long val : 32;
5328 + default_pitch_offset_t f;
5329 +} default_pitch_offset_u;
5330 +
5331 +typedef struct _default_sc_bottom_right_t {
5332 + unsigned long default_sc_right : 14;
5333 + unsigned long : 2;
5334 + unsigned long default_sc_bottom : 14;
5335 + unsigned long : 2;
5336 + } default_sc_bottom_right_t;
5337 +
5338 +typedef union {
5339 + unsigned long val : 32;
5340 + default_sc_bottom_right_t f;
5341 +} default_sc_bottom_right_u;
5342 +
5343 +typedef struct _default2_sc_bottom_right_t {
5344 + unsigned long default_sc_right : 14;
5345 + unsigned long : 2;
5346 + unsigned long default_sc_bottom : 14;
5347 + unsigned long : 2;
5348 + } default2_sc_bottom_right_t;
5349 +
5350 +typedef union {
5351 + unsigned long val : 32;
5352 + default2_sc_bottom_right_t f;
5353 +} default2_sc_bottom_right_u;
5354 +
5355 +typedef struct _ref1_pitch_offset_t {
5356 + unsigned long offset : 20;
5357 + unsigned long : 2;
5358 + unsigned long pitch : 8;
5359 + unsigned long : 2;
5360 + } ref1_pitch_offset_t;
5361 +
5362 +typedef union {
5363 + unsigned long val : 32;
5364 + ref1_pitch_offset_t f;
5365 +} ref1_pitch_offset_u;
5366 +
5367 +typedef struct _ref2_pitch_offset_t {
5368 + unsigned long offset : 20;
5369 + unsigned long : 2;
5370 + unsigned long pitch : 8;
5371 + unsigned long : 2;
5372 + } ref2_pitch_offset_t;
5373 +
5374 +typedef union {
5375 + unsigned long val : 32;
5376 + ref2_pitch_offset_t f;
5377 +} ref2_pitch_offset_u;
5378 +
5379 +typedef struct _ref3_pitch_offset_t {
5380 + unsigned long offset : 20;
5381 + unsigned long : 2;
5382 + unsigned long pitch : 8;
5383 + unsigned long : 2;
5384 + } ref3_pitch_offset_t;
5385 +
5386 +typedef union {
5387 + unsigned long val : 32;
5388 + ref3_pitch_offset_t f;
5389 +} ref3_pitch_offset_u;
5390 +
5391 +typedef struct _ref4_pitch_offset_t {
5392 + unsigned long offset : 20;
5393 + unsigned long : 2;
5394 + unsigned long pitch : 8;
5395 + unsigned long : 2;
5396 + } ref4_pitch_offset_t;
5397 +
5398 +typedef union {
5399 + unsigned long val : 32;
5400 + ref4_pitch_offset_t f;
5401 +} ref4_pitch_offset_u;
5402 +
5403 +typedef struct _ref5_pitch_offset_t {
5404 + unsigned long offset : 20;
5405 + unsigned long : 2;
5406 + unsigned long pitch : 8;
5407 + unsigned long : 2;
5408 + } ref5_pitch_offset_t;
5409 +
5410 +typedef union {
5411 + unsigned long val : 32;
5412 + ref5_pitch_offset_t f;
5413 +} ref5_pitch_offset_u;
5414 +
5415 +typedef struct _ref6_pitch_offset_t {
5416 + unsigned long offset : 20;
5417 + unsigned long : 2;
5418 + unsigned long pitch : 8;
5419 + unsigned long : 2;
5420 + } ref6_pitch_offset_t;
5421 +
5422 +typedef union {
5423 + unsigned long val : 32;
5424 + ref6_pitch_offset_t f;
5425 +} ref6_pitch_offset_u;
5426 +
5427 +typedef struct _dp_gui_master_cntl_t {
5428 + unsigned long gmc_src_pitch_offset_cntl : 1;
5429 + unsigned long gmc_dst_pitch_offset_cntl : 1;
5430 + unsigned long gmc_src_clipping : 1;
5431 + unsigned long gmc_dst_clipping : 1;
5432 + unsigned long gmc_brush_datatype : 4;
5433 + unsigned long gmc_dst_datatype : 4;
5434 + unsigned long gmc_src_datatype : 3;
5435 + unsigned long gmc_byte_pix_order : 1;
5436 + unsigned long gmc_default_sel : 1;
5437 + unsigned long gmc_rop3 : 8;
5438 + unsigned long gmc_dp_src_source : 3;
5439 + unsigned long gmc_clr_cmp_fcn_dis : 1;
5440 + unsigned long : 1;
5441 + unsigned long gmc_wr_msk_dis : 1;
5442 + unsigned long gmc_dp_op : 1;
5443 + } dp_gui_master_cntl_t;
5444 +
5445 +typedef union {
5446 + unsigned long val : 32;
5447 + dp_gui_master_cntl_t f;
5448 +} dp_gui_master_cntl_u;
5449 +
5450 +typedef struct _sc_top_left_t {
5451 + unsigned long sc_left : 14;
5452 + unsigned long : 2;
5453 + unsigned long sc_top : 14;
5454 + unsigned long : 2;
5455 + } sc_top_left_t;
5456 +
5457 +typedef union {
5458 + unsigned long val : 32;
5459 + sc_top_left_t f;
5460 +} sc_top_left_u;
5461 +
5462 +typedef struct _sc_bottom_right_t {
5463 + unsigned long sc_right : 14;
5464 + unsigned long : 2;
5465 + unsigned long sc_bottom : 14;
5466 + unsigned long : 2;
5467 + } sc_bottom_right_t;
5468 +
5469 +typedef union {
5470 + unsigned long val : 32;
5471 + sc_bottom_right_t f;
5472 +} sc_bottom_right_u;
5473 +
5474 +typedef struct _src_sc_top_left_t {
5475 + unsigned short sc_left;
5476 + unsigned short sc_top;
5477 +} src_sc_top_left_t;
5478 +
5479 +typedef union {
5480 + unsigned long val : 32;
5481 + src_sc_top_left_t f;
5482 +} src_sc_top_left_u;
5483 +
5484 +typedef struct _src_sc_bottom_right_t {
5485 + unsigned long sc_right : 14;
5486 + unsigned long : 2;
5487 + unsigned long sc_bottom : 14;
5488 + unsigned long : 2;
5489 + } src_sc_bottom_right_t;
5490 +
5491 +typedef union {
5492 + unsigned long val : 32;
5493 + src_sc_bottom_right_t f;
5494 +} src_sc_bottom_right_u;
5495 +
5496 +typedef struct _global_alpha_t {
5497 + unsigned long alpha_r : 8;
5498 + unsigned long alpha_g : 8;
5499 + unsigned long alpha_b : 8;
5500 + unsigned long alpha_a : 8;
5501 +} global_alpha_t;
5502 +
5503 +typedef union {
5504 + unsigned long val : 32;
5505 + global_alpha_t f;
5506 +} global_alpha_u;
5507 +
5508 +typedef struct _filter_coef_t {
5509 + unsigned long c_4 : 4;
5510 + unsigned long c_3 : 4;
5511 + unsigned long c_2 : 4;
5512 + unsigned long c_1 : 4;
5513 + unsigned long c1 : 4;
5514 + unsigned long c2 : 4;
5515 + unsigned long c3 : 4;
5516 + unsigned long c4 : 4;
5517 +} filter_coef_t;
5518 +
5519 +typedef union {
5520 + unsigned long val : 32;
5521 + filter_coef_t f;
5522 +} filter_coef_u;
5523 +
5524 +typedef struct _mvc_cntl_start_t {
5525 + unsigned long mc_cntl_src_1_index : 4;
5526 + unsigned long mc_cntl_dst_offset : 20;
5527 + unsigned long mc_dst_pitch_mul : 2;
5528 + unsigned long mc_cntl_src_2_index : 3;
5529 + unsigned long mc_cntl_width_height_sel : 3;
5530 +} mvc_cntl_start_t;
5531 +
5532 +typedef union {
5533 + unsigned long val : 32;
5534 + mvc_cntl_start_t f;
5535 +} mvc_cntl_start_u;
5536 +
5537 +typedef struct _e2_arithmetic_cntl_t {
5538 + unsigned long opcode : 5;
5539 + unsigned long shiftright : 4;
5540 + unsigned long clamp : 1;
5541 + unsigned long rounding : 2;
5542 + unsigned long filter_n : 3;
5543 + unsigned long : 1;
5544 + unsigned long srcblend_inv : 1;
5545 + unsigned long srcblend : 4;
5546 + unsigned long : 3;
5547 + unsigned long dstblend_inv : 1;
5548 + unsigned long dstblend : 4;
5549 + unsigned long dst_signed : 1;
5550 + unsigned long autoinc : 1;
5551 + unsigned long : 1;
5552 +} e2_arithmetic_cntl_t;
5553 +
5554 +typedef union {
5555 + unsigned long val : 32;
5556 + e2_arithmetic_cntl_t f;
5557 +} e2_arithmetic_cntl_u;
5558 +
5559 +typedef struct _debug0_t {
5560 + unsigned long debug0_r : 8;
5561 + unsigned long : 8;
5562 + unsigned long debug0_rw : 8;
5563 + unsigned long : 8;
5564 +} debug0_t;
5565 +
5566 +typedef union {
5567 + unsigned long val : 32;
5568 + debug0_t f;
5569 +} debug0_u;
5570 +
5571 +typedef struct _debug1_t {
5572 + unsigned long debug1_r : 8;
5573 + unsigned long : 8;
5574 + unsigned long debug1_rw : 8;
5575 + unsigned long : 8;
5576 +} debug1_t;
5577 +
5578 +typedef union {
5579 + unsigned long val : 32;
5580 + debug1_t f;
5581 +} debug1_u;
5582 +
5583 +typedef struct _debug2_t {
5584 + unsigned long debug2_r : 8;
5585 + unsigned long : 8;
5586 + unsigned long debug2_rw : 8;
5587 + unsigned long : 8;
5588 +} debug2_t;
5589 +
5590 +typedef union {
5591 + unsigned long val : 32;
5592 + debug2_t f;
5593 +} debug2_u;
5594 +
5595 +typedef struct _debug3_t {
5596 + unsigned long : 32;
5597 +} debug3_t;
5598 +
5599 +typedef union {
5600 + unsigned long val : 32;
5601 + debug3_t f;
5602 +} debug3_u;
5603 +
5604 +typedef struct _debug4_t {
5605 + unsigned long : 32;
5606 +} debug4_t;
5607 +
5608 +typedef union {
5609 + unsigned long val : 32;
5610 + debug4_t f;
5611 +} debug4_u;
5612 +
5613 +typedef struct _debug5_t {
5614 + unsigned long : 32;
5615 +} debug5_t;
5616 +
5617 +typedef union {
5618 + unsigned long val : 32;
5619 + debug5_t f;
5620 +} debug5_u;
5621 +
5622 +typedef struct _debug6_t {
5623 + unsigned long : 32;
5624 +} debug6_t;
5625 +
5626 +typedef union {
5627 + unsigned long val : 32;
5628 + debug6_t f;
5629 +} debug6_u;
5630 +
5631 +typedef struct _debug7_t {
5632 + unsigned long : 32;
5633 +} debug7_t;
5634 +
5635 +typedef union {
5636 + unsigned long val : 32;
5637 + debug7_t f;
5638 +} debug7_u;
5639 +
5640 +typedef struct _debug8_t {
5641 + unsigned long : 32;
5642 +} debug8_t;
5643 +
5644 +typedef union {
5645 + unsigned long val : 32;
5646 + debug8_t f;
5647 +} debug8_u;
5648 +
5649 +typedef struct _debug9_t {
5650 + unsigned long : 32;
5651 +} debug9_t;
5652 +
5653 +typedef union {
5654 + unsigned long val : 32;
5655 + debug9_t f;
5656 +} debug9_u;
5657 +
5658 +typedef struct _debug10_t {
5659 + unsigned long : 32;
5660 + } debug10_t;
5661 +
5662 +typedef union {
5663 + unsigned long val : 32;
5664 + debug10_t f;
5665 +} debug10_u;
5666 +
5667 +typedef struct _debug11_t {
5668 + unsigned long : 32;
5669 + } debug11_t;
5670 +
5671 +typedef union {
5672 + unsigned long val : 32;
5673 + debug11_t f;
5674 +} debug11_u;
5675 +
5676 +typedef struct _debug12_t {
5677 + unsigned long : 32;
5678 + } debug12_t;
5679 +
5680 +typedef union {
5681 + unsigned long val : 32;
5682 + debug12_t f;
5683 +} debug12_u;
5684 +
5685 +typedef struct _debug13_t {
5686 + unsigned long : 32;
5687 + } debug13_t;
5688 +
5689 +typedef union {
5690 + unsigned long val : 32;
5691 + debug13_t f;
5692 +} debug13_u;
5693 +
5694 +typedef struct _debug14_t {
5695 + unsigned long : 32;
5696 + } debug14_t;
5697 +
5698 +typedef union {
5699 + unsigned long val : 32;
5700 + debug14_t f;
5701 +} debug14_u;
5702 +
5703 +typedef struct _debug15_t {
5704 + unsigned long : 32;
5705 + } debug15_t;
5706 +
5707 +typedef union {
5708 + unsigned long val : 32;
5709 + debug15_t f;
5710 +} debug15_u;
5711 +
5712 +typedef struct _eng_cntl_t {
5713 + unsigned long erc_reg_rd_ws : 1;
5714 + unsigned long erc_reg_wr_ws : 1;
5715 + unsigned long erc_idle_reg_wr : 1;
5716 + unsigned long dis_engine_triggers : 1;
5717 + unsigned long dis_rop_src_uses_dst_w_h : 1;
5718 + unsigned long dis_src_uses_dst_dirmaj : 1;
5719 + unsigned long : 6;
5720 + unsigned long force_3dclk_when_2dclk : 1;
5721 + unsigned long : 19;
5722 + } eng_cntl_t;
5723 +
5724 +typedef union {
5725 + unsigned long val : 32;
5726 + eng_cntl_t f;
5727 +} eng_cntl_u;
5728 +
5729 +typedef struct _eng_perf_cnt_t {
5730 + unsigned long perf_cnt : 20;
5731 + unsigned long perf_sel : 4;
5732 + unsigned long perf_en : 1;
5733 + unsigned long : 3;
5734 + unsigned long perf_clr : 1;
5735 + unsigned long : 3;
5736 + } eng_perf_cnt_t;
5737 +
5738 +typedef union {
5739 + unsigned long val : 32;
5740 + eng_perf_cnt_t f;
5741 +} eng_perf_cnt_u;
5742 +
5743 +typedef struct _idct_runs_t {
5744 + unsigned long idct_runs_3 : 8;
5745 + unsigned long idct_runs_2 : 8;
5746 + unsigned long idct_runs_1 : 8;
5747 + unsigned long idct_runs_0 : 8;
5748 + } idct_runs_t;
5749 +
5750 +typedef union {
5751 + unsigned long val : 32;
5752 + idct_runs_t f;
5753 +} idct_runs_u;
5754 +
5755 +typedef struct _idct_levels_t {
5756 + unsigned long idct_level_hi : 16;
5757 + unsigned long idct_level_lo : 16;
5758 + } idct_levels_t;
5759 +
5760 +typedef union {
5761 + unsigned long val : 32;
5762 + idct_levels_t f;
5763 +} idct_levels_u;
5764 +
5765 +typedef struct _idct_control_t {
5766 + unsigned long idct_ctl_luma_rd_format : 2;
5767 + unsigned long idct_ctl_chroma_rd_format : 2;
5768 + unsigned long idct_ctl_scan_pattern : 1;
5769 + unsigned long idct_ctl_intra : 1;
5770 + unsigned long idct_ctl_flush : 1;
5771 + unsigned long idct_ctl_passthru : 1;
5772 + unsigned long idct_ctl_sw_reset : 1;
5773 + unsigned long idct_ctl_constreq : 1;
5774 + unsigned long idct_ctl_scramble : 1;
5775 + unsigned long idct_ctl_alt_scan : 1;
5776 + unsigned long : 20;
5777 + } idct_control_t;
5778 +
5779 +typedef union {
5780 + unsigned long val : 32;
5781 + idct_control_t f;
5782 +} idct_control_u;
5783 +
5784 +typedef struct _idct_auth_control_t {
5785 + unsigned long control_bits : 32;
5786 + } idct_auth_control_t;
5787 +
5788 +typedef union {
5789 + unsigned long val : 32;
5790 + idct_auth_control_t f;
5791 +} idct_auth_control_u;
5792 +
5793 +typedef struct _idct_auth_t {
5794 + unsigned long auth : 32;
5795 + } idct_auth_t;
5796 +
5797 +typedef union {
5798 + unsigned long val : 32;
5799 + idct_auth_t f;
5800 +} idct_auth_u;
5801 +
5802 +typedef struct _mem_cntl_t {
5803 + unsigned long : 1;
5804 + unsigned long en_mem_ch1 : 1;
5805 + unsigned long en_mem_ch2 : 1;
5806 + unsigned long int_mem_mapping : 1;
5807 + unsigned long : 28;
5808 + } mem_cntl_t;
5809 +
5810 +typedef union {
5811 + unsigned long val : 32;
5812 + mem_cntl_t f;
5813 +} mem_cntl_u;
5814 +
5815 +typedef struct _mem_arb_t {
5816 + unsigned long disp_time_slot : 4;
5817 + unsigned long disp_timer : 4;
5818 + unsigned long arb_option : 1;
5819 + unsigned long : 23;
5820 + } mem_arb_t;
5821 +
5822 +typedef union {
5823 + unsigned long val : 32;
5824 + mem_arb_t f;
5825 +} mem_arb_u;
5826 +
5827 +typedef struct _mc_fb_location_t {
5828 + unsigned long mc_fb_start : 16;
5829 + unsigned long mc_fb_top : 16;
5830 + } mc_fb_location_t;
5831 +
5832 +typedef union {
5833 + unsigned long val : 32;
5834 + mc_fb_location_t f;
5835 +} mc_fb_location_u;
5836 +
5837 +typedef struct _mem_ext_cntl_t {
5838 + unsigned long mem_ext_enable : 1;
5839 + unsigned long mem_ap_enable : 1;
5840 + unsigned long mem_addr_mapping : 2;
5841 + unsigned long mem_wdoe_cntl : 2;
5842 + unsigned long mem_wdoe_extend : 1;
5843 + unsigned long : 1;
5844 + unsigned long mem_page_timer : 8;
5845 + unsigned long mem_dynamic_cke : 1;
5846 + unsigned long mem_sdram_tri_en : 1;
5847 + unsigned long mem_self_refresh_en : 1;
5848 + unsigned long mem_power_down : 1;
5849 + unsigned long mem_hw_power_down_en : 1;
5850 + unsigned long mem_power_down_stat : 1;
5851 + unsigned long : 3;
5852 + unsigned long mem_pd_mck : 1;
5853 + unsigned long mem_pd_ma : 1;
5854 + unsigned long mem_pd_mdq : 1;
5855 + unsigned long mem_tristate_mck : 1;
5856 + unsigned long mem_tristate_ma : 1;
5857 + unsigned long mem_tristate_mcke : 1;
5858 + unsigned long mem_invert_mck : 1;
5859 + } mem_ext_cntl_t;
5860 +
5861 +typedef union {
5862 + unsigned long val : 32;
5863 + mem_ext_cntl_t f;
5864 +} mem_ext_cntl_u;
5865 +
5866 +typedef struct _mc_ext_mem_location_t {
5867 + unsigned long mc_ext_mem_start : 16;
5868 + unsigned long mc_ext_mem_top : 16;
5869 + } mc_ext_mem_location_t;
5870 +
5871 +typedef union {
5872 + unsigned long val : 32;
5873 + mc_ext_mem_location_t f;
5874 +} mc_ext_mem_location_u;
5875 +
5876 +typedef struct _mem_ext_timing_cntl_t {
5877 + unsigned long mem_trp : 2;
5878 + unsigned long mem_trcd : 2;
5879 + unsigned long mem_tras : 3;
5880 + unsigned long : 1;
5881 + unsigned long mem_trrd : 2;
5882 + unsigned long mem_tr2w : 2;
5883 + unsigned long mem_twr : 2;
5884 + unsigned long : 4;
5885 + unsigned long mem_twr_mode : 1;
5886 + unsigned long : 1;
5887 + unsigned long mem_refresh_dis : 1;
5888 + unsigned long : 3;
5889 + unsigned long mem_refresh_rate : 8;
5890 + } mem_ext_timing_cntl_t;
5891 +
5892 +typedef union {
5893 + unsigned long val : 32;
5894 + mem_ext_timing_cntl_t f;
5895 +} mem_ext_timing_cntl_u;
5896 +
5897 +typedef struct _mem_sdram_mode_reg_t {
5898 + unsigned long mem_mode_reg : 14;
5899 + unsigned long : 2;
5900 + unsigned long mem_read_latency : 2;
5901 + unsigned long mem_schmen_latency : 2;
5902 + unsigned long mem_cas_latency : 2;
5903 + unsigned long mem_schmen_extend : 1;
5904 + unsigned long : 8;
5905 + unsigned long mem_sdram_reset : 1;
5906 + } mem_sdram_mode_reg_t;
5907 +
5908 +typedef union {
5909 + unsigned long val : 32;
5910 + mem_sdram_mode_reg_t f;
5911 +} mem_sdram_mode_reg_u;
5912 +
5913 +typedef struct _mem_io_cntl_t {
5914 + unsigned long mem_sn_mck : 4;
5915 + unsigned long mem_sn_ma : 4;
5916 + unsigned long mem_sn_mdq : 4;
5917 + unsigned long mem_srn_mck : 1;
5918 + unsigned long mem_srn_ma : 1;
5919 + unsigned long mem_srn_mdq : 1;
5920 + unsigned long : 1;
5921 + unsigned long mem_sp_mck : 4;
5922 + unsigned long mem_sp_ma : 4;
5923 + unsigned long mem_sp_mdq : 4;
5924 + unsigned long mem_srp_mck : 1;
5925 + unsigned long mem_srp_ma : 1;
5926 + unsigned long mem_srp_mdq : 1;
5927 + unsigned long : 1;
5928 + } mem_io_cntl_t;
5929 +
5930 +typedef union {
5931 + unsigned long val : 32;
5932 + mem_io_cntl_t f;
5933 +} mem_io_cntl_u;
5934 +
5935 +typedef struct _mc_debug_t {
5936 + unsigned long mc_debug : 32;
5937 + } mc_debug_t;
5938 +
5939 +typedef union {
5940 + unsigned long val : 32;
5941 + mc_debug_t f;
5942 +} mc_debug_u;
5943 +
5944 +typedef struct _mc_bist_ctrl_t {
5945 + unsigned long mc_bist_ctrl : 32;
5946 + } mc_bist_ctrl_t;
5947 +
5948 +typedef union {
5949 + unsigned long val : 32;
5950 + mc_bist_ctrl_t f;
5951 +} mc_bist_ctrl_u;
5952 +
5953 +typedef struct _mc_bist_collar_read_t {
5954 + unsigned long mc_bist_collar_read : 32;
5955 + } mc_bist_collar_read_t;
5956 +
5957 +typedef union {
5958 + unsigned long val : 32;
5959 + mc_bist_collar_read_t f;
5960 +} mc_bist_collar_read_u;
5961 +
5962 +typedef struct _tc_mismatch_t {
5963 + unsigned long tc_mismatch : 24;
5964 + unsigned long : 8;
5965 + } tc_mismatch_t;
5966 +
5967 +typedef union {
5968 + unsigned long val : 32;
5969 + tc_mismatch_t f;
5970 +} tc_mismatch_u;
5971 +
5972 +typedef struct _mc_perf_mon_cntl_t {
5973 + unsigned long clr_perf : 1;
5974 + unsigned long en_perf : 1;
5975 + unsigned long : 2;
5976 + unsigned long perf_op_a : 2;
5977 + unsigned long perf_op_b : 2;
5978 + unsigned long : 8;
5979 + unsigned long monitor_period : 8;
5980 + unsigned long perf_count_a_overflow : 1;
5981 + unsigned long perf_count_b_overflow : 1;
5982 + unsigned long : 6;
5983 + } mc_perf_mon_cntl_t;
5984 +
5985 +typedef union {
5986 + unsigned long val : 32;
5987 + mc_perf_mon_cntl_t f;
5988 +} mc_perf_mon_cntl_u;
5989 +
5990 +typedef struct _mc_perf_counters_t {
5991 + unsigned long mc_perf_counter_a : 16;
5992 + unsigned long mc_perf_counter_b : 16;
5993 + } mc_perf_counters_t;
5994 +
5995 +typedef union {
5996 + unsigned long val : 32;
5997 + mc_perf_counters_t f;
5998 +} mc_perf_counters_u;
5999 +
6000 +typedef struct _wait_until_t {
6001 + unsigned long wait_crtc_pflip : 1;
6002 + unsigned long wait_re_crtc_vline : 1;
6003 + unsigned long wait_fe_crtc_vline : 1;
6004 + unsigned long wait_crtc_vline : 1;
6005 + unsigned long wait_dma_viph0_idle : 1;
6006 + unsigned long wait_dma_viph1_idle : 1;
6007 + unsigned long wait_dma_viph2_idle : 1;
6008 + unsigned long wait_dma_viph3_idle : 1;
6009 + unsigned long wait_dma_vid_idle : 1;
6010 + unsigned long wait_dma_gui_idle : 1;
6011 + unsigned long wait_cmdfifo : 1;
6012 + unsigned long wait_ov0_flip : 1;
6013 + unsigned long wait_ov0_slicedone : 1;
6014 + unsigned long : 1;
6015 + unsigned long wait_2d_idle : 1;
6016 + unsigned long wait_3d_idle : 1;
6017 + unsigned long wait_2d_idleclean : 1;
6018 + unsigned long wait_3d_idleclean : 1;
6019 + unsigned long wait_host_idleclean : 1;
6020 + unsigned long wait_extern_sig : 1;
6021 + unsigned long cmdfifo_entries : 7;
6022 + unsigned long : 3;
6023 + unsigned long wait_both_crtc_pflip : 1;
6024 + unsigned long eng_display_select : 1;
6025 + } wait_until_t;
6026 +
6027 +typedef union {
6028 + unsigned long val : 32;
6029 + wait_until_t f;
6030 +} wait_until_u;
6031 +
6032 +typedef struct _isync_cntl_t {
6033 + unsigned long isync_any2d_idle3d : 1;
6034 + unsigned long isync_any3d_idle2d : 1;
6035 + unsigned long isync_trig2d_idle3d : 1;
6036 + unsigned long isync_trig3d_idle2d : 1;
6037 + unsigned long isync_wait_idlegui : 1;
6038 + unsigned long isync_cpscratch_idlegui : 1;
6039 + unsigned long : 26;
6040 + } isync_cntl_t;
6041 +
6042 +typedef union {
6043 + unsigned long val : 32;
6044 + isync_cntl_t f;
6045 +} isync_cntl_u;
6046 +
6047 +typedef struct _rbbm_guicntl_t {
6048 + unsigned long host_data_swap : 2;
6049 + unsigned long : 30;
6050 + } rbbm_guicntl_t;
6051 +
6052 +typedef union {
6053 + unsigned long val : 32;
6054 + rbbm_guicntl_t f;
6055 +} rbbm_guicntl_u;
6056 +
6057 +typedef struct _rbbm_status_t {
6058 + unsigned long cmdfifo_avail : 7;
6059 + unsigned long : 1;
6060 + unsigned long hirq_on_rbb : 1;
6061 + unsigned long cprq_on_rbb : 1;
6062 + unsigned long cfrq_on_rbb : 1;
6063 + unsigned long hirq_in_rtbuf : 1;
6064 + unsigned long cprq_in_rtbuf : 1;
6065 + unsigned long cfrq_in_rtbuf : 1;
6066 + unsigned long cf_pipe_busy : 1;
6067 + unsigned long eng_ev_busy : 1;
6068 + unsigned long cp_cmdstrm_busy : 1;
6069 + unsigned long e2_busy : 1;
6070 + unsigned long rb2d_busy : 1;
6071 + unsigned long rb3d_busy : 1;
6072 + unsigned long se_busy : 1;
6073 + unsigned long re_busy : 1;
6074 + unsigned long tam_busy : 1;
6075 + unsigned long tdm_busy : 1;
6076 + unsigned long pb_busy : 1;
6077 + unsigned long : 6;
6078 + unsigned long gui_active : 1;
6079 + } rbbm_status_t;
6080 +
6081 +typedef union {
6082 + unsigned long val : 32;
6083 + rbbm_status_t f;
6084 +} rbbm_status_u;
6085 +
6086 +typedef struct _rbbm_cntl_t {
6087 + unsigned long rb_settle : 4;
6088 + unsigned long abortclks_hi : 3;
6089 + unsigned long : 1;
6090 + unsigned long abortclks_cp : 3;
6091 + unsigned long : 1;
6092 + unsigned long abortclks_cfifo : 3;
6093 + unsigned long : 2;
6094 + unsigned long cpq_data_swap : 1;
6095 + unsigned long : 3;
6096 + unsigned long no_abort_idct : 1;
6097 + unsigned long no_abort_bios : 1;
6098 + unsigned long no_abort_fb : 1;
6099 + unsigned long no_abort_cp : 1;
6100 + unsigned long no_abort_hi : 1;
6101 + unsigned long no_abort_hdp : 1;
6102 + unsigned long no_abort_mc : 1;
6103 + unsigned long no_abort_aic : 1;
6104 + unsigned long no_abort_vip : 1;
6105 + unsigned long no_abort_disp : 1;
6106 + unsigned long no_abort_cg : 1;
6107 + } rbbm_cntl_t;
6108 +
6109 +typedef union {
6110 + unsigned long val : 32;
6111 + rbbm_cntl_t f;
6112 +} rbbm_cntl_u;
6113 +
6114 +typedef struct _rbbm_soft_reset_t {
6115 + unsigned long soft_reset_cp : 1;
6116 + unsigned long soft_reset_hi : 1;
6117 + unsigned long reserved3 : 3;
6118 + unsigned long soft_reset_e2 : 1;
6119 + unsigned long reserved2 : 2;
6120 + unsigned long soft_reset_mc : 1;
6121 + unsigned long reserved1 : 2;
6122 + unsigned long soft_reset_disp : 1;
6123 + unsigned long soft_reset_cg : 1;
6124 + unsigned long : 19;
6125 + } rbbm_soft_reset_t;
6126 +
6127 +typedef union {
6128 + unsigned long val : 32;
6129 + rbbm_soft_reset_t f;
6130 +} rbbm_soft_reset_u;
6131 +
6132 +typedef struct _nqwait_until_t {
6133 + unsigned long wait_gui_idle : 1;
6134 + unsigned long : 31;
6135 + } nqwait_until_t;
6136 +
6137 +typedef union {
6138 + unsigned long val : 32;
6139 + nqwait_until_t f;
6140 +} nqwait_until_u;
6141 +
6142 +typedef struct _rbbm_debug_t {
6143 + unsigned long rbbm_debug : 32;
6144 + } rbbm_debug_t;
6145 +
6146 +typedef union {
6147 + unsigned long val : 32;
6148 + rbbm_debug_t f;
6149 +} rbbm_debug_u;
6150 +
6151 +typedef struct _rbbm_cmdfifo_addr_t {
6152 + unsigned long cmdfifo_addr : 6;
6153 + unsigned long : 26;
6154 + } rbbm_cmdfifo_addr_t;
6155 +
6156 +typedef union {
6157 + unsigned long val : 32;
6158 + rbbm_cmdfifo_addr_t f;
6159 +} rbbm_cmdfifo_addr_u;
6160 +
6161 +typedef struct _rbbm_cmdfifo_datal_t {
6162 + unsigned long cmdfifo_datal : 32;
6163 + } rbbm_cmdfifo_datal_t;
6164 +
6165 +typedef union {
6166 + unsigned long val : 32;
6167 + rbbm_cmdfifo_datal_t f;
6168 +} rbbm_cmdfifo_datal_u;
6169 +
6170 +typedef struct _rbbm_cmdfifo_datah_t {
6171 + unsigned long cmdfifo_datah : 12;
6172 + unsigned long : 20;
6173 + } rbbm_cmdfifo_datah_t;
6174 +
6175 +typedef union {
6176 + unsigned long val : 32;
6177 + rbbm_cmdfifo_datah_t f;
6178 +} rbbm_cmdfifo_datah_u;
6179 +
6180 +typedef struct _rbbm_cmdfifo_stat_t {
6181 + unsigned long cmdfifo_rptr : 6;
6182 + unsigned long : 2;
6183 + unsigned long cmdfifo_wptr : 6;
6184 + unsigned long : 18;
6185 + } rbbm_cmdfifo_stat_t;
6186 +
6187 +typedef union {
6188 + unsigned long val : 32;
6189 + rbbm_cmdfifo_stat_t f;
6190 +} rbbm_cmdfifo_stat_u;
6191 +
6192 +typedef struct _clk_pin_cntl_t {
6193 + unsigned long osc_en : 1;
6194 + unsigned long osc_gain : 5;
6195 + unsigned long dont_use_xtalin : 1;
6196 + unsigned long xtalin_pm_en : 1;
6197 + unsigned long xtalin_dbl_en : 1;
6198 + unsigned long : 7;
6199 + unsigned long cg_debug : 16;
6200 + } clk_pin_cntl_t;
6201 +
6202 +typedef union {
6203 + unsigned long val : 32;
6204 + clk_pin_cntl_t f;
6205 +} clk_pin_cntl_u;
6206 +
6207 +typedef struct _pll_ref_fb_div_t {
6208 + unsigned long pll_ref_div : 4;
6209 + unsigned long : 4;
6210 + unsigned long pll_fb_div_int : 6;
6211 + unsigned long : 2;
6212 + unsigned long pll_fb_div_frac : 3;
6213 + unsigned long : 1;
6214 + unsigned long pll_reset_time : 4;
6215 + unsigned long pll_lock_time : 8;
6216 + } pll_ref_fb_div_t;
6217 +
6218 +typedef union {
6219 + unsigned long val : 32;
6220 + pll_ref_fb_div_t f;
6221 +} pll_ref_fb_div_u;
6222 +
6223 +typedef struct _pll_cntl_t {
6224 + unsigned long pll_pwdn : 1;
6225 + unsigned long pll_reset : 1;
6226 + unsigned long pll_pm_en : 1;
6227 + unsigned long pll_mode : 1;
6228 + unsigned long pll_refclk_sel : 1;
6229 + unsigned long pll_fbclk_sel : 1;
6230 + unsigned long pll_tcpoff : 1;
6231 + unsigned long pll_pcp : 3;
6232 + unsigned long pll_pvg : 3;
6233 + unsigned long pll_vcofr : 1;
6234 + unsigned long pll_ioffset : 2;
6235 + unsigned long pll_pecc_mode : 2;
6236 + unsigned long pll_pecc_scon : 2;
6237 + unsigned long pll_dactal : 4;
6238 + unsigned long pll_cp_clip : 2;
6239 + unsigned long pll_conf : 3;
6240 + unsigned long pll_mbctrl : 2;
6241 + unsigned long pll_ring_off : 1;
6242 + } pll_cntl_t;
6243 +
6244 +typedef union {
6245 + unsigned long val : 32;
6246 + pll_cntl_t f;
6247 +} pll_cntl_u;
6248 +
6249 +typedef struct _sclk_cntl_t {
6250 + unsigned long sclk_src_sel : 2;
6251 + unsigned long : 2;
6252 + unsigned long sclk_post_div_fast : 4;
6253 + unsigned long sclk_clkon_hys : 3;
6254 + unsigned long sclk_post_div_slow : 4;
6255 + unsigned long disp_cg_ok2switch_en : 1;
6256 + unsigned long sclk_force_reg : 1;
6257 + unsigned long sclk_force_disp : 1;
6258 + unsigned long sclk_force_mc : 1;
6259 + unsigned long sclk_force_extmc : 1;
6260 + unsigned long sclk_force_cp : 1;
6261 + unsigned long sclk_force_e2 : 1;
6262 + unsigned long sclk_force_e3 : 1;
6263 + unsigned long sclk_force_idct : 1;
6264 + unsigned long sclk_force_bist : 1;
6265 + unsigned long busy_extend_cp : 1;
6266 + unsigned long busy_extend_e2 : 1;
6267 + unsigned long busy_extend_e3 : 1;
6268 + unsigned long busy_extend_idct : 1;
6269 + unsigned long : 3;
6270 + } sclk_cntl_t;
6271 +
6272 +typedef union {
6273 + unsigned long val : 32;
6274 + sclk_cntl_t f;
6275 +} sclk_cntl_u;
6276 +
6277 +typedef struct _pclk_cntl_t {
6278 + unsigned long pclk_src_sel : 2;
6279 + unsigned long : 2;
6280 + unsigned long pclk_post_div : 4;
6281 + unsigned long : 8;
6282 + unsigned long pclk_force_disp : 1;
6283 + unsigned long : 15;
6284 + } pclk_cntl_t;
6285 +
6286 +typedef union {
6287 + unsigned long val : 32;
6288 + pclk_cntl_t f;
6289 +} pclk_cntl_u;
6290 +
6291 +typedef struct _clk_test_cntl_t {
6292 + unsigned long testclk_sel : 4;
6293 + unsigned long : 3;
6294 + unsigned long start_check_freq : 1;
6295 + unsigned long tstcount_rst : 1;
6296 + unsigned long : 15;
6297 + unsigned long test_count : 8;
6298 + } clk_test_cntl_t;
6299 +
6300 +typedef union {
6301 + unsigned long val : 32;
6302 + clk_test_cntl_t f;
6303 +} clk_test_cntl_u;
6304 +
6305 +typedef struct _pwrmgt_cntl_t {
6306 + unsigned long pwm_enable : 1;
6307 + unsigned long : 1;
6308 + unsigned long pwm_mode_req : 2;
6309 + unsigned long pwm_wakeup_cond : 2;
6310 + unsigned long pwm_fast_noml_hw_en : 1;
6311 + unsigned long pwm_noml_fast_hw_en : 1;
6312 + unsigned long pwm_fast_noml_cond : 4;
6313 + unsigned long pwm_noml_fast_cond : 4;
6314 + unsigned long pwm_idle_timer : 8;
6315 + unsigned long pwm_busy_timer : 8;
6316 + } pwrmgt_cntl_t;
6317 +
6318 +typedef union {
6319 + unsigned long val : 32;
6320 + pwrmgt_cntl_t f;
6321 +} pwrmgt_cntl_u;
6322 +
6323 +typedef struct _pwrmgt_status_t {
6324 + unsigned long pwm_mode : 2;
6325 + unsigned long : 30;
6326 + } pwrmgt_status_t;
6327 +
6328 +typedef union {
6329 + unsigned long val : 32;
6330 + pwrmgt_status_t f;
6331 +} pwrmgt_status_u;
6332 +
6333 +
6334 +#endif //_W100_REGS_H_
6335 Index: git/hw/kdrive/Makefile.am
6336 ===================================================================
6337 --- git.orig/hw/kdrive/Makefile.am 2006-09-02 12:12:13.000000000 +0200
6338 +++ git/hw/kdrive/Makefile.am 2006-09-02 12:12:14.000000000 +0200
6339 @@ -7,6 +7,10 @@
6340 FBDEV_SUBDIRS = fbdev epson
6341 endif
6342
6343 +if KDRIVEW100
6344 +W100_SUBDIRS = w100
6345 +endif
6346 +
6347 if XSDLSERVER
6348 XSDL_SUBDIRS = sdl
6349 endif
6350 @@ -20,6 +24,7 @@
6351 linux \
6352 $(XSDL_SUBDIRS) \
6353 $(FBDEV_SUBDIRS) \
6354 + $(W100_SUBDIRS) \
6355 $(VESA_SUBDIRS) \
6356 $(XEPHYR_SUBDIRS) \
6357 fake
6358 Index: git/configure.ac
6359 ===================================================================
6360 --- git.orig/configure.ac 2006-09-02 12:12:14.000000000 +0200
6361 +++ git/configure.ac 2006-09-02 12:12:14.000000000 +0200
6362 @@ -442,6 +442,7 @@
6363 AC_ARG_ENABLE(kdrive, AS_HELP_STRING([--enable-kdrive], [Build kdrive servers (default: no)]), [KDRIVE=$enableval], [KDRIVE=no])
6364 AC_ARG_ENABLE(xephyr, AS_HELP_STRING([--enable-xephyr], [Build the kdrive Xephyr server (default: auto)]), [XEPHYR=$enableval], [XEPHYR=auto])
6365 AC_ARG_ENABLE(xsdl, AS_HELP_STRING([--enable-xsdl], [Build the kdrive Xsdl server (default: auto)]), [XSDL=$enableval], [XSDL=auto])
6366 +AC_ARG_ENABLE(w100, AS_HELP_STRING([--enable-w100], [Build the kdrive Xw100 server (default: no)]), [KDRIVEW100=$enableval], [KDRIVEW100=no])
6367 dnl xprint
6368 AC_ARG_ENABLE(freetype, AS_HELP_STRING([ --enable-freetype], [Build Xprint FreeType backend (default: yes)]), [XP_USE_FREETYPE=$enableval],[XP_USE_FREETYPE=no])
6369 AC_ARG_WITH(freetype-config, AS_HELP_STRING([ --with-freetype-config=PROG], [Use FreeType configuration program PROG (default: auto)]), freetype_config=$withval, freetype_config=auto)
6370 @@ -1519,6 +1520,10 @@
6371 AC_SUBST([XSDL_LIBS])
6372 AC_SUBST([XSDL_INCS])
6373
6374 +AM_CONDITIONAL(KDRIVEW100, [test "x$KDRIVEW100" = xyes])
6375 +if test "x$KDRIVEW100" = xyes; then
6376 + AC_DEFINE(KDRIVEW100, 1, [Build Xw100 server])
6377 +fi
6378
6379 dnl these only go in xkb-config.h (which is shared by the Xorg and Xnest servers)
6380 AC_DEFINE(__XKBDEFRULES__, "xorg", [Default XKB rules])
6381 @@ -1753,6 +1758,7 @@
6382 hw/kdrive/epson/Makefile
6383 hw/kdrive/fake/Makefile
6384 hw/kdrive/fbdev/Makefile
6385 +hw/kdrive/w100/Makefile
6386 hw/kdrive/i810/Makefile
6387 hw/kdrive/linux/Makefile
6388 hw/kdrive/mach64/Makefile
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