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0cf61f02e0de7fc563bd3efec4047008c4e5a0e0
[openwrt/svn-archive/archive.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.16/arch/mips/aruba/Makefile linux-2.6.16-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.16/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.16-owrt/arch/mips/aruba/Makefile 2006-03-20 14:25:10.000000000 +0100
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/Makefile linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.16/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile 2006-03-20 14:25:10.000000000 +0100
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.c linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c 2006-03-20 14:25:10.000000000 +0100
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.h linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h 2006-03-20 14:25:10.000000000 +0100
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.16/arch/mips/aruba/prom.c linux-2.6.16-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.16/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.16-owrt/arch/mips/aruba/prom.c 2006-03-20 14:25:10.000000000 +0100
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.16/arch/mips/aruba/serial.c linux-2.6.16-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.16/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.16-owrt/arch/mips/aruba/serial.c 2006-03-20 14:25:10.000000000 +0100
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.16/arch/mips/aruba/setup.c linux-2.6.16-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.16/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.16-owrt/arch/mips/aruba/setup.c 2006-03-20 14:30:00.000000000 +0100
786 @@ -0,0 +1,122 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/mm.h>
827 +#include <linux/sched.h>
828 +#include <linux/irq.h>
829 +#include <asm/bootinfo.h>
830 +#include <asm/io.h>
831 +#include <linux/ioport.h>
832 +#include <asm/mipsregs.h>
833 +#include <asm/pgtable.h>
834 +#include <asm/reboot.h>
835 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
836 +#include <asm/idt-boards/rc32434/rc32434.h>
837 +#include <linux/pm.h>
838 +
839 +extern char *__init prom_getcmdline(void);
840 +
841 +extern void (*board_time_init) (void);
842 +extern void (*board_timer_setup) (struct irqaction * irq);
843 +extern void aruba_time_init(void);
844 +extern void aruba_timer_setup(struct irqaction *irq);
845 +extern void aruba_reset(void);
846 +
847 +#define epldMask ((volatile unsigned char *)0xB900000d)
848 +
849 +static void aruba_machine_restart(char *command)
850 +{
851 + switch (mips_machtype) {
852 + case MACH_ARUBA_AP70:
853 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
854 + break;
855 + case MACH_ARUBA_AP65:
856 + case MACH_ARUBA_AP60:
857 + default:
858 + /* Reset*/
859 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
860 + udelay(100);
861 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
862 + udelay(100);
863 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
864 + break;
865 + }
866 +}
867 +
868 +static void aruba_machine_halt(void)
869 +{
870 + for (;;) continue;
871 +}
872 +
873 +extern char * getenv(char *e);
874 +extern void unlock_ap60_70_flash(void);
875 +
876 +void __init plat_setup(void)
877 +{
878 + board_time_init = aruba_time_init;
879 +
880 + board_timer_setup = aruba_timer_setup;
881 +
882 + _machine_restart = aruba_machine_restart;
883 + _machine_halt = aruba_machine_halt;
884 + pm_power_off = aruba_machine_halt;
885 +
886 + set_io_port_base(KSEG1);
887 +
888 + /* Enable PCI interrupts in EPLD Mask register */
889 + *epldMask = 0x0;
890 + *(epldMask + 1) = 0x0;
891 +
892 + write_c0_wired(0);
893 + unlock_ap60_70_flash();
894 +
895 + printk("BOARD - %s\n",getenv("boardname"));
896 +
897 + return 0;
898 +}
899 +
900 +int page_is_ram(unsigned long pagenr)
901 +{
902 + return 1;
903 +}
904 +
905 +const char *get_system_type(void)
906 +{
907 + return "MIPS IDT32434 - ARUBA";
908 +}
909 diff -Nur linux-2.6.16/arch/mips/aruba/time.c linux-2.6.16-owrt/arch/mips/aruba/time.c
910 --- linux-2.6.16/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
911 +++ linux-2.6.16-owrt/arch/mips/aruba/time.c 2006-03-20 14:25:10.000000000 +0100
912 @@ -0,0 +1,108 @@
913 +/**************************************************************************
914 + *
915 + * BRIEF MODULE DESCRIPTION
916 + * timer routines for IDT EB434 boards
917 + *
918 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
919 + *
920 + * This program is free software; you can redistribute it and/or modify it
921 + * under the terms of the GNU General Public License as published by the
922 + * Free Software Foundation; either version 2 of the License, or (at your
923 + * option) any later version.
924 + *
925 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
926 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
927 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
928 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
929 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
930 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
931 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
932 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
933 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
934 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
935 + *
936 + * You should have received a copy of the GNU General Public License along
937 + * with this program; if not, write to the Free Software Foundation, Inc.,
938 + * 675 Mass Ave, Cambridge, MA 02139, USA.
939 + *
940 + *
941 + **************************************************************************
942 + * May 2004 rkt, neb
943 + *
944 + * Initial Release
945 + *
946 + *
947 + *
948 + **************************************************************************
949 + */
950 +
951 +#include <linux/config.h>
952 +#include <linux/init.h>
953 +#include <linux/kernel_stat.h>
954 +#include <linux/sched.h>
955 +#include <linux/spinlock.h>
956 +#include <linux/mc146818rtc.h>
957 +#include <linux/irq.h>
958 +#include <linux/timex.h>
959 +
960 +#include <linux/param.h>
961 +#include <asm/mipsregs.h>
962 +#include <asm/ptrace.h>
963 +#include <asm/time.h>
964 +#include <asm/hardirq.h>
965 +
966 +#include <asm/mipsregs.h>
967 +#include <asm/ptrace.h>
968 +#include <asm/debug.h>
969 +#include <asm/time.h>
970 +
971 +#include <asm/idt-boards/rc32434/rc32434.h>
972 +
973 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
974 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
975 +
976 +extern unsigned int idt_cpu_freq;
977 +
978 +static unsigned long __init cal_r4koff(void)
979 +{
980 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
981 + return (mips_hpt_frequency / HZ);
982 +}
983 +
984 +void __init aruba_time_init(void)
985 +{
986 + unsigned int est_freq, flags;
987 + local_irq_save(flags);
988 +
989 + printk("calculating r4koff... ");
990 + r4k_offset = cal_r4koff();
991 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
992 +
993 + est_freq = 2 * r4k_offset * HZ;
994 + est_freq += 5000; /* round */
995 + est_freq -= est_freq % 10000;
996 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
997 + (est_freq % 1000000) * 100 / 1000000);
998 + local_irq_restore(flags);
999 +
1000 +}
1001 +
1002 +void __init aruba_timer_setup(struct irqaction *irq)
1003 +{
1004 + /* we are using the cpu counter for timer interrupts */
1005 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1006 +
1007 + /* to generate the first timer interrupt */
1008 + r4k_cur = (read_c0_count() + r4k_offset);
1009 + write_c0_compare(r4k_cur);
1010 +
1011 +}
1012 +
1013 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1014 +{
1015 + irq_enter();
1016 + kstat_this_cpu.irqs[irq]++;
1017 +
1018 + timer_interrupt(irq, NULL, regs);
1019 + irq_exit();
1020 +}
1021 diff -Nur linux-2.6.16/arch/mips/Kconfig linux-2.6.16-owrt/arch/mips/Kconfig
1022 --- linux-2.6.16/arch/mips/Kconfig 2006-03-20 06:53:29.000000000 +0100
1023 +++ linux-2.6.16-owrt/arch/mips/Kconfig 2006-03-20 14:25:10.000000000 +0100
1024 @@ -227,6 +227,17 @@
1025 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1026 a kernel for this platform.
1027
1028 +config MACH_ARUBA
1029 + bool "Support for the ARUBA product line"
1030 + select DMA_NONCOHERENT
1031 + select CPU_HAS_PREFETCH
1032 + select HW_HAS_PCI
1033 + select SWAP_IO_SPACE
1034 + select SYS_SUPPORTS_32BIT_KERNEL
1035 + select SYS_HAS_CPU_MIPS32_R1
1036 + select SYS_SUPPORTS_BIG_ENDIAN
1037 +
1038 +
1039 config MACH_JAZZ
1040 bool "Support for the Jazz family of machines"
1041 select ARC
1042 diff -Nur linux-2.6.16/arch/mips/Makefile linux-2.6.16-owrt/arch/mips/Makefile
1043 --- linux-2.6.16/arch/mips/Makefile 2006-03-20 06:53:29.000000000 +0100
1044 +++ linux-2.6.16-owrt/arch/mips/Makefile 2006-03-20 14:25:10.000000000 +0100
1045 @@ -279,6 +279,14 @@
1046 #
1047
1048 #
1049 +# Aruba
1050 +#
1051 +
1052 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1053 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1054 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1055 +
1056 +#
1057 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1058 #
1059 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1060 diff -Nur linux-2.6.16/arch/mips/mm/tlbex.c linux-2.6.16-owrt/arch/mips/mm/tlbex.c
1061 --- linux-2.6.16/arch/mips/mm/tlbex.c 2006-03-20 06:53:29.000000000 +0100
1062 +++ linux-2.6.16-owrt/arch/mips/mm/tlbex.c 2006-03-20 14:25:10.000000000 +0100
1063 @@ -852,7 +852,6 @@
1064
1065 case CPU_R10000:
1066 case CPU_R12000:
1067 - case CPU_4KC:
1068 case CPU_SB1:
1069 case CPU_SB1A:
1070 case CPU_4KSC:
1071 @@ -880,6 +879,7 @@
1072 tlbw(p);
1073 break;
1074
1075 + case CPU_4KC:
1076 case CPU_4KEC:
1077 case CPU_24K:
1078 case CPU_34K:
1079 diff -Nur linux-2.6.16/drivers/net/Kconfig linux-2.6.16-owrt/drivers/net/Kconfig
1080 --- linux-2.6.16/drivers/net/Kconfig 2006-03-20 06:53:29.000000000 +0100
1081 +++ linux-2.6.16-owrt/drivers/net/Kconfig 2006-03-20 14:25:10.000000000 +0100
1082 @@ -187,6 +187,13 @@
1083
1084 source "drivers/net/arm/Kconfig"
1085
1086 +config IDT_RC32434_ETH
1087 + tristate "IDT RC32434 Local Ethernet support"
1088 + depends on NET_ETHERNET
1089 + help
1090 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1091 + To compile this driver as a module, choose M here.
1092 +
1093 config MACE
1094 tristate "MACE (Power Mac ethernet) support"
1095 depends on NET_ETHERNET && PPC_PMAC && PPC32
1096 diff -Nur linux-2.6.16/drivers/net/Makefile linux-2.6.16-owrt/drivers/net/Makefile
1097 --- linux-2.6.16/drivers/net/Makefile 2006-03-20 06:53:29.000000000 +0100
1098 +++ linux-2.6.16-owrt/drivers/net/Makefile 2006-03-20 14:25:10.000000000 +0100
1099 @@ -38,6 +38,7 @@
1100
1101 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1102
1103 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1104 obj-$(CONFIG_DGRS) += dgrs.o
1105 obj-$(CONFIG_VORTEX) += 3c59x.o
1106 obj-$(CONFIG_TYPHOON) += typhoon.o
1107 diff -Nur linux-2.6.16/drivers/net/natsemi.c linux-2.6.16-owrt/drivers/net/natsemi.c
1108 --- linux-2.6.16/drivers/net/natsemi.c 2006-03-20 06:53:29.000000000 +0100
1109 +++ linux-2.6.16-owrt/drivers/net/natsemi.c 2006-03-20 14:25:10.000000000 +0100
1110 @@ -771,6 +771,49 @@
1111 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1112 static struct ethtool_ops ethtool_ops;
1113
1114 +#ifdef CONFIG_MACH_ARUBA
1115 +
1116 +#include <linux/ctype.h>
1117 +
1118 +#ifndef ERR
1119 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1120 +#endif
1121 +
1122 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1123 +{
1124 + int i, j;
1125 + unsigned char result, value;
1126 +
1127 + for (i=0; i<6; i++) {
1128 + result = 0;
1129 + if (i != 5 && *(macstr+2) != ':') {
1130 + ERR("invalid mac address format: %d %c\n",
1131 + i, *(macstr+2));
1132 + return -EINVAL;
1133 + }
1134 + for (j=0; j<2; j++) {
1135 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1136 + toupper(*macstr)-'A'+10) < 16) {
1137 + result = result*16 + value;
1138 + macstr++;
1139 + }
1140 + else {
1141 + ERR("invalid mac address "
1142 + "character: %c\n", *macstr);
1143 + return -EINVAL;
1144 + }
1145 + }
1146 +
1147 + macstr++;
1148 + dev->dev_addr[i] = result;
1149 + }
1150 +
1151 + dev->dev_addr[5]++;
1152 + return 0;
1153 +}
1154 +
1155 +#endif
1156 +
1157 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1158 {
1159 return (void __iomem *) dev->base_addr;
1160 @@ -859,6 +902,7 @@
1161 goto err_ioremap;
1162 }
1163
1164 +#ifndef CONFIG_MACH_ARUBA
1165 /* Work around the dropped serial bit. */
1166 prev_eedata = eeprom_read(ioaddr, 6);
1167 for (i = 0; i < 3; i++) {
1168 @@ -867,6 +911,19 @@
1169 dev->dev_addr[i*2+1] = eedata >> 7;
1170 prev_eedata = eedata;
1171 }
1172 +#else
1173 + {
1174 + char mac[32];
1175 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1176 + extern char *getenv(char *e);
1177 + memset(mac, 0, 32);
1178 + memcpy(mac, getenv("ethaddr"), 17);
1179 + if (parse_mac_addr(dev, mac)){
1180 + printk("%s: MAC address not found\n", __func__);
1181 + memcpy(dev->dev_addr, def_mac, 6);
1182 + }
1183 + }
1184 +#endif
1185
1186 dev->base_addr = (unsigned long __force) ioaddr;
1187 dev->irq = irq;
1188 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.c linux-2.6.16-owrt/drivers/net/rc32434_eth.c
1189 --- linux-2.6.16/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1190 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.c 2006-03-20 14:25:10.000000000 +0100
1191 @@ -0,0 +1,1268 @@
1192 +/**************************************************************************
1193 + *
1194 + * BRIEF MODULE DESCRIPTION
1195 + * Driver for the IDT RC32434 on-chip ethernet controller.
1196 + *
1197 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1198 + *
1199 + * This program is free software; you can redistribute it and/or modify it
1200 + * under the terms of the GNU General Public License as published by the
1201 + * Free Software Foundation; either version 2 of the License, or (at your
1202 + * option) any later version.
1203 + *
1204 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1205 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1206 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1207 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1208 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1209 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1210 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1211 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1212 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1213 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1214 + *
1215 + * You should have received a copy of the GNU General Public License along
1216 + * with this program; if not, write to the Free Software Foundation, Inc.,
1217 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1218 + *
1219 + *
1220 + **************************************************************************
1221 + * May 2004 rkt, neb
1222 + *
1223 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1224 + *
1225 + * Aug 2004 Sadik
1226 + *
1227 + * Added NAPI
1228 + *
1229 + **************************************************************************
1230 + */
1231 +
1232 +#include <linux/config.h>
1233 +#include <linux/module.h>
1234 +#include <linux/kernel.h>
1235 +#include <linux/moduleparam.h>
1236 +#include <linux/sched.h>
1237 +#include <linux/ctype.h>
1238 +#include <linux/types.h>
1239 +#include <linux/fcntl.h>
1240 +#include <linux/interrupt.h>
1241 +#include <linux/ptrace.h>
1242 +#include <linux/init.h>
1243 +#include <linux/ioport.h>
1244 +#include <linux/proc_fs.h>
1245 +#include <linux/in.h>
1246 +#include <linux/slab.h>
1247 +#include <linux/string.h>
1248 +#include <linux/delay.h>
1249 +#include <linux/netdevice.h>
1250 +#include <linux/etherdevice.h>
1251 +#include <linux/skbuff.h>
1252 +#include <linux/errno.h>
1253 +#include <asm/bootinfo.h>
1254 +#include <asm/system.h>
1255 +#include <asm/bitops.h>
1256 +#include <asm/pgtable.h>
1257 +#include <asm/segment.h>
1258 +#include <asm/io.h>
1259 +#include <asm/dma.h>
1260 +
1261 +#include "rc32434_eth.h"
1262 +
1263 +#define DRIVER_VERSION "(mar2904)"
1264 +
1265 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1266 +
1267 +
1268 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1269 + ((dev)->dev_addr[1]))
1270 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1271 + ((dev)->dev_addr[3] << 16) | \
1272 + ((dev)->dev_addr[4] << 8) | \
1273 + ((dev)->dev_addr[5]))
1274 +
1275 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1276 +static char mac0[18] = "08:00:06:05:40:01";
1277 +
1278 +MODULE_PARM(mac0, "c18");
1279 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1280 +
1281 +static struct rc32434_if_t {
1282 + char *name;
1283 + struct net_device *dev;
1284 + char* mac_str;
1285 + int weight;
1286 + u32 iobase;
1287 + u32 rxdmabase;
1288 + u32 txdmabase;
1289 + int rx_dma_irq;
1290 + int tx_dma_irq;
1291 + int rx_ovr_irq;
1292 + int tx_und_irq;
1293 +} rc32434_iflist[] =
1294 +{
1295 + {
1296 + "rc32434_eth0", NULL, mac0,
1297 + 64,
1298 + ETH0_PhysicalAddress,
1299 + ETH0_RX_DMA_ADDR,
1300 + ETH0_TX_DMA_ADDR,
1301 + ETH0_DMA_RX_IRQ,
1302 + ETH0_DMA_TX_IRQ,
1303 + ETH0_RX_OVR_IRQ,
1304 + ETH0_TX_UND_IRQ
1305 + }
1306 +};
1307 +
1308 +
1309 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1310 +{
1311 + int i, j;
1312 + unsigned char result, value;
1313 +
1314 + for (i=0; i<6; i++) {
1315 + result = 0;
1316 + if (i != 5 && *(macstr+2) != ':') {
1317 + ERR("invalid mac address format: %d %c\n",
1318 + i, *(macstr+2));
1319 + return -EINVAL;
1320 + }
1321 + for (j=0; j<2; j++) {
1322 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1323 + toupper(*macstr)-'A'+10) < 16) {
1324 + result = result*16 + value;
1325 + macstr++;
1326 + }
1327 + else {
1328 + ERR("invalid mac address "
1329 + "character: %c\n", *macstr);
1330 + return -EINVAL;
1331 + }
1332 + }
1333 +
1334 + macstr++;
1335 + dev->dev_addr[i] = result;
1336 + }
1337 +
1338 + return 0;
1339 +}
1340 +
1341 +
1342 +
1343 +static inline void rc32434_abort_tx(struct net_device *dev)
1344 +{
1345 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1346 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1347 +
1348 +}
1349 +
1350 +static inline void rc32434_abort_rx(struct net_device *dev)
1351 +{
1352 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1353 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1354 +
1355 +}
1356 +
1357 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1358 +{
1359 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1360 +}
1361 +
1362 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1363 +{
1364 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1365 +}
1366 +
1367 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1368 +{
1369 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1370 +}
1371 +
1372 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1373 +{
1374 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1375 +}
1376 +
1377 +#ifdef RC32434_PROC_DEBUG
1378 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1379 + int length, int *eof, void *data)
1380 +{
1381 + struct net_device *dev = (struct net_device *)data;
1382 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1383 + int len = 0;
1384 +
1385 + /* print out header */
1386 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1387 + len += sprintf (buf + len,
1388 + "DMA halt count = %10d, DMA run count = %10d\n",
1389 + lp->dma_halt_cnt, lp->dma_run_cnt);
1390 +
1391 + if (fpos >= len) {
1392 + *start = buf;
1393 + *eof = 1;
1394 + return 0;
1395 + }
1396 + *start = buf + fpos;
1397 +
1398 + if ((len -= fpos) > length)
1399 + return length;
1400 + *eof = 1;
1401 +
1402 + return len;
1403 +
1404 +}
1405 +#endif
1406 +
1407 +
1408 +/*
1409 + * Restart the RC32434 ethernet controller.
1410 + */
1411 +static int rc32434_restart(struct net_device *dev)
1412 +{
1413 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1414 +
1415 + /*
1416 + * Disable interrupts
1417 + */
1418 + disable_irq(lp->rx_irq);
1419 + disable_irq(lp->tx_irq);
1420 +#ifdef RC32434_REVISION
1421 + disable_irq(lp->ovr_irq);
1422 +#endif
1423 + disable_irq(lp->und_irq);
1424 +
1425 + /* Mask F E bit in Tx DMA */
1426 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1427 + /* Mask D H E bit in Rx DMA */
1428 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1429 +
1430 + rc32434_init(dev);
1431 + rc32434_multicast_list(dev);
1432 +
1433 + enable_irq(lp->und_irq);
1434 +#ifdef RC32434_REVISION
1435 + enable_irq(lp->ovr_irq);
1436 +#endif
1437 + enable_irq(lp->tx_irq);
1438 + enable_irq(lp->rx_irq);
1439 +
1440 + return 0;
1441 +}
1442 +
1443 +int rc32434_init_module(void)
1444 +{
1445 +#ifdef CONFIG_MACH_ARUBA
1446 + if (mips_machtype != MACH_ARUBA_AP70)
1447 + return 1;
1448 +#endif
1449 +
1450 + printk(KERN_INFO DRIVER_NAME " \n");
1451 + return rc32434_probe(0);
1452 +}
1453 +
1454 +static int rc32434_probe(int port_num)
1455 +{
1456 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1457 + struct rc32434_local *lp = NULL;
1458 + struct net_device *dev = NULL;
1459 + int i, retval,err;
1460 +
1461 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1462 + if(!dev) {
1463 + ERR("rc32434_eth: alloc_etherdev failed\n");
1464 + return -1;
1465 + }
1466 +
1467 + SET_MODULE_OWNER(dev);
1468 + bif->dev = dev;
1469 +
1470 +#ifdef CONFIG_MACH_ARUBA
1471 + {
1472 + extern char * getenv(char *e);
1473 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1474 + }
1475 +#endif
1476 +
1477 + printk("mac: %s\n", bif->mac_str);
1478 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1479 + ERR("MAC address parse failed\n");
1480 + free_netdev(dev);
1481 + return -1;
1482 + }
1483 +
1484 +
1485 + /* Initialize the device structure. */
1486 + if (dev->priv == NULL) {
1487 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1488 + memset(lp, 0, sizeof(struct rc32434_local));
1489 + }
1490 + else {
1491 + lp = (struct rc32434_local *)dev->priv;
1492 + }
1493 +
1494 + lp->rx_irq = bif->rx_dma_irq;
1495 + lp->tx_irq = bif->tx_dma_irq;
1496 + lp->ovr_irq = bif->rx_ovr_irq;
1497 + lp->und_irq = bif->tx_und_irq;
1498 +
1499 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1500 +
1501 + if (!lp->eth_regs) {
1502 + ERR("Can't remap eth registers\n");
1503 + retval = -ENXIO;
1504 + goto probe_err_out;
1505 + }
1506 +
1507 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1508 +
1509 + if (!lp->rx_dma_regs) {
1510 + ERR("Can't remap Rx DMA registers\n");
1511 + retval = -ENXIO;
1512 + goto probe_err_out;
1513 + }
1514 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1515 +
1516 + if (!lp->tx_dma_regs) {
1517 + ERR("Can't remap Tx DMA registers\n");
1518 + retval = -ENXIO;
1519 + goto probe_err_out;
1520 + }
1521 +
1522 +#ifdef RC32434_PROC_DEBUG
1523 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1524 + rc32434_read_proc, dev);
1525 +#endif
1526 +
1527 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1528 + if (!lp->td_ring) {
1529 + ERR("Can't allocate descriptors\n");
1530 + retval = -ENOMEM;
1531 + goto probe_err_out;
1532 + }
1533 +
1534 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1535 +
1536 + /* now convert TD_RING pointer to KSEG1 */
1537 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1538 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1539 +
1540 +
1541 + spin_lock_init(&lp->lock);
1542 +
1543 + dev->base_addr = bif->iobase;
1544 + /* just use the rx dma irq */
1545 + dev->irq = bif->rx_dma_irq;
1546 +
1547 + dev->priv = lp;
1548 +
1549 + dev->open = rc32434_open;
1550 + dev->stop = rc32434_close;
1551 + dev->hard_start_xmit = rc32434_send_packet;
1552 + dev->get_stats = rc32434_get_stats;
1553 + dev->set_multicast_list = &rc32434_multicast_list;
1554 + dev->tx_timeout = rc32434_tx_timeout;
1555 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1556 +
1557 +#ifdef CONFIG_IDT_USE_NAPI
1558 + dev->poll = rc32434_poll;
1559 + dev->weight = bif->weight;
1560 + printk("Using NAPI with weight %d\n",dev->weight);
1561 +#else
1562 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1563 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1564 +#endif
1565 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1566 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1567 +
1568 + if ((err = register_netdev(dev))) {
1569 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1570 + free_netdev(dev);
1571 + retval = -EINVAL;
1572 + goto probe_err_out;
1573 + }
1574 +
1575 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1576 + for (i = 0; i < 6; i++) {
1577 + printk("%2.2x", dev->dev_addr[i]);
1578 + if (i<5)
1579 + printk(":");
1580 + }
1581 + printk("\n");
1582 +
1583 + return 0;
1584 +
1585 + probe_err_out:
1586 + rc32434_cleanup_module();
1587 + ERR(" failed. Returns %d\n", retval);
1588 + return retval;
1589 +
1590 +}
1591 +
1592 +
1593 +static void rc32434_cleanup_module(void)
1594 +{
1595 + int i;
1596 +
1597 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1598 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1599 + if (bif->dev != NULL) {
1600 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1601 + if (lp != NULL) {
1602 + if (lp->eth_regs)
1603 + iounmap((void*)lp->eth_regs);
1604 + if (lp->rx_dma_regs)
1605 + iounmap((void*)lp->rx_dma_regs);
1606 + if (lp->tx_dma_regs)
1607 + iounmap((void*)lp->tx_dma_regs);
1608 + if (lp->td_ring)
1609 + kfree((void*)KSEG0ADDR(lp->td_ring));
1610 +
1611 +#ifdef RC32434_PROC_DEBUG
1612 + if (lp->ps) {
1613 + remove_proc_entry(bif->name, proc_net);
1614 + }
1615 +#endif
1616 + kfree(lp);
1617 + }
1618 +
1619 + unregister_netdev(bif->dev);
1620 + free_netdev(bif->dev);
1621 + kfree(bif->dev);
1622 + }
1623 + }
1624 +}
1625 +
1626 +
1627 +
1628 +static int rc32434_open(struct net_device *dev)
1629 +{
1630 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1631 +
1632 + /* Initialize */
1633 + if (rc32434_init(dev)) {
1634 + ERR("Error: cannot open the Ethernet device\n");
1635 + return -EAGAIN;
1636 + }
1637 +
1638 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1639 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1640 + SA_SHIRQ | SA_INTERRUPT,
1641 + "rc32434 ethernet Rx", dev)) {
1642 + ERR(": unable to get Rx DMA IRQ %d\n",
1643 + lp->rx_irq);
1644 + return -EAGAIN;
1645 + }
1646 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1647 + SA_SHIRQ | SA_INTERRUPT,
1648 + "rc32434 ethernet Tx", dev)) {
1649 + ERR(": unable to get Tx DMA IRQ %d\n",
1650 + lp->tx_irq);
1651 + free_irq(lp->rx_irq, dev);
1652 + return -EAGAIN;
1653 + }
1654 +
1655 +#ifdef RC32434_REVISION
1656 + /* Install handler for overrun error. */
1657 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1658 + SA_SHIRQ | SA_INTERRUPT,
1659 + "Ethernet Overflow", dev)) {
1660 + ERR(": unable to get OVR IRQ %d\n",
1661 + lp->ovr_irq);
1662 + free_irq(lp->rx_irq, dev);
1663 + free_irq(lp->tx_irq, dev);
1664 + return -EAGAIN;
1665 + }
1666 +#endif
1667 +
1668 + /* Install handler for underflow error. */
1669 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1670 + SA_SHIRQ | SA_INTERRUPT,
1671 + "Ethernet Underflow", dev)) {
1672 + ERR(": unable to get UND IRQ %d\n",
1673 + lp->und_irq);
1674 + free_irq(lp->rx_irq, dev);
1675 + free_irq(lp->tx_irq, dev);
1676 +#ifdef RC32434_REVISION
1677 + free_irq(lp->ovr_irq, dev);
1678 +#endif
1679 + return -EAGAIN;
1680 + }
1681 +
1682 +
1683 + return 0;
1684 +}
1685 +
1686 +
1687 +
1688 +
1689 +static int rc32434_close(struct net_device *dev)
1690 +{
1691 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1692 + u32 tmp;
1693 +
1694 + /* Disable interrupts */
1695 + disable_irq(lp->rx_irq);
1696 + disable_irq(lp->tx_irq);
1697 +#ifdef RC32434_REVISION
1698 + disable_irq(lp->ovr_irq);
1699 +#endif
1700 + disable_irq(lp->und_irq);
1701 +
1702 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1703 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1704 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1705 +
1706 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1707 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1708 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1709 +
1710 + free_irq(lp->rx_irq, dev);
1711 + free_irq(lp->tx_irq, dev);
1712 +#ifdef RC32434_REVISION
1713 + free_irq(lp->ovr_irq, dev);
1714 +#endif
1715 + free_irq(lp->und_irq, dev);
1716 + return 0;
1717 +}
1718 +
1719 +
1720 +/* transmit packet */
1721 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1722 +{
1723 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1724 + unsigned long flags;
1725 + u32 length;
1726 + DMAD_t td;
1727 +
1728 +
1729 + spin_lock_irqsave(&lp->lock, flags);
1730 +
1731 + td = &lp->td_ring[lp->tx_chain_tail];
1732 +
1733 + /* stop queue when full, drop pkts if queue already full */
1734 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1735 + lp->tx_full = 1;
1736 +
1737 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1738 + netif_stop_queue(dev);
1739 + }
1740 + else {
1741 + lp->stats.tx_dropped++;
1742 + dev_kfree_skb_any(skb);
1743 + spin_unlock_irqrestore(&lp->lock, flags);
1744 + return 1;
1745 + }
1746 + }
1747 +
1748 + lp->tx_count ++;
1749 +
1750 + lp->tx_skb[lp->tx_chain_tail] = skb;
1751 +
1752 + length = skb->len;
1753 +
1754 + /* Setup the transmit descriptor. */
1755 + td->ca = CPHYSADDR(skb->data);
1756 +
1757 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1758 + if( lp->tx_chain_status == empty ) {
1759 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1760 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1761 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1762 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1763 + }
1764 + else {
1765 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1766 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1767 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1768 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1769 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1770 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1771 + lp->tx_chain_status = empty;
1772 + }
1773 + }
1774 + else {
1775 + if( lp->tx_chain_status == empty ) {
1776 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1777 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1778 + lp->tx_chain_status = filled;
1779 + }
1780 + else {
1781 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1782 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1783 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1784 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1785 + }
1786 + }
1787 +
1788 + dev->trans_start = jiffies;
1789 +
1790 + spin_unlock_irqrestore(&lp->lock, flags);
1791 +
1792 + return 0;
1793 +}
1794 +
1795 +
1796 +/* Ethernet MII-PHY Handler */
1797 +static void rc32434_mii_handler(unsigned long data)
1798 +{
1799 + struct net_device *dev = (struct net_device *)data;
1800 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1801 + unsigned long flags;
1802 + unsigned long duplex_status;
1803 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1804 +
1805 + spin_lock_irqsave(&lp->lock, flags);
1806 +
1807 + /* Two ports are using the same MII, the difference is the PHY address */
1808 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1809 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1810 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1811 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1812 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1813 +
1814 + ERR("irq:%x port_addr:%x RDD:%x\n",
1815 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1816 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1817 + if(duplex_status != lp->duplex_mode) {
1818 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1819 + lp->duplex_mode = duplex_status;
1820 + rc32434_restart(dev);
1821 + }
1822 +
1823 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1824 + add_timer(&lp->mii_phy_timer);
1825 +
1826 + spin_unlock_irqrestore(&lp->lock, flags);
1827 +
1828 +}
1829 +
1830 +#ifdef RC32434_REVISION
1831 +/* Ethernet Rx Overflow interrupt */
1832 +static irqreturn_t
1833 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1834 +{
1835 + struct net_device *dev = (struct net_device *)dev_id;
1836 + struct rc32434_local *lp;
1837 + unsigned int ovr;
1838 + irqreturn_t retval = IRQ_NONE;
1839 +
1840 + ASSERT(dev != NULL);
1841 +
1842 + lp = (struct rc32434_local *)dev->priv;
1843 + spin_lock(&lp->lock);
1844 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1845 +
1846 + if(ovr & ETHINTFC_ovr_m) {
1847 + netif_stop_queue(dev);
1848 +
1849 + /* clear OVR bit */
1850 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1851 +
1852 + /* Restart interface */
1853 + rc32434_restart(dev);
1854 + retval = IRQ_HANDLED;
1855 + }
1856 + spin_unlock(&lp->lock);
1857 +
1858 + return retval;
1859 +}
1860 +
1861 +#endif
1862 +
1863 +
1864 +/* Ethernet Tx Underflow interrupt */
1865 +static irqreturn_t
1866 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1867 +{
1868 + struct net_device *dev = (struct net_device *)dev_id;
1869 + struct rc32434_local *lp;
1870 + unsigned int und;
1871 + irqreturn_t retval = IRQ_NONE;
1872 +
1873 + ASSERT(dev != NULL);
1874 +
1875 + lp = (struct rc32434_local *)dev->priv;
1876 +
1877 + spin_lock(&lp->lock);
1878 +
1879 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1880 +
1881 + if(und & ETHINTFC_und_m) {
1882 + netif_stop_queue(dev);
1883 +
1884 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1885 +
1886 + /* Restart interface */
1887 + rc32434_restart(dev);
1888 + retval = IRQ_HANDLED;
1889 + }
1890 +
1891 + spin_unlock(&lp->lock);
1892 +
1893 + return retval;
1894 +}
1895 +
1896 +
1897 +/* Ethernet Rx DMA interrupt */
1898 +static irqreturn_t
1899 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1900 +{
1901 + struct net_device *dev = (struct net_device *)dev_id;
1902 + struct rc32434_local* lp;
1903 + volatile u32 dmas,dmasm;
1904 + irqreturn_t retval;
1905 +
1906 + ASSERT(dev != NULL);
1907 +
1908 + lp = (struct rc32434_local *)dev->priv;
1909 +
1910 + spin_lock(&lp->lock);
1911 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1912 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1913 + /* Mask D H E bit in Rx DMA */
1914 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1915 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1916 +#ifdef CONFIG_IDT_USE_NAPI
1917 + if(netif_rx_schedule_prep(dev))
1918 + __netif_rx_schedule(dev);
1919 +#else
1920 + tasklet_hi_schedule(lp->rx_tasklet);
1921 +#endif
1922 +
1923 + if (dmas & DMAS_e_m)
1924 + ERR(": DMA error\n");
1925 +
1926 + retval = IRQ_HANDLED;
1927 + }
1928 + else
1929 + retval = IRQ_NONE;
1930 +
1931 + spin_unlock(&lp->lock);
1932 + return retval;
1933 +}
1934 +
1935 +#ifdef CONFIG_IDT_USE_NAPI
1936 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1937 +#else
1938 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1939 +#endif
1940 +{
1941 + struct net_device *dev = (struct net_device *)rx_data_dev;
1942 + struct rc32434_local* lp = netdev_priv(dev);
1943 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1944 + struct sk_buff *skb, *skb_new;
1945 + u8* pkt_buf;
1946 + u32 devcs, count, pkt_len, pktuncrc_len;
1947 + volatile u32 dmas;
1948 +#ifdef CONFIG_IDT_USE_NAPI
1949 + u32 received = 0;
1950 + int rx_work_limit = min(*budget,dev->quota);
1951 +#else
1952 + unsigned long flags;
1953 + spin_lock_irqsave(&lp->lock, flags);
1954 +#endif
1955 +
1956 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1957 +#ifdef CONFIG_IDT_USE_NAPI
1958 + if(--rx_work_limit <0)
1959 + {
1960 + break;
1961 + }
1962 +#endif
1963 + /* init the var. used for the later operations within the while loop */
1964 + skb_new = NULL;
1965 + devcs = rd->devcs;
1966 + pkt_len = RCVPKT_LENGTH(devcs);
1967 + skb = lp->rx_skb[lp->rx_next_done];
1968 +
1969 + if (count < 64) {
1970 + lp->stats.rx_errors++;
1971 + lp->stats.rx_dropped++;
1972 + }
1973 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1974 + /* check that this is a whole packet */
1975 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1976 + lp->stats.rx_errors++;
1977 + lp->stats.rx_dropped++;
1978 + }
1979 + else if ( (devcs & ETHRX_rok_m) ) {
1980 +
1981 + {
1982 + /* must be the (first and) last descriptor then */
1983 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1984 +
1985 + pktuncrc_len = pkt_len - 4;
1986 + /* invalidate the cache */
1987 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
1988 +
1989 + /* Malloc up new buffer. */
1990 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
1991 +
1992 + if (skb_new != NULL){
1993 + /* Make room */
1994 + skb_put(skb, pktuncrc_len);
1995 +
1996 + skb->protocol = eth_type_trans(skb, dev);
1997 +
1998 + /* pass the packet to upper layers */
1999 +#ifdef CONFIG_IDT_USE_NAPI
2000 + netif_receive_skb(skb);
2001 +#else
2002 + netif_rx(skb);
2003 +#endif
2004 +
2005 + dev->last_rx = jiffies;
2006 + lp->stats.rx_packets++;
2007 + lp->stats.rx_bytes += pktuncrc_len;
2008 +
2009 + if (IS_RCV_MP(devcs))
2010 + lp->stats.multicast++;
2011 +
2012 + /* 16 bit align */
2013 + skb_reserve(skb_new, 2);
2014 +
2015 + skb_new->dev = dev;
2016 + lp->rx_skb[lp->rx_next_done] = skb_new;
2017 + }
2018 + else {
2019 + ERR("no memory, dropping rx packet.\n");
2020 + lp->stats.rx_errors++;
2021 + lp->stats.rx_dropped++;
2022 + }
2023 + }
2024 +
2025 + }
2026 + else {
2027 + /* This should only happen if we enable accepting broken packets */
2028 + lp->stats.rx_errors++;
2029 + lp->stats.rx_dropped++;
2030 +
2031 + /* add statistics counters */
2032 + if (IS_RCV_CRC_ERR(devcs)) {
2033 + DBG(2, "RX CRC error\n");
2034 + lp->stats.rx_crc_errors++;
2035 + }
2036 + else if (IS_RCV_LOR_ERR(devcs)) {
2037 + DBG(2, "RX LOR error\n");
2038 + lp->stats.rx_length_errors++;
2039 + }
2040 + else if (IS_RCV_LE_ERR(devcs)) {
2041 + DBG(2, "RX LE error\n");
2042 + lp->stats.rx_length_errors++;
2043 + }
2044 + else if (IS_RCV_OVR_ERR(devcs)) {
2045 + lp->stats.rx_over_errors++;
2046 + }
2047 + else if (IS_RCV_CV_ERR(devcs)) {
2048 + /* code violation */
2049 + DBG(2, "RX CV error\n");
2050 + lp->stats.rx_frame_errors++;
2051 + }
2052 + else if (IS_RCV_CES_ERR(devcs)) {
2053 + DBG(2, "RX Preamble error\n");
2054 + }
2055 + }
2056 +
2057 + rd->devcs = 0;
2058 +
2059 + /* restore descriptor's curr_addr */
2060 + if(skb_new)
2061 + rd->ca = CPHYSADDR(skb_new->data);
2062 + else
2063 + rd->ca = CPHYSADDR(skb->data);
2064 +
2065 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2066 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2067 +
2068 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2069 + rd = &lp->rd_ring[lp->rx_next_done];
2070 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2071 + }
2072 +#ifdef CONFIG_IDT_USE_NAPI
2073 + dev->quota -= received;
2074 + *budget =- received;
2075 + if(rx_work_limit < 0)
2076 + goto not_done;
2077 +#endif
2078 +
2079 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2080 +
2081 + if(dmas & DMAS_h_m) {
2082 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2083 +#ifdef RC32434_PROC_DEBUG
2084 + lp->dma_halt_cnt++;
2085 +#endif
2086 + rd->devcs = 0;
2087 + skb = lp->rx_skb[lp->rx_next_done];
2088 + rd->ca = CPHYSADDR(skb->data);
2089 + rc32434_chain_rx(lp,rd);
2090 + }
2091 +
2092 +#ifdef CONFIG_IDT_USE_NAPI
2093 + netif_rx_complete(dev);
2094 +#endif
2095 + /* Enable D H E bit in Rx DMA */
2096 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2097 +#ifdef CONFIG_IDT_USE_NAPI
2098 + return 0;
2099 + not_done:
2100 + return 1;
2101 +#else
2102 + spin_unlock_irqrestore(&lp->lock, flags);
2103 + return;
2104 +#endif
2105 +
2106 +
2107 +}
2108 +
2109 +
2110 +
2111 +/* Ethernet Tx DMA interrupt */
2112 +static irqreturn_t
2113 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2114 +{
2115 + struct net_device *dev = (struct net_device *)dev_id;
2116 + struct rc32434_local *lp;
2117 + volatile u32 dmas,dmasm;
2118 + irqreturn_t retval;
2119 +
2120 + ASSERT(dev != NULL);
2121 +
2122 + lp = (struct rc32434_local *)dev->priv;
2123 +
2124 + spin_lock(&lp->lock);
2125 +
2126 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2127 +
2128 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2129 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2130 + /* Mask F E bit in Tx DMA */
2131 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2132 +
2133 + tasklet_hi_schedule(lp->tx_tasklet);
2134 +
2135 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2136 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2137 + lp->tx_chain_status = empty;
2138 + lp->tx_chain_head = lp->tx_chain_tail;
2139 + dev->trans_start = jiffies;
2140 + }
2141 +
2142 + if (dmas & DMAS_e_m)
2143 + ERR(": DMA error\n");
2144 +
2145 + retval = IRQ_HANDLED;
2146 + }
2147 + else
2148 + retval = IRQ_NONE;
2149 +
2150 + spin_unlock(&lp->lock);
2151 +
2152 + return retval;
2153 +}
2154 +
2155 +
2156 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2157 +{
2158 + struct net_device *dev = (struct net_device *)tx_data_dev;
2159 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2160 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2161 + u32 devcs;
2162 + unsigned long flags;
2163 + volatile u32 dmas;
2164 +
2165 + spin_lock_irqsave(&lp->lock, flags);
2166 +
2167 + /* process all desc that are done */
2168 + while(IS_DMA_FINISHED(td->control)) {
2169 + if(lp->tx_full == 1) {
2170 + netif_wake_queue(dev);
2171 + lp->tx_full = 0;
2172 + }
2173 +
2174 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2175 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2176 + lp->stats.tx_errors++;
2177 + lp->stats.tx_dropped++;
2178 +
2179 + /* should never happen */
2180 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2181 + }
2182 + else if (IS_TX_TOK(devcs)) {
2183 + lp->stats.tx_packets++;
2184 + }
2185 + else {
2186 + lp->stats.tx_errors++;
2187 + lp->stats.tx_dropped++;
2188 +
2189 + /* underflow */
2190 + if (IS_TX_UND_ERR(devcs))
2191 + lp->stats.tx_fifo_errors++;
2192 +
2193 + /* oversized frame */
2194 + if (IS_TX_OF_ERR(devcs))
2195 + lp->stats.tx_aborted_errors++;
2196 +
2197 + /* excessive deferrals */
2198 + if (IS_TX_ED_ERR(devcs))
2199 + lp->stats.tx_carrier_errors++;
2200 +
2201 + /* collisions: medium busy */
2202 + if (IS_TX_EC_ERR(devcs))
2203 + lp->stats.collisions++;
2204 +
2205 + /* late collision */
2206 + if (IS_TX_LC_ERR(devcs))
2207 + lp->stats.tx_window_errors++;
2208 +
2209 + }
2210 +
2211 + /* We must always free the original skb */
2212 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2213 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2214 + lp->tx_skb[lp->tx_next_done] = NULL;
2215 + }
2216 +
2217 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2218 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2219 + lp->td_ring[lp->tx_next_done].link = 0;
2220 + lp->td_ring[lp->tx_next_done].ca = 0;
2221 + lp->tx_count --;
2222 +
2223 + /* go on to next transmission */
2224 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2225 + td = &lp->td_ring[lp->tx_next_done];
2226 +
2227 + }
2228 +
2229 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2230 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2231 +
2232 + /* Enable F E bit in Tx DMA */
2233 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2234 + spin_unlock_irqrestore(&lp->lock, flags);
2235 +
2236 +}
2237 +
2238 +
2239 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2240 +{
2241 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2242 + return &lp->stats;
2243 +}
2244 +
2245 +
2246 +/*
2247 + * Set or clear the multicast filter for this adaptor.
2248 + */
2249 +static void rc32434_multicast_list(struct net_device *dev)
2250 +{
2251 + /* listen to broadcasts always and to treat */
2252 + /* IFF bits independantly */
2253 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2254 + unsigned long flags;
2255 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2256 +
2257 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2258 + recognise |= ETHARC_pro_m;
2259 +
2260 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2261 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2262 + else if (dev->mc_count > 0) {
2263 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2264 + recognise |= ETHARC_am_m; /* for the time being */
2265 + }
2266 +
2267 + spin_lock_irqsave(&lp->lock, flags);
2268 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2269 + spin_unlock_irqrestore(&lp->lock, flags);
2270 +}
2271 +
2272 +
2273 +static void rc32434_tx_timeout(struct net_device *dev)
2274 +{
2275 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2276 + unsigned long flags;
2277 +
2278 + spin_lock_irqsave(&lp->lock, flags);
2279 + rc32434_restart(dev);
2280 + spin_unlock_irqrestore(&lp->lock, flags);
2281 +
2282 +}
2283 +
2284 +
2285 +/*
2286 + * Initialize the RC32434 ethernet controller.
2287 + */
2288 +static int rc32434_init(struct net_device *dev)
2289 +{
2290 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2291 + int i, j;
2292 +
2293 + /* Disable DMA */
2294 + rc32434_abort_tx(dev);
2295 + rc32434_abort_rx(dev);
2296 +
2297 + /* reset ethernet logic */
2298 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2299 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2300 + dev->trans_start = jiffies;
2301 +
2302 + /* Enable Ethernet Interface */
2303 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2304 +
2305 +#ifndef CONFIG_IDT_USE_NAPI
2306 + tasklet_disable(lp->rx_tasklet);
2307 +#endif
2308 + tasklet_disable(lp->tx_tasklet);
2309 +
2310 + /* Initialize the transmit Descriptors */
2311 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2312 + lp->td_ring[i].control = DMAD_iof_m;
2313 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2314 + lp->td_ring[i].ca = 0;
2315 + lp->td_ring[i].link = 0;
2316 + if (lp->tx_skb[i] != NULL) {
2317 + dev_kfree_skb_any(lp->tx_skb[i]);
2318 + lp->tx_skb[i] = NULL;
2319 + }
2320 + }
2321 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2322 + lp-> tx_chain_status = empty;
2323 +
2324 + /*
2325 + * Initialize the receive descriptors so that they
2326 + * become a circular linked list, ie. let the last
2327 + * descriptor point to the first again.
2328 + */
2329 + for (i=0; i<RC32434_NUM_RDS; i++) {
2330 + struct sk_buff *skb = lp->rx_skb[i];
2331 +
2332 + if (lp->rx_skb[i] == NULL) {
2333 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2334 + if (skb == NULL) {
2335 + ERR("No memory in the system\n");
2336 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2337 + if (lp->rx_skb[j] != NULL)
2338 + dev_kfree_skb_any(lp->rx_skb[j]);
2339 +
2340 + return 1;
2341 + }
2342 + else {
2343 + skb->dev = dev;
2344 + skb_reserve(skb, 2);
2345 + lp->rx_skb[i] = skb;
2346 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2347 +
2348 + }
2349 + }
2350 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2351 + lp->rd_ring[i].devcs = 0;
2352 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2353 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2354 +
2355 + }
2356 + /* loop back */
2357 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2358 + lp->rx_next_done = 0;
2359 +
2360 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2361 + lp->rx_chain_head = 0;
2362 + lp->rx_chain_tail = 0;
2363 + lp->rx_chain_status = empty;
2364 +
2365 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2366 + /* Start Rx DMA */
2367 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2368 +
2369 + /* Enable F E bit in Tx DMA */
2370 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2371 + /* Enable D H E bit in Rx DMA */
2372 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2373 +
2374 + /* Accept only packets destined for this Ethernet device address */
2375 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2376 +
2377 + /* Set all Ether station address registers to their initial values */
2378 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2379 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2380 +
2381 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2382 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2383 +
2384 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2385 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2386 +
2387 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2388 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2389 +
2390 +
2391 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2392 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2393 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2394 +
2395 + /* Back to back inter-packet-gap */
2396 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2397 + /* Non - Back to back inter-packet-gap */
2398 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2399 +
2400 + /* Management Clock Prescaler Divisor */
2401 + /* Clock independent setting */
2402 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2403 + &lp->eth_regs->ethmcp);
2404 +
2405 + /* don't transmit until fifo contains 48b */
2406 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2407 +
2408 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2409 +
2410 +#ifndef CONFIG_IDT_USE_NAPI
2411 + tasklet_enable(lp->rx_tasklet);
2412 +#endif
2413 + tasklet_enable(lp->tx_tasklet);
2414 +
2415 + netif_start_queue(dev);
2416 +
2417 +
2418 + return 0;
2419 +
2420 +}
2421 +
2422 +
2423 +#ifndef MODULE
2424 +
2425 +static int __init rc32434_setup(char *options)
2426 +{
2427 + /* no options yet */
2428 + return 1;
2429 +}
2430 +
2431 +static int __init rc32434_setup_ethaddr0(char *options)
2432 +{
2433 + memcpy(mac0, options, 17);
2434 + mac0[17]= '\0';
2435 + return 1;
2436 +}
2437 +
2438 +__setup("rc32434eth=", rc32434_setup);
2439 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2440 +
2441 +
2442 +#endif /* MODULE */
2443 +
2444 +module_init(rc32434_init_module);
2445 +module_exit(rc32434_cleanup_module);
2446 +
2447 +
2448 +
2449 +
2450 +
2451 +
2452 +
2453 +
2454 +
2455 +
2456 +
2457 +
2458 +
2459 +
2460 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.h linux-2.6.16-owrt/drivers/net/rc32434_eth.h
2461 --- linux-2.6.16/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2462 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.h 2006-03-20 14:25:10.000000000 +0100
2463 @@ -0,0 +1,187 @@
2464 +/**************************************************************************
2465 + *
2466 + * BRIEF MODULE DESCRIPTION
2467 + * Definitions for IDT RC32434 on-chip ethernet controller.
2468 + *
2469 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2470 + *
2471 + * This program is free software; you can redistribute it and/or modify it
2472 + * under the terms of the GNU General Public License as published by the
2473 + * Free Software Foundation; either version 2 of the License, or (at your
2474 + * option) any later version.
2475 + *
2476 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2477 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2478 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2479 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2480 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2481 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2482 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2483 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2484 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2485 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2486 + *
2487 + * You should have received a copy of the GNU General Public License along
2488 + * with this program; if not, write to the Free Software Foundation, Inc.,
2489 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2490 + *
2491 + *
2492 + **************************************************************************
2493 + * May 2004 rkt, neb
2494 + *
2495 + * Initial Release
2496 + *
2497 + * Aug 2004
2498 + *
2499 + * Added NAPI
2500 + *
2501 + **************************************************************************
2502 + */
2503 +
2504 +
2505 +#include <asm/idt-boards/rc32434/rc32434.h>
2506 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2507 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2508 +
2509 +#define RC32434_DEBUG 2
2510 +//#define RC32434_PROC_DEBUG
2511 +#undef RC32434_DEBUG
2512 +
2513 +#ifdef RC32434_DEBUG
2514 +
2515 +/* use 0 for production, 1 for verification, >2 for debug */
2516 +static int rc32434_debug = RC32434_DEBUG;
2517 +#define ASSERT(expr) \
2518 + if(!(expr)) { \
2519 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2520 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2521 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2522 +#else
2523 +#define ASSERT(expr) do {} while (0)
2524 +#define DBG(lvl, format, arg...) do {} while (0)
2525 +#endif
2526 +
2527 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2528 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2529 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2530 +
2531 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2532 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2533 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2534 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2535 +
2536 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2537 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2538 +
2539 +/* the following must be powers of two */
2540 +#ifdef CONFIG_IDT_USE_NAPI
2541 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2542 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2543 +#else
2544 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2545 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2546 +#endif
2547 +
2548 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2549 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2550 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2551 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2552 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2553 +
2554 +#define RC32434_TX_TIMEOUT HZ * 100
2555 +
2556 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2557 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2558 +
2559 +enum status { filled, empty};
2560 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2561 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2562 +
2563 +
2564 +/* Information that need to be kept for each board. */
2565 +struct rc32434_local {
2566 + ETH_t eth_regs;
2567 + DMA_Chan_t rx_dma_regs;
2568 + DMA_Chan_t tx_dma_regs;
2569 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2570 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2571 +
2572 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2573 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2574 +
2575 +#ifndef CONFIG_IDT_USE_NAPI
2576 + struct tasklet_struct * rx_tasklet;
2577 +#endif
2578 + struct tasklet_struct * tx_tasklet;
2579 +
2580 + int rx_next_done;
2581 + int rx_chain_head;
2582 + int rx_chain_tail;
2583 + enum status rx_chain_status;
2584 +
2585 + int tx_next_done;
2586 + int tx_chain_head;
2587 + int tx_chain_tail;
2588 + enum status tx_chain_status;
2589 + int tx_count;
2590 + int tx_full;
2591 +
2592 + struct timer_list mii_phy_timer;
2593 + unsigned long duplex_mode;
2594 +
2595 + int rx_irq;
2596 + int tx_irq;
2597 + int ovr_irq;
2598 + int und_irq;
2599 +
2600 + struct net_device_stats stats;
2601 + spinlock_t lock;
2602 +
2603 + /* debug /proc entry */
2604 + struct proc_dir_entry *ps;
2605 + int dma_halt_cnt; int dma_run_cnt;
2606 +};
2607 +
2608 +extern unsigned int idt_cpu_freq;
2609 +
2610 +/* Index to functions, as function prototypes. */
2611 +static int rc32434_open(struct net_device *dev);
2612 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2613 +static void rc32434_mii_handler(unsigned long data);
2614 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2615 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2616 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2617 +#ifdef RC32434_REVISION
2618 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2619 +#endif
2620 +static int rc32434_close(struct net_device *dev);
2621 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2622 +static void rc32434_multicast_list(struct net_device *dev);
2623 +static int rc32434_init(struct net_device *dev);
2624 +static void rc32434_tx_timeout(struct net_device *dev);
2625 +
2626 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2627 +#ifdef CONFIG_IDT_USE_NAPI
2628 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2629 +#else
2630 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2631 +#endif
2632 +static void rc32434_cleanup_module(void);
2633 +static int rc32434_probe(int port_num);
2634 +int rc32434_init_module(void);
2635 +
2636 +
2637 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2638 +{
2639 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2640 + rc32434_writel(0x10, &ch->dmac);
2641 +
2642 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2643 + dev->trans_start = jiffies;
2644 +
2645 + rc32434_writel(0, &ch->dmas);
2646 + }
2647 +
2648 + rc32434_writel(0, &ch->dmadptr);
2649 + rc32434_writel(0, &ch->dmandptr);
2650 +}
2651 diff -Nur linux-2.6.16/include/asm-mips/bootinfo.h linux-2.6.16-owrt/include/asm-mips/bootinfo.h
2652 --- linux-2.6.16/include/asm-mips/bootinfo.h 2006-03-20 06:53:29.000000000 +0100
2653 +++ linux-2.6.16-owrt/include/asm-mips/bootinfo.h 2006-03-20 14:25:10.000000000 +0100
2654 @@ -218,6 +218,17 @@
2655 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2656 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2657
2658 +
2659 +/*
2660 + * Valid machtype for group ARUBA
2661 + */
2662 +#define MACH_GROUP_ARUBA 23
2663 +#define MACH_ARUBA_UNKNOWN 0
2664 +#define MACH_ARUBA_AP60 1
2665 +#define MACH_ARUBA_AP65 2
2666 +#define MACH_ARUBA_AP70 3
2667 +#define MACH_ARUBA_AP40 4
2668 +
2669 #define CL_SIZE COMMAND_LINE_SIZE
2670
2671 const char *get_system_type(void);
2672 diff -Nur linux-2.6.16/include/asm-mips/cpu.h linux-2.6.16-owrt/include/asm-mips/cpu.h
2673 --- linux-2.6.16/include/asm-mips/cpu.h 2006-03-20 06:53:29.000000000 +0100
2674 +++ linux-2.6.16-owrt/include/asm-mips/cpu.h 2006-03-20 14:25:10.000000000 +0100
2675 @@ -53,6 +53,9 @@
2676 #define PRID_IMP_R12000 0x0e00
2677 #define PRID_IMP_R8000 0x1000
2678 #define PRID_IMP_PR4450 0x1200
2679 +#define PRID_IMP_RC32334 0x1800
2680 +#define PRID_IMP_RC32355 0x1900
2681 +#define PRID_IMP_RC32365 0x1900
2682 #define PRID_IMP_R4600 0x2000
2683 #define PRID_IMP_R4700 0x2100
2684 #define PRID_IMP_TX39 0x2200
2685 @@ -196,7 +199,8 @@
2686 #define CPU_34K 60
2687 #define CPU_PR4450 61
2688 #define CPU_SB1A 62
2689 -#define CPU_LAST 62
2690 +#define CPU_RC32300 63
2691 +#define CPU_LAST 63
2692
2693 /*
2694 * ISA Level encodings
2695 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2696 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2697 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-03-20 14:25:10.000000000 +0100
2698 @@ -0,0 +1,142 @@
2699 +/**************************************************************************
2700 + *
2701 + * BRIEF MODULE DESCRIPTION
2702 + * RC32300 helper routines
2703 + *
2704 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2705 + *
2706 + * This program is free software; you can redistribute it and/or modify it
2707 + * under the terms of the GNU General Public License as published by the
2708 + * Free Software Foundation; either version 2 of the License, or (at your
2709 + * option) any later version.
2710 + *
2711 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2712 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2713 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2714 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2715 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2716 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2717 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2718 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2719 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2720 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2721 + *
2722 + * You should have received a copy of the GNU General Public License along
2723 + * with this program; if not, write to the Free Software Foundation, Inc.,
2724 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2725 + *
2726 + *
2727 + **************************************************************************
2728 + * May 2004 P. Sadik.
2729 + *
2730 + * Initial Release
2731 + *
2732 + *
2733 + *
2734 + **************************************************************************
2735 + */
2736 +
2737 +#ifndef __IDT_RC32300_H__
2738 +#define __IDT_RC32300_H__
2739 +
2740 +#include <linux/delay.h>
2741 +#include <asm/io.h>
2742 +
2743 +
2744 +/* cpu pipeline flush */
2745 +static inline void rc32300_sync(void)
2746 +{
2747 + __asm__ volatile ("sync");
2748 +}
2749 +
2750 +static inline void rc32300_sync_udelay(int us)
2751 +{
2752 + __asm__ volatile ("sync");
2753 + udelay(us);
2754 +}
2755 +
2756 +static inline void rc32300_sync_delay(int ms)
2757 +{
2758 + __asm__ volatile ("sync");
2759 + mdelay(ms);
2760 +}
2761 +
2762 +/*
2763 + * Macros to access internal RC32300 registers. No byte
2764 + * swapping should be done when accessing the internal
2765 + * registers.
2766 + */
2767 +
2768 +static inline u8 rc32300_readb(unsigned long pa)
2769 +{
2770 + return *((volatile u8 *)KSEG1ADDR(pa));
2771 +}
2772 +static inline u16 rc32300_readw(unsigned long pa)
2773 +{
2774 + return *((volatile u16 *)KSEG1ADDR(pa));
2775 +}
2776 +static inline u32 rc32300_readl(unsigned long pa)
2777 +{
2778 + return *((volatile u32 *)KSEG1ADDR(pa));
2779 +}
2780 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2781 +{
2782 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2783 +}
2784 +static inline void rc32300_writew(u16 val, unsigned long pa)
2785 +{
2786 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2787 +}
2788 +static inline void rc32300_writel(u32 val, unsigned long pa)
2789 +{
2790 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2791 +}
2792 +
2793 +
2794 +#define local_readb __raw_readb
2795 +#define local_readw __raw_readw
2796 +#define local_readl __raw_readl
2797 +
2798 +#define local_writeb __raw_writeb
2799 +#define local_writew __raw_writew
2800 +#define local_writel __raw_writel
2801 +
2802 +
2803 +/*
2804 + * C access to CLZ and CLO instructions
2805 + * (count leading zeroes/ones).
2806 + */
2807 +static inline int rc32300_clz(unsigned long val)
2808 +{
2809 + int ret;
2810 + __asm__ volatile (
2811 + ".set\tnoreorder\n\t"
2812 + ".set\tnoat\n\t"
2813 + ".set\tmips32\n\t"
2814 + "clz\t%0,%1\n\t"
2815 + ".set\tmips0\n\t"
2816 + ".set\tat\n\t"
2817 + ".set\treorder"
2818 + : "=r" (ret)
2819 + : "r" (val));
2820 +
2821 + return ret;
2822 +}
2823 +static inline int rc32300_clo(unsigned long val)
2824 +{
2825 + int ret;
2826 + __asm__ volatile (
2827 + ".set\tnoreorder\n\t"
2828 + ".set\tnoat\n\t"
2829 + ".set\tmips32\n\t"
2830 + "clo\t%0,%1\n\t"
2831 + ".set\tmips0\n\t"
2832 + ".set\tat\n\t"
2833 + ".set\treorder"
2834 + : "=r" (ret)
2835 + : "r" (val));
2836 +
2837 + return ret;
2838 +}
2839 +
2840 +#endif // __IDT_RC32300_H__
2841 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2842 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2843 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-03-20 14:25:10.000000000 +0100
2844 @@ -0,0 +1,207 @@
2845 +/**************************************************************************
2846 + *
2847 + * BRIEF MODULE DESCRIPTION
2848 + * Definitions for IDT RC32334 CPU.
2849 + *
2850 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2851 + *
2852 + * This program is free software; you can redistribute it and/or modify it
2853 + * under the terms of the GNU General Public License as published by the
2854 + * Free Software Foundation; either version 2 of the License, or (at your
2855 + * option) any later version.
2856 + *
2857 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2858 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2859 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2860 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2861 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2862 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2863 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2864 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2865 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2866 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2867 + *
2868 + * You should have received a copy of the GNU General Public License along
2869 + * with this program; if not, write to the Free Software Foundation, Inc.,
2870 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2871 + *
2872 + *
2873 + **************************************************************************
2874 + * May 2004 P. Sadik.
2875 + *
2876 + * Initial Release
2877 + *
2878 + *
2879 + *
2880 + **************************************************************************
2881 + */
2882 +
2883 +
2884 +#ifndef __IDT_RC32334_H__
2885 +#define __IDT_RC32334_H__
2886 +
2887 +#include <linux/delay.h>
2888 +#include <asm/io.h>
2889 +
2890 +/* Base address of internal registers */
2891 +#define RC32334_REG_BASE 0x18000000
2892 +
2893 +/* CPU and IP Bus Control */
2894 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2895 +#define CPU_BTA 0xffffe204 // virtual!
2896 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2897 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2898 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2899 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2900 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2901 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2902 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2903 +
2904 +/* Memory Controller */
2905 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2906 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2907 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2908 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2909 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2910 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2911 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2912 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2913 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2914 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2915 +
2916 +/* PCI Controller */
2917 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2918 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2919 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2920 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2921 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2922 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2923 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2924 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2925 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2926 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2927 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2928 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2929 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2930 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2931 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2932 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2933 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2934 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2935 +
2936 +/* Timers */
2937 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2938 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2939 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2940 +#define TIMER_REG_OFFSET 0x10
2941 +
2942 +/* Programmable I/O */
2943 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2944 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2945 +
2946 +/*
2947 + * DMA
2948 + *
2949 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2950 + *
2951 + * DMA0: 18001400
2952 + * DMA1: 18001440
2953 + * DMA2: 18001900
2954 + * DMA3: 18001940
2955 + * NB: dma number must be immediate value or variable.
2956 + * It MUST NOT be a function since it would get called twice!
2957 + */
2958 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2959 +
2960 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2961 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2962 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2963 +
2964 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2965 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2966 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2967 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2968 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2969 +
2970 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2971 +
2972 +/* Expansion Interrupt Controller */
2973 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2974 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2975 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2976 +#define IC_GROUP_OFFSET 0x10
2977 +
2978 +#define NUM_INTR_GROUPS 15
2979 +/*
2980 + * The IRQ mapping is as follows:
2981 + *
2982 + * IRQ Mapped To
2983 + * --- -------------------
2984 + * 0 SW0 (IP0) SW0 intr
2985 + * 1 SW1 (IP1) SW1 intr
2986 + * 2 Int0 (IP2) board-specific
2987 + * 3 Int1 (IP3) board-specific
2988 + * 4 Int2 (IP4) board-specific
2989 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
2990 + * 6 Int4 (IP6) board-specific
2991 + * 7 Int5 (IP7) CP0 Timer
2992 + *
2993 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
2994 + * internally on the RC32334 is routed to the Expansion
2995 + * Interrupt Controller.
2996 + */
2997 +#define MIPS_CPU_TIMER_IRQ 7
2998 +
2999 +#define GROUP1_IRQ_BASE 8 // bus error
3000 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3001 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3002 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3003 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3004 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3005 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3006 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3007 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3008 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3009 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3010 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3011 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3012 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3013 +
3014 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3015 +
3016 +/* 16550 UARTs */
3017 +#ifdef __MIPSEB__
3018 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3019 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3020 +#else
3021 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3022 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3023 +#endif
3024 +
3025 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3026 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3027 +
3028 +#define IDT_CLOCK_MULT 2
3029 +
3030 +/* NVRAM */
3031 +#define NVRAM_BASE 0x12000000
3032 +#define NVRAM_ENVSIZE_OFF 4
3033 +#define NVRAM_ENVSTART_OFF 0x40
3034 +
3035 +/* LCD 4-digit display */
3036 +#define LCD_CLEAR 0x14000400
3037 +#define LCD_DIGIT0 0x1400000f
3038 +#define LCD_DIGIT1 0x14000008
3039 +#define LCD_DIGIT2 0x14000007
3040 +#define LCD_DIGIT3 0x14000003
3041 +
3042 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3043 +#define RC32334_SCC8530_IRQ 2
3044 +#define RC32334_PCI_INTA_IRQ 3
3045 +#define RC32334_PCI_INTB_IRQ 4
3046 +#define RC32334_PCI_INTC_IRQ 6
3047 +#define RC32334_PCI_INTD_IRQ 7
3048 +
3049 +#define RAM_SIZE (32*1024*1024)
3050 +
3051 +#endif // __IDT_RC32334_H__
3052 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3053 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3054 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-03-20 14:25:10.000000000 +0100
3055 @@ -0,0 +1,206 @@
3056 +/**************************************************************************
3057 + *
3058 + * BRIEF MODULE DESCRIPTION
3059 + * DMA controller defines on IDT RC32355
3060 + *
3061 + * Copyright 2004 IDT Inc.
3062 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3063 + *
3064 + *
3065 + * This program is free software; you can redistribute it and/or modify it
3066 + * under the terms of the GNU General Public License as published by the
3067 + * Free Software Foundation; either version 2 of the License, or (at your
3068 + * option) any later version.
3069 + *
3070 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3071 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3072 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3073 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3074 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3075 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3076 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3077 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3078 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3079 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3080 + *
3081 + * You should have received a copy of the GNU General Public License along
3082 + * with this program; if not, write to the Free Software Foundation, Inc.,
3083 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3084 + *
3085 + *
3086 + * May 2004 rkt
3087 + * Initial Release
3088 + *
3089 + **************************************************************************
3090 + */
3091 +
3092 +#ifndef BANYAN_DMA_H
3093 +#define BANYAN_DMA_H
3094 +#include <asm/idt-boards/rc32300/rc32300.h>
3095 +
3096 +/*
3097 + * An image of one RC32355 dma channel registers
3098 + */
3099 +typedef struct {
3100 + u32 dmac;
3101 + u32 dmas;
3102 + u32 dmasm;
3103 + u32 dmadptr;
3104 + u32 dmandptr;
3105 +} rc32355_dma_ch_t;
3106 +
3107 +/*
3108 + * An image of all RC32355 dma channel registers
3109 + */
3110 +typedef struct {
3111 + rc32355_dma_ch_t ch[16];
3112 +} rc32355_dma_regs_t;
3113 +
3114 +
3115 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3116 +
3117 +
3118 +/* DMAC register layout */
3119 +
3120 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3121 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3122 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3123 +
3124 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3125 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3126 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3127 +
3128 +/* DMAS and DMASM register layout */
3129 +
3130 +#define DMAS_F 0x01 /* Finished */
3131 +#define DMAS_D 0x02 /* Done */
3132 +#define DMAS_C 0x04 /* Chain */
3133 +#define DMAS_E 0x08 /* Error */
3134 +#define DMAS_H 0x10 /* Halt */
3135 +
3136 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3137 +#define DMA_HALT_TIMEOUT 500
3138 +
3139 +
3140 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3141 +{
3142 + int timeout=1;
3143 +
3144 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3145 + local_writel(0, &ch->dmac);
3146 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3147 + if (local_readl(&ch->dmas) & DMAS_H) {
3148 + local_writel(0, &ch->dmas);
3149 + break;
3150 + }
3151 + }
3152 + }
3153 +
3154 + return timeout ? 0 : 1;
3155 +}
3156 +
3157 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3158 +{
3159 + local_writel(0, &ch->dmandptr);
3160 + local_writel(dma_addr, &ch->dmadptr);
3161 +}
3162 +
3163 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3164 +{
3165 + local_writel(dma_addr, &ch->dmandptr);
3166 +}
3167 +
3168 +
3169 +/* The following can be used to describe DMA channels 0 to 15, and the */
3170 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3171 +
3172 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3173 +
3174 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3175 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3176 +
3177 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3178 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3179 +
3180 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3181 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3182 +
3183 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3184 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3185 +
3186 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3187 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3188 +#define DMA_DEV_ATMVCC(entry) 0
3189 +
3190 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3191 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3192 +
3193 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3194 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3195 +
3196 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3197 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3198 +
3199 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3200 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3201 +
3202 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3203 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3204 +
3205 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3206 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3207 +
3208 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3209 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3210 +
3211 +#define DMA_CHAN_USBIN 13 /* USB input */
3212 +#define DMA_DEV_USBIN 0 /* USB input */
3213 +
3214 +#define DMA_CHAN_USBOUT 14 /* USB output */
3215 +#define DMA_DEV_USBOUT 0 /* USB output */
3216 +
3217 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3218 +#define DMA_DEV_EXTERN 0 /* External DMA */
3219 +
3220 +/*
3221 + * An RC32355 dma descriptor in system memory
3222 + */
3223 +typedef struct {
3224 + u32 cmdstat; /* control and status */
3225 + u32 curr_addr; /* current address of data */
3226 + u32 devcs; /* peripheral-specific control and status */
3227 + u32 link; /* link to next descriptor */
3228 +} rc32355_dma_desc_t;
3229 +
3230 +/* Values for the descriptor cmdstat word */
3231 +
3232 +#define DMADESC_F 0x80000000u /* Finished bit */
3233 +#define DMADESC_D 0x40000000u /* Done bit */
3234 +#define DMADESC_T 0x20000000u /* Terminated bit */
3235 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3236 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3237 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3238 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3239 +
3240 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3241 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3242 +
3243 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3244 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3245 +
3246 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3247 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3248 +
3249 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3250 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3251 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3252 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3253 +
3254 +#define DMA_DEVCMD(devcmd) \
3255 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3256 +#define DMA_DS(ds) \
3257 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3258 +#define DMA_COUNT(count) \
3259 + ((count) & DMADESC_COUNT_MASK)
3260 +
3261 +#endif /* RC32355_DMA_H */
3262 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3263 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3264 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-03-20 14:25:10.000000000 +0100
3265 @@ -0,0 +1,442 @@
3266 +/**************************************************************************
3267 + *
3268 + * BRIEF MODULE DESCRIPTION
3269 + * Ethernet registers on IDT RC32355
3270 + *
3271 + * Copyright 2004 IDT Inc.
3272 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3273 + *
3274 + *
3275 + * This program is free software; you can redistribute it and/or modify it
3276 + * under the terms of the GNU General Public License as published by the
3277 + * Free Software Foundation; either version 2 of the License, or (at your
3278 + * option) any later version.
3279 + *
3280 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3281 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3282 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3283 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3284 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3285 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3286 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3287 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3288 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3289 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3290 + *
3291 + * You should have received a copy of the GNU General Public License along
3292 + * with this program; if not, write to the Free Software Foundation, Inc.,
3293 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3294 + *
3295 + *
3296 + * May 2004 rkt
3297 + * Initial Release
3298 + *
3299 + **************************************************************************
3300 + */
3301 +
3302 +
3303 +#ifndef RC32355_ETHER_H
3304 +#define RC32355_ETHER_H
3305 +
3306 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3307 +
3308 +/*
3309 + * A partial image of the RC32355 ethernet registers
3310 + */
3311 +typedef struct {
3312 + u32 ethintfc;
3313 + u32 ethfifott;
3314 + u32 etharc;
3315 + u32 ethhash0;
3316 + u32 ethhash1;
3317 + u32 ethfifost;
3318 + u32 ethfifos;
3319 + u32 ethodeops;
3320 + u32 ethis;
3321 + u32 ethos;
3322 + u32 ethmcp;
3323 + u32 _u1;
3324 + u32 ethid;
3325 + u32 _u2;
3326 + u32 _u3;
3327 + u32 _u4;
3328 + u32 ethod;
3329 + u32 _u5;
3330 + u32 _u6;
3331 + u32 _u7;
3332 + u32 ethodeop;
3333 + u32 _u8[43];
3334 + u32 ethsal0;
3335 + u32 ethsah0;
3336 + u32 ethsal1;
3337 + u32 ethsah1;
3338 + u32 ethsal2;
3339 + u32 ethsah2;
3340 + u32 ethsal3;
3341 + u32 ethsah3;
3342 + u32 ethrbc;
3343 + u32 ethrpc;
3344 + u32 ethrupc;
3345 + u32 ethrfc;
3346 + u32 ethtbc;
3347 + u32 ethgpf;
3348 + u32 _u9[50];
3349 + u32 ethmac1;
3350 + u32 ethmac2;
3351 + u32 ethipgt;
3352 + u32 ethipgr;
3353 + u32 ethclrt;
3354 + u32 ethmaxf;
3355 + u32 _u10;
3356 + u32 ethmtest;
3357 + u32 miimcfg;
3358 + u32 miimcmd;
3359 + u32 miimaddr;
3360 + u32 miimwtd;
3361 + u32 miimrdd;
3362 + u32 miimind;
3363 + u32 _u11;
3364 + u32 _u12;
3365 + u32 ethcfsa0;
3366 + u32 ethcfsa1;
3367 + u32 ethcfsa2;
3368 +} rc32355_eth_regs_t;
3369 +
3370 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3371 +
3372 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3373 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3374 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3375 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3376 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3377 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3378 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3379 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3380 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3381 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3382 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3383 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3384 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3385 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3386 +
3387 +/* for n in { 0, 1, 2, 3 } */
3388 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3389 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3390 +
3391 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3392 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3393 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3394 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3395 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3396 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3397 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3398 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3399 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3400 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3401 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3402 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3403 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3404 +
3405 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3406 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3407 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3408 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3409 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3410 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3411 +
3412 +/* for n in { 0, 1, 2 } */
3413 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3414 +
3415 +
3416 +/*
3417 + * Register Interpretations follow
3418 + */
3419 +
3420 +/******************************************************************************
3421 + * ETHINTFC register
3422 + *****************************************************************************/
3423 +
3424 +#define ETHERINTFC_EN (1<<0)
3425 +#define ETHERINTFC_ITS (1<<1)
3426 +#define ETHERINTFC_RES (1<<2)
3427 +#define ETHERINTFC_RIP (1<<2)
3428 +#define ETHERINTFC_JAM (1<<3)
3429 +
3430 +/******************************************************************************
3431 + * ETHFIFOTT register
3432 + *****************************************************************************/
3433 +
3434 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3435 +
3436 +/******************************************************************************
3437 + * ETHARC register
3438 + *****************************************************************************/
3439 +
3440 +#define ETHERARC_PRO (1<<0)
3441 +#define ETHERARC_AM (1<<1)
3442 +#define ETHERARC_AFM (1<<2)
3443 +#define ETHERARC_AB (1<<3)
3444 +
3445 +/******************************************************************************
3446 + * ETHHASH registers
3447 + *****************************************************************************/
3448 +
3449 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3450 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3451 +
3452 +/******************************************************************************
3453 + * ETHSA registers
3454 + *****************************************************************************/
3455 +
3456 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3457 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3458 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3459 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3460 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3461 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3462 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3463 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3464 +
3465 +/******************************************************************************
3466 + * ETHFIFOST register
3467 + *****************************************************************************/
3468 +
3469 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3470 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3471 +
3472 +/******************************************************************************
3473 + * ETHFIFOS register
3474 + *****************************************************************************/
3475 +
3476 +#define ETHERFIFOS_IR (1<<0)
3477 +#define ETHERFIFOS_OR (1<<1)
3478 +#define ETHERFIFOS_OVR (1<<2)
3479 +#define ETHERFIFOS_UND (1<<3)
3480 +
3481 +/******************************************************************************
3482 + * DATA registers
3483 + *****************************************************************************/
3484 +
3485 +#define ETHERID(v) (((v)&0xffff)<<0)
3486 +#define ETHEROD(v) (((v)&0xffff)<<0)
3487 +
3488 +/******************************************************************************
3489 + * ETHODEOPS register
3490 + *****************************************************************************/
3491 +
3492 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3493 +
3494 +/******************************************************************************
3495 + * ETHODEOP register
3496 + *****************************************************************************/
3497 +
3498 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3499 +
3500 +/******************************************************************************
3501 + * ETHIS register
3502 + *****************************************************************************/
3503 +
3504 +#define ETHERIS_EOP (1<<0)
3505 +#define ETHERIS_ROK (1<<2)
3506 +#define ETHERIS_FM (1<<3)
3507 +#define ETHERIS_MP (1<<4)
3508 +#define ETHERIS_BP (1<<5)
3509 +#define ETHERIS_VLT (1<<6)
3510 +#define ETHERIS_CF (1<<7)
3511 +#define ETHERIS_OVR (1<<8)
3512 +#define ETHERIS_CRC (1<<9)
3513 +#define ETHERIS_CV (1<<10)
3514 +#define ETHERIS_DB (1<<11)
3515 +#define ETHERIS_LE (1<<12)
3516 +#define ETHERIS_LOR (1<<13)
3517 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3518 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3519 +
3520 +/******************************************************************************
3521 + * ETHOS register
3522 + *****************************************************************************/
3523 +
3524 +#define ETHEROS_T (1<<0)
3525 +#define ETHEROS_TOK (1<<6)
3526 +#define ETHEROS_MP (1<<7)
3527 +#define ETHEROS_BP (1<<8)
3528 +#define ETHEROS_UND (1<<9)
3529 +#define ETHEROS_OF (1<<10)
3530 +#define ETHEROS_ED (1<<11)
3531 +#define ETHEROS_EC (1<<12)
3532 +#define ETHEROS_LC (1<<13)
3533 +#define ETHEROS_TD (1<<14)
3534 +#define ETHEROS_CRC (1<<15)
3535 +#define ETHEROS_LE (1<<16)
3536 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3537 +#define ETHEROS_PFD (1<<21)
3538 +
3539 +/******************************************************************************
3540 + * Statistics registers
3541 + *****************************************************************************/
3542 +
3543 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3544 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3545 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3546 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3547 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3548 +
3549 +/******************************************************************************
3550 + * ETHGPF register
3551 + *****************************************************************************/
3552 +
3553 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3554 +
3555 +/******************************************************************************
3556 + * MAC registers
3557 + *****************************************************************************/
3558 +//ETHMAC1
3559 +#define ETHERMAC1_RE (1<<0)
3560 +#define ETHERMAC1_PAF (1<<1)
3561 +#define ETHERMAC1_RFC (1<<2)
3562 +#define ETHERMAC1_TFC (1<<3)
3563 +#define ETHERMAC1_LB (1<<4)
3564 +#define ETHERMAC1_MR (1<<15)
3565 +
3566 +//ETHMAC2
3567 +#define ETHERMAC2_FD (1<<0)
3568 +#define ETHERMAC2_FLC (1<<1)
3569 +#define ETHERMAC2_HFE (1<<2)
3570 +#define ETHERMAC2_DC (1<<3)
3571 +#define ETHERMAC2_CEN (1<<4)
3572 +#define ETHERMAC2_PE (1<<5)
3573 +#define ETHERMAC2_VPE (1<<6)
3574 +#define ETHERMAC2_APE (1<<7)
3575 +#define ETHERMAC2_PPE (1<<8)
3576 +#define ETHERMAC2_LPE (1<<9)
3577 +#define ETHERMAC2_NB (1<<12)
3578 +#define ETHERMAC2_BP (1<<13)
3579 +#define ETHERMAC2_ED (1<<14)
3580 +
3581 +//ETHIPGT
3582 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3583 +
3584 +//ETHIPGR
3585 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3586 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3587 +
3588 +//ETHCLRT
3589 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3590 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3591 +
3592 +//ETHMAXF
3593 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3594 +
3595 +//ETHMTEST
3596 +#define ETHERMTEST_TB (1<<2)
3597 +
3598 +//ETHMCP
3599 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3600 +
3601 +//MIIMCFG
3602 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3603 +#define ETHERMIIMCFG_R (1<<15)
3604 +
3605 +//MIIMCMD
3606 +#define ETHERMIIMCMD_RD (1<<0)
3607 +#define ETHERMIIMCMD_SCN (1<<1)
3608 +
3609 +//MIIMADDR
3610 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3611 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3612 +
3613 +//MIIMWTD
3614 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3615 +
3616 +//MIIMRDD
3617 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3618 +
3619 +//MIIMIND
3620 +#define ETHERMIIMIND_BSY (1<<0)
3621 +#define ETHERMIIMIND_SCN (1<<1)
3622 +#define ETHERMIIMIND_NV (1<<2)
3623 +
3624 +//DMA DEVCS IN
3625 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3626 +#define ETHERDMA_IN_CES (1<<14)
3627 +#define ETHERDMA_IN_LOR (1<<13)
3628 +#define ETHERDMA_IN_LE (1<<12)
3629 +#define ETHERDMA_IN_DB (1<<11)
3630 +#define ETHERDMA_IN_CV (1<<10)
3631 +#define ETHERDMA_IN_CRC (1<<9)
3632 +#define ETHERDMA_IN_OVR (1<<8)
3633 +#define ETHERDMA_IN_CF (1<<7)
3634 +#define ETHERDMA_IN_VLT (1<<6)
3635 +#define ETHERDMA_IN_BP (1<<5)
3636 +#define ETHERDMA_IN_MP (1<<4)
3637 +#define ETHERDMA_IN_FM (1<<3)
3638 +#define ETHERDMA_IN_ROK (1<<2)
3639 +#define ETHERDMA_IN_LD (1<<1)
3640 +#define ETHERDMA_IN_FD (1<<0)
3641 +
3642 +//DMA DEVCS OUT
3643 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3644 +#define ETHERDMA_OUT_CNT 0x001e0000
3645 +#define ETHERDMA_OUT_SHFT 17
3646 +#define ETHERDMA_OUT_LE (1<<16)
3647 +
3648 +#define ETHERDMA_OUT_CRC (1<<15)
3649 +#define ETHERDMA_OUT_TD (1<<14)
3650 +#define ETHERDMA_OUT_LC (1<<13)
3651 +#define ETHERDMA_OUT_EC (1<<12)
3652 +#define ETHERDMA_OUT_ED (1<<11)
3653 +#define ETHERDMA_OUT_OF (1<<10)
3654 +#define ETHERDMA_OUT_UND (1<<9)
3655 +#define ETHERDMA_OUT_BP (1<<8)
3656 +#define ETHERDMA_OUT_MP (1<<7)
3657 +#define ETHERDMA_OUT_TOK (1<<6)
3658 +#define ETHERDMA_OUT_HEN (1<<5)
3659 +#define ETHERDMA_OUT_CEN (1<<4)
3660 +#define ETHERDMA_OUT_PEN (1<<3)
3661 +#define ETHERDMA_OUT_OEN (1<<2)
3662 +#define ETHERDMA_OUT_LD (1<<1)
3663 +#define ETHERDMA_OUT_FD (1<<0)
3664 +
3665 +#define RCV_ERRS \
3666 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3667 +#define TX_ERRS \
3668 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3669 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3670 +
3671 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
3672 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
3673 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
3674 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
3675 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
3676 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
3677 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
3678 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
3679 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
3680 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
3681 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
3682 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
3683 + Range */
3684 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
3685 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
3686 + received packet */
3687 +
3688 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
3689 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
3690 +
3691 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
3692 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
3693 + Underflow */
3694 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
3695 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
3696 + deferral */
3697 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
3698 + collisions */
3699 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
3700 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
3701 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
3702 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
3703 +
3704 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
3705 +
3706 +#endif /* RC32355_ETHER_H */
3707 +
3708 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3709 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
3710 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-03-20 14:25:10.000000000 +0100
3711 @@ -0,0 +1,177 @@
3712 +/**************************************************************************
3713 + *
3714 + * BRIEF MODULE DESCRIPTION
3715 + * Definitions for IDT RC32355 CPU.
3716 + *
3717 + * Copyright 2004 IDT Inc.
3718 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3719 + *
3720 + *
3721 + * This program is free software; you can redistribute it and/or modify it
3722 + * under the terms of the GNU General Public License as published by the
3723 + * Free Software Foundation; either version 2 of the License, or (at your
3724 + * option) any later version.
3725 + *
3726 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3727 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3728 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3729 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3730 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3731 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3732 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3733 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3734 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3735 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3736 + *
3737 + * You should have received a copy of the GNU General Public License along
3738 + * with this program; if not, write to the Free Software Foundation, Inc.,
3739 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3740 + *
3741 + *
3742 + * May 2004 rkt
3743 + * Initial Release
3744 + *
3745 + **************************************************************************
3746 + */
3747 +
3748 +
3749 +#ifndef _RC32355_H_
3750 +#define _RC32355_H_
3751 +
3752 +#include <linux/delay.h>
3753 +#include <asm/io.h>
3754 +
3755 +/* Base address of internal registers */
3756 +#define RC32355_REG_BASE 0x18000000
3757 +
3758 +/* System ID Registers */
3759 +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
3760 +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
3761 +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
3762 +
3763 +/* Reset Controller */
3764 +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
3765 +
3766 +/* Device Controller */
3767 +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
3768 +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
3769 +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
3770 +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
3771 +#define DEV_REG_OFFSET 0x10
3772 +
3773 +/* SDRAM Controller */
3774 +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
3775 +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
3776 +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
3777 +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
3778 +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
3779 +
3780 +/* Bus Arbiter */
3781 +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
3782 +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
3783 +
3784 +/* Counters/Timers */
3785 +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
3786 +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
3787 +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
3788 +#define TIMER_REG_OFFSET 0x0C
3789 +
3790 +/* System Integrity */
3791 +
3792 +/* Interrupt Controller */
3793 +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
3794 +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
3795 +#define IC_GROUP_OFFSET 0x08
3796 +
3797 +#define NUM_INTR_GROUPS 5
3798 +/*
3799 + * The IRQ mapping is as follows:
3800 + *
3801 + * IRQ Mapped To
3802 + * --- -------------------
3803 + * 0 SW0 (IP0) SW0 intr
3804 + * 1 SW1 (IP1) SW1 intr
3805 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
3806 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
3807 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
3808 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
3809 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
3810 + * 7 Int5 (IP7) CP0 Timer
3811 + *
3812 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3813 + * internally on the RC32355 is routed to the Expansion
3814 + * Interrupt Controller.
3815 + */
3816 +#define MIPS_CPU_TIMER_IRQ 7
3817 +
3818 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
3819 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
3820 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
3821 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3822 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
3823 +
3824 +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
3825 +
3826 +/* DMA - see rc32355_dma.h for full list of registers */
3827 +
3828 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3829 +#define DMA_CHAN_OFFSET 0x14
3830 +
3831 +/* GPIO Controller */
3832 +
3833 +/* TDM Bus */
3834 +
3835 +/* 16550 UARTs */
3836 +#ifdef __MIPSEB__
3837 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3838 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3839 +#else
3840 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3841 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3842 +#endif
3843 +
3844 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
3845 +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
3846 +
3847 +/* ATM */
3848 +
3849 +/* Ethernet - see rc32355_eth.h for full list of registers */
3850 +
3851 +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
3852 +
3853 +
3854 +#define IDT_CLOCK_MULT 2
3855 +
3856 +/* Memory map of 79EB355 board */
3857 +
3858 +/* DRAM */
3859 +#define RAM_BASE 0x00000000
3860 +#define RAM_SIZE (32*1024*1024)
3861 +
3862 +/* SRAM (device 1) */
3863 +#define SRAM_BASE 0x02000000
3864 +#define SRAM_SIZE 0x00100000
3865 +
3866 +/* FLASH (device 2) */
3867 +#define FLASH_BASE 0x0C000000
3868 +#define FLASH_SIZE 0x00C00000
3869 +
3870 +/* ATM PHY (device 4) */
3871 +#define ATM_PHY_BASE 0x14000000
3872 +
3873 +/* TDM switch (device 3) */
3874 +#define TDM_BASE 0x1A000000
3875 +
3876 +/* LCD panel (device 3) */
3877 +#define LCD_BASE 0x1A002000
3878 +
3879 +/* RTC (DS1511W) (device 3) */
3880 +#define RTC_BASE 0x1A004000
3881 +
3882 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3883 +#define NVRAM_ADDR RTC_BASE + 0x10
3884 +#define NVRAM_DATA RTC_BASE + 0x13
3885 +#define NVRAM_ENVSIZE_OFF 4
3886 +#define NVRAM_ENVSTART_OFF 32
3887 +
3888 +#endif /* _RC32355_H_ */
3889 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3890 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
3891 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-03-20 14:25:10.000000000 +0100
3892 @@ -0,0 +1,226 @@
3893 +/**************************************************************************
3894 + *
3895 + * BRIEF MODULE DESCRIPTION
3896 + * RC32365/336 DMA hardware abstraction.
3897 + *
3898 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3899 + *
3900 + * This program is free software; you can redistribute it and/or modify it
3901 + * under the terms of the GNU General Public License as published by the
3902 + * Free Software Foundation; either version 2 of the License, or (at your
3903 + * option) any later version.
3904 + *
3905 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3906 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3907 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3908 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3909 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3910 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3911 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3912 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3913 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3914 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3915 + *
3916 + * You should have received a copy of the GNU General Public License along
3917 + * with this program; if not, write to the Free Software Foundation, Inc.,
3918 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3919 + *
3920 + *
3921 + **************************************************************************
3922 + * May 2004 P. Sadik.
3923 + *
3924 + * Initial Release
3925 + *
3926 + *
3927 + *
3928 + **************************************************************************
3929 + */
3930 +
3931 +#ifndef __IDT_RC32365_DMA_H__
3932 +#define __IDT_RC32365_DMA_H__
3933 +
3934 +enum
3935 +{
3936 + DMA0_PhysicalAddress = 0x18038000,
3937 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
3938 +
3939 + DMA0_VirtualAddress = 0xb8038000,
3940 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
3941 +} ;
3942 +
3943 +/*
3944 + * DMA descriptor (in physical memory).
3945 + */
3946 +
3947 +typedef struct DMAD_s
3948 +{
3949 + u32 control ; // Control. use DMAD_*
3950 + u32 ca ; // Current Address.
3951 + u32 devcs ; // Device control and status.
3952 + u32 link ; // Next descriptor in chain.
3953 +} volatile *DMAD_t ;
3954 +
3955 +enum
3956 +{
3957 + DMAD_size = sizeof (struct DMAD_s),
3958 + DMAD_count_b = 0, // in DMAD_t -> control
3959 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
3960 + DMAD_ds_b = 20, // in DMAD_t -> control
3961 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
3962 + DMAD_ds_extToMem0_v = 0,
3963 + DMAD_ds_memToExt0_v = 1,
3964 + DMAD_ds_extToMem1_v = 0,
3965 + DMAD_ds_memToExt1_v = 1,
3966 + DMAD_ds_ethRcv0_v = 0,
3967 + DMAD_ds_ethXmt0_v = 0,
3968 + DMAD_ds_ethRcv1_v = 0,
3969 + DMAD_ds_ethXmt2_v = 0,
3970 + DMAD_ds_memToFifo_v = 0,
3971 + DMAD_ds_fifoToMem_v = 0,
3972 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
3973 + DMAD_ds_pciToMem_v = 0,
3974 + DMAD_ds_memToPci_v = 0,
3975 + DMAD_ds_securityInput_v = 0,
3976 + DMAD_ds_securityOutput_v = 0,
3977 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
3978 +
3979 + DMAD_devcmd_b = 22, // in DMAD_t -> control
3980 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
3981 + DMAD_devcmd_byte_v = 0, //memory-to-memory
3982 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
3983 + DMAD_devcmd_word_v = 2, //memory-to-memory
3984 + DMAD_devcmd_2words_v = 3, //memory-to-memory
3985 + DMAD_devcmd_4words_v = 4, //memory-to-memory
3986 + DMAD_devcmd_6words_v = 5, //memory-to-memory
3987 + DMAD_devcmd_8words_v = 6, //memory-to-memory
3988 + DMAD_devcmd_16words_v = 7, //memory-to-memory
3989 + DMAD_cof_b = 25, // chain on finished
3990 + DMAD_cof_m = 0x02000000, //
3991 + DMAD_cod_b = 26, // chain on done
3992 + DMAD_cod_m = 0x04000000, //
3993 + DMAD_iof_b = 27, // interrupt on finished
3994 + DMAD_iof_m = 0x08000000, //
3995 + DMAD_iod_b = 28, // interrupt on done
3996 + DMAD_iod_m = 0x10000000, //
3997 + DMAD_t_b = 29, // terminated
3998 + DMAD_t_m = 0x20000000, //
3999 + DMAD_d_b = 30, // done
4000 + DMAD_d_m = 0x40000000, //
4001 + DMAD_f_b = 31, // finished
4002 + DMAD_f_m = 0x80000000, //
4003 +} ;
4004 +
4005 +/*
4006 + * DMA register (within Internal Register Map).
4007 + */
4008 +
4009 +struct DMA_Chan_s
4010 +{
4011 + u32 dmac ; // Control.
4012 + u32 dmas ; // Status.
4013 + u32 dmasm ; // Mask.
4014 + u32 dmadptr ; // Descriptor pointer.
4015 + u32 dmandptr ; // Next descriptor pointer.
4016 +};
4017 +
4018 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4019 +
4020 +//DMA_Channels use DMACH_count instead
4021 +
4022 +enum
4023 +{
4024 + DMAC_run_b = 0, //
4025 + DMAC_run_m = 0x00000001, //
4026 + DMAC_dm_b = 1, // done mask
4027 + DMAC_dm_m = 0x00000002, //
4028 + DMAC_mode_b = 2, //
4029 + DMAC_mode_m = 0x0000000c, //
4030 + DMAC_mode_auto_v = 0,
4031 + DMAC_mode_burst_v = 1,
4032 + DMAC_mode_transfer_v = 2, //usually used
4033 + DMAC_mode_reserved_v = 3,
4034 + DMAC_a_b = 4, //
4035 + DMAC_a_m = 0x00000010, //
4036 +
4037 + DMAS_f_b = 0, // finished (sticky)
4038 + DMAS_f_m = 0x00000001, //
4039 + DMAS_d_b = 1, // done (sticky)
4040 + DMAS_d_m = 0x00000002, //
4041 + DMAS_c_b = 2, // chain (sticky)
4042 + DMAS_c_m = 0x00000004, //
4043 + DMAS_e_b = 3, // error (sticky)
4044 + DMAS_e_m = 0x00000008, //
4045 + DMAS_h_b = 4, // halt (sticky)
4046 + DMAS_h_m = 0x00000010, //
4047 +
4048 + DMASM_f_b = 0, // finished (1=mask)
4049 + DMASM_f_m = 0x00000001, //
4050 + DMASM_d_b = 1, // done (1=mask)
4051 + DMASM_d_m = 0x00000002, //
4052 + DMASM_c_b = 2, // chain (1=mask)
4053 + DMASM_c_m = 0x00000004, //
4054 + DMASM_e_b = 3, // error (1=mask)
4055 + DMASM_e_m = 0x00000008, //
4056 + DMASM_h_b = 4, // halt (1=mask)
4057 + DMASM_h_m = 0x00000010, //
4058 +} ;
4059 +
4060 +/*
4061 + * DMA channel definitions
4062 + */
4063 +
4064 +enum
4065 +{
4066 + DMACH_ethRcv0 = 0,
4067 + DMACH_ethXmt0 = 1,
4068 + DMACH_ethRcv1 = 2,
4069 + DMACH_ethXmt2 = 3,
4070 + DMACH_pciToMem = 4,
4071 + DMACH_memToPci = 5,
4072 + DMACH_securityInput = 6,
4073 + DMACH_securityOutput = 7,
4074 + DMACH_rng = 8,
4075 +
4076 + DMACH_count //must be last
4077 +};
4078 +
4079 +
4080 +typedef struct DMAC_s
4081 +{
4082 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4083 +} volatile *DMA_t ;
4084 +
4085 +
4086 +/*
4087 + * External DMA parameters
4088 +*/
4089 +
4090 +enum
4091 +{
4092 + DMADEVCMD_ts_b = 0, // ts field in devcmd
4093 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
4094 + DMADEVCMD_ts_byte_v = 0,
4095 + DMADEVCMD_ts_halfword_v = 1,
4096 + DMADEVCMD_ts_word_v = 2,
4097 + DMADEVCMD_ts_2word_v = 3,
4098 + DMADEVCMD_ts_4word_v = 4,
4099 + DMADEVCMD_ts_6word_v = 5,
4100 + DMADEVCMD_ts_8word_v = 6,
4101 + DMADEVCMD_ts_16word_v = 7
4102 +};
4103 +
4104 +
4105 +#if 1 // aws - Compatibility.
4106 +# define EXTDMA_ts_b DMADEVCMD_ts_b
4107 +# define EXTDMA_ts_m DMADEVCMD_ts_m
4108 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
4109 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
4110 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
4111 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
4112 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
4113 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
4114 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
4115 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
4116 +#endif // aws - Compatibility.
4117 +
4118 +#endif // __IDT_RC32365_DMA_H__
4119 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4120 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
4121 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-03-20 14:25:10.000000000 +0100
4122 @@ -0,0 +1,86 @@
4123 +/**************************************************************************
4124 + *
4125 + * BRIEF MODULE DESCRIPTION
4126 + * RC32365/336 DMA interface routines.
4127 + *
4128 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4129 + *
4130 + * This program is free software; you can redistribute it and/or modify it
4131 + * under the terms of the GNU General Public License as published by the
4132 + * Free Software Foundation; either version 2 of the License, or (at your
4133 + * option) any later version.
4134 + *
4135 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4136 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4137 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4138 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4139 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4140 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4141 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4142 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4143 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4144 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4145 + *
4146 + * You should have received a copy of the GNU General Public License along
4147 + * with this program; if not, write to the Free Software Foundation, Inc.,
4148 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4149 + *
4150 + *
4151 + **************************************************************************
4152 + * May 2004 P. Sadik.
4153 + *
4154 + * Initial Release
4155 + *
4156 + *
4157 + *
4158 + **************************************************************************
4159 + */
4160 +
4161 +#ifndef __IDT_RC32365_DMA_V_H__
4162 +#define __IDT_RC32365_DMA_V_H__
4163 +
4164 +
4165 +#include <asm/idt-boards/rc32300/rc32300.h>
4166 +#include <asm/idt-boards/rc32300/rc32365_dma.h>
4167 +#include <asm/idt-boards/rc32300/rc32365.h>
4168 +
4169 +#define DMA_CHAN_OFFSET 0x14
4170 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4171 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
4172 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
4173 +
4174 +#define DMA_COUNT(count) \
4175 + ((count) & DMAD_count_m)
4176 +
4177 +#define DMA_HALT_TIMEOUT 500
4178 +
4179 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4180 +{
4181 + int timeout=1;
4182 + if (local_readl(&ch->dmac) & DMAC_run_m) {
4183 + local_writel(0, &ch->dmac);
4184 +
4185 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4186 + if (local_readl(&ch->dmas) & DMAS_h_m) {
4187 + local_writel(0, &ch->dmas);
4188 + break;
4189 + }
4190 + }
4191 +
4192 + }
4193 +
4194 + return timeout ? 0 : 1;
4195 +}
4196 +
4197 +
4198 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4199 +{
4200 + local_writel(0, &ch->dmandptr);
4201 + local_writel(dma_addr, &ch->dmadptr);
4202 +}
4203 +
4204 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4205 +{
4206 + local_writel(dma_addr, &ch->dmandptr);
4207 +}
4208 +#endif //__IDT_RC32365_DMA_V_H__
4209 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4210 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1970-01-01 01:00:00.000000000 +0100
4211 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-03-20 14:25:10.000000000 +0100
4212 @@ -0,0 +1,344 @@
4213 +/**************************************************************************
4214 + *
4215 + * BRIEF MODULE DESCRIPTION
4216 + * RC32365/336 Ethernet hardware abstraction.
4217 + *
4218 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4219 + *
4220 + * This program is free software; you can redistribute it and/or modify it
4221 + * under the terms of the GNU General Public License as published by the
4222 + * Free Software Foundation; either version 2 of the License, or (at your
4223 + * option) any later version.
4224 + *
4225 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4226 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4227 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4228 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4229 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4230 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4231 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4232 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4233 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4234 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4235 + *
4236 + * You should have received a copy of the GNU General Public License along
4237 + * with this program; if not, write to the Free Software Foundation, Inc.,
4238 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4239 + *
4240 + *
4241 + **************************************************************************
4242 + * May 2004 P. Sadik.
4243 + *
4244 + * Initial Release
4245 + *
4246 + *
4247 + *
4248 + **************************************************************************
4249 + */
4250 +
4251 +#ifndef __IDT_RC32365_ETH_H__
4252 +#define __IDT_RC32365_ETH_H__
4253 +
4254 +enum
4255 +{
4256 + ETH0_PhysicalAddress = 0x18058000,
4257 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
4258 + ETH0_VirtualAddress = 0xb8058000,
4259 +
4260 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
4261 +
4262 + ETH1_PhysicalAddress = 0x18060000,
4263 + ETH1_VirtualAddress = 0xb8060000, // Default
4264 +} ;
4265 +
4266 +typedef struct
4267 +{
4268 + u32 ethintfc ;
4269 + u32 ethfifott ;
4270 + u32 etharc ;
4271 + u32 ethhash0 ;
4272 + u32 ethhash1 ;
4273 + u32 ethu0 [4] ; // Reserved.
4274 + u32 ethpfs ;
4275 + u32 ethmcp ;
4276 + u32 eth_u1 [10] ; // Reserved.
4277 + u32 ethspare ;
4278 + u32 eth_u2 [42] ; // Reserved.
4279 + u32 ethsal0 ;
4280 + u32 ethsah0 ;
4281 + u32 ethsal1 ;
4282 + u32 ethsah1 ;
4283 + u32 ethsal2 ;
4284 + u32 ethsah2 ;
4285 + u32 ethsal3 ;
4286 + u32 ethsah3 ;
4287 + u32 ethrbc ;
4288 + u32 ethrpc ;
4289 + u32 ethrupc ;
4290 + u32 ethrfc ;
4291 + u32 ethtbc ;
4292 + u32 ethgpf ;
4293 + u32 eth_u9 [50] ; // Reserved.
4294 + u32 ethmac1 ;
4295 + u32 ethmac2 ;
4296 + u32 ethipgt ;
4297 + u32 ethipgr ;
4298 + u32 ethclrt ;
4299 + u32 ethmaxf ;
4300 + u32 eth_u10 ; // Reserved.
4301 + u32 ethmtest ;
4302 + u32 miimcfg ;
4303 + u32 miimcmd ;
4304 + u32 miimaddr ;
4305 + u32 miimwtd ;
4306 + u32 miimrdd ;
4307 + u32 miimind ;
4308 + u32 eth_u11 ; // Reserved.
4309 + u32 eth_u12 ; // Reserved.
4310 + u32 ethcfsa0 ;
4311 + u32 ethcfsa1 ;
4312 + u32 ethcfsa2 ;
4313 +} volatile *ETH_t;
4314 +
4315 +enum
4316 +{
4317 + ETHINTFC_en_b = 0,
4318 + ETHINTFC_en_m = 0x00000001,
4319 + ETHINTFC_its_b = 1,
4320 + ETHINTFC_its_m = 0x00000002,
4321 + ETHINTFC_rip_b = 2,
4322 + ETHINTFC_rip_m = 0x00000004,
4323 + ETHINTFC_jam_b = 3,
4324 + ETHINTFC_jam_m = 0x00000008,
4325 + ETHINTFC_ovr_b = 4,
4326 + ETHINTFC_ovr_m = 0x00000010,
4327 + ETHINTFC_und_b = 5,
4328 + ETHINTFC_und_m = 0x00000020,
4329 +
4330 + ETHFIFOTT_tth_b = 0,
4331 + ETHFIFOTT_tth_m = 0x0000007f,
4332 +
4333 + ETHARC_pro_b = 0,
4334 + ETHARC_pro_m = 0x00000001,
4335 + ETHARC_am_b = 1,
4336 + ETHARC_am_m = 0x00000002,
4337 + ETHARC_afm_b = 2,
4338 + ETHARC_afm_m = 0x00000004,
4339 + ETHARC_ab_b = 3,
4340 + ETHARC_ab_m = 0x00000008,
4341 +
4342 + ETHSAL_byte5_b = 0,
4343 + ETHSAL_byte5_m = 0x000000ff,
4344 + ETHSAL_byte4_b = 8,
4345 + ETHSAL_byte4_m = 0x0000ff00,
4346 + ETHSAL_byte3_b = 16,
4347 + ETHSAL_byte3_m = 0x00ff0000,
4348 + ETHSAL_byte2_b = 24,
4349 + ETHSAL_byte2_m = 0xff000000,
4350 +
4351 + ETHSAH_byte1_b = 0,
4352 + ETHSAH_byte1_m = 0x000000ff,
4353 + ETHSAH_byte0_b = 8,
4354 + ETHSAH_byte0_m = 0x0000ff00,
4355 +
4356 + ETHGPF_ptv_b = 0,
4357 + ETHGPF_ptv_m = 0x0000ffff,
4358 +
4359 + ETHPFS_pfd_b = 0,
4360 + ETHPFS_pfd_m = 0x00000001,
4361 +
4362 + ETHCFSA0_cfsa4_b = 0,
4363 + ETHCFSA0_cfsa4_m = 0x000000ff,
4364 + ETHCFSA0_cfsa5_b = 8,
4365 + ETHCFSA0_cfsa5_m = 0x0000ff00,
4366 +
4367 + ETHCFSA1_cfsa2_b = 0,
4368 + ETHCFSA1_cfsa2_m = 0x000000ff,
4369 + ETHCFSA1_cfsa3_b = 8,
4370 + ETHCFSA1_cfsa3_m = 0x0000ff00,
4371 +
4372 + ETHCFSA2_cfsa0_b = 0,
4373 + ETHCFSA2_cfsa0_m = 0x000000ff,
4374 + ETHCFSA2_cfsa1_b = 8,
4375 + ETHCFSA2_cfsa1_m = 0x0000ff00,
4376 +
4377 + ETHMAC1_re_b = 0,
4378 + ETHMAC1_re_m = 0x00000001,
4379 + ETHMAC1_paf_b = 1,
4380 + ETHMAC1_paf_m = 0x00000002,
4381 + ETHMAC1_rfc_b = 2,
4382 + ETHMAC1_rfc_m = 0x00000004,
4383 + ETHMAC1_tfc_b = 3,
4384 + ETHMAC1_tfc_m = 0x00000008,
4385 + ETHMAC1_lb_b = 4,
4386 + ETHMAC1_lb_m = 0x00000010,
4387 + ETHMAC1_mr_b = 31,
4388 + ETHMAC1_mr_m = 0x80000000,
4389 +
4390 + ETHMAC2_fd_b = 0,
4391 + ETHMAC2_fd_m = 0x00000001,
4392 + ETHMAC2_flc_b = 1,
4393 + ETHMAC2_flc_m = 0x00000002,
4394 + ETHMAC2_hfe_b = 2,
4395 + ETHMAC2_hfe_m = 0x00000004,
4396 + ETHMAC2_dc_b = 3,
4397 + ETHMAC2_dc_m = 0x00000008,
4398 + ETHMAC2_cen_b = 4,
4399 + ETHMAC2_cen_m = 0x00000010,
4400 + ETHMAC2_pe_b = 5,
4401 + ETHMAC2_pe_m = 0x00000020,
4402 + ETHMAC2_vpe_b = 6,
4403 + ETHMAC2_vpe_m = 0x00000040,
4404 + ETHMAC2_ape_b = 7,
4405 + ETHMAC2_ape_m = 0x00000080,
4406 + ETHMAC2_ppe_b = 8,
4407 + ETHMAC2_ppe_m = 0x00000100,
4408 + ETHMAC2_lpe_b = 9,
4409 + ETHMAC2_lpe_m = 0x00000200,
4410 + ETHMAC2_nb_b = 12,
4411 + ETHMAC2_nb_m = 0x00001000,
4412 + ETHMAC2_bp_b = 13,
4413 + ETHMAC2_bp_m = 0x00002000,
4414 + ETHMAC2_ed_b = 14,
4415 + ETHMAC2_ed_m = 0x00004000,
4416 +
4417 + ETHIPGT_ipgt_b = 0,
4418 + ETHIPGT_ipgt_m = 0x0000007f,
4419 +
4420 + ETHIPGR_ipgr2_b = 0,
4421 + ETHIPGR_ipgr2_m = 0x0000007f,
4422 + ETHIPGR_ipgr1_b = 8,
4423 + ETHIPGR_ipgr1_m = 0x00007f00,
4424 +
4425 + ETHCLRT_maxret_b = 0,
4426 + ETHCLRT_maxret_m = 0x0000000f,
4427 + ETHCLRT_colwin_b = 8,
4428 + ETHCLRT_colwin_m = 0x00003f00,
4429 +
4430 + ETHMAXF_maxf_b = 0,
4431 + ETHMAXF_maxf_m = 0x0000ffff,
4432 +
4433 + ETHMTEST_tb_b = 2,
4434 + ETHMTEST_tb_m = 0x00000004,
4435 +
4436 + ETHMCP_div_b = 0,
4437 + ETHMCP_div_m = 0x000000ff,
4438 +
4439 + MIIMCFG_rsv_b = 0,
4440 + MIIMCFG_rsv_m = 0x0000000c,
4441 +
4442 + MIIMCMD_rd_b = 0,
4443 + MIIMCMD_rd_m = 0x00000001,
4444 + MIIMCMD_scn_b = 1,
4445 + MIIMCMD_scn_m = 0x00000002,
4446 +
4447 + MIIMADDR_regaddr_b = 0,
4448 + MIIMADDR_regaddr_m = 0x0000001f,
4449 + MIIMADDR_phyaddr_b = 8,
4450 + MIIMADDR_phyaddr_m = 0x00001f00,
4451 +
4452 + MIIMWTD_wdata_b = 0,
4453 + MIIMWTD_wdata_m = 0x0000ffff,
4454 +
4455 + MIIMRDD_rdata_b = 0,
4456 + MIIMRDD_rdata_m = 0x0000ffff,
4457 +
4458 + MIIMIND_bsy_b = 0,
4459 + MIIMIND_bsy_m = 0x00000001,
4460 + MIIMIND_scn_b = 1,
4461 + MIIMIND_scn_m = 0x00000002,
4462 + MIIMIND_nv_b = 2,
4463 + MIIMIND_nv_m = 0x00000004,
4464 +
4465 +} ;
4466 +
4467 +/*
4468 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4469 + */
4470 +enum
4471 +{
4472 + ETHRX_fd_b = 0,
4473 + ETHRX_fd_m = 0x00000001,
4474 + ETHRX_ld_b = 1,
4475 + ETHRX_ld_m = 0x00000002,
4476 + ETHRX_rok_b = 2,
4477 + ETHRX_rok_m = 0x00000004,
4478 + ETHRX_fm_b = 3,
4479 + ETHRX_fm_m = 0x00000008,
4480 + ETHRX_mp_b = 4,
4481 + ETHRX_mp_m = 0x00000010,
4482 + ETHRX_bp_b = 5,
4483 + ETHRX_bp_m = 0x00000020,
4484 + ETHRX_vlt_b = 6,
4485 + ETHRX_vlt_m = 0x00000040,
4486 + ETHRX_cf_b = 7,
4487 + ETHRX_cf_m = 0x00000080,
4488 + ETHRX_ovr_b = 8,
4489 + ETHRX_ovr_m = 0x00000100,
4490 + ETHRX_crc_b = 9,
4491 + ETHRX_crc_m = 0x00000200,
4492 + ETHRX_cv_b = 10,
4493 + ETHRX_cv_m = 0x00000400,
4494 + ETHRX_db_b = 11,
4495 + ETHRX_db_m = 0x00000800,
4496 + ETHRX_le_b = 12,
4497 + ETHRX_le_m = 0x00001000,
4498 + ETHRX_lor_b = 13,
4499 + ETHRX_lor_m = 0x00002000,
4500 + ETHRX_ces_b = 14,
4501 + ETHRX_ces_m = 0x00004000,
4502 + ETHRX_length_b = 16,
4503 + ETHRX_length_m = 0xffff0000,
4504 +
4505 + ETHTX_fd_b = 0,
4506 + ETHTX_fd_m = 0x00000001,
4507 + ETHTX_ld_b = 1,
4508 + ETHTX_ld_m = 0x00000002,
4509 + ETHTX_oen_b = 2,
4510 + ETHTX_oen_m = 0x00000004,
4511 + ETHTX_pen_b = 3,
4512 + ETHTX_pen_m = 0x00000008,
4513 + ETHTX_cen_b = 4,
4514 + ETHTX_cen_m = 0x00000010,
4515 + ETHTX_hen_b = 5,
4516 + ETHTX_hen_m = 0x00000020,
4517 + ETHTX_tok_b = 6,
4518 + ETHTX_tok_m = 0x00000040,
4519 + ETHTX_mp_b = 7,
4520 + ETHTX_mp_m = 0x00000080,
4521 + ETHTX_bp_b = 8,
4522 + ETHTX_bp_m = 0x00000100,
4523 + ETHTX_und_b = 9,
4524 + ETHTX_und_m = 0x00000200,
4525 + ETHTX_of_b = 10,
4526 + ETHTX_of_m = 0x00000400,
4527 + ETHTX_ed_b = 11,
4528 + ETHTX_ed_m = 0x00000800,
4529 + ETHTX_ec_b = 12,
4530 + ETHTX_ec_m = 0x00001000,
4531 + ETHTX_lc_b = 13,
4532 + ETHTX_lc_m = 0x00002000,
4533 + ETHTX_td_b = 14,
4534 + ETHTX_td_m = 0x00004000,
4535 + ETHTX_crc_b = 15,
4536 + ETHTX_crc_m = 0x00008000,
4537 + ETHTX_le_b = 16,
4538 + ETHTX_le_m = 0x00010000,
4539 + ETHTX_cc_b = 17,
4540 + ETHTX_cc_m = 0x001E0000,
4541 +} ;
4542 +
4543 +enum
4544 +{
4545 + ETH0_IPABMC_PhysicalAddress = 0x18040010,
4546 + ETH0_IPABMC_VirtualAddress = 0xb8040000,
4547 + ETH1_IPABMC_PhysicalAddress = 0x18040018,
4548 + ETH1_IPABMC_VirtualAddress = 0xb8040018,
4549 +} ;
4550 +
4551 +typedef struct
4552 +{
4553 + u32 ipabmcrx ;
4554 + u32 ipabmctx ;
4555 +}volatile *IPABM_ETH_t;
4556 +#endif //__IDT_RC32365_ETH_H__
4557 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4558 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 1970-01-01 01:00:00.000000000 +0100
4559 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 2006-03-20 14:25:10.000000000 +0100
4560 @@ -0,0 +1,72 @@
4561 +/**************************************************************************
4562 + *
4563 + * BRIEF MODULE DESCRIPTION
4564 + * RC32365/336 Ethernet status checking.
4565 + *
4566 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4567 + *
4568 + * This program is free software; you can redistribute it and/or modify it
4569 + * under the terms of the GNU General Public License as published by the
4570 + * Free Software Foundation; either version 2 of the License, or (at your
4571 + * option) any later version.
4572 + *
4573 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4574 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4575 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4576 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4577 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4578 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4579 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4580 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4581 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4582 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4583 + *
4584 + * You should have received a copy of the GNU General Public License along
4585 + * with this program; if not, write to the Free Software Foundation, Inc.,
4586 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4587 + *
4588 + *
4589 + **************************************************************************
4590 + * May 2004 P. Sadik.
4591 + *
4592 + * Initial Release
4593 + *
4594 + *
4595 + *
4596 + **************************************************************************
4597 + */
4598 +
4599 +#ifndef __IDT_RC32365_ETH_V_H__
4600 +#define __IDT_RC32365_ETH_V_H__
4601 +#include <asm/idt-boards/rc32300/rc32365_eth.h>
4602 +
4603 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
4604 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
4605 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
4606 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
4607 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
4608 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
4609 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
4610 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
4611 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
4612 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
4613 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
4614 +
4615 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
4616 +
4617 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
4618 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
4619 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
4620 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
4621 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
4622 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
4623 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
4624 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
4625 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
4626 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
4627 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
4628 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
4629 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
4630 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
4631 +
4632 +#endif //__IDT_RC32365_ETH_V_H__
4633 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4634 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 1970-01-01 01:00:00.000000000 +0100
4635 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 2006-03-20 14:25:10.000000000 +0100
4636 @@ -0,0 +1,181 @@
4637 +/**************************************************************************
4638 + *
4639 + * BRIEF MODULE DESCRIPTION
4640 + * RC32365/336 GPIO hardware abstraction.
4641 + *
4642 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4643 + *
4644 + * This program is free software; you can redistribute it and/or modify it
4645 + * under the terms of the GNU General Public License as published by the
4646 + * Free Software Foundation; either version 2 of the License, or (at your
4647 + * option) any later version.
4648 + *
4649 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4650 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4651 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4652 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4653 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4654 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4655 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4656 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4657 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4658 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4659 + *
4660 + * You should have received a copy of the GNU General Public License along
4661 + * with this program; if not, write to the Free Software Foundation, Inc.,
4662 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4663 + *
4664 + *
4665 + **************************************************************************
4666 + * May 2004 P. Sadik.
4667 + *
4668 + * Initial Release
4669 + *
4670 + *
4671 + *
4672 + **************************************************************************
4673 + */
4674 +
4675 +#ifndef __IDT_RC32365_GPIO_H__
4676 +#define __IDT_RC32365_GPIO_H__
4677 +
4678 +enum
4679 +{
4680 + GPIO0_PhysicalAddress = 0x18048000,
4681 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
4682 +
4683 + GPIO0_VirtualAddress = 0xb8048000,
4684 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
4685 +} ;
4686 +
4687 +typedef struct
4688 +{
4689 + u32 gpiofunc; /* GPIO Function Register
4690 + * gpiofunc[x]==0 bit = gpio
4691 + * func[x]==1 bit = altfunc
4692 + */
4693 + u32 gpiocfg; /* GPIO Configuration Register
4694 + * gpiocfg[x]==0 bit = input
4695 + * gpiocfg[x]==1 bit = output
4696 + */
4697 + u32 gpiod; /* GPIO Data Register
4698 + * gpiod[x] read/write gpio pinX status
4699 + */
4700 + u32 gpioilevel; /* GPIO Interrupt Status Register
4701 + * interrupt level (see gpioistat)
4702 + */
4703 + u32 gpioistat; /* Gpio Interrupt Status Register
4704 + * istat[x] = (gpiod[x] == level[x])
4705 + * cleared in ISR (STICKY bits)
4706 + */
4707 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
4708 +} volatile * GPIO_t ;
4709 +
4710 +typedef enum
4711 +{
4712 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
4713 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
4714 + GPIO_input_v = 0, // gpiocfg use pin as input.
4715 + GPIO_output_v = 1, // gpiocfg use pin as output.
4716 + GPIO_pin0_b = 0,
4717 + GPIO_pin0_m = 0x00000001,
4718 + GPIO_pin1_b = 1,
4719 + GPIO_pin1_m = 0x00000002,
4720 + GPIO_pin2_b = 2,
4721 + GPIO_pin2_m = 0x00000004,
4722 + GPIO_pin3_b = 3,
4723 + GPIO_pin3_m = 0x00000008,
4724 + GPIO_pin4_b = 4,
4725 + GPIO_pin4_m = 0x00000010,
4726 + GPIO_pin5_b = 5,
4727 + GPIO_pin5_m = 0x00000020,
4728 + GPIO_pin6_b = 6,
4729 + GPIO_pin6_m = 0x00000040,
4730 + GPIO_pin7_b = 7,
4731 + GPIO_pin7_m = 0x00000080,
4732 + GPIO_pin8_b = 8,
4733 + GPIO_pin8_m = 0x00000100,
4734 + GPIO_pin9_b = 9,
4735 + GPIO_pin9_m = 0x00000200,
4736 + GPIO_pin10_b = 10,
4737 + GPIO_pin10_m = 0x00000400,
4738 + GPIO_pin11_b = 11,
4739 + GPIO_pin11_m = 0x00000800,
4740 + GPIO_pin12_b = 12,
4741 + GPIO_pin12_m = 0x00001000,
4742 + GPIO_pin13_b = 13,
4743 + GPIO_pin13_m = 0x00002000,
4744 + GPIO_pin14_b = 14,
4745 + GPIO_pin14_m = 0x00004000,
4746 + GPIO_pin15_b = 15,
4747 + GPIO_pin15_m = 0x00008000,
4748 +
4749 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
4750 +
4751 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
4752 + GPIO_u0sout_m = GPIO_pin0_m,
4753 + GPIO_u0sout_cfg_v = GPIO_output_v,
4754 +
4755 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
4756 + GPIO_u0sinp_m = GPIO_pin1_m,
4757 + GPIO_u0sinp_cfg_v = GPIO_input_v,
4758 +
4759 + GPIO_maddr22_b = GPIO_pin2_b, // M&P bus bit 22.
4760 + GPIO_maddr22_m = GPIO_pin2_m,
4761 + GPIO_maddr22_cfg_v = GPIO_output_v,
4762 +
4763 + GPIO_maddr23_b = GPIO_pin3_b, // M&P bus bit 23.
4764 + GPIO_maddr23_m = GPIO_pin3_m,
4765 + GPIO_maddr23_cfg_v = GPIO_output_v,
4766 +
4767 + GPIO_maddr24_b = GPIO_pin4_b, // M&P bus bit 24.
4768 + GPIO_maddr24_m = GPIO_pin4_m,
4769 + GPIO_maddr24_cfg_v = GPIO_output_v,
4770 +
4771 + GPIO_maddr25_b = GPIO_pin5_b, // M&P bus bit 25.
4772 + GPIO_maddr25_m = GPIO_pin5_m,
4773 + GPIO_maddr25_cfg_v = GPIO_output_v,
4774 +
4775 + GPIO_rngclk_b = GPIO_pin6_b, // reserved.
4776 + GPIO_rngclk_m = GPIO_pin6_m,
4777 + GPIO_rngclk_cfg_v = GPIO_input_v,
4778 +
4779 + GPIO_sdckenp_b = GPIO_pin7_b, // reserved.
4780 + GPIO_sdckenp_m = GPIO_pin7_m,
4781 + GPIO_sdckenp_cfg_v = GPIO_output_v,
4782 +
4783 + GPIO_cen1_b = GPIO_pin8_b, // reserved.
4784 + GPIO_cen1_m = GPIO_pin8_m,
4785 + GPIO_cen1_cfg_v = GPIO_output_v,
4786 +
4787 + GPIO_cen2_b = GPIO_pin9_b, // reserved.
4788 + GPIO_cen2_m = GPIO_pin9_m,
4789 + GPIO_cen2_cfg_v = GPIO_output_v,
4790 +
4791 + GPIO_regn_b = GPIO_pin10_b, // reserved.
4792 + GPIO_regn_m = GPIO_pin10_m,
4793 + GPIO_regn_cfg_v = GPIO_output_v,
4794 +
4795 + GPIO_iordn_b = GPIO_pin11_b, // reserved.
4796 + GPIO_iordn_m = GPIO_pin11_m,
4797 + GPIO_iordn_cfg_v = GPIO_output_v,
4798 +
4799 + GPIO_iowrn_b = GPIO_pin12_b, // reserved.
4800 + GPIO_iowrn_m = GPIO_pin12_m,
4801 + GPIO_iowrn_cfg_v = GPIO_output_v,
4802 +
4803 + GPIO_pcireqn2_b = GPIO_pin13_b, // PCI messaging int.
4804 + GPIO_pcireqn2_m = GPIO_pin13_m,
4805 + GPIO_pcireqn2_cfg_v = GPIO_input_v,
4806 +
4807 + GPIO_pcigntn2_b = GPIO_pin14_b, // PCI messaging int.
4808 + GPIO_pcigntn2_m = GPIO_pin14_m,
4809 + GPIO_pcigntn2_cfg_v = GPIO_output_v,
4810 +
4811 + GPIO_pcimuintn_b = GPIO_pin15_b, // PCI messaging int.
4812 + GPIO_pcimuintn_m = GPIO_pin15_m,
4813 + GPIO_pcimuintn_cfg_v= GPIO_output_v,
4814 +
4815 +} GPIO_DEFS_t;
4816 +
4817 +#endif //__IDT_RC32365_GPIO_H__
4818 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4819 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 1970-01-01 01:00:00.000000000 +0100
4820 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 2006-03-20 14:25:10.000000000 +0100
4821 @@ -0,0 +1,91 @@
4822 +/**************************************************************************
4823 + *
4824 + * BRIEF MODULE DESCRIPTION
4825 + * Routines to set/clear/toggle GPIO on RC32365
4826 + *
4827 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4828 + *
4829 + * This program is free software; you can redistribute it and/or modify it
4830 + * under the terms of the GNU General Public License as published by the
4831 + * Free Software Foundation; either version 2 of the License, or (at your
4832 + * option) any later version.
4833 + *
4834 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4835 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4836 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4837 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4838 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4839 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4840 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4841 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4842 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4843 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4844 + *
4845 + * You should have received a copy of the GNU General Public License along
4846 + * with this program; if not, write to the Free Software Foundation, Inc.,
4847 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4848 + *
4849 + *
4850 + **************************************************************************
4851 + * May 2004 P. Sadik.
4852 + *
4853 + * Initial Release
4854 + *
4855 + *
4856 + *
4857 + **************************************************************************
4858 + */
4859 +#ifndef __IDT_RC32365_GPIO_V_H__
4860 +#define __IDT_RC32365_GPIO_V_H__
4861 +
4862 +
4863 +#ifdef _LANGUAGE_ASSEMBLY
4864 +#define SET_GPIO(pin) \
4865 + lui t5,0xb804 ; \
4866 + ori t5,t5,0x8000 ; \
4867 + lw t4,8(t5) ; \
4868 + ori t4,t4,pin ; \
4869 + sw t4,8(t5) ;
4870 +
4871 +#define CLEAR_GPIO(pin) \
4872 + lui t5,0xb804 ; \
4873 + ori t5,t5,0x8000 ; \
4874 + lw t4,8(t5) ; \
4875 + lui t6,0xFFFF; \
4876 + ori t6,t6,0xFFFF; \
4877 + xori t6,t6,pin ; \
4878 + and t4,t6 ; \
4879 + sw t4,8(t5) ;
4880 +
4881 +#define TOGGLE_GPIO(pin) \
4882 + lui t5,0xb804 ; \
4883 + ori t5,t5,0x8000 ; \
4884 + lw t4,8(t5) ; \
4885 + xori t4,t4,pin ; \
4886 + sw t4,8(t5) ;
4887 +
4888 +#else // !_LANGUAGE_ASSEMBLY
4889 +#include <asm/rc32300/types.h>
4890 +#include <asm/rc32300/rc32365_gpio.h>
4891 +#include <asm/rc32300/rc32365.h>
4892 +
4893 +static inline void set_gpio(unsigned long pin)
4894 +{
4895 + idt_gpio->gpiod |= pin;
4896 +}
4897 +
4898 +static inline void clear_gpio(unsigned long pin)
4899 +{
4900 + idt_gpio->gpiod &= ~pin;
4901 +}
4902 +static inline void toggle_gpio(unsigned long pin)
4903 +{
4904 + idt_gpio->gpiod ^= pin;
4905 +}
4906 +#define SET_GPIO(pin) set_gpio(pin)
4907 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4908 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4909 +#endif // _LANGUAGE_ASSEMBLY
4910 +
4911 +#endif //__IDT_RC32365_GPIO_V_H__
4912 +
4913 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4914 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365.h 1970-01-01 01:00:00.000000000 +0100
4915 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h 2006-03-20 14:25:10.000000000 +0100
4916 @@ -0,0 +1,160 @@
4917 +/**************************************************************************
4918 + *
4919 + * BRIEF MODULE DESCRIPTION
4920 + * Definitions for IDT RC32365 CPU.
4921 + *
4922 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4923 + *
4924 + * This program is free software; you can redistribute it and/or modify it
4925 + * under the terms of the GNU General Public License as published by the
4926 + * Free Software Foundation; either version 2 of the License, or (at your
4927 + * option) any later version.
4928 + *
4929 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4930 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4931 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4932 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4933 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4934 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4935 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4936 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4937 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4938 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4939 + *
4940 + * You should have received a copy of the GNU General Public License along
4941 + * with this program; if not, write to the Free Software Foundation, Inc.,
4942 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4943 + *
4944 + *
4945 + **************************************************************************
4946 + * May 2004 P. Sadik.
4947 + *
4948 + * Initial Release
4949 + *
4950 + *
4951 + *
4952 + **************************************************************************
4953 + */
4954 +
4955 +#ifndef __IDT_RC32365_H__
4956 +#define __IDT_RC32365_H__
4957 +
4958 +extern unsigned int cedar_za;
4959 +
4960 +/* Base address of internal registers */
4961 +#define RC32365_REG_BASE 0x18000000
4962 +
4963 +/* System ID Registers */
4964 +#define CPU_SYSID (RC32365_REG_BASE + 0x00018)
4965 +#define CPU_DEVTYPE (RC32365_REG_BASE + 0x0001c)
4966 +
4967 +/* Reset Controller */
4968 +#define RESET_CNTL (RC32365_REG_BASE + 0x08000)
4969 +#define BOOT_VECTOR (RC32365_REG_BASE + 0x08004)
4970 +
4971 +/* Device Controller */
4972 +#define DEV0_BASE (RC32365_REG_BASE + 0x10000)
4973 +#define DEV0_MASK (RC32365_REG_BASE + 0x10004)
4974 +#define DEV0_CNTL (RC32365_REG_BASE + 0x10008)
4975 +#define DEV0_TIMING (RC32365_REG_BASE + 0x1000c)
4976 +#define DEV_REG_OFFSET 0x10
4977 +
4978 +/* SDRAM Controller */
4979 +#define SDRAM0_BASE (RC32365_REG_BASE + 0x18000)
4980 +#define SDRAM0_MASK (RC32365_REG_BASE + 0x18004)
4981 +#define SDRAM1_BASE (RC32365_REG_BASE + 0x18008)
4982 +#define SDRAM1_MASK (RC32365_REG_BASE + 0x1800c)
4983 +#define SDRAM_CNTL (RC32365_REG_BASE + 0x18010)
4984 +
4985 +/* Counters/Timers */
4986 +#define TIMER0_COUNT (RC32365_REG_BASE + 0x20000)
4987 +#define TIMER0_COMPARE (RC32365_REG_BASE + 0x20004)
4988 +#define TIMER0_CNTL (RC32365_REG_BASE + 0x20008)
4989 +#define TIMER0_SELECT (RC32365_REG_BASE + 0x2000c)
4990 +#define TIMER_REG_OFFSET 0x10
4991 +
4992 +/* System Integrity */
4993 +
4994 +/* Interrupt Controller */
4995 +#define IC_GROUP0_PEND (RC32365_REG_BASE + 0x30000)
4996 +#define IC_GROUP0_TEST (RC32365_REG_BASE + 0x30004)
4997 +#define IC_GROUP0_MASK (RC32365_REG_BASE + 0x30008)
4998 +#define IC_GROUP_OFFSET 0x0c
4999 +
5000 +#define NUM_INTR_GROUPS 5
5001 +/*
5002 + * The IRQ mapping is as follows:
5003 + *
5004 + * IRQ Mapped To
5005 + * --- -------------------
5006 + * 0 SW0 (IP0) SW0 intr
5007 + * 1 SW1 (IP1) SW1 intr
5008 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
5009 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
5010 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
5011 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
5012 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
5013 + * 7 Int5 (IP7) CP0 Timer
5014 + *
5015 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
5016 + * internally on the RC32365 is routed to the Expansion
5017 + * Interrupt Controller.
5018 + */
5019 +#define MIPS_CPU_TIMER_IRQ 7
5020 +
5021 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
5022 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
5023 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // RNG, SEC
5024 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
5025 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
5026 +
5027 +#define RC32365_NR_IRQS (GROUP4_IRQ_BASE + 32)
5028 +
5029 +/* DMA - see rc32365_dma.h for full list of registers */
5030 +
5031 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
5032 +#define DMA_CHAN_OFFSET 0x14
5033 +
5034 +/* GPIO Controller */
5035 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
5036 +
5037 +/* 16550 UARTs */
5038 +#ifdef __MIPSEB__
5039 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
5040 +#else
5041 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
5042 +#endif
5043 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 0)
5044 +
5045 +/* Ethernet - see rc32365_eth.h for full list of registers */
5046 +
5047 +#define RC32365_ETH_BASE (RC32365_REG_BASE + 0x58000)
5048 +
5049 +#define IDT_CLOCK_MULT 2
5050 +
5051 +/* FLASH (device 1) */
5052 +#define FLASH_BASE 0x08000000
5053 +#define FLASH_SIZE 0x00800000
5054 +
5055 +/* LCD 4-digit display (device 2) */
5056 +#define LCD_DIGIT0 0x0C000003
5057 +#define LCD_DIGIT1 0x0C000002
5058 +#define LCD_DIGIT2 0x0C000001
5059 +#define LCD_DIGIT3 0x0C000000
5060 +
5061 +/* RTC (DS1553) (device 2) */
5062 +#define RTC_BASE 0x0c800000
5063 +/* NVRAM */
5064 +#define NVRAM_BASE RTC_BASE
5065 +#define NVRAM_ENVSIZE_OFF 4
5066 +#define NVRAM_ENVSTART_OFF 32
5067 +
5068 +/* Interrupts routed on 79EB365 board */
5069 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE + 8)
5070 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE + 9)
5071 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5072 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5073 +
5074 +#define RAM_SIZE (32 * 1024 * 1024)
5075 +
5076 +#endif //__IDT_RC32365_H__
5077 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5078 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 1970-01-01 01:00:00.000000000 +0100
5079 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-03-20 14:25:10.000000000 +0100
5080 @@ -0,0 +1,515 @@
5081 +/**************************************************************************
5082 + *
5083 + * BRIEF MODULE DESCRIPTION
5084 + * Datatype declaration for IDT 79EB365/336 PCI
5085 + *
5086 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5087 + *
5088 + * This program is free software; you can redistribute it and/or modify it
5089 + * under the terms of the GNU General Public License as published by the
5090 + * Free Software Foundation; either version 2 of the License, or (at your
5091 + * option) any later version.
5092 + *
5093 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5094 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5095 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5096 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5097 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5098 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5099 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5100 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5101 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5102 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5103 + *
5104 + * You should have received a copy of the GNU General Public License along
5105 + * with this program; if not, write to the Free Software Foundation, Inc.,
5106 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5107 + *
5108 + *
5109 + **************************************************************************
5110 + * May 2004 P. Sadik.
5111 + *
5112 + * Initial Release
5113 + *
5114 + *
5115 + *
5116 + **************************************************************************
5117 + */
5118 +
5119 +#ifndef __IDT_RC32365_PCI_H__
5120 +#define __IDT_RC32365_PCI_H__
5121 +
5122 +enum
5123 +{
5124 + PCI0_PhysicalAddress = 0x18068000,
5125 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
5126 +
5127 + PCI0_VirtualAddress = 0xb8068000,
5128 + PCI_VirtualAddress = PCI0_VirtualAddress,
5129 +} ;
5130 +
5131 +enum
5132 +{
5133 + PCI_LbaCount = 4, // Local base addresses.
5134 +} ;
5135 +
5136 +typedef struct
5137 +{
5138 + u32 a ; // Address.
5139 + u32 c ; // Control.
5140 + u32 m ; // mapping.
5141 +} PCI_Map_s ;
5142 +
5143 +typedef struct
5144 +{
5145 + u32 pcic ;
5146 + u32 pcis ;
5147 + u32 pcism ;
5148 + u32 pcicfga ;
5149 + u32 pcicfgd ;
5150 + PCI_Map_s pcilba [PCI_LbaCount] ;
5151 + u32 pcidac ;
5152 + u32 pcidas ;
5153 + u32 pcidasm ;
5154 + u32 pcidad ;
5155 + u32 pcidma8c ;
5156 + u32 pcidma9c ;
5157 + u32 pcitc ;
5158 +} volatile *PCI_t ;
5159 +
5160 +// PCI messaging unit.
5161 +enum
5162 +{
5163 + PCIM_Count = 2,
5164 +} ;
5165 +typedef struct
5166 +{
5167 + u32 pciim [PCIM_Count] ;
5168 + u32 pciom [PCIM_Count] ;
5169 + u32 pciid ;
5170 + u32 pciiic ;
5171 + u32 pciiim ;
5172 + u32 pciiod ;
5173 + u32 pciioic ;
5174 + u32 pciioim ;
5175 +} volatile *PCIM_t ;
5176 +
5177 +/*******************************************************************************
5178 + *
5179 + * PCI Control Register
5180 + *
5181 + ******************************************************************************/
5182 +enum
5183 +{
5184 + PCIC_en_b = 0,
5185 + PCIC_en_m = 0x00000001,
5186 + PCIC_tnr_b = 1,
5187 + PCIC_tnr_m = 0x00000002,
5188 + PCIC_sce_b = 2,
5189 + PCIC_sce_m = 0x00000004,
5190 + PCIC_ien_b = 3,
5191 + PCIC_ien_m = 0x00000008,
5192 + PCIC_aaa_b = 4,
5193 + PCIC_aaa_m = 0x00000010,
5194 + PCIC_eap_b = 5,
5195 + PCIC_eap_m = 0x00000020,
5196 + PCIC_pcim_b = 6,
5197 + PCIC_pcim_m = 0x000001c0,
5198 + PCIC_pcim_disabled_v = 0,
5199 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
5200 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
5201 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
5202 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
5203 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
5204 + PCIC_pcim_reserved6_v = 6,
5205 + PCIC_pcim_reserved7_v = 7,
5206 + PCIC_igm_b = 9,
5207 + PCIC_igm_m = 0x00000200,
5208 +} ;
5209 +
5210 +/*******************************************************************************
5211 + *
5212 + * PCI Status Register
5213 + *
5214 + ******************************************************************************/
5215 +enum {
5216 + PCIS_eed_b = 0,
5217 + PCIS_eed_m = 0x00000001,
5218 + PCIS_wr_b = 1,
5219 + PCIS_wr_m = 0x00000002,
5220 + PCIS_nmi_b = 2,
5221 + PCIS_nmi_m = 0x00000004,
5222 + PCIS_ii_b = 3,
5223 + PCIS_ii_m = 0x00000008,
5224 + PCIS_cwe_b = 4,
5225 + PCIS_cwe_m = 0x00000010,
5226 + PCIS_cre_b = 5,
5227 + PCIS_cre_m = 0x00000020,
5228 + PCIS_mdpe_b = 6,
5229 + PCIS_mdpe_m = 0x00000040,
5230 + PCIS_sta_b = 7,
5231 + PCIS_sta_m = 0x00000080,
5232 + PCIS_rta_b = 8,
5233 + PCIS_rta_m = 0x00000100,
5234 + PCIS_rma_b = 9,
5235 + PCIS_rma_m = 0x00000200,
5236 + PCIS_sse_b = 10,
5237 + PCIS_sse_m = 0x00000400,
5238 + PCIS_ose_b = 11,
5239 + PCIS_ose_m = 0x00000800,
5240 + PCIS_pe_b = 12,
5241 + PCIS_pe_m = 0x00001000,
5242 + PCIS_tae_b = 13,
5243 + PCIS_tae_m = 0x00002000,
5244 + PCIS_rle_b = 14,
5245 + PCIS_rle_m = 0x00004000,
5246 + PCIS_bme_b = 15,
5247 + PCIS_bme_m = 0x00008000,
5248 + PCIS_prd_b = 16,
5249 + PCIS_prd_m = 0x00010000,
5250 + PCIS_rip_b = 17,
5251 + PCIS_rip_m = 0x00020000,
5252 +} ;
5253 +
5254 +/*******************************************************************************
5255 + *
5256 + * PCI Status Mask Register
5257 + *
5258 + ******************************************************************************/
5259 +enum {
5260 + PCISM_eed_b = 0,
5261 + PCISM_eed_m = 0x00000001,
5262 + PCISM_wr_b = 1,
5263 + PCISM_wr_m = 0x00000002,
5264 + PCISM_nmi_b = 2,
5265 + PCISM_nmi_m = 0x00000004,
5266 + PCISM_ii_b = 3,
5267 + PCISM_ii_m = 0x00000008,
5268 + PCISM_cwe_b = 4,
5269 + PCISM_cwe_m = 0x00000010,
5270 + PCISM_cre_b = 5,
5271 + PCISM_cre_m = 0x00000020,
5272 + PCISM_mdpe_b = 6,
5273 + PCISM_mdpe_m = 0x00000040,
5274 + PCISM_sta_b = 7,
5275 + PCISM_sta_m = 0x00000080,
5276 + PCISM_rta_b = 8,
5277 + PCISM_rta_m = 0x00000100,
5278 + PCISM_rma_b = 9,
5279 + PCISM_rma_m = 0x00000200,
5280 + PCISM_sse_b = 10,
5281 + PCISM_sse_m = 0x00000400,
5282 + PCISM_ose_b = 11,
5283 + PCISM_ose_m = 0x00000800,
5284 + PCISM_pe_b = 12,
5285 + PCISM_pe_m = 0x00001000,
5286 + PCISM_tae_b = 13,
5287 + PCISM_tae_m = 0x00002000,
5288 + PCISM_rle_b = 14,
5289 + PCISM_rle_m = 0x00004000,
5290 + PCISM_bme_b = 15,
5291 + PCISM_bme_m = 0x00008000,
5292 + PCISM_prd_b = 16,
5293 + PCISM_prd_m = 0x00010000,
5294 + PCISM_rip_b = 17,
5295 + PCISM_rip_m = 0x00020000,
5296 +} ;
5297 +
5298 +/*******************************************************************************
5299 + *
5300 + * PCI Configuration Address Register
5301 + *
5302 + ******************************************************************************/
5303 +enum {
5304 + PCICFGA_reg_b = 2,
5305 + PCICFGA_reg_m = 0x000000fc,
5306 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
5307 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
5308 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
5309 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
5310 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
5311 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
5312 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
5313 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
5314 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5315 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
5316 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
5317 + PCICFGA_reg_pba0m_v = 0x48>>2,
5318 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
5319 + PCICFGA_reg_pba1m_v = 0x50>>2,
5320 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
5321 + PCICFGA_reg_pba2m_v = 0x58>>2,
5322 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
5323 + PCICFGA_reg_pba3m_v = 0x60>>2,
5324 + PCICFGA_reg_pmgt_v = 0x64>>2,
5325 + PCICFGA_func_b = 8,
5326 + PCICFGA_func_m = 0x00000700,
5327 + PCICFGA_dev_b = 11,
5328 + PCICFGA_dev_m = 0x0000f800,
5329 + PCICFGA_dev_internal_v = 0,
5330 + PCICFGA_bus_b = 16,
5331 + PCICFGA_bus_m = 0x00ff0000,
5332 + PCICFGA_bus_type0_v = 0, //local bus
5333 + PCICFGA_en_b = 31, // read only
5334 + PCICFGA_en_m = 0x80000000,
5335 +} ;
5336 +
5337 +enum {
5338 + PCFGID_vendor_b = 0,
5339 + PCFGID_vendor_m = 0x0000ffff,
5340 + PCFGID_vendor_IDT_v = 0x111d,
5341 + PCFGID_device_b = 16,
5342 + PCFGID_device_m = 0xffff0000,
5343 + PCFGID_device_Acaciade_v = 0x0207,
5344 +
5345 + PCFG04_command_ioena_b = 1,
5346 + PCFG04_command_ioena_m = 0x00000001,
5347 + PCFG04_command_memena_b = 2,
5348 + PCFG04_command_memena_m = 0x00000002,
5349 + PCFG04_command_bmena_b = 3,
5350 + PCFG04_command_bmena_m = 0x00000004,
5351 + PCFG04_command_mwinv_b = 5,
5352 + PCFG04_command_mwinv_m = 0x00000010,
5353 + PCFG04_command_parena_b = 7,
5354 + PCFG04_command_parena_m = 0x00000040,
5355 + PCFG04_command_serrena_b = 9,
5356 + PCFG04_command_serrena_m = 0x00000100,
5357 + PCFG04_command_fastbbena_b = 10,
5358 + PCFG04_command_fastbbena_m = 0x00000200,
5359 + PCFG04_status_b = 16,
5360 + PCFG04_status_m = 0xffff0000,
5361 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
5362 + PCFG04_status_66MHz_m = 0x00200000,
5363 + PCFG04_status_fbb_b = 23,
5364 + PCFG04_status_fbb_m = 0x00800000,
5365 + PCFG04_status_mdpe_b = 24,
5366 + PCFG04_status_mdpe_m = 0x01000000,
5367 + PCFG04_status_dst_b = 25,
5368 + PCFG04_status_dst_m = 0x06000000,
5369 + PCFG04_status_sta_b = 27,
5370 + PCFG04_status_sta_m = 0x08000000,
5371 + PCFG04_status_rta_b = 28,
5372 + PCFG04_status_rta_m = 0x10000000,
5373 + PCFG04_status_rma_b = 29,
5374 + PCFG04_status_rma_m = 0x20000000,
5375 + PCFG04_status_sse_b = 30,
5376 + PCFG04_status_sse_m = 0x40000000,
5377 + PCFG04_status_pe_b = 31,
5378 + PCFG04_status_pe_m = 0x40000000,
5379 +
5380 + PCFG08_revId_b = 0,
5381 + PCFG08_revId_m = 0x000000ff,
5382 + PCFG08_classCode_b = 0,
5383 + PCFG08_classCode_m = 0xffffff00,
5384 + PCFG08_classCode_bridge_v = 06,
5385 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
5386 + PCFG0C_cacheline_b = 0,
5387 + PCFG0C_cacheline_m = 0x000000ff,
5388 + PCFG0C_masterLatency_b = 8,
5389 + PCFG0C_masterLatency_m = 0x0000ff00,
5390 + PCFG0C_headerType_b = 16,
5391 + PCFG0C_headerType_m = 0x00ff0000,
5392 + PCFG0C_bist_b = 24,
5393 + PCFG0C_bist_m = 0xff000000,
5394 +
5395 + PCIPBA_msi_b = 0,
5396 + PCIPBA_msi_m = 0x00000001,
5397 + PCIPBA_p_b = 3,
5398 + PCIPBA_p_m = 0x00000004,
5399 + PCIPBA_baddr_b = 8,
5400 + PCIPBA_baddr_m = 0xffffff00,
5401 +
5402 + PCFGSS_vendorId_b = 0,
5403 + PCFGSS_vendorId_m = 0x0000ffff,
5404 + PCFGSS_id_b = 16,
5405 + PCFGSS_id_m = 0xffff0000,
5406 +
5407 + PCFG3C_interruptLine_b = 0,
5408 + PCFG3C_interruptLine_m = 0x000000ff,
5409 + PCFG3C_interruptPin_b = 8,
5410 + PCFG3C_interruptPin_m = 0x0000ff00,
5411 + PCFG3C_minGrant_b = 16,
5412 + PCFG3C_minGrant_m = 0x00ff0000,
5413 + PCFG3C_maxLat_b = 24,
5414 + PCFG3C_maxLat_m = 0xff000000,
5415 +
5416 + PCIPBAC_msi_b = 0,
5417 + PCIPBAC_msi_m = 0x00000001,
5418 + PCIPBAC_p_b = 1,
5419 + PCIPBAC_p_m = 0x00000002,
5420 + PCIPBAC_size_b = 2,
5421 + PCIPBAC_size_m = 0x0000007c,
5422 + PCIPBAC_sb_b = 7,
5423 + PCIPBAC_sb_m = 0x00000080,
5424 + PCIPBAC_pp_b = 8,
5425 + PCIPBAC_pp_m = 0x00000100,
5426 + PCIPBAC_mr_b = 9,
5427 + PCIPBAC_mr_m = 0x00000600,
5428 + PCIPBAC_mr_read_v =0, //no prefetching
5429 + PCIPBAC_mr_readLine_v =1,
5430 + PCIPBAC_mr_readMult_v =2,
5431 + PCIPBAC_mrl_b = 11,
5432 + PCIPBAC_mrl_m = 0x00000800,
5433 + PCIPBAC_mrm_b = 12,
5434 + PCIPBAC_mrm_m = 0x00001000,
5435 + PCIPBAC_trp_b = 13,
5436 + PCIPBAC_trp_m = 0x00002000,
5437 +
5438 + PCFG40_trdyTimeout_b = 0,
5439 + PCFG40_trdyTimeout_m = 0x000000ff,
5440 + PCFG40_retryLim_b = 8,
5441 + PCFG40_retryLim_m = 0x0000ff00,
5442 +};
5443 +
5444 +/*******************************************************************************
5445 + *
5446 + * PCI Local Base Address [0|1|2|3] Register
5447 + *
5448 + ******************************************************************************/
5449 +enum {
5450 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
5451 + PCILBA_baddr_m = 0xffffff00,
5452 +} ;
5453 +/*******************************************************************************
5454 + *
5455 + * PCI Local Base Address Control Register
5456 + *
5457 + ******************************************************************************/
5458 +enum {
5459 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
5460 + PCILBAC_msi_m = 0x00000001,
5461 + PCILBAC_msi_mem_v = 0,
5462 + PCILBAC_msi_io_v = 1,
5463 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
5464 + PCILBAC_size_m = 0x0000007c,
5465 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
5466 + PCILBAC_sb_m = 0x00000080,
5467 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
5468 + PCILBAC_rt_m = 0x00000100,
5469 + PCILBAC_rt_noprefetch_v = 0, // mem read
5470 + PCILBAC_rt_prefetch_v = 1, // mem readline
5471 +} ;
5472 +
5473 +/*******************************************************************************
5474 + *
5475 + * PCI Local Base Address [0|1|2|3] Mapping Register
5476 + *
5477 + ******************************************************************************/
5478 +enum {
5479 + PCILBAM_maddr_b = 8,
5480 + PCILBAM_maddr_m = 0xffffff00,
5481 +} ;
5482 +
5483 +/*******************************************************************************
5484 + *
5485 + * PCI Decoupled Access Control Register
5486 + *
5487 + ******************************************************************************/
5488 +enum {
5489 + PCIDAC_den_b = 0,
5490 + PCIDAC_den_m = 0x00000001,
5491 +} ;
5492 +
5493 +/*******************************************************************************
5494 + *
5495 + * PCI Decoupled Access Status Register
5496 + *
5497 + ******************************************************************************/
5498 +enum {
5499 + PCIDAS_d_b = 0,
5500 + PCIDAS_d_m = 0x00000001,
5501 + PCIDAS_b_b = 1,
5502 + PCIDAS_b_m = 0x00000002,
5503 + PCIDAS_e_b = 2,
5504 + PCIDAS_e_m = 0x00000004,
5505 + PCIDAS_ofe_b = 3,
5506 + PCIDAS_ofe_m = 0x00000008,
5507 + PCIDAS_off_b = 4,
5508 + PCIDAS_off_m = 0x00000010,
5509 + PCIDAS_ife_b = 5,
5510 + PCIDAS_ife_m = 0x00000020,
5511 + PCIDAS_iff_b = 6,
5512 + PCIDAS_iff_m = 0x00000040,
5513 +} ;
5514 +
5515 +/*******************************************************************************
5516 + *
5517 + * PCI DMA Channel 8 Configuration Register
5518 + *
5519 + ******************************************************************************/
5520 +enum
5521 +{
5522 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
5523 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
5524 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
5525 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
5526 +} ;
5527 +
5528 +/*******************************************************************************
5529 + *
5530 + * PCI DMA Channel 9 Configuration Register
5531 + *
5532 + ******************************************************************************/
5533 +enum
5534 +{
5535 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
5536 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
5537 +} ;
5538 +
5539 +/*******************************************************************************
5540 + *
5541 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5542 + *
5543 + ******************************************************************************/
5544 +enum {
5545 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
5546 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
5547 + // These are for reads (DMA channel 8)
5548 + PCIDMAD_devcmd_mr_v = 0, //memory read
5549 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
5550 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
5551 + PCIDMAD_devcmd_ior_v = 3, //I/O read
5552 + // These are for writes (DMA channel 9)
5553 + PCIDMAD_devcmd_mw_v = 0, //memory write
5554 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
5555 + PCIDMAD_devcmd_iow_v = 3, //I/O write
5556 +
5557 + // Swap byte field applies to both DMA channel 8 and 9
5558 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
5559 + PCIDMAD_sb_m = 0x01000000, // swap byte field
5560 +} ;
5561 +
5562 +
5563 +/*******************************************************************************
5564 + *
5565 + * PCI Target Control Register
5566 + *
5567 + ******************************************************************************/
5568 +enum
5569 +{
5570 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
5571 + PCITC_rtimer_m = 0x000000ff,
5572 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
5573 + PCITC_dtimer_m = 0x0000ff00,
5574 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
5575 + PCITC_rdr_m = 0x00040000,
5576 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
5577 + PCITC_ddt_m = 0x00080000,
5578 +} ;
5579 +/*******************************************************************************
5580 + *
5581 + * PCI messaging unit [applies to both inbound and outbound registers ]
5582 + *
5583 + ******************************************************************************/
5584 +enum
5585 +{
5586 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5587 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
5588 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5589 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
5590 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5591 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
5592 +};
5593 +
5594 +
5595 +#endif // __IDT_RC32365_PCI_H__
5596 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5597 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 1970-01-01 01:00:00.000000000 +0100
5598 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 2006-03-20 14:25:10.000000000 +0100
5599 @@ -0,0 +1,217 @@
5600 +/**************************************************************************
5601 + *
5602 + * BRIEF MODULE DESCRIPTION
5603 + * PCI header values for IDT 79EB365/336
5604 + *
5605 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5606 + *
5607 + * This program is free software; you can redistribute it and/or modify it
5608 + * under the terms of the GNU General Public License as published by the
5609 + * Free Software Foundation; either version 2 of the License, or (at your
5610 + * option) any later version.
5611 + *
5612 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5613 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5614 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5615 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5616 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5617 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5618 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5619 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5620 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5621 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5622 + *
5623 + * You should have received a copy of the GNU General Public License along
5624 + * with this program; if not, write to the Free Software Foundation, Inc.,
5625 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5626 + *
5627 + *
5628 + **************************************************************************
5629 + * May 2004 P. Sadik.
5630 + *
5631 + * Initial Release
5632 + *
5633 + *
5634 + *
5635 + **************************************************************************
5636 + */
5637 +
5638 +#ifndef __IDT_RC32365_PCI_V_H__
5639 +#define __IDT_RC32365_PCI_V_H__
5640 +
5641 +
5642 +#define PCI_MSG_VirtualAddress 0xB806C010
5643 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5644 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5645 +
5646 +#define PCIM_SHFT 0x6
5647 +#define PCIM_BIT_LEN 0x7
5648 +#define PCIM_H_EA 0x3
5649 +#define PCIM_H_IA_FIX 0x4
5650 +#define PCIM_H_IA_RR 0x5
5651 +
5652 +#define PCI_ADDR_START 0x50000000
5653 +
5654 +#define CPUTOPCI_MEM_WIN 0x02000000
5655 +#define CPUTOPCI_IO_WIN 0x00100000
5656 +#define PCILBA_SIZE_SHFT 2
5657 +#define PCILBA_SIZE_MASK 0x1F
5658 +#define SIZE_256MB 0x1C
5659 +#define SIZE_128MB 0x1B
5660 +#define SIZE_64MB 0x1A
5661 +#define SIZE_32MB 0x19
5662 +#define SIZE_16MB 0x18
5663 +#define SIZE_4MB 0x16
5664 +#define SIZE_2MB 0x15
5665 +#define SIZE_1MB 0x14
5666 +#define CEDAR_CONFIG0_ADDR 0x80000000
5667 +#define CEDAR_CONFIG1_ADDR 0x80000004
5668 +#define CEDAR_CONFIG2_ADDR 0x80000008
5669 +#define CEDAR_CONFIG3_ADDR 0x8000000C
5670 +#define CEDAR_CONFIG4_ADDR 0x80000010
5671 +#define CEDAR_CONFIG5_ADDR 0x80000014
5672 +#define CEDAR_CONFIG6_ADDR 0x80000018
5673 +#define CEDAR_CONFIG7_ADDR 0x8000001C
5674 +#define CEDAR_CONFIG8_ADDR 0x80000020
5675 +#define CEDAR_CONFIG9_ADDR 0x80000024
5676 +#define CEDAR_CONFIG10_ADDR 0x80000028
5677 +#define CEDAR_CONFIG11_ADDR 0x8000002C
5678 +#define CEDAR_CONFIG12_ADDR 0x80000030
5679 +#define CEDAR_CONFIG13_ADDR 0x80000034
5680 +#define CEDAR_CONFIG14_ADDR 0x80000038
5681 +#define CEDAR_CONFIG15_ADDR 0x8000003C
5682 +#define CEDAR_CONFIG16_ADDR 0x80000040
5683 +#define CEDAR_CONFIG17_ADDR 0x80000044
5684 +#define CEDAR_CONFIG18_ADDR 0x80000048
5685 +#define CEDAR_CONFIG19_ADDR 0x8000004C
5686 +#define CEDAR_CONFIG20_ADDR 0x80000050
5687 +#define CEDAR_CONFIG21_ADDR 0x80000054
5688 +#define CEDAR_CONFIG22_ADDR 0x80000058
5689 +#define CEDAR_CONFIG23_ADDR 0x8000005C
5690 +#define CEDAR_CONFIG24_ADDR 0x80000060
5691 +#define CEDAR_CONFIG25_ADDR 0x80000064
5692 +#define CEDAR_CMD (PCFG04_command_ioena_m | \
5693 + PCFG04_command_memena_m | \
5694 + PCFG04_command_bmena_m | \
5695 + PCFG04_command_mwinv_m | \
5696 + PCFG04_command_parena_m | \
5697 + PCFG04_command_serrena_m )
5698 +
5699 +#define CEDAR_STAT (PCFG04_status_mdpe_m | \
5700 + PCFG04_status_sta_m | \
5701 + PCFG04_status_rta_m | \
5702 + PCFG04_status_rma_m | \
5703 + PCFG04_status_sse_m | \
5704 + PCFG04_status_pe_m)
5705 +
5706 +#define CEDAR_CNFG1 ((CEDAR_STAT << 16) | \
5707 + CEDAR_CMD)
5708 +
5709 +#define CEDAR_REVID 0
5710 +#define CEDAR_CLASS_CODE 0
5711 +#define CEDAR_CNFG2 ((CEDAR_CLASS_CODE << 8) | \
5712 + CEDAR_REVID)
5713 +
5714 +#define CEDAR_CACHE_LINE_SIZE 4
5715 +#define CEDAR_MASTER_LAT 0x3c
5716 +#define CEDAR_HEADER_TYPE 0
5717 +#define CEDAR_BIST 0
5718 +
5719 +#define CEDAR_CNFG3 ((CEDAR_BIST << 24) | \
5720 + (CEDAR_HEADER_TYPE << 16) | \
5721 + (CEDAR_MASTER_LAT << 8) | \
5722 + CEDAR_CACHE_LINE_SIZE)
5723 +
5724 +#define CEDAR_BAR0 0x00000008 /* 128 MB Memory */
5725 +#define CEDAR_BAR1 0x18800001 /* 1 MB IO */
5726 +#define CEDAR_BAR2 0x18000001 /* 2 MB IO window for Cedar
5727 + internal Registers */
5728 +#define CEDAR_BAR3 0x48000008 /* Spare 128 MB Memory */
5729 +
5730 +#define CEDAR_CNFG4 CEDAR_BAR0
5731 +#define CEDAR_CNFG5 CEDAR_BAR1
5732 +#define CEDAR_CNFG6 CEDAR_BAR2
5733 +#define CEDAR_CNFG7 CEDAR_BAR3
5734 +
5735 +#define CEDAR_SUBSYS_VENDOR_ID 0
5736 +#define CEDAR_SUBSYSTEM_ID 0
5737 +#define CEDAR_CNFG8 0
5738 +#define CEDAR_CNFG9 0
5739 +#define CEDAR_CNFG10 0
5740 +#define CEDAR_CNFG11 ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5741 + CEDAR_SUBSYSTEM_ID)
5742 +#define CEDAR_INT_LINE 1
5743 +#define CEDAR_INT_PIN 1
5744 +#define CEDAR_MIN_GNT 8
5745 +#define CEDAR_MAX_LAT 0x38
5746 +#define CEDAR_CNFG12 0
5747 +#define CEDAR_CNFG13 0
5748 +#define CEDAR_CNFG14 0
5749 +#define CEDAR_CNFG15 ((CEDAR_MAX_LAT << 24) | \
5750 + (CEDAR_MIN_GNT << 16) | \
5751 + (CEDAR_INT_PIN << 8) | \
5752 + CEDAR_INT_LINE)
5753 +#define CEDAR_RETRY_LIMIT 0x80
5754 +#define CEDAR_TRDY_LIMIT 0x80
5755 +#define CEDAR_CNFG16 ((CEDAR_RETRY_LIMIT << 8) | \
5756 + CEDAR_TRDY_LIMIT)
5757 +#define PCI_PBAxC_R 0x0
5758 +#define PCI_PBAxC_RL 0x1
5759 +#define PCI_PBAxC_RM 0x2
5760 +#define SIZE_SHFT 2
5761 +#ifdef __MIPSEB__
5762 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5763 + PCIPBAC_pp_m | \
5764 + PCIPBAC_sb_m | \
5765 + (SIZE_128MB << SIZE_SHFT) | \
5766 + PCIPBAC_p_m)
5767 +#else
5768 +
5769 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5770 + PCIPBAC_pp_m | \
5771 + (SIZE_128MB << SIZE_SHFT) | \
5772 + PCIPBAC_p_m)
5773 +#endif
5774 +#define CEDAR_CNFG17 CEDAR_PBA0C
5775 +#define CEDAR_PBA0M 0x0
5776 +#define CEDAR_CNFG18 CEDAR_PBA0M
5777 +
5778 +#ifdef __MIPSEB__
5779 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5780 + PCIPBAC_sb_m | \
5781 + PCIPBAC_msi_m)
5782 +#else
5783 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5784 + PCIPBAC_msi_m)
5785 +#endif
5786 +#define CEDAR_CNFG19 CEDAR_PBA1C
5787 +#define CEDAR_PBA1M 0x0
5788 +#define CEDAR_CNFG20 CEDAR_PBA1M
5789 +
5790 +#ifdef __MIPSEB__
5791 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5792 + PCIPBAC_sb_m | \
5793 + PCIPBAC_msi_m)
5794 +#else
5795 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5796 + PCIPBAC_msi_m)
5797 +#endif
5798 +
5799 +#define CEDAR_CNFG21 CEDAR_PBA2C
5800 +#define CEDAR_PBA2M 0x18000000
5801 +#define CEDAR_CNFG22 CEDAR_PBA2M
5802 +
5803 +#ifdef __MIPSEB__
5804 +#define CEDAR_PBA3C PCIPBAC_sb_m
5805 +#else
5806 +#define CEDAR_PBA3C 0
5807 +#endif
5808 +
5809 +#define CEDAR_CNFG23 CEDAR_PBA3C
5810 +#define CEDAR_PBA3M 0
5811 +#define CEDAR_CNFG24 CEDAR_PBA3M
5812 +
5813 +#define PCITC_DTIMER_VAL 8
5814 +#define PCITC_RTIMER_VAL 0x10
5815 +
5816 +#endif //__IDT_RC32365_PCI_V_H__
5817 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5818 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 1970-01-01 01:00:00.000000000 +0100
5819 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-03-20 14:25:10.000000000 +0100
5820 @@ -0,0 +1,205 @@
5821 +/**************************************************************************
5822 + *
5823 + * BRIEF MODULE DESCRIPTION
5824 + * DMA register definition
5825 + *
5826 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5827 + *
5828 + * This program is free software; you can redistribute it and/or modify it
5829 + * under the terms of the GNU General Public License as published by the
5830 + * Free Software Foundation; either version 2 of the License, or (at your
5831 + * option) any later version.
5832 + *
5833 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5834 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5835 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5836 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5837 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5838 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5839 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5840 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5841 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5842 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5843 + *
5844 + * You should have received a copy of the GNU General Public License along
5845 + * with this program; if not, write to the Free Software Foundation, Inc.,
5846 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5847 + *
5848 + *
5849 + **************************************************************************
5850 + * May 2004 rkt, neb
5851 + *
5852 + * Initial Release
5853 + *
5854 + *
5855 + *
5856 + **************************************************************************
5857 + */
5858 +
5859 +#ifndef __IDT_DMA_H__
5860 +#define __IDT_DMA_H__
5861 +
5862 +enum
5863 +{
5864 + DMA0_PhysicalAddress = 0x18040000,
5865 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
5866 +
5867 + DMA0_VirtualAddress = 0xb8040000,
5868 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
5869 +} ;
5870 +
5871 +/*
5872 + * DMA descriptor (in physical memory).
5873 + */
5874 +
5875 +typedef struct DMAD_s
5876 +{
5877 + u32 control ; // Control. use DMAD_*
5878 + u32 ca ; // Current Address.
5879 + u32 devcs ; // Device control and status.
5880 + u32 link ; // Next descriptor in chain.
5881 +} volatile *DMAD_t ;
5882 +
5883 +enum
5884 +{
5885 + DMAD_size = sizeof (struct DMAD_s),
5886 + DMAD_count_b = 0, // in DMAD_t -> control
5887 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
5888 + DMAD_ds_b = 20, // in DMAD_t -> control
5889 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
5890 + DMAD_ds_ethRcv0_v = 0,
5891 + DMAD_ds_ethXmt0_v = 0,
5892 + DMAD_ds_memToFifo_v = 0,
5893 + DMAD_ds_fifoToMem_v = 0,
5894 + DMAD_ds_pciToMem_v = 0,
5895 + DMAD_ds_memToPci_v = 0,
5896 +
5897 + DMAD_devcmd_b = 22, // in DMAD_t -> control
5898 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
5899 + DMAD_devcmd_byte_v = 0, //memory-to-memory
5900 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
5901 + DMAD_devcmd_word_v = 2, //memory-to-memory
5902 + DMAD_devcmd_2words_v = 3, //memory-to-memory
5903 + DMAD_devcmd_4words_v = 4, //memory-to-memory
5904 + DMAD_devcmd_6words_v = 5, //memory-to-memory
5905 + DMAD_devcmd_8words_v = 6, //memory-to-memory
5906 + DMAD_devcmd_16words_v = 7, //memory-to-memory
5907 + DMAD_cof_b = 25, // chain on finished
5908 + DMAD_cof_m = 0x02000000, //
5909 + DMAD_cod_b = 26, // chain on done
5910 + DMAD_cod_m = 0x04000000, //
5911 + DMAD_iof_b = 27, // interrupt on finished
5912 + DMAD_iof_m = 0x08000000, //
5913 + DMAD_iod_b = 28, // interrupt on done
5914 + DMAD_iod_m = 0x10000000, //
5915 + DMAD_t_b = 29, // terminated
5916 + DMAD_t_m = 0x20000000, //
5917 + DMAD_d_b = 30, // done
5918 + DMAD_d_m = 0x40000000, //
5919 + DMAD_f_b = 31, // finished
5920 + DMAD_f_m = 0x80000000, //
5921 +} ;
5922 +
5923 +/*
5924 + * DMA register (within Internal Register Map).
5925 + */
5926 +
5927 +struct DMA_Chan_s
5928 +{
5929 + u32 dmac ; // Control.
5930 + u32 dmas ; // Status.
5931 + u32 dmasm ; // Mask.
5932 + u32 dmadptr ; // Descriptor pointer.
5933 + u32 dmandptr ; // Next descriptor pointer.
5934 +};
5935 +
5936 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5937 +
5938 +//DMA_Channels use DMACH_count instead
5939 +
5940 +enum
5941 +{
5942 + DMAC_run_b = 0, //
5943 + DMAC_run_m = 0x00000001, //
5944 + DMAC_dm_b = 1, // done mask
5945 + DMAC_dm_m = 0x00000002, //
5946 + DMAC_mode_b = 2, //
5947 + DMAC_mode_m = 0x0000000c, //
5948 + DMAC_mode_auto_v = 0,
5949 + DMAC_mode_burst_v = 1,
5950 + DMAC_mode_transfer_v = 2, //usually used
5951 + DMAC_mode_reserved_v = 3,
5952 + DMAC_a_b = 4, //
5953 + DMAC_a_m = 0x00000010, //
5954 +
5955 + DMAS_f_b = 0, // finished (sticky)
5956 + DMAS_f_m = 0x00000001, //
5957 + DMAS_d_b = 1, // done (sticky)
5958 + DMAS_d_m = 0x00000002, //
5959 + DMAS_c_b = 2, // chain (sticky)
5960 + DMAS_c_m = 0x00000004, //
5961 + DMAS_e_b = 3, // error (sticky)
5962 + DMAS_e_m = 0x00000008, //
5963 + DMAS_h_b = 4, // halt (sticky)
5964 + DMAS_h_m = 0x00000010, //
5965 +
5966 + DMASM_f_b = 0, // finished (1=mask)
5967 + DMASM_f_m = 0x00000001, //
5968 + DMASM_d_b = 1, // done (1=mask)
5969 + DMASM_d_m = 0x00000002, //
5970 + DMASM_c_b = 2, // chain (1=mask)
5971 + DMASM_c_m = 0x00000004, //
5972 + DMASM_e_b = 3, // error (1=mask)
5973 + DMASM_e_m = 0x00000008, //
5974 + DMASM_h_b = 4, // halt (1=mask)
5975 + DMASM_h_m = 0x00000010, //
5976 +} ;
5977 +
5978 +/*
5979 + * DMA channel definitions
5980 + */
5981 +
5982 +enum
5983 +{
5984 + DMACH_ethRcv0 = 0,
5985 + DMACH_ethXmt0 = 1,
5986 + DMACH_memToFifo = 2,
5987 + DMACH_fifoToMem = 3,
5988 + DMACH_pciToMem = 4,
5989 + DMACH_memToPci = 5,
5990 +
5991 + DMACH_count //must be last
5992 +};
5993 +
5994 +
5995 +typedef struct DMAC_s
5996 +{
5997 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
5998 +} volatile *DMA_t ;
5999 +
6000 +
6001 +/*
6002 + * External DMA parameters
6003 +*/
6004 +
6005 +enum
6006 +{
6007 + DMADEVCMD_ts_b = 0, // ts field in devcmd
6008 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
6009 + DMADEVCMD_ts_byte_v = 0,
6010 + DMADEVCMD_ts_halfword_v = 1,
6011 + DMADEVCMD_ts_word_v = 2,
6012 + DMADEVCMD_ts_2word_v = 3,
6013 + DMADEVCMD_ts_4word_v = 4,
6014 + DMADEVCMD_ts_6word_v = 5,
6015 + DMADEVCMD_ts_8word_v = 6,
6016 + DMADEVCMD_ts_16word_v = 7
6017 +};
6018 +
6019 +
6020 +#endif // __IDT_DMA_H__
6021 +
6022 +
6023 +
6024 +
6025 +
6026 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
6027 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 1970-01-01 01:00:00.000000000 +0100
6028 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 2006-03-20 14:25:10.000000000 +0100
6029 @@ -0,0 +1,89 @@
6030 +/**************************************************************************
6031 + *
6032 + * BRIEF MODULE DESCRIPTION
6033 + * Definitions for DMA controller.
6034 + *
6035 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6036 + *
6037 + * This program is free software; you can redistribute it and/or modify it
6038 + * under the terms of the GNU General Public License as published by the
6039 + * Free Software Foundation; either version 2 of the License, or (at your
6040 + * option) any later version.
6041 + *
6042 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6043 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6044 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6045 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6046 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6047 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6048 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6049 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6050 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6051 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6052 + *
6053 + * You should have received a copy of the GNU General Public License along
6054 + * with this program; if not, write to the Free Software Foundation, Inc.,
6055 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6056 + *
6057 + *
6058 + **************************************************************************
6059 + * May 2004 rkt, neb.
6060 + *
6061 + * Initial Release
6062 + *
6063 + *
6064 + *
6065 + **************************************************************************
6066 + */
6067 +
6068 +#ifndef __IDT_DMA_V_H__
6069 +#define __IDT_DMA_V_H__
6070 +
6071 +#include <asm/idt-boards/rc32434/rc32434_dma.h>
6072 +#include <asm/idt-boards/rc32434/rc32434.h>
6073 +
6074 +#define DMA_CHAN_OFFSET 0x14
6075 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6076 +#define DMA_COUNT(count) \
6077 + ((count) & DMAD_count_m)
6078 +
6079 +#define DMA_HALT_TIMEOUT 500
6080 +
6081 +
6082 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6083 +{
6084 + int timeout=1;
6085 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6086 + rc32434_writel(0, &ch->dmac);
6087 +
6088 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6089 + if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6090 + rc32434_writel(0, &ch->dmas);
6091 + break;
6092 + }
6093 + }
6094 +
6095 + }
6096 +
6097 + return timeout ? 0 : 1;
6098 +}
6099 +
6100 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6101 +{
6102 + rc32434_writel(0, &ch->dmandptr);
6103 + rc32434_writel(dma_addr, &ch->dmadptr);
6104 +}
6105 +
6106 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6107 +{
6108 + rc32434_writel(dma_addr, &ch->dmandptr);
6109 +}
6110 +
6111 +#endif // __IDT_DMA_V_H__
6112 +
6113 +
6114 +
6115 +
6116 +
6117 +
6118 +
6119 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6120 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
6121 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-03-20 14:25:10.000000000 +0100
6122 @@ -0,0 +1,333 @@
6123 +/**************************************************************************
6124 + *
6125 + * BRIEF MODULE DESCRIPTION
6126 + * Ethernet register definition
6127 + *
6128 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6129 + *
6130 + * This program is free software; you can redistribute it and/or modify it
6131 + * under the terms of the GNU General Public License as published by the
6132 + * Free Software Foundation; either version 2 of the License, or (at your
6133 + * option) any later version.
6134 + *
6135 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6136 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6137 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6138 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6139 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6140 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6141 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6142 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6143 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6144 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6145 + *
6146 + * You should have received a copy of the GNU General Public License along
6147 + * with this program; if not, write to the Free Software Foundation, Inc.,
6148 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6149 + *
6150 + *
6151 + **************************************************************************
6152 + * May 2004 rkt, neb.
6153 + *
6154 + * Initial Release
6155 + *
6156 + *
6157 + *
6158 + **************************************************************************
6159 + */
6160 +
6161 +#ifndef __IDT_ETH_H__
6162 +#define __IDT_ETH_H__
6163 +
6164 +
6165 +enum
6166 +{
6167 + ETH0_PhysicalAddress = 0x18060000,
6168 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
6169 +
6170 + ETH0_VirtualAddress = 0xb8060000,
6171 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
6172 +} ;
6173 +
6174 +typedef struct
6175 +{
6176 + u32 ethintfc ;
6177 + u32 ethfifott ;
6178 + u32 etharc ;
6179 + u32 ethhash0 ;
6180 + u32 ethhash1 ;
6181 + u32 ethu0 [4] ; // Reserved.
6182 + u32 ethpfs ;
6183 + u32 ethmcp ;
6184 + u32 eth_u1 [10] ; // Reserved.
6185 + u32 ethspare ;
6186 + u32 eth_u2 [42] ; // Reserved.
6187 + u32 ethsal0 ;
6188 + u32 ethsah0 ;
6189 + u32 ethsal1 ;
6190 + u32 ethsah1 ;
6191 + u32 ethsal2 ;
6192 + u32 ethsah2 ;
6193 + u32 ethsal3 ;
6194 + u32 ethsah3 ;
6195 + u32 ethrbc ;
6196 + u32 ethrpc ;
6197 + u32 ethrupc ;
6198 + u32 ethrfc ;
6199 + u32 ethtbc ;
6200 + u32 ethgpf ;
6201 + u32 eth_u9 [50] ; // Reserved.
6202 + u32 ethmac1 ;
6203 + u32 ethmac2 ;
6204 + u32 ethipgt ;
6205 + u32 ethipgr ;
6206 + u32 ethclrt ;
6207 + u32 ethmaxf ;
6208 + u32 eth_u10 ; // Reserved.
6209 + u32 ethmtest ;
6210 + u32 miimcfg ;
6211 + u32 miimcmd ;
6212 + u32 miimaddr ;
6213 + u32 miimwtd ;
6214 + u32 miimrdd ;
6215 + u32 miimind ;
6216 + u32 eth_u11 ; // Reserved.
6217 + u32 eth_u12 ; // Reserved.
6218 + u32 ethcfsa0 ;
6219 + u32 ethcfsa1 ;
6220 + u32 ethcfsa2 ;
6221 +} volatile *ETH_t;
6222 +
6223 +enum
6224 +{
6225 + ETHINTFC_en_b = 0,
6226 + ETHINTFC_en_m = 0x00000001,
6227 + ETHINTFC_its_b = 1,
6228 + ETHINTFC_its_m = 0x00000002,
6229 + ETHINTFC_rip_b = 2,
6230 + ETHINTFC_rip_m = 0x00000004,
6231 + ETHINTFC_jam_b = 3,
6232 + ETHINTFC_jam_m = 0x00000008,
6233 + ETHINTFC_ovr_b = 4,
6234 + ETHINTFC_ovr_m = 0x00000010,
6235 + ETHINTFC_und_b = 5,
6236 + ETHINTFC_und_m = 0x00000020,
6237 +
6238 + ETHFIFOTT_tth_b = 0,
6239 + ETHFIFOTT_tth_m = 0x0000007f,
6240 +
6241 + ETHARC_pro_b = 0,
6242 + ETHARC_pro_m = 0x00000001,
6243 + ETHARC_am_b = 1,
6244 + ETHARC_am_m = 0x00000002,
6245 + ETHARC_afm_b = 2,
6246 + ETHARC_afm_m = 0x00000004,
6247 + ETHARC_ab_b = 3,
6248 + ETHARC_ab_m = 0x00000008,
6249 +
6250 + ETHSAL_byte5_b = 0,
6251 + ETHSAL_byte5_m = 0x000000ff,
6252 + ETHSAL_byte4_b = 8,
6253 + ETHSAL_byte4_m = 0x0000ff00,
6254 + ETHSAL_byte3_b = 16,
6255 + ETHSAL_byte3_m = 0x00ff0000,
6256 + ETHSAL_byte2_b = 24,
6257 + ETHSAL_byte2_m = 0xff000000,
6258 +
6259 + ETHSAH_byte1_b = 0,
6260 + ETHSAH_byte1_m = 0x000000ff,
6261 + ETHSAH_byte0_b = 8,
6262 + ETHSAH_byte0_m = 0x0000ff00,
6263 +
6264 + ETHGPF_ptv_b = 0,
6265 + ETHGPF_ptv_m = 0x0000ffff,
6266 +
6267 + ETHPFS_pfd_b = 0,
6268 + ETHPFS_pfd_m = 0x00000001,
6269 +
6270 + ETHCFSA0_cfsa4_b = 0,
6271 + ETHCFSA0_cfsa4_m = 0x000000ff,
6272 + ETHCFSA0_cfsa5_b = 8,
6273 + ETHCFSA0_cfsa5_m = 0x0000ff00,
6274 +
6275 + ETHCFSA1_cfsa2_b = 0,
6276 + ETHCFSA1_cfsa2_m = 0x000000ff,
6277 + ETHCFSA1_cfsa3_b = 8,
6278 + ETHCFSA1_cfsa3_m = 0x0000ff00,
6279 +
6280 + ETHCFSA2_cfsa0_b = 0,
6281 + ETHCFSA2_cfsa0_m = 0x000000ff,
6282 + ETHCFSA2_cfsa1_b = 8,
6283 + ETHCFSA2_cfsa1_m = 0x0000ff00,
6284 +
6285 + ETHMAC1_re_b = 0,
6286 + ETHMAC1_re_m = 0x00000001,
6287 + ETHMAC1_paf_b = 1,
6288 + ETHMAC1_paf_m = 0x00000002,
6289 + ETHMAC1_rfc_b = 2,
6290 + ETHMAC1_rfc_m = 0x00000004,
6291 + ETHMAC1_tfc_b = 3,
6292 + ETHMAC1_tfc_m = 0x00000008,
6293 + ETHMAC1_lb_b = 4,
6294 + ETHMAC1_lb_m = 0x00000010,
6295 + ETHMAC1_mr_b = 31,
6296 + ETHMAC1_mr_m = 0x80000000,
6297 +
6298 + ETHMAC2_fd_b = 0,
6299 + ETHMAC2_fd_m = 0x00000001,
6300 + ETHMAC2_flc_b = 1,
6301 + ETHMAC2_flc_m = 0x00000002,
6302 + ETHMAC2_hfe_b = 2,
6303 + ETHMAC2_hfe_m = 0x00000004,
6304 + ETHMAC2_dc_b = 3,
6305 + ETHMAC2_dc_m = 0x00000008,
6306 + ETHMAC2_cen_b = 4,
6307 + ETHMAC2_cen_m = 0x00000010,
6308 + ETHMAC2_pe_b = 5,
6309 + ETHMAC2_pe_m = 0x00000020,
6310 + ETHMAC2_vpe_b = 6,
6311 + ETHMAC2_vpe_m = 0x00000040,
6312 + ETHMAC2_ape_b = 7,
6313 + ETHMAC2_ape_m = 0x00000080,
6314 + ETHMAC2_ppe_b = 8,
6315 + ETHMAC2_ppe_m = 0x00000100,
6316 + ETHMAC2_lpe_b = 9,
6317 + ETHMAC2_lpe_m = 0x00000200,
6318 + ETHMAC2_nb_b = 12,
6319 + ETHMAC2_nb_m = 0x00001000,
6320 + ETHMAC2_bp_b = 13,
6321 + ETHMAC2_bp_m = 0x00002000,
6322 + ETHMAC2_ed_b = 14,
6323 + ETHMAC2_ed_m = 0x00004000,
6324 +
6325 + ETHIPGT_ipgt_b = 0,
6326 + ETHIPGT_ipgt_m = 0x0000007f,
6327 +
6328 + ETHIPGR_ipgr2_b = 0,
6329 + ETHIPGR_ipgr2_m = 0x0000007f,
6330 + ETHIPGR_ipgr1_b = 8,
6331 + ETHIPGR_ipgr1_m = 0x00007f00,
6332 +
6333 + ETHCLRT_maxret_b = 0,
6334 + ETHCLRT_maxret_m = 0x0000000f,
6335 + ETHCLRT_colwin_b = 8,
6336 + ETHCLRT_colwin_m = 0x00003f00,
6337 +
6338 + ETHMAXF_maxf_b = 0,
6339 + ETHMAXF_maxf_m = 0x0000ffff,
6340 +
6341 + ETHMTEST_tb_b = 2,
6342 + ETHMTEST_tb_m = 0x00000004,
6343 +
6344 + ETHMCP_div_b = 0,
6345 + ETHMCP_div_m = 0x000000ff,
6346 +
6347 + MIIMCFG_rsv_b = 0,
6348 + MIIMCFG_rsv_m = 0x0000000c,
6349 +
6350 + MIIMCMD_rd_b = 0,
6351 + MIIMCMD_rd_m = 0x00000001,
6352 + MIIMCMD_scn_b = 1,
6353 + MIIMCMD_scn_m = 0x00000002,
6354 +
6355 + MIIMADDR_regaddr_b = 0,
6356 + MIIMADDR_regaddr_m = 0x0000001f,
6357 + MIIMADDR_phyaddr_b = 8,
6358 + MIIMADDR_phyaddr_m = 0x00001f00,
6359 +
6360 + MIIMWTD_wdata_b = 0,
6361 + MIIMWTD_wdata_m = 0x0000ffff,
6362 +
6363 + MIIMRDD_rdata_b = 0,
6364 + MIIMRDD_rdata_m = 0x0000ffff,
6365 +
6366 + MIIMIND_bsy_b = 0,
6367 + MIIMIND_bsy_m = 0x00000001,
6368 + MIIMIND_scn_b = 1,
6369 + MIIMIND_scn_m = 0x00000002,
6370 + MIIMIND_nv_b = 2,
6371 + MIIMIND_nv_m = 0x00000004,
6372 +
6373 +} ;
6374 +
6375 +/*
6376 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6377 + */
6378 +enum
6379 +{
6380 + ETHRX_fd_b = 0,
6381 + ETHRX_fd_m = 0x00000001,
6382 + ETHRX_ld_b = 1,
6383 + ETHRX_ld_m = 0x00000002,
6384 + ETHRX_rok_b = 2,
6385 + ETHRX_rok_m = 0x00000004,
6386 + ETHRX_fm_b = 3,
6387 + ETHRX_fm_m = 0x00000008,
6388 + ETHRX_mp_b = 4,
6389 + ETHRX_mp_m = 0x00000010,
6390 + ETHRX_bp_b = 5,
6391 + ETHRX_bp_m = 0x00000020,
6392 + ETHRX_vlt_b = 6,
6393 + ETHRX_vlt_m = 0x00000040,
6394 + ETHRX_cf_b = 7,
6395 + ETHRX_cf_m = 0x00000080,
6396 + ETHRX_ovr_b = 8,
6397 + ETHRX_ovr_m = 0x00000100,
6398 + ETHRX_crc_b = 9,
6399 + ETHRX_crc_m = 0x00000200,
6400 + ETHRX_cv_b = 10,
6401 + ETHRX_cv_m = 0x00000400,
6402 + ETHRX_db_b = 11,
6403 + ETHRX_db_m = 0x00000800,
6404 + ETHRX_le_b = 12,
6405 + ETHRX_le_m = 0x00001000,
6406 + ETHRX_lor_b = 13,
6407 + ETHRX_lor_m = 0x00002000,
6408 + ETHRX_ces_b = 14,
6409 + ETHRX_ces_m = 0x00004000,
6410 + ETHRX_length_b = 16,
6411 + ETHRX_length_m = 0xffff0000,
6412 +
6413 + ETHTX_fd_b = 0,
6414 + ETHTX_fd_m = 0x00000001,
6415 + ETHTX_ld_b = 1,
6416 + ETHTX_ld_m = 0x00000002,
6417 + ETHTX_oen_b = 2,
6418 + ETHTX_oen_m = 0x00000004,
6419 + ETHTX_pen_b = 3,
6420 + ETHTX_pen_m = 0x00000008,
6421 + ETHTX_cen_b = 4,
6422 + ETHTX_cen_m = 0x00000010,
6423 + ETHTX_hen_b = 5,
6424 + ETHTX_hen_m = 0x00000020,
6425 + ETHTX_tok_b = 6,
6426 + ETHTX_tok_m = 0x00000040,
6427 + ETHTX_mp_b = 7,
6428 + ETHTX_mp_m = 0x00000080,
6429 + ETHTX_bp_b = 8,
6430 + ETHTX_bp_m = 0x00000100,
6431 + ETHTX_und_b = 9,
6432 + ETHTX_und_m = 0x00000200,
6433 + ETHTX_of_b = 10,
6434 + ETHTX_of_m = 0x00000400,
6435 + ETHTX_ed_b = 11,
6436 + ETHTX_ed_m = 0x00000800,
6437 + ETHTX_ec_b = 12,
6438 + ETHTX_ec_m = 0x00001000,
6439 + ETHTX_lc_b = 13,
6440 + ETHTX_lc_m = 0x00002000,
6441 + ETHTX_td_b = 14,
6442 + ETHTX_td_m = 0x00004000,
6443 + ETHTX_crc_b = 15,
6444 + ETHTX_crc_m = 0x00008000,
6445 + ETHTX_le_b = 16,
6446 + ETHTX_le_m = 0x00010000,
6447 + ETHTX_cc_b = 17,
6448 + ETHTX_cc_m = 0x001E0000,
6449 +} ;
6450 +
6451 +#endif // __IDT_ETH_H__
6452 +
6453 +
6454 +
6455 +
6456 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6457 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 1970-01-01 01:00:00.000000000 +0100
6458 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 2006-03-20 14:25:10.000000000 +0100
6459 @@ -0,0 +1,77 @@
6460 +/**************************************************************************
6461 + *
6462 + * BRIEF MODULE DESCRIPTION
6463 + * Ethernet register definition
6464 + *
6465 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6466 + *
6467 + * This program is free software; you can redistribute it and/or modify it
6468 + * under the terms of the GNU General Public License as published by the
6469 + * Free Software Foundation; either version 2 of the License, or (at your
6470 + * option) any later version.
6471 + *
6472 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6473 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6474 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6475 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6476 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6477 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6478 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6479 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6480 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6481 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6482 + *
6483 + * You should have received a copy of the GNU General Public License along
6484 + * with this program; if not, write to the Free Software Foundation, Inc.,
6485 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6486 + *
6487 + *
6488 + **************************************************************************
6489 + * May 2004 rkt, neb.
6490 + *
6491 + * Initial Release
6492 + *
6493 + *
6494 + *
6495 + **************************************************************************
6496 + */
6497 +
6498 +#ifndef __IDT_ETH_V_H__
6499 +#define __IDT_ETH_V_H__
6500 +
6501 +#include <asm/idt-boards/rc32434/rc32434_eth.h>
6502 +
6503 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
6504 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
6505 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
6506 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
6507 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
6508 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
6509 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
6510 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
6511 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
6512 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
6513 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
6514 +
6515 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
6516 +
6517 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
6518 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
6519 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
6520 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
6521 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
6522 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
6523 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
6524 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
6525 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
6526 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
6527 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
6528 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
6529 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
6530 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
6531 +#endif // __IDT_ETH_V_H__
6532 +
6533 +
6534 +
6535 +
6536 +
6537 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6538 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 1970-01-01 01:00:00.000000000 +0100
6539 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 2006-03-20 14:25:10.000000000 +0100
6540 @@ -0,0 +1,167 @@
6541 +/**************************************************************************
6542 + *
6543 + * BRIEF MODULE DESCRIPTION
6544 + * GPIO register definition
6545 + *
6546 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6547 + *
6548 + * This program is free software; you can redistribute it and/or modify it
6549 + * under the terms of the GNU General Public License as published by the
6550 + * Free Software Foundation; either version 2 of the License, or (at your
6551 + * option) any later version.
6552 + *
6553 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6554 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6555 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6556 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6557 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6558 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6559 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6560 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6561 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6562 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6563 + *
6564 + * You should have received a copy of the GNU General Public License along
6565 + * with this program; if not, write to the Free Software Foundation, Inc.,
6566 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6567 + *
6568 + *
6569 + **************************************************************************
6570 + * May 2004 rkt, neb.
6571 + *
6572 + * Initial Release
6573 + *
6574 + *
6575 + *
6576 + **************************************************************************
6577 + */
6578 +
6579 +#ifndef __IDT_GPIO_H__
6580 +#define __IDT_GPIO_H__
6581 +
6582 +enum
6583 +{
6584 + GPIO0_PhysicalAddress = 0x18050000,
6585 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
6586 +
6587 + GPIO0_VirtualAddress = 0xb8050000,
6588 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
6589 +} ;
6590 +
6591 +typedef struct
6592 +{
6593 + u32 gpiofunc; /* GPIO Function Register
6594 + * gpiofunc[x]==0 bit = gpio
6595 + * func[x]==1 bit = altfunc
6596 + */
6597 + u32 gpiocfg; /* GPIO Configuration Register
6598 + * gpiocfg[x]==0 bit = input
6599 + * gpiocfg[x]==1 bit = output
6600 + */
6601 + u32 gpiod; /* GPIO Data Register
6602 + * gpiod[x] read/write gpio pinX status
6603 + */
6604 + u32 gpioilevel; /* GPIO Interrupt Status Register
6605 + * interrupt level (see gpioistat)
6606 + */
6607 + u32 gpioistat; /* Gpio Interrupt Status Register
6608 + * istat[x] = (gpiod[x] == level[x])
6609 + * cleared in ISR (STICKY bits)
6610 + */
6611 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
6612 +} volatile * GPIO_t ;
6613 +
6614 +typedef enum
6615 +{
6616 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
6617 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
6618 + GPIO_input_v = 0, // gpiocfg use pin as input.
6619 + GPIO_output_v = 1, // gpiocfg use pin as output.
6620 + GPIO_pin0_b = 0,
6621 + GPIO_pin0_m = 0x00000001,
6622 + GPIO_pin1_b = 1,
6623 + GPIO_pin1_m = 0x00000002,
6624 + GPIO_pin2_b = 2,
6625 + GPIO_pin2_m = 0x00000004,
6626 + GPIO_pin3_b = 3,
6627 + GPIO_pin3_m = 0x00000008,
6628 + GPIO_pin4_b = 4,
6629 + GPIO_pin4_m = 0x00000010,
6630 + GPIO_pin5_b = 5,
6631 + GPIO_pin5_m = 0x00000020,
6632 + GPIO_pin6_b = 6,
6633 + GPIO_pin6_m = 0x00000040,
6634 + GPIO_pin7_b = 7,
6635 + GPIO_pin7_m = 0x00000080,
6636 + GPIO_pin8_b = 8,
6637 + GPIO_pin8_m = 0x00000100,
6638 + GPIO_pin9_b = 9,
6639 + GPIO_pin9_m = 0x00000200,
6640 + GPIO_pin10_b = 10,
6641 + GPIO_pin10_m = 0x00000400,
6642 + GPIO_pin11_b = 11,
6643 + GPIO_pin11_m = 0x00000800,
6644 + GPIO_pin12_b = 12,
6645 + GPIO_pin12_m = 0x00001000,
6646 + GPIO_pin13_b = 13,
6647 + GPIO_pin13_m = 0x00002000,
6648 +
6649 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
6650 +
6651 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
6652 + GPIO_u0sout_m = GPIO_pin0_m,
6653 + GPIO_u0sout_cfg_v = GPIO_output_v,
6654 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
6655 + GPIO_u0sinp_m = GPIO_pin1_m,
6656 + GPIO_u0sinp_cfg_v = GPIO_input_v,
6657 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
6658 + GPIO_u0rtsn_m = GPIO_pin2_m,
6659 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
6660 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
6661 + GPIO_u0ctsn_m = GPIO_pin3_m,
6662 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
6663 +
6664 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
6665 + GPIO_maddr22_m = GPIO_pin4_m,
6666 + GPIO_maddr22_cfg_v = GPIO_output_v,
6667 +
6668 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
6669 + GPIO_maddr23_m = GPIO_pin5_m,
6670 + GPIO_maddr23_cfg_v = GPIO_output_v,
6671 +
6672 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
6673 + GPIO_maddr24_m = GPIO_pin6_m,
6674 + GPIO_maddr24_cfg_v = GPIO_output_v,
6675 +
6676 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
6677 + GPIO_maddr25_m = GPIO_pin7_m,
6678 + GPIO_maddr25_cfg_v = GPIO_output_v,
6679 +
6680 + GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
6681 + GPIO_cpudmadebug_m = GPIO_pin8_m,
6682 + GPIO_cpudmadebug_cfg_v = GPIO_output_v,
6683 +
6684 + GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
6685 + GPIO_pcireq4_m = GPIO_pin9_m,
6686 + GPIO_pcireq4_cfg_v = GPIO_input_v,
6687 +
6688 + GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
6689 + GPIO_pcigrant4_m = GPIO_pin10_m,
6690 + GPIO_pcigrant4_cfg_v = GPIO_output_v,
6691 +
6692 + GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
6693 + GPIO_pcireq5_m = GPIO_pin11_m,
6694 + GPIO_pcireq5_cfg_v = GPIO_input_v,
6695 +
6696 + GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
6697 + GPIO_pcigrant5_m = GPIO_pin12_m,
6698 + GPIO_pcigrant5_cfg_v = GPIO_output_v,
6699 +
6700 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
6701 + GPIO_pcimuintn_m = GPIO_pin13_m,
6702 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
6703 +
6704 +} GPIO_DEFS_t;
6705 +
6706 +#endif // __IDT_GPIO_H__
6707 +
6708 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6709 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
6710 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h 2006-03-20 14:25:10.000000000 +0100
6711 @@ -0,0 +1,199 @@
6712 + /**************************************************************************
6713 + *
6714 + * BRIEF MODULE DESCRIPTION
6715 + * Definitions for IDT RC32434 CPU
6716 + *
6717 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6718 + *
6719 + * This program is free software; you can redistribute it and/or modify it
6720 + * under the terms of the GNU General Public License as published by the
6721 + * Free Software Foundation; either version 2 of the License, or (at your
6722 + * option) any later version.
6723 + *
6724 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6725 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6726 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6727 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6728 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6729 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6730 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6731 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6732 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6733 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6734 + *
6735 + * You should have received a copy of the GNU General Public License along
6736 + * with this program; if not, write to the Free Software Foundation, Inc.,
6737 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6738 + *
6739 + *
6740 + **************************************************************************
6741 + * May 2004 rkt, neb.
6742 + *
6743 + * Initial Release
6744 + *
6745 + *
6746 + *
6747 + **************************************************************************
6748 + */
6749 +
6750 +#ifndef _RC32434_H_
6751 +#define _RC32434_H_
6752 +
6753 +#include <linux/config.h>
6754 +#include <linux/delay.h>
6755 +#include <asm/io.h>
6756 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6757 +
6758 +#define RC32434_REG_BASE 0x18000000
6759 +
6760 +
6761 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6762 +#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
6763 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
6764 +
6765 +#define IDT_CLOCK_MULT 2
6766 +#define MIPS_CPU_TIMER_IRQ 7
6767 +/* Interrupt Controller */
6768 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
6769 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
6770 +#define IC_GROUP_OFFSET 0x0C
6771 +#define RTC_BASE 0xBA001FF0
6772 +
6773 +#define NUM_INTR_GROUPS 5
6774 +/* 16550 UARTs */
6775 +
6776 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
6777 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6778 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6779 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6780 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6781 +
6782 +#ifdef __MIPSEB__
6783 +
6784 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6785 +#define EB434_UART1_BASE (0x19800003)
6786 +
6787 +#else
6788 +
6789 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6790 +#define EB434_UART1_BASE (0x19800000)
6791 +
6792 +#endif
6793 +
6794 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
6795 +#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
6796 +
6797 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
6798 +
6799 +/* cpu pipeline flush */
6800 +static inline void rc32434_sync(void)
6801 +{
6802 + __asm__ volatile ("sync");
6803 +}
6804 +
6805 +static inline void rc32434_sync_udelay(int us)
6806 +{
6807 + __asm__ volatile ("sync");
6808 + udelay(us);
6809 +}
6810 +
6811 +static inline void rc32434_sync_delay(int ms)
6812 +{
6813 + __asm__ volatile ("sync");
6814 + mdelay(ms);
6815 +}
6816 +
6817 +
6818 +
6819 +/*
6820 + * Macros to access internal RC32434 registers. No byte
6821 + * swapping should be done when accessing the internal
6822 + * registers.
6823 + */
6824 +
6825 +#define rc32434_readb __raw_readb
6826 +#define rc32434_readw __raw_readw
6827 +#define rc32434_readl __raw_readl
6828 +
6829 +#define rc32434_writeb __raw_writeb
6830 +#define rc32434_writew __raw_writew
6831 +#define rc32434_writel __raw_writel
6832 +
6833 +#if 0
6834 +static inline u8 rc32434_readb(unsigned long pa)
6835 +{
6836 + return *((volatile u8 *)KSEG1ADDR(pa));
6837 +}
6838 +static inline u16 rc32434_readw(unsigned long pa)
6839 +{
6840 + return *((volatile u16 *)KSEG1ADDR(pa));
6841 +}
6842 +static inline u32 rc32434_readl(unsigned long pa)
6843 +{
6844 + return *((volatile u32 *)KSEG1ADDR(pa));
6845 +}
6846 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6847 +{
6848 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
6849 +}
6850 +static inline void rc32434_writew(u16 val, unsigned long pa)
6851 +{
6852 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
6853 +}
6854 +static inline void rc32434_writel(u32 val, unsigned long pa)
6855 +{
6856 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
6857 +}
6858 +
6859 +#endif
6860 +
6861 +
6862 +/*
6863 + * C access to CLZ and CLO instructions
6864 + * (count leading zeroes/ones).
6865 + */
6866 +static inline int rc32434_clz(unsigned long val)
6867 +{
6868 + int ret;
6869 + __asm__ volatile (
6870 + ".set\tnoreorder\n\t"
6871 + ".set\tnoat\n\t"
6872 + ".set\tmips32\n\t"
6873 + "clz\t%0,%1\n\t"
6874 + ".set\tmips0\n\t"
6875 + ".set\tat\n\t"
6876 + ".set\treorder"
6877 + : "=r" (ret)
6878 + : "r" (val));
6879 +
6880 + return ret;
6881 +}
6882 +static inline int rc32434_clo(unsigned long val)
6883 +{
6884 + int ret;
6885 + __asm__ volatile (
6886 + ".set\tnoreorder\n\t"
6887 + ".set\tnoat\n\t"
6888 + ".set\tmips32\n\t"
6889 + "clo\t%0,%1\n\t"
6890 + ".set\tmips0\n\t"
6891 + ".set\tat\n\t"
6892 + ".set\treorder"
6893 + : "=r" (ret)
6894 + : "r" (val));
6895 +
6896 + return ret;
6897 +}
6898 +#endif /* _RC32434_H_ */
6899 +
6900 +
6901 +
6902 +
6903 +
6904 +
6905 +
6906 +
6907 +
6908 +
6909 +
6910 +
6911 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6912 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 1970-01-01 01:00:00.000000000 +0100
6913 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 2006-03-20 14:25:10.000000000 +0100
6914 @@ -0,0 +1,90 @@
6915 +/**************************************************************************
6916 + *
6917 + * BRIEF MODULE DESCRIPTION
6918 + * System Integrity register definition
6919 + *
6920 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6921 + *
6922 + * This program is free software; you can redistribute it and/or modify it
6923 + * under the terms of the GNU General Public License as published by the
6924 + * Free Software Foundation; either version 2 of the License, or (at your
6925 + * option) any later version.
6926 + *
6927 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6928 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6929 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6930 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6931 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6932 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6933 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6934 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6935 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6936 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6937 + *
6938 + * You should have received a copy of the GNU General Public License along
6939 + * with this program; if not, write to the Free Software Foundation, Inc.,
6940 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6941 + *
6942 + *
6943 + **************************************************************************
6944 + * May 2004 rkt, neb
6945 + *
6946 + * Initial Release
6947 + *
6948 + *
6949 + *
6950 + **************************************************************************
6951 + */
6952 +
6953 +#ifndef __IDT_INTEG_H__
6954 +#define __IDT_INTEG_H__
6955 +
6956 +enum
6957 +{
6958 + INTEG0_PhysicalAddress = 0x18030000,
6959 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
6960 +
6961 + INTEG0_VirtualAddress = 0xB8030000,
6962 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
6963 +} ;
6964 +
6965 +// if you are looking for CEA, try rst.h
6966 +typedef struct
6967 +{
6968 + u32 filler [0xc] ; // 0x30 bytes unused.
6969 + u32 errcs ; // sticky use ERRCS_
6970 + u32 wtcount ; // Watchdog timer count reg.
6971 + u32 wtcompare ; // Watchdog timer timeout value.
6972 + u32 wtc ; // Watchdog timer control. use WTC_
6973 +} volatile *INTEG_t ;
6974 +
6975 +enum
6976 +{
6977 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
6978 + ERRCS_wto_m = 0x00000001,
6979 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
6980 + ERRCS_wne_m = 0x00000002,
6981 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
6982 + ERRCS_ucw_m = 0x00000004,
6983 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
6984 + ERRCS_ucr_m = 0x00000008,
6985 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
6986 + ERRCS_upw_m = 0x00000010,
6987 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
6988 + ERRCS_upr_m = 0x00000020,
6989 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
6990 + ERRCS_udw_m = 0x00000040,
6991 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
6992 + ERRCS_udr_m = 0x00000080,
6993 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
6994 + ERRCS_sae_m = 0x00000100,
6995 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
6996 + ERRCS_wre_m = 0x00000200,
6997 +
6998 + WTC_en_b = 0, // In INTEG_t -> wtc
6999 + WTC_en_m = 0x00000001,
7000 + WTC_to_b = 1, // In INTEG_t -> wtc
7001 + WTC_to_m = 0x00000002,
7002 +} ;
7003 +
7004 +#endif // __IDT_INTEG_H__
7005 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
7006 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_int.h 1970-01-01 01:00:00.000000000 +0100
7007 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-03-20 14:25:10.000000000 +0100
7008 @@ -0,0 +1,174 @@
7009 +/**************************************************************************
7010 + *
7011 + * BRIEF MODULE DESCRIPTION
7012 + * Interrupt Controller register definition.
7013 + *
7014 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7015 + *
7016 + * This program is free software; you can redistribute it and/or modify it
7017 + * under the terms of the GNU General Public License as published by the
7018 + * Free Software Foundation; either version 2 of the License, or (at your
7019 + * option) any later version.
7020 + *
7021 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7022 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7023 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7024 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7025 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7026 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7027 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7028 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7029 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7030 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7031 + *
7032 + * You should have received a copy of the GNU General Public License along
7033 + * with this program; if not, write to the Free Software Foundation, Inc.,
7034 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7035 + *
7036 + *
7037 + **************************************************************************
7038 + * May 2004 rkt, neb.
7039 + *
7040 + * Initial Release
7041 + *
7042 + *
7043 + *
7044 + **************************************************************************
7045 + */
7046 +
7047 +#ifndef __IDT_INT_H__
7048 +#define __IDT_INT_H__
7049 +
7050 +enum
7051 +{
7052 + INT0_PhysicalAddress = 0x18038000,
7053 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
7054 +
7055 + INT0_VirtualAddress = 0xB8038000,
7056 + INT_VirtualAddress = INT0_VirtualAddress, // Default
7057 +} ;
7058 +
7059 +struct INT_s
7060 +{
7061 + u32 ipend ; //Pending interrupts. use INT?_
7062 + u32 itest ; //Test bits. use INT?_
7063 + u32 imask ; //Interrupt disabled when set. use INT?_
7064 +} ;
7065 +
7066 +enum
7067 +{
7068 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
7069 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
7070 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
7071 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
7072 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
7073 +
7074 + IPEND_count, // must be last (used in loops)
7075 + IPEND_min = IPEND2 // min IPEND (used in loops)
7076 +};
7077 +
7078 +typedef struct INTC_s
7079 +{
7080 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
7081 + u32 nmips ; // use NMIPS_
7082 +} volatile *INT_t ;
7083 +
7084 +enum
7085 +{
7086 + INT2_timer0_b = 0,
7087 + INT2_timer0_m = 0x00000001,
7088 + INT2_timer1_b = 1,
7089 + INT2_timer1_m = 0x00000002,
7090 + INT2_timer2_b = 2,
7091 + INT2_timer2_m = 0x00000004,
7092 + INT2_refresh_b = 3,
7093 + INT2_refresh_m = 0x00000008,
7094 + INT2_watchdogTimeout_b = 4,
7095 + INT2_watchdogTimeout_m = 0x00000010,
7096 + INT2_undecodedCpuWrite_b = 5,
7097 + INT2_undecodedCpuWrite_m = 0x00000020,
7098 + INT2_undecodedCpuRead_b = 6,
7099 + INT2_undecodedCpuRead_m = 0x00000040,
7100 + INT2_undecodedPciWrite_b = 7,
7101 + INT2_undecodedPciWrite_m = 0x00000080,
7102 + INT2_undecodedPciRead_b = 8,
7103 + INT2_undecodedPciRead_m = 0x00000100,
7104 + INT2_undecodedDmaWrite_b = 9,
7105 + INT2_undecodedDmaWrite_m = 0x00000200,
7106 + INT2_undecodedDmaRead_b = 10,
7107 + INT2_undecodedDmaRead_m = 0x00000400,
7108 + INT2_ipBusSlaveAckError_b = 11,
7109 + INT2_ipBusSlaveAckError_m = 0x00000800,
7110 +
7111 + INT3_dmaChannel0_b = 0,
7112 + INT3_dmaChannel0_m = 0x00000001,
7113 + INT3_dmaChannel1_b = 1,
7114 + INT3_dmaChannel1_m = 0x00000002,
7115 + INT3_dmaChannel2_b = 2,
7116 + INT3_dmaChannel2_m = 0x00000004,
7117 + INT3_dmaChannel3_b = 3,
7118 + INT3_dmaChannel3_m = 0x00000008,
7119 + INT3_dmaChannel4_b = 4,
7120 + INT3_dmaChannel4_m = 0x00000010,
7121 + INT3_dmaChannel5_b = 5,
7122 + INT3_dmaChannel5_m = 0x00000020,
7123 +
7124 + INT5_uartGeneral0_b = 0,
7125 + INT5_uartGeneral0_m = 0x00000001,
7126 + INT5_uartTxrdy0_b = 1,
7127 + INT5_uartTxrdy0_m = 0x00000002,
7128 + INT5_uartRxrdy0_b = 2,
7129 + INT5_uartRxrdy0_m = 0x00000004,
7130 + INT5_pci_b = 3,
7131 + INT5_pci_m = 0x00000008,
7132 + INT5_pciDecoupled_b = 4,
7133 + INT5_pciDecoupled_m = 0x00000010,
7134 + INT5_spi_b = 5,
7135 + INT5_spi_m = 0x00000020,
7136 + INT5_deviceDecoupled_b = 6,
7137 + INT5_deviceDecoupled_m = 0x00000040,
7138 + INT5_eth0Ovr_b = 9,
7139 + INT5_eth0Ovr_m = 0x00000200,
7140 + INT5_eth0Und_b = 10,
7141 + INT5_eth0Und_m = 0x00000400,
7142 + INT5_eth0Pfd_b = 11,
7143 + INT5_eth0Pfd_m = 0x00000800,
7144 + INT5_nvram_b = 12,
7145 + INT5_nvram_m = 0x00001000,
7146 +
7147 + INT6_gpio0_b = 0,
7148 + INT6_gpio0_m = 0x00000001,
7149 + INT6_gpio1_b = 1,
7150 + INT6_gpio1_m = 0x00000002,
7151 + INT6_gpio2_b = 2,
7152 + INT6_gpio2_m = 0x00000004,
7153 + INT6_gpio3_b = 3,
7154 + INT6_gpio3_m = 0x00000008,
7155 + INT6_gpio4_b = 4,
7156 + INT6_gpio4_m = 0x00000010,
7157 + INT6_gpio5_b = 5,
7158 + INT6_gpio5_m = 0x00000020,
7159 + INT6_gpio6_b = 6,
7160 + INT6_gpio6_m = 0x00000040,
7161 + INT6_gpio7_b = 7,
7162 + INT6_gpio7_m = 0x00000080,
7163 + INT6_gpio8_b = 8,
7164 + INT6_gpio8_m = 0x00000100,
7165 + INT6_gpio9_b = 9,
7166 + INT6_gpio9_m = 0x00000200,
7167 + INT6_gpio10_b = 10,
7168 + INT6_gpio10_m = 0x00000400,
7169 + INT6_gpio11_b = 11,
7170 + INT6_gpio11_m = 0x00000800,
7171 + INT6_gpio12_b = 12,
7172 + INT6_gpio12_m = 0x00001000,
7173 + INT6_gpio13_b = 13,
7174 + INT6_gpio13_m = 0x00002000,
7175 +
7176 + NMIPS_gpio_b = 0,
7177 + NMIPS_gpio_m = 0x00000001,
7178 +} ;
7179 +
7180 +#endif // __IDT_INT_H__
7181 +
7182 +
7183 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7184 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 1970-01-01 01:00:00.000000000 +0100
7185 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 2006-03-20 14:25:10.000000000 +0100
7186 @@ -0,0 +1,111 @@
7187 +/**************************************************************************
7188 + *
7189 + * BRIEF MODULE DESCRIPTION
7190 + * IP Arbiter register definitions
7191 + *
7192 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7193 + *
7194 + * This program is free software; you can redistribute it and/or modify it
7195 + * under the terms of the GNU General Public License as published by the
7196 + * Free Software Foundation; either version 2 of the License, or (at your
7197 + * option) any later version.
7198 + *
7199 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7200 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7201 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7202 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7203 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7204 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7205 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7206 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7207 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7208 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7209 + *
7210 + * You should have received a copy of the GNU General Public License along
7211 + * with this program; if not, write to the Free Software Foundation, Inc.,
7212 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7213 + *
7214 + *
7215 + **************************************************************************
7216 + * May 2004 rkt,neb
7217 + *
7218 + * Initial Release
7219 + *
7220 + *
7221 + *
7222 + **************************************************************************
7223 + */
7224 +
7225 +#ifndef __IDT_IPARB_H__
7226 +#define __IDT_IPARB_H__
7227 +
7228 +enum
7229 +{
7230 + IPARB0_PhysicalAddress = 0x18048000,
7231 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
7232 +
7233 + IPARB0_VirtualAddress = 0xB8048000,
7234 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
7235 +} ;
7236 +
7237 +enum
7238 +{
7239 + IPABMXC_ethernet0Receive = 0,
7240 + IPABMXC_ethernet0Transmit = 1,
7241 + IPABMXC_memoryToHoldFifo = 2,
7242 + IPABMXC_holdFifoToMemory = 3,
7243 + IPABMXC_pciToMemory = 4,
7244 + IPABMXC_memoryToPci = 5,
7245 + IPABMXC_pciTarget = 6,
7246 + IPABMXC_pciTargetStart = 7,
7247 + IPABMXC_cpuToIpBus = 8,
7248 +
7249 + IPABMXC_Count, // Must be last in list !
7250 + IPABMXC_Min = IPABMXC_ethernet0Receive,
7251 +
7252 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
7253 +} ;
7254 +
7255 +typedef struct
7256 +{
7257 + u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
7258 + u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
7259 + u32 ipac ; // use IPAC_
7260 + u32 ipaitcc; // use IPAITCC_
7261 + u32 ipaspare ;
7262 +} volatile * IPARB_t ;
7263 +
7264 +enum
7265 +{
7266 + IPAC_dp_b = 0,
7267 + IPAC_dp_m = 0x00000001,
7268 + IPAC_dep_b = 1,
7269 + IPAC_dep_m = 0x00000002,
7270 + IPAC_drm_b = 2,
7271 + IPAC_drm_m = 0x00000004,
7272 + IPAC_dwm_b = 3,
7273 + IPAC_dwm_m = 0x00000008,
7274 + IPAC_msk_b = 4,
7275 + IPAC_msk_m = 0x00000010,
7276 +
7277 + IPAPC_ptc_b = 0,
7278 + IPAPC_ptc_m = 0x00003fff,
7279 + IPAPC_mf_b = 14,
7280 + IPAPC_mf_m = 0x00004000,
7281 + IPAPC_cptc_b = 16,
7282 + IPAPC_cptc_m = 0x3fff0000,
7283 +
7284 + IPAITCC_itcc = 0,
7285 + IPAITCC_itcc, = 0x000001ff,
7286 +
7287 + IPABMC_mtc_b = 0,
7288 + IPABMC_mtc_m = 0x00000fff,
7289 + IPABMC_p_b = 12,
7290 + IPABMC_p_m = 0x00003000,
7291 + IPABMC_msk_b = 14,
7292 + IPABMC_msk_m = 0x00004000,
7293 + IPABMC_cmtc_b = 16,
7294 + IPABMC_cmtc_m = 0x0fff0000,
7295 +};
7296 +
7297 +#endif // __IDT_IPARB_H__
7298 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7299 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 1970-01-01 01:00:00.000000000 +0100
7300 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-03-20 14:25:10.000000000 +0100
7301 @@ -0,0 +1,695 @@
7302 +/**************************************************************************
7303 + *
7304 + * BRIEF MODULE DESCRIPTION
7305 + * PCI register definitio
7306 + *
7307 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7308 + *
7309 + * This program is free software; you can redistribute it and/or modify it
7310 + * under the terms of the GNU General Public License as published by the
7311 + * Free Software Foundation; either version 2 of the License, or (at your
7312 + * option) any later version.
7313 + *
7314 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7315 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7316 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7317 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7318 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7319 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7320 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7321 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7322 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7323 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7324 + *
7325 + * You should have received a copy of the GNU General Public License along
7326 + * with this program; if not, write to the Free Software Foundation, Inc.,
7327 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7328 + *
7329 + *
7330 + **************************************************************************
7331 + * May 2004 rkt, neb.
7332 + *
7333 + * Initial Release
7334 + *
7335 + *
7336 + *
7337 + **************************************************************************
7338 + */
7339 +
7340 +#ifndef __IDT_PCI_H__
7341 +#define __IDT_PCI_H__
7342 +
7343 +enum
7344 +{
7345 + PCI0_PhysicalAddress = 0x18080000,
7346 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
7347 +
7348 + PCI0_VirtualAddress = 0xB8080000,
7349 + PCI_VirtualAddress = PCI0_VirtualAddress,
7350 +} ;
7351 +
7352 +enum
7353 +{
7354 + PCI_LbaCount = 4, // Local base addresses.
7355 +} ;
7356 +
7357 +typedef struct
7358 +{
7359 + u32 a ; // Address.
7360 + u32 c ; // Control.
7361 + u32 m ; // mapping.
7362 +} PCI_Map_s ;
7363 +
7364 +typedef struct
7365 +{
7366 + u32 pcic ;
7367 + u32 pcis ;
7368 + u32 pcism ;
7369 + u32 pcicfga ;
7370 + u32 pcicfgd ;
7371 + PCI_Map_s pcilba [PCI_LbaCount] ;
7372 + u32 pcidac ;
7373 + u32 pcidas ;
7374 + u32 pcidasm ;
7375 + u32 pcidad ;
7376 + u32 pcidma8c ;
7377 + u32 pcidma9c ;
7378 + u32 pcitc ;
7379 +} volatile *PCI_t ;
7380 +
7381 +// PCI messaging unit.
7382 +enum
7383 +{
7384 + PCIM_Count = 2,
7385 +} ;
7386 +typedef struct
7387 +{
7388 + u32 pciim [PCIM_Count] ;
7389 + u32 pciom [PCIM_Count] ;
7390 + u32 pciid ;
7391 + u32 pciiic ;
7392 + u32 pciiim ;
7393 + u32 pciiod ;
7394 + u32 pciioic ;
7395 + u32 pciioim ;
7396 +} volatile *PCIM_t ;
7397 +
7398 +/*******************************************************************************
7399 + *
7400 + * PCI Control Register
7401 + *
7402 + ******************************************************************************/
7403 +enum
7404 +{
7405 + PCIC_en_b = 0,
7406 + PCIC_en_m = 0x00000001,
7407 + PCIC_tnr_b = 1,
7408 + PCIC_tnr_m = 0x00000002,
7409 + PCIC_sce_b = 2,
7410 + PCIC_sce_m = 0x00000004,
7411 + PCIC_ien_b = 3,
7412 + PCIC_ien_m = 0x00000008,
7413 + PCIC_aaa_b = 4,
7414 + PCIC_aaa_m = 0x00000010,
7415 + PCIC_eap_b = 5,
7416 + PCIC_eap_m = 0x00000020,
7417 + PCIC_pcim_b = 6,
7418 + PCIC_pcim_m = 0x000001c0,
7419 + PCIC_pcim_disabled_v = 0,
7420 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
7421 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
7422 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
7423 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
7424 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
7425 + PCIC_pcim_reserved6_v = 6,
7426 + PCIC_pcim_reserved7_v = 7,
7427 + PCIC_igm_b = 9,
7428 + PCIC_igm_m = 0x00000200,
7429 +} ;
7430 +
7431 +/*******************************************************************************
7432 + *
7433 + * PCI Status Register
7434 + *
7435 + ******************************************************************************/
7436 +enum {
7437 + PCIS_eed_b = 0,
7438 + PCIS_eed_m = 0x00000001,
7439 + PCIS_wr_b = 1,
7440 + PCIS_wr_m = 0x00000002,
7441 + PCIS_nmi_b = 2,
7442 + PCIS_nmi_m = 0x00000004,
7443 + PCIS_ii_b = 3,
7444 + PCIS_ii_m = 0x00000008,
7445 + PCIS_cwe_b = 4,
7446 + PCIS_cwe_m = 0x00000010,
7447 + PCIS_cre_b = 5,
7448 + PCIS_cre_m = 0x00000020,
7449 + PCIS_mdpe_b = 6,
7450 + PCIS_mdpe_m = 0x00000040,
7451 + PCIS_sta_b = 7,
7452 + PCIS_sta_m = 0x00000080,
7453 + PCIS_rta_b = 8,
7454 + PCIS_rta_m = 0x00000100,
7455 + PCIS_rma_b = 9,
7456 + PCIS_rma_m = 0x00000200,
7457 + PCIS_sse_b = 10,
7458 + PCIS_sse_m = 0x00000400,
7459 + PCIS_ose_b = 11,
7460 + PCIS_ose_m = 0x00000800,
7461 + PCIS_pe_b = 12,
7462 + PCIS_pe_m = 0x00001000,
7463 + PCIS_tae_b = 13,
7464 + PCIS_tae_m = 0x00002000,
7465 + PCIS_rle_b = 14,
7466 + PCIS_rle_m = 0x00004000,
7467 + PCIS_bme_b = 15,
7468 + PCIS_bme_m = 0x00008000,
7469 + PCIS_prd_b = 16,
7470 + PCIS_prd_m = 0x00010000,
7471 + PCIS_rip_b = 17,
7472 + PCIS_rip_m = 0x00020000,
7473 +} ;
7474 +
7475 +/*******************************************************************************
7476 + *
7477 + * PCI Status Mask Register
7478 + *
7479 + ******************************************************************************/
7480 +enum {
7481 + PCISM_eed_b = 0,
7482 + PCISM_eed_m = 0x00000001,
7483 + PCISM_wr_b = 1,
7484 + PCISM_wr_m = 0x00000002,
7485 + PCISM_nmi_b = 2,
7486 + PCISM_nmi_m = 0x00000004,
7487 + PCISM_ii_b = 3,
7488 + PCISM_ii_m = 0x00000008,
7489 + PCISM_cwe_b = 4,
7490 + PCISM_cwe_m = 0x00000010,
7491 + PCISM_cre_b = 5,
7492 + PCISM_cre_m = 0x00000020,
7493 + PCISM_mdpe_b = 6,
7494 + PCISM_mdpe_m = 0x00000040,
7495 + PCISM_sta_b = 7,
7496 + PCISM_sta_m = 0x00000080,
7497 + PCISM_rta_b = 8,
7498 + PCISM_rta_m = 0x00000100,
7499 + PCISM_rma_b = 9,
7500 + PCISM_rma_m = 0x00000200,
7501 + PCISM_sse_b = 10,
7502 + PCISM_sse_m = 0x00000400,
7503 + PCISM_ose_b = 11,
7504 + PCISM_ose_m = 0x00000800,
7505 + PCISM_pe_b = 12,
7506 + PCISM_pe_m = 0x00001000,
7507 + PCISM_tae_b = 13,
7508 + PCISM_tae_m = 0x00002000,
7509 + PCISM_rle_b = 14,
7510 + PCISM_rle_m = 0x00004000,
7511 + PCISM_bme_b = 15,
7512 + PCISM_bme_m = 0x00008000,
7513 + PCISM_prd_b = 16,
7514 + PCISM_prd_m = 0x00010000,
7515 + PCISM_rip_b = 17,
7516 + PCISM_rip_m = 0x00020000,
7517 +} ;
7518 +
7519 +/*******************************************************************************
7520 + *
7521 + * PCI Configuration Address Register
7522 + *
7523 + ******************************************************************************/
7524 +enum {
7525 + PCICFGA_reg_b = 2,
7526 + PCICFGA_reg_m = 0x000000fc,
7527 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
7528 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
7529 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
7530 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
7531 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
7532 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
7533 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
7534 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
7535 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7536 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
7537 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
7538 + PCICFGA_reg_pba0m_v = 0x48>>2,
7539 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
7540 + PCICFGA_reg_pba1m_v = 0x50>>2,
7541 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
7542 + PCICFGA_reg_pba2m_v = 0x58>>2,
7543 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
7544 + PCICFGA_reg_pba3m_v = 0x60>>2,
7545 + PCICFGA_reg_pmgt_v = 0x64>>2,
7546 + PCICFGA_func_b = 8,
7547 + PCICFGA_func_m = 0x00000700,
7548 + PCICFGA_dev_b = 11,
7549 + PCICFGA_dev_m = 0x0000f800,
7550 + PCICFGA_dev_internal_v = 0,
7551 + PCICFGA_bus_b = 16,
7552 + PCICFGA_bus_m = 0x00ff0000,
7553 + PCICFGA_bus_type0_v = 0, //local bus
7554 + PCICFGA_en_b = 31, // read only
7555 + PCICFGA_en_m = 0x80000000,
7556 +} ;
7557 +
7558 +enum {
7559 + PCFGID_vendor_b = 0,
7560 + PCFGID_vendor_m = 0x0000ffff,
7561 + PCFGID_vendor_IDT_v = 0x111d,
7562 + PCFGID_device_b = 16,
7563 + PCFGID_device_m = 0xffff0000,
7564 + PCFGID_device_Korinade_v = 0x0214,
7565 +
7566 + PCFG04_command_ioena_b = 1,
7567 + PCFG04_command_ioena_m = 0x00000001,
7568 + PCFG04_command_memena_b = 2,
7569 + PCFG04_command_memena_m = 0x00000002,
7570 + PCFG04_command_bmena_b = 3,
7571 + PCFG04_command_bmena_m = 0x00000004,
7572 + PCFG04_command_mwinv_b = 5,
7573 + PCFG04_command_mwinv_m = 0x00000010,
7574 + PCFG04_command_parena_b = 7,
7575 + PCFG04_command_parena_m = 0x00000040,
7576 + PCFG04_command_serrena_b = 9,
7577 + PCFG04_command_serrena_m = 0x00000100,
7578 + PCFG04_command_fastbbena_b = 10,
7579 + PCFG04_command_fastbbena_m = 0x00000200,
7580 + PCFG04_status_b = 16,
7581 + PCFG04_status_m = 0xffff0000,
7582 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
7583 + PCFG04_status_66MHz_m = 0x00200000,
7584 + PCFG04_status_fbb_b = 23,
7585 + PCFG04_status_fbb_m = 0x00800000,
7586 + PCFG04_status_mdpe_b = 24,
7587 + PCFG04_status_mdpe_m = 0x01000000,
7588 + PCFG04_status_dst_b = 25,
7589 + PCFG04_status_dst_m = 0x06000000,
7590 + PCFG04_status_sta_b = 27,
7591 + PCFG04_status_sta_m = 0x08000000,
7592 + PCFG04_status_rta_b = 28,
7593 + PCFG04_status_rta_m = 0x10000000,
7594 + PCFG04_status_rma_b = 29,
7595 + PCFG04_status_rma_m = 0x20000000,
7596 + PCFG04_status_sse_b = 30,
7597 + PCFG04_status_sse_m = 0x40000000,
7598 + PCFG04_status_pe_b = 31,
7599 + PCFG04_status_pe_m = 0x40000000,
7600 +
7601 + PCFG08_revId_b = 0,
7602 + PCFG08_revId_m = 0x000000ff,
7603 + PCFG08_classCode_b = 0,
7604 + PCFG08_classCode_m = 0xffffff00,
7605 + PCFG08_classCode_bridge_v = 06,
7606 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
7607 + PCFG0C_cacheline_b = 0,
7608 + PCFG0C_cacheline_m = 0x000000ff,
7609 + PCFG0C_masterLatency_b = 8,
7610 + PCFG0C_masterLatency_m = 0x0000ff00,
7611 + PCFG0C_headerType_b = 16,
7612 + PCFG0C_headerType_m = 0x00ff0000,
7613 + PCFG0C_bist_b = 24,
7614 + PCFG0C_bist_m = 0xff000000,
7615 +
7616 + PCIPBA_msi_b = 0,
7617 + PCIPBA_msi_m = 0x00000001,
7618 + PCIPBA_p_b = 3,
7619 + PCIPBA_p_m = 0x00000004,
7620 + PCIPBA_baddr_b = 8,
7621 + PCIPBA_baddr_m = 0xffffff00,
7622 +
7623 + PCFGSS_vendorId_b = 0,
7624 + PCFGSS_vendorId_m = 0x0000ffff,
7625 + PCFGSS_id_b = 16,
7626 + PCFGSS_id_m = 0xffff0000,
7627 +
7628 + PCFG3C_interruptLine_b = 0,
7629 + PCFG3C_interruptLine_m = 0x000000ff,
7630 + PCFG3C_interruptPin_b = 8,
7631 + PCFG3C_interruptPin_m = 0x0000ff00,
7632 + PCFG3C_minGrant_b = 16,
7633 + PCFG3C_minGrant_m = 0x00ff0000,
7634 + PCFG3C_maxLat_b = 24,
7635 + PCFG3C_maxLat_m = 0xff000000,
7636 +
7637 + PCIPBAC_msi_b = 0,
7638 + PCIPBAC_msi_m = 0x00000001,
7639 + PCIPBAC_p_b = 1,
7640 + PCIPBAC_p_m = 0x00000002,
7641 + PCIPBAC_size_b = 2,
7642 + PCIPBAC_size_m = 0x0000007c,
7643 + PCIPBAC_sb_b = 7,
7644 + PCIPBAC_sb_m = 0x00000080,
7645 + PCIPBAC_pp_b = 8,
7646 + PCIPBAC_pp_m = 0x00000100,
7647 + PCIPBAC_mr_b = 9,
7648 + PCIPBAC_mr_m = 0x00000600,
7649 + PCIPBAC_mr_read_v =0, //no prefetching
7650 + PCIPBAC_mr_readLine_v =1,
7651 + PCIPBAC_mr_readMult_v =2,
7652 + PCIPBAC_mrl_b = 11,
7653 + PCIPBAC_mrl_m = 0x00000800,
7654 + PCIPBAC_mrm_b = 12,
7655 + PCIPBAC_mrm_m = 0x00001000,
7656 + PCIPBAC_trp_b = 13,
7657 + PCIPBAC_trp_m = 0x00002000,
7658 +
7659 + PCFG40_trdyTimeout_b = 0,
7660 + PCFG40_trdyTimeout_m = 0x000000ff,
7661 + PCFG40_retryLim_b = 8,
7662 + PCFG40_retryLim_m = 0x0000ff00,
7663 +};
7664 +
7665 +/*******************************************************************************
7666 + *
7667 + * PCI Local Base Address [0|1|2|3] Register
7668 + *
7669 + ******************************************************************************/
7670 +enum {
7671 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
7672 + PCILBA_baddr_m = 0xffffff00,
7673 +} ;
7674 +/*******************************************************************************
7675 + *
7676 + * PCI Local Base Address Control Register
7677 + *
7678 + ******************************************************************************/
7679 +enum {
7680 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
7681 + PCILBAC_msi_m = 0x00000001,
7682 + PCILBAC_msi_mem_v = 0,
7683 + PCILBAC_msi_io_v = 1,
7684 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
7685 + PCILBAC_size_m = 0x0000007c,
7686 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
7687 + PCILBAC_sb_m = 0x00000080,
7688 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
7689 + PCILBAC_rt_m = 0x00000100,
7690 + PCILBAC_rt_noprefetch_v = 0, // mem read
7691 + PCILBAC_rt_prefetch_v = 1, // mem readline
7692 +} ;
7693 +
7694 +/*******************************************************************************
7695 + *
7696 + * PCI Local Base Address [0|1|2|3] Mapping Register
7697 + *
7698 + ******************************************************************************/
7699 +enum {
7700 + PCILBAM_maddr_b = 8,
7701 + PCILBAM_maddr_m = 0xffffff00,
7702 +} ;
7703 +
7704 +/*******************************************************************************
7705 + *
7706 + * PCI Decoupled Access Control Register
7707 + *
7708 + ******************************************************************************/
7709 +enum {
7710 + PCIDAC_den_b = 0,
7711 + PCIDAC_den_m = 0x00000001,
7712 +} ;
7713 +
7714 +/*******************************************************************************
7715 + *
7716 + * PCI Decoupled Access Status Register
7717 + *
7718 + ******************************************************************************/
7719 +enum {
7720 + PCIDAS_d_b = 0,
7721 + PCIDAS_d_m = 0x00000001,
7722 + PCIDAS_b_b = 1,
7723 + PCIDAS_b_m = 0x00000002,
7724 + PCIDAS_e_b = 2,
7725 + PCIDAS_e_m = 0x00000004,
7726 + PCIDAS_ofe_b = 3,
7727 + PCIDAS_ofe_m = 0x00000008,
7728 + PCIDAS_off_b = 4,
7729 + PCIDAS_off_m = 0x00000010,
7730 + PCIDAS_ife_b = 5,
7731 + PCIDAS_ife_m = 0x00000020,
7732 + PCIDAS_iff_b = 6,
7733 + PCIDAS_iff_m = 0x00000040,
7734 +} ;
7735 +
7736 +/*******************************************************************************
7737 + *
7738 + * PCI DMA Channel 8 Configuration Register
7739 + *
7740 + ******************************************************************************/
7741 +enum
7742 +{
7743 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
7744 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
7745 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
7746 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
7747 +} ;
7748 +
7749 +/*******************************************************************************
7750 + *
7751 + * PCI DMA Channel 9 Configuration Register
7752 + *
7753 + ******************************************************************************/
7754 +enum
7755 +{
7756 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
7757 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
7758 +} ;
7759 +
7760 +/*******************************************************************************
7761 + *
7762 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7763 + *
7764 + ******************************************************************************/
7765 +enum {
7766 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
7767 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
7768 + // These are for reads (DMA channel 8)
7769 + PCIDMAD_devcmd_mr_v = 0, //memory read
7770 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
7771 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
7772 + PCIDMAD_devcmd_ior_v = 3, //I/O read
7773 + // These are for writes (DMA channel 9)
7774 + PCIDMAD_devcmd_mw_v = 0, //memory write
7775 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
7776 + PCIDMAD_devcmd_iow_v = 3, //I/O write
7777 +
7778 + // Swap byte field applies to both DMA channel 8 and 9
7779 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
7780 + PCIDMAD_sb_m = 0x01000000, // swap byte field
7781 +} ;
7782 +
7783 +
7784 +/*******************************************************************************
7785 + *
7786 + * PCI Target Control Register
7787 + *
7788 + ******************************************************************************/
7789 +enum
7790 +{
7791 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
7792 + PCITC_rtimer_m = 0x000000ff,
7793 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
7794 + PCITC_dtimer_m = 0x0000ff00,
7795 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
7796 + PCITC_rdr_m = 0x00040000,
7797 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
7798 + PCITC_ddt_m = 0x00080000,
7799 +} ;
7800 +/*******************************************************************************
7801 + *
7802 + * PCI messaging unit [applies to both inbound and outbound registers ]
7803 + *
7804 + ******************************************************************************/
7805 +enum
7806 +{
7807 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7808 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
7809 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7810 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
7811 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7812 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
7813 +};
7814 +
7815 +
7816 +
7817 +
7818 +
7819 +
7820 +#define PCI_MSG_VirtualAddress 0xB8088010
7821 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7822 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7823 +
7824 +#define PCIM_SHFT 0x6
7825 +#define PCIM_BIT_LEN 0x7
7826 +#define PCIM_H_EA 0x3
7827 +#define PCIM_H_IA_FIX 0x4
7828 +#define PCIM_H_IA_RR 0x5
7829 +#if 0
7830 +#define PCI_ADDR_START 0x13000000
7831 +#endif
7832 +
7833 +#define PCI_ADDR_START 0x50000000
7834 +
7835 +#define CPUTOPCI_MEM_WIN 0x02000000
7836 +#define CPUTOPCI_IO_WIN 0x00100000
7837 +#define PCILBA_SIZE_SHFT 2
7838 +#define PCILBA_SIZE_MASK 0x1F
7839 +#define SIZE_256MB 0x1C
7840 +#define SIZE_128MB 0x1B
7841 +#define SIZE_64MB 0x1A
7842 +#define SIZE_32MB 0x19
7843 +#define SIZE_16MB 0x18
7844 +#define SIZE_4MB 0x16
7845 +#define SIZE_2MB 0x15
7846 +#define SIZE_1MB 0x14
7847 +#define KORINA_CONFIG0_ADDR 0x80000000
7848 +#define KORINA_CONFIG1_ADDR 0x80000004
7849 +#define KORINA_CONFIG2_ADDR 0x80000008
7850 +#define KORINA_CONFIG3_ADDR 0x8000000C
7851 +#define KORINA_CONFIG4_ADDR 0x80000010
7852 +#define KORINA_CONFIG5_ADDR 0x80000014
7853 +#define KORINA_CONFIG6_ADDR 0x80000018
7854 +#define KORINA_CONFIG7_ADDR 0x8000001C
7855 +#define KORINA_CONFIG8_ADDR 0x80000020
7856 +#define KORINA_CONFIG9_ADDR 0x80000024
7857 +#define KORINA_CONFIG10_ADDR 0x80000028
7858 +#define KORINA_CONFIG11_ADDR 0x8000002C
7859 +#define KORINA_CONFIG12_ADDR 0x80000030
7860 +#define KORINA_CONFIG13_ADDR 0x80000034
7861 +#define KORINA_CONFIG14_ADDR 0x80000038
7862 +#define KORINA_CONFIG15_ADDR 0x8000003C
7863 +#define KORINA_CONFIG16_ADDR 0x80000040
7864 +#define KORINA_CONFIG17_ADDR 0x80000044
7865 +#define KORINA_CONFIG18_ADDR 0x80000048
7866 +#define KORINA_CONFIG19_ADDR 0x8000004C
7867 +#define KORINA_CONFIG20_ADDR 0x80000050
7868 +#define KORINA_CONFIG21_ADDR 0x80000054
7869 +#define KORINA_CONFIG22_ADDR 0x80000058
7870 +#define KORINA_CONFIG23_ADDR 0x8000005C
7871 +#define KORINA_CONFIG24_ADDR 0x80000060
7872 +#define KORINA_CONFIG25_ADDR 0x80000064
7873 +#define KORINA_CMD (PCFG04_command_ioena_m | \
7874 + PCFG04_command_memena_m | \
7875 + PCFG04_command_bmena_m | \
7876 + PCFG04_command_mwinv_m | \
7877 + PCFG04_command_parena_m | \
7878 + PCFG04_command_serrena_m )
7879 +
7880 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
7881 + PCFG04_status_sta_m | \
7882 + PCFG04_status_rta_m | \
7883 + PCFG04_status_rma_m | \
7884 + PCFG04_status_sse_m | \
7885 + PCFG04_status_pe_m)
7886 +
7887 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
7888 +
7889 +#define KORINA_REVID 0
7890 +#define KORINA_CLASS_CODE 0
7891 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
7892 + KORINA_REVID)
7893 +
7894 +#define KORINA_CACHE_LINE_SIZE 4
7895 +#define KORINA_MASTER_LAT 0x3c
7896 +#define KORINA_HEADER_TYPE 0
7897 +#define KORINA_BIST 0
7898 +
7899 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7900 + (KORINA_HEADER_TYPE<<16) | \
7901 + (KORINA_MASTER_LAT<<8) | \
7902 + KORINA_CACHE_LINE_SIZE )
7903 +
7904 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
7905 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
7906 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
7907 + internal Registers */
7908 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
7909 +
7910 +#define KORINA_CNFG4 KORINA_BAR0
7911 +#define KORINA_CNFG5 KORINA_BAR1
7912 +#define KORINA_CNFG6 KORINA_BAR2
7913 +#define KORINA_CNFG7 KORINA_BAR3
7914 +
7915 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7916 +#define KORINA_SUBSYSTEM_ID 0x0214
7917 +#define KORINA_CNFG8 0
7918 +#define KORINA_CNFG9 0
7919 +#define KORINA_CNFG10 0
7920 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7921 + KORINA_SUBSYSTEM_ID)
7922 +#define KORINA_INT_LINE 1
7923 +#define KORINA_INT_PIN 1
7924 +#define KORINA_MIN_GNT 8
7925 +#define KORINA_MAX_LAT 0x38
7926 +#define KORINA_CNFG12 0
7927 +#define KORINA_CNFG13 0
7928 +#define KORINA_CNFG14 0
7929 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
7930 + (KORINA_MIN_GNT<<16) | \
7931 + (KORINA_INT_PIN<<8) | \
7932 + KORINA_INT_LINE)
7933 +#define KORINA_RETRY_LIMIT 0x80
7934 +#define KORINA_TRDY_LIMIT 0x80
7935 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7936 + KORINA_TRDY_LIMIT)
7937 +#define PCI_PBAxC_R 0x0
7938 +#define PCI_PBAxC_RL 0x1
7939 +#define PCI_PBAxC_RM 0x2
7940 +#define SIZE_SHFT 2
7941 +
7942 +#if defined(__MIPSEB__)
7943 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7944 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7945 + PCIPBAC_pp_m | \
7946 + (SIZE_128MB<<SIZE_SHFT) | \
7947 + PCIPBAC_p_m)
7948 +#else
7949 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
7950 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7951 + PCIPBAC_pp_m | \
7952 + (SIZE_128MB<<SIZE_SHFT) | \
7953 + PCIPBAC_p_m)
7954 +#endif
7955 +#define KORINA_CNFG17 KORINA_PBA0C
7956 +#define KORINA_PBA0M 0x0
7957 +#define KORINA_CNFG18 KORINA_PBA0M
7958 +
7959 +#if defined(__MIPSEB__)
7960 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7961 + PCIPBAC_msi_m)
7962 +#else
7963 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
7964 + PCIPBAC_msi_m)
7965 +#endif
7966 +#define KORINA_CNFG19 KORINA_PBA1C
7967 +#define KORINA_PBA1M 0x0
7968 +#define KORINA_CNFG20 KORINA_PBA1M
7969 +
7970 +#if defined(__MIPSEB__)
7971 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7972 + PCIPBAC_msi_m)
7973 +#else
7974 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
7975 + PCIPBAC_msi_m)
7976 +#endif
7977 +#define KORINA_CNFG21 KORINA_PBA2C
7978 +#define KORINA_PBA2M 0x18000000
7979 +#define KORINA_CNFG22 KORINA_PBA2M
7980 +#define KORINA_PBA3C 0
7981 +#define KORINA_CNFG23 KORINA_PBA3C
7982 +#define KORINA_PBA3M 0
7983 +#define KORINA_CNFG24 KORINA_PBA3M
7984 +
7985 +
7986 +
7987 +#define PCITC_DTIMER_VAL 8
7988 +#define PCITC_RTIMER_VAL 0x10
7989 +
7990 +
7991 +
7992 +
7993 +#endif // __IDT_PCI_H__
7994 +
7995 +
7996 +
7997 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
7998 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 1970-01-01 01:00:00.000000000 +0100
7999 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-03-20 14:25:10.000000000 +0100
8000 @@ -0,0 +1,119 @@
8001 +/**************************************************************************
8002 + *
8003 + * BRIEF MODULE DESCRIPTION
8004 + * Reset register definitions.
8005 + *
8006 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8007 + *
8008 + * This program is free software; you can redistribute it and/or modify it
8009 + * under the terms of the GNU General Public License as published by the
8010 + * Free Software Foundation; either version 2 of the License, or (at your
8011 + * option) any later version.
8012 + *
8013 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8014 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8015 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8016 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8017 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8018 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8019 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8020 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8021 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8022 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8023 + *
8024 + * You should have received a copy of the GNU General Public License along
8025 + * with this program; if not, write to the Free Software Foundation, Inc.,
8026 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8027 + *
8028 + *
8029 + **************************************************************************
8030 + * May 2004 rkt, neb.
8031 + *
8032 + * Initial Release
8033 + *
8034 + *
8035 + *
8036 + **************************************************************************
8037 + */
8038 +
8039 +#ifndef __IDT_RST_H__
8040 +#define __IDT_RST_H__
8041 +
8042 +enum
8043 +{
8044 + RST0_PhysicalAddress = 0x18000000,
8045 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
8046 +
8047 + RST0_VirtualAddress = 0xb8000000,
8048 + RST_VirtualAddress = RST0_VirtualAddress, // Default
8049 +} ;
8050 +
8051 +typedef struct RST_s
8052 +{
8053 + u32 filler [0x0006] ;
8054 + u32 sysid ;
8055 + u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
8056 + u32 reset ;
8057 + u32 bcv ;
8058 + u32 cea ;
8059 +} volatile * RST_t ;
8060 +
8061 +enum
8062 +{
8063 + SYSID_rev_b = 0,
8064 + SYSID_rev_m = 0x000000ff,
8065 + SYSID_imp_b = 8,
8066 + SYSID_imp_m = 0x000fff00,
8067 + SYSID_vendor_b = 8,
8068 + SYSID_vendor_m = 0xfff00000,
8069 +
8070 + BCV_pll_b = 0,
8071 + BCV_pll_m = 0x0000000f,
8072 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
8073 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
8074 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
8075 + BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
8076 + BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
8077 + BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
8078 + BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
8079 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
8080 + BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
8081 + BCV_pll_Res9_v = 0x9,
8082 + BCV_pll_Res10_v = 0xa,
8083 + BCV_pll_Res11_v = 0xb,
8084 + BCV_pll_Res12_v = 0xc,
8085 + BCV_pll_Res13_v = 0xd,
8086 + BCV_pll_Res14_v = 0xe,
8087 + BCV_pll_Res15_v = 0xf,
8088 + BCV_clkDiv_b = 4,
8089 + BCV_clkDiv_m = 0x00000030,
8090 + BCV_clkDiv_Div1_v = 0x0,
8091 + BCV_clkDiv_Div2_v = 0x1,
8092 + BCV_clkDiv_Div4_v = 0x2,
8093 + BCV_clkDiv_Res3_v = 0x3,
8094 + BCV_bigEndian_b = 6,
8095 + BCV_bigEndian_m = 0x00000040,
8096 + BCV_resetFast_b = 7,
8097 + BCV_resetFast_m = 0x00000080,
8098 + BCV_pciMode_b = 8,
8099 + BCV_pciMode_m = 0x00000700,
8100 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
8101 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
8102 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
8103 + BCV_pciMode_external_v = 3, // host, external arbiter.
8104 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
8105 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
8106 + BCV_pciMode_res6_v = 6,
8107 + BCV_pciMode_res7_v = 7,
8108 + BCV_watchDisable_b = 11,
8109 + BCV_watchDisable_m = 0x00000800,
8110 + BCV_res12_b = 12,
8111 + BCV_res12_m = 0x00001000,
8112 + BCV_res13_b = 13,
8113 + BCV_res13_m = 0x00002000,
8114 + BCV_res14_b = 14,
8115 + BCV_res14_m = 0x00004000,
8116 + BCV_res15_b = 15,
8117 + BCV_res15_m = 0x00008000,
8118 +} ;
8119 +#endif // __IDT_RST_H__
8120 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8121 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 1970-01-01 01:00:00.000000000 +0100
8122 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-03-20 14:25:10.000000000 +0100
8123 @@ -0,0 +1,120 @@
8124 +/**************************************************************************
8125 + *
8126 + * BRIEF MODULE DESCRIPTION
8127 + * Serial Peripheral Interface register definitions.
8128 + *
8129 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8130 + *
8131 + * This program is free software; you can redistribute it and/or modify it
8132 + * under the terms of the GNU General Public License as published by the
8133 + * Free Software Foundation; either version 2 of the License, or (at your
8134 + * option) any later version.
8135 + *
8136 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8137 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8138 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8139 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8140 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8141 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8142 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8143 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8144 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8145 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8146 + *
8147 + * You should have received a copy of the GNU General Public License along
8148 + * with this program; if not, write to the Free Software Foundation, Inc.,
8149 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8150 + *
8151 + *
8152 + **************************************************************************
8153 + * May 2004 rkt, neb.
8154 + *
8155 + * Initial Release
8156 + *
8157 + *
8158 + *
8159 + **************************************************************************
8160 + */
8161 +
8162 +#ifndef __IDT_SPI_H__
8163 +#define __IDT_SPI_H__
8164 +
8165 +enum
8166 +{
8167 + SPI0_PhysicalAddress = 0x18070000,
8168 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
8169 +
8170 + SPI0_VirtualAddress = 0xB8070000,
8171 + SPI_VirtualAddress = SPI0_VirtualAddress,
8172 +} ;
8173 +
8174 +typedef struct
8175 +{
8176 + u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8177 + u32 spc ; // spi control reg use SPC_
8178 + u32 sps ; // spi status reg use SPS_
8179 + u32 spd ; // spi data reg use SPD_
8180 + u32 siofunc ; // serial IO function use SIOFUNC_
8181 + u32 siocfg ; // serial IO config use SIOCFG_
8182 + u32 siod; // serial IO data use SIOD_
8183 +} volatile *SPI_t ;
8184 +
8185 +enum
8186 +{
8187 + SPCP_div_b = 0,
8188 + SPCP_div_m = 0x000000ff,
8189 + SPC_spr_b = 0,
8190 + SPC_spr_m = 0x00000003,
8191 + SPC_spr_div2_v = 0,
8192 + SPC_spr_div4_v = 1,
8193 + SPC_spr_div16_v = 2,
8194 + SPC_spr_div32_v = 3,
8195 + SPC_cpha_b = 2,
8196 + SPC_cpha_m = 0x00000004,
8197 + SPC_cpol_b = 3,
8198 + SPC_cpol_m = 0x00000008,
8199 + SPC_mstr_b = 4,
8200 + SPC_mstr_m = 0x00000010,
8201 + SPC_spe_b = 6,
8202 + SPC_spe_m = 0x00000040,
8203 + SPC_spie_b = 7,
8204 + SPC_spie_m = 0x00000080,
8205 +
8206 + SPS_modf_b = 4,
8207 + SPS_modf_m = 0x00000010,
8208 + SPS_wcol_b = 6,
8209 + SPS_wcol_m = 0x00000040,
8210 + SPS_spif_b = 7,
8211 + SPS_spif_m = 0x00000070,
8212 +
8213 + SPD_data_b = 0,
8214 + SPD_data_m = 0x000000ff,
8215 +
8216 + SIOFUNC_sdo_b = 0,
8217 + SIOFUNC_sdo_m = 0x00000001,
8218 + SIOFUNC_sdi_b = 1,
8219 + SIOFUNC_sdi_m = 0x00000002,
8220 + SIOFUNC_sck_b = 2,
8221 + SIOFUNC_sck_m = 0x00000004,
8222 + SIOFUNC_pci_b = 3,
8223 + SIOFUNC_pci_m = 0x00000008,
8224 +
8225 + SIOCFG_sdo_b = 0,
8226 + SIOCFG_sdo_m = 0x00000001,
8227 + SIOCFG_sdi_b = 1,
8228 + SIOCFG_sdi_m = 0x00000002,
8229 + SIOCFG_sck_b = 2,
8230 + SIOCFG_sck_m = 0x00000004,
8231 + SIOCFG_pci_b = 3,
8232 + SIOCFG_pci_m = 0x00000008,
8233 +
8234 + SIOD_sdo_b = 0,
8235 + SIOD_sdo_m = 0x00000001,
8236 + SIOD_sdi_b = 1,
8237 + SIOD_sdi_m = 0x00000002,
8238 + SIOD_sck_b = 2,
8239 + SIOD_sck_m = 0x00000004,
8240 + SIOD_pci_b = 3,
8241 + SIOD_pci_m = 0x00000008,
8242 +} ;
8243 +#endif // __IDT_SPI_H__
8244 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8245 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 1970-01-01 01:00:00.000000000 +0100
8246 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 2006-03-20 14:25:10.000000000 +0100
8247 @@ -0,0 +1,91 @@
8248 +/**************************************************************************
8249 + *
8250 + * BRIEF MODULE DESCRIPTION
8251 + * Definitions for timer registers
8252 + *
8253 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8254 + *
8255 + * This program is free software; you can redistribute it and/or modify it
8256 + * under the terms of the GNU General Public License as published by the
8257 + * Free Software Foundation; either version 2 of the License, or (at your
8258 + * option) any later version.
8259 + *
8260 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8261 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8262 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8263 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8264 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8265 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8266 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8267 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8268 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8269 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8270 + *
8271 + * You should have received a copy of the GNU General Public License along
8272 + * with this program; if not, write to the Free Software Foundation, Inc.,
8273 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8274 + *
8275 + *
8276 + **************************************************************************
8277 + * May 2004 rkt,neb.
8278 + *
8279 + * Initial Release
8280 + *
8281 + *
8282 + *
8283 + **************************************************************************
8284 + */
8285 +
8286 +#ifndef __IDT_TIM_H__
8287 +#define __IDT_TIM_H__
8288 +
8289 +enum
8290 +{
8291 + TIM0_PhysicalAddress = 0x18028000,
8292 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
8293 +
8294 + TIM0_VirtualAddress = 0xb8028000,
8295 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
8296 +} ;
8297 +
8298 +enum
8299 +{
8300 + TIM_Count = 3,
8301 +} ;
8302 +
8303 +struct TIM_CNTR_s
8304 +{
8305 + u32 count ;
8306 + u32 compare ;
8307 + u32 ctc ; //use CTC_
8308 +} ;
8309 +
8310 +typedef struct TIM_s
8311 +{
8312 + struct TIM_CNTR_s tim [TIM_Count] ;
8313 + u32 rcount ; //use RCOUNT_
8314 + u32 rcompare ; //use RCOMPARE_
8315 + u32 rtc ; //use RTC_
8316 +} volatile * TIM_t ;
8317 +
8318 +enum
8319 +{
8320 + CTC_en_b = 0,
8321 + CTC_en_m = 0x00000001,
8322 + CTC_to_b = 1,
8323 + CTC_to_m = 0x00000002,
8324 +
8325 + RCOUNT_count_b = 0,
8326 + RCOUNT_count_m = 0x0000ffff,
8327 + RCOMPARE_compare_b = 0,
8328 + RCOMPARE_compare_m = 0x0000ffff,
8329 + RTC_ce_b = 0,
8330 + RTC_ce_m = 0x00000001,
8331 + RTC_to_b = 1,
8332 + RTC_to_m = 0x00000002,
8333 + RTC_rqe_b = 2,
8334 + RTC_rqe_m = 0x00000004,
8335 +
8336 +} ;
8337 +#endif // __IDT_TIM_H__
8338 +
8339 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8340 --- linux-2.6.16/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 1970-01-01 01:00:00.000000000 +0100
8341 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 2006-03-20 14:25:10.000000000 +0100
8342 @@ -0,0 +1,189 @@
8343 +/**************************************************************************
8344 + *
8345 + * BRIEF MODULE DESCRIPTION
8346 + * UART register definitions
8347 + *
8348 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8349 + *
8350 + * This program is free software; you can redistribute it and/or modify it
8351 + * under the terms of the GNU General Public License as published by the
8352 + * Free Software Foundation; either version 2 of the License, or (at your
8353 + * option) any later version.
8354 + *
8355 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8356 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8357 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8358 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8359 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8360 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8361 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8362 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8363 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8364 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8365 + *
8366 + * You should have received a copy of the GNU General Public License along
8367 + * with this program; if not, write to the Free Software Foundation, Inc.,
8368 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8369 + *
8370 + *
8371 + **************************************************************************
8372 + * May 2004 rkt, neb.
8373 + *
8374 + * Initial Release
8375 + *
8376 + *
8377 + *
8378 + **************************************************************************
8379 + */
8380 +
8381 +#ifndef __IDT_UART_H__
8382 +#define __IDT_UART_H__
8383 +
8384 +enum
8385 +{
8386 + UART0_PhysicalAddress = 0x1c000000,
8387 + UART_PhysicalAddress = UART0_PhysicalAddress, // Default
8388 +
8389 + UART0_VirtualAddress = 0xbc000000,
8390 + UART_VirtualAddress = UART0_VirtualAddress, // Default
8391 +} ;
8392 +
8393 +/*
8394 + * Register definitions are in bytes so we can handle endian problems.
8395 + */
8396 +
8397 +typedef struct UART_s
8398 +{
8399 + union
8400 + {
8401 + u32 const uartrb ; // 0x00 - DLAB=0, read.
8402 + u32 uartth ; // 0x00 - DLAB=0, write.
8403 + u32 uartdll ; // 0x00 - DLAB=1, read/write.
8404 + } ;
8405 +
8406 + union
8407 + {
8408 + u32 uartie ; // 0x04 - DLAB=0, read/write.
8409 + u32 uartdlh ; // 0x04 - DLAB=1, read/write.
8410 + } ;
8411 + union
8412 + {
8413 + u32 const uartii ; // 0x08 - DLAB=0, read.
8414 + u32 uartfc ; // 0x08 - DLAB=0, write.
8415 + } ;
8416 +
8417 + u32 uartlc ; // 0x0c
8418 + u32 uartmc ; // 0x10
8419 + u32 uartls ; // 0x14
8420 + u32 uartms ; // 0x18
8421 + u32 uarts ; // 0x1c
8422 +} volatile *UART_t ;
8423 +
8424 +// Reset registers.
8425 +typedef u32 volatile *UARTRR_t ;
8426 +
8427 +enum
8428 +{
8429 + UARTIE_rda_b = 0,
8430 + UARTIE_rda_m = 0x00000001,
8431 + UARTIE_the_b = 1,
8432 + UARTIE_the_m = 0x00000002,
8433 + UARTIE_rls_b = 2,
8434 + UARTIE_rls_m = 0x00000004,
8435 + UARTIE_ems_b = 3,
8436 + UARTIE_ems_m = 0x00000008,
8437 +
8438 + UARTII_pi_b = 0,
8439 + UARTII_pi_m = 0x00000001,
8440 + UARTII_iid_b = 1,
8441 + UARTII_iid_m = 0x0000000e,
8442 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
8443 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
8444 + UARTII_iid_rda_v = 2, // Receive data available
8445 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
8446 + UARTII_iid_res4_v = 4, // reserved.
8447 + UARTII_iid_res5_v = 5, // reserved.
8448 + UARTII_iid_cto_v = 6, // Character timeout.
8449 + UARTII_iid_res7_v = 7, // reserved.
8450 +
8451 + UARTFC_en_b = 0,
8452 + UARTFC_en_m = 0x00000001,
8453 + UARTFC_rr_b = 1,
8454 + UARTFC_rr_m = 0x00000002,
8455 + UARTFC_tr_b = 2,
8456 + UARTFC_tr_m = 0x00000004,
8457 + UARTFC_dms_b = 3,
8458 + UARTFC_dms_m = 0x00000008,
8459 + UARTFC_rt_b = 6,
8460 + UARTFC_rt_m = 0x000000c0,
8461 + UARTFC_rt_1Byte_v = 0,
8462 + UARTFC_rt_4Byte_v = 1,
8463 + UARTFC_rt_8Byte_v = 2,
8464 + UARTFC_rt_14Byte_v = 3,
8465 +
8466 + UARTLC_wls_b = 0,
8467 + UARTLC_wls_m = 0x00000003,
8468 + UARTLC_wls_5Bits_v = 0,
8469 + UARTLC_wls_6Bits_v = 1,
8470 + UARTLC_wls_7Bits_v = 2,
8471 + UARTLC_wls_8Bits_v = 3,
8472 + UARTLC_stb_b = 2,
8473 + UARTLC_stb_m = 0x00000004,
8474 + UARTLC_pen_b = 3,
8475 + UARTLC_pen_m = 0x00000008,
8476 + UARTLC_eps_b = 4,
8477 + UARTLC_eps_m = 0x00000010,
8478 + UARTLC_sp_b = 5,
8479 + UARTLC_sp_m = 0x00000020,
8480 + UARTLC_sb_b = 6,
8481 + UARTLC_sb_m = 0x00000040,
8482 + UARTLC_dlab_b = 7,
8483 + UARTLC_dlab_m = 0x00000080,
8484 +
8485 + UARTMC_dtr_b = 0,
8486 + UARTMC_dtr_m = 0x00000001,
8487 + UARTMC_rts_b = 1,
8488 + UARTMC_rts_m = 0x00000002,
8489 + UARTMC_o1_b = 2,
8490 + UARTMC_o1_m = 0x00000004,
8491 + UARTMC_o2_b = 3,
8492 + UARTMC_o2_m = 0x00000008,
8493 + UARTMC_lp_b = 4,
8494 + UARTMC_lp_m = 0x00000010,
8495 +
8496 + UARTLS_dr_b = 0,
8497 + UARTLS_dr_m = 0x00000001,
8498 + UARTLS_oe_b = 1,
8499 + UARTLS_oe_m = 0x00000002,
8500 + UARTLS_pe_b = 2,
8501 + UARTLS_pe_m = 0x00000004,
8502 + UARTLS_fe_b = 3,
8503 + UARTLS_fe_m = 0x00000008,
8504 + UARTLS_bi_b = 4,
8505 + UARTLS_bi_m = 0x00000010,
8506 + UARTLS_thr_b = 5,
8507 + UARTLS_thr_m = 0x00000020,
8508 + UARTLS_te_b = 6,
8509 + UARTLS_te_m = 0x00000040,
8510 + UARTLS_rfe_b = 7,
8511 + UARTLS_rfe_m = 0x00000080,
8512 +
8513 + UARTMS_dcts_b = 0,
8514 + UARTMS_dcts_m = 0x00000001,
8515 + UARTMS_ddsr_b = 1,
8516 + UARTMS_ddsr_m = 0x00000002,
8517 + UARTMS_teri_b = 2,
8518 + UARTMS_teri_m = 0x00000004,
8519 + UARTMS_ddcd_b = 3,
8520 + UARTMS_ddcd_m = 0x00000008,
8521 + UARTMS_cts_b = 4,
8522 + UARTMS_cts_m = 0x00000010,
8523 + UARTMS_dsr_b = 5,
8524 + UARTMS_dsr_m = 0x00000020,
8525 + UARTMS_ri_b = 6,
8526 + UARTMS_ri_m = 0x00000040,
8527 + UARTMS_dcd_b = 7,
8528 + UARTMS_dcd_m = 0x00000080,
8529 +} ;
8530 +
8531 +#endif // __IDT_UART_H__
8532 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8533 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 1970-01-01 01:00:00.000000000 +0100
8534 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-03-20 14:25:10.000000000 +0100
8535 @@ -0,0 +1,231 @@
8536 +/**************************************************************************
8537 + *
8538 + * BRIEF MODULE DESCRIPTION
8539 + * Register definitions for IDT RC32438 DMA.
8540 + *
8541 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8542 + *
8543 + * This program is free software; you can redistribute it and/or modify it
8544 + * under the terms of the GNU General Public License as published by the
8545 + * Free Software Foundation; either version 2 of the License, or (at your
8546 + * option) any later version.
8547 + *
8548 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8549 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8550 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8551 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8552 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8553 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8554 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8555 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8556 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8557 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8558 + *
8559 + * You should have received a copy of the GNU General Public License along
8560 + * with this program; if not, write to the Free Software Foundation, Inc.,
8561 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8562 + *
8563 + *
8564 + **************************************************************************
8565 + * May 2004 P. Sadik.
8566 + *
8567 + * Initial Release
8568 + *
8569 + *
8570 + *
8571 + **************************************************************************
8572 + */
8573 +#ifndef __IDT_RC32438_DMA_H__
8574 +#define __IDT_RC32438_DMA_H__
8575 +enum
8576 +{
8577 + DMA0_PhysicalAddress = 0x18040000,
8578 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
8579 +
8580 + DMA0_VirtualAddress = 0xb8040000,
8581 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
8582 +} ;
8583 +
8584 +/*
8585 + * DMA descriptor (in physical memory).
8586 + */
8587 +
8588 +typedef struct DMAD_s
8589 +{
8590 + u32 control ; // Control. use DMAD_*
8591 + u32 ca ; // Current Address.
8592 + u32 devcs ; // Device control and status.
8593 + u32 link ; // Next descriptor in chain.
8594 +} volatile *DMAD_t ;
8595 +
8596 +enum
8597 +{
8598 + DMAD_size = sizeof (struct DMAD_s),
8599 + DMAD_count_b = 0, // in DMAD_t -> control
8600 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
8601 + DMAD_ds_b = 20, // in DMAD_t -> control
8602 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
8603 + DMAD_ds_extToMem0_v = 0,
8604 + DMAD_ds_memToExt0_v = 1,
8605 + DMAD_ds_extToMem1_v = 0,
8606 + DMAD_ds_memToExt1_v = 1,
8607 + DMAD_ds_ethRcv0_v = 0,
8608 + DMAD_ds_ethXmt0_v = 0,
8609 + DMAD_ds_ethRcv1_v = 0,
8610 + DMAD_ds_ethXmt2_v = 0,
8611 + DMAD_ds_memToFifo_v = 0,
8612 + DMAD_ds_fifoToMem_v = 0,
8613 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
8614 + DMAD_ds_pciToMem_v = 0,
8615 + DMAD_ds_memToPci_v = 0,
8616 + DMAD_ds_securityInput_v = 0,
8617 + DMAD_ds_securityOutput_v = 0,
8618 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
8619 +
8620 + DMAD_devcmd_b = 22, // in DMAD_t -> control
8621 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
8622 + DMAD_devcmd_byte_v = 0, //memory-to-memory
8623 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
8624 + DMAD_devcmd_word_v = 2, //memory-to-memory
8625 + DMAD_devcmd_2words_v = 3, //memory-to-memory
8626 + DMAD_devcmd_4words_v = 4, //memory-to-memory
8627 + DMAD_devcmd_6words_v = 5, //memory-to-memory
8628 + DMAD_devcmd_8words_v = 6, //memory-to-memory
8629 + DMAD_devcmd_16words_v = 7, //memory-to-memory
8630 + DMAD_cof_b = 25, // chain on finished
8631 + DMAD_cof_m = 0x02000000, //
8632 + DMAD_cod_b = 26, // chain on done
8633 + DMAD_cod_m = 0x04000000, //
8634 + DMAD_iof_b = 27, // interrupt on finished
8635 + DMAD_iof_m = 0x08000000, //
8636 + DMAD_iod_b = 28, // interrupt on done
8637 + DMAD_iod_m = 0x10000000, //
8638 + DMAD_t_b = 29, // terminated
8639 + DMAD_t_m = 0x20000000, //
8640 + DMAD_d_b = 30, // done
8641 + DMAD_d_m = 0x40000000, //
8642 + DMAD_f_b = 31, // finished
8643 + DMAD_f_m = 0x80000000, //
8644 +} ;
8645 +
8646 +/*
8647 + * DMA register (within Internal Register Map).
8648 + */
8649 +
8650 +struct DMA_Chan_s
8651 +{
8652 + u32 dmac ; // Control.
8653 + u32 dmas ; // Status.
8654 + u32 dmasm ; // Mask.
8655 + u32 dmadptr ; // Descriptor pointer.
8656 + u32 dmandptr ; // Next descriptor pointer.
8657 +};
8658 +
8659 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8660 +
8661 +//DMA_Channels use DMACH_count instead
8662 +
8663 +enum
8664 +{
8665 + DMAC_run_b = 0, //
8666 + DMAC_run_m = 0x00000001, //
8667 + DMAC_dm_b = 1, // done mask
8668 + DMAC_dm_m = 0x00000002, //
8669 + DMAC_mode_b = 2, //
8670 + DMAC_mode_m = 0x0000000c, //
8671 + DMAC_mode_auto_v = 0,
8672 + DMAC_mode_burst_v = 1,
8673 + DMAC_mode_transfer_v = 2, //usually used
8674 + DMAC_mode_reserved_v = 3,
8675 + DMAC_a_b = 4, //
8676 + DMAC_a_m = 0x00000010, //
8677 +
8678 + DMAS_f_b = 0, // finished (sticky)
8679 + DMAS_f_m = 0x00000001, //
8680 + DMAS_d_b = 1, // done (sticky)
8681 + DMAS_d_m = 0x00000002, //
8682 + DMAS_c_b = 2, // chain (sticky)
8683 + DMAS_c_m = 0x00000004, //
8684 + DMAS_e_b = 3, // error (sticky)
8685 + DMAS_e_m = 0x00000008, //
8686 + DMAS_h_b = 4, // halt (sticky)
8687 + DMAS_h_m = 0x00000010, //
8688 +
8689 + DMASM_f_b = 0, // finished (1=mask)
8690 + DMASM_f_m = 0x00000001, //
8691 + DMASM_d_b = 1, // done (1=mask)
8692 + DMASM_d_m = 0x00000002, //
8693 + DMASM_c_b = 2, // chain (1=mask)
8694 + DMASM_c_m = 0x00000004, //
8695 + DMASM_e_b = 3, // error (1=mask)
8696 + DMASM_e_m = 0x00000008, //
8697 + DMASM_h_b = 4, // halt (1=mask)
8698 + DMASM_h_m = 0x00000010, //
8699 +} ;
8700 +
8701 +/*
8702 + * DMA channel definitions
8703 + */
8704 +
8705 +enum
8706 +{
8707 + DMACH_extToMem0 = 0,
8708 + DMACH_memToExt0 = 0,
8709 + DMACH_extToMem1 = 1,
8710 + DMACH_memToExt1 = 1,
8711 + DMACH_ethRcv0 = 2,
8712 + DMACH_ethXmt0 = 3,
8713 + DMACH_ethRcv1 = 4,
8714 + DMACH_ethXmt2 = 5,
8715 + DMACH_memToFifo = 6,
8716 + DMACH_fifoToMem = 7,
8717 + DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8718 + DMACH_pciToMem = 8,
8719 + DMACH_memToPci = 9,
8720 + DMACH_securityInput = 10,
8721 + DMACH_securityOutput = 11,
8722 + DMACH_rng_se = 12, //randomNumberGenerator on SE
8723 +
8724 + DMACH_count //must be last
8725 +};
8726 +
8727 +
8728 +typedef struct DMAC_s
8729 +{
8730 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8731 +} volatile *DMA_t ;
8732 +
8733 +
8734 +/*
8735 + * External DMA parameters
8736 +*/
8737 +
8738 +enum
8739 +{
8740 + DMADEVCMD_ts_b = 0, // ts field in devcmd
8741 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
8742 + DMADEVCMD_ts_byte_v = 0,
8743 + DMADEVCMD_ts_halfword_v = 1,
8744 + DMADEVCMD_ts_word_v = 2,
8745 + DMADEVCMD_ts_2word_v = 3,
8746 + DMADEVCMD_ts_4word_v = 4,
8747 + DMADEVCMD_ts_6word_v = 5,
8748 + DMADEVCMD_ts_8word_v = 6,
8749 + DMADEVCMD_ts_16word_v = 7
8750 +};
8751 +
8752 +
8753 +#if 1 // aws - Compatibility.
8754 +# define EXTDMA_ts_b DMADEVCMD_ts_b
8755 +# define EXTDMA_ts_m DMADEVCMD_ts_m
8756 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
8757 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
8758 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
8759 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
8760 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
8761 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
8762 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
8763 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
8764 +#endif // aws - Compatibility.
8765 +
8766 +#endif //__IDT_RC32438_DMA_H__
8767 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8768 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 1970-01-01 01:00:00.000000000 +0100
8769 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 2006-03-20 14:25:10.000000000 +0100
8770 @@ -0,0 +1,82 @@
8771 +/**************************************************************************
8772 + *
8773 + * BRIEF MODULE DESCRIPTION
8774 + * DMA operations for IDT RC32438.
8775 + *
8776 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8777 + *
8778 + * This program is free software; you can redistribute it and/or modify it
8779 + * under the terms of the GNU General Public License as published by the
8780 + * Free Software Foundation; either version 2 of the License, or (at your
8781 + * option) any later version.
8782 + *
8783 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8784 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8785 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8786 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8787 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8788 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8789 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8790 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8791 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8792 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8793 + *
8794 + * You should have received a copy of the GNU General Public License along
8795 + * with this program; if not, write to the Free Software Foundation, Inc.,
8796 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8797 + *
8798 + *
8799 + **************************************************************************
8800 + * May 2004 P. Sadik.
8801 + *
8802 + * Initial Release
8803 + *
8804 + *
8805 + *
8806 + **************************************************************************
8807 + */
8808 +
8809 +#ifndef __IDT_RC32438_DMA_V_H__
8810 +#define __IDT_RC32438_DMA_V_H__
8811 +#include <asm/idt-boards/rc32438/rc32438_dma.h>
8812 +
8813 +#define DMA_CHAN_OFFSET 0x14
8814 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8815 +#define DMA_COUNT(count) \
8816 + ((count) & DMAD_count_m)
8817 +
8818 +#define DMA_HALT_TIMEOUT 500
8819 +
8820 +
8821 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8822 +{
8823 + int timeout=1;
8824 + if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8825 + rc32438_writel(0, &ch->dmac);
8826 +
8827 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8828 + if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8829 + rc32438_writel(0, &ch->dmas);
8830 + break;
8831 + }
8832 + }
8833 +
8834 + }
8835 +
8836 + return timeout ? 0 : 1;
8837 +}
8838 +
8839 +
8840 +
8841 +
8842 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8843 +{
8844 + rc32438_writel(0, &ch->dmandptr);
8845 + rc32438_writel(dma_addr, &ch->dmadptr);
8846 +}
8847 +
8848 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8849 +{
8850 + rc32438_writel(dma_addr, &ch->dmandptr);
8851 +}
8852 +#endif //__IDT_RC32438_DMA_V_H__
8853 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8854 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 1970-01-01 01:00:00.000000000 +0100
8855 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-03-20 14:25:10.000000000 +0100
8856 @@ -0,0 +1,328 @@
8857 +/**************************************************************************
8858 + *
8859 + * BRIEF MODULE DESCRIPTION
8860 + * Definitions for IDT EB438 ethernet
8861 + *
8862 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8863 + *
8864 + * This program is free software; you can redistribute it and/or modify it
8865 + * under the terms of the GNU General Public License as published by the
8866 + * Free Software Foundation; either version 2 of the License, or (at your
8867 + * option) any later version.
8868 + *
8869 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8870 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8871 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8872 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8873 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8874 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8875 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8876 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8877 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8878 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8879 + *
8880 + * You should have received a copy of the GNU General Public License along
8881 + * with this program; if not, write to the Free Software Foundation, Inc.,
8882 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8883 + *
8884 + *
8885 + **************************************************************************
8886 + * May 2004 P. Sadik.
8887 + *
8888 + * Initial Release
8889 + *
8890 + *
8891 + *
8892 + **************************************************************************
8893 + */
8894 +
8895 +#ifndef __IDT_RC32438_ETH_H__
8896 +#define __IDT_RC32438_ETH_H__
8897 +enum
8898 +{
8899 + ETH0_PhysicalAddress = 0x18058000,
8900 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
8901 +
8902 + ETH0_VirtualAddress = 0xb8058000,
8903 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
8904 + ETH1_PhysicalAddress = 0x18060000,
8905 + ETH1_VirtualAddress = 0xb8060000, // Default
8906 +} ;
8907 +
8908 +typedef struct
8909 +{
8910 + u32 ethintfc ;
8911 + u32 ethfifott ;
8912 + u32 etharc ;
8913 + u32 ethhash0 ;
8914 + u32 ethhash1 ;
8915 + u32 ethu0 [4] ; // Reserved.
8916 + u32 ethpfs ;
8917 + u32 ethmcp ;
8918 + u32 eth_u1 [10] ; // Reserved.
8919 + u32 ethspare ;
8920 + u32 eth_u2 [42] ; // Reserved.
8921 + u32 ethsal0 ;
8922 + u32 ethsah0 ;
8923 + u32 ethsal1 ;
8924 + u32 ethsah1 ;
8925 + u32 ethsal2 ;
8926 + u32 ethsah2 ;
8927 + u32 ethsal3 ;
8928 + u32 ethsah3 ;
8929 + u32 ethrbc ;
8930 + u32 ethrpc ;
8931 + u32 ethrupc ;
8932 + u32 ethrfc ;
8933 + u32 ethtbc ;
8934 + u32 ethgpf ;
8935 + u32 eth_u9 [50] ; // Reserved.
8936 + u32 ethmac1 ;
8937 + u32 ethmac2 ;
8938 + u32 ethipgt ;
8939 + u32 ethipgr ;
8940 + u32 ethclrt ;
8941 + u32 ethmaxf ;
8942 + u32 eth_u10 ; // Reserved.
8943 + u32 ethmtest ;
8944 + u32 miimcfg ;
8945 + u32 miimcmd ;
8946 + u32 miimaddr ;
8947 + u32 miimwtd ;
8948 + u32 miimrdd ;
8949 + u32 miimind ;
8950 + u32 eth_u11 ; // Reserved.
8951 + u32 eth_u12 ; // Reserved.
8952 + u32 ethcfsa0 ;
8953 + u32 ethcfsa1 ;
8954 + u32 ethcfsa2 ;
8955 +} volatile *ETH_t;
8956 +
8957 +enum
8958 +{
8959 + ETHINTFC_en_b = 0,
8960 + ETHINTFC_en_m = 0x00000001,
8961 + ETHINTFC_its_b = 1,
8962 + ETHINTFC_its_m = 0x00000002,
8963 + ETHINTFC_rip_b = 2,
8964 + ETHINTFC_rip_m = 0x00000004,
8965 + ETHINTFC_jam_b = 3,
8966 + ETHINTFC_jam_m = 0x00000008,
8967 + ETHINTFC_ovr_b = 4,
8968 + ETHINTFC_ovr_m = 0x00000010,
8969 + ETHINTFC_und_b = 5,
8970 + ETHINTFC_und_m = 0x00000020,
8971 +
8972 + ETHFIFOTT_tth_b = 0,
8973 + ETHFIFOTT_tth_m = 0x0000007f,
8974 +
8975 + ETHARC_pro_b = 0,
8976 + ETHARC_pro_m = 0x00000001,
8977 + ETHARC_am_b = 1,
8978 + ETHARC_am_m = 0x00000002,
8979 + ETHARC_afm_b = 2,
8980 + ETHARC_afm_m = 0x00000004,
8981 + ETHARC_ab_b = 3,
8982 + ETHARC_ab_m = 0x00000008,
8983 +
8984 + ETHSAL_byte5_b = 0,
8985 + ETHSAL_byte5_m = 0x000000ff,
8986 + ETHSAL_byte4_b = 8,
8987 + ETHSAL_byte4_m = 0x0000ff00,
8988 + ETHSAL_byte3_b = 16,
8989 + ETHSAL_byte3_m = 0x00ff0000,
8990 + ETHSAL_byte2_b = 24,
8991 + ETHSAL_byte2_m = 0xff000000,
8992 +
8993 + ETHSAH_byte1_b = 0,
8994 + ETHSAH_byte1_m = 0x000000ff,
8995 + ETHSAH_byte0_b = 8,
8996 + ETHSAH_byte0_m = 0x0000ff00,
8997 +
8998 + ETHGPF_ptv_b = 0,
8999 + ETHGPF_ptv_m = 0x0000ffff,
9000 +
9001 + ETHPFS_pfd_b = 0,
9002 + ETHPFS_pfd_m = 0x00000001,
9003 +
9004 + ETHCFSA0_cfsa4_b = 0,
9005 + ETHCFSA0_cfsa4_m = 0x000000ff,
9006 + ETHCFSA0_cfsa5_b = 8,
9007 + ETHCFSA0_cfsa5_m = 0x0000ff00,
9008 +
9009 + ETHCFSA1_cfsa2_b = 0,
9010 + ETHCFSA1_cfsa2_m = 0x000000ff,
9011 + ETHCFSA1_cfsa3_b = 8,
9012 + ETHCFSA1_cfsa3_m = 0x0000ff00,
9013 +
9014 + ETHCFSA2_cfsa0_b = 0,
9015 + ETHCFSA2_cfsa0_m = 0x000000ff,
9016 + ETHCFSA2_cfsa1_b = 8,
9017 + ETHCFSA2_cfsa1_m = 0x0000ff00,
9018 +
9019 + ETHMAC1_re_b = 0,
9020 + ETHMAC1_re_m = 0x00000001,
9021 + ETHMAC1_paf_b = 1,
9022 + ETHMAC1_paf_m = 0x00000002,
9023 + ETHMAC1_rfc_b = 2,
9024 + ETHMAC1_rfc_m = 0x00000004,
9025 + ETHMAC1_tfc_b = 3,
9026 + ETHMAC1_tfc_m = 0x00000008,
9027 + ETHMAC1_lb_b = 4,
9028 + ETHMAC1_lb_m = 0x00000010,
9029 + ETHMAC1_mr_b = 31,
9030 + ETHMAC1_mr_m = 0x80000000,
9031 +
9032 + ETHMAC2_fd_b = 0,
9033 + ETHMAC2_fd_m = 0x00000001,
9034 + ETHMAC2_flc_b = 1,
9035 + ETHMAC2_flc_m = 0x00000002,
9036 + ETHMAC2_hfe_b = 2,
9037 + ETHMAC2_hfe_m = 0x00000004,
9038 + ETHMAC2_dc_b = 3,
9039 + ETHMAC2_dc_m = 0x00000008,
9040 + ETHMAC2_cen_b = 4,
9041 + ETHMAC2_cen_m = 0x00000010,
9042 + ETHMAC2_pe_b = 5,
9043 + ETHMAC2_pe_m = 0x00000020,
9044 + ETHMAC2_vpe_b = 6,
9045 + ETHMAC2_vpe_m = 0x00000040,
9046 + ETHMAC2_ape_b = 7,
9047 + ETHMAC2_ape_m = 0x00000080,
9048 + ETHMAC2_ppe_b = 8,
9049 + ETHMAC2_ppe_m = 0x00000100,
9050 + ETHMAC2_lpe_b = 9,
9051 + ETHMAC2_lpe_m = 0x00000200,
9052 + ETHMAC2_nb_b = 12,
9053 + ETHMAC2_nb_m = 0x00001000,
9054 + ETHMAC2_bp_b = 13,
9055 + ETHMAC2_bp_m = 0x00002000,
9056 + ETHMAC2_ed_b = 14,
9057 + ETHMAC2_ed_m = 0x00004000,
9058 +
9059 + ETHIPGT_ipgt_b = 0,
9060 + ETHIPGT_ipgt_m = 0x0000007f,
9061 +
9062 + ETHIPGR_ipgr2_b = 0,
9063 + ETHIPGR_ipgr2_m = 0x0000007f,
9064 + ETHIPGR_ipgr1_b = 8,
9065 + ETHIPGR_ipgr1_m = 0x00007f00,
9066 +
9067 + ETHCLRT_maxret_b = 0,
9068 + ETHCLRT_maxret_m = 0x0000000f,
9069 + ETHCLRT_colwin_b = 8,
9070 + ETHCLRT_colwin_m = 0x00003f00,
9071 +
9072 + ETHMAXF_maxf_b = 0,
9073 + ETHMAXF_maxf_m = 0x0000ffff,
9074 +
9075 + ETHMTEST_tb_b = 2,
9076 + ETHMTEST_tb_m = 0x00000004,
9077 +
9078 + ETHMCP_div_b = 0,
9079 + ETHMCP_div_m = 0x000000ff,
9080 +
9081 + MIIMCFG_rsv_b = 0,
9082 + MIIMCFG_rsv_m = 0x0000000c,
9083 +
9084 + MIIMCMD_rd_b = 0,
9085 + MIIMCMD_rd_m = 0x00000001,
9086 + MIIMCMD_scn_b = 1,
9087 + MIIMCMD_scn_m = 0x00000002,
9088 +
9089 + MIIMADDR_regaddr_b = 0,
9090 + MIIMADDR_regaddr_m = 0x0000001f,
9091 + MIIMADDR_phyaddr_b = 8,
9092 + MIIMADDR_phyaddr_m = 0x00001f00,
9093 +
9094 + MIIMWTD_wdata_b = 0,
9095 + MIIMWTD_wdata_m = 0x0000ffff,
9096 +
9097 + MIIMRDD_rdata_b = 0,
9098 + MIIMRDD_rdata_m = 0x0000ffff,
9099 +
9100 + MIIMIND_bsy_b = 0,
9101 + MIIMIND_bsy_m = 0x00000001,
9102 + MIIMIND_scn_b = 1,
9103 + MIIMIND_scn_m = 0x00000002,
9104 + MIIMIND_nv_b = 2,
9105 + MIIMIND_nv_m = 0x00000004,
9106 +
9107 +} ;
9108 +
9109 +/*
9110 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9111 + */
9112 +enum
9113 +{
9114 + ETHRX_fd_b = 0,
9115 + ETHRX_fd_m = 0x00000001,
9116 + ETHRX_ld_b = 1,
9117 + ETHRX_ld_m = 0x00000002,
9118 + ETHRX_rok_b = 2,
9119 + ETHRX_rok_m = 0x00000004,
9120 + ETHRX_fm_b = 3,
9121 + ETHRX_fm_m = 0x00000008,
9122 + ETHRX_mp_b = 4,
9123 + ETHRX_mp_m = 0x00000010,
9124 + ETHRX_bp_b = 5,
9125 + ETHRX_bp_m = 0x00000020,
9126 + ETHRX_vlt_b = 6,
9127 + ETHRX_vlt_m = 0x00000040,
9128 + ETHRX_cf_b = 7,
9129 + ETHRX_cf_m = 0x00000080,
9130 + ETHRX_ovr_b = 8,
9131 + ETHRX_ovr_m = 0x00000100,
9132 + ETHRX_crc_b = 9,
9133 + ETHRX_crc_m = 0x00000200,
9134 + ETHRX_cv_b = 10,
9135 + ETHRX_cv_m = 0x00000400,
9136 + ETHRX_db_b = 11,
9137 + ETHRX_db_m = 0x00000800,
9138 + ETHRX_le_b = 12,
9139 + ETHRX_le_m = 0x00001000,
9140 + ETHRX_lor_b = 13,
9141 + ETHRX_lor_m = 0x00002000,
9142 + ETHRX_ces_b = 14,
9143 + ETHRX_ces_m = 0x00004000,
9144 + ETHRX_length_b = 16,
9145 + ETHRX_length_m = 0xffff0000,
9146 +
9147 + ETHTX_fd_b = 0,
9148 + ETHTX_fd_m = 0x00000001,
9149 + ETHTX_ld_b = 1,
9150 + ETHTX_ld_m = 0x00000002,
9151 + ETHTX_oen_b = 2,
9152 + ETHTX_oen_m = 0x00000004,
9153 + ETHTX_pen_b = 3,
9154 + ETHTX_pen_m = 0x00000008,
9155 + ETHTX_cen_b = 4,
9156 + ETHTX_cen_m = 0x00000010,
9157 + ETHTX_hen_b = 5,
9158 + ETHTX_hen_m = 0x00000020,
9159 + ETHTX_tok_b = 6,
9160 + ETHTX_tok_m = 0x00000040,
9161 + ETHTX_mp_b = 7,
9162 + ETHTX_mp_m = 0x00000080,
9163 + ETHTX_bp_b = 8,
9164 + ETHTX_bp_m = 0x00000100,
9165 + ETHTX_und_b = 9,
9166 + ETHTX_und_m = 0x00000200,
9167 + ETHTX_of_b = 10,
9168 + ETHTX_of_m = 0x00000400,
9169 + ETHTX_ed_b = 11,
9170 + ETHTX_ed_m = 0x00000800,
9171 + ETHTX_ec_b = 12,
9172 + ETHTX_ec_m = 0x00001000,
9173 + ETHTX_lc_b = 13,
9174 + ETHTX_lc_m = 0x00002000,
9175 + ETHTX_td_b = 14,
9176 + ETHTX_td_m = 0x00004000,
9177 + ETHTX_crc_b = 15,
9178 + ETHTX_crc_m = 0x00008000,
9179 + ETHTX_le_b = 16,
9180 + ETHTX_le_m = 0x00010000,
9181 + ETHTX_cc_b = 17,
9182 + ETHTX_cc_m = 0x001E0000,
9183 +} ;
9184 +#endif //__IDT_RC32438_ETH_H__
9185 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9186 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 1970-01-01 01:00:00.000000000 +0100
9187 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 2006-03-20 14:25:10.000000000 +0100
9188 @@ -0,0 +1,72 @@
9189 +/**************************************************************************
9190 + *
9191 + * BRIEF MODULE DESCRIPTION
9192 + * macros for IDT EB438 ethernet
9193 + *
9194 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9195 + *
9196 + * This program is free software; you can redistribute it and/or modify it
9197 + * under the terms of the GNU General Public License as published by the
9198 + * Free Software Foundation; either version 2 of the License, or (at your
9199 + * option) any later version.
9200 + *
9201 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9202 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9203 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9204 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9205 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9206 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9207 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9208 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9209 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9210 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9211 + *
9212 + * You should have received a copy of the GNU General Public License along
9213 + * with this program; if not, write to the Free Software Foundation, Inc.,
9214 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9215 + *
9216 + *
9217 + **************************************************************************
9218 + * May 2004 P. Sadik.
9219 + *
9220 + * Initial Release
9221 + *
9222 + *
9223 + *
9224 + **************************************************************************
9225 + */
9226 +
9227 +#ifndef __IDT_RC32438_ETH_V_H__
9228 +#define __IDT_RC32438_ETH_V_H__
9229 +#include <asm/idt-boards/rc32438/rc32438_eth.h>
9230 +
9231 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
9232 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
9233 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
9234 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
9235 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
9236 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
9237 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
9238 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
9239 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
9240 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
9241 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
9242 +
9243 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
9244 +
9245 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
9246 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
9247 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
9248 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
9249 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
9250 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
9251 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
9252 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
9253 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
9254 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
9255 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
9256 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
9257 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
9258 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
9259 +
9260 +#endif //__IDT_RC32438_ETH_V_H__
9261 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9262 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 1970-01-01 01:00:00.000000000 +0100
9263 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 2006-03-20 14:25:10.000000000 +0100
9264 @@ -0,0 +1,257 @@
9265 +/**************************************************************************
9266 + *
9267 + * BRIEF MODULE DESCRIPTION
9268 + * Definitions for IDT RC32438 GPIO.
9269 + *
9270 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9271 + *
9272 + * This program is free software; you can redistribute it and/or modify it
9273 + * under the terms of the GNU General Public License as published by the
9274 + * Free Software Foundation; either version 2 of the License, or (at your
9275 + * option) any later version.
9276 + *
9277 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9278 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9279 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9280 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9281 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9282 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9283 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9284 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9285 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9286 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9287 + *
9288 + * You should have received a copy of the GNU General Public License along
9289 + * with this program; if not, write to the Free Software Foundation, Inc.,
9290 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9291 + *
9292 + *
9293 + **************************************************************************
9294 + * May 2004 P. Sadik.
9295 + *
9296 + * Initial Release
9297 + *
9298 + *
9299 + *
9300 + **************************************************************************
9301 + */
9302 +#ifndef __IDT_RC32438_GPIO_H__
9303 +#define __IDT_RC32438_GPIO_H__
9304 +enum
9305 +{
9306 + GPIO0_PhysicalAddress = 0x18048000,
9307 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
9308 +
9309 + GPIO0_VirtualAddress = 0xb8048000,
9310 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
9311 +} ;
9312 +
9313 +typedef struct
9314 +{
9315 + u32 gpiofunc; /* GPIO Function Register
9316 + * gpiofunc[x]==0 bit = gpio
9317 + * func[x]==1 bit = altfunc
9318 + */
9319 + u32 gpiocfg; /* GPIO Configuration Register
9320 + * gpiocfg[x]==0 bit = input
9321 + * gpiocfg[x]==1 bit = output
9322 + */
9323 + u32 gpiod; /* GPIO Data Register
9324 + * gpiod[x] read/write gpio pinX status
9325 + */
9326 + u32 gpioilevel; /* GPIO Interrupt Status Register
9327 + * interrupt level (see gpioistat)
9328 + */
9329 + u32 gpioistat; /* Gpio Interrupt Status Register
9330 + * istat[x] = (gpiod[x] == level[x])
9331 + * cleared in ISR (STICKY bits)
9332 + */
9333 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
9334 +} volatile * GPIO_t ;
9335 +
9336 +typedef enum
9337 +{
9338 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
9339 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
9340 + GPIO_input_v = 0, // gpiocfg use pin as input.
9341 + GPIO_output_v = 1, // gpiocfg use pin as output.
9342 + GPIO_pin0_b = 0,
9343 + GPIO_pin0_m = 0x00000001,
9344 + GPIO_pin1_b = 1,
9345 + GPIO_pin1_m = 0x00000002,
9346 + GPIO_pin2_b = 2,
9347 + GPIO_pin2_m = 0x00000004,
9348 + GPIO_pin3_b = 3,
9349 + GPIO_pin3_m = 0x00000008,
9350 + GPIO_pin4_b = 4,
9351 + GPIO_pin4_m = 0x00000010,
9352 + GPIO_pin5_b = 5,
9353 + GPIO_pin5_m = 0x00000020,
9354 + GPIO_pin6_b = 6,
9355 + GPIO_pin6_m = 0x00000040,
9356 + GPIO_pin7_b = 7,
9357 + GPIO_pin7_m = 0x00000080,
9358 + GPIO_pin8_b = 8,
9359 + GPIO_pin8_m = 0x00000100,
9360 + GPIO_pin9_b = 9,
9361 + GPIO_pin9_m = 0x00000200,
9362 + GPIO_pin10_b = 10,
9363 + GPIO_pin10_m = 0x00000400,
9364 + GPIO_pin11_b = 11,
9365 + GPIO_pin11_m = 0x00000800,
9366 + GPIO_pin12_b = 12,
9367 + GPIO_pin12_m = 0x00001000,
9368 + GPIO_pin13_b = 13,
9369 + GPIO_pin13_m = 0x00002000,
9370 + GPIO_pin14_b = 14,
9371 + GPIO_pin14_m = 0x00004000,
9372 + GPIO_pin15_b = 15,
9373 + GPIO_pin15_m = 0x00008000,
9374 + GPIO_pin16_b = 16,
9375 + GPIO_pin16_m = 0x00010000,
9376 + GPIO_pin17_b = 17,
9377 + GPIO_pin17_m = 0x00020000,
9378 + GPIO_pin18_b = 18,
9379 + GPIO_pin18_m = 0x00040000,
9380 + GPIO_pin19_b = 19,
9381 + GPIO_pin19_m = 0x00080000,
9382 + GPIO_pin20_b = 20,
9383 + GPIO_pin20_m = 0x00100000,
9384 + GPIO_pin21_b = 21,
9385 + GPIO_pin21_m = 0x00200000,
9386 + GPIO_pin22_b = 22,
9387 + GPIO_pin22_m = 0x00400000,
9388 + GPIO_pin23_b = 23,
9389 + GPIO_pin23_m = 0x00800000,
9390 + GPIO_pin24_b = 24,
9391 + GPIO_pin24_m = 0x01000000,
9392 + GPIO_pin25_b = 25,
9393 + GPIO_pin25_m = 0x02000000,
9394 + GPIO_pin26_b = 26,
9395 + GPIO_pin26_m = 0x04000000,
9396 + GPIO_pin27_b = 27,
9397 + GPIO_pin27_m = 0x08000000,
9398 + GPIO_pin28_b = 28,
9399 + GPIO_pin28_m = 0x10000000,
9400 + GPIO_pin29_b = 29,
9401 + GPIO_pin29_m = 0x20000000,
9402 + GPIO_pin30_b = 30,
9403 + GPIO_pin30_m = 0x40000000,
9404 + GPIO_pin31_b = 31,
9405 + GPIO_pin31_m = 0x80000000,
9406 +
9407 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
9408 +
9409 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
9410 + GPIO_u0sout_m = GPIO_pin0_m,
9411 + GPIO_u0sout_cfg_v = GPIO_output_v,
9412 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
9413 + GPIO_u0sinp_m = GPIO_pin1_m,
9414 + GPIO_u0sinp_cfg_v = GPIO_input_v,
9415 + GPIO_u0rin_b = GPIO_pin2_b, // UART 0 ring indic.
9416 + GPIO_u0rin_m = GPIO_pin2_m,
9417 + GPIO_u0rin_cfg_v = GPIO_input_v,
9418 + GPIO_u0dcdn_b = GPIO_pin3_b, // UART 0 data carr.det.
9419 + GPIO_u0dcdn_m = GPIO_pin3_m,
9420 + GPIO_u0dcdn_cfg_v = GPIO_input_v,
9421 + GPIO_u0dtrn_b = GPIO_pin4_b, // UART 0 data term rdy.
9422 + GPIO_u0dtrn_m = GPIO_pin4_m,
9423 + GPIO_u0dtrn_cfg_v = GPIO_output_v,
9424 + GPIO_u0dsrn_b = GPIO_pin5_b, // UART 0 data set rdy.
9425 + GPIO_u0dsrn_m = GPIO_pin5_m,
9426 + GPIO_u0dsrn_cfg_v = GPIO_input_v,
9427 + GPIO_u0rtsn_b = GPIO_pin6_b, // UART 0 req. to send.
9428 + GPIO_u0rtsn_m = GPIO_pin6_m,
9429 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
9430 + GPIO_u0ctsn_b = GPIO_pin7_b, // UART 0 clear to send.
9431 + GPIO_u0ctsn_m = GPIO_pin7_m,
9432 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
9433 +
9434 + GPIO_u1sout_b = GPIO_pin8_b, // UART 1 serial out.
9435 + GPIO_u1sout_m = GPIO_pin8_m,
9436 + GPIO_u1sout_cfg_v = GPIO_output_v,
9437 + GPIO_u1sinp_b = GPIO_pin9_b, // UART 1 serial in.
9438 + GPIO_u1sinp_m = GPIO_pin9_m,
9439 + GPIO_u1sinp_cfg_v = GPIO_input_v,
9440 + GPIO_u1dtrn_b = GPIO_pin10_b, // UART 1 data term rdy.
9441 + GPIO_u1dtrn_m = GPIO_pin10_m,
9442 + GPIO_u1dtrn_cfg_v = GPIO_output_v,
9443 + GPIO_u1dsrn_b = GPIO_pin11_b, // UART 1 data set rdy.
9444 + GPIO_u1dsrn_m = GPIO_pin11_m,
9445 + GPIO_u1dsrn_cfg_v = GPIO_input_v,
9446 + GPIO_u1rtsn_b = GPIO_pin12_b, // UART 1 req. to send.
9447 + GPIO_u1rtsn_m = GPIO_pin12_m,
9448 + GPIO_u1rtsn_cfg_v = GPIO_output_v,
9449 + GPIO_u1ctsn_b = GPIO_pin13_b, // UART 1 clear to send.
9450 + GPIO_u1ctsn_m = GPIO_pin13_m,
9451 + GPIO_u1ctsn_cfg_v = GPIO_input_v,
9452 +
9453 + GPIO_dmareqn0_b = GPIO_pin14_b, // Ext. DMA 0 request
9454 + GPIO_dmareqn0_m = GPIO_pin14_m,
9455 + GPIO_dmareqn0_cfg_v = GPIO_input_v,
9456 +
9457 + GPIO_dmareqn1_b = GPIO_pin15_b, // Ext. DMA 1 request
9458 + GPIO_dmareqn1_m = GPIO_pin15_m,
9459 + GPIO_dmareqn1_cfg_v = GPIO_input_v,
9460 +
9461 + GPIO_dmadonen0_b = GPIO_pin16_b, // Ext. DMA 0 done
9462 + GPIO_dmadonen0_m = GPIO_pin16_m,
9463 + GPIO_dmadonen0_cfg_v = GPIO_input_v,
9464 +
9465 + GPIO_dmadonen1_b = GPIO_pin17_b, // Ext. DMA 1 done
9466 + GPIO_dmadonen1_m = GPIO_pin17_m,
9467 + GPIO_dmadonen1_cfg_v = GPIO_input_v,
9468 +
9469 + GPIO_dmafinn0_b = GPIO_pin18_b, // Ext. DMA 0 finished
9470 + GPIO_dmafinn0_m = GPIO_pin18_m,
9471 + GPIO_dmafinn0_cfg_v = GPIO_output_v,
9472 +
9473 + GPIO_dmafinn1_b = GPIO_pin19_b, // Ext. DMA 1 finished
9474 + GPIO_dmafinn1_m = GPIO_pin19_m,
9475 + GPIO_dmafinn1_cfg_v = GPIO_output_v,
9476 +
9477 + GPIO_maddr22_b = GPIO_pin20_b, // M&P bus bit 22.
9478 + GPIO_maddr22_m = GPIO_pin20_m,
9479 + GPIO_maddr22_cfg_v = GPIO_output_v,
9480 +
9481 + GPIO_maddr23_b = GPIO_pin21_b, // M&P bus bit 23.
9482 + GPIO_maddr23_m = GPIO_pin21_m,
9483 + GPIO_maddr23_cfg_v = GPIO_output_v,
9484 +
9485 + GPIO_maddr24_b = GPIO_pin22_b, // M&P bus bit 24.
9486 + GPIO_maddr24_m = GPIO_pin22_m,
9487 + GPIO_maddr24_cfg_v = GPIO_output_v,
9488 +
9489 + GPIO_maddr25_b = GPIO_pin23_b, // M&P bus bit 25.
9490 + GPIO_maddr25_m = GPIO_pin23_m,
9491 + GPIO_maddr25_cfg_v = GPIO_output_v,
9492 +
9493 + GPIO_afspare6_b = GPIO_pin24_b, // reserved.
9494 + GPIO_afspare6_m = GPIO_pin24_m,
9495 + GPIO_afspare6_cfg_v = GPIO_input_v,
9496 + GPIO_afspare5_b = GPIO_pin25_b, // reserved.
9497 + GPIO_afspare5_m = GPIO_pin25_m,
9498 + GPIO_afspare5_cfg_v = GPIO_input_v,
9499 + GPIO_afspare4_b = GPIO_pin26_b, // reserved.
9500 + GPIO_afspare4_m = GPIO_pin26_m,
9501 + GPIO_afspare4_cfg_v = GPIO_input_v,
9502 + GPIO_afspare3_b = GPIO_pin27_b, // reserved.
9503 + GPIO_afspare3_m = GPIO_pin27_m,
9504 + GPIO_afspare3_cfg_v = GPIO_input_v,
9505 + GPIO_afspare2_b = GPIO_pin28_b, // reserved.
9506 + GPIO_afspare2_m = GPIO_pin28_m,
9507 + GPIO_afspare2_cfg_v = GPIO_input_v,
9508 + GPIO_afspare1_b = GPIO_pin29_b, // reserved.
9509 + GPIO_afspare1_m = GPIO_pin29_m,
9510 + GPIO_afspare1_cfg_v = GPIO_input_v,
9511 +
9512 + GPIO_pcimuintn_b = GPIO_pin30_b, // PCI messaging int.
9513 + GPIO_pcimuintn_m = GPIO_pin30_m,
9514 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
9515 +
9516 + GPIO_rngclk_b = GPIO_pin31_b, // RNG external clock
9517 + GPIO_rngclk_m = GPIO_pin31_m,
9518 + GPIO_rncclk_cfg_v = GPIO_input_v,
9519 +} GPIO_DEFS_t;
9520 +
9521 +#endif //__IDT_RC32438_GPIO_H__
9522 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9523 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438.h 1970-01-01 01:00:00.000000000 +0100
9524 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h 2006-03-20 14:25:10.000000000 +0100
9525 @@ -0,0 +1,152 @@
9526 +/**************************************************************************
9527 + *
9528 + * BRIEF MODULE DESCRIPTION
9529 + * Definitions for IDT RC32438 CPU.
9530 + *
9531 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9532 + *
9533 + * This program is free software; you can redistribute it and/or modify it
9534 + * under the terms of the GNU General Public License as published by the
9535 + * Free Software Foundation; either version 2 of the License, or (at your
9536 + * option) any later version.
9537 + *
9538 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9539 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9540 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9541 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9542 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9543 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9544 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9545 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9546 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9547 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9548 + *
9549 + * You should have received a copy of the GNU General Public License along
9550 + * with this program; if not, write to the Free Software Foundation, Inc.,
9551 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9552 + *
9553 + *
9554 + **************************************************************************
9555 + * May 2004 P. Sadik.
9556 + *
9557 + * Initial Release
9558 + *
9559 + *
9560 + *
9561 + **************************************************************************
9562 + */
9563 +
9564 +#ifndef __IDT_RC32438_H__
9565 +#define __IDT_RC32438_H__
9566 +#include <linux/config.h>
9567 +#include <linux/delay.h>
9568 +#include <asm/io.h>
9569 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9570 +
9571 +#define RC32438_REG_BASE 0x18000000
9572 +
9573 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9574 +#define idttimer ((volatile TIM_t) TIM0_VirtualAddress)
9575 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
9576 +
9577 +#define IDT_CLOCK_MULT 2
9578 +#define MIPS_CPU_TIMER_IRQ 7
9579 +/* Interrupt Controller */
9580 +#define IC_GROUP0_PEND (RC32438_REG_BASE + 0x38000)
9581 +#define IC_GROUP0_MASK (RC32438_REG_BASE + 0x38008)
9582 +#define IC_GROUP_OFFSET 0x0C
9583 +#define RTC_BASE 0xAC0801FF0
9584 +
9585 +#define NUM_INTR_GROUPS 5
9586 +/* 16550 UARTs */
9587 +
9588 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
9589 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9590 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9591 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9592 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9593 +
9594 +#ifdef __MIPSEB__
9595 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9596 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9597 +#else
9598 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9599 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9600 +#endif
9601 +
9602 +#define RC32438_UART0_IRQ GROUP3_IRQ_BASE + 0
9603 +#define RC32438_UART1_IRQ GROUP3_IRQ_BASE + 3
9604 +
9605 +#define RC32438_NR_IRQS (GROUP4_IRQ_BASE + 32)
9606 +
9607 +
9608 +
9609 +/* cpu pipeline flush */
9610 +static inline void rc32438_sync(void)
9611 +{
9612 + __asm__ volatile ("sync");
9613 +}
9614 +
9615 +static inline void rc32438_sync_udelay(int us)
9616 +{
9617 + __asm__ volatile ("sync");
9618 + udelay(us);
9619 +}
9620 +
9621 +static inline void rc32438_sync_delay(int ms)
9622 +{
9623 + __asm__ volatile ("sync");
9624 + mdelay(ms);
9625 +}
9626 +
9627 +/*
9628 + * Macros to access internal RC32438 registers. No byte
9629 + * swapping should be done when accessing the internal
9630 + * registers.
9631 + */
9632 +
9633 +#define rc32438_readb __raw_readb
9634 +#define rc32438_readw __raw_readw
9635 +#define rc32438_readl __raw_readl
9636 +
9637 +#define rc32438_writeb __raw_writeb
9638 +#define rc32438_writew __raw_writew
9639 +#define rc32438_writel __raw_writel
9640 +
9641 +/*
9642 + * C access to CLZ and CLO instructions
9643 + * (count leading zeroes/ones).
9644 + */
9645 +static inline int rc32438_clz(unsigned long val)
9646 +{
9647 + int ret;
9648 + __asm__ volatile (
9649 + ".set\tnoreorder\n\t"
9650 + ".set\tnoat\n\t"
9651 + ".set\tmips32\n\t"
9652 + "clz\t%0,%1\n\t"
9653 + ".set\tmips0\n\t"
9654 + ".set\tat\n\t"
9655 + ".set\treorder"
9656 + : "=r" (ret)
9657 + : "r" (val));
9658 +
9659 + return ret;
9660 +}
9661 +static inline int rc32438_clo(unsigned long val)
9662 +{
9663 + int ret;
9664 + __asm__ volatile (
9665 + ".set\tnoreorder\n\t"
9666 + ".set\tnoat\n\t"
9667 + ".set\tmips32\n\t"
9668 + "clo\t%0,%1\n\t"
9669 + ".set\tmips0\n\t"
9670 + ".set\tat\n\t"
9671 + ".set\treorder"
9672 + : "=r" (ret)
9673 + : "r" (val));
9674 +
9675 + return ret;
9676 +}
9677 +#endif //__IDT_RC32438_H__
9678 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9679 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 1970-01-01 01:00:00.000000000 +0100
9680 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-03-20 14:25:10.000000000 +0100
9681 @@ -0,0 +1,510 @@
9682 +/**************************************************************************
9683 + *
9684 + * BRIEF MODULE DESCRIPTION
9685 + * Definitions for IDT RC32438 PCI.
9686 + *
9687 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9688 + *
9689 + * This program is free software; you can redistribute it and/or modify it
9690 + * under the terms of the GNU General Public License as published by the
9691 + * Free Software Foundation; either version 2 of the License, or (at your
9692 + * option) any later version.
9693 + *
9694 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9695 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9696 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9697 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9698 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9699 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9700 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9701 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9702 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9703 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9704 + *
9705 + * You should have received a copy of the GNU General Public License along
9706 + * with this program; if not, write to the Free Software Foundation, Inc.,
9707 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9708 + *
9709 + *
9710 + **************************************************************************
9711 + * May 2004 P. Sadik
9712 + *
9713 + * Initial Release
9714 + *
9715 + *
9716 + *
9717 + **************************************************************************
9718 + */
9719 +
9720 +enum
9721 +{
9722 + PCI0_PhysicalAddress = 0x18080000,
9723 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
9724 +
9725 + PCI0_VirtualAddress = 0xb8080000,
9726 + PCI_VirtualAddress = PCI0_VirtualAddress,
9727 +} ;
9728 +
9729 +enum
9730 +{
9731 + PCI_LbaCount = 4, // Local base addresses.
9732 +} ;
9733 +
9734 +typedef struct
9735 +{
9736 + u32 a ; // Address.
9737 + u32 c ; // Control.
9738 + u32 m ; // mapping.
9739 +} PCI_Map_s ;
9740 +
9741 +typedef struct
9742 +{
9743 + u32 pcic ;
9744 + u32 pcis ;
9745 + u32 pcism ;
9746 + u32 pcicfga ;
9747 + u32 pcicfgd ;
9748 + PCI_Map_s pcilba [PCI_LbaCount] ;
9749 + u32 pcidac ;
9750 + u32 pcidas ;
9751 + u32 pcidasm ;
9752 + u32 pcidad ;
9753 + u32 pcidma8c ;
9754 + u32 pcidma9c ;
9755 + u32 pcitc ;
9756 +} volatile *PCI_t ;
9757 +
9758 +// PCI messaging unit.
9759 +enum
9760 +{
9761 + PCIM_Count = 2,
9762 +} ;
9763 +typedef struct
9764 +{
9765 + u32 pciim [PCIM_Count] ;
9766 + u32 pciom [PCIM_Count] ;
9767 + u32 pciid ;
9768 + u32 pciiic ;
9769 + u32 pciiim ;
9770 + u32 pciiod ;
9771 + u32 pciioic ;
9772 + u32 pciioim ;
9773 +} volatile *PCIM_t ;
9774 +
9775 +/*******************************************************************************
9776 + *
9777 + * PCI Control Register
9778 + *
9779 + ******************************************************************************/
9780 +enum
9781 +{
9782 + PCIC_en_b = 0,
9783 + PCIC_en_m = 0x00000001,
9784 + PCIC_tnr_b = 1,
9785 + PCIC_tnr_m = 0x00000002,
9786 + PCIC_sce_b = 2,
9787 + PCIC_sce_m = 0x00000004,
9788 + PCIC_ien_b = 3,
9789 + PCIC_ien_m = 0x00000008,
9790 + PCIC_aaa_b = 4,
9791 + PCIC_aaa_m = 0x00000010,
9792 + PCIC_eap_b = 5,
9793 + PCIC_eap_m = 0x00000020,
9794 + PCIC_pcim_b = 6,
9795 + PCIC_pcim_m = 0x000001c0,
9796 + PCIC_pcim_disabled_v = 0,
9797 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
9798 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
9799 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
9800 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
9801 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
9802 + PCIC_pcim_reserved6_v = 6,
9803 + PCIC_pcim_reserved7_v = 7,
9804 + PCIC_igm_b = 9,
9805 + PCIC_igm_m = 0x00000200,
9806 +} ;
9807 +
9808 +/*******************************************************************************
9809 + *
9810 + * PCI Status Register
9811 + *
9812 + ******************************************************************************/
9813 +enum {
9814 + PCIS_eed_b = 0,
9815 + PCIS_eed_m = 0x00000001,
9816 + PCIS_wr_b = 1,
9817 + PCIS_wr_m = 0x00000002,
9818 + PCIS_nmi_b = 2,
9819 + PCIS_nmi_m = 0x00000004,
9820 + PCIS_ii_b = 3,
9821 + PCIS_ii_m = 0x00000008,
9822 + PCIS_cwe_b = 4,
9823 + PCIS_cwe_m = 0x00000010,
9824 + PCIS_cre_b = 5,
9825 + PCIS_cre_m = 0x00000020,
9826 + PCIS_mdpe_b = 6,
9827 + PCIS_mdpe_m = 0x00000040,
9828 + PCIS_sta_b = 7,
9829 + PCIS_sta_m = 0x00000080,
9830 + PCIS_rta_b = 8,
9831 + PCIS_rta_m = 0x00000100,
9832 + PCIS_rma_b = 9,
9833 + PCIS_rma_m = 0x00000200,
9834 + PCIS_sse_b = 10,
9835 + PCIS_sse_m = 0x00000400,
9836 + PCIS_ose_b = 11,
9837 + PCIS_ose_m = 0x00000800,
9838 + PCIS_pe_b = 12,
9839 + PCIS_pe_m = 0x00001000,
9840 + PCIS_tae_b = 13,
9841 + PCIS_tae_m = 0x00002000,
9842 + PCIS_rle_b = 14,
9843 + PCIS_rle_m = 0x00004000,
9844 + PCIS_bme_b = 15,
9845 + PCIS_bme_m = 0x00008000,
9846 + PCIS_prd_b = 16,
9847 + PCIS_prd_m = 0x00010000,
9848 + PCIS_rip_b = 17,
9849 + PCIS_rip_m = 0x00020000,
9850 +} ;
9851 +
9852 +/*******************************************************************************
9853 + *
9854 + * PCI Status Mask Register
9855 + *
9856 + ******************************************************************************/
9857 +enum {
9858 + PCISM_eed_b = 0,
9859 + PCISM_eed_m = 0x00000001,
9860 + PCISM_wr_b = 1,
9861 + PCISM_wr_m = 0x00000002,
9862 + PCISM_nmi_b = 2,
9863 + PCISM_nmi_m = 0x00000004,
9864 + PCISM_ii_b = 3,
9865 + PCISM_ii_m = 0x00000008,
9866 + PCISM_cwe_b = 4,
9867 + PCISM_cwe_m = 0x00000010,
9868 + PCISM_cre_b = 5,
9869 + PCISM_cre_m = 0x00000020,
9870 + PCISM_mdpe_b = 6,
9871 + PCISM_mdpe_m = 0x00000040,
9872 + PCISM_sta_b = 7,
9873 + PCISM_sta_m = 0x00000080,
9874 + PCISM_rta_b = 8,
9875 + PCISM_rta_m = 0x00000100,
9876 + PCISM_rma_b = 9,
9877 + PCISM_rma_m = 0x00000200,
9878 + PCISM_sse_b = 10,
9879 + PCISM_sse_m = 0x00000400,
9880 + PCISM_ose_b = 11,
9881 + PCISM_ose_m = 0x00000800,
9882 + PCISM_pe_b = 12,
9883 + PCISM_pe_m = 0x00001000,
9884 + PCISM_tae_b = 13,
9885 + PCISM_tae_m = 0x00002000,
9886 + PCISM_rle_b = 14,
9887 + PCISM_rle_m = 0x00004000,
9888 + PCISM_bme_b = 15,
9889 + PCISM_bme_m = 0x00008000,
9890 + PCISM_prd_b = 16,
9891 + PCISM_prd_m = 0x00010000,
9892 + PCISM_rip_b = 17,
9893 + PCISM_rip_m = 0x00020000,
9894 +} ;
9895 +
9896 +/*******************************************************************************
9897 + *
9898 + * PCI Configuration Address Register
9899 + *
9900 + ******************************************************************************/
9901 +enum {
9902 + PCICFGA_reg_b = 2,
9903 + PCICFGA_reg_m = 0x000000fc,
9904 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
9905 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
9906 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
9907 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
9908 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
9909 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
9910 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
9911 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
9912 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9913 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
9914 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
9915 + PCICFGA_reg_pba0m_v = 0x48>>2,
9916 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
9917 + PCICFGA_reg_pba1m_v = 0x50>>2,
9918 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
9919 + PCICFGA_reg_pba2m_v = 0x58>>2,
9920 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
9921 + PCICFGA_reg_pba3m_v = 0x60>>2,
9922 + PCICFGA_reg_pmgt_v = 0x64>>2,
9923 + PCICFGA_func_b = 8,
9924 + PCICFGA_func_m = 0x00000700,
9925 + PCICFGA_dev_b = 11,
9926 + PCICFGA_dev_m = 0x0000f800,
9927 + PCICFGA_dev_internal_v = 0,
9928 + PCICFGA_bus_b = 16,
9929 + PCICFGA_bus_m = 0x00ff0000,
9930 + PCICFGA_bus_type0_v = 0, //local bus
9931 + PCICFGA_en_b = 31, // read only
9932 + PCICFGA_en_m = 0x80000000,
9933 +} ;
9934 +
9935 +enum {
9936 + PCFGID_vendor_b = 0,
9937 + PCFGID_vendor_m = 0x0000ffff,
9938 + PCFGID_vendor_IDT_v = 0x111d,
9939 + PCFGID_device_b = 16,
9940 + PCFGID_device_m = 0xffff0000,
9941 + PCFGID_device_Acaciade_v = 0x0207,
9942 +
9943 + PCFG04_command_ioena_b = 1,
9944 + PCFG04_command_ioena_m = 0x00000001,
9945 + PCFG04_command_memena_b = 2,
9946 + PCFG04_command_memena_m = 0x00000002,
9947 + PCFG04_command_bmena_b = 3,
9948 + PCFG04_command_bmena_m = 0x00000004,
9949 + PCFG04_command_mwinv_b = 5,
9950 + PCFG04_command_mwinv_m = 0x00000010,
9951 + PCFG04_command_parena_b = 7,
9952 + PCFG04_command_parena_m = 0x00000040,
9953 + PCFG04_command_serrena_b = 9,
9954 + PCFG04_command_serrena_m = 0x00000100,
9955 + PCFG04_command_fastbbena_b = 10,
9956 + PCFG04_command_fastbbena_m = 0x00000200,
9957 + PCFG04_status_b = 16,
9958 + PCFG04_status_m = 0xffff0000,
9959 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
9960 + PCFG04_status_66MHz_m = 0x00200000,
9961 + PCFG04_status_fbb_b = 23,
9962 + PCFG04_status_fbb_m = 0x00800000,
9963 + PCFG04_status_mdpe_b = 24,
9964 + PCFG04_status_mdpe_m = 0x01000000,
9965 + PCFG04_status_dst_b = 25,
9966 + PCFG04_status_dst_m = 0x06000000,
9967 + PCFG04_status_sta_b = 27,
9968 + PCFG04_status_sta_m = 0x08000000,
9969 + PCFG04_status_rta_b = 28,
9970 + PCFG04_status_rta_m = 0x10000000,
9971 + PCFG04_status_rma_b = 29,
9972 + PCFG04_status_rma_m = 0x20000000,
9973 + PCFG04_status_sse_b = 30,
9974 + PCFG04_status_sse_m = 0x40000000,
9975 + PCFG04_status_pe_b = 31,
9976 + PCFG04_status_pe_m = 0x40000000,
9977 +
9978 + PCFG08_revId_b = 0,
9979 + PCFG08_revId_m = 0x000000ff,
9980 + PCFG08_classCode_b = 0,
9981 + PCFG08_classCode_m = 0xffffff00,
9982 + PCFG08_classCode_bridge_v = 06,
9983 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
9984 + PCFG0C_cacheline_b = 0,
9985 + PCFG0C_cacheline_m = 0x000000ff,
9986 + PCFG0C_masterLatency_b = 8,
9987 + PCFG0C_masterLatency_m = 0x0000ff00,
9988 + PCFG0C_headerType_b = 16,
9989 + PCFG0C_headerType_m = 0x00ff0000,
9990 + PCFG0C_bist_b = 24,
9991 + PCFG0C_bist_m = 0xff000000,
9992 +
9993 + PCIPBA_msi_b = 0,
9994 + PCIPBA_msi_m = 0x00000001,
9995 + PCIPBA_p_b = 3,
9996 + PCIPBA_p_m = 0x00000004,
9997 + PCIPBA_baddr_b = 8,
9998 + PCIPBA_baddr_m = 0xffffff00,
9999 +
10000 + PCFGSS_vendorId_b = 0,
10001 + PCFGSS_vendorId_m = 0x0000ffff,
10002 + PCFGSS_id_b = 16,
10003 + PCFGSS_id_m = 0xffff0000,
10004 +
10005 + PCFG3C_interruptLine_b = 0,
10006 + PCFG3C_interruptLine_m = 0x000000ff,
10007 + PCFG3C_interruptPin_b = 8,
10008 + PCFG3C_interruptPin_m = 0x0000ff00,
10009 + PCFG3C_minGrant_b = 16,
10010 + PCFG3C_minGrant_m = 0x00ff0000,
10011 + PCFG3C_maxLat_b = 24,
10012 + PCFG3C_maxLat_m = 0xff000000,
10013 +
10014 + PCIPBAC_msi_b = 0,
10015 + PCIPBAC_msi_m = 0x00000001,
10016 + PCIPBAC_p_b = 1,
10017 + PCIPBAC_p_m = 0x00000002,
10018 + PCIPBAC_size_b = 2,
10019 + PCIPBAC_size_m = 0x0000007c,
10020 + PCIPBAC_sb_b = 7,
10021 + PCIPBAC_sb_m = 0x00000080,
10022 + PCIPBAC_pp_b = 8,
10023 + PCIPBAC_pp_m = 0x00000100,
10024 + PCIPBAC_mr_b = 9,
10025 + PCIPBAC_mr_m = 0x00000600,
10026 + PCIPBAC_mr_read_v =0, //no prefetching
10027 + PCIPBAC_mr_readLine_v =1,
10028 + PCIPBAC_mr_readMult_v =2,
10029 + PCIPBAC_mrl_b = 11,
10030 + PCIPBAC_mrl_m = 0x00000800,
10031 + PCIPBAC_mrm_b = 12,
10032 + PCIPBAC_mrm_m = 0x00001000,
10033 + PCIPBAC_trp_b = 13,
10034 + PCIPBAC_trp_m = 0x00002000,
10035 +
10036 + PCFG40_trdyTimeout_b = 0,
10037 + PCFG40_trdyTimeout_m = 0x000000ff,
10038 + PCFG40_retryLim_b = 8,
10039 + PCFG40_retryLim_m = 0x0000ff00,
10040 +};
10041 +
10042 +/*******************************************************************************
10043 + *
10044 + * PCI Local Base Address [0|1|2|3] Register
10045 + *
10046 + ******************************************************************************/
10047 +enum {
10048 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
10049 + PCILBA_baddr_m = 0xffffff00,
10050 +} ;
10051 +/*******************************************************************************
10052 + *
10053 + * PCI Local Base Address Control Register
10054 + *
10055 + ******************************************************************************/
10056 +enum {
10057 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
10058 + PCILBAC_msi_m = 0x00000001,
10059 + PCILBAC_msi_mem_v = 0,
10060 + PCILBAC_msi_io_v = 1,
10061 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
10062 + PCILBAC_size_m = 0x0000007c,
10063 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
10064 + PCILBAC_sb_m = 0x00000080,
10065 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
10066 + PCILBAC_rt_m = 0x00000100,
10067 + PCILBAC_rt_noprefetch_v = 0, // mem read
10068 + PCILBAC_rt_prefetch_v = 1, // mem readline
10069 +} ;
10070 +
10071 +/*******************************************************************************
10072 + *
10073 + * PCI Local Base Address [0|1|2|3] Mapping Register
10074 + *
10075 + ******************************************************************************/
10076 +enum {
10077 + PCILBAM_maddr_b = 8,
10078 + PCILBAM_maddr_m = 0xffffff00,
10079 +} ;
10080 +
10081 +/*******************************************************************************
10082 + *
10083 + * PCI Decoupled Access Control Register
10084 + *
10085 + ******************************************************************************/
10086 +enum {
10087 + PCIDAC_den_b = 0,
10088 + PCIDAC_den_m = 0x00000001,
10089 +} ;
10090 +
10091 +/*******************************************************************************
10092 + *
10093 + * PCI Decoupled Access Status Register
10094 + *
10095 + ******************************************************************************/
10096 +enum {
10097 + PCIDAS_d_b = 0,
10098 + PCIDAS_d_m = 0x00000001,
10099 + PCIDAS_b_b = 1,
10100 + PCIDAS_b_m = 0x00000002,
10101 + PCIDAS_e_b = 2,
10102 + PCIDAS_e_m = 0x00000004,
10103 + PCIDAS_ofe_b = 3,
10104 + PCIDAS_ofe_m = 0x00000008,
10105 + PCIDAS_off_b = 4,
10106 + PCIDAS_off_m = 0x00000010,
10107 + PCIDAS_ife_b = 5,
10108 + PCIDAS_ife_m = 0x00000020,
10109 + PCIDAS_iff_b = 6,
10110 + PCIDAS_iff_m = 0x00000040,
10111 +} ;
10112 +
10113 +/*******************************************************************************
10114 + *
10115 + * PCI DMA Channel 8 Configuration Register
10116 + *
10117 + ******************************************************************************/
10118 +enum
10119 +{
10120 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
10121 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
10122 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
10123 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
10124 +} ;
10125 +
10126 +/*******************************************************************************
10127 + *
10128 + * PCI DMA Channel 9 Configuration Register
10129 + *
10130 + ******************************************************************************/
10131 +enum
10132 +{
10133 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
10134 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
10135 +} ;
10136 +
10137 +/*******************************************************************************
10138 + *
10139 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10140 + *
10141 + ******************************************************************************/
10142 +enum {
10143 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
10144 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
10145 + // These are for reads (DMA channel 8)
10146 + PCIDMAD_devcmd_mr_v = 0, //memory read
10147 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
10148 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
10149 + PCIDMAD_devcmd_ior_v = 3, //I/O read
10150 + // These are for writes (DMA channel 9)
10151 + PCIDMAD_devcmd_mw_v = 0, //memory write
10152 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
10153 + PCIDMAD_devcmd_iow_v = 3, //I/O write
10154 +
10155 + // Swap byte field applies to both DMA channel 8 and 9
10156 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
10157 + PCIDMAD_sb_m = 0x01000000, // swap byte field
10158 +} ;
10159 +
10160 +
10161 +/*******************************************************************************
10162 + *
10163 + * PCI Target Control Register
10164 + *
10165 + ******************************************************************************/
10166 +enum
10167 +{
10168 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
10169 + PCITC_rtimer_m = 0x000000ff,
10170 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
10171 + PCITC_dtimer_m = 0x0000ff00,
10172 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
10173 + PCITC_rdr_m = 0x00040000,
10174 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
10175 + PCITC_ddt_m = 0x00080000,
10176 +} ;
10177 +/*******************************************************************************
10178 + *
10179 + * PCI messaging unit [applies to both inbound and outbound registers ]
10180 + *
10181 + ******************************************************************************/
10182 +enum
10183 +{
10184 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10185 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
10186 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10187 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
10188 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10189 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
10190 +};
10191 +
10192 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10193 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 1970-01-01 01:00:00.000000000 +0100
10194 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 2006-03-20 14:25:10.000000000 +0100
10195 @@ -0,0 +1,190 @@
10196 +/**************************************************************************
10197 + *
10198 + * BRIEF MODULE DESCRIPTION
10199 + * Definitions for IDT RC32438 PCI setup.
10200 + *
10201 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10202 + *
10203 + * This program is free software; you can redistribute it and/or modify it
10204 + * under the terms of the GNU General Public License as published by the
10205 + * Free Software Foundation; either version 2 of the License, or (at your
10206 + * option) any later version.
10207 + *
10208 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10209 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10210 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10211 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10212 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10213 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10214 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10215 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10216 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10217 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10218 + *
10219 + * You should have received a copy of the GNU General Public License along
10220 + * with this program; if not, write to the Free Software Foundation, Inc.,
10221 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10222 + *
10223 + *
10224 + **************************************************************************
10225 + * May 2004 P. Sadik
10226 + *
10227 + * Initial Release
10228 + *
10229 + *
10230 + *
10231 + **************************************************************************
10232 + */
10233 +
10234 +#define PCI_MSG_VirtualAddress 0xB8088010
10235 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10236 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10237 +
10238 +#define PCIM_SHFT 0x6
10239 +#define PCIM_BIT_LEN 0x7
10240 +#define PCIM_H_EA 0x3
10241 +#define PCIM_H_IA_FIX 0x4
10242 +#define PCIM_H_IA_RR 0x5
10243 +
10244 +#define PCI_ADDR_START 0x50000000
10245 +
10246 +#define CPUTOPCI_MEM_WIN 0x02000000
10247 +#define CPUTOPCI_IO_WIN 0x00100000
10248 +#define PCILBA_SIZE_SHFT 2
10249 +#define PCILBA_SIZE_MASK 0x1F
10250 +#define SIZE_256MB 0x1C
10251 +#define SIZE_128MB 0x1B
10252 +#define SIZE_64MB 0x1A
10253 +#define SIZE_32MB 0x19
10254 +#define SIZE_16MB 0x18
10255 +#define SIZE_4MB 0x16
10256 +#define SIZE_2MB 0x15
10257 +#define SIZE_1MB 0x14
10258 +#define ACACIA_CONFIG0_ADDR 0x80000000
10259 +#define ACACIA_CONFIG1_ADDR 0x80000004
10260 +#define ACACIA_CONFIG2_ADDR 0x80000008
10261 +#define ACACIA_CONFIG3_ADDR 0x8000000C
10262 +#define ACACIA_CONFIG4_ADDR 0x80000010
10263 +#define ACACIA_CONFIG5_ADDR 0x80000014
10264 +#define ACACIA_CONFIG6_ADDR 0x80000018
10265 +#define ACACIA_CONFIG7_ADDR 0x8000001C
10266 +#define ACACIA_CONFIG8_ADDR 0x80000020
10267 +#define ACACIA_CONFIG9_ADDR 0x80000024
10268 +#define ACACIA_CONFIG10_ADDR 0x80000028
10269 +#define ACACIA_CONFIG11_ADDR 0x8000002C
10270 +#define ACACIA_CONFIG12_ADDR 0x80000030
10271 +#define ACACIA_CONFIG13_ADDR 0x80000034
10272 +#define ACACIA_CONFIG14_ADDR 0x80000038
10273 +#define ACACIA_CONFIG15_ADDR 0x8000003C
10274 +#define ACACIA_CONFIG16_ADDR 0x80000040
10275 +#define ACACIA_CONFIG17_ADDR 0x80000044
10276 +#define ACACIA_CONFIG18_ADDR 0x80000048
10277 +#define ACACIA_CONFIG19_ADDR 0x8000004C
10278 +#define ACACIA_CONFIG20_ADDR 0x80000050
10279 +#define ACACIA_CONFIG21_ADDR 0x80000054
10280 +#define ACACIA_CONFIG22_ADDR 0x80000058
10281 +#define ACACIA_CONFIG23_ADDR 0x8000005C
10282 +#define ACACIA_CONFIG24_ADDR 0x80000060
10283 +#define ACACIA_CONFIG25_ADDR 0x80000064
10284 +#define ACACIA_CMD (PCFG04_command_ioena_m | \
10285 + PCFG04_command_memena_m | \
10286 + PCFG04_command_bmena_m | \
10287 + PCFG04_command_mwinv_m | \
10288 + PCFG04_command_parena_m | \
10289 + PCFG04_command_serrena_m )
10290 +
10291 +#define ACACIA_STAT (PCFG04_status_mdpe_m | \
10292 + PCFG04_status_sta_m | \
10293 + PCFG04_status_rta_m | \
10294 + PCFG04_status_rma_m | \
10295 + PCFG04_status_sse_m | \
10296 + PCFG04_status_pe_m)
10297 +
10298 +#define ACACIA_CNFG1 ((ACACIA_STAT<<16)|ACACIA_CMD)
10299 +
10300 +#define ACACIA_REVID 0
10301 +#define ACACIA_CLASS_CODE 0
10302 +#define ACACIA_CNFG2 ((ACACIA_CLASS_CODE<<8) | \
10303 + ACACIA_REVID)
10304 +
10305 +#define ACACIA_CACHE_LINE_SIZE 4
10306 +#define ACACIA_MASTER_LAT 0x3c
10307 +#define ACACIA_HEADER_TYPE 0
10308 +#define ACACIA_BIST 0
10309 +
10310 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10311 + (ACACIA_HEADER_TYPE<<16) | \
10312 + (ACACIA_MASTER_LAT<<8) | \
10313 + ACACIA_CACHE_LINE_SIZE )
10314 +
10315 +#define ACACIA_BAR0 0x00000008 /* 128 MB Memory */
10316 +#define ACACIA_BAR1 0x18800001 /* 1 MB IO */
10317 +#define ACACIA_BAR2 0x18000001 /* 2 MB IO window for Acacia
10318 + internal Registers */
10319 +#define ACACIA_BAR3 0x48000008 /* Spare 128 MB Memory */
10320 +
10321 +#define ACACIA_CNFG4 ACACIA_BAR0
10322 +#define ACACIA_CNFG5 ACACIA_BAR1
10323 +#define ACACIA_CNFG6 ACACIA_BAR2
10324 +#define ACACIA_CNFG7 ACACIA_BAR3
10325 +
10326 +#define ACACIA_SUBSYS_VENDOR_ID 0
10327 +#define ACACIA_SUBSYSTEM_ID 0
10328 +#define ACACIA_CNFG8 0
10329 +#define ACACIA_CNFG9 0
10330 +#define ACACIA_CNFG10 0
10331 +#define ACACIA_CNFG11 ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10332 + ACACIA_SUBSYSTEM_ID)
10333 +#define ACACIA_INT_LINE 1
10334 +#define ACACIA_INT_PIN 1
10335 +#define ACACIA_MIN_GNT 8
10336 +#define ACACIA_MAX_LAT 0x38
10337 +#define ACACIA_CNFG12 0
10338 +#define ACACIA_CNFG13 0
10339 +#define ACACIA_CNFG14 0
10340 +#define ACACIA_CNFG15 ((ACACIA_MAX_LAT<<24) | \
10341 + (ACACIA_MIN_GNT<<16) | \
10342 + (ACACIA_INT_PIN<<8) | \
10343 + ACACIA_INT_LINE)
10344 +#define ACACIA_RETRY_LIMIT 0x80
10345 +#define ACACIA_TRDY_LIMIT 0x80
10346 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10347 + ACACIA_TRDY_LIMIT)
10348 +#define PCI_PBAxC_R 0x0
10349 +#define PCI_PBAxC_RL 0x1
10350 +#define PCI_PBAxC_RM 0x2
10351 +#define SIZE_SHFT 2
10352 +
10353 +#define ACACIA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10354 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10355 + PCIPBAC_pp_m | \
10356 + (SIZE_128MB<<SIZE_SHFT) | \
10357 + PCIPBAC_p_m)
10358 +
10359 +#define ACACIA_CNFG17 ACACIA_PBA0C
10360 +#define ACACIA_PBA0M 0x0
10361 +#define ACACIA_CNFG18 ACACIA_PBA0M
10362 +
10363 +#define ACACIA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10364 + PCIPBAC_msi_m)
10365 +
10366 +#define ACACIA_CNFG19 ACACIA_PBA1C
10367 +#define ACACIA_PBA1M 0x0
10368 +#define ACACIA_CNFG20 ACACIA_PBA1M
10369 +
10370 +#define ACACIA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10371 + PCIPBAC_msi_m)
10372 +
10373 +#define ACACIA_CNFG21 ACACIA_PBA2C
10374 +#define ACACIA_PBA2M 0x18000000
10375 +#define ACACIA_CNFG22 ACACIA_PBA2M
10376 +#define ACACIA_PBA3C 0
10377 +#define ACACIA_CNFG23 ACACIA_PBA3C
10378 +#define ACACIA_PBA3M 0
10379 +#define ACACIA_CNFG24 ACACIA_PBA3M
10380 +
10381 +
10382 +
10383 +#define PCITC_DTIMER_VAL 8
10384 +#define PCITC_RTIMER_VAL 0x10
10385 +
10386 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10387 --- linux-2.6.16/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 1970-01-01 01:00:00.000000000 +0100
10388 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 2006-03-20 14:25:10.000000000 +0100
10389 @@ -0,0 +1,91 @@
10390 +/**************************************************************************
10391 + *
10392 + * BRIEF MODULE DESCRIPTION
10393 + * Timer register definition IDT RC32438 CPU.
10394 + *
10395 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10396 + *
10397 + * This program is free software; you can redistribute it and/or modify it
10398 + * under the terms of the GNU General Public License as published by the
10399 + * Free Software Foundation; either version 2 of the License, or (at your
10400 + * option) any later version.
10401 + *
10402 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10403 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10404 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10405 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10406 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10407 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10408 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10409 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10410 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10411 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10412 + *
10413 + * You should have received a copy of the GNU General Public License along
10414 + * with this program; if not, write to the Free Software Foundation, Inc.,
10415 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10416 + *
10417 + *
10418 + **************************************************************************
10419 + * May 2004 P. Sadik.
10420 + *
10421 + * Initial Release
10422 + *
10423 + *
10424 + *
10425 + **************************************************************************
10426 + */
10427 +
10428 +#ifndef __IDT_RC32438_TIM_H__
10429 +#define __IDT_RC32438_TIM_H__
10430 +
10431 +enum
10432 +{
10433 + TIM0_PhysicalAddress = 0x18028000,
10434 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
10435 +
10436 + TIM0_VirtualAddress = 0xb8028000,
10437 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
10438 +} ;
10439 +
10440 +enum
10441 +{
10442 + TIM_Count = 3,
10443 +} ;
10444 +
10445 +struct TIM_CNTR_s
10446 +{
10447 + u32 count ;
10448 + u32 compare ;
10449 + u32 ctc ; //use CTC_
10450 +} ;
10451 +
10452 +typedef struct TIM_s
10453 +{
10454 + struct TIM_CNTR_s tim [TIM_Count] ;
10455 + u32 rcount ; //use RCOUNT_
10456 + u32 rcompare ; //use RCOMPARE_
10457 + u32 rtc ; //use RTC_
10458 +} volatile * TIM_t ;
10459 +
10460 +enum
10461 +{
10462 + CTC_en_b = 0,
10463 + CTC_en_m = 0x00000001,
10464 + CTC_to_b = 1,
10465 + CTC_to_m = 0x00000002,
10466 +
10467 + RCOUNT_count_b = 0,
10468 + RCOUNT_count_m = 0x0000ffff,
10469 + RCOMPARE_compare_b = 0,
10470 + RCOMPARE_compare_m = 0x0000ffff,
10471 + RTC_ce_b = 0,
10472 + RTC_ce_m = 0x00000001,
10473 + RTC_to_b = 1,
10474 + RTC_to_m = 0x00000002,
10475 + RTC_rqe_b = 2,
10476 + RTC_rqe_m = 0x00000004,
10477 +
10478 +} ;
10479 +#endif //__IDT_RC32438_TIM_H__
10480 +
10481 diff -Nur linux-2.6.16/include/asm-mips/mach-generic/irq.h linux-2.6.16-owrt/include/asm-mips/mach-generic/irq.h
10482 --- linux-2.6.16/include/asm-mips/mach-generic/irq.h 2006-03-20 06:53:29.000000000 +0100
10483 +++ linux-2.6.16-owrt/include/asm-mips/mach-generic/irq.h 2006-03-20 14:25:10.000000000 +0100
10484 @@ -8,6 +8,6 @@
10485 #ifndef __ASM_MACH_GENERIC_IRQ_H
10486 #define __ASM_MACH_GENERIC_IRQ_H
10487
10488 -#define NR_IRQS 128
10489 +#define NR_IRQS 256
10490
10491 #endif /* __ASM_MACH_GENERIC_IRQ_H */
10492 diff -Nur linux-2.6.16/include/linux/init.h linux-2.6.16-owrt/include/linux/init.h
10493 --- linux-2.6.16/include/linux/init.h 2006-03-20 06:53:29.000000000 +0100
10494 +++ linux-2.6.16-owrt/include/linux/init.h 2006-03-20 14:25:10.000000000 +0100
10495 @@ -86,6 +86,8 @@
10496 static initcall_t __initcall_##fn __attribute_used__ \
10497 __attribute__((__section__(".initcall" level ".init"))) = fn
10498
10499 +#define early_initcall(fn) __define_initcall(".early1",fn)
10500 +
10501 #define core_initcall(fn) __define_initcall("1",fn)
10502 #define postcore_initcall(fn) __define_initcall("2",fn)
10503 #define arch_initcall(fn) __define_initcall("3",fn)
10504 diff -Nur linux-2.6.16/include/linux/kernel.h linux-2.6.16-owrt/include/linux/kernel.h
10505 --- linux-2.6.16/include/linux/kernel.h 2006-03-20 06:53:29.000000000 +0100
10506 +++ linux-2.6.16-owrt/include/linux/kernel.h 2006-03-20 14:25:10.000000000 +0100
10507 @@ -324,6 +324,7 @@
10508 };
10509
10510 /* Force a compilation error if condition is true */
10511 +extern void BUILD_BUG(void);
10512 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10513
10514 /* Trap pasters of __FUNCTION__ at compile-time */
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