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[openwrt/svn-archive/archive.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.16/arch/mips/aruba/Makefile linux-2.6.16-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.16/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.16-owrt/arch/mips/aruba/Makefile 2006-03-20 14:25:10.000000000 +0100
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/Makefile linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.16/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile 2006-03-20 14:25:10.000000000 +0100
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.c linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c 2006-03-20 14:25:10.000000000 +0100
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.h linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h 2006-03-20 14:25:10.000000000 +0100
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.16/arch/mips/aruba/prom.c linux-2.6.16-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.16/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.16-owrt/arch/mips/aruba/prom.c 2006-03-20 14:25:10.000000000 +0100
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.16/arch/mips/aruba/serial.c linux-2.6.16-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.16/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.16-owrt/arch/mips/aruba/serial.c 2006-03-20 14:25:10.000000000 +0100
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.16/arch/mips/aruba/setup.c linux-2.6.16-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.16/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.16-owrt/arch/mips/aruba/setup.c 2006-03-20 14:30:00.000000000 +0100
786 @@ -0,0 +1,122 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/mm.h>
827 +#include <linux/sched.h>
828 +#include <linux/irq.h>
829 +#include <asm/bootinfo.h>
830 +#include <asm/io.h>
831 +#include <linux/ioport.h>
832 +#include <asm/mipsregs.h>
833 +#include <asm/pgtable.h>
834 +#include <asm/reboot.h>
835 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
836 +#include <asm/idt-boards/rc32434/rc32434.h>
837 +#include <linux/pm.h>
838 +
839 +extern char *__init prom_getcmdline(void);
840 +
841 +extern void (*board_time_init) (void);
842 +extern void (*board_timer_setup) (struct irqaction * irq);
843 +extern void aruba_time_init(void);
844 +extern void aruba_timer_setup(struct irqaction *irq);
845 +extern void aruba_reset(void);
846 +
847 +#define epldMask ((volatile unsigned char *)0xB900000d)
848 +
849 +static void aruba_machine_restart(char *command)
850 +{
851 + switch (mips_machtype) {
852 + case MACH_ARUBA_AP70:
853 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
854 + break;
855 + case MACH_ARUBA_AP65:
856 + case MACH_ARUBA_AP60:
857 + default:
858 + /* Reset*/
859 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
860 + udelay(100);
861 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
862 + udelay(100);
863 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
864 + break;
865 + }
866 +}
867 +
868 +static void aruba_machine_halt(void)
869 +{
870 + for (;;) continue;
871 +}
872 +
873 +extern char * getenv(char *e);
874 +extern void unlock_ap60_70_flash(void);
875 +
876 +void __init plat_setup(void)
877 +{
878 + board_time_init = aruba_time_init;
879 +
880 + board_timer_setup = aruba_timer_setup;
881 +
882 + _machine_restart = aruba_machine_restart;
883 + _machine_halt = aruba_machine_halt;
884 + pm_power_off = aruba_machine_halt;
885 +
886 + set_io_port_base(KSEG1);
887 +
888 + /* Enable PCI interrupts in EPLD Mask register */
889 + *epldMask = 0x0;
890 + *(epldMask + 1) = 0x0;
891 +
892 + write_c0_wired(0);
893 + unlock_ap60_70_flash();
894 +
895 + printk("BOARD - %s\n",getenv("boardname"));
896 +
897 + return 0;
898 +}
899 +
900 +int page_is_ram(unsigned long pagenr)
901 +{
902 + return 1;
903 +}
904 +
905 +const char *get_system_type(void)
906 +{
907 + return "MIPS IDT32434 - ARUBA";
908 +}
909 diff -Nur linux-2.6.16/arch/mips/aruba/time.c linux-2.6.16-owrt/arch/mips/aruba/time.c
910 --- linux-2.6.16/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
911 +++ linux-2.6.16-owrt/arch/mips/aruba/time.c 2006-03-20 14:25:10.000000000 +0100
912 @@ -0,0 +1,108 @@
913 +/**************************************************************************
914 + *
915 + * BRIEF MODULE DESCRIPTION
916 + * timer routines for IDT EB434 boards
917 + *
918 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
919 + *
920 + * This program is free software; you can redistribute it and/or modify it
921 + * under the terms of the GNU General Public License as published by the
922 + * Free Software Foundation; either version 2 of the License, or (at your
923 + * option) any later version.
924 + *
925 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
926 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
927 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
928 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
929 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
930 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
931 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
932 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
933 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
934 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
935 + *
936 + * You should have received a copy of the GNU General Public License along
937 + * with this program; if not, write to the Free Software Foundation, Inc.,
938 + * 675 Mass Ave, Cambridge, MA 02139, USA.
939 + *
940 + *
941 + **************************************************************************
942 + * May 2004 rkt, neb
943 + *
944 + * Initial Release
945 + *
946 + *
947 + *
948 + **************************************************************************
949 + */
950 +
951 +#include <linux/config.h>
952 +#include <linux/init.h>
953 +#include <linux/kernel_stat.h>
954 +#include <linux/sched.h>
955 +#include <linux/spinlock.h>
956 +#include <linux/mc146818rtc.h>
957 +#include <linux/irq.h>
958 +#include <linux/timex.h>
959 +
960 +#include <linux/param.h>
961 +#include <asm/mipsregs.h>
962 +#include <asm/ptrace.h>
963 +#include <asm/time.h>
964 +#include <asm/hardirq.h>
965 +
966 +#include <asm/mipsregs.h>
967 +#include <asm/ptrace.h>
968 +#include <asm/debug.h>
969 +#include <asm/time.h>
970 +
971 +#include <asm/idt-boards/rc32434/rc32434.h>
972 +
973 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
974 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
975 +
976 +extern unsigned int idt_cpu_freq;
977 +
978 +static unsigned long __init cal_r4koff(void)
979 +{
980 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
981 + return (mips_hpt_frequency / HZ);
982 +}
983 +
984 +void __init aruba_time_init(void)
985 +{
986 + unsigned int est_freq, flags;
987 + local_irq_save(flags);
988 +
989 + printk("calculating r4koff... ");
990 + r4k_offset = cal_r4koff();
991 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
992 +
993 + est_freq = 2 * r4k_offset * HZ;
994 + est_freq += 5000; /* round */
995 + est_freq -= est_freq % 10000;
996 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
997 + (est_freq % 1000000) * 100 / 1000000);
998 + local_irq_restore(flags);
999 +
1000 +}
1001 +
1002 +void __init aruba_timer_setup(struct irqaction *irq)
1003 +{
1004 + /* we are using the cpu counter for timer interrupts */
1005 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1006 +
1007 + /* to generate the first timer interrupt */
1008 + r4k_cur = (read_c0_count() + r4k_offset);
1009 + write_c0_compare(r4k_cur);
1010 +
1011 +}
1012 +
1013 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1014 +{
1015 + irq_enter();
1016 + kstat_this_cpu.irqs[irq]++;
1017 +
1018 + timer_interrupt(irq, NULL, regs);
1019 + irq_exit();
1020 +}
1021 diff -Nur linux-2.6.16/arch/mips/Kconfig linux-2.6.16-owrt/arch/mips/Kconfig
1022 --- linux-2.6.16/arch/mips/Kconfig 2006-03-20 06:53:29.000000000 +0100
1023 +++ linux-2.6.16-owrt/arch/mips/Kconfig 2006-03-20 14:25:10.000000000 +0100
1024 @@ -227,6 +227,17 @@
1025 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1026 a kernel for this platform.
1027
1028 +config MACH_ARUBA
1029 + bool "Support for the ARUBA product line"
1030 + select DMA_NONCOHERENT
1031 + select CPU_HAS_PREFETCH
1032 + select HW_HAS_PCI
1033 + select SWAP_IO_SPACE
1034 + select SYS_SUPPORTS_32BIT_KERNEL
1035 + select SYS_HAS_CPU_MIPS32_R1
1036 + select SYS_SUPPORTS_BIG_ENDIAN
1037 +
1038 +
1039 config MACH_JAZZ
1040 bool "Support for the Jazz family of machines"
1041 select ARC
1042 diff -Nur linux-2.6.16/arch/mips/Makefile linux-2.6.16-owrt/arch/mips/Makefile
1043 --- linux-2.6.16/arch/mips/Makefile 2006-03-20 06:53:29.000000000 +0100
1044 +++ linux-2.6.16-owrt/arch/mips/Makefile 2006-03-20 14:25:10.000000000 +0100
1045 @@ -279,6 +279,14 @@
1046 #
1047
1048 #
1049 +# Aruba
1050 +#
1051 +
1052 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1053 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1054 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1055 +
1056 +#
1057 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1058 #
1059 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1060 diff -Nur linux-2.6.16/arch/mips/mm/tlbex.c linux-2.6.16-owrt/arch/mips/mm/tlbex.c
1061 --- linux-2.6.16/arch/mips/mm/tlbex.c 2006-03-20 06:53:29.000000000 +0100
1062 +++ linux-2.6.16-owrt/arch/mips/mm/tlbex.c 2006-03-20 14:25:10.000000000 +0100
1063 @@ -852,7 +852,6 @@
1064
1065 case CPU_R10000:
1066 case CPU_R12000:
1067 - case CPU_4KC:
1068 case CPU_SB1:
1069 case CPU_SB1A:
1070 case CPU_4KSC:
1071 @@ -880,6 +879,7 @@
1072 tlbw(p);
1073 break;
1074
1075 + case CPU_4KC:
1076 case CPU_4KEC:
1077 case CPU_24K:
1078 case CPU_34K:
1079 diff -Nur linux-2.6.16/drivers/net/Kconfig linux-2.6.16-owrt/drivers/net/Kconfig
1080 --- linux-2.6.16/drivers/net/Kconfig 2006-03-20 06:53:29.000000000 +0100
1081 +++ linux-2.6.16-owrt/drivers/net/Kconfig 2006-03-20 14:25:10.000000000 +0100
1082 @@ -187,6 +187,13 @@
1083
1084 source "drivers/net/arm/Kconfig"
1085
1086 +config IDT_RC32434_ETH
1087 + tristate "IDT RC32434 Local Ethernet support"
1088 + depends on NET_ETHERNET
1089 + help
1090 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1091 + To compile this driver as a module, choose M here.
1092 +
1093 config MACE
1094 tristate "MACE (Power Mac ethernet) support"
1095 depends on NET_ETHERNET && PPC_PMAC && PPC32
1096 diff -Nur linux-2.6.16/drivers/net/Makefile linux-2.6.16-owrt/drivers/net/Makefile
1097 --- linux-2.6.16/drivers/net/Makefile 2006-03-20 06:53:29.000000000 +0100
1098 +++ linux-2.6.16-owrt/drivers/net/Makefile 2006-03-20 14:25:10.000000000 +0100
1099 @@ -38,6 +38,7 @@
1100
1101 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1102
1103 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1104 obj-$(CONFIG_DGRS) += dgrs.o
1105 obj-$(CONFIG_VORTEX) += 3c59x.o
1106 obj-$(CONFIG_TYPHOON) += typhoon.o
1107 diff -Nur linux-2.6.16/drivers/net/natsemi.c linux-2.6.16-owrt/drivers/net/natsemi.c
1108 --- linux-2.6.16/drivers/net/natsemi.c 2006-03-20 06:53:29.000000000 +0100
1109 +++ linux-2.6.16-owrt/drivers/net/natsemi.c 2006-03-20 14:25:10.000000000 +0100
1110 @@ -771,6 +771,49 @@
1111 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1112 static struct ethtool_ops ethtool_ops;
1113
1114 +#ifdef CONFIG_MACH_ARUBA
1115 +
1116 +#include <linux/ctype.h>
1117 +
1118 +#ifndef ERR
1119 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1120 +#endif
1121 +
1122 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1123 +{
1124 + int i, j;
1125 + unsigned char result, value;
1126 +
1127 + for (i=0; i<6; i++) {
1128 + result = 0;
1129 + if (i != 5 && *(macstr+2) != ':') {
1130 + ERR("invalid mac address format: %d %c\n",
1131 + i, *(macstr+2));
1132 + return -EINVAL;
1133 + }
1134 + for (j=0; j<2; j++) {
1135 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1136 + toupper(*macstr)-'A'+10) < 16) {
1137 + result = result*16 + value;
1138 + macstr++;
1139 + }
1140 + else {
1141 + ERR("invalid mac address "
1142 + "character: %c\n", *macstr);
1143 + return -EINVAL;
1144 + }
1145 + }
1146 +
1147 + macstr++;
1148 + dev->dev_addr[i] = result;
1149 + }
1150 +
1151 + dev->dev_addr[5]++;
1152 + return 0;
1153 +}
1154 +
1155 +#endif
1156 +
1157 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1158 {
1159 return (void __iomem *) dev->base_addr;
1160 @@ -859,6 +902,7 @@
1161 goto err_ioremap;
1162 }
1163
1164 +#ifndef CONFIG_MACH_ARUBA
1165 /* Work around the dropped serial bit. */
1166 prev_eedata = eeprom_read(ioaddr, 6);
1167 for (i = 0; i < 3; i++) {
1168 @@ -867,6 +911,19 @@
1169 dev->dev_addr[i*2+1] = eedata >> 7;
1170 prev_eedata = eedata;
1171 }
1172 +#else
1173 + {
1174 + char mac[32];
1175 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1176 + extern char *getenv(char *e);
1177 + memset(mac, 0, 32);
1178 + memcpy(mac, getenv("ethaddr"), 17);
1179 + if (parse_mac_addr(dev, mac)){
1180 + printk("%s: MAC address not found\n", __func__);
1181 + memcpy(dev->dev_addr, def_mac, 6);
1182 + }
1183 + }
1184 +#endif
1185
1186 dev->base_addr = (unsigned long __force) ioaddr;
1187 dev->irq = irq;
1188 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.c linux-2.6.16-owrt/drivers/net/rc32434_eth.c
1189 --- linux-2.6.16/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1190 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.c 2006-03-20 14:25:10.000000000 +0100
1191 @@ -0,0 +1,1268 @@
1192 +/**************************************************************************
1193 + *
1194 + * BRIEF MODULE DESCRIPTION
1195 + * Driver for the IDT RC32434 on-chip ethernet controller.
1196 + *
1197 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1198 + *
1199 + * This program is free software; you can redistribute it and/or modify it
1200 + * under the terms of the GNU General Public License as published by the
1201 + * Free Software Foundation; either version 2 of the License, or (at your
1202 + * option) any later version.
1203 + *
1204 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1205 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1206 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1207 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1208 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1209 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1210 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1211 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1212 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1213 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1214 + *
1215 + * You should have received a copy of the GNU General Public License along
1216 + * with this program; if not, write to the Free Software Foundation, Inc.,
1217 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1218 + *
1219 + *
1220 + **************************************************************************
1221 + * May 2004 rkt, neb
1222 + *
1223 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1224 + *
1225 + * Aug 2004 Sadik
1226 + *
1227 + * Added NAPI
1228 + *
1229 + **************************************************************************
1230 + */
1231 +
1232 +#include <linux/config.h>
1233 +#include <linux/module.h>
1234 +#include <linux/kernel.h>
1235 +#include <linux/moduleparam.h>
1236 +#include <linux/sched.h>
1237 +#include <linux/ctype.h>
1238 +#include <linux/types.h>
1239 +#include <linux/fcntl.h>
1240 +#include <linux/interrupt.h>
1241 +#include <linux/ptrace.h>
1242 +#include <linux/init.h>
1243 +#include <linux/ioport.h>
1244 +#include <linux/proc_fs.h>
1245 +#include <linux/in.h>
1246 +#include <linux/slab.h>
1247 +#include <linux/string.h>
1248 +#include <linux/delay.h>
1249 +#include <linux/netdevice.h>
1250 +#include <linux/etherdevice.h>
1251 +#include <linux/skbuff.h>
1252 +#include <linux/errno.h>
1253 +#include <asm/bootinfo.h>
1254 +#include <asm/system.h>
1255 +#include <asm/bitops.h>
1256 +#include <asm/pgtable.h>
1257 +#include <asm/segment.h>
1258 +#include <asm/io.h>
1259 +#include <asm/dma.h>
1260 +
1261 +#include "rc32434_eth.h"
1262 +
1263 +#define DRIVER_VERSION "(mar2904)"
1264 +
1265 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1266 +
1267 +
1268 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1269 + ((dev)->dev_addr[1]))
1270 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1271 + ((dev)->dev_addr[3] << 16) | \
1272 + ((dev)->dev_addr[4] << 8) | \
1273 + ((dev)->dev_addr[5]))
1274 +
1275 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1276 +static char mac0[18] = "08:00:06:05:40:01";
1277 +
1278 +MODULE_PARM(mac0, "c18");
1279 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1280 +
1281 +static struct rc32434_if_t {
1282 + char *name;
1283 + struct net_device *dev;
1284 + char* mac_str;
1285 + int weight;
1286 + u32 iobase;
1287 + u32 rxdmabase;
1288 + u32 txdmabase;
1289 + int rx_dma_irq;
1290 + int tx_dma_irq;
1291 + int rx_ovr_irq;
1292 + int tx_und_irq;
1293 +} rc32434_iflist[] =
1294 +{
1295 + {
1296 + "rc32434_eth0", NULL, mac0,
1297 + 64,
1298 + ETH0_PhysicalAddress,
1299 + ETH0_RX_DMA_ADDR,
1300 + ETH0_TX_DMA_ADDR,
1301 + ETH0_DMA_RX_IRQ,
1302 + ETH0_DMA_TX_IRQ,
1303 + ETH0_RX_OVR_IRQ,
1304 + ETH0_TX_UND_IRQ
1305 + }
1306 +};
1307 +
1308 +
1309 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1310 +{
1311 + int i, j;
1312 + unsigned char result, value;
1313 +
1314 + for (i=0; i<6; i++) {
1315 + result = 0;
1316 + if (i != 5 && *(macstr+2) != ':') {
1317 + ERR("invalid mac address format: %d %c\n",
1318 + i, *(macstr+2));
1319 + return -EINVAL;
1320 + }
1321 + for (j=0; j<2; j++) {
1322 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1323 + toupper(*macstr)-'A'+10) < 16) {
1324 + result = result*16 + value;
1325 + macstr++;
1326 + }
1327 + else {
1328 + ERR("invalid mac address "
1329 + "character: %c\n", *macstr);
1330 + return -EINVAL;
1331 + }
1332 + }
1333 +
1334 + macstr++;
1335 + dev->dev_addr[i] = result;
1336 + }
1337 +
1338 + return 0;
1339 +}
1340 +
1341 +
1342 +
1343 +static inline void rc32434_abort_tx(struct net_device *dev)
1344 +{
1345 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1346 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1347 +
1348 +}
1349 +
1350 +static inline void rc32434_abort_rx(struct net_device *dev)
1351 +{
1352 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1353 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1354 +
1355 +}
1356 +
1357 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1358 +{
1359 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1360 +}
1361 +
1362 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1363 +{
1364 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1365 +}
1366 +
1367 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1368 +{
1369 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1370 +}
1371 +
1372 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1373 +{
1374 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1375 +}
1376 +
1377 +#ifdef RC32434_PROC_DEBUG
1378 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1379 + int length, int *eof, void *data)
1380 +{
1381 + struct net_device *dev = (struct net_device *)data;
1382 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1383 + int len = 0;
1384 +
1385 + /* print out header */
1386 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1387 + len += sprintf (buf + len,
1388 + "DMA halt count = %10d, DMA run count = %10d\n",
1389 + lp->dma_halt_cnt, lp->dma_run_cnt);
1390 +
1391 + if (fpos >= len) {
1392 + *start = buf;
1393 + *eof = 1;
1394 + return 0;
1395 + }
1396 + *start = buf + fpos;
1397 +
1398 + if ((len -= fpos) > length)
1399 + return length;
1400 + *eof = 1;
1401 +
1402 + return len;
1403 +
1404 +}
1405 +#endif
1406 +
1407 +
1408 +/*
1409 + * Restart the RC32434 ethernet controller.
1410 + */
1411 +static int rc32434_restart(struct net_device *dev)
1412 +{
1413 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1414 +
1415 + /*
1416 + * Disable interrupts
1417 + */
1418 + disable_irq(lp->rx_irq);
1419 + disable_irq(lp->tx_irq);
1420 +#ifdef RC32434_REVISION
1421 + disable_irq(lp->ovr_irq);
1422 +#endif
1423 + disable_irq(lp->und_irq);
1424 +
1425 + /* Mask F E bit in Tx DMA */
1426 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1427 + /* Mask D H E bit in Rx DMA */
1428 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1429 +
1430 + rc32434_init(dev);
1431 + rc32434_multicast_list(dev);
1432 +
1433 + enable_irq(lp->und_irq);
1434 +#ifdef RC32434_REVISION
1435 + enable_irq(lp->ovr_irq);
1436 +#endif
1437 + enable_irq(lp->tx_irq);
1438 + enable_irq(lp->rx_irq);
1439 +
1440 + return 0;
1441 +}
1442 +
1443 +int rc32434_init_module(void)
1444 +{
1445 +#ifdef CONFIG_MACH_ARUBA
1446 + if (mips_machtype != MACH_ARUBA_AP70)
1447 + return 1;
1448 +#endif
1449 +
1450 + printk(KERN_INFO DRIVER_NAME " \n");
1451 + return rc32434_probe(0);
1452 +}
1453 +
1454 +static int rc32434_probe(int port_num)
1455 +{
1456 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1457 + struct rc32434_local *lp = NULL;
1458 + struct net_device *dev = NULL;
1459 + int i, retval,err;
1460 +
1461 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1462 + if(!dev) {
1463 + ERR("rc32434_eth: alloc_etherdev failed\n");
1464 + return -1;
1465 + }
1466 +
1467 + SET_MODULE_OWNER(dev);
1468 + bif->dev = dev;
1469 +
1470 +#ifdef CONFIG_MACH_ARUBA
1471 + {
1472 + extern char * getenv(char *e);
1473 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1474 + }
1475 +#endif
1476 +
1477 + printk("mac: %s\n", bif->mac_str);
1478 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1479 + ERR("MAC address parse failed\n");
1480 + free_netdev(dev);
1481 + return -1;
1482 + }
1483 +
1484 +
1485 + /* Initialize the device structure. */
1486 + if (dev->priv == NULL) {
1487 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1488 + memset(lp, 0, sizeof(struct rc32434_local));
1489 + }
1490 + else {
1491 + lp = (struct rc32434_local *)dev->priv;
1492 + }
1493 +
1494 + lp->rx_irq = bif->rx_dma_irq;
1495 + lp->tx_irq = bif->tx_dma_irq;
1496 + lp->ovr_irq = bif->rx_ovr_irq;
1497 + lp->und_irq = bif->tx_und_irq;
1498 +
1499 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1500 +
1501 + if (!lp->eth_regs) {
1502 + ERR("Can't remap eth registers\n");
1503 + retval = -ENXIO;
1504 + goto probe_err_out;
1505 + }
1506 +
1507 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1508 +
1509 + if (!lp->rx_dma_regs) {
1510 + ERR("Can't remap Rx DMA registers\n");
1511 + retval = -ENXIO;
1512 + goto probe_err_out;
1513 + }
1514 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1515 +
1516 + if (!lp->tx_dma_regs) {
1517 + ERR("Can't remap Tx DMA registers\n");
1518 + retval = -ENXIO;
1519 + goto probe_err_out;
1520 + }
1521 +
1522 +#ifdef RC32434_PROC_DEBUG
1523 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1524 + rc32434_read_proc, dev);
1525 +#endif
1526 +
1527 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1528 + if (!lp->td_ring) {
1529 + ERR("Can't allocate descriptors\n");
1530 + retval = -ENOMEM;
1531 + goto probe_err_out;
1532 + }
1533 +
1534 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1535 +
1536 + /* now convert TD_RING pointer to KSEG1 */
1537 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1538 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1539 +
1540 +
1541 + spin_lock_init(&lp->lock);
1542 +
1543 + dev->base_addr = bif->iobase;
1544 + /* just use the rx dma irq */
1545 + dev->irq = bif->rx_dma_irq;
1546 +
1547 + dev->priv = lp;
1548 +
1549 + dev->open = rc32434_open;
1550 + dev->stop = rc32434_close;
1551 + dev->hard_start_xmit = rc32434_send_packet;
1552 + dev->get_stats = rc32434_get_stats;
1553 + dev->set_multicast_list = &rc32434_multicast_list;
1554 + dev->tx_timeout = rc32434_tx_timeout;
1555 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1556 +
1557 +#ifdef CONFIG_IDT_USE_NAPI
1558 + dev->poll = rc32434_poll;
1559 + dev->weight = bif->weight;
1560 + printk("Using NAPI with weight %d\n",dev->weight);
1561 +#else
1562 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1563 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1564 +#endif
1565 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1566 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1567 +
1568 + if ((err = register_netdev(dev))) {
1569 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1570 + free_netdev(dev);
1571 + retval = -EINVAL;
1572 + goto probe_err_out;
1573 + }
1574 +
1575 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1576 + for (i = 0; i < 6; i++) {
1577 + printk("%2.2x", dev->dev_addr[i]);
1578 + if (i<5)
1579 + printk(":");
1580 + }
1581 + printk("\n");
1582 +
1583 + return 0;
1584 +
1585 + probe_err_out:
1586 + rc32434_cleanup_module();
1587 + ERR(" failed. Returns %d\n", retval);
1588 + return retval;
1589 +
1590 +}
1591 +
1592 +
1593 +static void rc32434_cleanup_module(void)
1594 +{
1595 + int i;
1596 +
1597 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1598 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1599 + if (bif->dev != NULL) {
1600 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1601 + if (lp != NULL) {
1602 + if (lp->eth_regs)
1603 + iounmap((void*)lp->eth_regs);
1604 + if (lp->rx_dma_regs)
1605 + iounmap((void*)lp->rx_dma_regs);
1606 + if (lp->tx_dma_regs)
1607 + iounmap((void*)lp->tx_dma_regs);
1608 + if (lp->td_ring)
1609 + kfree((void*)KSEG0ADDR(lp->td_ring));
1610 +
1611 +#ifdef RC32434_PROC_DEBUG
1612 + if (lp->ps) {
1613 + remove_proc_entry(bif->name, proc_net);
1614 + }
1615 +#endif
1616 + kfree(lp);
1617 + }
1618 +
1619 + unregister_netdev(bif->dev);
1620 + free_netdev(bif->dev);
1621 + kfree(bif->dev);
1622 + }
1623 + }
1624 +}
1625 +
1626 +
1627 +
1628 +static int rc32434_open(struct net_device *dev)
1629 +{
1630 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1631 +
1632 + /* Initialize */
1633 + if (rc32434_init(dev)) {
1634 + ERR("Error: cannot open the Ethernet device\n");
1635 + return -EAGAIN;
1636 + }
1637 +
1638 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1639 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1640 + SA_SHIRQ | SA_INTERRUPT,
1641 + "rc32434 ethernet Rx", dev)) {
1642 + ERR(": unable to get Rx DMA IRQ %d\n",
1643 + lp->rx_irq);
1644 + return -EAGAIN;
1645 + }
1646 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1647 + SA_SHIRQ | SA_INTERRUPT,
1648 + "rc32434 ethernet Tx", dev)) {
1649 + ERR(": unable to get Tx DMA IRQ %d\n",
1650 + lp->tx_irq);
1651 + free_irq(lp->rx_irq, dev);
1652 + return -EAGAIN;
1653 + }
1654 +
1655 +#ifdef RC32434_REVISION
1656 + /* Install handler for overrun error. */
1657 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1658 + SA_SHIRQ | SA_INTERRUPT,
1659 + "Ethernet Overflow", dev)) {
1660 + ERR(": unable to get OVR IRQ %d\n",
1661 + lp->ovr_irq);
1662 + free_irq(lp->rx_irq, dev);
1663 + free_irq(lp->tx_irq, dev);
1664 + return -EAGAIN;
1665 + }
1666 +#endif
1667 +
1668 + /* Install handler for underflow error. */
1669 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1670 + SA_SHIRQ | SA_INTERRUPT,
1671 + "Ethernet Underflow", dev)) {
1672 + ERR(": unable to get UND IRQ %d\n",
1673 + lp->und_irq);
1674 + free_irq(lp->rx_irq, dev);
1675 + free_irq(lp->tx_irq, dev);
1676 +#ifdef RC32434_REVISION
1677 + free_irq(lp->ovr_irq, dev);
1678 +#endif
1679 + return -EAGAIN;
1680 + }
1681 +
1682 +
1683 + return 0;
1684 +}
1685 +
1686 +
1687 +
1688 +
1689 +static int rc32434_close(struct net_device *dev)
1690 +{
1691 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1692 + u32 tmp;
1693 +
1694 + /* Disable interrupts */
1695 + disable_irq(lp->rx_irq);
1696 + disable_irq(lp->tx_irq);
1697 +#ifdef RC32434_REVISION
1698 + disable_irq(lp->ovr_irq);
1699 +#endif
1700 + disable_irq(lp->und_irq);
1701 +
1702 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1703 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1704 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1705 +
1706 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1707 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1708 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1709 +
1710 + free_irq(lp->rx_irq, dev);
1711 + free_irq(lp->tx_irq, dev);
1712 +#ifdef RC32434_REVISION
1713 + free_irq(lp->ovr_irq, dev);
1714 +#endif
1715 + free_irq(lp->und_irq, dev);
1716 + return 0;
1717 +}
1718 +
1719 +
1720 +/* transmit packet */
1721 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1722 +{
1723 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1724 + unsigned long flags;
1725 + u32 length;
1726 + DMAD_t td;
1727 +
1728 +
1729 + spin_lock_irqsave(&lp->lock, flags);
1730 +
1731 + td = &lp->td_ring[lp->tx_chain_tail];
1732 +
1733 + /* stop queue when full, drop pkts if queue already full */
1734 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1735 + lp->tx_full = 1;
1736 +
1737 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1738 + netif_stop_queue(dev);
1739 + }
1740 + else {
1741 + lp->stats.tx_dropped++;
1742 + dev_kfree_skb_any(skb);
1743 + spin_unlock_irqrestore(&lp->lock, flags);
1744 + return 1;
1745 + }
1746 + }
1747 +
1748 + lp->tx_count ++;
1749 +
1750 + lp->tx_skb[lp->tx_chain_tail] = skb;
1751 +
1752 + length = skb->len;
1753 +
1754 + /* Setup the transmit descriptor. */
1755 + td->ca = CPHYSADDR(skb->data);
1756 +
1757 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1758 + if( lp->tx_chain_status == empty ) {
1759 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1760 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1761 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1762 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1763 + }
1764 + else {
1765 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1766 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1767 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1768 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1769 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1770 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1771 + lp->tx_chain_status = empty;
1772 + }
1773 + }
1774 + else {
1775 + if( lp->tx_chain_status == empty ) {
1776 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1777 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1778 + lp->tx_chain_status = filled;
1779 + }
1780 + else {
1781 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1782 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1783 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1784 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1785 + }
1786 + }
1787 +
1788 + dev->trans_start = jiffies;
1789 +
1790 + spin_unlock_irqrestore(&lp->lock, flags);
1791 +
1792 + return 0;
1793 +}
1794 +
1795 +
1796 +/* Ethernet MII-PHY Handler */
1797 +static void rc32434_mii_handler(unsigned long data)
1798 +{
1799 + struct net_device *dev = (struct net_device *)data;
1800 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1801 + unsigned long flags;
1802 + unsigned long duplex_status;
1803 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1804 +
1805 + spin_lock_irqsave(&lp->lock, flags);
1806 +
1807 + /* Two ports are using the same MII, the difference is the PHY address */
1808 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1809 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1810 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1811 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1812 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1813 +
1814 + ERR("irq:%x port_addr:%x RDD:%x\n",
1815 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1816 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1817 + if(duplex_status != lp->duplex_mode) {
1818 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1819 + lp->duplex_mode = duplex_status;
1820 + rc32434_restart(dev);
1821 + }
1822 +
1823 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1824 + add_timer(&lp->mii_phy_timer);
1825 +
1826 + spin_unlock_irqrestore(&lp->lock, flags);
1827 +
1828 +}
1829 +
1830 +#ifdef RC32434_REVISION
1831 +/* Ethernet Rx Overflow interrupt */
1832 +static irqreturn_t
1833 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1834 +{
1835 + struct net_device *dev = (struct net_device *)dev_id;
1836 + struct rc32434_local *lp;
1837 + unsigned int ovr;
1838 + irqreturn_t retval = IRQ_NONE;
1839 +
1840 + ASSERT(dev != NULL);
1841 +
1842 + lp = (struct rc32434_local *)dev->priv;
1843 + spin_lock(&lp->lock);
1844 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1845 +
1846 + if(ovr & ETHINTFC_ovr_m) {
1847 + netif_stop_queue(dev);
1848 +
1849 + /* clear OVR bit */
1850 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1851 +
1852 + /* Restart interface */
1853 + rc32434_restart(dev);
1854 + retval = IRQ_HANDLED;
1855 + }
1856 + spin_unlock(&lp->lock);
1857 +
1858 + return retval;
1859 +}
1860 +
1861 +#endif
1862 +
1863 +
1864 +/* Ethernet Tx Underflow interrupt */
1865 +static irqreturn_t
1866 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1867 +{
1868 + struct net_device *dev = (struct net_device *)dev_id;
1869 + struct rc32434_local *lp;
1870 + unsigned int und;
1871 + irqreturn_t retval = IRQ_NONE;
1872 +
1873 + ASSERT(dev != NULL);
1874 +
1875 + lp = (struct rc32434_local *)dev->priv;
1876 +
1877 + spin_lock(&lp->lock);
1878 +
1879 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1880 +
1881 + if(und & ETHINTFC_und_m) {
1882 + netif_stop_queue(dev);
1883 +
1884 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1885 +
1886 + /* Restart interface */
1887 + rc32434_restart(dev);
1888 + retval = IRQ_HANDLED;
1889 + }
1890 +
1891 + spin_unlock(&lp->lock);
1892 +
1893 + return retval;
1894 +}
1895 +
1896 +
1897 +/* Ethernet Rx DMA interrupt */
1898 +static irqreturn_t
1899 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1900 +{
1901 + struct net_device *dev = (struct net_device *)dev_id;
1902 + struct rc32434_local* lp;
1903 + volatile u32 dmas,dmasm;
1904 + irqreturn_t retval;
1905 +
1906 + ASSERT(dev != NULL);
1907 +
1908 + lp = (struct rc32434_local *)dev->priv;
1909 +
1910 + spin_lock(&lp->lock);
1911 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1912 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1913 + /* Mask D H E bit in Rx DMA */
1914 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1915 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1916 +#ifdef CONFIG_IDT_USE_NAPI
1917 + if(netif_rx_schedule_prep(dev))
1918 + __netif_rx_schedule(dev);
1919 +#else
1920 + tasklet_hi_schedule(lp->rx_tasklet);
1921 +#endif
1922 +
1923 + if (dmas & DMAS_e_m)
1924 + ERR(": DMA error\n");
1925 +
1926 + retval = IRQ_HANDLED;
1927 + }
1928 + else
1929 + retval = IRQ_NONE;
1930 +
1931 + spin_unlock(&lp->lock);
1932 + return retval;
1933 +}
1934 +
1935 +#ifdef CONFIG_IDT_USE_NAPI
1936 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1937 +#else
1938 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1939 +#endif
1940 +{
1941 + struct net_device *dev = (struct net_device *)rx_data_dev;
1942 + struct rc32434_local* lp = netdev_priv(dev);
1943 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1944 + struct sk_buff *skb, *skb_new;
1945 + u8* pkt_buf;
1946 + u32 devcs, count, pkt_len, pktuncrc_len;
1947 + volatile u32 dmas;
1948 +#ifdef CONFIG_IDT_USE_NAPI
1949 + u32 received = 0;
1950 + int rx_work_limit = min(*budget,dev->quota);
1951 +#else
1952 + unsigned long flags;
1953 + spin_lock_irqsave(&lp->lock, flags);
1954 +#endif
1955 +
1956 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1957 +#ifdef CONFIG_IDT_USE_NAPI
1958 + if(--rx_work_limit <0)
1959 + {
1960 + break;
1961 + }
1962 +#endif
1963 + /* init the var. used for the later operations within the while loop */
1964 + skb_new = NULL;
1965 + devcs = rd->devcs;
1966 + pkt_len = RCVPKT_LENGTH(devcs);
1967 + skb = lp->rx_skb[lp->rx_next_done];
1968 +
1969 + if (count < 64) {
1970 + lp->stats.rx_errors++;
1971 + lp->stats.rx_dropped++;
1972 + }
1973 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1974 + /* check that this is a whole packet */
1975 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1976 + lp->stats.rx_errors++;
1977 + lp->stats.rx_dropped++;
1978 + }
1979 + else if ( (devcs & ETHRX_rok_m) ) {
1980 +
1981 + {
1982 + /* must be the (first and) last descriptor then */
1983 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1984 +
1985 + pktuncrc_len = pkt_len - 4;
1986 + /* invalidate the cache */
1987 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
1988 +
1989 + /* Malloc up new buffer. */
1990 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
1991 +
1992 + if (skb_new != NULL){
1993 + /* Make room */
1994 + skb_put(skb, pktuncrc_len);
1995 +
1996 + skb->protocol = eth_type_trans(skb, dev);
1997 +
1998 + /* pass the packet to upper layers */
1999 +#ifdef CONFIG_IDT_USE_NAPI
2000 + netif_receive_skb(skb);
2001 +#else
2002 + netif_rx(skb);
2003 +#endif
2004 +
2005 + dev->last_rx = jiffies;
2006 + lp->stats.rx_packets++;
2007 + lp->stats.rx_bytes += pktuncrc_len;
2008 +
2009 + if (IS_RCV_MP(devcs))
2010 + lp->stats.multicast++;
2011 +
2012 + /* 16 bit align */
2013 + skb_reserve(skb_new, 2);
2014 +
2015 + skb_new->dev = dev;
2016 + lp->rx_skb[lp->rx_next_done] = skb_new;
2017 + }
2018 + else {
2019 + ERR("no memory, dropping rx packet.\n");
2020 + lp->stats.rx_errors++;
2021 + lp->stats.rx_dropped++;
2022 + }
2023 + }
2024 +
2025 + }
2026 + else {
2027 + /* This should only happen if we enable accepting broken packets */
2028 + lp->stats.rx_errors++;
2029 + lp->stats.rx_dropped++;
2030 +
2031 + /* add statistics counters */
2032 + if (IS_RCV_CRC_ERR(devcs)) {
2033 + DBG(2, "RX CRC error\n");
2034 + lp->stats.rx_crc_errors++;
2035 + }
2036 + else if (IS_RCV_LOR_ERR(devcs)) {
2037 + DBG(2, "RX LOR error\n");
2038 + lp->stats.rx_length_errors++;
2039 + }
2040 + else if (IS_RCV_LE_ERR(devcs)) {
2041 + DBG(2, "RX LE error\n");
2042 + lp->stats.rx_length_errors++;
2043 + }
2044 + else if (IS_RCV_OVR_ERR(devcs)) {
2045 + lp->stats.rx_over_errors++;
2046 + }
2047 + else if (IS_RCV_CV_ERR(devcs)) {
2048 + /* code violation */
2049 + DBG(2, "RX CV error\n");
2050 + lp->stats.rx_frame_errors++;
2051 + }
2052 + else if (IS_RCV_CES_ERR(devcs)) {
2053 + DBG(2, "RX Preamble error\n");
2054 + }
2055 + }
2056 +
2057 + rd->devcs = 0;
2058 +
2059 + /* restore descriptor's curr_addr */
2060 + if(skb_new)
2061 + rd->ca = CPHYSADDR(skb_new->data);
2062 + else
2063 + rd->ca = CPHYSADDR(skb->data);
2064 +
2065 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2066 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2067 +
2068 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2069 + rd = &lp->rd_ring[lp->rx_next_done];
2070 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2071 + }
2072 +#ifdef CONFIG_IDT_USE_NAPI
2073 + dev->quota -= received;
2074 + *budget =- received;
2075 + if(rx_work_limit < 0)
2076 + goto not_done;
2077 +#endif
2078 +
2079 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2080 +
2081 + if(dmas & DMAS_h_m) {
2082 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2083 +#ifdef RC32434_PROC_DEBUG
2084 + lp->dma_halt_cnt++;
2085 +#endif
2086 + rd->devcs = 0;
2087 + skb = lp->rx_skb[lp->rx_next_done];
2088 + rd->ca = CPHYSADDR(skb->data);
2089 + rc32434_chain_rx(lp,rd);
2090 + }
2091 +
2092 +#ifdef CONFIG_IDT_USE_NAPI
2093 + netif_rx_complete(dev);
2094 +#endif
2095 + /* Enable D H E bit in Rx DMA */
2096 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2097 +#ifdef CONFIG_IDT_USE_NAPI
2098 + return 0;
2099 + not_done:
2100 + return 1;
2101 +#else
2102 + spin_unlock_irqrestore(&lp->lock, flags);
2103 + return;
2104 +#endif
2105 +
2106 +
2107 +}
2108 +
2109 +
2110 +
2111 +/* Ethernet Tx DMA interrupt */
2112 +static irqreturn_t
2113 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2114 +{
2115 + struct net_device *dev = (struct net_device *)dev_id;
2116 + struct rc32434_local *lp;
2117 + volatile u32 dmas,dmasm;
2118 + irqreturn_t retval;
2119 +
2120 + ASSERT(dev != NULL);
2121 +
2122 + lp = (struct rc32434_local *)dev->priv;
2123 +
2124 + spin_lock(&lp->lock);
2125 +
2126 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2127 +
2128 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2129 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2130 + /* Mask F E bit in Tx DMA */
2131 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2132 +
2133 + tasklet_hi_schedule(lp->tx_tasklet);
2134 +
2135 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2136 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2137 + lp->tx_chain_status = empty;
2138 + lp->tx_chain_head = lp->tx_chain_tail;
2139 + dev->trans_start = jiffies;
2140 + }
2141 +
2142 + if (dmas & DMAS_e_m)
2143 + ERR(": DMA error\n");
2144 +
2145 + retval = IRQ_HANDLED;
2146 + }
2147 + else
2148 + retval = IRQ_NONE;
2149 +
2150 + spin_unlock(&lp->lock);
2151 +
2152 + return retval;
2153 +}
2154 +
2155 +
2156 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2157 +{
2158 + struct net_device *dev = (struct net_device *)tx_data_dev;
2159 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2160 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2161 + u32 devcs;
2162 + unsigned long flags;
2163 + volatile u32 dmas;
2164 +
2165 + spin_lock_irqsave(&lp->lock, flags);
2166 +
2167 + /* process all desc that are done */
2168 + while(IS_DMA_FINISHED(td->control)) {
2169 + if(lp->tx_full == 1) {
2170 + netif_wake_queue(dev);
2171 + lp->tx_full = 0;
2172 + }
2173 +
2174 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2175 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2176 + lp->stats.tx_errors++;
2177 + lp->stats.tx_dropped++;
2178 +
2179 + /* should never happen */
2180 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2181 + }
2182 + else if (IS_TX_TOK(devcs)) {
2183 + lp->stats.tx_packets++;
2184 + }
2185 + else {
2186 + lp->stats.tx_errors++;
2187 + lp->stats.tx_dropped++;
2188 +
2189 + /* underflow */
2190 + if (IS_TX_UND_ERR(devcs))
2191 + lp->stats.tx_fifo_errors++;
2192 +
2193 + /* oversized frame */
2194 + if (IS_TX_OF_ERR(devcs))
2195 + lp->stats.tx_aborted_errors++;
2196 +
2197 + /* excessive deferrals */
2198 + if (IS_TX_ED_ERR(devcs))
2199 + lp->stats.tx_carrier_errors++;
2200 +
2201 + /* collisions: medium busy */
2202 + if (IS_TX_EC_ERR(devcs))
2203 + lp->stats.collisions++;
2204 +
2205 + /* late collision */
2206 + if (IS_TX_LC_ERR(devcs))
2207 + lp->stats.tx_window_errors++;
2208 +
2209 + }
2210 +
2211 + /* We must always free the original skb */
2212 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2213 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2214 + lp->tx_skb[lp->tx_next_done] = NULL;
2215 + }
2216 +
2217 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2218 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2219 + lp->td_ring[lp->tx_next_done].link = 0;
2220 + lp->td_ring[lp->tx_next_done].ca = 0;
2221 + lp->tx_count --;
2222 +
2223 + /* go on to next transmission */
2224 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2225 + td = &lp->td_ring[lp->tx_next_done];
2226 +
2227 + }
2228 +
2229 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2230 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2231 +
2232 + /* Enable F E bit in Tx DMA */
2233 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2234 + spin_unlock_irqrestore(&lp->lock, flags);
2235 +
2236 +}
2237 +
2238 +
2239 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2240 +{
2241 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2242 + return &lp->stats;
2243 +}
2244 +
2245 +
2246 +/*
2247 + * Set or clear the multicast filter for this adaptor.
2248 + */
2249 +static void rc32434_multicast_list(struct net_device *dev)
2250 +{
2251 + /* listen to broadcasts always and to treat */
2252 + /* IFF bits independantly */
2253 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2254 + unsigned long flags;
2255 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2256 +
2257 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2258 + recognise |= ETHARC_pro_m;
2259 +
2260 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2261 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2262 + else if (dev->mc_count > 0) {
2263 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2264 + recognise |= ETHARC_am_m; /* for the time being */
2265 + }
2266 +
2267 + spin_lock_irqsave(&lp->lock, flags);
2268 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2269 + spin_unlock_irqrestore(&lp->lock, flags);
2270 +}
2271 +
2272 +
2273 +static void rc32434_tx_timeout(struct net_device *dev)
2274 +{
2275 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2276 + unsigned long flags;
2277 +
2278 + spin_lock_irqsave(&lp->lock, flags);
2279 + rc32434_restart(dev);
2280 + spin_unlock_irqrestore(&lp->lock, flags);
2281 +
2282 +}
2283 +
2284 +
2285 +/*
2286 + * Initialize the RC32434 ethernet controller.
2287 + */
2288 +static int rc32434_init(struct net_device *dev)
2289 +{
2290 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2291 + int i, j;
2292 +
2293 + /* Disable DMA */
2294 + rc32434_abort_tx(dev);
2295 + rc32434_abort_rx(dev);
2296 +
2297 + /* reset ethernet logic */
2298 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2299 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2300 + dev->trans_start = jiffies;
2301 +
2302 + /* Enable Ethernet Interface */
2303 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2304 +
2305 +#ifndef CONFIG_IDT_USE_NAPI
2306 + tasklet_disable(lp->rx_tasklet);
2307 +#endif
2308 + tasklet_disable(lp->tx_tasklet);
2309 +
2310 + /* Initialize the transmit Descriptors */
2311 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2312 + lp->td_ring[i].control = DMAD_iof_m;
2313 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2314 + lp->td_ring[i].ca = 0;
2315 + lp->td_ring[i].link = 0;
2316 + if (lp->tx_skb[i] != NULL) {
2317 + dev_kfree_skb_any(lp->tx_skb[i]);
2318 + lp->tx_skb[i] = NULL;
2319 + }
2320 + }
2321 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2322 + lp-> tx_chain_status = empty;
2323 +
2324 + /*
2325 + * Initialize the receive descriptors so that they
2326 + * become a circular linked list, ie. let the last
2327 + * descriptor point to the first again.
2328 + */
2329 + for (i=0; i<RC32434_NUM_RDS; i++) {
2330 + struct sk_buff *skb = lp->rx_skb[i];
2331 +
2332 + if (lp->rx_skb[i] == NULL) {
2333 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2334 + if (skb == NULL) {
2335 + ERR("No memory in the system\n");
2336 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2337 + if (lp->rx_skb[j] != NULL)
2338 + dev_kfree_skb_any(lp->rx_skb[j]);
2339 +
2340 + return 1;
2341 + }
2342 + else {
2343 + skb->dev = dev;
2344 + skb_reserve(skb, 2);
2345 + lp->rx_skb[i] = skb;
2346 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2347 +
2348 + }
2349 + }
2350 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2351 + lp->rd_ring[i].devcs = 0;
2352 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2353 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2354 +
2355 + }
2356 + /* loop back */
2357 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2358 + lp->rx_next_done = 0;
2359 +
2360 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2361 + lp->rx_chain_head = 0;
2362 + lp->rx_chain_tail = 0;
2363 + lp->rx_chain_status = empty;
2364 +
2365 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2366 + /* Start Rx DMA */
2367 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2368 +
2369 + /* Enable F E bit in Tx DMA */
2370 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2371 + /* Enable D H E bit in Rx DMA */
2372 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2373 +
2374 + /* Accept only packets destined for this Ethernet device address */
2375 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2376 +
2377 + /* Set all Ether station address registers to their initial values */
2378 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2379 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2380 +
2381 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2382 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2383 +
2384 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2385 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2386 +
2387 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2388 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2389 +
2390 +
2391 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2392 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2393 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2394 +
2395 + /* Back to back inter-packet-gap */
2396 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2397 + /* Non - Back to back inter-packet-gap */
2398 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2399 +
2400 + /* Management Clock Prescaler Divisor */
2401 + /* Clock independent setting */
2402 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2403 + &lp->eth_regs->ethmcp);
2404 +
2405 + /* don't transmit until fifo contains 48b */
2406 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2407 +
2408 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2409 +
2410 +#ifndef CONFIG_IDT_USE_NAPI
2411 + tasklet_enable(lp->rx_tasklet);
2412 +#endif
2413 + tasklet_enable(lp->tx_tasklet);
2414 +
2415 + netif_start_queue(dev);
2416 +
2417 +
2418 + return 0;
2419 +
2420 +}
2421 +
2422 +
2423 +#ifndef MODULE
2424 +
2425 +static int __init rc32434_setup(char *options)
2426 +{
2427 + /* no options yet */
2428 + return 1;
2429 +}
2430 +
2431 +static int __init rc32434_setup_ethaddr0(char *options)
2432 +{
2433 + memcpy(mac0, options, 17);
2434 + mac0[17]= '\0';
2435 + return 1;
2436 +}
2437 +
2438 +__setup("rc32434eth=", rc32434_setup);
2439 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2440 +
2441 +
2442 +#endif /* MODULE */
2443 +
2444 +module_init(rc32434_init_module);
2445 +module_exit(rc32434_cleanup_module);
2446 +
2447 +
2448 +
2449 +
2450 +
2451 +
2452 +
2453 +
2454 +
2455 +
2456 +
2457 +
2458 +
2459 +
2460 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.h linux-2.6.16-owrt/drivers/net/rc32434_eth.h
2461 --- linux-2.6.16/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2462 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.h 2006-03-20 14:25:10.000000000 +0100
2463 @@ -0,0 +1,187 @@
2464 +/**************************************************************************
2465 + *
2466 + * BRIEF MODULE DESCRIPTION
2467 + * Definitions for IDT RC32434 on-chip ethernet controller.
2468 + *
2469 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2470 + *
2471 + * This program is free software; you can redistribute it and/or modify it
2472 + * under the terms of the GNU General Public License as published by the
2473 + * Free Software Foundation; either version 2 of the License, or (at your
2474 + * option) any later version.
2475 + *
2476 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2477 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2478 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2479 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2480 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2481 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2482 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2483 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2484 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2485 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2486 + *
2487 + * You should have received a copy of the GNU General Public License along
2488 + * with this program; if not, write to the Free Software Foundation, Inc.,
2489 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2490 + *
2491 + *
2492 + **************************************************************************
2493 + * May 2004 rkt, neb
2494 + *
2495 + * Initial Release
2496 + *
2497 + * Aug 2004
2498 + *
2499 + * Added NAPI
2500 + *
2501 + **************************************************************************
2502 + */
2503 +
2504 +
2505 +#include <asm/idt-boards/rc32434/rc32434.h>
2506 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2507 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2508 +
2509 +#define RC32434_DEBUG 2
2510 +//#define RC32434_PROC_DEBUG
2511 +#undef RC32434_DEBUG
2512 +
2513 +#ifdef RC32434_DEBUG
2514 +
2515 +/* use 0 for production, 1 for verification, >2 for debug */
2516 +static int rc32434_debug = RC32434_DEBUG;
2517 +#define ASSERT(expr) \
2518 + if(!(expr)) { \
2519 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2520 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2521 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2522 +#else
2523 +#define ASSERT(expr) do {} while (0)
2524 +#define DBG(lvl, format, arg...) do {} while (0)
2525 +#endif
2526 +
2527 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2528 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2529 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2530 +
2531 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2532 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2533 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2534 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2535 +
2536 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2537 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2538 +
2539 +/* the following must be powers of two */
2540 +#ifdef CONFIG_IDT_USE_NAPI
2541 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2542 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2543 +#else
2544 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2545 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2546 +#endif
2547 +
2548 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2549 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2550 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2551 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2552 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2553 +
2554 +#define RC32434_TX_TIMEOUT HZ * 100
2555 +
2556 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2557 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2558 +
2559 +enum status { filled, empty};
2560 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2561 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2562 +
2563 +
2564 +/* Information that need to be kept for each board. */
2565 +struct rc32434_local {
2566 + ETH_t eth_regs;
2567 + DMA_Chan_t rx_dma_regs;
2568 + DMA_Chan_t tx_dma_regs;
2569 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2570 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2571 +
2572 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2573 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2574 +
2575 +#ifndef CONFIG_IDT_USE_NAPI
2576 + struct tasklet_struct * rx_tasklet;
2577 +#endif
2578 + struct tasklet_struct * tx_tasklet;
2579 +
2580 + int rx_next_done;
2581 + int rx_chain_head;
2582 + int rx_chain_tail;
2583 + enum status rx_chain_status;
2584 +
2585 + int tx_next_done;
2586 + int tx_chain_head;
2587 + int tx_chain_tail;
2588 + enum status tx_chain_status;
2589 + int tx_count;
2590 + int tx_full;
2591 +
2592 + struct timer_list mii_phy_timer;
2593 + unsigned long duplex_mode;
2594 +
2595 + int rx_irq;
2596 + int tx_irq;
2597 + int ovr_irq;
2598 + int und_irq;
2599 +
2600 + struct net_device_stats stats;
2601 + spinlock_t lock;
2602 +
2603 + /* debug /proc entry */
2604 + struct proc_dir_entry *ps;
2605 + int dma_halt_cnt; int dma_run_cnt;
2606 +};
2607 +
2608 +extern unsigned int idt_cpu_freq;
2609 +
2610 +/* Index to functions, as function prototypes. */
2611 +static int rc32434_open(struct net_device *dev);
2612 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2613 +static void rc32434_mii_handler(unsigned long data);
2614 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2615 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2616 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2617 +#ifdef RC32434_REVISION
2618 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2619 +#endif
2620 +static int rc32434_close(struct net_device *dev);
2621 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2622 +static void rc32434_multicast_list(struct net_device *dev);
2623 +static int rc32434_init(struct net_device *dev);
2624 +static void rc32434_tx_timeout(struct net_device *dev);
2625 +
2626 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2627 +#ifdef CONFIG_IDT_USE_NAPI
2628 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2629 +#else
2630 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2631 +#endif
2632 +static void rc32434_cleanup_module(void);
2633 +static int rc32434_probe(int port_num);
2634 +int rc32434_init_module(void);
2635 +
2636 +
2637 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2638 +{
2639 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2640 + rc32434_writel(0x10, &ch->dmac);
2641 +
2642 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2643 + dev->trans_start = jiffies;
2644 +
2645 + rc32434_writel(0, &ch->dmas);
2646 + }
2647 +
2648 + rc32434_writel(0, &ch->dmadptr);
2649 + rc32434_writel(0, &ch->dmandptr);
2650 +}
2651 diff -Nur linux-2.6.16/include/asm-mips/bootinfo.h linux-2.6.16-owrt/include/asm-mips/bootinfo.h
2652 --- linux-2.6.16/include/asm-mips/bootinfo.h 2006-03-20 06:53:29.000000000 +0100
2653 +++ linux-2.6.16-owrt/include/asm-mips/bootinfo.h 2006-03-20 14:25:10.000000000 +0100
2654 @@ -218,6 +218,17 @@
2655 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2656 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2657
2658 +
2659 +/*
2660 + * Valid machtype for group ARUBA
2661 + */
2662 +#define MACH_GROUP_ARUBA 23
2663 +#define MACH_ARUBA_UNKNOWN 0
2664 +#define MACH_ARUBA_AP60 1
2665 +#define MACH_ARUBA_AP65 2
2666 +#define MACH_ARUBA_AP70 3
2667 +#define MACH_ARUBA_AP40 4
2668 +
2669 #define CL_SIZE COMMAND_LINE_SIZE
2670
2671 const char *get_system_type(void);
2672 diff -Nur linux-2.6.16/include/asm-mips/cpu.h linux-2.6.16-owrt/include/asm-mips/cpu.h
2673 --- linux-2.6.16/include/asm-mips/cpu.h 2006-03-20 06:53:29.000000000 +0100
2674 +++ linux-2.6.16-owrt/include/asm-mips/cpu.h 2006-03-20 14:25:10.000000000 +0100
2675 @@ -53,6 +53,9 @@
2676 #define PRID_IMP_R12000 0x0e00
2677 #define PRID_IMP_R8000 0x1000
2678 #define PRID_IMP_PR4450 0x1200
2679 +#define PRID_IMP_RC32334 0x1800
2680 +#define PRID_IMP_RC32355 0x1900
2681 +#define PRID_IMP_RC32365 0x1900
2682 #define PRID_IMP_R4600 0x2000
2683 #define PRID_IMP_R4700 0x2100
2684 #define PRID_IMP_TX39 0x2200
2685 @@ -196,7 +199,8 @@
2686 #define CPU_34K 60
2687 #define CPU_PR4450 61
2688 #define CPU_SB1A 62
2689 -#define CPU_LAST 62
2690 +#define CPU_RC32300 63
2691 +#define CPU_LAST 63
2692
2693 /*
2694 * ISA Level encodings
2695 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2696 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2697 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-03-20 14:25:10.000000000 +0100
2698 @@ -0,0 +1,142 @@
2699 +/**************************************************************************
2700 + *
2701 + * BRIEF MODULE DESCRIPTION
2702 + * RC32300 helper routines
2703 + *
2704 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2705 + *
2706 + * This program is free software; you can redistribute it and/or modify it
2707 + * under the terms of the GNU General Public License as published by the
2708 + * Free Software Foundation; either version 2 of the License, or (at your
2709 + * option) any later version.
2710 + *
2711 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2712 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2713 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2714 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2715 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2716 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2717 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2718 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2719 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2720 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2721 + *
2722 + * You should have received a copy of the GNU General Public License along
2723 + * with this program; if not, write to the Free Software Foundation, Inc.,
2724 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2725 + *
2726 + *
2727 + **************************************************************************
2728 + * May 2004 P. Sadik.
2729 + *
2730 + * Initial Release
2731 + *
2732 + *
2733 + *
2734 + **************************************************************************
2735 + */
2736 +
2737 +#ifndef __IDT_RC32300_H__
2738 +#define __IDT_RC32300_H__
2739 +
2740 +#include <linux/delay.h>
2741 +#include <asm/io.h>
2742 +
2743 +
2744 +/* cpu pipeline flush */
2745 +static inline void rc32300_sync(void)
2746 +{
2747 + __asm__ volatile ("sync");
2748 +}
2749 +
2750 +static inline void rc32300_sync_udelay(int us)
2751 +{
2752 + __asm__ volatile ("sync");
2753 + udelay(us);
2754 +}
2755 +
2756 +static inline void rc32300_sync_delay(int ms)
2757 +{
2758 + __asm__ volatile ("sync");
2759 + mdelay(ms);
2760 +}
2761 +
2762 +/*
2763 + * Macros to access internal RC32300 registers. No byte
2764 + * swapping should be done when accessing the internal
2765 + * registers.
2766 + */
2767 +
2768 +static inline u8 rc32300_readb(unsigned long pa)
2769 +{
2770 + return *((volatile u8 *)KSEG1ADDR(pa));
2771 +}
2772 +static inline u16 rc32300_readw(unsigned long pa)
2773 +{
2774 + return *((volatile u16 *)KSEG1ADDR(pa));
2775 +}
2776 +static inline u32 rc32300_readl(unsigned long pa)
2777 +{
2778 + return *((volatile u32 *)KSEG1ADDR(pa));
2779 +}
2780 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2781 +{
2782 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2783 +}
2784 +static inline void rc32300_writew(u16 val, unsigned long pa)
2785 +{
2786 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2787 +}
2788 +static inline void rc32300_writel(u32 val, unsigned long pa)
2789 +{
2790 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2791 +}
2792 +
2793 +
2794 +#define local_readb __raw_readb
2795 +#define local_readw __raw_readw
2796 +#define local_readl __raw_readl
2797 +
2798 +#define local_writeb __raw_writeb
2799 +#define local_writew __raw_writew
2800 +#define local_writel __raw_writel
2801 +
2802 +
2803 +/*
2804 + * C access to CLZ and CLO instructions
2805 + * (count leading zeroes/ones).
2806 + */
2807 +static inline int rc32300_clz(unsigned long val)
2808 +{
2809 + int ret;
2810 + __asm__ volatile (
2811 + ".set\tnoreorder\n\t"
2812 + ".set\tnoat\n\t"
2813 + ".set\tmips32\n\t"
2814 + "clz\t%0,%1\n\t"
2815 + ".set\tmips0\n\t"
2816 + ".set\tat\n\t"
2817 + ".set\treorder"
2818 + : "=r" (ret)
2819 + : "r" (val));
2820 +
2821 + return ret;
2822 +}
2823 +static inline int rc32300_clo(unsigned long val)
2824 +{
2825 + int ret;
2826 + __asm__ volatile (
2827 + ".set\tnoreorder\n\t"
2828 + ".set\tnoat\n\t"
2829 + ".set\tmips32\n\t"
2830 + "clo\t%0,%1\n\t"
2831 + ".set\tmips0\n\t"
2832 + ".set\tat\n\t"
2833 + ".set\treorder"
2834 + : "=r" (ret)
2835 + : "r" (val));
2836 +
2837 + return ret;
2838 +}
2839 +
2840 +#endif // __IDT_RC32300_H__
2841 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2842 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2843 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-03-20 14:25:10.000000000 +0100
2844 @@ -0,0 +1,207 @@
2845 +/**************************************************************************
2846 + *
2847 + * BRIEF MODULE DESCRIPTION
2848 + * Definitions for IDT RC32334 CPU.
2849 + *
2850 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2851 + *
2852 + * This program is free software; you can redistribute it and/or modify it
2853 + * under the terms of the GNU General Public License as published by the
2854 + * Free Software Foundation; either version 2 of the License, or (at your
2855 + * option) any later version.
2856 + *
2857 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2858 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2859 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2860 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2861 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2862 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2863 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2864 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2865 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2866 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2867 + *
2868 + * You should have received a copy of the GNU General Public License along
2869 + * with this program; if not, write to the Free Software Foundation, Inc.,
2870 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2871 + *
2872 + *
2873 + **************************************************************************
2874 + * May 2004 P. Sadik.
2875 + *
2876 + * Initial Release
2877 + *
2878 + *
2879 + *
2880 + **************************************************************************
2881 + */
2882 +
2883 +
2884 +#ifndef __IDT_RC32334_H__
2885 +#define __IDT_RC32334_H__
2886 +
2887 +#include <linux/delay.h>
2888 +#include <asm/io.h>
2889 +
2890 +/* Base address of internal registers */
2891 +#define RC32334_REG_BASE 0x18000000
2892 +
2893 +/* CPU and IP Bus Control */
2894 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2895 +#define CPU_BTA 0xffffe204 // virtual!
2896 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2897 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2898 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2899 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2900 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2901 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2902 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2903 +
2904 +/* Memory Controller */
2905 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2906 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2907 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2908 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2909 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2910 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2911 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2912 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2913 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2914 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2915 +
2916 +/* PCI Controller */
2917 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2918 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2919 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2920 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2921 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2922 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2923 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2924 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2925 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2926 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2927 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2928 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2929 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2930 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2931 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2932 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2933 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2934 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2935 +
2936 +/* Timers */
2937 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2938 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2939 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2940 +#define TIMER_REG_OFFSET 0x10
2941 +
2942 +/* Programmable I/O */
2943 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2944 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2945 +
2946 +/*
2947 + * DMA
2948 + *
2949 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2950 + *
2951 + * DMA0: 18001400
2952 + * DMA1: 18001440
2953 + * DMA2: 18001900
2954 + * DMA3: 18001940
2955 + * NB: dma number must be immediate value or variable.
2956 + * It MUST NOT be a function since it would get called twice!
2957 + */
2958 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2959 +
2960 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2961 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2962 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2963 +
2964 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2965 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2966 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2967 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2968 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2969 +
2970 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2971 +
2972 +/* Expansion Interrupt Controller */
2973 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2974 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2975 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2976 +#define IC_GROUP_OFFSET 0x10
2977 +
2978 +#define NUM_INTR_GROUPS 15
2979 +/*
2980 + * The IRQ mapping is as follows:
2981 + *
2982 + * IRQ Mapped To
2983 + * --- -------------------
2984 + * 0 SW0 (IP0) SW0 intr
2985 + * 1 SW1 (IP1) SW1 intr
2986 + * 2 Int0 (IP2) board-specific
2987 + * 3 Int1 (IP3) board-specific
2988 + * 4 Int2 (IP4) board-specific
2989 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
2990 + * 6 Int4 (IP6) board-specific
2991 + * 7 Int5 (IP7) CP0 Timer
2992 + *
2993 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
2994 + * internally on the RC32334 is routed to the Expansion
2995 + * Interrupt Controller.
2996 + */
2997 +#define MIPS_CPU_TIMER_IRQ 7
2998 +
2999 +#define GROUP1_IRQ_BASE 8 // bus error
3000 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3001 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3002 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3003 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3004 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3005 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3006 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3007 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3008 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3009 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3010 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3011 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3012 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3013 +
3014 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3015 +
3016 +/* 16550 UARTs */
3017 +#ifdef __MIPSEB__
3018 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3019 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3020 +#else
3021 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3022 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3023 +#endif
3024 +
3025 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3026 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3027 +
3028 +#define IDT_CLOCK_MULT 2
3029 +
3030 +/* NVRAM */
3031 +#define NVRAM_BASE 0x12000000
3032 +#define NVRAM_ENVSIZE_OFF 4
3033 +#define NVRAM_ENVSTART_OFF 0x40
3034 +
3035 +/* LCD 4-digit display */
3036 +#define LCD_CLEAR 0x14000400
3037 +#define LCD_DIGIT0 0x1400000f
3038 +#define LCD_DIGIT1 0x14000008
3039 +#define LCD_DIGIT2 0x14000007
3040 +#define LCD_DIGIT3 0x14000003
3041 +
3042 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3043 +#define RC32334_SCC8530_IRQ 2
3044 +#define RC32334_PCI_INTA_IRQ 3
3045 +#define RC32334_PCI_INTB_IRQ 4
3046 +#define RC32334_PCI_INTC_IRQ 6
3047 +#define RC32334_PCI_INTD_IRQ 7
3048 +
3049 +#define RAM_SIZE (32*1024*1024)
3050 +
3051 +#endif // __IDT_RC32334_H__
3052 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3053 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3054 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-03-20 14:25:10.000000000 +0100
3055 @@ -0,0 +1,206 @@
3056 +/**************************************************************************
3057 + *
3058 + * BRIEF MODULE DESCRIPTION
3059 + * DMA controller defines on IDT RC32355
3060 + *
3061 + * Copyright 2004 IDT Inc.
3062 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3063 + *
3064 + *
3065 + * This program is free software; you can redistribute it and/or modify it
3066 + * under the terms of the GNU General Public License as published by the
3067 + * Free Software Foundation; either version 2 of the License, or (at your
3068 + * option) any later version.
3069 + *
3070 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3071 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3072 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3073 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3074 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3075 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3076 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3077 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3078 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3079 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3080 + *
3081 + * You should have received a copy of the GNU General Public License along
3082 + * with this program; if not, write to the Free Software Foundation, Inc.,
3083 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3084 + *
3085 + *
3086 + * May 2004 rkt
3087 + * Initial Release
3088 + *
3089 + **************************************************************************
3090 + */
3091 +
3092 +#ifndef BANYAN_DMA_H
3093 +#define BANYAN_DMA_H
3094 +#include <asm/idt-boards/rc32300/rc32300.h>
3095 +
3096 +/*
3097 + * An image of one RC32355 dma channel registers
3098 + */
3099 +typedef struct {
3100 + u32 dmac;
3101 + u32 dmas;
3102 + u32 dmasm;
3103 + u32 dmadptr;
3104 + u32 dmandptr;
3105 +} rc32355_dma_ch_t;
3106 +
3107 +/*
3108 + * An image of all RC32355 dma channel registers
3109 + */
3110 +typedef struct {
3111 + rc32355_dma_ch_t ch[16];
3112 +} rc32355_dma_regs_t;
3113 +
3114 +
3115 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3116 +
3117 +
3118 +/* DMAC register layout */
3119 +
3120 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3121 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3122 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3123 +
3124 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3125 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3126 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3127 +
3128 +/* DMAS and DMASM register layout */
3129 +
3130 +#define DMAS_F 0x01 /* Finished */
3131 +#define DMAS_D 0x02 /* Done */
3132 +#define DMAS_C 0x04 /* Chain */
3133 +#define DMAS_E 0x08 /* Error */
3134 +#define DMAS_H 0x10 /* Halt */
3135 +
3136 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3137 +#define DMA_HALT_TIMEOUT 500
3138 +
3139 +
3140 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3141 +{
3142 + int timeout=1;
3143 +
3144 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3145 + local_writel(0, &ch->dmac);
3146 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3147 + if (local_readl(&ch->dmas) & DMAS_H) {
3148 + local_writel(0, &ch->dmas);
3149 + break;
3150 + }
3151 + }
3152 + }
3153 +
3154 + return timeout ? 0 : 1;
3155 +}
3156 +
3157 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3158 +{
3159 + local_writel(0, &ch->dmandptr);
3160 + local_writel(dma_addr, &ch->dmadptr);
3161 +}
3162 +
3163 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3164 +{
3165 + local_writel(dma_addr, &ch->dmandptr);
3166 +}
3167 +
3168 +
3169 +/* The following can be used to describe DMA channels 0 to 15, and the */
3170 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3171 +
3172 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3173 +
3174 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3175 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3176 +
3177 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3178 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3179 +
3180 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3181 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3182 +
3183 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3184 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3185 +
3186 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3187 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3188 +#define DMA_DEV_ATMVCC(entry) 0
3189 +
3190 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3191 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3192 +
3193 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3194 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3195 +
3196 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3197 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3198 +
3199 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3200 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3201 +
3202 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3203 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3204 +
3205 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3206 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3207 +
3208 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3209 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3210 +
3211 +#define DMA_CHAN_USBIN 13 /* USB input */
3212 +#define DMA_DEV_USBIN 0 /* USB input */
3213 +
3214 +#define DMA_CHAN_USBOUT 14 /* USB output */
3215 +#define DMA_DEV_USBOUT 0 /* USB output */
3216 +
3217 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3218 +#define DMA_DEV_EXTERN 0 /* External DMA */
3219 +
3220 +/*
3221 + * An RC32355 dma descriptor in system memory
3222 + */
3223 +typedef struct {
3224 + u32 cmdstat; /* control and status */
3225 + u32 curr_addr; /* current address of data */
3226 + u32 devcs; /* peripheral-specific control and status */
3227 + u32 link; /* link to next descriptor */
3228 +} rc32355_dma_desc_t;
3229 +
3230 +/* Values for the descriptor cmdstat word */
3231 +
3232 +#define DMADESC_F 0x80000000u /* Finished bit */
3233 +#define DMADESC_D 0x40000000u /* Done bit */
3234 +#define DMADESC_T 0x20000000u /* Terminated bit */
3235 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3236 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3237 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3238 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3239 +
3240 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3241 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3242 +
3243 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3244 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3245 +
3246 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3247 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3248 +
3249 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3250 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3251 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3252 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3253 +
3254 +#define DMA_DEVCMD(devcmd) \
3255 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3256 +#define DMA_DS(ds) \
3257 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3258 +#define DMA_COUNT(count) \
3259 + ((count) & DMADESC_COUNT_MASK)
3260 +
3261 +#endif /* RC32355_DMA_H */
3262 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3263 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3264 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-03-20 14:25:10.000000000 +0100
3265 @@ -0,0 +1,442 @@
3266 +/**************************************************************************
3267 + *
3268 + * BRIEF MODULE DESCRIPTION
3269 + * Ethernet registers on IDT RC32355
3270 + *
3271 + * Copyright 2004 IDT Inc.
3272 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3273 + *
3274 + *
3275 + * This program is free software; you can redistribute it and/or modify it
3276 + * under the terms of the GNU General Public License as published by the
3277 + * Free Software Foundation; either version 2 of the License, or (at your
3278 + * option) any later version.
3279 + *
3280 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3281 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3282 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3283 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3284 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3285 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3286 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3287 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3288 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3289 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3290 + *
3291 + * You should have received a copy of the GNU General Public License along
3292 + * with this program; if not, write to the Free Software Foundation, Inc.,
3293 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3294 + *
3295 + *
3296 + * May 2004 rkt
3297 + * Initial Release
3298 + *
3299 + **************************************************************************
3300 + */
3301 +
3302 +
3303 +#ifndef RC32355_ETHER_H
3304 +#define RC32355_ETHER_H
3305 +
3306 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3307 +
3308 +/*
3309 + * A partial image of the RC32355 ethernet registers
3310 + */
3311 +typedef struct {
3312 + u32 ethintfc;
3313 + u32 ethfifott;
3314 + u32 etharc;
3315 + u32 ethhash0;
3316 + u32 ethhash1;
3317 + u32 ethfifost;
3318 + u32 ethfifos;
3319 + u32 ethodeops;
3320 + u32 ethis;
3321 + u32 ethos;
3322 + u32 ethmcp;
3323 + u32 _u1;
3324 + u32 ethid;
3325 + u32 _u2;
3326 + u32 _u3;
3327 + u32 _u4;
3328 + u32 ethod;
3329 + u32 _u5;
3330 + u32 _u6;
3331 + u32 _u7;
3332 + u32 ethodeop;
3333 + u32 _u8[43];
3334 + u32 ethsal0;
3335 + u32 ethsah0;
3336 + u32 ethsal1;
3337 + u32 ethsah1;
3338 + u32 ethsal2;
3339 + u32 ethsah2;
3340 + u32 ethsal3;
3341 + u32 ethsah3;
3342 + u32 ethrbc;
3343 + u32 ethrpc;
3344 + u32 ethrupc;
3345 + u32 ethrfc;
3346 + u32 ethtbc;
3347 + u32 ethgpf;
3348 + u32 _u9[50];
3349 + u32 ethmac1;
3350 + u32 ethmac2;
3351 + u32 ethipgt;
3352 + u32 ethipgr;
3353 + u32 ethclrt;
3354 + u32 ethmaxf;
3355 + u32 _u10;
3356 + u32 ethmtest;
3357 + u32 miimcfg;
3358 + u32 miimcmd;
3359 + u32 miimaddr;
3360 + u32 miimwtd;
3361 + u32 miimrdd;
3362 + u32 miimind;
3363 + u32 _u11;
3364 + u32 _u12;
3365 + u32 ethcfsa0;
3366 + u32 ethcfsa1;
3367 + u32 ethcfsa2;
3368 +} rc32355_eth_regs_t;
3369 +
3370 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3371 +
3372 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3373 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3374 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3375 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3376 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3377 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3378 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3379 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3380 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3381 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3382 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3383 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3384 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3385 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3386 +
3387 +/* for n in { 0, 1, 2, 3 } */
3388 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3389 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3390 +
3391 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3392 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3393 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3394 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3395 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3396 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3397 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3398 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3399 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3400 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3401 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3402 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3403 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3404 +
3405 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3406 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3407 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3408 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3409 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3410 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3411 +
3412 +/* for n in { 0, 1, 2 } */
3413 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3414 +
3415 +
3416 +/*
3417 + * Register Interpretations follow
3418 + */
3419 +
3420 +/******************************************************************************
3421 + * ETHINTFC register
3422 + *****************************************************************************/
3423 +
3424 +#define ETHERINTFC_EN (1<<0)
3425 +#define ETHERINTFC_ITS (1<<1)
3426 +#define ETHERINTFC_RES (1<<2)
3427 +#define ETHERINTFC_RIP (1<<2)
3428 +#define ETHERINTFC_JAM (1<<3)
3429 +
3430 +/******************************************************************************
3431 + * ETHFIFOTT register
3432 + *****************************************************************************/
3433 +
3434 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3435 +
3436 +/******************************************************************************
3437 + * ETHARC register
3438 + *****************************************************************************/
3439 +
3440 +#define ETHERARC_PRO (1<<0)
3441 +#define ETHERARC_AM (1<<1)
3442 +#define ETHERARC_AFM (1<<2)
3443 +#define ETHERARC_AB (1<<3)
3444 +
3445 +/******************************************************************************
3446 + * ETHHASH registers
3447 + *****************************************************************************/
3448 +
3449 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3450 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3451 +
3452 +/******************************************************************************
3453 + * ETHSA registers
3454 + *****************************************************************************/
3455 +
3456 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3457 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3458 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3459 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3460 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3461 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3462 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3463 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3464 +
3465 +/******************************************************************************
3466 + * ETHFIFOST register
3467 + *****************************************************************************/
3468 +
3469 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3470 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3471 +
3472 +/******************************************************************************
3473 + * ETHFIFOS register
3474 + *****************************************************************************/
3475 +
3476 +#define ETHERFIFOS_IR (1<<0)
3477 +#define ETHERFIFOS_OR (1<<1)
3478 +#define ETHERFIFOS_OVR (1<<2)
3479 +#define ETHERFIFOS_UND (1<<3)
3480 +
3481 +/******************************************************************************
3482 + * DATA registers
3483 + *****************************************************************************/
3484 +
3485 +#define ETHERID(v) (((v)&0xffff)<<0)
3486 +#define ETHEROD(v) (((v)&0xffff)<<0)
3487 +
3488 +/******************************************************************************
3489 + * ETHODEOPS register
3490 + *****************************************************************************/
3491 +
3492 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3493 +
3494 +/******************************************************************************
3495 + * ETHODEOP register
3496 + *****************************************************************************/
3497 +
3498 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3499 +
3500 +/******************************************************************************
3501 + * ETHIS register
3502 + *****************************************************************************/
3503 +
3504 +#define ETHERIS_EOP (1<<0)
3505 +#define ETHERIS_ROK (1<<2)
3506 +#define ETHERIS_FM (1<<3)
3507 +#define ETHERIS_MP (1<<4)
3508 +#define ETHERIS_BP (1<<5)
3509 +#define ETHERIS_VLT (1<<6)
3510 +#define ETHERIS_CF (1<<7)
3511 +#define ETHERIS_OVR (1<<8)
3512 +#define ETHERIS_CRC (1<<9)
3513 +#define ETHERIS_CV (1<<10)
3514 +#define ETHERIS_DB (1<<11)
3515 +#define ETHERIS_LE (1<<12)
35