finally fix/tweaks for vncrepeater (thanks to Russell Harmon)
[openwrt/svn-archive/archive.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.16/arch/mips/aruba/Makefile linux-2.6.16-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.16/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.16-owrt/arch/mips/aruba/Makefile 2006-03-20 14:25:10.000000000 +0100
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o wdt_merlot.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/Makefile linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.16/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile 2006-03-20 14:25:10.000000000 +0100
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.c linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c 2006-03-20 14:25:10.000000000 +0100
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.h linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h 2006-03-20 14:25:10.000000000 +0100
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.16/arch/mips/aruba/prom.c linux-2.6.16-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.16/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.16-owrt/arch/mips/aruba/prom.c 2006-03-20 14:25:10.000000000 +0100
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.16/arch/mips/aruba/serial.c linux-2.6.16-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.16/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.16-owrt/arch/mips/aruba/serial.c 2006-03-20 14:25:10.000000000 +0100
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.16/arch/mips/aruba/setup.c linux-2.6.16-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.16/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.16-owrt/arch/mips/aruba/setup.c 2006-03-20 14:30:00.000000000 +0100
786 @@ -0,0 +1,125 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/mm.h>
827 +#include <linux/sched.h>
828 +#include <linux/irq.h>
829 +#include <asm/bootinfo.h>
830 +#include <asm/io.h>
831 +#include <linux/ioport.h>
832 +#include <asm/mipsregs.h>
833 +#include <asm/pgtable.h>
834 +#include <asm/reboot.h>
835 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
836 +#include <asm/idt-boards/rc32434/rc32434.h>
837 +#include <linux/pm.h>
838 +
839 +extern char *__init prom_getcmdline(void);
840 +
841 +extern void (*board_time_init) (void);
842 +extern void (*board_timer_setup) (struct irqaction * irq);
843 +extern void aruba_time_init(void);
844 +extern void aruba_timer_setup(struct irqaction *irq);
845 +extern void aruba_reset(void);
846 +
847 +#define epldMask ((volatile unsigned char *)0xB900000d)
848 +
849 +static void aruba_machine_restart(char *command)
850 +{
851 + switch (mips_machtype) {
852 + case MACH_ARUBA_AP70:
853 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
854 + break;
855 + case MACH_ARUBA_AP65:
856 + case MACH_ARUBA_AP60:
857 + default:
858 + /* Reset*/
859 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
860 + udelay(100);
861 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
862 + udelay(100);
863 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
864 + break;
865 + }
866 +}
867 +
868 +static void aruba_machine_halt(void)
869 +{
870 + for (;;) continue;
871 +}
872 +
873 +extern char * getenv(char *e);
874 +extern void unlock_ap60_70_flash(void);
875 +extern void wdt_merlot_disable(void);
876 +
877 +void __init plat_setup(void)
878 +{
879 + board_time_init = aruba_time_init;
880 +
881 + board_timer_setup = aruba_timer_setup;
882 +
883 + _machine_restart = aruba_machine_restart;
884 + _machine_halt = aruba_machine_halt;
885 + pm_power_off = aruba_machine_halt;
886 +
887 + set_io_port_base(KSEG1);
888 +
889 + /* Enable PCI interrupts in EPLD Mask register */
890 + *epldMask = 0x0;
891 + *(epldMask + 1) = 0x0;
892 +
893 + write_c0_wired(0);
894 + unlock_ap60_70_flash();
895 +
896 + printk("BOARD - %s\n",getenv("boardname"));
897 +
898 + wdt_merlot_disable();
899 +
900 + return 0;
901 +}
902 +
903 +int page_is_ram(unsigned long pagenr)
904 +{
905 + return 1;
906 +}
907 +
908 +const char *get_system_type(void)
909 +{
910 + return "MIPS IDT32434 - ARUBA";
911 +}
912 diff -Nur linux-2.6.16/arch/mips/aruba/time.c linux-2.6.16-owrt/arch/mips/aruba/time.c
913 --- linux-2.6.16/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
914 +++ linux-2.6.16-owrt/arch/mips/aruba/time.c 2006-03-20 14:25:10.000000000 +0100
915 @@ -0,0 +1,108 @@
916 +/**************************************************************************
917 + *
918 + * BRIEF MODULE DESCRIPTION
919 + * timer routines for IDT EB434 boards
920 + *
921 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
922 + *
923 + * This program is free software; you can redistribute it and/or modify it
924 + * under the terms of the GNU General Public License as published by the
925 + * Free Software Foundation; either version 2 of the License, or (at your
926 + * option) any later version.
927 + *
928 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
929 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
930 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
931 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
932 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
933 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
934 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
935 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
936 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
937 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
938 + *
939 + * You should have received a copy of the GNU General Public License along
940 + * with this program; if not, write to the Free Software Foundation, Inc.,
941 + * 675 Mass Ave, Cambridge, MA 02139, USA.
942 + *
943 + *
944 + **************************************************************************
945 + * May 2004 rkt, neb
946 + *
947 + * Initial Release
948 + *
949 + *
950 + *
951 + **************************************************************************
952 + */
953 +
954 +#include <linux/config.h>
955 +#include <linux/init.h>
956 +#include <linux/kernel_stat.h>
957 +#include <linux/sched.h>
958 +#include <linux/spinlock.h>
959 +#include <linux/mc146818rtc.h>
960 +#include <linux/irq.h>
961 +#include <linux/timex.h>
962 +
963 +#include <linux/param.h>
964 +#include <asm/mipsregs.h>
965 +#include <asm/ptrace.h>
966 +#include <asm/time.h>
967 +#include <asm/hardirq.h>
968 +
969 +#include <asm/mipsregs.h>
970 +#include <asm/ptrace.h>
971 +#include <asm/debug.h>
972 +#include <asm/time.h>
973 +
974 +#include <asm/idt-boards/rc32434/rc32434.h>
975 +
976 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
977 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
978 +
979 +extern unsigned int idt_cpu_freq;
980 +
981 +static unsigned long __init cal_r4koff(void)
982 +{
983 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
984 + return (mips_hpt_frequency / HZ);
985 +}
986 +
987 +void __init aruba_time_init(void)
988 +{
989 + unsigned int est_freq, flags;
990 + local_irq_save(flags);
991 +
992 + printk("calculating r4koff... ");
993 + r4k_offset = cal_r4koff();
994 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
995 +
996 + est_freq = 2 * r4k_offset * HZ;
997 + est_freq += 5000; /* round */
998 + est_freq -= est_freq % 10000;
999 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1000 + (est_freq % 1000000) * 100 / 1000000);
1001 + local_irq_restore(flags);
1002 +
1003 +}
1004 +
1005 +void __init aruba_timer_setup(struct irqaction *irq)
1006 +{
1007 + /* we are using the cpu counter for timer interrupts */
1008 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1009 +
1010 + /* to generate the first timer interrupt */
1011 + r4k_cur = (read_c0_count() + r4k_offset);
1012 + write_c0_compare(r4k_cur);
1013 +
1014 +}
1015 +
1016 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1017 +{
1018 + irq_enter();
1019 + kstat_this_cpu.irqs[irq]++;
1020 +
1021 + timer_interrupt(irq, NULL, regs);
1022 + irq_exit();
1023 +}
1024 diff -Nur linux-2.6.16/arch/mips/aruba/wdt_merlot.c linux-2.6.16-owrt/arch/mips/aruba/wdt_merlot.c
1025 --- linux-2.6.16/arch/mips/aruba/wdt_merlot.c 1970-01-01 01:00:00.000000000 +0100
1026 +++ linux-2.6.16-owrt/arch/mips/aruba/wdt_merlot.c 2006-03-20 14:25:10.000000000 +0100
1027 @@ -0,0 +1,30 @@
1028 +#include <linux/config.h>
1029 +#include <linux/kernel.h>
1030 +#include <asm/bootinfo.h>
1031 +
1032 +void wdt_merlot_disable()
1033 +{
1034 + volatile __u32 *wdt_errcs;
1035 + volatile __u32 *wdt_wtc;
1036 + volatile __u32 *wdt_ctl;
1037 + volatile __u32 val;
1038 +
1039 + switch (mips_machtype) {
1040 + case MACH_ARUBA_AP70:
1041 + wdt_errcs = (__u32 *) 0xb8030030;
1042 + wdt_wtc = (__u32 *) 0xb803003c;
1043 + val = *wdt_errcs;
1044 + val &= ~0x201;
1045 + *wdt_errcs = val;
1046 + val = *wdt_wtc;
1047 + val &= ~0x1;
1048 + *wdt_wtc = val;
1049 + break;
1050 + case MACH_ARUBA_AP65:
1051 + case MACH_ARUBA_AP60:
1052 + default:
1053 + wdt_ctl = (__u32 *) 0xbc003008;
1054 + *wdt_ctl = 0;
1055 + break;
1056 + }
1057 +}
1058 diff -Nur linux-2.6.16/arch/mips/Kconfig linux-2.6.16-owrt/arch/mips/Kconfig
1059 --- linux-2.6.16/arch/mips/Kconfig 2006-03-20 06:53:29.000000000 +0100
1060 +++ linux-2.6.16-owrt/arch/mips/Kconfig 2006-03-20 14:25:10.000000000 +0100
1061 @@ -227,6 +227,17 @@
1062 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1063 a kernel for this platform.
1064
1065 +config MACH_ARUBA
1066 + bool "Support for the ARUBA product line"
1067 + select DMA_NONCOHERENT
1068 + select CPU_HAS_PREFETCH
1069 + select HW_HAS_PCI
1070 + select SWAP_IO_SPACE
1071 + select SYS_SUPPORTS_32BIT_KERNEL
1072 + select SYS_HAS_CPU_MIPS32_R1
1073 + select SYS_SUPPORTS_BIG_ENDIAN
1074 +
1075 +
1076 config MACH_JAZZ
1077 bool "Support for the Jazz family of machines"
1078 select ARC
1079 diff -Nur linux-2.6.16/arch/mips/Makefile linux-2.6.16-owrt/arch/mips/Makefile
1080 --- linux-2.6.16/arch/mips/Makefile 2006-03-20 06:53:29.000000000 +0100
1081 +++ linux-2.6.16-owrt/arch/mips/Makefile 2006-03-20 14:25:10.000000000 +0100
1082 @@ -279,6 +279,14 @@
1083 #
1084
1085 #
1086 +# Aruba
1087 +#
1088 +
1089 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1090 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1091 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1092 +
1093 +#
1094 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1095 #
1096 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1097 diff -Nur linux-2.6.16/arch/mips/mm/tlbex.c linux-2.6.16-owrt/arch/mips/mm/tlbex.c
1098 --- linux-2.6.16/arch/mips/mm/tlbex.c 2006-03-20 06:53:29.000000000 +0100
1099 +++ linux-2.6.16-owrt/arch/mips/mm/tlbex.c 2006-03-20 14:25:10.000000000 +0100
1100 @@ -852,7 +852,6 @@
1101
1102 case CPU_R10000:
1103 case CPU_R12000:
1104 - case CPU_4KC:
1105 case CPU_SB1:
1106 case CPU_SB1A:
1107 case CPU_4KSC:
1108 @@ -880,6 +879,7 @@
1109 tlbw(p);
1110 break;
1111
1112 + case CPU_4KC:
1113 case CPU_4KEC:
1114 case CPU_24K:
1115 case CPU_34K:
1116 diff -Nur linux-2.6.16/drivers/net/Kconfig linux-2.6.16-owrt/drivers/net/Kconfig
1117 --- linux-2.6.16/drivers/net/Kconfig 2006-03-20 06:53:29.000000000 +0100
1118 +++ linux-2.6.16-owrt/drivers/net/Kconfig 2006-03-20 14:25:10.000000000 +0100
1119 @@ -187,6 +187,13 @@
1120
1121 source "drivers/net/arm/Kconfig"
1122
1123 +config IDT_RC32434_ETH
1124 + tristate "IDT RC32434 Local Ethernet support"
1125 + depends on NET_ETHERNET
1126 + help
1127 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1128 + To compile this driver as a module, choose M here.
1129 +
1130 config MACE
1131 tristate "MACE (Power Mac ethernet) support"
1132 depends on NET_ETHERNET && PPC_PMAC && PPC32
1133 diff -Nur linux-2.6.16/drivers/net/Makefile linux-2.6.16-owrt/drivers/net/Makefile
1134 --- linux-2.6.16/drivers/net/Makefile 2006-03-20 06:53:29.000000000 +0100
1135 +++ linux-2.6.16-owrt/drivers/net/Makefile 2006-03-20 14:25:10.000000000 +0100
1136 @@ -38,6 +38,7 @@
1137
1138 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1139
1140 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1141 obj-$(CONFIG_DGRS) += dgrs.o
1142 obj-$(CONFIG_VORTEX) += 3c59x.o
1143 obj-$(CONFIG_TYPHOON) += typhoon.o
1144 diff -Nur linux-2.6.16/drivers/net/natsemi.c linux-2.6.16-owrt/drivers/net/natsemi.c
1145 --- linux-2.6.16/drivers/net/natsemi.c 2006-03-20 06:53:29.000000000 +0100
1146 +++ linux-2.6.16-owrt/drivers/net/natsemi.c 2006-03-20 14:25:10.000000000 +0100
1147 @@ -771,6 +771,49 @@
1148 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1149 static struct ethtool_ops ethtool_ops;
1150
1151 +#ifdef CONFIG_MACH_ARUBA
1152 +
1153 +#include <linux/ctype.h>
1154 +
1155 +#ifndef ERR
1156 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1157 +#endif
1158 +
1159 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1160 +{
1161 + int i, j;
1162 + unsigned char result, value;
1163 +
1164 + for (i=0; i<6; i++) {
1165 + result = 0;
1166 + if (i != 5 && *(macstr+2) != ':') {
1167 + ERR("invalid mac address format: %d %c\n",
1168 + i, *(macstr+2));
1169 + return -EINVAL;
1170 + }
1171 + for (j=0; j<2; j++) {
1172 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1173 + toupper(*macstr)-'A'+10) < 16) {
1174 + result = result*16 + value;
1175 + macstr++;
1176 + }
1177 + else {
1178 + ERR("invalid mac address "
1179 + "character: %c\n", *macstr);
1180 + return -EINVAL;
1181 + }
1182 + }
1183 +
1184 + macstr++;
1185 + dev->dev_addr[i] = result;
1186 + }
1187 +
1188 + dev->dev_addr[5]++;
1189 + return 0;
1190 +}
1191 +
1192 +#endif
1193 +
1194 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1195 {
1196 return (void __iomem *) dev->base_addr;
1197 @@ -859,6 +902,7 @@
1198 goto err_ioremap;
1199 }
1200
1201 +#ifndef CONFIG_MACH_ARUBA
1202 /* Work around the dropped serial bit. */
1203 prev_eedata = eeprom_read(ioaddr, 6);
1204 for (i = 0; i < 3; i++) {
1205 @@ -867,6 +911,19 @@
1206 dev->dev_addr[i*2+1] = eedata >> 7;
1207 prev_eedata = eedata;
1208 }
1209 +#else
1210 + {
1211 + char mac[32];
1212 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1213 + extern char *getenv(char *e);
1214 + memset(mac, 0, 32);
1215 + memcpy(mac, getenv("ethaddr"), 17);
1216 + if (parse_mac_addr(dev, mac)){
1217 + printk("%s: MAC address not found\n", __func__);
1218 + memcpy(dev->dev_addr, def_mac, 6);
1219 + }
1220 + }
1221 +#endif
1222
1223 dev->base_addr = (unsigned long __force) ioaddr;
1224 dev->irq = irq;
1225 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.c linux-2.6.16-owrt/drivers/net/rc32434_eth.c
1226 --- linux-2.6.16/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1227 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.c 2006-03-20 14:25:10.000000000 +0100
1228 @@ -0,0 +1,1268 @@
1229 +/**************************************************************************
1230 + *
1231 + * BRIEF MODULE DESCRIPTION
1232 + * Driver for the IDT RC32434 on-chip ethernet controller.
1233 + *
1234 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1235 + *
1236 + * This program is free software; you can redistribute it and/or modify it
1237 + * under the terms of the GNU General Public License as published by the
1238 + * Free Software Foundation; either version 2 of the License, or (at your
1239 + * option) any later version.
1240 + *
1241 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1242 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1243 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1244 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1245 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1246 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1247 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1248 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1249 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1250 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1251 + *
1252 + * You should have received a copy of the GNU General Public License along
1253 + * with this program; if not, write to the Free Software Foundation, Inc.,
1254 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1255 + *
1256 + *
1257 + **************************************************************************
1258 + * May 2004 rkt, neb
1259 + *
1260 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1261 + *
1262 + * Aug 2004 Sadik
1263 + *
1264 + * Added NAPI
1265 + *
1266 + **************************************************************************
1267 + */
1268 +
1269 +#include <linux/config.h>
1270 +#include <linux/module.h>
1271 +#include <linux/kernel.h>
1272 +#include <linux/moduleparam.h>
1273 +#include <linux/sched.h>
1274 +#include <linux/ctype.h>
1275 +#include <linux/types.h>
1276 +#include <linux/fcntl.h>
1277 +#include <linux/interrupt.h>
1278 +#include <linux/ptrace.h>
1279 +#include <linux/init.h>
1280 +#include <linux/ioport.h>
1281 +#include <linux/proc_fs.h>
1282 +#include <linux/in.h>
1283 +#include <linux/slab.h>
1284 +#include <linux/string.h>
1285 +#include <linux/delay.h>
1286 +#include <linux/netdevice.h>
1287 +#include <linux/etherdevice.h>
1288 +#include <linux/skbuff.h>
1289 +#include <linux/errno.h>
1290 +#include <asm/bootinfo.h>
1291 +#include <asm/system.h>
1292 +#include <asm/bitops.h>
1293 +#include <asm/pgtable.h>
1294 +#include <asm/segment.h>
1295 +#include <asm/io.h>
1296 +#include <asm/dma.h>
1297 +
1298 +#include "rc32434_eth.h"
1299 +
1300 +#define DRIVER_VERSION "(mar2904)"
1301 +
1302 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1303 +
1304 +
1305 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1306 + ((dev)->dev_addr[1]))
1307 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1308 + ((dev)->dev_addr[3] << 16) | \
1309 + ((dev)->dev_addr[4] << 8) | \
1310 + ((dev)->dev_addr[5]))
1311 +
1312 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1313 +static char mac0[18] = "08:00:06:05:40:01";
1314 +
1315 +MODULE_PARM(mac0, "c18");
1316 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1317 +
1318 +static struct rc32434_if_t {
1319 + char *name;
1320 + struct net_device *dev;
1321 + char* mac_str;
1322 + int weight;
1323 + u32 iobase;
1324 + u32 rxdmabase;
1325 + u32 txdmabase;
1326 + int rx_dma_irq;
1327 + int tx_dma_irq;
1328 + int rx_ovr_irq;
1329 + int tx_und_irq;
1330 +} rc32434_iflist[] =
1331 +{
1332 + {
1333 + "rc32434_eth0", NULL, mac0,
1334 + 64,
1335 + ETH0_PhysicalAddress,
1336 + ETH0_RX_DMA_ADDR,
1337 + ETH0_TX_DMA_ADDR,
1338 + ETH0_DMA_RX_IRQ,
1339 + ETH0_DMA_TX_IRQ,
1340 + ETH0_RX_OVR_IRQ,
1341 + ETH0_TX_UND_IRQ
1342 + }
1343 +};
1344 +
1345 +
1346 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1347 +{
1348 + int i, j;
1349 + unsigned char result, value;
1350 +
1351 + for (i=0; i<6; i++) {
1352 + result = 0;
1353 + if (i != 5 && *(macstr+2) != ':') {
1354 + ERR("invalid mac address format: %d %c\n",
1355 + i, *(macstr+2));
1356 + return -EINVAL;
1357 + }
1358 + for (j=0; j<2; j++) {
1359 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1360 + toupper(*macstr)-'A'+10) < 16) {
1361 + result = result*16 + value;
1362 + macstr++;
1363 + }
1364 + else {
1365 + ERR("invalid mac address "
1366 + "character: %c\n", *macstr);
1367 + return -EINVAL;
1368 + }
1369 + }
1370 +
1371 + macstr++;
1372 + dev->dev_addr[i] = result;
1373 + }
1374 +
1375 + return 0;
1376 +}
1377 +
1378 +
1379 +
1380 +static inline void rc32434_abort_tx(struct net_device *dev)
1381 +{
1382 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1383 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1384 +
1385 +}
1386 +
1387 +static inline void rc32434_abort_rx(struct net_device *dev)
1388 +{
1389 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1390 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1391 +
1392 +}
1393 +
1394 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1395 +{
1396 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1397 +}
1398 +
1399 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1400 +{
1401 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1402 +}
1403 +
1404 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1405 +{
1406 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1407 +}
1408 +
1409 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1410 +{
1411 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1412 +}
1413 +
1414 +#ifdef RC32434_PROC_DEBUG
1415 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1416 + int length, int *eof, void *data)
1417 +{
1418 + struct net_device *dev = (struct net_device *)data;
1419 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1420 + int len = 0;
1421 +
1422 + /* print out header */
1423 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1424 + len += sprintf (buf + len,
1425 + "DMA halt count = %10d, DMA run count = %10d\n",
1426 + lp->dma_halt_cnt, lp->dma_run_cnt);
1427 +
1428 + if (fpos >= len) {
1429 + *start = buf;
1430 + *eof = 1;
1431 + return 0;
1432 + }
1433 + *start = buf + fpos;
1434 +
1435 + if ((len -= fpos) > length)
1436 + return length;
1437 + *eof = 1;
1438 +
1439 + return len;
1440 +
1441 +}
1442 +#endif
1443 +
1444 +
1445 +/*
1446 + * Restart the RC32434 ethernet controller.
1447 + */
1448 +static int rc32434_restart(struct net_device *dev)
1449 +{
1450 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1451 +
1452 + /*
1453 + * Disable interrupts
1454 + */
1455 + disable_irq(lp->rx_irq);
1456 + disable_irq(lp->tx_irq);
1457 +#ifdef RC32434_REVISION
1458 + disable_irq(lp->ovr_irq);
1459 +#endif
1460 + disable_irq(lp->und_irq);
1461 +
1462 + /* Mask F E bit in Tx DMA */
1463 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1464 + /* Mask D H E bit in Rx DMA */
1465 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1466 +
1467 + rc32434_init(dev);
1468 + rc32434_multicast_list(dev);
1469 +
1470 + enable_irq(lp->und_irq);
1471 +#ifdef RC32434_REVISION
1472 + enable_irq(lp->ovr_irq);
1473 +#endif
1474 + enable_irq(lp->tx_irq);
1475 + enable_irq(lp->rx_irq);
1476 +
1477 + return 0;
1478 +}
1479 +
1480 +int rc32434_init_module(void)
1481 +{
1482 +#ifdef CONFIG_MACH_ARUBA
1483 + if (mips_machtype != MACH_ARUBA_AP70)
1484 + return 1;
1485 +#endif
1486 +
1487 + printk(KERN_INFO DRIVER_NAME " \n");
1488 + return rc32434_probe(0);
1489 +}
1490 +
1491 +static int rc32434_probe(int port_num)
1492 +{
1493 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1494 + struct rc32434_local *lp = NULL;
1495 + struct net_device *dev = NULL;
1496 + int i, retval,err;
1497 +
1498 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1499 + if(!dev) {
1500 + ERR("rc32434_eth: alloc_etherdev failed\n");
1501 + return -1;
1502 + }
1503 +
1504 + SET_MODULE_OWNER(dev);
1505 + bif->dev = dev;
1506 +
1507 +#ifdef CONFIG_MACH_ARUBA
1508 + {
1509 + extern char * getenv(char *e);
1510 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1511 + }
1512 +#endif
1513 +
1514 + printk("mac: %s\n", bif->mac_str);
1515 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1516 + ERR("MAC address parse failed\n");
1517 + free_netdev(dev);
1518 + return -1;
1519 + }
1520 +
1521 +
1522 + /* Initialize the device structure. */
1523 + if (dev->priv == NULL) {
1524 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1525 + memset(lp, 0, sizeof(struct rc32434_local));
1526 + }
1527 + else {
1528 + lp = (struct rc32434_local *)dev->priv;
1529 + }
1530 +
1531 + lp->rx_irq = bif->rx_dma_irq;
1532 + lp->tx_irq = bif->tx_dma_irq;
1533 + lp->ovr_irq = bif->rx_ovr_irq;
1534 + lp->und_irq = bif->tx_und_irq;
1535 +
1536 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1537 +
1538 + if (!lp->eth_regs) {
1539 + ERR("Can't remap eth registers\n");
1540 + retval = -ENXIO;
1541 + goto probe_err_out;
1542 + }
1543 +
1544 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1545 +
1546 + if (!lp->rx_dma_regs) {
1547 + ERR("Can't remap Rx DMA registers\n");
1548 + retval = -ENXIO;
1549 + goto probe_err_out;
1550 + }
1551 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1552 +
1553 + if (!lp->tx_dma_regs) {
1554 + ERR("Can't remap Tx DMA registers\n");
1555 + retval = -ENXIO;
1556 + goto probe_err_out;
1557 + }
1558 +
1559 +#ifdef RC32434_PROC_DEBUG
1560 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1561 + rc32434_read_proc, dev);
1562 +#endif
1563 +
1564 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1565 + if (!lp->td_ring) {
1566 + ERR("Can't allocate descriptors\n");
1567 + retval = -ENOMEM;
1568 + goto probe_err_out;
1569 + }
1570 +
1571 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1572 +
1573 + /* now convert TD_RING pointer to KSEG1 */
1574 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1575 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1576 +
1577 +
1578 + spin_lock_init(&lp->lock);
1579 +
1580 + dev->base_addr = bif->iobase;
1581 + /* just use the rx dma irq */
1582 + dev->irq = bif->rx_dma_irq;
1583 +
1584 + dev->priv = lp;
1585 +
1586 + dev->open = rc32434_open;
1587 + dev->stop = rc32434_close;
1588 + dev->hard_start_xmit = rc32434_send_packet;
1589 + dev->get_stats = rc32434_get_stats;
1590 + dev->set_multicast_list = &rc32434_multicast_list;
1591 + dev->tx_timeout = rc32434_tx_timeout;
1592 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1593 +
1594 +#ifdef CONFIG_IDT_USE_NAPI
1595 + dev->poll = rc32434_poll;
1596 + dev->weight = bif->weight;
1597 + printk("Using NAPI with weight %d\n",dev->weight);
1598 +#else
1599 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1600 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1601 +#endif
1602 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1603 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1604 +
1605 + if ((err = register_netdev(dev))) {
1606 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1607 + free_netdev(dev);
1608 + retval = -EINVAL;
1609 + goto probe_err_out;
1610 + }
1611 +
1612 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1613 + for (i = 0; i < 6; i++) {
1614 + printk("%2.2x", dev->dev_addr[i]);
1615 + if (i<5)
1616 + printk(":");
1617 + }
1618 + printk("\n");
1619 +
1620 + return 0;
1621 +
1622 + probe_err_out:
1623 + rc32434_cleanup_module();
1624 + ERR(" failed. Returns %d\n", retval);
1625 + return retval;
1626 +
1627 +}
1628 +
1629 +
1630 +static void rc32434_cleanup_module(void)
1631 +{
1632 + int i;
1633 +
1634 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1635 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1636 + if (bif->dev != NULL) {
1637 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1638 + if (lp != NULL) {
1639 + if (lp->eth_regs)
1640 + iounmap((void*)lp->eth_regs);
1641 + if (lp->rx_dma_regs)
1642 + iounmap((void*)lp->rx_dma_regs);
1643 + if (lp->tx_dma_regs)
1644 + iounmap((void*)lp->tx_dma_regs);
1645 + if (lp->td_ring)
1646 + kfree((void*)KSEG0ADDR(lp->td_ring));
1647 +
1648 +#ifdef RC32434_PROC_DEBUG
1649 + if (lp->ps) {
1650 + remove_proc_entry(bif->name, proc_net);
1651 + }
1652 +#endif
1653 + kfree(lp);
1654 + }
1655 +
1656 + unregister_netdev(bif->dev);
1657 + free_netdev(bif->dev);
1658 + kfree(bif->dev);
1659 + }
1660 + }
1661 +}
1662 +
1663 +
1664 +
1665 +static int rc32434_open(struct net_device *dev)
1666 +{
1667 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1668 +
1669 + /* Initialize */
1670 + if (rc32434_init(dev)) {
1671 + ERR("Error: cannot open the Ethernet device\n");
1672 + return -EAGAIN;
1673 + }
1674 +
1675 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1676 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1677 + SA_SHIRQ | SA_INTERRUPT,
1678 + "rc32434 ethernet Rx", dev)) {
1679 + ERR(": unable to get Rx DMA IRQ %d\n",
1680 + lp->rx_irq);
1681 + return -EAGAIN;
1682 + }
1683 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1684 + SA_SHIRQ | SA_INTERRUPT,
1685 + "rc32434 ethernet Tx", dev)) {
1686 + ERR(": unable to get Tx DMA IRQ %d\n",
1687 + lp->tx_irq);
1688 + free_irq(lp->rx_irq, dev);
1689 + return -EAGAIN;
1690 + }
1691 +
1692 +#ifdef RC32434_REVISION
1693 + /* Install handler for overrun error. */
1694 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1695 + SA_SHIRQ | SA_INTERRUPT,
1696 + "Ethernet Overflow", dev)) {
1697 + ERR(": unable to get OVR IRQ %d\n",
1698 + lp->ovr_irq);
1699 + free_irq(lp->rx_irq, dev);
1700 + free_irq(lp->tx_irq, dev);
1701 + return -EAGAIN;
1702 + }
1703 +#endif
1704 +
1705 + /* Install handler for underflow error. */
1706 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1707 + SA_SHIRQ | SA_INTERRUPT,
1708 + "Ethernet Underflow", dev)) {
1709 + ERR(": unable to get UND IRQ %d\n",
1710 + lp->und_irq);
1711 + free_irq(lp->rx_irq, dev);
1712 + free_irq(lp->tx_irq, dev);
1713 +#ifdef RC32434_REVISION
1714 + free_irq(lp->ovr_irq, dev);
1715 +#endif
1716 + return -EAGAIN;
1717 + }
1718 +
1719 +
1720 + return 0;
1721 +}
1722 +
1723 +
1724 +
1725 +
1726 +static int rc32434_close(struct net_device *dev)
1727 +{
1728 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1729 + u32 tmp;
1730 +
1731 + /* Disable interrupts */
1732 + disable_irq(lp->rx_irq);
1733 + disable_irq(lp->tx_irq);
1734 +#ifdef RC32434_REVISION
1735 + disable_irq(lp->ovr_irq);
1736 +#endif
1737 + disable_irq(lp->und_irq);
1738 +
1739 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1740 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1741 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1742 +
1743 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1744 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1745 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1746 +
1747 + free_irq(lp->rx_irq, dev);
1748 + free_irq(lp->tx_irq, dev);
1749 +#ifdef RC32434_REVISION
1750 + free_irq(lp->ovr_irq, dev);
1751 +#endif
1752 + free_irq(lp->und_irq, dev);
1753 + return 0;
1754 +}
1755 +
1756 +
1757 +/* transmit packet */
1758 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1759 +{
1760 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1761 + unsigned long flags;
1762 + u32 length;
1763 + DMAD_t td;
1764 +
1765 +
1766 + spin_lock_irqsave(&lp->lock, flags);
1767 +
1768 + td = &lp->td_ring[lp->tx_chain_tail];
1769 +
1770 + /* stop queue when full, drop pkts if queue already full */
1771 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1772 + lp->tx_full = 1;
1773 +
1774 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1775 + netif_stop_queue(dev);
1776 + }
1777 + else {
1778 + lp->stats.tx_dropped++;
1779 + dev_kfree_skb_any(skb);
1780 + spin_unlock_irqrestore(&lp->lock, flags);
1781 + return 1;
1782 + }
1783 + }
1784 +
1785 + lp->tx_count ++;
1786 +
1787 + lp->tx_skb[lp->tx_chain_tail] = skb;
1788 +
1789 + length = skb->len;
1790 +
1791 + /* Setup the transmit descriptor. */
1792 + td->ca = CPHYSADDR(skb->data);
1793 +
1794 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1795 + if( lp->tx_chain_status == empty ) {
1796 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1797 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1798 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1799 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1800 + }
1801 + else {
1802 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1803 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1804 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1805 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1806 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1807 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1808 + lp->tx_chain_status = empty;
1809 + }
1810 + }
1811 + else {
1812 + if( lp->tx_chain_status == empty ) {
1813 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1814 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1815 + lp->tx_chain_status = filled;
1816 + }
1817 + else {
1818 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1819 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1820 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1821 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1822 + }
1823 + }
1824 +
1825 + dev->trans_start = jiffies;
1826 +
1827 + spin_unlock_irqrestore(&lp->lock, flags);
1828 +
1829 + return 0;
1830 +}
1831 +
1832 +
1833 +/* Ethernet MII-PHY Handler */
1834 +static void rc32434_mii_handler(unsigned long data)
1835 +{
1836 + struct net_device *dev = (struct net_device *)data;
1837 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1838 + unsigned long flags;
1839 + unsigned long duplex_status;
1840 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1841 +
1842 + spin_lock_irqsave(&lp->lock, flags);
1843 +
1844 + /* Two ports are using the same MII, the difference is the PHY address */
1845 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1846 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1847 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1848 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1849 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1850 +
1851 + ERR("irq:%x port_addr:%x RDD:%x\n",
1852 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1853 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1854 + if(duplex_status != lp->duplex_mode) {
1855 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1856 + lp->duplex_mode = duplex_status;
1857 + rc32434_restart(dev);
1858 + }
1859 +
1860 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1861 + add_timer(&lp->mii_phy_timer);
1862 +
1863 + spin_unlock_irqrestore(&lp->lock, flags);
1864 +
1865 +}
1866 +
1867 +#ifdef RC32434_REVISION
1868 +/* Ethernet Rx Overflow interrupt */
1869 +static irqreturn_t
1870 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1871 +{
1872 + struct net_device *dev = (struct net_device *)dev_id;
1873 + struct rc32434_local *lp;
1874 + unsigned int ovr;
1875 + irqreturn_t retval = IRQ_NONE;
1876 +
1877 + ASSERT(dev != NULL);
1878 +
1879 + lp = (struct rc32434_local *)dev->priv;
1880 + spin_lock(&lp->lock);
1881 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1882 +
1883 + if(ovr & ETHINTFC_ovr_m) {
1884 + netif_stop_queue(dev);
1885 +
1886 + /* clear OVR bit */
1887 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1888 +
1889 + /* Restart interface */
1890 + rc32434_restart(dev);
1891 + retval = IRQ_HANDLED;
1892 + }
1893 + spin_unlock(&lp->lock);
1894 +
1895 + return retval;
1896 +}
1897 +
1898 +#endif
1899 +
1900 +
1901 +/* Ethernet Tx Underflow interrupt */
1902 +static irqreturn_t
1903 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1904 +{
1905 + struct net_device *dev = (struct net_device *)dev_id;
1906 + struct rc32434_local *lp;
1907 + unsigned int und;
1908 + irqreturn_t retval = IRQ_NONE;
1909 +
1910 + ASSERT(dev != NULL);
1911 +
1912 + lp = (struct rc32434_local *)dev->priv;
1913 +
1914 + spin_lock(&lp->lock);
1915 +
1916 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1917 +
1918 + if(und & ETHINTFC_und_m) {
1919 + netif_stop_queue(dev);
1920 +
1921 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1922 +
1923 + /* Restart interface */
1924 + rc32434_restart(dev);
1925 + retval = IRQ_HANDLED;
1926 + }
1927 +
1928 + spin_unlock(&lp->lock);
1929 +
1930 + return retval;
1931 +}
1932 +
1933 +
1934 +/* Ethernet Rx DMA interrupt */
1935 +static irqreturn_t
1936 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1937 +{
1938 + struct net_device *dev = (struct net_device *)dev_id;
1939 + struct rc32434_local* lp;
1940 + volatile u32 dmas,dmasm;
1941 + irqreturn_t retval;
1942 +
1943 + ASSERT(dev != NULL);
1944 +
1945 + lp = (struct rc32434_local *)dev->priv;
1946 +
1947 + spin_lock(&lp->lock);
1948 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1949 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1950 + /* Mask D H E bit in Rx DMA */
1951 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1952 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1953 +#ifdef CONFIG_IDT_USE_NAPI
1954 + if(netif_rx_schedule_prep(dev))
1955 + __netif_rx_schedule(dev);
1956 +#else
1957 + tasklet_hi_schedule(lp->rx_tasklet);
1958 +#endif
1959 +
1960 + if (dmas & DMAS_e_m)
1961 + ERR(": DMA error\n");
1962 +
1963 + retval = IRQ_HANDLED;
1964 + }
1965 + else
1966 + retval = IRQ_NONE;
1967 +
1968 + spin_unlock(&lp->lock);
1969 + return retval;
1970 +}
1971 +
1972 +#ifdef CONFIG_IDT_USE_NAPI
1973 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1974 +#else
1975 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1976 +#endif
1977 +{
1978 + struct net_device *dev = (struct net_device *)rx_data_dev;
1979 + struct rc32434_local* lp = netdev_priv(dev);
1980 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1981 + struct sk_buff *skb, *skb_new;
1982 + u8* pkt_buf;
1983 + u32 devcs, count, pkt_len, pktuncrc_len;
1984 + volatile u32 dmas;
1985 +#ifdef CONFIG_IDT_USE_NAPI
1986 + u32 received = 0;
1987 + int rx_work_limit = min(*budget,dev->quota);
1988 +#else
1989 + unsigned long flags;
1990 + spin_lock_irqsave(&lp->lock, flags);
1991 +#endif
1992 +
1993 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1994 +#ifdef CONFIG_IDT_USE_NAPI
1995 + if(--rx_work_limit <0)
1996 + {
1997 + break;
1998 + }
1999 +#endif
2000 + /* init the var. used for the later operations within the while loop */
2001 + skb_new = NULL;
2002 + devcs = rd->devcs;
2003 + pkt_len = RCVPKT_LENGTH(devcs);
2004 + skb = lp->rx_skb[lp->rx_next_done];
2005 +
2006 + if (count < 64) {
2007 + lp->stats.rx_errors++;
2008 + lp->stats.rx_dropped++;
2009 + }
2010 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
2011 + /* check that this is a whole packet */
2012 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
2013 + lp->stats.rx_errors++;
2014 + lp->stats.rx_dropped++;
2015 + }
2016 + else if ( (devcs & ETHRX_rok_m) ) {
2017 +
2018 + {
2019 + /* must be the (first and) last descriptor then */
2020 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
2021 +
2022 + pktuncrc_len = pkt_len - 4;
2023 + /* invalidate the cache */
2024 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2025 +
2026 + /* Malloc up new buffer. */
2027 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2028 +
2029 + if (skb_new != NULL){
2030 + /* Make room */
2031 + skb_put(skb, pktuncrc_len);
2032 +
2033 + skb->protocol = eth_type_trans(skb, dev);
2034 +
2035 + /* pass the packet to upper layers */
2036 +#ifdef CONFIG_IDT_USE_NAPI
2037 + netif_receive_skb(skb);
2038 +#else
2039 + netif_rx(skb);
2040 +#endif
2041 +
2042 + dev->last_rx = jiffies;
2043 + lp->stats.rx_packets++;
2044 + lp->stats.rx_bytes += pktuncrc_len;
2045 +
2046 + if (IS_RCV_MP(devcs))
2047 + lp->stats.multicast++;
2048 +
2049 + /* 16 bit align */
2050 + skb_reserve(skb_new, 2);
2051 +
2052 + skb_new->dev = dev;
2053 + lp->rx_skb[lp->rx_next_done] = skb_new;
2054 + }
2055 + else {
2056 + ERR("no memory, dropping rx packet.\n");
2057 + lp->stats.rx_errors++;
2058 + lp->stats.rx_dropped++;
2059 + }
2060 + }
2061 +
2062 + }
2063 + else {
2064 + /* This should only happen if we enable accepting broken packets */
2065 + lp->stats.rx_errors++;
2066 + lp->stats.rx_dropped++;
2067 +
2068 + /* add statistics counters */
2069 + if (IS_RCV_CRC_ERR(devcs)) {
2070 + DBG(2, "RX CRC error\n");
2071 + lp->stats.rx_crc_errors++;
2072 + }
2073 + else if (IS_RCV_LOR_ERR(devcs)) {
2074 + DBG(2, "RX LOR error\n");
2075 + lp->stats.rx_length_errors++;
2076 + }
2077 + else if (IS_RCV_LE_ERR(devcs)) {
2078 + DBG(2, "RX LE error\n");
2079 + lp->stats.rx_length_errors++;
2080 + }
2081 + else if (IS_RCV_OVR_ERR(devcs)) {
2082 + lp->stats.rx_over_errors++;
2083 + }
2084 + else if (IS_RCV_CV_ERR(devcs)) {
2085 + /* code violation */
2086 + DBG(2, "RX CV error\n");
2087 + lp->stats.rx_frame_errors++;
2088 + }
2089 + else if (IS_RCV_CES_ERR(devcs)) {
2090 + DBG(2, "RX Preamble error\n");
2091 + }
2092 + }
2093 +
2094 + rd->devcs = 0;
2095 +
2096 + /* restore descriptor's curr_addr */
2097 + if(skb_new)
2098 + rd->ca = CPHYSADDR(skb_new->data);
2099 + else
2100 + rd->ca = CPHYSADDR(skb->data);
2101 +
2102 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2103 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2104 +
2105 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2106 + rd = &lp->rd_ring[lp->rx_next_done];
2107 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2108 + }
2109 +#ifdef CONFIG_IDT_USE_NAPI
2110 + dev->quota -= received;
2111 + *budget =- received;
2112 + if(rx_work_limit < 0)
2113 + goto not_done;
2114 +#endif
2115 +
2116 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2117 +
2118 + if(dmas & DMAS_h_m) {
2119 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2120 +#ifdef RC32434_PROC_DEBUG
2121 + lp->dma_halt_cnt++;
2122 +#endif
2123 + rd->devcs = 0;
2124 + skb = lp->rx_skb[lp->rx_next_done];
2125 + rd->ca = CPHYSADDR(skb->data);
2126 + rc32434_chain_rx(lp,rd);
2127 + }
2128 +
2129 +#ifdef CONFIG_IDT_USE_NAPI
2130 + netif_rx_complete(dev);
2131 +#endif
2132 + /* Enable D H E bit in Rx DMA */
2133 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2134 +#ifdef CONFIG_IDT_USE_NAPI
2135 + return 0;
2136 + not_done:
2137 + return 1;
2138 +#else
2139 + spin_unlock_irqrestore(&lp->lock, flags);
2140 + return;
2141 +#endif
2142 +
2143 +
2144 +}
2145 +
2146 +
2147 +
2148 +/* Ethernet Tx DMA interrupt */
2149 +static irqreturn_t
2150 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2151 +{
2152 + struct net_device *dev = (struct net_device *)dev_id;
2153 + struct rc32434_local *lp;
2154 + volatile u32 dmas,dmasm;
2155 + irqreturn_t retval;
2156 +
2157 + ASSERT(dev != NULL);
2158 +
2159 + lp = (struct rc32434_local *)dev->priv;
2160 +
2161 + spin_lock(&lp->lock);
2162 +
2163 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2164 +
2165 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2166 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2167 + /* Mask F E bit in Tx DMA */
2168 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2169 +
2170 + tasklet_hi_schedule(lp->tx_tasklet);
2171 +
2172 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2173 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2174 + lp->tx_chain_status = empty;
2175 + lp->tx_chain_head = lp->tx_chain_tail;
2176 + dev->trans_start = jiffies;
2177 + }
2178 +
2179 + if (dmas & DMAS_e_m)
2180 + ERR(": DMA error\n");
2181 +
2182 + retval = IRQ_HANDLED;
2183 + }
2184 + else
2185 + retval = IRQ_NONE;
2186 +
2187 + spin_unlock(&lp->lock);
2188 +
2189 + return retval;
2190 +}
2191 +
2192 +
2193 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2194 +{
2195 + struct net_device *dev = (struct net_device *)tx_data_dev;
2196 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2197 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2198 + u32 devcs;
2199 + unsigned long flags;
2200 + volatile u32 dmas;
2201 +
2202 + spin_lock_irqsave(&lp->lock, flags);
2203 +
2204 + /* process all desc that are done */
2205 + while(IS_DMA_FINISHED(td->control)) {
2206 + if(lp->tx_full == 1) {
2207 + netif_wake_queue(dev);
2208 + lp->tx_full = 0;
2209 + }
2210 +
2211 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2212 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2213 + lp->stats.tx_errors++;
2214 + lp->stats.tx_dropped++;
2215 +
2216 + /* should never happen */
2217 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2218 + }
2219 + else if (IS_TX_TOK(devcs)) {
2220 + lp->stats.tx_packets++;
2221 + }
2222 + else {
2223 + lp->stats.tx_errors++;
2224 + lp->stats.tx_dropped++;
2225 +
2226 + /* underflow */
2227 + if (IS_TX_UND_ERR(devcs))
2228 + lp->stats.tx_fifo_errors++;
2229 +
2230 + /* oversized frame */
2231 + if (IS_TX_OF_ERR(devcs))
2232 + lp->stats.tx_aborted_errors++;
2233 +
2234 + /* excessive deferrals */
2235 + if (IS_TX_ED_ERR(devcs))
2236 + lp->stats.tx_carrier_errors++;
2237 +
2238 + /* collisions: medium busy */
2239 + if (IS_TX_EC_ERR(devcs))
2240 + lp->stats.collisions++;
2241 +
2242 + /* late collision */
2243 + if (IS_TX_LC_ERR(devcs))
2244 + lp->stats.tx_window_errors++;
2245 +
2246 + }
2247 +
2248 + /* We must always free the original skb */
2249 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2250 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2251 + lp->tx_skb[lp->tx_next_done] = NULL;
2252 + }
2253 +
2254 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2255 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2256 + lp->td_ring[lp->tx_next_done].link = 0;
2257 + lp->td_ring[lp->tx_next_done].ca = 0;
2258 + lp->tx_count --;
2259 +
2260 + /* go on to next transmission */
2261 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2262 + td = &lp->td_ring[lp->tx_next_done];
2263 +
2264 + }
2265 +
2266 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2267 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2268 +
2269 + /* Enable F E bit in Tx DMA */
2270 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2271 + spin_unlock_irqrestore(&lp->lock, flags);
2272 +
2273 +}
2274 +
2275 +
2276 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2277 +{
2278 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2279 + return &lp->stats;
2280 +}
2281 +
2282 +
2283 +/*
2284 + * Set or clear the multicast filter for this adaptor.
2285 + */
2286 +static void rc32434_multicast_list(struct net_device *dev)
2287 +{
2288 + /* listen to broadcasts always and to treat */
2289 + /* IFF bits independantly */
2290 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2291 + unsigned long flags;
2292 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2293 +
2294 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2295 + recognise |= ETHARC_pro_m;
2296 +
2297 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2298 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2299 + else if (dev->mc_count > 0) {
2300 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2301 + recognise |= ETHARC_am_m; /* for the time being */
2302 + }
2303 +
2304 + spin_lock_irqsave(&lp->lock, flags);
2305 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2306 + spin_unlock_irqrestore(&lp->lock, flags);
2307 +}
2308 +
2309 +
2310 +static void rc32434_tx_timeout(struct net_device *dev)
2311 +{
2312 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2313 + unsigned long flags;
2314 +
2315 + spin_lock_irqsave(&lp->lock, flags);
2316 + rc32434_restart(dev);
2317 + spin_unlock_irqrestore(&lp->lock, flags);
2318 +
2319 +}
2320 +
2321 +
2322 +/*
2323 + * Initialize the RC32434 ethernet controller.
2324 + */
2325 +static int rc32434_init(struct net_device *dev)
2326 +{
2327 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2328 + int i, j;
2329 +
2330 + /* Disable DMA */
2331 + rc32434_abort_tx(dev);
2332 + rc32434_abort_rx(dev);
2333 +
2334 + /* reset ethernet logic */
2335 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2336 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2337 + dev->trans_start = jiffies;
2338 +
2339 + /* Enable Ethernet Interface */
2340 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2341 +
2342 +#ifndef CONFIG_IDT_USE_NAPI
2343 + tasklet_disable(lp->rx_tasklet);
2344 +#endif
2345 + tasklet_disable(lp->tx_tasklet);
2346 +
2347 + /* Initialize the transmit Descriptors */
2348 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2349 + lp->td_ring[i].control = DMAD_iof_m;
2350 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2351 + lp->td_ring[i].ca = 0;
2352 + lp->td_ring[i].link = 0;
2353 + if (lp->tx_skb[i] != NULL) {
2354 + dev_kfree_skb_any(lp->tx_skb[i]);
2355 + lp->tx_skb[i] = NULL;
2356 + }
2357 + }
2358 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2359 + lp-> tx_chain_status = empty;
2360 +
2361 + /*
2362 + * Initialize the receive descriptors so that they
2363 + * become a circular linked list, ie. let the last
2364 + * descriptor point to the first again.
2365 + */
2366 + for (i=0; i<RC32434_NUM_RDS; i++) {
2367 + struct sk_buff *skb = lp->rx_skb[i];
2368 +
2369 + if (lp->rx_skb[i] == NULL) {
2370 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2371 + if (skb == NULL) {
2372 + ERR("No memory in the system\n");
2373 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2374 + if (lp->rx_skb[j] != NULL)
2375 + dev_kfree_skb_any(lp->rx_skb[j]);
2376 +
2377 + return 1;
2378 + }
2379 + else {
2380 + skb->dev = dev;
2381 + skb_reserve(skb, 2);
2382 + lp->rx_skb[i] = skb;
2383 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2384 +
2385 + }
2386 + }
2387 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2388 + lp->rd_ring[i].devcs = 0;
2389 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2390 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2391 +
2392 + }
2393 + /* loop back */
2394 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2395 + lp->rx_next_done = 0;
2396 +
2397 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2398 + lp->rx_chain_head = 0;
2399 + lp->rx_chain_tail = 0;
2400 + lp->rx_chain_status = empty;
2401 +
2402 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2403 + /* Start Rx DMA */
2404 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2405 +
2406 + /* Enable F E bit in Tx DMA */
2407 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2408 + /* Enable D H E bit in Rx DMA */
2409 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2410 +
2411 + /* Accept only packets destined for this Ethernet device address */
2412 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2413 +
2414 + /* Set all Ether station address registers to their initial values */
2415 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2416 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2417 +
2418 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2419 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2420 +
2421 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2422 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2423 +
2424 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2425 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2426 +
2427 +
2428 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2429 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2430 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2431 +
2432 + /* Back to back inter-packet-gap */
2433 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2434 + /* Non - Back to back inter-packet-gap */
2435 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2436 +
2437 + /* Management Clock Prescaler Divisor */
2438 + /* Clock independent setting */
2439 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2440 + &lp->eth_regs->ethmcp);
2441 +
2442 + /* don't transmit until fifo contains 48b */
2443 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2444 +
2445 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2446 +
2447 +#ifndef CONFIG_IDT_USE_NAPI
2448 + tasklet_enable(lp->rx_tasklet);
2449 +#endif
2450 + tasklet_enable(lp->tx_tasklet);
2451 +
2452 + netif_start_queue(dev);
2453 +
2454 +
2455 + return 0;
2456 +
2457 +}
2458 +
2459 +
2460 +#ifndef MODULE
2461 +
2462 +static int __init rc32434_setup(char *options)
2463 +{
2464 + /* no options yet */
2465 + return 1;
2466 +}
2467 +
2468 +static int __init rc32434_setup_ethaddr0(char *options)
2469 +{
2470 + memcpy(mac0, options, 17);
2471 + mac0[17]= '\0';
2472 + return 1;
2473 +}
2474 +
2475 +__setup("rc32434eth=", rc32434_setup);
2476 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2477 +
2478 +
2479 +#endif /* MODULE */
2480 +
2481 +module_init(rc32434_init_module);
2482 +module_exit(rc32434_cleanup_module);
2483 +
2484 +
2485 +
2486 +
2487 +
2488 +
2489 +
2490 +
2491 +
2492 +
2493 +
2494 +
2495 +
2496 +
2497 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.h linux-2.6.16-owrt/drivers/net/rc32434_eth.h
2498 --- linux-2.6.16/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2499 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.h 2006-03-20 14:25:10.000000000 +0100
2500 @@ -0,0 +1,187 @@
2501 +/**************************************************************************
2502 + *
2503 + * BRIEF MODULE DESCRIPTION
2504 + * Definitions for IDT RC32434 on-chip ethernet controller.
2505 + *
2506 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2507 + *
2508 + * This program is free software; you can redistribute it and/or modify it
2509 + * under the terms of the GNU General Public License as published by the
2510 + * Free Software Foundation; either version 2 of the License, or (at your
2511 + * option) any later version.
2512 + *
2513 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2514 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2515 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2516 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2517 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2518 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2519 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2520 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2521 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2522 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2523 + *
2524 + * You should have received a copy of the GNU General Public License along
2525 + * with this program; if not, write to the Free Software Foundation, Inc.,
2526 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2527 + *
2528 + *
2529 + **************************************************************************
2530 + * May 2004 rkt, neb
2531 + *
2532 + * Initial Release
2533 + *
2534 + * Aug 2004
2535 + *
2536 + * Added NAPI
2537 + *
2538 + **************************************************************************
2539 + */
2540 +
2541 +
2542 +#include <asm/idt-boards/rc32434/rc32434.h>
2543 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2544 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2545 +
2546 +#define RC32434_DEBUG 2
2547 +//#define RC32434_PROC_DEBUG
2548 +#undef RC32434_DEBUG
2549 +
2550 +#ifdef RC32434_DEBUG
2551 +
2552 +/* use 0 for production, 1 for verification, >2 for debug */
2553 +static int rc32434_debug = RC32434_DEBUG;
2554 +#define ASSERT(expr) \
2555 + if(!(expr)) { \
2556 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2557 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2558 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2559 +#else
2560 +#define ASSERT(expr) do {} while (0)
2561 +#define DBG(lvl, format, arg...) do {} while (0)
2562 +#endif
2563 +
2564 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2565 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2566 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2567 +
2568 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2569 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2570 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2571 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2572 +
2573 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2574 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2575 +
2576 +/* the following must be powers of two */
2577 +#ifdef CONFIG_IDT_USE_NAPI
2578 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2579 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2580 +#else
2581 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2582 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2583 +#endif
2584 +
2585 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2586 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2587 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2588 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2589 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2590 +
2591 +#define RC32434_TX_TIMEOUT HZ * 100
2592 +
2593 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2594 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2595 +
2596 +enum status { filled, empty};
2597 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2598 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2599 +
2600 +
2601 +/* Information that need to be kept for each board. */
2602 +struct rc32434_local {
2603 + ETH_t eth_regs;
2604 + DMA_Chan_t rx_dma_regs;
2605 + DMA_Chan_t tx_dma_regs;
2606 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2607 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2608 +
2609 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2610 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2611 +
2612 +#ifndef CONFIG_IDT_USE_NAPI
2613 + struct tasklet_struct * rx_tasklet;
2614 +#endif
2615 + struct tasklet_struct * tx_tasklet;
2616 +
2617 + int rx_next_done;
2618 + int rx_chain_head;
2619 + int rx_chain_tail;
2620 + enum status rx_chain_status;
2621 +
2622 + int tx_next_done;
2623 + int tx_chain_head;
2624 + int tx_chain_tail;
2625 + enum status tx_chain_status;
2626 + int tx_count;
2627 + int tx_full;
2628 +
2629 + struct timer_list mii_phy_timer;
2630 + unsigned long duplex_mode;
2631 +
2632 + int rx_irq;
2633 + int tx_irq;
2634 + int ovr_irq;
2635 + int und_irq;
2636 +
2637 + struct net_device_stats stats;
2638 + spinlock_t lock;
2639 +
2640 + /* debug /proc entry */
2641 + struct proc_dir_entry *ps;
2642 + int dma_halt_cnt; int dma_run_cnt;
2643 +};
2644 +
2645 +extern unsigned int idt_cpu_freq;
2646 +
2647 +/* Index to functions, as function prototypes. */
2648 +static int rc32434_open(struct net_device *dev);
2649 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2650 +static void rc32434_mii_handler(unsigned long data);
2651 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2652 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2653 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2654 +#ifdef RC32434_REVISION
2655 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2656 +#endif
2657 +static int rc32434_close(struct net_device *dev);
2658 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2659 +static void rc32434_multicast_list(struct net_device *dev);
2660 +static int rc32434_init(struct net_device *dev);
2661 +static void rc32434_tx_timeout(struct net_device *dev);
2662 +
2663 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2664 +#ifdef CONFIG_IDT_USE_NAPI
2665 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2666 +#else
2667 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2668 +#endif
2669 +static void rc32434_cleanup_module(void);
2670 +static int rc32434_probe(int port_num);
2671 +int rc32434_init_module(void);
2672 +
2673 +
2674 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2675 +{
2676 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2677 + rc32434_writel(0x10, &ch->dmac);
2678 +
2679 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2680 + dev->trans_start = jiffies;
2681 +
2682 + rc32434_writel(0, &ch->dmas);
2683 + }
2684 +
2685 + rc32434_writel(0, &ch->dmadptr);
2686 + rc32434_writel(0, &ch->dmandptr);
2687 +}
2688 diff -Nur linux-2.6.16/include/asm-mips/bootinfo.h linux-2.6.16-owrt/include/asm-mips/bootinfo.h
2689 --- linux-2.6.16/include/asm-mips/bootinfo.h 2006-03-20 06:53:29.000000000 +0100
2690 +++ linux-2.6.16-owrt/include/asm-mips/bootinfo.h 2006-03-20 14:25:10.000000000 +0100
2691 @@ -218,6 +218,17 @@
2692 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2693 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2694
2695 +
2696 +/*
2697 + * Valid machtype for group ARUBA
2698 + */
2699 +#define MACH_GROUP_ARUBA 23
2700 +#define MACH_ARUBA_UNKNOWN 0
2701 +#define MACH_ARUBA_AP60 1
2702 +#define MACH_ARUBA_AP65 2
2703 +#define MACH_ARUBA_AP70 3
2704 +#define MACH_ARUBA_AP40 4
2705 +
2706 #define CL_SIZE COMMAND_LINE_SIZE
2707
2708 const char *get_system_type(void);
2709 diff -Nur linux-2.6.16/include/asm-mips/cpu.h linux-2.6.16-owrt/include/asm-mips/cpu.h
2710 --- linux-2.6.16/include/asm-mips/cpu.h 2006-03-20 06:53:29.000000000 +0100
2711 +++ linux-2.6.16-owrt/include/asm-mips/cpu.h 2006-03-20 14:25:10.000000000 +0100
2712 @@ -53,6 +53,9 @@
2713 #define PRID_IMP_R12000 0x0e00
2714 #define PRID_IMP_R8000 0x1000
2715 #define PRID_IMP_PR4450 0x1200
2716 +#define PRID_IMP_RC32334 0x1800
2717 +#define PRID_IMP_RC32355 0x1900
2718 +#define PRID_IMP_RC32365 0x1900
2719 #define PRID_IMP_R4600 0x2000
2720 #define PRID_IMP_R4700 0x2100
2721 #define PRID_IMP_TX39 0x2200
2722 @@ -196,7 +199,8 @@
2723 #define CPU_34K 60
2724 #define CPU_PR4450 61
2725 #define CPU_SB1A 62
2726 -#define CPU_LAST 62
2727 +#define CPU_RC32300 63
2728 +#define CPU_LAST 63
2729
2730 /*
2731 * ISA Level encodings
2732 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2733 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2734 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-03-20 14:25:10.000000000 +0100
2735 @@ -0,0 +1,142 @@
2736 +/**************************************************************************
2737 + *
2738 + * BRIEF MODULE DESCRIPTION
2739 + * RC32300 helper routines
2740 + *
2741 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2742 + *
2743 + * This program is free software; you can redistribute it and/or modify it
2744 + * under the terms of the GNU General Public License as published by the
2745 + * Free Software Foundation; either version 2 of the License, or (at your
2746 + * option) any later version.
2747 + *
2748 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2749 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2750 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2751 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2752 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2753 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2754 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2755 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2756 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2757 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2758 + *
2759 + * You should have received a copy of the GNU General Public License along
2760 + * with this program; if not, write to the Free Software Foundation, Inc.,
2761 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2762 + *
2763 + *
2764 + **************************************************************************
2765 + * May 2004 P. Sadik.
2766 + *
2767 + * Initial Release
2768 + *
2769 + *
2770 + *
2771 + **************************************************************************
2772 + */
2773 +
2774 +#ifndef __IDT_RC32300_H__
2775 +#define __IDT_RC32300_H__
2776 +
2777 +#include <linux/delay.h>
2778 +#include <asm/io.h>
2779 +
2780 +
2781 +/* cpu pipeline flush */
2782 +static inline void rc32300_sync(void)
2783 +{
2784 + __asm__ volatile ("sync");
2785 +}
2786 +
2787 +static inline void rc32300_sync_udelay(int us)
2788 +{
2789 + __asm__ volatile ("sync");
2790 + udelay(us);
2791 +}
2792 +
2793 +static inline void rc32300_sync_delay(int ms)
2794 +{
2795 + __asm__ volatile ("sync");
2796 + mdelay(ms);
2797 +}
2798 +
2799 +/*
2800 + * Macros to access internal RC32300 registers. No byte
2801 + * swapping should be done when accessing the internal
2802 + * registers.
2803 + */
2804 +
2805 +static inline u8 rc32300_readb(unsigned long pa)
2806 +{
2807 + return *((volatile u8 *)KSEG1ADDR(pa));
2808 +}
2809 +static inline u16 rc32300_readw(unsigned long pa)
2810 +{
2811 + return *((volatile u16 *)KSEG1ADDR(pa));
2812 +}
2813 +static inline u32 rc32300_readl(unsigned long pa)
2814 +{
2815 + return *((volatile u32 *)KSEG1ADDR(pa));
2816 +}
2817 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2818 +{
2819 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2820 +}
2821 +static inline void rc32300_writew(u16 val, unsigned long pa)
2822 +{
2823 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2824 +}
2825 +static inline void rc32300_writel(u32 val, unsigned long pa)
2826 +{
2827 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2828 +}
2829 +
2830 +
2831 +#define local_readb __raw_readb
2832 +#define local_readw __raw_readw
2833 +#define local_readl __raw_readl
2834 +
2835 +#define local_writeb __raw_writeb
2836 +#define local_writew __raw_writew
2837 +#define local_writel __raw_writel
2838 +
2839 +
2840 +/*
2841 + * C access to CLZ and CLO instructions
2842 + * (count leading zeroes/ones).
2843 + */
2844 +static inline int rc32300_clz(unsigned long val)
2845 +{
2846 + int ret;
2847 + __asm__ volatile (
2848 + ".set\tnoreorder\n\t"
2849 + ".set\tnoat\n\t"
2850 + ".set\tmips32\n\t"
2851 + "clz\t%0,%1\n\t"
2852 + ".set\tmips0\n\t"
2853 + ".set\tat\n\t"
2854 + ".set\treorder"
2855 + : "=r" (ret)
2856 + : "r" (val));
2857 +
2858 + return ret;
2859 +}
2860 +static inline int rc32300_clo(unsigned long val)
2861 +{
2862 + int ret;
2863 + __asm__ volatile (
2864 + ".set\tnoreorder\n\t"
2865 + ".set\tnoat\n\t"
2866 + ".set\tmips32\n\t"
2867 + "clo\t%0,%1\n\t"
2868 + ".set\tmips0\n\t"
2869 + ".set\tat\n\t"
2870 + ".set\treorder"
2871 + : "=r" (ret)
2872 + : "r" (val));
2873 +
2874 + return ret;
2875 +}
2876 +
2877 +#endif // __IDT_RC32300_H__
2878 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2879 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2880 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-03-20 14:25:10.000000000 +0100
2881 @@ -0,0 +1,207 @@
2882 +/**************************************************************************
2883 + *
2884 + * BRIEF MODULE DESCRIPTION
2885 + * Definitions for IDT RC32334 CPU.
2886 + *
2887 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2888 + *
2889 + * This program is free software; you can redistribute it and/or modify it
2890 + * under the terms of the GNU General Public License as published by the
2891 + * Free Software Foundation; either version 2 of the License, or (at your
2892 + * option) any later version.
2893 + *
2894 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2895 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2896 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2897 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2898 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2899 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2900 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2901 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2902 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2903 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2904 + *
2905 + * You should have received a copy of the GNU General Public License along
2906 + * with this program; if not, write to the Free Software Foundation, Inc.,
2907 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2908 + *
2909 + *
2910 + **************************************************************************
2911 + * May 2004 P. Sadik.
2912 + *
2913 + * Initial Release
2914 + *
2915 + *
2916 + *
2917 + **************************************************************************
2918 + */
2919 +
2920 +
2921 +#ifndef __IDT_RC32334_H__
2922 +#define __IDT_RC32334_H__
2923 +
2924 +#include <linux/delay.h>
2925 +#include <asm/io.h>
2926 +
2927 +/* Base address of internal registers */
2928 +#define RC32334_REG_BASE 0x18000000
2929 +
2930 +/* CPU and IP Bus Control */
2931 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2932 +#define CPU_BTA 0xffffe204 // virtual!
2933 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2934 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2935 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2936 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2937 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2938 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2939 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2940 +
2941 +/* Memory Controller */
2942 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2943 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2944 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2945 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2946 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2947 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2948 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2949 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2950 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2951 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2952 +
2953 +/* PCI Controller */
2954 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2955 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2956 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2957 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2958 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2959 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2960 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2961 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2962 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2963 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2964 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2965 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2966 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2967 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2968 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2969 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2970 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2971 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2972 +
2973 +/* Timers */
2974 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2975 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2976 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2977 +#define TIMER_REG_OFFSET 0x10
2978 +
2979 +/* Programmable I/O */
2980 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2981 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2982 +
2983 +/*
2984 + * DMA
2985 + *
2986 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2987 + *
2988 + * DMA0: 18001400
2989 + * DMA1: 18001440
2990 + * DMA2: 18001900
2991 + * DMA3: 18001940
2992 + * NB: dma number must be immediate value or variable.
2993 + * It MUST NOT be a function since it would get called twice!
2994 + */
2995 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2996 +
2997 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2998 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2999 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
3000 +
3001 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
3002 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
3003 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
3004 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
3005 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
3006 +
3007 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
3008 +
3009 +/* Expansion Interrupt Controller */
3010 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
3011 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
3012 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
3013 +#define IC_GROUP_OFFSET 0x10
3014 +
3015 +#define NUM_INTR_GROUPS 15
3016 +/*
3017 + * The IRQ mapping is as follows:
3018 + *
3019 + * IRQ Mapped To
3020 + * --- -------------------
3021 + * 0 SW0 (IP0) SW0 intr
3022 + * 1 SW1 (IP1) SW1 intr
3023 + * 2 Int0 (IP2) board-specific
3024 + * 3 Int1 (IP3) board-specific
3025 + * 4 Int2 (IP4) board-specific
3026 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
3027 + * 6 Int4 (IP6) board-specific
3028 + * 7 Int5 (IP7) CP0 Timer
3029 + *
3030 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3031 + * internally on the RC32334 is routed to the Expansion
3032 + * Interrupt Controller.
3033 + */
3034 +#define MIPS_CPU_TIMER_IRQ 7
3035 +
3036 +#define GROUP1_IRQ_BASE 8 // bus error
3037 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3038 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3039 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3040 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3041 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3042 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3043 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3044 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3045 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3046 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3047 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3048 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3049 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3050 +
3051 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3052 +
3053 +/* 16550 UARTs */
3054 +#ifdef __MIPSEB__
3055 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3056 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3057 +#else
3058 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3059 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3060 +#endif
3061 +
3062 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3063 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3064 +
3065 +#define IDT_CLOCK_MULT 2
3066 +
3067 +/* NVRAM */
3068 +#define NVRAM_BASE 0x12000000
3069 +#define NVRAM_ENVSIZE_OFF 4
3070 +#define NVRAM_ENVSTART_OFF 0x40
3071 +
3072 +/* LCD 4-digit display */
3073 +#define LCD_CLEAR 0x14000400
3074 +#define LCD_DIGIT0 0x1400000f
3075 +#define LCD_DIGIT1 0x14000008
3076 +#define LCD_DIGIT2 0x14000007
3077 +#define LCD_DIGIT3 0x14000003
3078 +
3079 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3080 +#define RC32334_SCC8530_IRQ 2
3081 +#define RC32334_PCI_INTA_IRQ 3
3082 +#define RC32334_PCI_INTB_IRQ 4
3083 +#define RC32334_PCI_INTC_IRQ 6
3084 +#define RC32334_PCI_INTD_IRQ 7
3085 +
3086 +#define RAM_SIZE (32*1024*1024)
3087 +
3088 +#endif // __IDT_RC32334_H__
3089 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3090 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3091 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-03-20 14:25:10.000000000 +0100
3092 @@ -0,0 +1,206 @@
3093 +/**************************************************************************
3094 + *
3095 + * BRIEF MODULE DESCRIPTION
3096 + * DMA controller defines on IDT RC32355
3097 + *
3098 + * Copyright 2004 IDT Inc.
3099 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3100 + *
3101 + *
3102 + * This program is free software; you can redistribute it and/or modify it
3103 + * under the terms of the GNU General Public License as published by the
3104 + * Free Software Foundation; either version 2 of the License, or (at your
3105 + * option) any later version.
3106 + *
3107 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3108 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3109 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3110 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3111 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3112 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3113 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3114 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3115 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3116 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3117 + *
3118 + * You should have received a copy of the GNU General Public License along
3119 + * with this program; if not, write to the Free Software Foundation, Inc.,
3120 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3121 + *
3122 + *
3123 + * May 2004 rkt
3124 + * Initial Release
3125 + *
3126 + **************************************************************************
3127 + */
3128 +
3129 +#ifndef BANYAN_DMA_H
3130 +#define BANYAN_DMA_H
3131 +#include <asm/idt-boards/rc32300/rc32300.h>
3132 +
3133 +/*
3134 + * An image of one RC32355 dma channel registers
3135 + */
3136 +typedef struct {
3137 + u32 dmac;
3138 + u32 dmas;
3139 + u32 dmasm;
3140 + u32 dmadptr;
3141 + u32 dmandptr;
3142 +} rc32355_dma_ch_t;
3143 +
3144 +/*
3145 + * An image of all RC32355 dma channel registers
3146 + */
3147 +typedef struct {
3148 + rc32355_dma_ch_t ch[16];
3149 +} rc32355_dma_regs_t;
3150 +
3151 +
3152 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3153 +
3154 +
3155 +/* DMAC register layout */
3156 +
3157 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3158 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3159 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3160 +
3161 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3162 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3163 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3164 +
3165 +/* DMAS and DMASM register layout */
3166 +
3167 +#define DMAS_F 0x01 /* Finished */
3168 +#define DMAS_D 0x02 /* Done */
3169 +#define DMAS_C 0x04 /* Chain */
3170 +#define DMAS_E 0x08 /* Error */
3171 +#define DMAS_H 0x10 /* Halt */
3172 +
3173 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3174 +#define DMA_HALT_TIMEOUT 500
3175 +
3176 +
3177 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3178 +{
3179 + int timeout=1;
3180 +
3181 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3182 + local_writel(0, &ch->dmac);
3183 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3184 + if (local_readl(&ch->dmas) & DMAS_H) {
3185 + local_writel(0, &ch->dmas);
3186 + break;
3187 + }
3188 + }
3189 + }
3190 +
3191 + return timeout ? 0 : 1;
3192 +}
3193 +
3194 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3195 +{
3196 + local_writel(0, &ch->dmandptr);
3197 + local_writel(dma_addr, &ch->dmadptr);
3198 +}
3199 +
3200 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3201 +{
3202 + local_writel(dma_addr, &ch->dmandptr);
3203 +}
3204 +
3205 +
3206 +/* The following can be used to describe DMA channels 0 to 15, and the */
3207 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3208 +
3209 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3210 +
3211 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3212 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3213 +
3214 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3215 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3216 +
3217 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3218 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3219 +
3220 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3221 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3222 +
3223 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3224 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3225 +#define DMA_DEV_ATMVCC(entry) 0
3226 +
3227 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3228 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3229 +
3230 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3231 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3232 +
3233 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3234 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3235 +
3236 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3237 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3238 +
3239 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3240 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3241 +
3242 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3243 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3244 +
3245 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3246 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3247 +
3248 +#define DMA_CHAN_USBIN 13 /* USB input */
3249 +#define DMA_DEV_USBIN 0 /* USB input */
3250 +
3251 +#define DMA_CHAN_USBOUT 14 /* USB output */
3252 +#define DMA_DEV_USBOUT 0 /* USB output */
3253 +
3254 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3255 +#define DMA_DEV_EXTERN 0 /* External DMA */
3256 +
3257 +/*
3258 + * An RC32355 dma descriptor in system memory
3259 + */
3260 +typedef struct {
3261 + u32 cmdstat; /* control and status */
3262 + u32 curr_addr; /* current address of data */
3263 + u32 devcs; /* peripheral-specific control and status */
3264 + u32 link; /* link to next descriptor */
3265 +} rc32355_dma_desc_t;
3266 +
3267 +/* Values for the descriptor cmdstat word */
3268 +
3269 +#define DMADESC_F 0x80000000u /* Finished bit */
3270 +#define DMADESC_D 0x40000000u /* Done bit */
3271 +#define DMADESC_T 0x20000000u /* Terminated bit */
3272 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3273 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3274 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3275 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3276 +
3277 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3278 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3279 +
3280 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3281 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3282 +
3283 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3284 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3285 +
3286 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3287 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3288 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3289 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3290 +
3291 +#define DMA_DEVCMD(devcmd) \
3292 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3293 +#define DMA_DS(ds) \
3294 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3295 +#define DMA_COUNT(count) \
3296 + ((count) & DMADESC_COUNT_MASK)
3297 +
3298 +#endif /* RC32355_DMA_H */
3299 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3300 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3301 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-03-20 14:25:10.000000000 +0100
3302 @@ -0,0 +1,442 @@
3303 +/**************************************************************************
3304 + *
3305 + * BRIEF MODULE DESCRIPTION
3306 + * Ethernet registers on IDT RC32355
3307 + *
3308 + * Copyright 2004 IDT Inc.
3309 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3310 + *
3311 + *
3312 + * This program is free software; you can redistribute it and/or modify it
3313 + * under the terms of the GNU General Public License as published by the
3314 + * Free Software Foundation; either version 2 of the License, or (at your
3315 + * option) any later version.
3316 + *
3317 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3318 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3319 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3320 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3321 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3322 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3323 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3324 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3325 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3326 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3327 + *
3328 + * You should have received a copy of the GNU General Public License along
3329 + * with this program; if not, write to the Free Software Foundation, Inc.,
3330 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3331 + *
3332 + *
3333 + * May 2004 rkt
3334 + * Initial Release
3335 + *
3336 + **************************************************************************
3337 + */
3338 +
3339 +
3340 +#ifndef RC32355_ETHER_H
3341 +#define RC32355_ETHER_H
3342 +
3343 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3344 +
3345 +/*
3346 + * A partial image of the RC32355 ethernet registers
3347 + */
3348 +typedef struct {
3349 + u32 ethintfc;
3350 + u32 ethfifott;
3351 + u32 etharc;
3352 + u32 ethhash0;
3353 + u32 ethhash1;
3354 + u32 ethfifost;
3355 + u32 ethfifos;
3356 + u32 ethodeops;
3357 + u32 ethis;
3358 + u32 ethos;
3359 + u32 ethmcp;
3360 + u32 _u1;
3361 + u32 ethid;
3362 + u32 _u2;
3363 + u32 _u3;
3364 + u32 _u4;
3365 + u32 ethod;
3366 + u32 _u5;
3367 + u32 _u6;
3368 + u32 _u7;
3369 + u32 ethodeop;
3370 + u32 _u8[43];
3371 + u32 ethsal0;
3372 + u32 ethsah0;
3373 + u32 ethsal1;
3374 + u32 ethsah1;
3375 + u32 ethsal2;
3376 + u32 ethsah2;
3377 + u32 ethsal3;
3378 + u32 ethsah3;
3379 + u32 ethrbc;
3380 + u32 ethrpc;
3381 + u32 ethrupc;
3382 + u32 ethrfc;
3383 + u32 ethtbc;
3384 + u32 ethgpf;
3385 + u32 _u9[50];
3386 + u32 ethmac1;
3387 + u32 ethmac2;
3388 + u32 ethipgt;
3389 + u32 ethipgr;
3390 + u32 ethclrt;
3391 + u32 ethmaxf;
3392 + u32 _u10;
3393 + u32 ethmtest;
3394 + u32 miimcfg;
3395 + u32 miimcmd;
3396 + u32 miimaddr;
3397 + u32 miimwtd;
3398 + u32 miimrdd;
3399 + u32 miimind;
3400 + u32 _u11;
3401 + u32 _u12;
3402 + u32 ethcfsa0;
3403 + u32 ethcfsa1;
3404 + u32 ethcfsa2;
3405 +} rc32355_eth_regs_t;
3406 +
3407 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3408 +
3409 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3410 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3411 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3412 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3413 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3414 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3415 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3416 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3417 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3418 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3419 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3420 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3421 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3422 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3423 +
3424 +/* for n in { 0, 1, 2, 3 } */
3425 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3426 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3427 +
3428 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3429 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3430 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3431 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3432 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3433 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3434 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3435 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3436 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3437 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3438 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3439 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3440 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3441 +
3442 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3443 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3444 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3445 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3446 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3447 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3448 +
3449 +/* for n in { 0, 1, 2 } */
3450 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3451 +
3452 +
3453 +/*
3454 + * Register Interpretations follow
3455 + */
3456 +
3457 +/******************************************************************************
3458 + * ETHINTFC register
3459 + *****************************************************************************/
3460 +
3461 +#define ETHERINTFC_EN (1<<0)
3462 +#define ETHERINTFC_ITS (1<<1)
3463 +#define ETHERINTFC_RES (1<<2)
3464 +#define ETHERINTFC_RIP (1<<2)
3465 +#define ETHERINTFC_JAM (1<<3)
3466 +
3467 +/******************************************************************************
3468 + * ETHFIFOTT register
3469 + *****************************************************************************/
3470 +
3471 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3472 +
3473 +/******************************************************************************
3474 + * ETHARC register
3475 + *****************************************************************************/
3476 +
3477 +#define ETHERARC_PRO (1<<0)
3478 +#define ETHERARC_AM (1<<1)
3479 +#define ETHERARC_AFM (1<<2)
3480 +#define ETHERARC_AB (1<<3)
3481 +
3482 +/******************************************************************************
3483 + * ETHHASH registers
3484 + *****************************************************************************/
3485 +
3486 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3487 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3488 +
3489 +/******************************************************************************
3490 + * ETHSA registers
3491 + *****************************************************************************/
3492 +
3493 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3494 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3495 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3496 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3497 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3498 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3499 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3500 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3501 +
3502 +/******************************************************************************
3503 + * ETHFIFOST register
3504 + *****************************************************************************/
3505 +
3506 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3507 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3508 +
3509 +/******************************************************************************
3510 + * ETHFIFOS register
3511 + *****************************************************************************/
3512 +
3513 +#define ETHERFIFOS_IR (1<<0)
3514 +#define ETHERFIFOS_OR (1<<1)
3515 +#define ETHERFIFOS_OVR (1<<2)
3516 +#define ETHERFIFOS_UND (1<<3)