split patch; start irq cleanup
[openwrt/svn-archive/archive.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.15/arch/mips/aruba/Makefile linux-2.6.15-openwrt/arch/mips/aruba/Makefile
2 --- linux-2.6.15/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.15-openwrt/arch/mips/aruba/Makefile 2006-01-10 00:32:32.000000000 +0100
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o wdt_merlot.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/Makefile linux-2.6.15-openwrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.15/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/Makefile 2006-01-10 00:32:32.000000000 +0100
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/nvram434.c linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.15/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.c 2006-01-10 00:32:32.000000000 +0100
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/nvram434.h linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.15/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.h 2006-01-10 00:32:32.000000000 +0100
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.15/arch/mips/aruba/prom.c linux-2.6.15-openwrt/arch/mips/aruba/prom.c
571 --- linux-2.6.15/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.15-openwrt/arch/mips/aruba/prom.c 2006-01-10 00:32:32.000000000 +0100
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.15/arch/mips/aruba/serial.c linux-2.6.15-openwrt/arch/mips/aruba/serial.c
686 --- linux-2.6.15/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.15-openwrt/arch/mips/aruba/serial.c 2006-01-10 00:32:32.000000000 +0100
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.15/arch/mips/aruba/setup.c linux-2.6.15-openwrt/arch/mips/aruba/setup.c
784 --- linux-2.6.15/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.15-openwrt/arch/mips/aruba/setup.c 2006-01-10 00:32:32.000000000 +0100
786 @@ -0,0 +1,124 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/mm.h>
827 +#include <linux/sched.h>
828 +#include <linux/irq.h>
829 +#include <asm/bootinfo.h>
830 +#include <asm/io.h>
831 +#include <linux/ioport.h>
832 +#include <asm/mipsregs.h>
833 +#include <asm/pgtable.h>
834 +#include <asm/reboot.h>
835 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
836 +#include <asm/idt-boards/rc32434/rc32434.h>
837 +
838 +extern char *__init prom_getcmdline(void);
839 +
840 +extern void (*board_time_init) (void);
841 +extern void (*board_timer_setup) (struct irqaction * irq);
842 +extern void aruba_time_init(void);
843 +extern void aruba_timer_setup(struct irqaction *irq);
844 +extern void aruba_reset(void);
845 +
846 +#define epldMask ((volatile unsigned char *)0xB900000d)
847 +
848 +static void aruba_machine_restart(char *command)
849 +{
850 + switch (mips_machtype) {
851 + case MACH_ARUBA_AP70:
852 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
853 + break;
854 + case MACH_ARUBA_AP65:
855 + case MACH_ARUBA_AP60:
856 + default:
857 + /* Reset*/
858 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
859 + udelay(100);
860 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
861 + udelay(100);
862 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
863 + break;
864 + }
865 +}
866 +
867 +static void aruba_machine_halt(void)
868 +{
869 + for (;;) continue;
870 +}
871 +
872 +extern char * getenv(char *e);
873 +extern void unlock_ap60_70_flash(void);
874 +extern void wdt_merlot_disable(void);
875 +
876 +void __init plat_setup(void)
877 +{
878 + board_time_init = aruba_time_init;
879 +
880 + board_timer_setup = aruba_timer_setup;
881 +
882 + _machine_restart = aruba_machine_restart;
883 + _machine_halt = aruba_machine_halt;
884 + _machine_power_off = aruba_machine_halt;
885 +
886 + set_io_port_base(KSEG1);
887 +
888 + /* Enable PCI interrupts in EPLD Mask register */
889 + *epldMask = 0x0;
890 + *(epldMask + 1) = 0x0;
891 +
892 + write_c0_wired(0);
893 + unlock_ap60_70_flash();
894 +
895 + printk("BOARD - %s\n",getenv("boardname"));
896 +
897 + wdt_merlot_disable();
898 +
899 + return 0;
900 +}
901 +
902 +int page_is_ram(unsigned long pagenr)
903 +{
904 + return 1;
905 +}
906 +
907 +const char *get_system_type(void)
908 +{
909 + return "MIPS IDT32434 - ARUBA";
910 +}
911 diff -Nur linux-2.6.15/arch/mips/aruba/time.c linux-2.6.15-openwrt/arch/mips/aruba/time.c
912 --- linux-2.6.15/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
913 +++ linux-2.6.15-openwrt/arch/mips/aruba/time.c 2006-01-10 00:32:32.000000000 +0100
914 @@ -0,0 +1,108 @@
915 +/**************************************************************************
916 + *
917 + * BRIEF MODULE DESCRIPTION
918 + * timer routines for IDT EB434 boards
919 + *
920 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
921 + *
922 + * This program is free software; you can redistribute it and/or modify it
923 + * under the terms of the GNU General Public License as published by the
924 + * Free Software Foundation; either version 2 of the License, or (at your
925 + * option) any later version.
926 + *
927 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
928 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
929 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
930 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
931 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
932 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
933 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
934 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
935 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
936 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
937 + *
938 + * You should have received a copy of the GNU General Public License along
939 + * with this program; if not, write to the Free Software Foundation, Inc.,
940 + * 675 Mass Ave, Cambridge, MA 02139, USA.
941 + *
942 + *
943 + **************************************************************************
944 + * May 2004 rkt, neb
945 + *
946 + * Initial Release
947 + *
948 + *
949 + *
950 + **************************************************************************
951 + */
952 +
953 +#include <linux/config.h>
954 +#include <linux/init.h>
955 +#include <linux/kernel_stat.h>
956 +#include <linux/sched.h>
957 +#include <linux/spinlock.h>
958 +#include <linux/mc146818rtc.h>
959 +#include <linux/irq.h>
960 +#include <linux/timex.h>
961 +
962 +#include <linux/param.h>
963 +#include <asm/mipsregs.h>
964 +#include <asm/ptrace.h>
965 +#include <asm/time.h>
966 +#include <asm/hardirq.h>
967 +
968 +#include <asm/mipsregs.h>
969 +#include <asm/ptrace.h>
970 +#include <asm/debug.h>
971 +#include <asm/time.h>
972 +
973 +#include <asm/idt-boards/rc32434/rc32434.h>
974 +
975 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
976 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
977 +
978 +extern unsigned int idt_cpu_freq;
979 +
980 +static unsigned long __init cal_r4koff(void)
981 +{
982 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
983 + return (mips_hpt_frequency / HZ);
984 +}
985 +
986 +void __init aruba_time_init(void)
987 +{
988 + unsigned int est_freq, flags;
989 + local_irq_save(flags);
990 +
991 + printk("calculating r4koff... ");
992 + r4k_offset = cal_r4koff();
993 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
994 +
995 + est_freq = 2 * r4k_offset * HZ;
996 + est_freq += 5000; /* round */
997 + est_freq -= est_freq % 10000;
998 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
999 + (est_freq % 1000000) * 100 / 1000000);
1000 + local_irq_restore(flags);
1001 +
1002 +}
1003 +
1004 +void __init aruba_timer_setup(struct irqaction *irq)
1005 +{
1006 + /* we are using the cpu counter for timer interrupts */
1007 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1008 +
1009 + /* to generate the first timer interrupt */
1010 + r4k_cur = (read_c0_count() + r4k_offset);
1011 + write_c0_compare(r4k_cur);
1012 +
1013 +}
1014 +
1015 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1016 +{
1017 + irq_enter();
1018 + kstat_this_cpu.irqs[irq]++;
1019 +
1020 + timer_interrupt(irq, NULL, regs);
1021 + irq_exit();
1022 +}
1023 diff -Nur linux-2.6.15/arch/mips/aruba/wdt_merlot.c linux-2.6.15-openwrt/arch/mips/aruba/wdt_merlot.c
1024 --- linux-2.6.15/arch/mips/aruba/wdt_merlot.c 1970-01-01 01:00:00.000000000 +0100
1025 +++ linux-2.6.15-openwrt/arch/mips/aruba/wdt_merlot.c 2006-01-10 00:32:32.000000000 +0100
1026 @@ -0,0 +1,30 @@
1027 +#include <linux/config.h>
1028 +#include <linux/kernel.h>
1029 +#include <asm/bootinfo.h>
1030 +
1031 +void wdt_merlot_disable()
1032 +{
1033 + volatile __u32 *wdt_errcs;
1034 + volatile __u32 *wdt_wtc;
1035 + volatile __u32 *wdt_ctl;
1036 + volatile __u32 val;
1037 +
1038 + switch (mips_machtype) {
1039 + case MACH_ARUBA_AP70:
1040 + wdt_errcs = (__u32 *) 0xb8030030;
1041 + wdt_wtc = (__u32 *) 0xb803003c;
1042 + val = *wdt_errcs;
1043 + val &= ~0x201;
1044 + *wdt_errcs = val;
1045 + val = *wdt_wtc;
1046 + val &= ~0x1;
1047 + *wdt_wtc = val;
1048 + break;
1049 + case MACH_ARUBA_AP65:
1050 + case MACH_ARUBA_AP60:
1051 + default:
1052 + wdt_ctl = (__u32 *) 0xbc003008;
1053 + *wdt_ctl = 0;
1054 + break;
1055 + }
1056 +}
1057 diff -Nur linux-2.6.15/arch/mips/Kconfig linux-2.6.15-openwrt/arch/mips/Kconfig
1058 --- linux-2.6.15/arch/mips/Kconfig 2006-01-03 04:21:10.000000000 +0100
1059 +++ linux-2.6.15-openwrt/arch/mips/Kconfig 2006-01-10 00:32:32.000000000 +0100
1060 @@ -227,6 +227,18 @@
1061 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1062 a kernel for this platform.
1063
1064 +config MACH_ARUBA
1065 + bool "Support for the ARUBA product line"
1066 + select DMA_NONCOHERENT
1067 + select IRQ_CPU
1068 + select CPU_HAS_PREFETCH
1069 + select HW_HAS_PCI
1070 + select SWAP_IO_SPACE
1071 + select SYS_SUPPORTS_32BIT_KERNEL
1072 + select SYS_HAS_CPU_MIPS32_R1
1073 + select SYS_SUPPORTS_BIG_ENDIAN
1074 +
1075 +
1076 config MACH_JAZZ
1077 bool "Support for the Jazz family of machines"
1078 select ARC
1079 diff -Nur linux-2.6.15/arch/mips/Makefile linux-2.6.15-openwrt/arch/mips/Makefile
1080 --- linux-2.6.15/arch/mips/Makefile 2006-01-03 04:21:10.000000000 +0100
1081 +++ linux-2.6.15-openwrt/arch/mips/Makefile 2006-01-10 00:32:32.000000000 +0100
1082 @@ -258,6 +258,14 @@
1083 #
1084
1085 #
1086 +# Aruba
1087 +#
1088 +
1089 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1090 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1091 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1092 +
1093 +#
1094 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1095 #
1096 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1097 diff -Nur linux-2.6.15/arch/mips/mm/tlbex.c linux-2.6.15-openwrt/arch/mips/mm/tlbex.c
1098 --- linux-2.6.15/arch/mips/mm/tlbex.c 2006-01-03 04:21:10.000000000 +0100
1099 +++ linux-2.6.15-openwrt/arch/mips/mm/tlbex.c 2006-01-10 00:32:32.000000000 +0100
1100 @@ -852,7 +852,6 @@
1101
1102 case CPU_R10000:
1103 case CPU_R12000:
1104 - case CPU_4KC:
1105 case CPU_SB1:
1106 case CPU_SB1A:
1107 case CPU_4KSC:
1108 @@ -880,6 +879,7 @@
1109 tlbw(p);
1110 break;
1111
1112 + case CPU_4KC:
1113 case CPU_4KEC:
1114 case CPU_24K:
1115 case CPU_34K:
1116 diff -Nur linux-2.6.15/drivers/net/Kconfig linux-2.6.15-openwrt/drivers/net/Kconfig
1117 --- linux-2.6.15/drivers/net/Kconfig 2006-01-03 04:21:10.000000000 +0100
1118 +++ linux-2.6.15-openwrt/drivers/net/Kconfig 2006-01-10 00:32:32.000000000 +0100
1119 @@ -176,6 +176,13 @@
1120
1121 source "drivers/net/arm/Kconfig"
1122
1123 +config IDT_RC32434_ETH
1124 + tristate "IDT RC32434 Local Ethernet support"
1125 + depends on NET_ETHERNET
1126 + help
1127 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1128 + To compile this driver as a module, choose M here.
1129 +
1130 config MACE
1131 tristate "MACE (Power Mac ethernet) support"
1132 depends on NET_ETHERNET && PPC_PMAC && PPC32
1133 diff -Nur linux-2.6.15/drivers/net/Makefile linux-2.6.15-openwrt/drivers/net/Makefile
1134 --- linux-2.6.15/drivers/net/Makefile 2006-01-03 04:21:10.000000000 +0100
1135 +++ linux-2.6.15-openwrt/drivers/net/Makefile 2006-01-10 00:32:33.000000000 +0100
1136 @@ -190,6 +190,7 @@
1137 obj-$(CONFIG_SMC91X) += smc91x.o
1138 obj-$(CONFIG_DM9000) += dm9000.o
1139 obj-$(CONFIG_FEC_8XX) += fec_8xx/
1140 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1141
1142 obj-$(CONFIG_ARM) += arm/
1143 obj-$(CONFIG_DEV_APPLETALK) += appletalk/
1144 diff -Nur linux-2.6.15/drivers/net/rc32434_eth.c linux-2.6.15-openwrt/drivers/net/rc32434_eth.c
1145 --- linux-2.6.15/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1146 +++ linux-2.6.15-openwrt/drivers/net/rc32434_eth.c 2006-01-10 00:32:33.000000000 +0100
1147 @@ -0,0 +1,1268 @@
1148 +/**************************************************************************
1149 + *
1150 + * BRIEF MODULE DESCRIPTION
1151 + * Driver for the IDT RC32434 on-chip ethernet controller.
1152 + *
1153 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1154 + *
1155 + * This program is free software; you can redistribute it and/or modify it
1156 + * under the terms of the GNU General Public License as published by the
1157 + * Free Software Foundation; either version 2 of the License, or (at your
1158 + * option) any later version.
1159 + *
1160 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1161 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1162 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1163 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1164 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1165 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1166 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1167 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1168 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1169 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1170 + *
1171 + * You should have received a copy of the GNU General Public License along
1172 + * with this program; if not, write to the Free Software Foundation, Inc.,
1173 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1174 + *
1175 + *
1176 + **************************************************************************
1177 + * May 2004 rkt, neb
1178 + *
1179 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1180 + *
1181 + * Aug 2004 Sadik
1182 + *
1183 + * Added NAPI
1184 + *
1185 + **************************************************************************
1186 + */
1187 +
1188 +#include <linux/config.h>
1189 +#include <linux/module.h>
1190 +#include <linux/kernel.h>
1191 +#include <linux/moduleparam.h>
1192 +#include <linux/sched.h>
1193 +#include <linux/ctype.h>
1194 +#include <linux/types.h>
1195 +#include <linux/fcntl.h>
1196 +#include <linux/interrupt.h>
1197 +#include <linux/ptrace.h>
1198 +#include <linux/init.h>
1199 +#include <linux/ioport.h>
1200 +#include <linux/proc_fs.h>
1201 +#include <linux/in.h>
1202 +#include <linux/slab.h>
1203 +#include <linux/string.h>
1204 +#include <linux/delay.h>
1205 +#include <linux/netdevice.h>
1206 +#include <linux/etherdevice.h>
1207 +#include <linux/skbuff.h>
1208 +#include <linux/errno.h>
1209 +#include <asm/bootinfo.h>
1210 +#include <asm/system.h>
1211 +#include <asm/bitops.h>
1212 +#include <asm/pgtable.h>
1213 +#include <asm/segment.h>
1214 +#include <asm/io.h>
1215 +#include <asm/dma.h>
1216 +
1217 +#include "rc32434_eth.h"
1218 +
1219 +#define DRIVER_VERSION "(mar2904)"
1220 +
1221 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1222 +
1223 +
1224 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1225 + ((dev)->dev_addr[1]))
1226 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1227 + ((dev)->dev_addr[3] << 16) | \
1228 + ((dev)->dev_addr[4] << 8) | \
1229 + ((dev)->dev_addr[5]))
1230 +
1231 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1232 +static char mac0[18] = "08:00:06:05:40:01";
1233 +
1234 +MODULE_PARM(mac0, "c18");
1235 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1236 +
1237 +static struct rc32434_if_t {
1238 + char *name;
1239 + struct net_device *dev;
1240 + char* mac_str;
1241 + int weight;
1242 + u32 iobase;
1243 + u32 rxdmabase;
1244 + u32 txdmabase;
1245 + int rx_dma_irq;
1246 + int tx_dma_irq;
1247 + int rx_ovr_irq;
1248 + int tx_und_irq;
1249 +} rc32434_iflist[] =
1250 +{
1251 + {
1252 + "rc32434_eth0", NULL, mac0,
1253 + 64,
1254 + ETH0_PhysicalAddress,
1255 + ETH0_RX_DMA_ADDR,
1256 + ETH0_TX_DMA_ADDR,
1257 + ETH0_DMA_RX_IRQ,
1258 + ETH0_DMA_TX_IRQ,
1259 + ETH0_RX_OVR_IRQ,
1260 + ETH0_TX_UND_IRQ
1261 + }
1262 +};
1263 +
1264 +
1265 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1266 +{
1267 + int i, j;
1268 + unsigned char result, value;
1269 +
1270 + for (i=0; i<6; i++) {
1271 + result = 0;
1272 + if (i != 5 && *(macstr+2) != ':') {
1273 + ERR("invalid mac address format: %d %c\n",
1274 + i, *(macstr+2));
1275 + return -EINVAL;
1276 + }
1277 + for (j=0; j<2; j++) {
1278 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1279 + toupper(*macstr)-'A'+10) < 16) {
1280 + result = result*16 + value;
1281 + macstr++;
1282 + }
1283 + else {
1284 + ERR("invalid mac address "
1285 + "character: %c\n", *macstr);
1286 + return -EINVAL;
1287 + }
1288 + }
1289 +
1290 + macstr++;
1291 + dev->dev_addr[i] = result;
1292 + }
1293 +
1294 + return 0;
1295 +}
1296 +
1297 +
1298 +
1299 +static inline void rc32434_abort_tx(struct net_device *dev)
1300 +{
1301 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1302 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1303 +
1304 +}
1305 +
1306 +static inline void rc32434_abort_rx(struct net_device *dev)
1307 +{
1308 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1309 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1310 +
1311 +}
1312 +
1313 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1314 +{
1315 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1316 +}
1317 +
1318 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1319 +{
1320 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1321 +}
1322 +
1323 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1324 +{
1325 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1326 +}
1327 +
1328 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1329 +{
1330 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1331 +}
1332 +
1333 +#ifdef RC32434_PROC_DEBUG
1334 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1335 + int length, int *eof, void *data)
1336 +{
1337 + struct net_device *dev = (struct net_device *)data;
1338 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1339 + int len = 0;
1340 +
1341 + /* print out header */
1342 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1343 + len += sprintf (buf + len,
1344 + "DMA halt count = %10d, DMA run count = %10d\n",
1345 + lp->dma_halt_cnt, lp->dma_run_cnt);
1346 +
1347 + if (fpos >= len) {
1348 + *start = buf;
1349 + *eof = 1;
1350 + return 0;
1351 + }
1352 + *start = buf + fpos;
1353 +
1354 + if ((len -= fpos) > length)
1355 + return length;
1356 + *eof = 1;
1357 +
1358 + return len;
1359 +
1360 +}
1361 +#endif
1362 +
1363 +
1364 +/*
1365 + * Restart the RC32434 ethernet controller.
1366 + */
1367 +static int rc32434_restart(struct net_device *dev)
1368 +{
1369 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1370 +
1371 + /*
1372 + * Disable interrupts
1373 + */
1374 + disable_irq(lp->rx_irq);
1375 + disable_irq(lp->tx_irq);
1376 +#ifdef RC32434_REVISION
1377 + disable_irq(lp->ovr_irq);
1378 +#endif
1379 + disable_irq(lp->und_irq);
1380 +
1381 + /* Mask F E bit in Tx DMA */
1382 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1383 + /* Mask D H E bit in Rx DMA */
1384 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1385 +
1386 + rc32434_init(dev);
1387 + rc32434_multicast_list(dev);
1388 +
1389 + enable_irq(lp->und_irq);
1390 +#ifdef RC32434_REVISION
1391 + enable_irq(lp->ovr_irq);
1392 +#endif
1393 + enable_irq(lp->tx_irq);
1394 + enable_irq(lp->rx_irq);
1395 +
1396 + return 0;
1397 +}
1398 +
1399 +int rc32434_init_module(void)
1400 +{
1401 +#ifdef CONFIG_MACH_ARUBA
1402 + if (mips_machtype != MACH_ARUBA_AP70)
1403 + return 1;
1404 +#endif
1405 +
1406 + printk(KERN_INFO DRIVER_NAME " \n");
1407 + return rc32434_probe(0);
1408 +}
1409 +
1410 +static int rc32434_probe(int port_num)
1411 +{
1412 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1413 + struct rc32434_local *lp = NULL;
1414 + struct net_device *dev = NULL;
1415 + int i, retval,err;
1416 +
1417 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1418 + if(!dev) {
1419 + ERR("rc32434_eth: alloc_etherdev failed\n");
1420 + return -1;
1421 + }
1422 +
1423 + SET_MODULE_OWNER(dev);
1424 + bif->dev = dev;
1425 +
1426 +#ifdef CONFIG_MACH_ARUBA
1427 + {
1428 + extern char * getenv(char *e);
1429 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1430 + }
1431 +#endif
1432 +
1433 + printk("mac: %s\n", bif->mac_str);
1434 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1435 + ERR("MAC address parse failed\n");
1436 + free_netdev(dev);
1437 + return -1;
1438 + }
1439 +
1440 +
1441 + /* Initialize the device structure. */
1442 + if (dev->priv == NULL) {
1443 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1444 + memset(lp, 0, sizeof(struct rc32434_local));
1445 + }
1446 + else {
1447 + lp = (struct rc32434_local *)dev->priv;
1448 + }
1449 +
1450 + lp->rx_irq = bif->rx_dma_irq;
1451 + lp->tx_irq = bif->tx_dma_irq;
1452 + lp->ovr_irq = bif->rx_ovr_irq;
1453 + lp->und_irq = bif->tx_und_irq;
1454 +
1455 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1456 +
1457 + if (!lp->eth_regs) {
1458 + ERR("Can't remap eth registers\n");
1459 + retval = -ENXIO;
1460 + goto probe_err_out;
1461 + }
1462 +
1463 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1464 +
1465 + if (!lp->rx_dma_regs) {
1466 + ERR("Can't remap Rx DMA registers\n");
1467 + retval = -ENXIO;
1468 + goto probe_err_out;
1469 + }
1470 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1471 +
1472 + if (!lp->tx_dma_regs) {
1473 + ERR("Can't remap Tx DMA registers\n");
1474 + retval = -ENXIO;
1475 + goto probe_err_out;
1476 + }
1477 +
1478 +#ifdef RC32434_PROC_DEBUG
1479 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1480 + rc32434_read_proc, dev);
1481 +#endif
1482 +
1483 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1484 + if (!lp->td_ring) {
1485 + ERR("Can't allocate descriptors\n");
1486 + retval = -ENOMEM;
1487 + goto probe_err_out;
1488 + }
1489 +
1490 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1491 +
1492 + /* now convert TD_RING pointer to KSEG1 */
1493 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1494 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1495 +
1496 +
1497 + spin_lock_init(&lp->lock);
1498 +
1499 + dev->base_addr = bif->iobase;
1500 + /* just use the rx dma irq */
1501 + dev->irq = bif->rx_dma_irq;
1502 +
1503 + dev->priv = lp;
1504 +
1505 + dev->open = rc32434_open;
1506 + dev->stop = rc32434_close;
1507 + dev->hard_start_xmit = rc32434_send_packet;
1508 + dev->get_stats = rc32434_get_stats;
1509 + dev->set_multicast_list = &rc32434_multicast_list;
1510 + dev->tx_timeout = rc32434_tx_timeout;
1511 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1512 +
1513 +#ifdef CONFIG_IDT_USE_NAPI
1514 + dev->poll = rc32434_poll;
1515 + dev->weight = bif->weight;
1516 + printk("Using NAPI with weight %d\n",dev->weight);
1517 +#else
1518 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1519 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1520 +#endif
1521 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1522 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1523 +
1524 + if ((err = register_netdev(dev))) {
1525 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1526 + free_netdev(dev);
1527 + retval = -EINVAL;
1528 + goto probe_err_out;
1529 + }
1530 +
1531 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1532 + for (i = 0; i < 6; i++) {
1533 + printk("%2.2x", dev->dev_addr[i]);
1534 + if (i<5)
1535 + printk(":");
1536 + }
1537 + printk("\n");
1538 +
1539 + return 0;
1540 +
1541 + probe_err_out:
1542 + rc32434_cleanup_module();
1543 + ERR(" failed. Returns %d\n", retval);
1544 + return retval;
1545 +
1546 +}
1547 +
1548 +
1549 +static void rc32434_cleanup_module(void)
1550 +{
1551 + int i;
1552 +
1553 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1554 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1555 + if (bif->dev != NULL) {
1556 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1557 + if (lp != NULL) {
1558 + if (lp->eth_regs)
1559 + iounmap((void*)lp->eth_regs);
1560 + if (lp->rx_dma_regs)
1561 + iounmap((void*)lp->rx_dma_regs);
1562 + if (lp->tx_dma_regs)
1563 + iounmap((void*)lp->tx_dma_regs);
1564 + if (lp->td_ring)
1565 + kfree((void*)KSEG0ADDR(lp->td_ring));
1566 +
1567 +#ifdef RC32434_PROC_DEBUG
1568 + if (lp->ps) {
1569 + remove_proc_entry(bif->name, proc_net);
1570 + }
1571 +#endif
1572 + kfree(lp);
1573 + }
1574 +
1575 + unregister_netdev(bif->dev);
1576 + free_netdev(bif->dev);
1577 + kfree(bif->dev);
1578 + }
1579 + }
1580 +}
1581 +
1582 +
1583 +
1584 +static int rc32434_open(struct net_device *dev)
1585 +{
1586 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1587 +
1588 + /* Initialize */
1589 + if (rc32434_init(dev)) {
1590 + ERR("Error: cannot open the Ethernet device\n");
1591 + return -EAGAIN;
1592 + }
1593 +
1594 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1595 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1596 + SA_SHIRQ | SA_INTERRUPT,
1597 + "rc32434 ethernet Rx", dev)) {
1598 + ERR(": unable to get Rx DMA IRQ %d\n",
1599 + lp->rx_irq);
1600 + return -EAGAIN;
1601 + }
1602 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1603 + SA_SHIRQ | SA_INTERRUPT,
1604 + "rc32434 ethernet Tx", dev)) {
1605 + ERR(": unable to get Tx DMA IRQ %d\n",
1606 + lp->tx_irq);
1607 + free_irq(lp->rx_irq, dev);
1608 + return -EAGAIN;
1609 + }
1610 +
1611 +#ifdef RC32434_REVISION
1612 + /* Install handler for overrun error. */
1613 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1614 + SA_SHIRQ | SA_INTERRUPT,
1615 + "Ethernet Overflow", dev)) {
1616 + ERR(": unable to get OVR IRQ %d\n",
1617 + lp->ovr_irq);
1618 + free_irq(lp->rx_irq, dev);
1619 + free_irq(lp->tx_irq, dev);
1620 + return -EAGAIN;
1621 + }
1622 +#endif
1623 +
1624 + /* Install handler for underflow error. */
1625 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1626 + SA_SHIRQ | SA_INTERRUPT,
1627 + "Ethernet Underflow", dev)) {
1628 + ERR(": unable to get UND IRQ %d\n",
1629 + lp->und_irq);
1630 + free_irq(lp->rx_irq, dev);
1631 + free_irq(lp->tx_irq, dev);
1632 +#ifdef RC32434_REVISION
1633 + free_irq(lp->ovr_irq, dev);
1634 +#endif
1635 + return -EAGAIN;
1636 + }
1637 +
1638 +
1639 + return 0;
1640 +}
1641 +
1642 +
1643 +
1644 +
1645 +static int rc32434_close(struct net_device *dev)
1646 +{
1647 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1648 + u32 tmp;
1649 +
1650 + /* Disable interrupts */
1651 + disable_irq(lp->rx_irq);
1652 + disable_irq(lp->tx_irq);
1653 +#ifdef RC32434_REVISION
1654 + disable_irq(lp->ovr_irq);
1655 +#endif
1656 + disable_irq(lp->und_irq);
1657 +
1658 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1659 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1660 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1661 +
1662 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1663 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1664 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1665 +
1666 + free_irq(lp->rx_irq, dev);
1667 + free_irq(lp->tx_irq, dev);
1668 +#ifdef RC32434_REVISION
1669 + free_irq(lp->ovr_irq, dev);
1670 +#endif
1671 + free_irq(lp->und_irq, dev);
1672 + return 0;
1673 +}
1674 +
1675 +
1676 +/* transmit packet */
1677 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1678 +{
1679 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1680 + unsigned long flags;
1681 + u32 length;
1682 + DMAD_t td;
1683 +
1684 +
1685 + spin_lock_irqsave(&lp->lock, flags);
1686 +
1687 + td = &lp->td_ring[lp->tx_chain_tail];
1688 +
1689 + /* stop queue when full, drop pkts if queue already full */
1690 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1691 + lp->tx_full = 1;
1692 +
1693 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1694 + netif_stop_queue(dev);
1695 + }
1696 + else {
1697 + lp->stats.tx_dropped++;
1698 + dev_kfree_skb_any(skb);
1699 + spin_unlock_irqrestore(&lp->lock, flags);
1700 + return 1;
1701 + }
1702 + }
1703 +
1704 + lp->tx_count ++;
1705 +
1706 + lp->tx_skb[lp->tx_chain_tail] = skb;
1707 +
1708 + length = skb->len;
1709 +
1710 + /* Setup the transmit descriptor. */
1711 + td->ca = CPHYSADDR(skb->data);
1712 +
1713 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1714 + if( lp->tx_chain_status == empty ) {
1715 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1716 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1717 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1718 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1719 + }
1720 + else {
1721 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1722 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1723 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1724 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1725 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1726 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1727 + lp->tx_chain_status = empty;
1728 + }
1729 + }
1730 + else {
1731 + if( lp->tx_chain_status == empty ) {
1732 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1733 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1734 + lp->tx_chain_status = filled;
1735 + }
1736 + else {
1737 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1738 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1739 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1740 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1741 + }
1742 + }
1743 +
1744 + dev->trans_start = jiffies;
1745 +
1746 + spin_unlock_irqrestore(&lp->lock, flags);
1747 +
1748 + return 0;
1749 +}
1750 +
1751 +
1752 +/* Ethernet MII-PHY Handler */
1753 +static void rc32434_mii_handler(unsigned long data)
1754 +{
1755 + struct net_device *dev = (struct net_device *)data;
1756 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1757 + unsigned long flags;
1758 + unsigned long duplex_status;
1759 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1760 +
1761 + spin_lock_irqsave(&lp->lock, flags);
1762 +
1763 + /* Two ports are using the same MII, the difference is the PHY address */
1764 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1765 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1766 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1767 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1768 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1769 +
1770 + ERR("irq:%x port_addr:%x RDD:%x\n",
1771 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1772 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1773 + if(duplex_status != lp->duplex_mode) {
1774 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1775 + lp->duplex_mode = duplex_status;
1776 + rc32434_restart(dev);
1777 + }
1778 +
1779 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1780 + add_timer(&lp->mii_phy_timer);
1781 +
1782 + spin_unlock_irqrestore(&lp->lock, flags);
1783 +
1784 +}
1785 +
1786 +#ifdef RC32434_REVISION
1787 +/* Ethernet Rx Overflow interrupt */
1788 +static irqreturn_t
1789 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1790 +{
1791 + struct net_device *dev = (struct net_device *)dev_id;
1792 + struct rc32434_local *lp;
1793 + unsigned int ovr;
1794 + irqreturn_t retval = IRQ_NONE;
1795 +
1796 + ASSERT(dev != NULL);
1797 +
1798 + lp = (struct rc32434_local *)dev->priv;
1799 + spin_lock(&lp->lock);
1800 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1801 +
1802 + if(ovr & ETHINTFC_ovr_m) {
1803 + netif_stop_queue(dev);
1804 +
1805 + /* clear OVR bit */
1806 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1807 +
1808 + /* Restart interface */
1809 + rc32434_restart(dev);
1810 + retval = IRQ_HANDLED;
1811 + }
1812 + spin_unlock(&lp->lock);
1813 +
1814 + return retval;
1815 +}
1816 +
1817 +#endif
1818 +
1819 +
1820 +/* Ethernet Tx Underflow interrupt */
1821 +static irqreturn_t
1822 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1823 +{
1824 + struct net_device *dev = (struct net_device *)dev_id;
1825 + struct rc32434_local *lp;
1826 + unsigned int und;
1827 + irqreturn_t retval = IRQ_NONE;
1828 +
1829 + ASSERT(dev != NULL);
1830 +
1831 + lp = (struct rc32434_local *)dev->priv;
1832 +
1833 + spin_lock(&lp->lock);
1834 +
1835 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1836 +
1837 + if(und & ETHINTFC_und_m) {
1838 + netif_stop_queue(dev);
1839 +
1840 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1841 +
1842 + /* Restart interface */
1843 + rc32434_restart(dev);
1844 + retval = IRQ_HANDLED;
1845 + }
1846 +
1847 + spin_unlock(&lp->lock);
1848 +
1849 + return retval;
1850 +}
1851 +
1852 +
1853 +/* Ethernet Rx DMA interrupt */
1854 +static irqreturn_t
1855 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1856 +{
1857 + struct net_device *dev = (struct net_device *)dev_id;
1858 + struct rc32434_local* lp;
1859 + volatile u32 dmas,dmasm;
1860 + irqreturn_t retval;
1861 +
1862 + ASSERT(dev != NULL);
1863 +
1864 + lp = (struct rc32434_local *)dev->priv;
1865 +
1866 + spin_lock(&lp->lock);
1867 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1868 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1869 + /* Mask D H E bit in Rx DMA */
1870 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1871 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1872 +#ifdef CONFIG_IDT_USE_NAPI
1873 + if(netif_rx_schedule_prep(dev))
1874 + __netif_rx_schedule(dev);
1875 +#else
1876 + tasklet_hi_schedule(lp->rx_tasklet);
1877 +#endif
1878 +
1879 + if (dmas & DMAS_e_m)
1880 + ERR(": DMA error\n");
1881 +
1882 + retval = IRQ_HANDLED;
1883 + }
1884 + else
1885 + retval = IRQ_NONE;
1886 +
1887 + spin_unlock(&lp->lock);
1888 + return retval;
1889 +}
1890 +
1891 +#ifdef CONFIG_IDT_USE_NAPI
1892 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1893 +#else
1894 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1895 +#endif
1896 +{
1897 + struct net_device *dev = (struct net_device *)rx_data_dev;
1898 + struct rc32434_local* lp = netdev_priv(dev);
1899 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1900 + struct sk_buff *skb, *skb_new;
1901 + u8* pkt_buf;
1902 + u32 devcs, count, pkt_len, pktuncrc_len;
1903 + volatile u32 dmas;
1904 +#ifdef CONFIG_IDT_USE_NAPI
1905 + u32 received = 0;
1906 + int rx_work_limit = min(*budget,dev->quota);
1907 +#else
1908 + unsigned long flags;
1909 + spin_lock_irqsave(&lp->lock, flags);
1910 +#endif
1911 +
1912 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1913 +#ifdef CONFIG_IDT_USE_NAPI
1914 + if(--rx_work_limit <0)
1915 + {
1916 + break;
1917 + }
1918 +#endif
1919 + /* init the var. used for the later operations within the while loop */
1920 + skb_new = NULL;
1921 + devcs = rd->devcs;
1922 + pkt_len = RCVPKT_LENGTH(devcs);
1923 + skb = lp->rx_skb[lp->rx_next_done];
1924 +
1925 + if (count < 64) {
1926 + lp->stats.rx_errors++;
1927 + lp->stats.rx_dropped++;
1928 + }
1929 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1930 + /* check that this is a whole packet */
1931 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1932 + lp->stats.rx_errors++;
1933 + lp->stats.rx_dropped++;
1934 + }
1935 + else if ( (devcs & ETHRX_rok_m) ) {
1936 +
1937 + {
1938 + /* must be the (first and) last descriptor then */
1939 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1940 +
1941 + pktuncrc_len = pkt_len - 4;
1942 + /* invalidate the cache */
1943 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
1944 +
1945 + /* Malloc up new buffer. */
1946 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
1947 +
1948 + if (skb_new != NULL){
1949 + /* Make room */
1950 + skb_put(skb, pktuncrc_len);
1951 +
1952 + skb->protocol = eth_type_trans(skb, dev);
1953 +
1954 + /* pass the packet to upper layers */
1955 +#ifdef CONFIG_IDT_USE_NAPI
1956 + netif_receive_skb(skb);
1957 +#else
1958 + netif_rx(skb);
1959 +#endif
1960 +
1961 + dev->last_rx = jiffies;
1962 + lp->stats.rx_packets++;
1963 + lp->stats.rx_bytes += pktuncrc_len;
1964 +
1965 + if (IS_RCV_MP(devcs))
1966 + lp->stats.multicast++;
1967 +
1968 + /* 16 bit align */
1969 + skb_reserve(skb_new, 2);
1970 +
1971 + skb_new->dev = dev;
1972 + lp->rx_skb[lp->rx_next_done] = skb_new;
1973 + }
1974 + else {
1975 + ERR("no memory, dropping rx packet.\n");
1976 + lp->stats.rx_errors++;
1977 + lp->stats.rx_dropped++;
1978 + }
1979 + }
1980 +
1981 + }
1982 + else {
1983 + /* This should only happen if we enable accepting broken packets */
1984 + lp->stats.rx_errors++;
1985 + lp->stats.rx_dropped++;
1986 +
1987 + /* add statistics counters */
1988 + if (IS_RCV_CRC_ERR(devcs)) {
1989 + DBG(2, "RX CRC error\n");
1990 + lp->stats.rx_crc_errors++;
1991 + }
1992 + else if (IS_RCV_LOR_ERR(devcs)) {
1993 + DBG(2, "RX LOR error\n");
1994 + lp->stats.rx_length_errors++;
1995 + }
1996 + else if (IS_RCV_LE_ERR(devcs)) {
1997 + DBG(2, "RX LE error\n");
1998 + lp->stats.rx_length_errors++;
1999 + }
2000 + else if (IS_RCV_OVR_ERR(devcs)) {
2001 + lp->stats.rx_over_errors++;
2002 + }
2003 + else if (IS_RCV_CV_ERR(devcs)) {
2004 + /* code violation */
2005 + DBG(2, "RX CV error\n");
2006 + lp->stats.rx_frame_errors++;
2007 + }
2008 + else if (IS_RCV_CES_ERR(devcs)) {
2009 + DBG(2, "RX Preamble error\n");
2010 + }
2011 + }
2012 +
2013 + rd->devcs = 0;
2014 +
2015 + /* restore descriptor's curr_addr */
2016 + if(skb_new)
2017 + rd->ca = CPHYSADDR(skb_new->data);
2018 + else
2019 + rd->ca = CPHYSADDR(skb->data);
2020 +
2021 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2022 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2023 +
2024 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2025 + rd = &lp->rd_ring[lp->rx_next_done];
2026 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2027 + }
2028 +#ifdef CONFIG_IDT_USE_NAPI
2029 + dev->quota -= received;
2030 + *budget =- received;
2031 + if(rx_work_limit < 0)
2032 + goto not_done;
2033 +#endif
2034 +
2035 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2036 +
2037 + if(dmas & DMAS_h_m) {
2038 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2039 +#ifdef RC32434_PROC_DEBUG
2040 + lp->dma_halt_cnt++;
2041 +#endif
2042 + rd->devcs = 0;
2043 + skb = lp->rx_skb[lp->rx_next_done];
2044 + rd->ca = CPHYSADDR(skb->data);
2045 + rc32434_chain_rx(lp,rd);
2046 + }
2047 +
2048 +#ifdef CONFIG_IDT_USE_NAPI
2049 + netif_rx_complete(dev);
2050 +#endif
2051 + /* Enable D H E bit in Rx DMA */
2052 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2053 +#ifdef CONFIG_IDT_USE_NAPI
2054 + return 0;
2055 + not_done:
2056 + return 1;
2057 +#else
2058 + spin_unlock_irqrestore(&lp->lock, flags);
2059 + return;
2060 +#endif
2061 +
2062 +
2063 +}
2064 +
2065 +
2066 +
2067 +/* Ethernet Tx DMA interrupt */
2068 +static irqreturn_t
2069 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2070 +{
2071 + struct net_device *dev = (struct net_device *)dev_id;
2072 + struct rc32434_local *lp;
2073 + volatile u32 dmas,dmasm;
2074 + irqreturn_t retval;
2075 +
2076 + ASSERT(dev != NULL);
2077 +
2078 + lp = (struct rc32434_local *)dev->priv;
2079 +
2080 + spin_lock(&lp->lock);
2081 +
2082 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2083 +
2084 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2085 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2086 + /* Mask F E bit in Tx DMA */
2087 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2088 +
2089 + tasklet_hi_schedule(lp->tx_tasklet);
2090 +
2091 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2092 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2093 + lp->tx_chain_status = empty;
2094 + lp->tx_chain_head = lp->tx_chain_tail;
2095 + dev->trans_start = jiffies;
2096 + }
2097 +
2098 + if (dmas & DMAS_e_m)
2099 + ERR(": DMA error\n");
2100 +
2101 + retval = IRQ_HANDLED;
2102 + }
2103 + else
2104 + retval = IRQ_NONE;
2105 +
2106 + spin_unlock(&lp->lock);
2107 +
2108 + return retval;
2109 +}
2110 +
2111 +
2112 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2113 +{
2114 + struct net_device *dev = (struct net_device *)tx_data_dev;
2115 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2116 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2117 + u32 devcs;
2118 + unsigned long flags;
2119 + volatile u32 dmas;
2120 +
2121 + spin_lock_irqsave(&lp->lock, flags);
2122 +
2123 + /* process all desc that are done */
2124 + while(IS_DMA_FINISHED(td->control)) {
2125 + if(lp->tx_full == 1) {
2126 + netif_wake_queue(dev);
2127 + lp->tx_full = 0;
2128 + }
2129 +
2130 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2131 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2132 + lp->stats.tx_errors++;
2133 + lp->stats.tx_dropped++;
2134 +
2135 + /* should never happen */
2136 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2137 + }
2138 + else if (IS_TX_TOK(devcs)) {
2139 + lp->stats.tx_packets++;
2140 + }
2141 + else {
2142 + lp->stats.tx_errors++;
2143 + lp->stats.tx_dropped++;
2144 +
2145 + /* underflow */
2146 + if (IS_TX_UND_ERR(devcs))
2147 + lp->stats.tx_fifo_errors++;
2148 +
2149 + /* oversized frame */
2150 + if (IS_TX_OF_ERR(devcs))
2151 + lp->stats.tx_aborted_errors++;
2152 +
2153 + /* excessive deferrals */
2154 + if (IS_TX_ED_ERR(devcs))
2155 + lp->stats.tx_carrier_errors++;
2156 +
2157 + /* collisions: medium busy */
2158 + if (IS_TX_EC_ERR(devcs))
2159 + lp->stats.collisions++;
2160 +
2161 + /* late collision */
2162 + if (IS_TX_LC_ERR(devcs))
2163 + lp->stats.tx_window_errors++;
2164 +
2165 + }
2166 +
2167 + /* We must always free the original skb */
2168 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2169 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2170 + lp->tx_skb[lp->tx_next_done] = NULL;
2171 + }
2172 +
2173 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2174 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2175 + lp->td_ring[lp->tx_next_done].link = 0;
2176 + lp->td_ring[lp->tx_next_done].ca = 0;
2177 + lp->tx_count --;
2178 +
2179 + /* go on to next transmission */
2180 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2181 + td = &lp->td_ring[lp->tx_next_done];
2182 +
2183 + }
2184 +
2185 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2186 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2187 +
2188 + /* Enable F E bit in Tx DMA */
2189 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2190 + spin_unlock_irqrestore(&lp->lock, flags);
2191 +
2192 +}
2193 +
2194 +
2195 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2196 +{
2197 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2198 + return &lp->stats;
2199 +}
2200 +
2201 +
2202 +/*
2203 + * Set or clear the multicast filter for this adaptor.
2204 + */
2205 +static void rc32434_multicast_list(struct net_device *dev)
2206 +{
2207 + /* listen to broadcasts always and to treat */
2208 + /* IFF bits independantly */
2209 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2210 + unsigned long flags;
2211 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2212 +
2213 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2214 + recognise |= ETHARC_pro_m;
2215 +
2216 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2217 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2218 + else if (dev->mc_count > 0) {
2219 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2220 + recognise |= ETHARC_am_m; /* for the time being */
2221 + }
2222 +
2223 + spin_lock_irqsave(&lp->lock, flags);
2224 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2225 + spin_unlock_irqrestore(&lp->lock, flags);
2226 +}
2227 +
2228 +
2229 +static void rc32434_tx_timeout(struct net_device *dev)
2230 +{
2231 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2232 + unsigned long flags;
2233 +
2234 + spin_lock_irqsave(&lp->lock, flags);
2235 + rc32434_restart(dev);
2236 + spin_unlock_irqrestore(&lp->lock, flags);
2237 +
2238 +}
2239 +
2240 +
2241 +/*
2242 + * Initialize the RC32434 ethernet controller.
2243 + */
2244 +static int rc32434_init(struct net_device *dev)
2245 +{
2246 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2247 + int i, j;
2248 +
2249 + /* Disable DMA */
2250 + rc32434_abort_tx(dev);
2251 + rc32434_abort_rx(dev);
2252 +
2253 + /* reset ethernet logic */
2254 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2255 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2256 + dev->trans_start = jiffies;
2257 +
2258 + /* Enable Ethernet Interface */
2259 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2260 +
2261 +#ifndef CONFIG_IDT_USE_NAPI
2262 + tasklet_disable(lp->rx_tasklet);
2263 +#endif
2264 + tasklet_disable(lp->tx_tasklet);
2265 +
2266 + /* Initialize the transmit Descriptors */
2267 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2268 + lp->td_ring[i].control = DMAD_iof_m;
2269 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2270 + lp->td_ring[i].ca = 0;
2271 + lp->td_ring[i].link = 0;
2272 + if (lp->tx_skb[i] != NULL) {
2273 + dev_kfree_skb_any(lp->tx_skb[i]);
2274 + lp->tx_skb[i] = NULL;
2275 + }
2276 + }
2277 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2278 + lp-> tx_chain_status = empty;
2279 +
2280 + /*
2281 + * Initialize the receive descriptors so that they
2282 + * become a circular linked list, ie. let the last
2283 + * descriptor point to the first again.
2284 + */
2285 + for (i=0; i<RC32434_NUM_RDS; i++) {
2286 + struct sk_buff *skb = lp->rx_skb[i];
2287 +
2288 + if (lp->rx_skb[i] == NULL) {
2289 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2290 + if (skb == NULL) {
2291 + ERR("No memory in the system\n");
2292 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2293 + if (lp->rx_skb[j] != NULL)
2294 + dev_kfree_skb_any(lp->rx_skb[j]);
2295 +
2296 + return 1;
2297 + }
2298 + else {
2299 + skb->dev = dev;
2300 + skb_reserve(skb, 2);
2301 + lp->rx_skb[i] = skb;
2302 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2303 +
2304 + }
2305 + }
2306 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2307 + lp->rd_ring[i].devcs = 0;
2308 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2309 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2310 +
2311 + }
2312 + /* loop back */
2313 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2314 + lp->rx_next_done = 0;
2315 +
2316 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2317 + lp->rx_chain_head = 0;
2318 + lp->rx_chain_tail = 0;
2319 + lp->rx_chain_status = empty;
2320 +
2321 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2322 + /* Start Rx DMA */
2323 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2324 +
2325 + /* Enable F E bit in Tx DMA */
2326 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2327 + /* Enable D H E bit in Rx DMA */
2328 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2329 +
2330 + /* Accept only packets destined for this Ethernet device address */
2331 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2332 +
2333 + /* Set all Ether station address registers to their initial values */
2334 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2335 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2336 +
2337 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2338 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2339 +
2340 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2341 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2342 +
2343 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2344 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2345 +
2346 +
2347 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2348 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2349 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2350 +
2351 + /* Back to back inter-packet-gap */
2352 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2353 + /* Non - Back to back inter-packet-gap */
2354 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2355 +
2356 + /* Management Clock Prescaler Divisor */
2357 + /* Clock independent setting */
2358 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2359 + &lp->eth_regs->ethmcp);
2360 +
2361 + /* don't transmit until fifo contains 48b */
2362 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2363 +
2364 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2365 +
2366 +#ifndef CONFIG_IDT_USE_NAPI
2367 + tasklet_enable(lp->rx_tasklet);
2368 +#endif
2369 + tasklet_enable(lp->tx_tasklet);
2370 +
2371 + netif_start_queue(dev);
2372 +
2373 +
2374 + return 0;
2375 +
2376 +}
2377 +
2378 +
2379 +#ifndef MODULE
2380 +
2381 +static int __init rc32434_setup(char *options)
2382 +{
2383 + /* no options yet */
2384 + return 1;
2385 +}
2386 +
2387 +static int __init rc32434_setup_ethaddr0(char *options)
2388 +{
2389 + memcpy(mac0, options, 17);
2390 + mac0[17]= '\0';
2391 + return 1;
2392 +}
2393 +
2394 +__setup("rc32434eth=", rc32434_setup);
2395 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2396 +
2397 +
2398 +#endif /* MODULE */
2399 +
2400 +module_init(rc32434_init_module);
2401 +module_exit(rc32434_cleanup_module);
2402 +
2403 +
2404 +
2405 +
2406 +
2407 +
2408 +
2409 +
2410 +
2411 +
2412 +
2413 +
2414 +
2415 +
2416 diff -Nur linux-2.6.15/drivers/net/rc32434_eth.h linux-2.6.15-openwrt/drivers/net/rc32434_eth.h
2417 --- linux-2.6.15/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2418 +++ linux-2.6.15-openwrt/drivers/net/rc32434_eth.h 2006-01-10 00:32:33.000000000 +0100
2419 @@ -0,0 +1,187 @@
2420 +/**************************************************************************
2421 + *
2422 + * BRIEF MODULE DESCRIPTION
2423 + * Definitions for IDT RC32434 on-chip ethernet controller.
2424 + *
2425 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2426 + *
2427 + * This program is free software; you can redistribute it and/or modify it
2428 + * under the terms of the GNU General Public License as published by the
2429 + * Free Software Foundation; either version 2 of the License, or (at your
2430 + * option) any later version.
2431 + *
2432 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2433 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2434 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2435 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2436 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2437 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2438 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2439 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2440 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2441 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2442 + *
2443 + * You should have received a copy of the GNU General Public License along
2444 + * with this program; if not, write to the Free Software Foundation, Inc.,
2445 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2446 + *
2447 + *
2448 + **************************************************************************
2449 + * May 2004 rkt, neb
2450 + *
2451 + * Initial Release
2452 + *
2453 + * Aug 2004
2454 + *
2455 + * Added NAPI
2456 + *
2457 + **************************************************************************
2458 + */
2459 +
2460 +
2461 +#include <asm/idt-boards/rc32434/rc32434.h>
2462 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2463 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2464 +
2465 +#define RC32434_DEBUG 2
2466 +//#define RC32434_PROC_DEBUG
2467 +#undef RC32434_DEBUG
2468 +
2469 +#ifdef RC32434_DEBUG
2470 +
2471 +/* use 0 for production, 1 for verification, >2 for debug */
2472 +static int rc32434_debug = RC32434_DEBUG;
2473 +#define ASSERT(expr) \
2474 + if(!(expr)) { \
2475 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2476 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2477 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2478 +#else
2479 +#define ASSERT(expr) do {} while (0)
2480 +#define DBG(lvl, format, arg...) do {} while (0)
2481 +#endif
2482 +
2483 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2484 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2485 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2486 +
2487 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2488 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2489 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2490 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2491 +
2492 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2493 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2494 +
2495 +/* the following must be powers of two */
2496 +#ifdef CONFIG_IDT_USE_NAPI
2497 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2498 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2499 +#else
2500 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2501 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2502 +#endif
2503 +
2504 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2505 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2506 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2507 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2508 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2509 +
2510 +#define RC32434_TX_TIMEOUT HZ * 100
2511 +
2512 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2513 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2514 +
2515 +enum status { filled, empty};
2516 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2517 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2518 +
2519 +
2520 +/* Information that need to be kept for each board. */
2521 +struct rc32434_local {
2522 + ETH_t eth_regs;
2523 + DMA_Chan_t rx_dma_regs;
2524 + DMA_Chan_t tx_dma_regs;
2525 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2526 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2527 +
2528 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2529 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2530 +
2531 +#ifndef CONFIG_IDT_USE_NAPI
2532 + struct tasklet_struct * rx_tasklet;
2533 +#endif
2534 + struct tasklet_struct * tx_tasklet;
2535 +
2536 + int rx_next_done;
2537 + int rx_chain_head;
2538 + int rx_chain_tail;
2539 + enum status rx_chain_status;
2540 +
2541 + int tx_next_done;
2542 + int tx_chain_head;
2543 + int tx_chain_tail;
2544 + enum status tx_chain_status;
2545 + int tx_count;
2546 + int tx_full;
2547 +
2548 + struct timer_list mii_phy_timer;
2549 + unsigned long duplex_mode;
2550 +
2551 + int rx_irq;
2552 + int tx_irq;
2553 + int ovr_irq;
2554 + int und_irq;
2555 +
2556 + struct net_device_stats stats;
2557 + spinlock_t lock;
2558 +
2559 + /* debug /proc entry */
2560 + struct proc_dir_entry *ps;
2561 + int dma_halt_cnt; int dma_run_cnt;
2562 +};
2563 +
2564 +extern unsigned int idt_cpu_freq;
2565 +
2566 +/* Index to functions, as function prototypes. */
2567 +static int rc32434_open(struct net_device *dev);
2568 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2569 +static void rc32434_mii_handler(unsigned long data);
2570 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2571 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2572 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2573 +#ifdef RC32434_REVISION
2574 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2575 +#endif
2576 +static int rc32434_close(struct net_device *dev);
2577 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2578 +static void rc32434_multicast_list(struct net_device *dev);
2579 +static int rc32434_init(struct net_device *dev);
2580 +static void rc32434_tx_timeout(struct net_device *dev);
2581 +
2582 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2583 +#ifdef CONFIG_IDT_USE_NAPI
2584 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2585 +#else
2586 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2587 +#endif
2588 +static void rc32434_cleanup_module(void);
2589 +static int rc32434_probe(int port_num);
2590 +int rc32434_init_module(void);
2591 +
2592 +
2593 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2594 +{
2595 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2596 + rc32434_writel(0x10, &ch->dmac);
2597 +
2598 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2599 + dev->trans_start = jiffies;
2600 +
2601 + rc32434_writel(0, &ch->dmas);
2602 + }
2603 +
2604 + rc32434_writel(0, &ch->dmadptr);
2605 + rc32434_writel(0, &ch->dmandptr);
2606 +}
2607 diff -Nur linux-2.6.15/include/asm-mips/bootinfo.h linux-2.6.15-openwrt/include/asm-mips/bootinfo.h
2608 --- linux-2.6.15/include/asm-mips/bootinfo.h 2006-01-03 04:21:10.000000000 +0100
2609 +++ linux-2.6.15-openwrt/include/asm-mips/bootinfo.h 2006-01-10 00:32:33.000000000 +0100
2610 @@ -218,6 +218,17 @@
2611 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2612 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2613
2614 +
2615 +/*
2616 + * Valid machtype for group ARUBA
2617 + */
2618 +#define MACH_GROUP_ARUBA 23
2619 +#define MACH_ARUBA_UNKNOWN 0
2620 +#define MACH_ARUBA_AP60 1
2621 +#define MACH_ARUBA_AP65 2
2622 +#define MACH_ARUBA_AP70 3
2623 +#define MACH_ARUBA_AP40 4
2624 +
2625 #define CL_SIZE COMMAND_LINE_SIZE
2626
2627 const char *get_system_type(void);
2628 diff -Nur linux-2.6.15/include/asm-mips/cpu.h linux-2.6.15-openwrt/include/asm-mips/cpu.h
2629 --- linux-2.6.15/include/asm-mips/cpu.h 2006-01-03 04:21:10.000000000 +0100
2630 +++ linux-2.6.15-openwrt/include/asm-mips/cpu.h 2006-01-10 00:32:33.000000000 +0100
2631 @@ -53,6 +53,9 @@
2632 #define PRID_IMP_R12000 0x0e00
2633 #define PRID_IMP_R8000 0x1000
2634 #define PRID_IMP_PR4450 0x1200
2635 +#define PRID_IMP_RC32334 0x1800
2636 +#define PRID_IMP_RC32355 0x1900
2637 +#define PRID_IMP_RC32365 0x1900
2638 #define PRID_IMP_R4600 0x2000
2639 #define PRID_IMP_R4700 0x2100
2640 #define PRID_IMP_TX39 0x2200
2641 @@ -196,7 +199,8 @@
2642 #define CPU_34K 60
2643 #define CPU_PR4450 61
2644 #define CPU_SB1A 62
2645 -#define CPU_LAST 62
2646 +#define CPU_RC32300 63
2647 +#define CPU_LAST 63
2648
2649 /*
2650 * ISA Level encodings
2651 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2652 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2653 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-01-10 00:32:33.000000000 +0100
2654 @@ -0,0 +1,142 @@
2655 +/**************************************************************************
2656 + *
2657 + * BRIEF MODULE DESCRIPTION
2658 + * RC32300 helper routines
2659 + *
2660 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2661 + *
2662 + * This program is free software; you can redistribute it and/or modify it
2663 + * under the terms of the GNU General Public License as published by the
2664 + * Free Software Foundation; either version 2 of the License, or (at your
2665 + * option) any later version.
2666 + *
2667 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2668 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2669 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2670 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2671 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2672 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2673 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2674 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2675 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2676 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2677 + *
2678 + * You should have received a copy of the GNU General Public License along
2679 + * with this program; if not, write to the Free Software Foundation, Inc.,
2680 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2681 + *
2682 + *
2683 + **************************************************************************
2684 + * May 2004 P. Sadik.
2685 + *
2686 + * Initial Release
2687 + *
2688 + *
2689 + *
2690 + **************************************************************************
2691 + */
2692 +
2693 +#ifndef __IDT_RC32300_H__
2694 +#define __IDT_RC32300_H__
2695 +
2696 +#include <linux/delay.h>
2697 +#include <asm/io.h>
2698 +
2699 +
2700 +/* cpu pipeline flush */
2701 +static inline void rc32300_sync(void)
2702 +{
2703 + __asm__ volatile ("sync");
2704 +}
2705 +
2706 +static inline void rc32300_sync_udelay(int us)
2707 +{
2708 + __asm__ volatile ("sync");
2709 + udelay(us);
2710 +}
2711 +
2712 +static inline void rc32300_sync_delay(int ms)
2713 +{
2714 + __asm__ volatile ("sync");
2715 + mdelay(ms);
2716 +}
2717 +
2718 +/*
2719 + * Macros to access internal RC32300 registers. No byte
2720 + * swapping should be done when accessing the internal
2721 + * registers.
2722 + */
2723 +
2724 +static inline u8 rc32300_readb(unsigned long pa)
2725 +{
2726 + return *((volatile u8 *)KSEG1ADDR(pa));
2727 +}
2728 +static inline u16 rc32300_readw(unsigned long pa)
2729 +{
2730 + return *((volatile u16 *)KSEG1ADDR(pa));
2731 +}
2732 +static inline u32 rc32300_readl(unsigned long pa)
2733 +{
2734 + return *((volatile u32 *)KSEG1ADDR(pa));
2735 +}
2736 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2737 +{
2738 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2739 +}
2740 +static inline void rc32300_writew(u16 val, unsigned long pa)
2741 +{
2742 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2743 +}
2744 +static inline void rc32300_writel(u32 val, unsigned long pa)
2745 +{
2746 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2747 +}
2748 +
2749 +
2750 +#define local_readb __raw_readb
2751 +#define local_readw __raw_readw
2752 +#define local_readl __raw_readl
2753 +
2754 +#define local_writeb __raw_writeb
2755 +#define local_writew __raw_writew
2756 +#define local_writel __raw_writel
2757 +
2758 +
2759 +/*
2760 + * C access to CLZ and CLO instructions
2761 + * (count leading zeroes/ones).
2762 + */
2763 +static inline int rc32300_clz(unsigned long val)
2764 +{
2765 + int ret;
2766 + __asm__ volatile (
2767 + ".set\tnoreorder\n\t"
2768 + ".set\tnoat\n\t"
2769 + ".set\tmips32\n\t"
2770 + "clz\t%0,%1\n\t"
2771 + ".set\tmips0\n\t"
2772 + ".set\tat\n\t"
2773 + ".set\treorder"
2774 + : "=r" (ret)
2775 + : "r" (val));
2776 +
2777 + return ret;
2778 +}
2779 +static inline int rc32300_clo(unsigned long val)
2780 +{
2781 + int ret;
2782 + __asm__ volatile (
2783 + ".set\tnoreorder\n\t"
2784 + ".set\tnoat\n\t"
2785 + ".set\tmips32\n\t"
2786 + "clo\t%0,%1\n\t"
2787 + ".set\tmips0\n\t"
2788 + ".set\tat\n\t"
2789 + ".set\treorder"
2790 + : "=r" (ret)
2791 + : "r" (val));
2792 +
2793 + return ret;
2794 +}
2795 +
2796 +#endif // __IDT_RC32300_H__
2797 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2798 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2799 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-01-10 00:32:33.000000000 +0100
2800 @@ -0,0 +1,207 @@
2801 +/**************************************************************************
2802 + *
2803 + * BRIEF MODULE DESCRIPTION
2804 + * Definitions for IDT RC32334 CPU.
2805 + *
2806 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2807 + *
2808 + * This program is free software; you can redistribute it and/or modify it
2809 + * under the terms of the GNU General Public License as published by the
2810 + * Free Software Foundation; either version 2 of the License, or (at your
2811 + * option) any later version.
2812 + *
2813 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2814 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2815 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2816 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2817 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2818 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2819 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2820 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2821 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2822 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2823 + *
2824 + * You should have received a copy of the GNU General Public License along
2825 + * with this program; if not, write to the Free Software Foundation, Inc.,
2826 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2827 + *
2828 + *
2829 + **************************************************************************
2830 + * May 2004 P. Sadik.
2831 + *
2832 + * Initial Release
2833 + *
2834 + *
2835 + *
2836 + **************************************************************************
2837 + */
2838 +
2839 +
2840 +#ifndef __IDT_RC32334_H__
2841 +#define __IDT_RC32334_H__
2842 +
2843 +#include <linux/delay.h>
2844 +#include <asm/io.h>
2845 +
2846 +/* Base address of internal registers */
2847 +#define RC32334_REG_BASE 0x18000000
2848 +
2849 +/* CPU and IP Bus Control */
2850 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2851 +#define CPU_BTA 0xffffe204 // virtual!
2852 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2853 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2854 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2855 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2856 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2857 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2858 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2859 +
2860 +/* Memory Controller */
2861 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2862 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2863 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2864 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2865 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2866 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2867 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2868 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2869 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2870 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2871 +
2872 +/* PCI Controller */
2873 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2874 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2875 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2876 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2877 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2878 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2879 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2880 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2881 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2882 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2883 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2884 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2885 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2886 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2887 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2888 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2889 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2890 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2891 +
2892 +/* Timers */
2893 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2894 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2895 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2896 +#define TIMER_REG_OFFSET 0x10
2897 +
2898 +/* Programmable I/O */
2899 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2900 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2901 +
2902 +/*
2903 + * DMA
2904 + *
2905 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2906 + *
2907 + * DMA0: 18001400
2908 + * DMA1: 18001440
2909 + * DMA2: 18001900
2910 + * DMA3: 18001940
2911 + * NB: dma number must be immediate value or variable.
2912 + * It MUST NOT be a function since it would get called twice!
2913 + */
2914 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2915 +
2916 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2917 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2918 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2919 +
2920 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2921 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2922 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2923 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2924 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2925 +
2926 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2927 +
2928 +/* Expansion Interrupt Controller */
2929 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2930 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2931 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2932 +#define IC_GROUP_OFFSET 0x10
2933 +
2934 +#define NUM_INTR_GROUPS 15
2935 +/*
2936 + * The IRQ mapping is as follows:
2937 + *
2938 + * IRQ Mapped To
2939 + * --- -------------------
2940 + * 0 SW0 (IP0) SW0 intr
2941 + * 1 SW1 (IP1) SW1 intr
2942 + * 2 Int0 (IP2) board-specific
2943 + * 3 Int1 (IP3) board-specific
2944 + * 4 Int2 (IP4) board-specific
2945 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
2946 + * 6 Int4 (IP6) board-specific
2947 + * 7 Int5 (IP7) CP0 Timer
2948 + *
2949 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
2950 + * internally on the RC32334 is routed to the Expansion
2951 + * Interrupt Controller.
2952 + */
2953 +#define MIPS_CPU_TIMER_IRQ 7
2954 +
2955 +#define GROUP1_IRQ_BASE 8 // bus error
2956 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
2957 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
2958 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
2959 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
2960 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
2961 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
2962 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
2963 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
2964 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
2965 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
2966 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
2967 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
2968 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
2969 +
2970 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
2971 +
2972 +/* 16550 UARTs */
2973 +#ifdef __MIPSEB__
2974 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
2975 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
2976 +#else
2977 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
2978 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
2979 +#endif
2980 +
2981 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
2982 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
2983 +
2984 +#define IDT_CLOCK_MULT 2
2985 +
2986 +/* NVRAM */
2987 +#define NVRAM_BASE 0x12000000
2988 +#define NVRAM_ENVSIZE_OFF 4
2989 +#define NVRAM_ENVSTART_OFF 0x40
2990 +
2991 +/* LCD 4-digit display */
2992 +#define LCD_CLEAR 0x14000400
2993 +#define LCD_DIGIT0 0x1400000f
2994 +#define LCD_DIGIT1 0x14000008
2995 +#define LCD_DIGIT2 0x14000007
2996 +#define LCD_DIGIT3 0x14000003
2997 +
2998 +/* Interrupts routed on 79S334A board (see rc32334.h) */
2999 +#define RC32334_SCC8530_IRQ 2
3000 +#define RC32334_PCI_INTA_IRQ 3
3001 +#define RC32334_PCI_INTB_IRQ 4
3002 +#define RC32334_PCI_INTC_IRQ 6
3003 +#define RC32334_PCI_INTD_IRQ 7
3004 +
3005 +#define RAM_SIZE (32*1024*1024)
3006 +
3007 +#endif // __IDT_RC32334_H__
3008 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3009 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3010 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-01-10 00:32:33.000000000 +0100
3011 @@ -0,0 +1,206 @@
3012 +/**************************************************************************
3013 + *
3014 + * BRIEF MODULE DESCRIPTION
3015 + * DMA controller defines on IDT RC32355
3016 + *
3017 + * Copyright 2004 IDT Inc.
3018 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3019 + *
3020 + *
3021 + * This program is free software; you can redistribute it and/or modify it
3022 + * under the terms of the GNU General Public License as published by the
3023 + * Free Software Foundation; either version 2 of the License, or (at your
3024 + * option) any later version.
3025 + *
3026 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3027 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3028 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3029 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3030 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3031 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3032 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3033 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3034 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3035 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3036 + *
3037 + * You should have received a copy of the GNU General Public License along
3038 + * with this program; if not, write to the Free Software Foundation, Inc.,
3039 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3040 + *
3041 + *
3042 + * May 2004 rkt
3043 + * Initial Release
3044 + *
3045 + **************************************************************************
3046 + */
3047 +
3048 +#ifndef BANYAN_DMA_H
3049 +#define BANYAN_DMA_H
3050 +#include <asm/idt-boards/rc32300/rc32300.h>
3051 +
3052 +/*
3053 + * An image of one RC32355 dma channel registers
3054 + */
3055 +typedef struct {
3056 + u32 dmac;
3057 + u32 dmas;
3058 + u32 dmasm;
3059 + u32 dmadptr;
3060 + u32 dmandptr;
3061 +} rc32355_dma_ch_t;
3062 +
3063 +/*
3064 + * An image of all RC32355 dma channel registers
3065 + */
3066 +typedef struct {
3067 + rc32355_dma_ch_t ch[16];
3068 +} rc32355_dma_regs_t;
3069 +
3070 +
3071 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3072 +
3073 +
3074 +/* DMAC register layout */
3075 +
3076 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3077 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3078 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3079 +
3080 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3081 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3082 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3083 +
3084 +/* DMAS and DMASM register layout */
3085 +
3086 +#define DMAS_F 0x01 /* Finished */
3087 +#define DMAS_D 0x02 /* Done */
3088 +#define DMAS_C 0x04 /* Chain */
3089 +#define DMAS_E 0x08 /* Error */
3090 +#define DMAS_H 0x10 /* Halt */
3091 +
3092 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3093 +#define DMA_HALT_TIMEOUT 500
3094 +
3095 +
3096 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3097 +{
3098 + int timeout=1;
3099 +
3100 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3101 + local_writel(0, &ch->dmac);
3102 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3103 + if (local_readl(&ch->dmas) & DMAS_H) {
3104 + local_writel(0, &ch->dmas);
3105 + break;
3106 + }
3107 + }
3108 + }
3109 +
3110 + return timeout ? 0 : 1;
3111 +}
3112 +
3113 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3114 +{
3115 + local_writel(0, &ch->dmandptr);
3116 + local_writel(dma_addr, &ch->dmadptr);
3117 +}
3118 +
3119 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3120 +{
3121 + local_writel(dma_addr, &ch->dmandptr);
3122 +}
3123 +
3124 +
3125 +/* The following can be used to describe DMA channels 0 to 15, and the */
3126 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3127 +
3128 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3129 +
3130 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3131 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3132 +
3133 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3134 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3135 +
3136 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3137 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3138 +
3139 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3140 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3141 +
3142 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3143 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3144 +#define DMA_DEV_ATMVCC(entry) 0
3145 +
3146 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3147 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3148 +
3149 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3150 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3151 +
3152 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3153 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3154 +
3155 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3156 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3157 +
3158 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3159 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3160 +
3161 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3162 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3163 +
3164 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3165 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3166 +
3167 +#define DMA_CHAN_USBIN 13 /* USB input */
3168 +#define DMA_DEV_USBIN 0 /* USB input */
3169 +
3170 +#define DMA_CHAN_USBOUT 14 /* USB output */
3171 +#define DMA_DEV_USBOUT 0 /* USB output */
3172 +
3173 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3174 +#define DMA_DEV_EXTERN 0 /* External DMA */
3175 +
3176 +/*
3177 + * An RC32355 dma descriptor in system memory
3178 + */
3179 +typedef struct {
3180 + u32 cmdstat; /* control and status */
3181 + u32 curr_addr; /* current address of data */
3182 + u32 devcs; /* peripheral-specific control and status */
3183 + u32 link; /* link to next descriptor */
3184 +} rc32355_dma_desc_t;
3185 +
3186 +/* Values for the descriptor cmdstat word */
3187 +
3188 +#define DMADESC_F 0x80000000u /* Finished bit */
3189 +#define DMADESC_D 0x40000000u /* Done bit */
3190 +#define DMADESC_T 0x20000000u /* Terminated bit */
3191 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3192 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3193 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3194 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3195 +
3196 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3197 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3198 +
3199 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3200 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3201 +
3202 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3203 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3204 +
3205 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3206 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3207 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3208 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3209 +
3210 +#define DMA_DEVCMD(devcmd) \
3211 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3212 +#define DMA_DS(ds) \
3213 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3214 +#define DMA_COUNT(count) \
3215 + ((count) & DMADESC_COUNT_MASK)
3216 +
3217 +#endif /* RC32355_DMA_H */
3218 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3219 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3220 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-01-10 00:32:33.000000000 +0100
3221 @@ -0,0 +1,442 @@
3222 +/**************************************************************************
3223 + *
3224 + * BRIEF MODULE DESCRIPTION
3225 + * Ethernet registers on IDT RC32355
3226 + *
3227 + * Copyright 2004 IDT Inc.
3228 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3229 + *
3230 + *
3231 + * This program is free software; you can redistribute it and/or modify it
3232 + * under the terms of the GNU General Public License as published by the
3233 + * Free Software Foundation; either version 2 of the License, or (at your
3234 + * option) any later version.
3235 + *
3236 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3237 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3238 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3239 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3240 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3241 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3242 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3243 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3244 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3245 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3246 + *
3247 + * You should have received a copy of the GNU General Public License along
3248 + * with this program; if not, write to the Free Software Foundation, Inc.,
3249 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3250 + *
3251 + *
3252 + * May 2004 rkt
3253 + * Initial Release
3254 + *
3255 + **************************************************************************
3256 + */
3257 +
3258 +
3259 +#ifndef RC32355_ETHER_H
3260 +#define RC32355_ETHER_H
3261 +
3262 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3263 +
3264 +/*
3265 + * A partial image of the RC32355 ethernet registers
3266 + */
3267 +typedef struct {
3268 + u32 ethintfc;
3269 + u32 ethfifott;
3270 + u32 etharc;
3271 + u32 ethhash0;
3272 + u32 ethhash1;
3273 + u32 ethfifost;
3274 + u32 ethfifos;
3275 + u32 ethodeops;
3276 + u32 ethis;
3277 + u32 ethos;
3278 + u32 ethmcp;
3279 + u32 _u1;
3280 + u32 ethid;
3281 + u32 _u2;
3282 + u32 _u3;
3283 + u32 _u4;
3284 + u32 ethod;
3285 + u32 _u5;
3286 + u32 _u6;
3287 + u32 _u7;
3288 + u32 ethodeop;
3289 + u32 _u8[43];
3290 + u32 ethsal0;
3291 + u32 ethsah0;
3292 + u32 ethsal1;
3293 + u32 ethsah1;
3294 + u32 ethsal2;
3295 + u32 ethsah2;
3296 + u32 ethsal3;
3297 + u32 ethsah3;
3298 + u32 ethrbc;
3299 + u32 ethrpc;
3300 + u32 ethrupc;
3301 + u32 ethrfc;
3302 + u32 ethtbc;
3303 + u32 ethgpf;
3304 + u32 _u9[50];
3305 + u32 ethmac1;
3306 + u32 ethmac2;
3307 + u32 ethipgt;
3308 + u32 ethipgr;
3309 + u32 ethclrt;
3310 + u32 ethmaxf;
3311 + u32 _u10;
3312 + u32 ethmtest;
3313 + u32 miimcfg;
3314 + u32 miimcmd;
3315 + u32 miimaddr;
3316 + u32 miimwtd;
3317 + u32 miimrdd;
3318 + u32 miimind;
3319 + u32 _u11;
3320 + u32 _u12;
3321 + u32 ethcfsa0;
3322 + u32 ethcfsa1;
3323 + u32 ethcfsa2;
3324 +} rc32355_eth_regs_t;
3325 +
3326 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3327 +
3328 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3329 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3330 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3331 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3332 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3333 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3334 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3335 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3336 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3337 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3338 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3339 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3340 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3341 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3342 +
3343 +/* for n in { 0, 1, 2, 3 } */
3344 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3345 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3346 +
3347 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3348 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3349 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3350 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3351 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3352 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3353 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3354 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3355 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3356 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3357 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3358 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3359 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3360 +
3361 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3362 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3363 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3364 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3365 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3366 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3367 +
3368 +/* for n in { 0, 1, 2 } */
3369 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3370 +
3371 +
3372 +/*
3373 + * Register Interpretations follow
3374 + */
3375 +
3376 +/******************************************************************************
3377 + * ETHINTFC register
3378 + *****************************************************************************/
3379 +
3380 +#define ETHERINTFC_EN (1<<0)
3381 +#define ETHERINTFC_ITS (1<<1)
3382 +#define ETHERINTFC_RES (1<<2)
3383 +#define ETHERINTFC_RIP (1<<2)
3384 +#define ETHERINTFC_JAM (1<<3)
3385 +
3386 +/******************************************************************************
3387 + * ETHFIFOTT register
3388 + *****************************************************************************/
3389 +
3390 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3391 +
3392 +/******************************************************************************
3393 + * ETHARC register
3394 + *****************************************************************************/
3395 +
3396 +#define ETHERARC_PRO (1<<0)
3397 +#define ETHERARC_AM (1<<1)
3398 +#define ETHERARC_AFM (1<<2)
3399 +#define ETHERARC_AB (1<<3)
3400 +
3401 +/******************************************************************************
3402 + * ETHHASH registers
3403 + *****************************************************************************/
3404 +
3405 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3406 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3407 +
3408 +/******************************************************************************
3409 + * ETHSA registers
3410 + *****************************************************************************/
3411 +
3412 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3413 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3414 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3415 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3416 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3417 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3418 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3419 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3420 +
3421 +/******************************************************************************
3422 + * ETHFIFOST register
3423 + *****************************************************************************/
3424 +
3425 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3426 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3427 +
3428 +/******************************************************************************
3429 + * ETHFIFOS register
3430 + *****************************************************************************/
3431 +
3432 +#define ETHERFIFOS_IR (1<<0)
3433 +#define ETHERFIFOS_OR (1<<1)
3434 +#define ETHERFIFOS_OVR (1<<2)
3435 +#define ETHERFIFOS_UND (1<<3)
3436 +
3437 +/******************************************************************************
3438 + * DATA registers
3439 + *****************************************************************************/
3440 +
3441 +#define ETHERID(v) (((v)&0xffff)<<0)
3442 +#define ETHEROD(v) (((v)&0xffff)<<0)
3443 +
3444 +/******************************************************************************
3445 + * ETHODEOPS register
3446 + *****************************************************************************/
3447 +
3448 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3449 +
3450 +/******************************************************************************
3451 + * ETHODEOP register
3452 + *****************************************************************************/
3453 +
3454 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3455 +
3456 +/******************************************************************************
3457 + * ETHIS register
3458 + *****************************************************************************/
3459 +
3460 +#define ETHERIS_EOP (1<<0)
3461 +#define ETHERIS_ROK (1<<2)
3462 +#define ETHERIS_FM (1<<3)
3463 +#define ETHERIS_MP (1<<4)
3464 +#define ETHERIS_BP (1<<5)
3465 +#define ETHERIS_VLT (1<<6)
3466 +#define ETHERIS_CF (1<<7)
3467 +#define ETHERIS_OVR (1<<8)
3468 +#define ETHERIS_CRC (1<<9)
3469 +#define ETHERIS_CV (1<<10)
3470 +#define ETHERIS_DB (1<<11)
3471 +#define ETHERIS_LE (1<<12)
3472 +#define ETHERIS_LOR (1<<13)
3473 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3474 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3475 +
3476 +/******************************************************************************
3477 + * ETHOS register
3478 + *****************************************************************************/
3479 +
3480 +#define ETHEROS_T (1<<0)
3481 +#define ETHEROS_TOK (1<<6)
3482 +#define ETHEROS_MP (1<<7)
3483 +#define ETHEROS_BP (1<<8)
3484 +#define ETHEROS_UND (1<<9)
3485 +#define ETHEROS_OF (1<<10)
3486 +#define ETHEROS_ED (1<<11)
3487 +#define ETHEROS_EC (1<<12)
3488 +#define ETHEROS_LC (1<<13)
3489 +#define ETHEROS_TD (1<<14)
3490 +#define ETHEROS_CRC (1<<15)
3491 +#define ETHEROS_LE (1<<16)
3492 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3493 +#define ETHEROS_PFD (1<<21)
3494 +
3495 +/******************************************************************************
3496 + * Statistics registers
3497 + *****************************************************************************/
3498 +
3499 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3500 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3501 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3502 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3503 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3504 +
3505 +/******************************************************************************
3506 + * ETHGPF register
3507 + *****************************************************************************/
3508 +
3509 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3510 +
3511 +/******************************************************************************
3512 + * MAC registers
3513 + *****************************************************************************/