openwrt/target/linux/aruba-2.6/patches/002-irq.patch

   1 diff -Nur linux-2.6.15/arch/mips/aruba/idtIRQ.S linux-2.6.15-openwrt/arch/mips/aruba/idtIRQ.S
   2 --- linux-2.6.15/arch/mips/aruba/idtIRQ.S       1970-01-01 01:00:00.000000000 +0100
   3 +++ linux-2.6.15-openwrt/arch/mips/aruba/idtIRQ.S       2006-01-10 00:32:32.000000000 +0100
   4 @@ -0,0 +1,87 @@
   5 +/**************************************************************************
   6 + *
   7 + *  BRIEF MODULE DESCRIPTION
   8 + *     Intterrupt dispatcher code for IDT boards
   9 + *
  10 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
  11 + *
  12 + *  This program is free software; you can redistribute  it and/or modify it
  13 + *  under  the terms of  the GNU General  Public License as published by the
  14 + *  Free Software Foundation;  either version 2 of the  License, or (at your
  15 + *  option) any later version.
  16 + *
  17 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 + *
  28 + *  You should have received a copy of the  GNU General Public License along
  29 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  30 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  31 + *
  32 + *
  33 + **************************************************************************
  34 + * May 2004 rkt, neb
  35 + *
  36 + * Initial Release
  37 + *
  38 + *
  39 + *
  40 + **************************************************************************
  41 + */
  42 +
  43 +
  44 +#include <asm/asm.h>
  45 +#include <asm/mipsregs.h>
  46 +#include <asm/regdef.h>
  47 +#include <asm/stackframe.h>
  48 +
  49 +       .text
  50 +       .set    noreorder
  51 +       .set    noat
  52 +       .align  5
  53 +       NESTED(idtIRQ, PT_SIZE, sp)
  54 +       .set noat
  55 +       SAVE_ALL
  56 +       CLI
  57 +
  58 +       .set    at
  59 +       .set    noreorder
  60 +
  61 +       /* Get the pending interrupts */
  62 +       mfc0    t0, CP0_CAUSE
  63 +       nop
  64 +
  65 +       /* Isolate the allowed ones by anding the irq mask */
  66 +       mfc0    t2, CP0_STATUS
  67 +       move    a1, sp          /* need a nop here, hence we anticipate */
  68 +       andi    t0, CAUSEF_IP
  69 +       and     t0, t2
  70 +
  71 +       /* check for r4k counter/timer IRQ. */
  72 +
  73 +       andi    t1, t0, CAUSEF_IP7
  74 +       beqz    t1, 1f
  75 +       nop
  76 +
  77 +       jal     aruba_timer_interrupt
  78 +
  79 +       li      a0, 7
  80 +
  81 +       j       ret_from_irq
  82 +       nop
  83 +1:
  84 +       jal     aruba_irqdispatch
  85 +       move    a0, t0
  86 +       j       ret_from_irq
  87 +       nop
  88 +
  89 +       END(idtIRQ)
  90 +
  91 +
  92 diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/aruba/irq.c
  93 --- linux-2.6.15/arch/mips/aruba/irq.c  1970-01-01 01:00:00.000000000 +0100
  94 +++ linux-2.6.15-openwrt/arch/mips/aruba/irq.c  2006-01-10 00:32:32.000000000 +0100
  95 @@ -0,0 +1,424 @@
  96 +/**************************************************************************
  97 + *
  98 + *  BRIEF MODULE DESCRIPTION
  99 + *     Interrupt routines for IDT EB434 boards
 100 + *
 101 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 102 + *
 103 + *  This program is free software; you can redistribute  it and/or modify it
 104 + *  under  the terms of  the GNU General  Public License as published by the
 105 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 106 + *  option) any later version.
 107 + *
 108 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 109 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 110 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 111 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 112 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 113 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 114 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 115 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 116 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 117 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 118 + *
 119 + *  You should have received a copy of the  GNU General Public License along
 120 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 121 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 122 + *
 123 + *
 124 + **************************************************************************
 125 + * May 2004 rkt, neb
 126 + *
 127 + * Initial Release
 128 + *
 129 + *
 130 + *
 131 + **************************************************************************
 132 + */
 133 +
 134 +#include <linux/errno.h>
 135 +#include <linux/init.h>
 136 +#include <linux/kernel_stat.h>
 137 +#include <linux/module.h>
 138 +#include <linux/signal.h>
 139 +#include <linux/sched.h>
 140 +#include <linux/types.h>
 141 +#include <linux/interrupt.h>
 142 +#include <linux/ioport.h>
 143 +#include <linux/timex.h>
 144 +#include <linux/slab.h>
 145 +#include <linux/random.h>
 146 +#include <linux/delay.h>
 147 +
 148 +#include <asm/bitops.h>
 149 +#include <asm/bootinfo.h>
 150 +#include <asm/io.h>
 151 +#include <asm/mipsregs.h>
 152 +#include <asm/system.h>
 153 +#include <asm/idt-boards/rc32434/rc32434.h>
 154 +#include <asm/idt-boards/rc32434/rc32434_gpio.h>
 155 +
 156 +#include <asm/irq.h>
 157 +
 158 +#undef DEBUG_IRQ
 159 +#ifdef DEBUG_IRQ
 160 +/* note: prints function name for you */
 161 +#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
 162 +#else
 163 +#define DPRINTK(fmt, args...)
 164 +#endif
 165 +
 166 +extern asmlinkage void idtIRQ(void);
 167 +static unsigned int startup_irq(unsigned int irq);
 168 +static void end_irq(unsigned int irq_nr);
 169 +static void mask_and_ack_irq(unsigned int irq_nr);
 170 +static void aruba_enable_irq(unsigned int irq_nr);
 171 +static void aruba_disable_irq(unsigned int irq_nr);
 172 +
 173 +extern void __init init_generic_irq(void);
 174 +
 175 +typedef struct {
 176 +       u32 mask;
 177 +       volatile u32 *base_addr;
 178 +} intr_group_t;
 179 +
 180 +static const intr_group_t intr_group_merlot[NUM_INTR_GROUPS] = {
 181 +       {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0)},
 182 +};
 183 +
 184 +#define READ_PEND_MERLOT(base) (*((volatile unsigned long *)(0xbc003010)))
 185 +#define READ_MASK_MERLOT(base) (*((volatile unsigned long *)(0xbc003010 + 4)))
 186 +#define WRITE_MASK_MERLOT(base, val) ((*((volatile unsigned long *)((0xbc003010) + 4))) = (val))
 187 +
 188 +static const intr_group_t intr_group_muscat[NUM_INTR_GROUPS] = {
 189 +       {0x0000efff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
 190 +       {0x00001fff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
 191 +       {0x00000007, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
 192 +       {0x0003ffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
 193 +       {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
 194 +};
 195 +
 196 +#define READ_PEND_MUSCAT(base) (*(base))
 197 +#define READ_MASK_MUSCAT(base) (*(base + 2))
 198 +#define WRITE_MASK_MUSCAT(base, val) (*(base + 2) = (val))
 199 +
 200 +static inline int irq_to_group(unsigned int irq_nr)
 201 +{
 202 +       switch (mips_machtype) {
 203 +               case MACH_ARUBA_AP70:
 204 +                       return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
 205 +               case MACH_ARUBA_AP65:
 206 +               case MACH_ARUBA_AP60:
 207 +               default:
 208 +                       return 0;
 209 +       }
 210 +}
 211 +
 212 +static inline int group_to_ip(unsigned int group)
 213 +{
 214 +       switch (mips_machtype) {
 215 +               case MACH_ARUBA_AP70:
 216 +                       return group + 2;
 217 +               case MACH_ARUBA_AP65:
 218 +               case MACH_ARUBA_AP60:
 219 +               default:
 220 +                       return 6;
 221 +       }
 222 +}
 223 +
 224 +static inline void enable_local_irq(unsigned int ip)
 225 +{
 226 +       int ipnum = 0x100 << ip;
 227 +       clear_c0_cause(ipnum);
 228 +       set_c0_status(ipnum);
 229 +}
 230 +
 231 +static inline void disable_local_irq(unsigned int ip)
 232 +{
 233 +       int ipnum = 0x100 << ip;
 234 +       clear_c0_status(ipnum);
 235 +}
 236 +
 237 +static inline void ack_local_irq(unsigned int ip)
 238 +{
 239 +       int ipnum = 0x100 << ip;
 240 +       clear_c0_cause(ipnum);
 241 +}
 242 +
 243 +static void aruba_enable_irq(unsigned int irq_nr)
 244 +{
 245 +       unsigned long flags;
 246 +       int ip = irq_nr - GROUP0_IRQ_BASE;
 247 +       unsigned int group, intr_bit;
 248 +       volatile unsigned int *addr;
 249 +
 250 +
 251 +       local_irq_save(flags);
 252 +
 253 +       if (ip < 0) {
 254 +               enable_local_irq(irq_nr);
 255 +       } else {
 256 +               // calculate group
 257 +               switch (mips_machtype) {
 258 +                       case MACH_ARUBA_AP70:
 259 +                               group = ip >> 5;
 260 +                               break;
 261 +                       case MACH_ARUBA_AP65:
 262 +                       case MACH_ARUBA_AP60:
 263 +                       default:
 264 +                               group = 0;
 265 +                               break;
 266 +               }
 267 +
 268 +               // calc interrupt bit within group
 269 +               ip -= (group << 5);
 270 +               intr_bit = 1 << ip;
 271 +
 272 +               // first enable the IP mapped to this IRQ
 273 +               enable_local_irq(group_to_ip(group));
 274 +
 275 +               switch (mips_machtype) {
 276 +                       case MACH_ARUBA_AP70:
 277 +                               addr = intr_group_muscat[group].base_addr;
 278 +                               // unmask intr within group
 279 +                               WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
 280 +                               break;
 281 +                       case MACH_ARUBA_AP65:
 282 +                       case MACH_ARUBA_AP60:
 283 +                       default:
 284 +                               addr = intr_group_merlot[group].base_addr;
 285 +                               WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
 286 +                               break;
 287 +               }
 288 +       }
 289 +
 290 +       local_irq_restore(flags);
 291 +
 292 +}
 293 +
 294 +static void aruba_disable_irq(unsigned int irq_nr)
 295 +{
 296 +       unsigned long flags;
 297 +       int ip = irq_nr - GROUP0_IRQ_BASE;
 298 +       unsigned int group, intr_bit, mask;
 299 +       volatile unsigned int *addr;
 300 +
 301 +       local_irq_save(flags);
 302 +
 303 +       if (ip < 0) {
 304 +               disable_local_irq(irq_nr);
 305 +       } else {
 306 +               // calculate group
 307 +               switch (mips_machtype) {
 308 +                       case MACH_ARUBA_AP70:
 309 +                               group = ip >> 5;
 310 +                               break;
 311 +                       case MACH_ARUBA_AP65:
 312 +                       case MACH_ARUBA_AP60:
 313 +                       default:
 314 +                               group = 0;
 315 +                               break;
 316 +               }
 317 +
 318 +               // calc interrupt bit within group
 319 +               ip -= group << 5;
 320 +               intr_bit = 1 << ip;
 321 +
 322 +               switch (mips_machtype) {
 323 +                       case MACH_ARUBA_AP70:
 324 +                               addr = intr_group_muscat[group].base_addr;
 325 +                               // mask intr within group
 326 +                               mask = READ_MASK_MUSCAT(addr);
 327 +                               mask |= intr_bit;
 328 +                               WRITE_MASK_MUSCAT(addr, mask);
 329 +
 330 +                               /*
 331 +                                  if there are no more interrupts enabled in this
 332 +                                  group, disable corresponding IP
 333 +                                */
 334 +                               if (mask == intr_group_muscat[group].mask)
 335 +                                       disable_local_irq(group_to_ip(group));
 336 +                               break;
 337 +                       case MACH_ARUBA_AP65:
 338 +                       case MACH_ARUBA_AP60:
 339 +                       default:
 340 +                               addr = intr_group_merlot[group].base_addr;
 341 +                               // mask intr within group
 342 +                               mask = READ_MASK_MERLOT(addr);
 343 +                               mask &= ~intr_bit;
 344 +                               WRITE_MASK_MERLOT(addr, mask);
 345 +                               if (!mask)
 346 +                                       disable_local_irq(group_to_ip(group));
 347 +                               break;
 348 +               }
 349 +       }
 350 +
 351 +       local_irq_restore(flags);
 352 +
 353 +}
 354 +
 355 +static unsigned int startup_irq(unsigned int irq_nr)
 356 +{
 357 +       aruba_enable_irq(irq_nr);
 358 +       return 0;
 359 +}
 360 +
 361 +static void shutdown_irq(unsigned int irq_nr)
 362 +{
 363 +       aruba_disable_irq(irq_nr);
 364 +       return;
 365 +}
 366 +
 367 +static void mask_and_ack_irq(unsigned int irq_nr)
 368 +{
 369 +       aruba_disable_irq(irq_nr);
 370 +       ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
 371 +}
 372 +
 373 +static void end_irq(unsigned int irq_nr)
 374 +{
 375 +
 376 +       unsigned long flags;
 377 +       int ip = irq_nr - GROUP0_IRQ_BASE;
 378 +       unsigned int intr_bit, group;
 379 +       volatile unsigned int *addr;
 380 +
 381 +
 382 +       local_irq_save(flags);
 383 +       if (irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)) {
 384 +               printk("warning: end_irq %d did not enable (%x) (ignoring)\n",
 385 +                      irq_nr, irq_desc[irq_nr].status);
 386 +       }
 387 +
 388 +       if (ip<0) {
 389 +               enable_local_irq(irq_nr);
 390 +       } else {
 391 +
 392 +               switch (mips_machtype) {
 393 +                       case MACH_ARUBA_AP70:
 394 +                               if (irq_nr == GROUP4_IRQ_BASE + 9)       idt_gpio->gpioistat &= 0xfffffdff;
 395 +                               else if (irq_nr == GROUP4_IRQ_BASE + 10) idt_gpio->gpioistat &= 0xfffffbff;
 396 +                               else if (irq_nr == GROUP4_IRQ_BASE + 11) idt_gpio->gpioistat &= 0xfffff7ff;
 397 +                               else if (irq_nr == GROUP4_IRQ_BASE + 12) idt_gpio->gpioistat &= 0xffffefff;
 398 +
 399 +                               group = ip >> 5;
 400 +
 401 +                               // calc interrupt bit within group
 402 +                               ip -= (group << 5);
 403 +                               intr_bit = 1 << ip;
 404 +
 405 +                               // first enable the IP mapped to this IRQ
 406 +                               enable_local_irq(group_to_ip(group));
 407 +
 408 +                               addr = intr_group_muscat[group].base_addr;
 409 +                               // unmask intr within group
 410 +                               WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
 411 +                               break;
 412 +
 413 +                       case MACH_ARUBA_AP65:
 414 +                               case MACH_ARUBA_AP60:
 415 +                               group = 0;
 416 +
 417 +                               // calc interrupt bit within group
 418 +                               intr_bit = 1 << ip;
 419 +
 420 +                               // first enable the IP mapped to this IRQ
 421 +                               enable_local_irq(group_to_ip(group));
 422 +
 423 +                               addr = intr_group_merlot[group].base_addr;
 424 +                               // unmask intr within group
 425 +                               WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
 426 +                               break;
 427 +               }
 428 +       }
 429 +       local_irq_restore(flags);
 430 +}
 431 +
 432 +static struct hw_interrupt_type aruba_irq_type = {
 433 +       .typename = "IDT434",
 434 +       .startup = startup_irq,
 435 +       .shutdown = shutdown_irq,
 436 +       .enable = aruba_enable_irq,
 437 +       .disable = aruba_disable_irq,
 438 +       .ack = mask_and_ack_irq,
 439 +       .end = end_irq,
 440 +};
 441 +
 442 +void __init arch_init_irq(void)
 443 +{
 444 +       int i;
 445 +       printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
 446 +       memset(irq_desc, 0, sizeof(irq_desc));
 447 +       set_except_vector(0, idtIRQ);
 448 +
 449 +
 450 +       set_c0_status(0xFF00);
 451 +
 452 +       for (i = 0; i < RC32434_NR_IRQS; i++) {
 453 +               irq_desc[i].status = IRQ_DISABLED;
 454 +               irq_desc[i].action = NULL;
 455 +               irq_desc[i].depth = 1;
 456 +               irq_desc[i].handler = &aruba_irq_type;
 457 +               spin_lock_init(&irq_desc[i].lock);
 458 +       }
 459 +
 460 +       switch (mips_machtype) {
 461 +               case MACH_ARUBA_AP70:
 462 +                       break;
 463 +               case MACH_ARUBA_AP65:
 464 +               case MACH_ARUBA_AP60:
 465 +               default:
 466 +                       WRITE_MASK_MERLOT(intr_group_merlot[0].base_addr, 0);
 467 +                       *((volatile unsigned long *)0xbc003014) = 0x10;
 468 +                       break;
 469 +       }
 470 +}
 471 +
 472 +/* Main Interrupt dispatcher */
 473 +void aruba_irqdispatch(unsigned long cp0_cause, struct pt_regs *regs)
 474 +{
 475 +       unsigned int pend, group, ip;
 476 +       volatile unsigned int *addr;
 477 +       switch (mips_machtype) {
 478 +               case MACH_ARUBA_AP70:
 479 +                       if ((ip = (cp0_cause & 0x7c00))) {
 480 +                               group = 21 - rc32434_clz(ip);
 481 +
 482 +                               addr = intr_group_muscat[group].base_addr;
 483 +
 484 +                               pend = READ_PEND_MUSCAT(addr);
 485 +                               pend &= ~READ_MASK_MUSCAT(addr);        // only unmasked interrupts
 486 +                               pend = 39 - rc32434_clz(pend);
 487 +                               do_IRQ((group << 5) + pend, regs);
 488 +                       }
 489 +                       break;
 490 +               case MACH_ARUBA_AP65:
 491 +               case MACH_ARUBA_AP60:
 492 +               default:
 493 +                       if (cp0_cause & 0x4000) {
 494 +                               // Misc Interrupt
 495 +                               group = 0;
 496 +                               addr = intr_group_merlot[group].base_addr;
 497 +                               pend = READ_PEND_MERLOT(addr);
 498 +                               pend &= READ_MASK_MERLOT(addr); // only unmasked interrupts
 499 +                               /* handle one misc interrupt at a time */
 500 +                               while (pend) {
 501 +                                       unsigned int intr_bit, irq_nr;
 502 +                                       intr_bit = pend ^ (pend - 1);
 503 +                                       irq_nr = ((31 - rc32434_clz(pend)) + GROUP0_IRQ_BASE);
 504 +                                       do_IRQ(irq_nr, regs);
 505 +                                       pend &= ~intr_bit;
 506 +                               }
 507 +                       }
 508 +                       if (cp0_cause & 0x3c00) {
 509 +                               while (cp0_cause) {
 510 +                                       unsigned int intr_bit, irq_nr;
 511 +                                       intr_bit = cp0_cause ^ (cp0_cause - 1);
 512 +                                       irq_nr = ((31 - rc32434_clz(cp0_cause)) - GROUP0_IRQ_BASE);
 513 +                                       do_IRQ(irq_nr, regs);
 514 +                                       cp0_cause &= ~intr_bit;
 515 +                               }
 516 +                       }
 517 +                       break;
 518 +       }
 519 +}