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[openwrt/svn-archive/archive.git] / openwrt / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
2 --- linux.old/arch/mips/Makefile 2006-04-27 18:04:37.000000000 +0200
3 +++ linux.dev/arch/mips/Makefile 2006-04-27 19:24:19.000000000 +0200
4 @@ -726,6 +726,19 @@
5 endif
6
7 #
8 +# Broadcom BCM947XX variants
9 +#
10 +ifdef CONFIG_BCM947XX
11 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
12 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
13 +LOADADDR := 0x80001000
14 +
15 +zImage: vmlinux
16 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
17 +export LOADADDR
18 +endif
19 +
20 +#
21 # Choosing incompatible machines durings configuration will result in
22 # error messages during linking. Select a default linkscript if
23 # none has been choosen above.
24 @@ -778,6 +791,7 @@
25 $(MAKE) -C arch/$(ARCH)/tools clean
26 $(MAKE) -C arch/mips/baget clean
27 $(MAKE) -C arch/mips/lasat clean
28 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
29
30 archmrproper:
31 @$(MAKEBOOT) mrproper
32 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
33 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
34 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-05-02 17:46:22.000000000 +0200
35 @@ -0,0 +1,17 @@
36 +#
37 +# Makefile for the BCM947xx specific kernel interface routines
38 +# under Linux.
39 +#
40 +
41 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
42 +
43 +O_TARGET := bcm947xx.o
44 +
45 +export-objs := export.o
46 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
47 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
48 +obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
49 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
50 +obj-y += export.o
51 +
52 +include $(TOPDIR)/Rules.make
53 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
54 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
55 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-04-27 20:32:48.000000000 +0200
56 @@ -0,0 +1,1212 @@
57 +/*
58 + * Misc useful routines to access NIC SROM/OTP .
59 + *
60 + * Copyright 2006, Broadcom Corporation
61 + * All Rights Reserved.
62 + *
63 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
64 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
65 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
66 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
67 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
68 + */
69 +
70 +#include <typedefs.h>
71 +#include <bcmdefs.h>
72 +#include <osl.h>
73 +#include <bcmutils.h>
74 +#include <bcmsrom.h>
75 +#include <bcmdevs.h>
76 +#include <bcmendian.h>
77 +#include <sbpcmcia.h>
78 +#include <pcicfg.h>
79 +#include <sbutils.h>
80 +#include <bcmnvram.h>
81 +
82 +/* debug/trace */
83 +#if defined(WLTEST)
84 +#define BS_ERROR(args) printf args
85 +#else
86 +#define BS_ERROR(args)
87 +#endif /* BCMDBG_ERR || WLTEST */
88 +
89 +#define VARS_MAX 4096 /* should be reduced */
90 +
91 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
92 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
93 +
94 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
95 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
96 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
97 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
98 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
99 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
100 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
101 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
102 + bool check_crc);
103 +
104 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
105 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
106 +
107 +/*
108 + * Initialize local vars from the right source for this platform.
109 + * Return 0 on success, nonzero on error.
110 + */
111 +int
112 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
113 +{
114 + ASSERT(bustype == BUSTYPE(bustype));
115 + if (vars == NULL || count == NULL)
116 + return (0);
117 +
118 + switch (BUSTYPE(bustype)) {
119 + case SB_BUS:
120 + case JTAG_BUS:
121 + return initvars_flash_sb(sbh, vars, count);
122 +
123 + case PCI_BUS:
124 + ASSERT(curmap); /* can not be NULL */
125 + return initvars_srom_pci(sbh, curmap, vars, count);
126 +
127 + case PCMCIA_BUS:
128 + return initvars_cis_pcmcia(sbh, osh, vars, count);
129 +
130 +
131 + default:
132 + ASSERT(0);
133 + }
134 + return (-1);
135 +}
136 +
137 +/* support only 16-bit word read from srom */
138 +int
139 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
140 +{
141 + void *srom;
142 + uint i, off, nw;
143 +
144 + ASSERT(bustype == BUSTYPE(bustype));
145 +
146 + /* check input - 16-bit access only */
147 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
148 + return 1;
149 +
150 + off = byteoff / 2;
151 + nw = nbytes / 2;
152 +
153 + if (BUSTYPE(bustype) == PCI_BUS) {
154 + if (!curmap)
155 + return 1;
156 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
157 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
158 + return 1;
159 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
160 + for (i = 0; i < nw; i++) {
161 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
162 + return 1;
163 + }
164 + } else {
165 + return 1;
166 + }
167 +
168 + return 0;
169 +}
170 +
171 +/* support only 16-bit word write into srom */
172 +int
173 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
174 +{
175 + uint16 *srom;
176 + uint i, nw, crc_range;
177 + uint16 image[SPROM_SIZE];
178 + uint8 crc;
179 + volatile uint32 val32;
180 +
181 + ASSERT(bustype == BUSTYPE(bustype));
182 +
183 + /* check input - 16-bit access only */
184 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
185 + return 1;
186 +
187 + /* Are we writing the whole thing at once? */
188 + if ((byteoff == 0) &&
189 + ((nbytes == SPROM_SIZE) ||
190 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
191 + (nbytes == (SROM4_WORDS * 2)))) {
192 + crc_range = nbytes;
193 + bcopy((void*)buf, (void*)image, nbytes);
194 + nw = nbytes / 2;
195 + } else {
196 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
197 + crc_range = SPROM_SIZE;
198 + else
199 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
200 +
201 + nw = crc_range / 2;
202 + /* read first 64 words from srom */
203 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
204 + return 1;
205 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
206 + crc_range = SROM4_WORDS;
207 + nw = crc_range / 2;
208 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
209 + return 1;
210 + }
211 + /* make changes */
212 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
213 + }
214 +
215 + /* calculate crc */
216 + htol16_buf(image, crc_range);
217 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
218 + ltoh16_buf(image, crc_range);
219 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
220 +
221 + if (BUSTYPE(bustype) == PCI_BUS) {
222 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
223 + /* enable writes to the SPROM */
224 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
225 + val32 |= SPROM_WRITEEN;
226 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
227 + bcm_mdelay(WRITE_ENABLE_DELAY);
228 + /* write srom */
229 + for (i = 0; i < nw; i++) {
230 + W_REG(osh, &srom[i], image[i]);
231 + bcm_mdelay(WRITE_WORD_DELAY);
232 + }
233 + /* disable writes to the SPROM */
234 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
235 + ~SPROM_WRITEEN);
236 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
237 + /* enable writes to the SPROM */
238 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
239 + return 1;
240 + bcm_mdelay(WRITE_ENABLE_DELAY);
241 + /* write srom */
242 + for (i = 0; i < nw; i++) {
243 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
244 + bcm_mdelay(WRITE_WORD_DELAY);
245 + }
246 + /* disable writes to the SPROM */
247 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
248 + return 1;
249 + } else {
250 + return 1;
251 + }
252 +
253 + bcm_mdelay(WRITE_ENABLE_DELAY);
254 + return 0;
255 +}
256 +
257 +
258 +static int
259 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
260 +{
261 + char eabuf[32];
262 + char *vp, *base;
263 + uint8 *cis, tup, tlen, sromrev = 1;
264 + int i, j;
265 + uint varsize;
266 + bool ag_init = FALSE;
267 + uint32 w32;
268 +
269 + ASSERT(vars);
270 + ASSERT(count);
271 +
272 + base = vp = MALLOC(osh, VARS_MAX);
273 + ASSERT(vp);
274 + if (!vp)
275 + return -2;
276 +
277 + while (ciscnt--) {
278 + cis = *pcis++;
279 + i = 0;
280 + do {
281 + tup = cis[i++];
282 + tlen = cis[i++];
283 + if ((i + tlen) >= CIS_SIZE)
284 + break;
285 +
286 + switch (tup) {
287 + case CISTPL_MANFID:
288 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
289 + vp++;
290 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
291 + vp++;
292 + break;
293 +
294 + case CISTPL_FUNCE:
295 + switch (cis[i]) {
296 + case LAN_NID:
297 + ASSERT(cis[i + 1] == 6);
298 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
299 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
300 + vp++;
301 + break;
302 + case 1: /* SDIO Extended Data */
303 + vp += sprintf(vp, "sdmaxblk=%d",
304 + (cis[i + 13] << 8) | cis[i + 12]);
305 + vp++;
306 + break;
307 + }
308 + break;
309 +
310 + case CISTPL_CFTABLE:
311 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
312 + vp++;
313 + break;
314 +
315 + case CISTPL_BRCM_HNBU:
316 + switch (cis[i]) {
317 + case HNBU_SROMREV:
318 + sromrev = cis[i + 1];
319 + break;
320 +
321 + case HNBU_CHIPID:
322 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
323 + cis[i + 1]);
324 + vp++;
325 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
326 + cis[i + 3]);
327 + vp++;
328 + if (tlen == 7) {
329 + vp += sprintf(vp, "chiprev=%d",
330 + (cis[i + 6] << 8) + cis[i + 5]);
331 + vp++;
332 + }
333 + break;
334 +
335 + case HNBU_BOARDREV:
336 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
337 + vp++;
338 + break;
339 +
340 + case HNBU_AA:
341 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
342 + vp++;
343 + break;
344 +
345 + case HNBU_AG:
346 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
347 + vp++;
348 + ag_init = TRUE;
349 + break;
350 +
351 + case HNBU_CC:
352 + ASSERT(sromrev == 1);
353 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
354 + vp++;
355 + break;
356 +
357 + case HNBU_PAPARMS:
358 + if (tlen == 2) {
359 + ASSERT(sromrev == 1);
360 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
361 + vp++;
362 + } else if (tlen >= 9) {
363 + if (tlen == 10) {
364 + ASSERT(sromrev == 2);
365 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
366 + vp++;
367 + } else
368 + ASSERT(tlen == 9);
369 +
370 + for (j = 0; j < 3; j++) {
371 + vp += sprintf(vp, "pa0b%d=%d", j,
372 + (cis[i + (j * 2) + 2] << 8) +
373 + cis[i + (j * 2) + 1]);
374 + vp++;
375 + }
376 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
377 + vp++;
378 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
379 + vp++;
380 + } else
381 + ASSERT(tlen >= 9);
382 + break;
383 +
384 + case HNBU_OEM:
385 + ASSERT(sromrev == 1);
386 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
387 + cis[i + 1], cis[i + 2],
388 + cis[i + 3], cis[i + 4],
389 + cis[i + 5], cis[i + 6],
390 + cis[i + 7], cis[i + 8]);
391 + vp++;
392 + break;
393 +
394 + case HNBU_BOARDFLAGS:
395 + w32 = (cis[i + 2] << 8) + cis[i + 1];
396 + if (tlen == 5)
397 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
398 + vp += sprintf(vp, "boardflags=0x%x", w32);
399 + vp++;
400 + break;
401 +
402 + case HNBU_LEDS:
403 + if (cis[i + 1] != 0xff) {
404 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
405 + vp++;
406 + }
407 + if (cis[i + 2] != 0xff) {
408 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
409 + vp++;
410 + }
411 + if (cis[i + 3] != 0xff) {
412 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
413 + vp++;
414 + }
415 + if (cis[i + 4] != 0xff) {
416 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
417 + vp++;
418 + }
419 + break;
420 +
421 + case HNBU_CCODE:
422 + {
423 + char str[3];
424 + ASSERT(sromrev > 1);
425 + str[0] = cis[i + 1];
426 + str[1] = cis[i + 2];
427 + str[2] = 0;
428 + vp += sprintf(vp, "ccode=%s", str);
429 + vp++;
430 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
431 + vp++;
432 + break;
433 + }
434 +
435 + case HNBU_CCKPO:
436 + ASSERT(sromrev > 2);
437 + vp += sprintf(vp, "cckpo=0x%x",
438 + (cis[i + 2] << 8) | cis[i + 1]);
439 + vp++;
440 + break;
441 +
442 + case HNBU_OFDMPO:
443 + ASSERT(sromrev > 2);
444 + vp += sprintf(vp, "ofdmpo=0x%x",
445 + (cis[i + 4] << 24) |
446 + (cis[i + 3] << 16) |
447 + (cis[i + 2] << 8) |
448 + cis[i + 1]);
449 + vp++;
450 + break;
451 + }
452 + break;
453 +
454 + }
455 + i += tlen;
456 + } while (tup != 0xff);
457 + }
458 +
459 + /* Set the srom version */
460 + vp += sprintf(vp, "sromrev=%d", sromrev);
461 + vp++;
462 +
463 + /* if there is no antenna gain field, set default */
464 + if (ag_init == FALSE) {
465 + ASSERT(sromrev == 1);
466 + vp += sprintf(vp, "ag0=%d", 0xff);
467 + vp++;
468 + }
469 +
470 + /* final nullbyte terminator */
471 + *vp++ = '\0';
472 + varsize = (uint)(vp - base);
473 +
474 + ASSERT((vp - base) < VARS_MAX);
475 +
476 + if (varsize == VARS_MAX) {
477 + *vars = base;
478 + } else {
479 + vp = MALLOC(osh, varsize);
480 + ASSERT(vp);
481 + if (vp)
482 + bcopy(base, vp, varsize);
483 + MFREE(osh, base, VARS_MAX);
484 + *vars = vp;
485 + if (!vp) {
486 + *count = 0;
487 + return -2;
488 + }
489 + }
490 + *count = varsize;
491 +
492 + return (0);
493 +}
494 +
495 +
496 +/* set PCMCIA sprom command register */
497 +static int
498 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
499 +{
500 + uint8 status = 0;
501 + uint wait_cnt = 1000;
502 +
503 + /* write sprom command register */
504 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
505 +
506 + /* wait status */
507 + while (wait_cnt--) {
508 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
509 + if (status & SROM_DONE)
510 + return 0;
511 + }
512 +
513 + return 1;
514 +}
515 +
516 +/* read a word from the PCMCIA srom */
517 +static int
518 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
519 +{
520 + uint8 addr_l, addr_h, data_l, data_h;
521 +
522 + addr_l = (uint8)((addr * 2) & 0xff);
523 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
524 +
525 + /* set address */
526 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
527 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
528 +
529 + /* do read */
530 + if (sprom_cmd_pcmcia(osh, SROM_READ))
531 + return 1;
532 +
533 + /* read data */
534 + data_h = data_l = 0;
535 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
536 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
537 +
538 + *data = (data_h << 8) | data_l;
539 + return 0;
540 +}
541 +
542 +/* write a word to the PCMCIA srom */
543 +static int
544 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
545 +{
546 + uint8 addr_l, addr_h, data_l, data_h;
547 +
548 + addr_l = (uint8)((addr * 2) & 0xff);
549 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
550 + data_l = (uint8)(data & 0xff);
551 + data_h = (uint8)((data >> 8) & 0xff);
552 +
553 + /* set address */
554 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
555 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
556 +
557 + /* write data */
558 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
559 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
560 +
561 + /* do write */
562 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
563 +}
564 +
565 +/*
566 + * Read in and validate sprom.
567 + * Return 0 on success, nonzero on error.
568 + */
569 +static int
570 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
571 +{
572 + int err = 0;
573 + uint i;
574 +
575 + /* read the sprom */
576 + for (i = 0; i < nwords; i++)
577 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
578 +
579 + if (check_crc) {
580 + /* fixup the endianness so crc8 will pass */
581 + htol16_buf(buf, nwords * 2);
582 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
583 + err = 1;
584 + /* now correct the endianness of the byte array */
585 + ltoh16_buf(buf, nwords * 2);
586 + }
587 +
588 + return err;
589 +}
590 +
591 +/*
592 +* Create variable table from memory.
593 +* Return 0 on success, nonzero on error.
594 +*/
595 +static int
596 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
597 +{
598 + int c = (int)(end - start);
599 +
600 + /* do it only when there is more than just the null string */
601 + if (c > 1) {
602 + char *vp = MALLOC(osh, c);
603 + ASSERT(vp);
604 + if (!vp)
605 + return BCME_NOMEM;
606 + bcopy(start, vp, c);
607 + *vars = vp;
608 + *count = c;
609 + }
610 + else {
611 + *vars = NULL;
612 + *count = 0;
613 + }
614 +
615 + return 0;
616 +}
617 +
618 +/*
619 + * Find variables with <devpath> from flash. 'base' points to the beginning
620 + * of the table upon enter and to the end of the table upon exit when success.
621 + * Return 0 on success, nonzero on error.
622 + */
623 +static int
624 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
625 +{
626 + char *vp = *base;
627 + char *flash;
628 + int err;
629 + char *s;
630 + uint l, dl, copy_len;
631 +
632 + /* allocate memory and read in flash */
633 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
634 + return BCME_NOMEM;
635 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
636 + goto exit;
637 +
638 + /* grab vars with the <devpath> prefix in name */
639 + dl = strlen(devpath);
640 + for (s = flash; s && *s; s += l + 1) {
641 + l = strlen(s);
642 +
643 + /* skip non-matching variable */
644 + if (strncmp(s, devpath, dl))
645 + continue;
646 +
647 + /* is there enough room to copy? */
648 + copy_len = l - dl + 1;
649 + if (len < copy_len) {
650 + err = BCME_BUFTOOSHORT;
651 + goto exit;
652 + }
653 +
654 + /* no prefix, just the name=value */
655 + strcpy(vp, &s[dl]);
656 + vp += copy_len;
657 + len -= copy_len;
658 + }
659 +
660 + /* add null string as terminator */
661 + if (len < 1) {
662 + err = BCME_BUFTOOSHORT;
663 + goto exit;
664 + }
665 + *vp++ = '\0';
666 +
667 + *base = vp;
668 +
669 +exit: MFREE(osh, flash, NVRAM_SPACE);
670 + return err;
671 +}
672 +
673 +/*
674 + * Initialize nonvolatile variable table from flash.
675 + * Return 0 on success, nonzero on error.
676 + */
677 +static int
678 +initvars_flash_sb(void *sbh, char **vars, uint *count)
679 +{
680 + osl_t *osh = sb_osh(sbh);
681 + char devpath[SB_DEVPATH_BUFSZ];
682 + char *vp, *base;
683 + int err;
684 +
685 + ASSERT(vars);
686 + ASSERT(count);
687 +
688 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
689 + return err;
690 +
691 + base = vp = MALLOC(osh, VARS_MAX);
692 + ASSERT(vp);
693 + if (!vp)
694 + return BCME_NOMEM;
695 +
696 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
697 + goto err;
698 +
699 + err = initvars_table(osh, base, vp, vars, count);
700 +
701 +err: MFREE(osh, base, VARS_MAX);
702 + return err;
703 +}
704 +
705 +#ifdef WLTEST
706 +char mfgsromvars[256];
707 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
708 + "et0macaddr=00:11:22:33:44:52\0"
709 + "et1macaddr=00:11:22:33:44:53\0"
710 + "boardtype=0xffff\0"
711 + "boardrev=0x10\0"
712 + "boardflags=8\0"
713 + "sromrev=2\0"
714 + "aa2g=3";
715 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
716 +#endif /* WL_TEST */
717 +
718 +/*
719 + * Initialize nonvolatile variable table from sprom.
720 + * Return 0 on success, nonzero on error.
721 + */
722 +static int
723 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
724 +{
725 + uint16 w, *b;
726 + uint8 sromrev = 0;
727 + struct ether_addr ea;
728 + char eabuf[32];
729 + uint32 w32;
730 + int woff, i;
731 + char *vp, *base;
732 + osl_t *osh = sb_osh(sbh);
733 + bool flash = FALSE;
734 + char name[SB_DEVPATH_BUFSZ+16], *value;
735 + char devpath[SB_DEVPATH_BUFSZ];
736 + int err;
737 +
738 + /*
739 + * Apply CRC over SROM content regardless SROM is present or not,
740 + * and use variable <devpath>sromrev's existance in flash to decide
741 + * if we should return an error when CRC fails or read SROM variables
742 + * from flash.
743 + */
744 + b = MALLOC(osh, SROM_MAX);
745 + ASSERT(b);
746 + if (!b)
747 + return -2;
748 +
749 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
750 + 64, TRUE);
751 + if (err == 0) {
752 + /* srom is good and is rev < 4 */
753 + /* top word of sprom contains version and crc8 */
754 + sromrev = b[63] & 0xff;
755 + /* bcm4401 sroms misprogrammed */
756 + if (sromrev == 0x10)
757 + sromrev = 1;
758 + } else if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
759 + /* If sromrev >= 4, read more */
760 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
761 + SROM4_WORDS, TRUE);
762 + sromrev = b[SROM4_WORDS - 1] & 0xff;
763 + }
764 +
765 + if (err) {
766 +#ifdef WLTEST
767 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
768 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
769 + if (w32 & SPROM_OTPIN_USE) {
770 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
771 + vp = base = mfgsromvars;
772 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
773 + BS_ERROR(("setting the devid to be 4311\n"));
774 + vp += sprintf(vp, "devid=0x4311");
775 + vp++;
776 + }
777 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
778 + vp += MFGSROM_DEFVARSLEN;
779 + goto varsdone;
780 + } else {
781 + BS_ERROR(("srom crc failed with SPROM....\n"));
782 +#endif /* WLTEST */
783 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
784 + return err;
785 + sprintf(name, "%ssromrev", devpath);
786 + if (!(value = getvar(NULL, name)))
787 + return (-1);
788 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
789 + flash = TRUE;
790 +#ifdef WLTEST
791 + }
792 +#endif /* WLTEST */
793 + }
794 +
795 + /* srom version check */
796 + if (sromrev > 4)
797 + return (-2);
798 +
799 + ASSERT(vars);
800 + ASSERT(count);
801 +
802 + base = vp = MALLOC(osh, VARS_MAX);
803 + ASSERT(vp);
804 + if (!vp)
805 + return -2;
806 +
807 + /* read variables from flash */
808 + if (flash) {
809 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
810 + goto err;
811 + goto varsdone;
812 + }
813 +
814 + vp += sprintf(vp, "sromrev=%d", sromrev);
815 + vp++;
816 +
817 + if (sromrev >= 4) {
818 + uint path, pathbase;
819 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
820 + SROM4_PATH2, SROM4_PATH3};
821 +
822 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
823 + vp++;
824 +
825 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
826 + vp++;
827 +
828 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
829 + vp++;
830 +
831 + /* The macaddr */
832 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
833 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
834 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
835 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
836 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
837 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
838 + bcm_ether_ntoa(&ea, eabuf);
839 + vp += sprintf(vp, "macaddr=%s", eabuf);
840 + vp++;
841 +
842 + w = b[SROM4_CCODE];
843 + if (w == 0)
844 + vp += sprintf(vp, "ccode=");
845 + else
846 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
847 + vp++;
848 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
849 + vp++;
850 +
851 + w = b[SROM4_LEDBH10];
852 + if ((w != 0) && (w != 0xffff)) {
853 + /* ledbh0 */
854 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
855 + vp++;
856 +
857 + /* ledbh1 */
858 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
859 + vp++;
860 + }
861 + w = b[SROM4_LEDBH32];
862 + if ((w != 0) && (w != 0xffff)) {
863 + /* ledbh2 */
864 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
865 + vp++;
866 +
867 + /* ledbh3 */
868 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
869 + vp++;
870 + }
871 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
872 + w = b[SROM4_LEDDC];
873 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
874 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
875 + vp += sprintf(vp, "leddc=%d", w32);
876 + vp++;
877 +
878 + w = b[SROM4_AA];
879 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
880 + vp++;
881 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
882 + vp++;
883 +
884 + w = b[SROM4_AG10];
885 + vp += sprintf(vp, "ag0=%d", w & 0xff);
886 + vp++;
887 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
888 + vp++;
889 + w = b[SROM4_AG32];
890 + vp += sprintf(vp, "ag2=%d", w & 0xff);
891 + vp++;
892 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
893 + vp++;
894 +
895 + /* Fixed power indices when power control is disabled */
896 + for (i = 0; i < 2; i++) {
897 + w = b[SROM4_TXPID2G + i];
898 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
899 + vp++;
900 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
901 + vp++;
902 + w = b[SROM4_TXPID5G + i];
903 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
904 + vp++;
905 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
906 + vp++;
907 + w = b[SROM4_TXPID5GL + i];
908 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
909 + vp++;
910 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
911 + vp++;
912 + w = b[SROM4_TXPID5GH + i];
913 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
914 + vp++;
915 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
916 + vp++;
917 + }
918 +
919 + /* Per path variables */
920 + for (path = 0; path < MAX_PATH; path++) {
921 + pathbase = pathbases[path];
922 + w = b[pathbase + SROM4_2G_ITT_MAXP];
923 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
924 + vp++;
925 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
926 + vp++;
927 +
928 + for (i = 0; i < 4; i++) {
929 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
930 + b[pathbase + SROM4_2G_PA + i]);
931 + vp++;
932 + }
933 +
934 + w = b[pathbase + SROM4_5G_ITT_MAXP];
935 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
936 + vp++;
937 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
938 + vp++;
939 +
940 + w = b[pathbase + SROM4_5GLH_MAXP];
941 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
942 + vp++;
943 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
944 + vp++;
945 +
946 + for (i = 0; i < 4; i++) {
947 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
948 + b[pathbase + SROM4_5G_PA + i]);
949 + vp++;
950 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
951 + b[pathbase + SROM4_5GL_PA + i]);
952 + vp++;
953 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
954 + b[pathbase + SROM4_5GH_PA + i]);
955 + vp++;
956 + }
957 + }
958 +
959 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
960 + vp++;
961 +
962 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
963 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
964 + vp++;
965 +
966 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
967 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
968 + vp++;
969 +
970 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
971 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
972 + vp++;
973 +
974 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
975 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
976 + vp++;
977 +
978 + for (i = 0; i < 8; i++) {
979 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
980 + vp++;
981 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
982 + vp++;
983 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
984 + vp++;
985 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
986 + vp++;
987 + }
988 +
989 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
990 + vp++;
991 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
992 + vp++;
993 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
994 + vp++;
995 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
996 + vp++;
997 +
998 + goto done;
999 + }
1000 + if (sromrev >= 3) {
1001 + /* New section takes over the 3th hardware function space */
1002 +
1003 + /* Words 22+23 are 11a (mid) ofdm power offsets */
1004 + w32 = ((uint32)b[23] << 16) | b[22];
1005 + vp += sprintf(vp, "ofdmapo=%d", w32);
1006 + vp++;
1007 +
1008 + /* Words 24+25 are 11a (low) ofdm power offsets */
1009 + w32 = ((uint32)b[25] << 16) | b[24];
1010 + vp += sprintf(vp, "ofdmalpo=%d", w32);
1011 + vp++;
1012 +
1013 + /* Words 26+27 are 11a (high) ofdm power offsets */
1014 + w32 = ((uint32)b[27] << 16) | b[26];
1015 + vp += sprintf(vp, "ofdmahpo=%d", w32);
1016 + vp++;
1017 +
1018 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
1019 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
1020 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
1021 + vp += sprintf(vp, "leddc=%d", w32);
1022 +
1023 + vp++;
1024 + }
1025 +
1026 + if (sromrev >= 2) {
1027 + /* New section takes over the 4th hardware function space */
1028 +
1029 + /* Word 29 is max power 11a high/low */
1030 + w = b[29];
1031 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
1032 + vp++;
1033 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
1034 + vp++;
1035 +
1036 + /* Words 30-32 set the 11alow pa settings,
1037 + * 33-35 are the 11ahigh ones.
1038 + */
1039 + for (i = 0; i < 3; i++) {
1040 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
1041 + vp++;
1042 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
1043 + vp++;
1044 + }
1045 + w = b[59];
1046 + if (w == 0)
1047 + vp += sprintf(vp, "ccode=");
1048 + else
1049 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
1050 + vp++;
1051 +
1052 + }
1053 +
1054 + /* parameter section of sprom starts at byte offset 72 */
1055 + woff = 72/2;
1056 +
1057 + /* first 6 bytes are il0macaddr */
1058 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1059 + ea.octet[1] = b[woff] & 0xff;
1060 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1061 + ea.octet[3] = b[woff+1] & 0xff;
1062 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1063 + ea.octet[5] = b[woff+2] & 0xff;
1064 + woff += 3;
1065 + bcm_ether_ntoa(&ea, eabuf);
1066 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1067 + vp++;
1068 +
1069 + /* next 6 bytes are et0macaddr */
1070 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1071 + ea.octet[1] = b[woff] & 0xff;
1072 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1073 + ea.octet[3] = b[woff+1] & 0xff;
1074 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1075 + ea.octet[5] = b[woff+2] & 0xff;
1076 + woff += 3;
1077 + bcm_ether_ntoa(&ea, eabuf);
1078 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1079 + vp++;
1080 +
1081 + /* next 6 bytes are et1macaddr */
1082 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1083 + ea.octet[1] = b[woff] & 0xff;
1084 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1085 + ea.octet[3] = b[woff+1] & 0xff;
1086 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1087 + ea.octet[5] = b[woff+2] & 0xff;
1088 + woff += 3;
1089 + bcm_ether_ntoa(&ea, eabuf);
1090 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1091 + vp++;
1092 +
1093 + /*
1094 + * Enet phy settings one or two singles or a dual
1095 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1096 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1097 + * Bit 14 : Mdio for enet0
1098 + * Bit 15 : Mdio for enet1
1099 + */
1100 + w = b[woff];
1101 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1102 + vp++;
1103 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1104 + vp++;
1105 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1106 + vp++;
1107 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1108 + vp++;
1109 +
1110 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1111 + w = b[46];
1112 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1113 + vp++;
1114 +
1115 + if (sromrev > 1)
1116 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1117 + else
1118 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1119 + vp++;
1120 +
1121 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1122 + vp++;
1123 +
1124 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1125 + vp++;
1126 +
1127 + /* Words 47-49 set the (wl) pa settings */
1128 + woff = 47;
1129 +
1130 + for (i = 0; i < 3; i++) {
1131 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1132 + vp++;
1133 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1134 + vp++;
1135 + }
1136 +
1137 + /*
1138 + * Words 50-51 set the customer-configured wl led behavior.
1139 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1140 + * LED behavior values defined in wlioctl.h .
1141 + */
1142 + w = b[50];
1143 + if ((w != 0) && (w != 0xffff)) {
1144 + /* ledbh0 */
1145 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1146 + vp++;
1147 +
1148 + /* ledbh1 */
1149 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1150 + vp++;
1151 + }
1152 + w = b[51];
1153 + if ((w != 0) && (w != 0xffff)) {
1154 + /* ledbh2 */
1155 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1156 + vp++;
1157 +
1158 + /* ledbh */
1159 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1160 + vp++;
1161 + }
1162 +
1163 + /* Word 52 is max power 0/1 */
1164 + w = b[52];
1165 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1166 + vp++;
1167 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1168 + vp++;
1169 +
1170 + /* Word 56 is idle tssi target 0/1 */
1171 + w = b[56];
1172 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1173 + vp++;
1174 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1175 + vp++;
1176 +
1177 + /* Word 57 is boardflags, if not programmed make it zero */
1178 + w32 = (uint32)b[57];
1179 + if (w32 == 0xffff) w32 = 0;
1180 + if (sromrev > 1) {
1181 + /* Word 28 is the high bits of boardflags */
1182 + w32 |= (uint32)b[28] << 16;
1183 + }
1184 + vp += sprintf(vp, "boardflags=%d", w32);
1185 + vp++;
1186 +
1187 + /* Word 58 is antenna gain 0/1 */
1188 + w = b[58];
1189 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1190 + vp++;
1191 +
1192 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1193 + vp++;
1194 +
1195 + if (sromrev == 1) {
1196 + /* set the oem string */
1197 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1198 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1199 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1200 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1201 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1202 + vp++;
1203 + } else if (sromrev == 2) {
1204 + /* Word 60 OFDM tx power offset from CCK level */
1205 + /* OFDM Power Offset - opo */
1206 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1207 + vp++;
1208 + } else {
1209 + /* Word 60: cck power offsets */
1210 + vp += sprintf(vp, "cckpo=%d", b[60]);
1211 + vp++;
1212 +
1213 + /* Words 61+62: 11g ofdm power offsets */
1214 + w32 = ((uint32)b[62] << 16) | b[61];
1215 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1216 + vp++;
1217 + }
1218 +
1219 + /* final nullbyte terminator */
1220 +done: *vp++ = '\0';
1221 +
1222 + ASSERT((vp - base) <= VARS_MAX);
1223 +
1224 +varsdone:
1225 + err = initvars_table(osh, base, vp, vars, count);
1226 +
1227 +err:
1228 +#ifdef WLTEST
1229 + if (base != mfgsromvars)
1230 +#endif
1231 + MFREE(osh, base, VARS_MAX);
1232 + MFREE(osh, b, SROM_MAX);
1233 + return err;
1234 +}
1235 +
1236 +/*
1237 + * Read the cis and call parsecis to initialize the vars.
1238 + * Return 0 on success, nonzero on error.
1239 + */
1240 +static int
1241 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1242 +{
1243 + uint8 *cis = NULL;
1244 + int rc;
1245 + uint data_sz;
1246 +
1247 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1248 +
1249 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1250 + return (-2);
1251 +
1252 + if (sb_pcmciarev(sbh) == 1) {
1253 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1254 + MFREE(osh, cis, data_sz);
1255 + return (-1);
1256 + }
1257 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1258 + ltoh16_buf((uint16 *)cis, data_sz);
1259 + } else
1260 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1261 +
1262 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1263 +
1264 + MFREE(osh, cis, data_sz);
1265 +
1266 + return (rc);
1267 +}
1268 +
1269 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1270 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1271 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-04-28 00:34:02.000000000 +0200
1272 @@ -0,0 +1,247 @@
1273 +/*
1274 + * Misc useful OS-independent routines.
1275 + *
1276 + * Copyright 2006, Broadcom Corporation
1277 + * All Rights Reserved.
1278 + *
1279 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1280 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1281 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1282 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1283 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1284 + */
1285 +
1286 +#include <typedefs.h>
1287 +#include <bcmdefs.h>
1288 +#include <stdarg.h>
1289 +#include <bcmutils.h>
1290 +#include <osl.h>
1291 +#include <sbutils.h>
1292 +#include <bcmnvram.h>
1293 +#include <bcmendian.h>
1294 +#include <bcmdevs.h>
1295 +
1296 +unsigned char bcm_ctype[] = {
1297 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1298 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1299 + _BCM_C, /* 8-15 */
1300 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1301 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1302 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1303 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1304 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1305 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1306 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1307 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1308 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1309 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1310 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1311 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1312 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1313 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1314 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1315 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1316 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1317 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1318 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1319 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1320 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1321 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1322 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1323 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1324 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1325 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1326 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1327 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1328 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1329 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1330 +};
1331 +
1332 +
1333 +ulong
1334 +bcm_strtoul(char *cp, char **endp, uint base)
1335 +{
1336 + ulong result, value;
1337 + bool minus;
1338 +
1339 + minus = FALSE;
1340 +
1341 + while (bcm_isspace(*cp))
1342 + cp++;
1343 +
1344 + if (cp[0] == '+')
1345 + cp++;
1346 + else if (cp[0] == '-') {
1347 + minus = TRUE;
1348 + cp++;
1349 + }
1350 +
1351 + if (base == 0) {
1352 + if (cp[0] == '0') {
1353 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1354 + base = 16;
1355 + cp = &cp[2];
1356 + } else {
1357 + base = 8;
1358 + cp = &cp[1];
1359 + }
1360 + } else
1361 + base = 10;
1362 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1363 + cp = &cp[2];
1364 + }
1365 +
1366 + result = 0;
1367 +
1368 + while (bcm_isxdigit(*cp) &&
1369 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1370 + result = result*base + value;
1371 + cp++;
1372 + }
1373 +
1374 + if (minus)
1375 + result = (ulong)(result * -1);
1376 +
1377 + if (endp)
1378 + *endp = (char *)cp;
1379 +
1380 + return (result);
1381 +}
1382 +
1383 +uchar
1384 +bcm_toupper(uchar c)
1385 +{
1386 + if (bcm_islower(c))
1387 + c -= 'a'-'A';
1388 + return (c);
1389 +}
1390 +
1391 +char*
1392 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1393 +{
1394 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1395 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1396 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1397 + return (buf);
1398 +}
1399 +
1400 +
1401 +/*
1402 + * Search the name=value vars for a specific one and return its value.
1403 + * Returns NULL if not found.
1404 + */
1405 +char*
1406 +getvar(char *vars, char *name)
1407 +{
1408 + char *s;
1409 + int len;
1410 +
1411 + len = strlen(name);
1412 +
1413 + /* first look in vars[] */
1414 + for (s = vars; s && *s;) {
1415 + /* CSTYLED */
1416 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1417 + return (&s[len+1]);
1418 +
1419 + while (*s++)
1420 + ;
1421 + }
1422 +
1423 + /* then query nvram */
1424 + return (nvram_get(name));
1425 +}
1426 +
1427 +/*
1428 + * Search the vars for a specific one and return its value as
1429 + * an integer. Returns 0 if not found.
1430 + */
1431 +int
1432 +getintvar(char *vars, char *name)
1433 +{
1434 + char *val;
1435 +
1436 + if ((val = getvar(vars, name)) == NULL)
1437 + return (0);
1438 +
1439 + return (bcm_strtoul(val, NULL, 0));
1440 +}
1441 +
1442 +
1443 +/*******************************************************************************
1444 + * crc8
1445 + *
1446 + * Computes a crc8 over the input data using the polynomial:
1447 + *
1448 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1449 + *
1450 + * The caller provides the initial value (either CRC8_INIT_VALUE
1451 + * or the previous returned value) to allow for processing of
1452 + * discontiguous blocks of data. When generating the CRC the
1453 + * caller is responsible for complementing the final return value
1454 + * and inserting it into the byte stream. When checking, a final
1455 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1456 + *
1457 + * Reference: Dallas Semiconductor Application Note 27
1458 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1459 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1460 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1461 + *
1462 + * ****************************************************************************
1463 + */
1464 +
1465 +static uint8 crc8_table[256] = {
1466 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1467 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1468 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1469 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1470 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1471 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1472 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1473 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1474 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1475 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1476 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1477 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1478 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1479 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1480 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1481 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1482 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1483 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1484 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1485 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1486 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1487 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1488 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1489 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1490 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1491 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1492 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1493 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1494 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1495 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1496 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1497 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1498 +};
1499 +
1500 +#define CRC_INNER_LOOP(n, c, x) \
1501 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1502 +
1503 +uint8
1504 +hndcrc8(
1505 + uint8 *pdata, /* pointer to array of data to process */
1506 + uint nbytes, /* number of input data bytes to process */
1507 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1508 +)
1509 +{
1510 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1511 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1512 + */
1513 + while (nbytes-- > 0)
1514 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1515 +
1516 + return crc;
1517 +}
1518 +
1519 +
1520 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1521 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1522 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-04-27 19:24:19.000000000 +0200
1523 @@ -0,0 +1,234 @@
1524 +/*
1525 + * NVRAM variable manipulation (Linux kernel half)
1526 + *
1527 + * Copyright 2001-2003, Broadcom Corporation
1528 + * All Rights Reserved.
1529 + *
1530 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1531 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1532 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1533 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1534 + *
1535 + * $Id$
1536 + */
1537 +
1538 +#include <linux/config.h>
1539 +#include <linux/init.h>
1540 +#include <linux/module.h>
1541 +#include <linux/kernel.h>
1542 +#include <linux/string.h>
1543 +#include <asm/io.h>
1544 +#include <asm/uaccess.h>
1545 +
1546 +#include <typedefs.h>
1547 +#include <osl.h>
1548 +#include <bcmendian.h>
1549 +#include <bcmutils.h>
1550 +
1551 +#define NVRAM_SIZE (0x1ff0)
1552 +static char _nvdata[NVRAM_SIZE] __initdata;
1553 +static char _valuestr[256] __initdata;
1554 +
1555 +/*
1556 + * TLV types. These codes are used in the "type-length-value"
1557 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1558 + *
1559 + * The layout of the flash/nvram is as follows:
1560 + *
1561 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1562 + *
1563 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1564 + * The "length" field marks the length of the data section, not
1565 + * including the type and length fields.
1566 + *
1567 + * Environment variables are stored as follows:
1568 + *
1569 + * <type_env> <length> <flags> <name> = <value>
1570 + *
1571 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1572 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1573 + *
1574 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1575 + * indicates the size of the length field.
1576 + *
1577 + * Flags are from the constants below:
1578 + *
1579 + */
1580 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1581 +#define ENV_LENGTH_8BITS 0x01
1582 +
1583 +#define ENV_TYPE_USER 0x80
1584 +
1585 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1586 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1587 +
1588 +/*
1589 + * The actual TLV types we support
1590 + */
1591 +
1592 +#define ENV_TLV_TYPE_END 0x00
1593 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1594 +
1595 +/*
1596 + * Environment variable flags
1597 + */
1598 +
1599 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1600 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1601 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1602 +
1603 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1604 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1605 +
1606 +
1607 +/* *********************************************************************
1608 + * _nvram_read(buffer,offset,length)
1609 + *
1610 + * Read data from the NVRAM device
1611 + *
1612 + * Input parameters:
1613 + * buffer - destination buffer
1614 + * offset - offset of data to read
1615 + * length - number of bytes to read
1616 + *
1617 + * Return value:
1618 + * number of bytes read, or <0 if error occured
1619 + ********************************************************************* */
1620 +static int
1621 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1622 +{
1623 + int i;
1624 + if (offset > NVRAM_SIZE)
1625 + return -1;
1626 +
1627 + for ( i = 0; i < length; i++) {
1628 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1629 + }
1630 + return length;
1631 +}
1632 +
1633 +
1634 +static char*
1635 +_strnchr(const char *dest,int c,size_t cnt)
1636 +{
1637 + while (*dest && (cnt > 0)) {
1638 + if (*dest == c) return (char *) dest;
1639 + dest++;
1640 + cnt--;
1641 + }
1642 + return NULL;
1643 +}
1644 +
1645 +
1646 +
1647 +/*
1648 + * Core support API: Externally visible.
1649 + */
1650 +
1651 +/*
1652 + * Get the value of an NVRAM variable
1653 + * @param name name of variable to get
1654 + * @return value of variable or NULL if undefined
1655 + */
1656 +
1657 +char*
1658 +cfe_env_get(unsigned char *nv_buf, char* name)
1659 +{
1660 + int size;
1661 + unsigned char *buffer;
1662 + unsigned char *ptr;
1663 + unsigned char *envval;
1664 + unsigned int reclen;
1665 + unsigned int rectype;
1666 + int offset;
1667 + int flg;
1668 +
1669 + size = NVRAM_SIZE;
1670 + buffer = &_nvdata[0];
1671 +
1672 + ptr = buffer;
1673 + offset = 0;
1674 +
1675 + /* Read the record type and length */
1676 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1677 + goto error;
1678 + }
1679 +
1680 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1681 +
1682 + /* Adjust pointer for TLV type */
1683 + rectype = *(ptr);
1684 + offset++;
1685 + size--;
1686 +
1687 + /*
1688 + * Read the length. It can be either 1 or 2 bytes
1689 + * depending on the code
1690 + */
1691 + if (rectype & ENV_LENGTH_8BITS) {
1692 + /* Read the record type and length - 8 bits */
1693 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1694 + goto error;
1695 + }
1696 + reclen = *(ptr);
1697 + size--;
1698 + offset++;
1699 + }
1700 + else {
1701 + /* Read the record type and length - 16 bits, MSB first */
1702 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1703 + goto error;
1704 + }
1705 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1706 + size -= 2;
1707 + offset += 2;
1708 + }
1709 +
1710 + if (reclen > size)
1711 + break; /* should not happen, bad NVRAM */
1712 +
1713 + switch (rectype) {
1714 + case ENV_TLV_TYPE_ENV:
1715 + /* Read the TLV data */
1716 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1717 + goto error;
1718 + flg = *ptr++;
1719 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1720 + if (envval) {
1721 + *envval++ = '\0';
1722 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1723 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1724 +#if 0
1725 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1726 +#endif
1727 + if(!strcmp(ptr, name)){
1728 + return _valuestr;
1729 + }
1730 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1731 + return _valuestr;
1732 + }
1733 + break;
1734 +
1735 + default:
1736 + /* Unknown TLV type, skip it. */
1737 + break;
1738 + }
1739 +
1740 + /*
1741 + * Advance to next TLV
1742 + */
1743 +
1744 + size -= (int)reclen;
1745 + offset += reclen;
1746 +
1747 + /* Read the next record type */
1748 + ptr = buffer;
1749 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1750 + goto error;
1751 + }
1752 +
1753 +error:
1754 + return NULL;
1755 +
1756 +}
1757 +
1758 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1759 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1760 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-04-27 19:24:19.000000000 +0200
1761 @@ -0,0 +1,33 @@
1762 +#
1763 +# Makefile for Broadcom BCM947XX boards
1764 +#
1765 +# Copyright 2001-2003, Broadcom Corporation
1766 +# All Rights Reserved.
1767 +#
1768 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1769 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1770 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1771 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1772 +#
1773 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1774 +#
1775 +
1776 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1777 +SYSTEM ?= $(TOPDIR)/vmlinux
1778 +
1779 +all: vmlinuz
1780 +
1781 +# Don't build dependencies, this may die if $(CC) isn't gcc
1782 +dep:
1783 +
1784 +# Create a gzipped version named vmlinuz for compatibility
1785 +vmlinuz: piggy
1786 + gzip -c9 $< > $@
1787 +
1788 +piggy: $(SYSTEM)
1789 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1790 +
1791 +mrproper: clean
1792 +
1793 +clean:
1794 + rm -f vmlinuz piggy
1795 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1796 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1797 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-04-28 02:57:34.000000000 +0200
1798 @@ -0,0 +1,62 @@
1799 +#include <linux/module.h>
1800 +
1801 +#define _export(n) \
1802 + void n(void); \
1803 + EXPORT_SYMBOL(n);
1804 +
1805 +_export(bcm947xx_sbh)
1806 +
1807 +_export(sb_attach)
1808 +_export(sb_boardtype)
1809 +_export(sb_boardvendor)
1810 +_export(sb_btcgpiowar)
1811 +_export(sb_bus)
1812 +_export(sb_chip)
1813 +_export(sb_chiprev)
1814 +_export(sb_chipcrev)
1815 +_export(sb_chippkg)
1816 +_export(sb_clkctl_clk)
1817 +_export(sb_clkctl_fast_pwrup_delay)
1818 +_export(sb_clkctl_init)
1819 +_export(sb_clkctl_xtal)
1820 +_export(sb_core_disable)
1821 +_export(sb_core_reset)
1822 +_export(sb_core_tofixup)
1823 +_export(sb_coreflags)
1824 +_export(sb_coreflagshi)
1825 +_export(sb_coreidx)
1826 +_export(sb_corerev)
1827 +_export(sb_coreunit)
1828 +_export(sb_detach)
1829 +_export(sb_deviceremoved)
1830 +_export(sb_gpiocontrol)
1831 +_export(sb_gpioled)
1832 +_export(sb_gpioin)
1833 +_export(sb_gpioout)
1834 +_export(sb_gpioouten)
1835 +_export(sb_gpiotimerval)
1836 +_export(sb_iscoreup)
1837 +_export(sb_pci_setup)
1838 +_export(sb_pcirev)
1839 +_export(sb_pcmcia_init)
1840 +_export(sb_pcmciarev)
1841 +_export(sb_register_intr_callback)
1842 +_export(sb_setcore)
1843 +_export(sb_war16165)
1844 +_export(sb_osh)
1845 +
1846 +_export(getvar)
1847 +_export(getintvar)
1848 +_export(bcm_strtoul)
1849 +_export(bcm_ctype)
1850 +_export(bcm_toupper)
1851 +_export(bcm_ether_ntoa)
1852 +
1853 +_export(nvram_get)
1854 +_export(nvram_getall)
1855 +_export(nvram_set)
1856 +_export(nvram_unset)
1857 +_export(nvram_commit)
1858 +
1859 +_export(srom_read)
1860 +_export(srom_write)
1861 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
1862 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
1863 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-04-27 19:24:19.000000000 +0200
1864 @@ -0,0 +1,15 @@
1865 +#
1866 +# Makefile for the BCM947xx specific kernel interface routines
1867 +# under Linux.
1868 +#
1869 +
1870 +.S.s:
1871 + $(CPP) $(AFLAGS) $< -o $*.s
1872 +.S.o:
1873 + $(CC) $(AFLAGS) -c $< -o $*.o
1874 +
1875 +O_TARGET := brcm.o
1876 +
1877 +obj-y := int-handler.o irq.o
1878 +
1879 +include $(TOPDIR)/Rules.make
1880 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1881 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1882 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-04-27 19:24:19.000000000 +0200
1883 @@ -0,0 +1,51 @@
1884 +/*
1885 + * Generic interrupt handler for Broadcom MIPS boards
1886 + *
1887 + * Copyright 2004, Broadcom Corporation
1888 + * All Rights Reserved.
1889 + *
1890 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1891 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1892 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1893 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1894 + *
1895 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1896 + */
1897 +
1898 +#include <linux/config.h>
1899 +
1900 +#include <asm/asm.h>
1901 +#include <asm/mipsregs.h>
1902 +#include <asm/regdef.h>
1903 +#include <asm/stackframe.h>
1904 +
1905 +/*
1906 + * MIPS IRQ Source
1907 + * -------- ------
1908 + * 0 Software (ignored)
1909 + * 1 Software (ignored)
1910 + * 2 Combined hardware interrupt (hw0)
1911 + * 3 Hardware
1912 + * 4 Hardware
1913 + * 5 Hardware
1914 + * 6 Hardware
1915 + * 7 R4k timer
1916 + */
1917 +
1918 + .text
1919 + .set noreorder
1920 + .set noat
1921 + .align 5
1922 + NESTED(brcmIRQ, PT_SIZE, sp)
1923 + SAVE_ALL
1924 + CLI
1925 + .set at
1926 + .set noreorder
1927 +
1928 + jal brcm_irq_dispatch
1929 + move a0, sp
1930 +
1931 + j ret_from_irq
1932 + nop
1933 +
1934 + END(brcmIRQ)
1935 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1936 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1937 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-04-27 19:24:19.000000000 +0200
1938 @@ -0,0 +1,130 @@
1939 +/*
1940 + * Generic interrupt control functions for Broadcom MIPS boards
1941 + *
1942 + * Copyright 2004, Broadcom Corporation
1943 + * All Rights Reserved.
1944 + *
1945 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1946 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1947 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1948 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1949 + *
1950 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1951 + */
1952 +
1953 +#include <linux/config.h>
1954 +#include <linux/init.h>
1955 +#include <linux/kernel.h>
1956 +#include <linux/types.h>
1957 +#include <linux/interrupt.h>
1958 +#include <linux/irq.h>
1959 +
1960 +#include <asm/irq.h>
1961 +#include <asm/mipsregs.h>
1962 +#include <asm/gdb-stub.h>
1963 +
1964 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1965 +
1966 +extern asmlinkage void brcmIRQ(void);
1967 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1968 +
1969 +void
1970 +brcm_irq_dispatch(struct pt_regs *regs)
1971 +{
1972 + u32 cause;
1973 +
1974 + cause = read_c0_cause() &
1975 + read_c0_status() &
1976 + CAUSEF_IP;
1977 +
1978 +#ifdef CONFIG_KERNPROF
1979 + change_c0_status(cause | 1, 1);
1980 +#else
1981 + clear_c0_status(cause);
1982 +#endif
1983 +
1984 + if (cause & CAUSEF_IP7)
1985 + do_IRQ(7, regs);
1986 + if (cause & CAUSEF_IP2)
1987 + do_IRQ(2, regs);
1988 + if (cause & CAUSEF_IP3)
1989 + do_IRQ(3, regs);
1990 + if (cause & CAUSEF_IP4)
1991 + do_IRQ(4, regs);
1992 + if (cause & CAUSEF_IP5)
1993 + do_IRQ(5, regs);
1994 + if (cause & CAUSEF_IP6)
1995 + do_IRQ(6, regs);
1996 +}
1997 +
1998 +static void
1999 +enable_brcm_irq(unsigned int irq)
2000 +{
2001 + if (irq < 8)
2002 + set_c0_status(1 << (irq + 8));
2003 + else
2004 + set_c0_status(IE_IRQ0);
2005 +}
2006 +
2007 +static void
2008 +disable_brcm_irq(unsigned int irq)
2009 +{
2010 + if (irq < 8)
2011 + clear_c0_status(1 << (irq + 8));
2012 + else
2013 + clear_c0_status(IE_IRQ0);
2014 +}
2015 +
2016 +static void
2017 +ack_brcm_irq(unsigned int irq)
2018 +{
2019 + /* Already done in brcm_irq_dispatch */
2020 +}
2021 +
2022 +static unsigned int
2023 +startup_brcm_irq(unsigned int irq)
2024 +{
2025 + enable_brcm_irq(irq);
2026 +
2027 + return 0; /* never anything pending */
2028 +}
2029 +
2030 +static void
2031 +end_brcm_irq(unsigned int irq)
2032 +{
2033 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
2034 + enable_brcm_irq(irq);
2035 +}
2036 +
2037 +static struct hw_interrupt_type brcm_irq_type = {
2038 + typename: "MIPS",
2039 + startup: startup_brcm_irq,
2040 + shutdown: disable_brcm_irq,
2041 + enable: enable_brcm_irq,
2042 + disable: disable_brcm_irq,
2043 + ack: ack_brcm_irq,
2044 + end: end_brcm_irq,
2045 + NULL
2046 +};
2047 +
2048 +void __init
2049 +init_IRQ(void)
2050 +{
2051 + int i;
2052 +
2053 + for (i = 0; i < NR_IRQS; i++) {
2054 + irq_desc[i].status = IRQ_DISABLED;
2055 + irq_desc[i].action = 0;
2056 + irq_desc[i].depth = 1;
2057 + irq_desc[i].handler = &brcm_irq_type;
2058 + }
2059 +
2060 + set_except_vector(0, brcmIRQ);
2061 + change_c0_status(ST0_IM, ALLINTS);
2062 +
2063 +#ifdef CONFIG_REMOTE_DEBUG
2064 + printk("Breaking into debugger...\n");
2065 + set_debug_traps();
2066 + breakpoint();
2067 +#endif
2068 +}
2069 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2070 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2071 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-04-27 23:09:33.000000000 +0200
2072 @@ -0,0 +1,159 @@
2073 +/*
2074 + * GPIO char driver
2075 + *
2076 + * Copyright 2005, Broadcom Corporation
2077 + * All Rights Reserved.
2078 + *
2079 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2080 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2081 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2082 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2083 + *
2084 + * $Id$
2085 + */
2086 +
2087 +#include <linux/module.h>
2088 +#include <linux/init.h>
2089 +#include <linux/fs.h>
2090 +#include <linux/miscdevice.h>
2091 +#include <asm/uaccess.h>
2092 +
2093 +#include <typedefs.h>
2094 +#include <osl.h>
2095 +#include <bcmutils.h>
2096 +#include <sbutils.h>
2097 +#include <bcmdevs.h>
2098 +
2099 +static sb_t *gpio_sbh;
2100 +static int gpio_major;
2101 +static devfs_handle_t gpio_dir;
2102 +static struct {
2103 + char *name;
2104 + devfs_handle_t handle;
2105 +} gpio_file[] = {
2106 + { "in", NULL },
2107 + { "out", NULL },
2108 + { "outen", NULL },
2109 + { "control", NULL }
2110 +};
2111 +
2112 +static int
2113 +gpio_open(struct inode *inode, struct file * file)
2114 +{
2115 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2116 + return -ENODEV;
2117 +
2118 + MOD_INC_USE_COUNT;
2119 + return 0;
2120 +}
2121 +
2122 +static int
2123 +gpio_release(struct inode *inode, struct file * file)
2124 +{
2125 + MOD_DEC_USE_COUNT;
2126 + return 0;
2127 +}
2128 +
2129 +static ssize_t
2130 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2131 +{
2132 + u32 val;
2133 +
2134 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2135 + case 0:
2136 + val = sb_gpioin(gpio_sbh);
2137 + break;
2138 + case 1:
2139 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2140 + break;
2141 + case 2:
2142 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2143 + break;
2144 + case 3:
2145 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2146 + break;
2147 + default:
2148 + return -ENODEV;
2149 + }
2150 +
2151 + if (put_user(val, (u32 *) buf))
2152 + return -EFAULT;
2153 +
2154 + return sizeof(val);
2155 +}
2156 +
2157 +static ssize_t
2158 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2159 +{
2160 + u32 val;
2161 +
2162 + if (get_user(val, (u32 *) buf))
2163 + return -EFAULT;
2164 +
2165 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2166 + case 0:
2167 + return -EACCES;
2168 + case 1:
2169 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2170 + break;
2171 + case 2:
2172 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2173 + break;
2174 + case 3:
2175 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2176 + break;
2177 + default:
2178 + return -ENODEV;
2179 + }
2180 +
2181 + return sizeof(val);
2182 +}
2183 +
2184 +static struct file_operations gpio_fops = {
2185 + owner: THIS_MODULE,
2186 + open: gpio_open,
2187 + release: gpio_release,
2188 + read: gpio_read,
2189 + write: gpio_write,
2190 +};
2191 +
2192 +static int __init
2193 +gpio_init(void)
2194 +{
2195 + int i;
2196 +
2197 + if (!(gpio_sbh = sb_kattach()))
2198 + return -ENODEV;
2199 +
2200 + sb_gpiosetcore(gpio_sbh);
2201 +
2202 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2203 + return gpio_major;
2204 +
2205 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2206 +
2207 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2208 + gpio_file[i].handle = devfs_register(gpio_dir,
2209 + gpio_file[i].name,
2210 + DEVFS_FL_DEFAULT, gpio_major, i,
2211 + S_IFCHR | S_IRUGO | S_IWUGO,
2212 + &gpio_fops, NULL);
2213 + }
2214 +
2215 + return 0;
2216 +}
2217 +
2218 +static void __exit
2219 +gpio_exit(void)
2220 +{
2221 + int i;
2222 +
2223 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2224 + devfs_unregister(gpio_file[i].handle);
2225 + devfs_unregister(gpio_dir);
2226 + devfs_unregister_chrdev(gpio_major, "gpio");
2227 + sb_detach(gpio_sbh);
2228 +}
2229 +
2230 +module_init(gpio_init);
2231 +module_exit(gpio_exit);
2232 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2233 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2234 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-04-28 00:33:05.000000000 +0200
2235 @@ -0,0 +1,158 @@
2236 +/*
2237 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2238 + *
2239 + * Copyright 2006, Broadcom Corporation
2240 + * All Rights Reserved.
2241 + *
2242 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2243 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2244 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2245 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2246 + *
2247 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2248 + */
2249 +
2250 +#include <typedefs.h>
2251 +#include <bcmdefs.h>
2252 +#include <osl.h>
2253 +#include <bcmutils.h>
2254 +#include <sbutils.h>
2255 +#include <bcmdevs.h>
2256 +#include <bcmnvram.h>
2257 +#include <sbconfig.h>
2258 +#include <sbextif.h>
2259 +#include <sbchipc.h>
2260 +#include <hndcpu.h>
2261 +
2262 +/*
2263 + * Returns TRUE if an external UART exists at the given base
2264 + * register.
2265 + */
2266 +static bool
2267 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2268 +{
2269 + uint8 save_mcr, status1;
2270 +
2271 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2272 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2273 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2274 + W_REG(osh, &regs[UART_MCR], save_mcr);
2275 +
2276 + return (status1 == 0x90);
2277 +}
2278 +
2279 +/*
2280 + * Initializes UART access. The callback function will be called once
2281 + * per found UART.
2282 + */
2283 +void
2284 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2285 + uint reg_shift))
2286 +{
2287 + osl_t *osh;
2288 + void *regs;
2289 + ulong base;
2290 + uint irq;
2291 + int i, n;
2292 +
2293 + osh = sb_osh(sbh);
2294 +
2295 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2296 + extifregs_t *eir = (extifregs_t *) regs;
2297 + sbconfig_t *sb;
2298 +
2299 + /* Determine external UART register base */
2300 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2301 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2302 +
2303 + /* Determine IRQ */
2304 + irq = sb_irq(sbh);
2305 +
2306 + /* Disable GPIO interrupt initially */
2307 + W_REG(osh, &eir->gpiointpolarity, 0);
2308 + W_REG(osh, &eir->gpiointmask, 0);
2309 +
2310 + /* Search for external UARTs */
2311 + n = 2;
2312 + for (i = 0; i < 2; i++) {
2313 + regs = (void *) REG_MAP(base + (i * 8), 8);
2314 + if (serial_exists(osh, regs)) {
2315 + /* Set GPIO 1 to be the external UART IRQ */
2316 + W_REG(osh, &eir->gpiointmask, 2);
2317 + /* XXXDetermine external UART clock */
2318 + if (add)
2319 + add(regs, irq, 13500000, 0);
2320 + }
2321 + }
2322 +
2323 + /* Add internal UART if enabled */
2324 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2325 + if (add)
2326 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2327 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2328 + chipcregs_t *cc = (chipcregs_t *) regs;
2329 + uint32 rev, cap, pll, baud_base, div;
2330 +
2331 + /* Determine core revision and capabilities */
2332 + rev = sb_corerev(sbh);
2333 + cap = R_REG(osh, &cc->capabilities);
2334 + pll = cap & CAP_PLL_MASK;
2335 +
2336 + /* Determine IRQ */
2337 + irq = sb_irq(sbh);
2338 +
2339 + if (pll == PLL_TYPE1) {
2340 + /* PLL clock */
2341 + baud_base = sb_clock_rate(pll,
2342 + R_REG(osh, &cc->clockcontrol_n),
2343 + R_REG(osh, &cc->clockcontrol_m2));
2344 + div = 1;
2345 + } else {
2346 + /* Fixed ALP clock */
2347 + if (rev >= 11 && rev != 15) {
2348 + baud_base = 20000000;
2349 + div = 1;
2350 + /* Set the override bit so we don't divide it */
2351 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2352 + }
2353 + /* Internal backplane clock */
2354 + else if (rev >= 3) {
2355 + baud_base = sb_clock(sbh);
2356 + div = 2; /* Minimum divisor */
2357 + W_REG(osh, &cc->clkdiv,
2358 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2359 + }
2360 + /* Fixed internal backplane clock */
2361 + else {
2362 + baud_base = 88000000;
2363 + div = 48;
2364 + }
2365 +
2366 + /* Clock source depends on strapping if UartClkOverride is unset */
2367 + if ((rev > 0) &&
2368 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2369 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2370 + /* Internal divided backplane clock */
2371 + baud_base /= div;
2372 + } else {
2373 + /* Assume external clock of 1.8432 MHz */
2374 + baud_base = 1843200;
2375 + }
2376 + }
2377 + }
2378 +
2379 + /* Add internal UARTs */
2380 + n = cap & CAP_UARTS_MASK;
2381 + for (i = 0; i < n; i++) {
2382 + /* Register offset changed after revision 0 */
2383 + if (rev)
2384 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2385 + else
2386 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2387 +
2388 + if (add)
2389 + add(regs, irq, baud_base, 0);
2390 + }
2391 + }
2392 +}
2393 +
2394 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2395 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2396 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-04-27 22:30:01.000000000 +0200
2397 @@ -0,0 +1,91 @@
2398 +/*
2399 + * BCM4710 address space map and definitions
2400 + * Think twice before adding to this file, this is not the kitchen sink
2401 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2402 + *
2403 + * Copyright 2004, Broadcom Corporation
2404 + * All Rights Reserved.
2405 + *
2406 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2407 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2408 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2409 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2410 + *
2411 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2412 + */
2413 +
2414 +#ifndef _bcm4710_h_
2415 +#define _bcm4710_h_
2416 +
2417 +/* Address map */
2418 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2419 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2420 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2421 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2422 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2423 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2424 +
2425 +/* Core register space */
2426 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2427 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2428 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2429 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2430 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2431 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2432 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2433 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2434 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2435 +
2436 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2437 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2438 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2439 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2440 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2441 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2442 +
2443 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2444 +
2445 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2446 +
2447 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2448 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2449 +
2450 +#define SBFLAG_PCI 0
2451 +#define SBFLAG_ENET0 1
2452 +#define SBFLAG_ILINE20 2
2453 +#define SBFLAG_CODEC 3
2454 +#define SBFLAG_USB 4
2455 +#define SBFLAG_EXTIF 5
2456 +#define SBFLAG_ENET1 6
2457 +
2458 +#ifdef CONFIG_HWSIM
2459 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2460 +#else
2461 +#define BCM4710_TRACE(trval)
2462 +#endif
2463 +
2464 +
2465 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2466 +
2467 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2468 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2469 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2470 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2471 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2472 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2473 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2474 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2475 +
2476 +#define LED_REG(x) \
2477 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2478 +
2479 +/*
2480 + * Reset function implemented in PLD. Read or write should trigger hard reset
2481 + */
2482 +#define SYS_HARD_RESET() \
2483 + { for (;;) \
2484 + *( (volatile unsigned char *)\
2485 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2486 + }
2487 +
2488 +#endif /* _bcm4710_h_ */
2489 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2490 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2491 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-04-27 20:12:21.000000000 +0200
2492 @@ -0,0 +1,106 @@
2493 +/*
2494 + * Misc system wide definitions
2495 + *
2496 + * Copyright 2006, Broadcom Corporation
2497 + * All Rights Reserved.
2498 + *
2499 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2500 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2501 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2502 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2503 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2504 + */
2505 +
2506 +#ifndef _bcmdefs_h_
2507 +#define _bcmdefs_h_
2508 +
2509 +/*
2510 + * One doesn't need to include this file explicitly, gets included automatically if
2511 + * typedefs.h is included.
2512 + */
2513 +
2514 +/* Reclaiming text and data :
2515 + * The following macros specify special linker sections that can be reclaimed
2516 + * after a system is considered 'up'.
2517 + */
2518 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2519 +extern bool bcmreclaimed;
2520 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2521 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2522 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2523 +#define BCMINITDATA(_data) _data
2524 +#define BCMINITFN(_fn) _fn
2525 +#define bcmreclaimed 0
2526 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2527 +
2528 +/* Reclaim uninit functions if BCMNODOWN is defined */
2529 +/* and if they are not already removed by -gc-sections */
2530 +#ifdef BCMNODOWN
2531 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2532 +#else
2533 +#define BCMUNINITFN(_fn) _fn
2534 +#endif
2535 +
2536 +#ifdef BCMRECLAIM
2537 +#define CONST
2538 +#else
2539 +#define CONST const
2540 +#endif /* BCMRECLAIM */
2541 +
2542 +/* Compatibility with old-style BCMRECLAIM */
2543 +#define BCMINIT(_id) _id
2544 +
2545 +
2546 +/* Put some library data/code into ROM to reduce RAM requirements */
2547 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2548 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2549 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2550 +#else
2551 +#define BCMROMDATA(_data) _data
2552 +#define BCMROMFN(_fn) _fn
2553 +#endif
2554 +
2555 +/* Bus types */
2556 +#define SB_BUS 0 /* Silicon Backplane */
2557 +#define PCI_BUS 1 /* PCI target */
2558 +#define PCMCIA_BUS 2 /* PCMCIA target */
2559 +#define SDIO_BUS 3 /* SDIO target */
2560 +#define JTAG_BUS 4 /* JTAG */
2561 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2562 +
2563 +/* Allows optimization for single-bus support */
2564 +#ifdef BCMBUSTYPE
2565 +#define BUSTYPE(bus) (BCMBUSTYPE)
2566 +#else
2567 +#define BUSTYPE(bus) (bus)
2568 +#endif
2569 +
2570 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2571 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2572 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2573 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2574 +
2575 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2576 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2577 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2578 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2579 +
2580 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2581 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2582 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2583 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2584 + */
2585 +#define BCMEXTRAHDROOM 160
2586 +
2587 +/* Headroom required for dongle-to-host communication. Packets allocated
2588 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2589 + * leave this much room in front for low-level message headers which may
2590 + * be needed to get across the dongle bus to the host. (These messages
2591 + * don't go over the network, so room for the full WL header above would
2592 + * be a waste.)
2593 + */
2594 +#define BCMDONGLEHDRSZ 8
2595 +
2596 +
2597 +
2598 +#endif /* _bcmdefs_h_ */
2599 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2600 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2601 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-04-27 22:30:25.000000000 +0200
2602 @@ -0,0 +1,369 @@
2603 +/*
2604 + * Broadcom device-specific manifest constants.
2605 + *
2606 + * Copyright 2006, Broadcom Corporation
2607 + * All Rights Reserved.
2608 + *
2609 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2610 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2611 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2612 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2613 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2614 + */
2615 +
2616 +#ifndef _BCMDEVS_H
2617 +#define _BCMDEVS_H
2618 +
2619 +#include "bcm4710.h"
2620 +
2621 +/* Known PCI vendor Id's */
2622 +#define VENDOR_EPIGRAM 0xfeda
2623 +#define VENDOR_BROADCOM 0x14e4
2624 +#define VENDOR_3COM 0x10b7
2625 +#define VENDOR_NETGEAR 0x1385
2626 +#define VENDOR_DIAMOND 0x1092
2627 +#define VENDOR_DELL 0x1028
2628 +#define VENDOR_HP 0x0e11
2629 +#define VENDOR_APPLE 0x106b
2630 +
2631 +/* PCI Device Id's */
2632 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2633 +#define BCM4211_DEVICE_ID 0x4211
2634 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2635 +#define BCM4231_DEVICE_ID 0x4231
2636 +
2637 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2638 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2639 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2640 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2641 +
2642 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2643 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2644 +
2645 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2646 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2647 +
2648 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2649 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2650 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2651 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2652 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2653 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2654 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2655 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2656 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2657 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2658 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2659 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
2660 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
2661 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
2662 +
2663 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
2664 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
2665 +
2666 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
2667 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2668 +
2669 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
2670 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2671 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2672 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2673 +
2674 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
2675 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2676 +#define BCM4306_D11G_ID2 0x4325
2677 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2678 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2679 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2680 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2681 +
2682 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2683 +
2684 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
2685 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
2686 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
2687 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
2688 +
2689 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2690 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2691 +
2692 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2693 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2694 +
2695 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
2696 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2697 +
2698 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
2699 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
2700 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
2701 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
2702 +
2703 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
2704 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
2705 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
2706 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
2707 +
2708 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
2709 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
2710 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
2711 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
2712 +
2713 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
2714 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
2715 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
2716 +
2717 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
2718 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2719 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2720 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2721 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2722 +
2723 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
2724 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
2725 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
2726 +
2727 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
2728 +
2729 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
2730 +
2731 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
2732 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
2733 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
2734 +
2735 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
2736 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
2737 +
2738 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
2739 +
2740 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
2741 +
2742 +/* PCMCIA vendor Id's */
2743 +
2744 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2745 +
2746 +/* SDIO vendor Id's */
2747 +#define VENDOR_BROADCOM_SDIO 0x00BF
2748 +
2749 +
2750 +/* boardflags */
2751 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2752 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2753 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2754 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2755 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2756 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2757 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2758 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2759 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2760 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2761 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2762 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2763 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2764 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2765 +
2766 +/* boardflags2 */
2767 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
2768 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
2769 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
2770 +
2771 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2772 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2773 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2774 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2775 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2776 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2777 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2778 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2779 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2780 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2781 +
2782 +/* power control defines */
2783 +#define PLL_DELAY 150 /* us pll on delay */
2784 +#define FREF_DELAY 200 /* us fref change delay */
2785 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2786 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2787 +
2788 +/* Reference Board Types */
2789 +
2790 +#define BU4710_BOARD 0x0400
2791 +#define VSIM4710_BOARD 0x0401
2792 +#define QT4710_BOARD 0x0402
2793 +
2794 +#define BU4309_BOARD 0x040a
2795 +#define BCM94309CB_BOARD 0x040b
2796 +#define BCM94309MP_BOARD 0x040c
2797 +#define BCM4309AP_BOARD 0x040d
2798 +
2799 +#define BCM94302MP_BOARD 0x040e
2800 +
2801 +#define BU4306_BOARD 0x0416
2802 +#define BCM94306CB_BOARD 0x0417
2803 +#define BCM94306MP_BOARD 0x0418
2804 +
2805 +#define BCM94710D_BOARD 0x041a
2806 +#define BCM94710R1_BOARD 0x041b
2807 +#define BCM94710R4_BOARD 0x041c
2808 +#define BCM94710AP_BOARD 0x041d
2809 +
2810 +#define BU2050_BOARD 0x041f
2811 +
2812 +
2813 +#define BCM94309G_BOARD 0x0421
2814 +
2815 +#define BU4704_BOARD 0x0423
2816 +#define BU4702_BOARD 0x0424
2817 +
2818 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2819 +
2820 +
2821 +#define BCM94702MN_BOARD 0x0428
2822 +
2823 +/* BCM4702 1U CompactPCI Board */
2824 +#define BCM94702CPCI_BOARD 0x0429
2825 +
2826 +/* BCM4702 with BCM95380 VLAN Router */
2827 +#define BCM95380RR_BOARD 0x042a
2828 +
2829 +/* cb4306 with SiGe PA */
2830 +#define BCM94306CBSG_BOARD 0x042b
2831 +
2832 +/* cb4306 with SiGe PA */
2833 +#define PCSG94306_BOARD 0x042d
2834 +
2835 +/* bu4704 with sdram */
2836 +#define BU4704SD_BOARD 0x042e
2837 +
2838 +/* Dual 11a/11g Router */
2839 +#define BCM94704AGR_BOARD 0x042f
2840 +
2841 +/* 11a-only minipci */
2842 +#define BCM94308MP_BOARD 0x0430
2843 +
2844 +
2845 +
2846 +#define BU4712_BOARD 0x0444
2847 +#define BU4712SD_BOARD 0x045d
2848 +#define BU4712L_BOARD 0x045f
2849 +
2850 +/* BCM4712 boards */
2851 +#define BCM94712AP_BOARD 0x0445
2852 +#define BCM94712P_BOARD 0x0446
2853 +
2854 +/* BCM4318 boards */
2855 +#define BU4318_BOARD 0x0447
2856 +#define CB4318_BOARD 0x0448
2857 +#define MPG4318_BOARD 0x0449
2858 +#define MP4318_BOARD 0x044a
2859 +#define SD4318_BOARD 0x044b
2860 +
2861 +/* BCM63XX boards */
2862 +#define BCM96338_BOARD 0x6338
2863 +#define BCM96348_BOARD 0x6348
2864 +
2865 +/* Another mp4306 with SiGe */
2866 +#define BCM94306P_BOARD 0x044c
2867 +
2868 +/* mp4303 */
2869 +#define BCM94303MP_BOARD 0x044e
2870 +
2871 +/* mpsgh4306 */
2872 +#define BCM94306MPSGH_BOARD 0x044f
2873 +
2874 +/* BRCM 4306 w/ Front End Modules */
2875 +#define BCM94306MPM 0x0450
2876 +#define BCM94306MPL 0x0453
2877 +
2878 +/* 4712agr */
2879 +#define BCM94712AGR_BOARD 0x0451
2880 +
2881 +/* pcmcia 4303 */
2882 +#define PC4303_BOARD 0x0454
2883 +
2884 +/* 5350K */
2885 +#define BCM95350K_BOARD 0x0455
2886 +
2887 +/* 5350R */
2888 +#define BCM95350R_BOARD 0x0456
2889 +
2890 +/* 4306mplna */
2891 +#define BCM94306MPLNA_BOARD 0x0457
2892 +
2893 +/* 4320 boards */
2894 +#define BU4320_BOARD 0x0458
2895 +#define BU4320S_BOARD 0x0459
2896 +#define BCM94320PH_BOARD 0x045a
2897 +
2898 +/* 4306mph */
2899 +#define BCM94306MPH_BOARD 0x045b
2900 +
2901 +/* 4306pciv */
2902 +#define BCM94306PCIV_BOARD 0x045c
2903 +
2904 +#define BU4712SD_BOARD 0x045d
2905 +
2906 +#define BCM94320PFLSH_BOARD 0x045e
2907 +
2908 +#define BU4712L_BOARD 0x045f
2909 +#define BCM94712LGR_BOARD 0x0460
2910 +#define BCM94320R_BOARD 0x0461
2911 +
2912 +#define BU5352_BOARD 0x0462
2913 +
2914 +#define BCM94318MPGH_BOARD 0x0463
2915 +
2916 +#define BU4311_BOARD 0x0464
2917 +#define BCM94311MC_BOARD 0x0465
2918 +#define BCM94311MCAG_BOARD 0x0466
2919 +
2920 +#define BCM95352GR_BOARD 0x0467
2921 +
2922 +/* bcm95351agr */
2923 +#define BCM95351AGR_BOARD 0x0470
2924 +
2925 +/* bcm94704mpcb */
2926 +#define BCM94704MPCB_BOARD 0x0472
2927 +
2928 +/* 4785 boards */
2929 +#define BU4785_BOARD 0x0478
2930 +
2931 +/* 4321 boards */
2932 +#define BU4321_BOARD 0x046b
2933 +#define BU4321E_BOARD 0x047c
2934 +#define MP4321_BOARD 0x046c
2935 +#define CB2_4321_BOARD 0x046d
2936 +#define MC4321_BOARD 0x046e
2937 +
2938 +/* # of GPIO pins */
2939 +#define GPIO_NUMPINS 16
2940 +
2941 +/* radio ID codes */
2942 +#define NORADIO_ID 0xe4f5
2943 +#define NORADIO_IDCODE 0x4e4f5246
2944 +
2945 +#define BCM2050_ID 0x2050
2946 +#define BCM2050_IDCODE 0x02050000
2947 +#define BCM2050A0_IDCODE 0x1205017f
2948 +#define BCM2050A1_IDCODE 0x2205017f
2949 +#define BCM2050R8_IDCODE 0x8205017f
2950 +
2951 +#define BCM2055_ID 0x2055
2952 +#define BCM2055_IDCODE 0x02055000
2953 +#define BCM2055A0_IDCODE 0x1205517f
2954 +
2955 +#define BCM2060_ID 0x2060
2956 +#define BCM2060_IDCODE 0x02060000
2957 +#define BCM2060WW_IDCODE 0x1206017f
2958 +
2959 +#define BCM2062_ID 0x2062
2960 +#define BCM2062_IDCODE 0x02062000
2961 +#define BCM2062A0_IDCODE 0x0206217f
2962 +
2963 +/* parts of an idcode: */
2964 +#define IDCODE_MFG_MASK 0x00000fff
2965 +#define IDCODE_MFG_SHIFT 0
2966 +#define IDCODE_ID_MASK 0x0ffff000
2967 +#define IDCODE_ID_SHIFT 12
2968 +#define IDCODE_REV_MASK 0xf0000000
2969 +#define IDCODE_REV_SHIFT 28
2970 +
2971 +#endif /* _BCMDEVS_H */
2972 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2973 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2974 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-05-02 04:32:03.000000000 +0200
2975 @@ -0,0 +1,391 @@
2976 +/*
2977 + * Broadcom device-specific manifest constants.
2978 + *
2979 + * Copyright 2005, Broadcom Corporation
2980 + * All Rights Reserved.
2981 + *
2982 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2983 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2984 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2985 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2986 + * $Id$
2987 + */
2988 +
2989 +#ifndef _BCMDEVS_H
2990 +#define _BCMDEVS_H
2991 +
2992 +
2993 +/* Known PCI vendor Id's */
2994 +#define VENDOR_EPIGRAM 0xfeda
2995 +#define VENDOR_BROADCOM 0x14e4
2996 +#define VENDOR_3COM 0x10b7
2997 +#define VENDOR_NETGEAR 0x1385
2998 +#define VENDOR_DIAMOND 0x1092
2999 +#define VENDOR_DELL 0x1028
3000 +#define VENDOR_HP 0x0e11
3001 +#define VENDOR_APPLE 0x106b
3002 +
3003 +/* PCI Device Id's */
3004 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
3005 +#define BCM4211_DEVICE_ID 0x4211
3006 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
3007 +#define BCM4231_DEVICE_ID 0x4231
3008 +
3009 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
3010 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
3011 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
3012 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
3013 +
3014 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
3015 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
3016 +
3017 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
3018 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
3019 +
3020 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
3021 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
3022 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
3023 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
3024 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
3025 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
3026 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
3027 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
3028 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3029 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3030 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3031 +
3032 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3033 +
3034 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
3035 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
3036 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
3037 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
3038 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
3039 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
3040 +
3041 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
3042 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3043 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3044 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3045 +
3046 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
3047 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
3048 +
3049 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
3050 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
3051 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
3052 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
3053 +
3054 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
3055 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3056 +#define BCM4306_D11G_ID2 0x4325
3057 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3058 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3059 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3060 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3061 +
3062 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3063 +
3064 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3065 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3066 +
3067 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
3068 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
3069 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
3070 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
3071 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
3072 +
3073 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3074 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3075 +
3076 +
3077 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
3078 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3079 +
3080 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
3081 +
3082 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
3083 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
3084 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
3085 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
3086 +
3087 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
3088 +
3089 +/* Address map */
3090 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
3091 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
3092 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
3093 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
3094 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
3095 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
3096 +
3097 +/* Core register space */
3098 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
3099 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
3100 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
3101 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
3102 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
3103 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
3104 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
3105 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
3106 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
3107 +
3108 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
3109 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
3110 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
3111 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
3112 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
3113 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
3114 +
3115 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
3116 +
3117 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
3118 +
3119 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
3120 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
3121 +
3122 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
3123 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3124 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3125 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3126 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3127 +
3128 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
3129 +
3130 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
3131 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
3132 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
3133 +
3134 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
3135 +
3136 +/* PCMCIA vendor Id's */
3137 +
3138 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3139 +
3140 +/* SDIO vendor Id's */
3141 +#define VENDOR_BROADCOM_SDIO 0x00BF
3142 +
3143 +
3144 +/* boardflags */
3145 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3146 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3147 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3148 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3149 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3150 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3151 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3152 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3153 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3154 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3155 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3156 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3157 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3158 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3159 +
3160 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3161 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
3162 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3163 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3164 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3165 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3166 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3167 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3168 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3169 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3170 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3171 +
3172 +/* Bus types */
3173 +#define SB_BUS 0 /* Silicon Backplane */
3174 +#define PCI_BUS 1 /* PCI target */
3175 +#define PCMCIA_BUS 2 /* PCMCIA target */
3176 +#define SDIO_BUS 3 /* SDIO target */
3177 +#define JTAG_BUS 4 /* JTAG */
3178 +
3179 +/* Allows optimization for single-bus support */
3180 +#ifdef BCMBUSTYPE
3181 +#define BUSTYPE(bus) (BCMBUSTYPE)
3182 +#else
3183 +#define BUSTYPE(bus) (bus)
3184 +#endif
3185 +
3186 +/* power control defines */
3187 +#define PLL_DELAY 150 /* us pll on delay */
3188 +#define FREF_DELAY 200 /* us fref change delay */
3189 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3190 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3191 +
3192 +/* Reference Board Types */
3193 +
3194 +#define BU4710_BOARD 0x0400
3195 +#define VSIM4710_BOARD 0x0401
3196 +#define QT4710_BOARD 0x0402
3197 +
3198 +#define BU4610_BOARD 0x0403
3199 +#define VSIM4610_BOARD 0x0404
3200 +
3201 +#define BU4307_BOARD 0x0405
3202 +#define BCM94301CB_BOARD 0x0406
3203 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
3204 +#define BCM94301MP_BOARD 0x0407
3205 +#define BCM94307MP_BOARD 0x0408
3206 +#define BCMAP4307_BOARD 0x0409
3207 +
3208 +#define BU4309_BOARD 0x040a
3209 +#define BCM94309CB_BOARD 0x040b
3210 +#define BCM94309MP_BOARD 0x040c
3211 +#define BCM4309AP_BOARD 0x040d
3212 +
3213 +#define BCM94302MP_BOARD 0x040e
3214 +
3215 +#define VSIM4310_BOARD 0x040f
3216 +#define BU4711_BOARD 0x0410
3217 +#define BCM94310U_BOARD 0x0411
3218 +#define BCM94310AP_BOARD 0x0412
3219 +#define BCM94310MP_BOARD 0x0414
3220 +
3221 +#define BU4306_BOARD 0x0416
3222 +#define BCM94306CB_BOARD 0x0417
3223 +#define BCM94306MP_BOARD 0x0418
3224 +
3225 +#define BCM94710D_BOARD 0x041a
3226 +#define BCM94710R1_BOARD 0x041b
3227 +#define BCM94710R4_BOARD 0x041c
3228 +#define BCM94710AP_BOARD 0x041d
3229 +
3230 +
3231 +#define BU2050_BOARD 0x041f
3232 +
3233 +
3234 +#define BCM94309G_BOARD 0x0421
3235 +
3236 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
3237 +
3238 +#define BU4704_BOARD 0x0423
3239 +#define BU4702_BOARD 0x0424
3240 +
3241 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3242 +
3243 +#define BU4317_BOARD 0x0426
3244 +
3245 +
3246 +#define BCM94702MN_BOARD 0x0428
3247 +
3248 +/* BCM4702 1U CompactPCI Board */
3249 +#define BCM94702CPCI_BOARD 0x0429
3250 +
3251 +/* BCM4702 with BCM95380 VLAN Router */
3252 +#define BCM95380RR_BOARD 0x042a
3253 +
3254 +/* cb4306 with SiGe PA */
3255 +#define BCM94306CBSG_BOARD 0x042b
3256 +
3257 +/* mp4301 with 2050 radio */
3258 +#define BCM94301MPL_BOARD 0x042c
3259 +
3260 +/* cb4306 with SiGe PA */
3261 +#define PCSG94306_BOARD 0x042d
3262 +
3263 +/* bu4704 with sdram */
3264 +#define BU4704SD_BOARD 0x042e
3265 +
3266 +/* Dual 11a/11g Router */
3267 +#define BCM94704AGR_BOARD 0x042f
3268 +
3269 +/* 11a-only minipci */
3270 +#define BCM94308MP_BOARD 0x0430
3271 +
3272 +
3273 +
3274 +/* BCM94317 boards */
3275 +#define BCM94317CB_BOARD 0x0440
3276 +#define BCM94317MP_BOARD 0x0441
3277 +#define BCM94317PCMCIA_BOARD 0x0442
3278 +#define BCM94317SDIO_BOARD 0x0443
3279 +
3280 +#define BU4712_BOARD 0x0444
3281 +#define BU4712SD_BOARD 0x045d
3282 +#define BU4712L_BOARD 0x045f
3283 +
3284 +/* BCM4712 boards */
3285 +#define BCM94712AP_BOARD 0x0445
3286 +#define BCM94712P_BOARD 0x0446
3287 +
3288 +/* BCM4318 boards */
3289 +#define BU4318_BOARD 0x0447
3290 +#define CB4318_BOARD 0x0448
3291 +#define MPG4318_BOARD 0x0449
3292 +#define MP4318_BOARD 0x044a
3293 +#define SD4318_BOARD 0x044b
3294 +
3295 +/* BCM63XX boards */
3296 +#define BCM96338_BOARD 0x6338
3297 +#define BCM96345_BOARD 0x6345
3298 +#define BCM96348_BOARD 0x6348
3299 +
3300 +/* Another mp4306 with SiGe */
3301 +#define BCM94306P_BOARD 0x044c
3302 +
3303 +/* CF-like 4317 modules */
3304 +#define BCM94317CF_BOARD 0x044d
3305 +
3306 +/* mp4303 */
3307 +#define BCM94303MP_BOARD 0x044e
3308 +
3309 +/* mpsgh4306 */
3310 +#define BCM94306MPSGH_BOARD 0x044f
3311 +
3312 +/* BRCM 4306 w/ Front End Modules */
3313 +#define BCM94306MPM 0x0450
3314 +#define BCM94306MPL 0x0453
3315 +
3316 +/* 4712agr */
3317 +#define BCM94712AGR_BOARD 0x0451
3318 +
3319 +/* The real CF 4317 board */
3320 +#define CFI4317_BOARD 0x0452
3321 +
3322 +/* pcmcia 4303 */
3323 +#define PC4303_BOARD 0x0454
3324 +
3325 +/* 5350K */
3326 +#define BCM95350K_BOARD 0x0455
3327 +
3328 +/* 5350R */
3329 +#define BCM95350R_BOARD 0x0456
3330 +
3331 +/* 4306mplna */
3332 +#define BCM94306MPLNA_BOARD 0x0457
3333 +
3334 +/* 4320 boards */
3335 +#define BU4320_BOARD 0x0458
3336 +#define BU4320S_BOARD 0x0459
3337 +#define BCM94320PH_BOARD 0x045a
3338 +
3339 +/* 4306mph */
3340 +#define BCM94306MPH_BOARD 0x045b
3341 +
3342 +/* 4306pciv */
3343 +#define BCM94306PCIV_BOARD 0x045c
3344 +
3345 +#define BU4712SD_BOARD 0x045d
3346 +
3347 +#define BCM94320PFLSH_BOARD 0x045e
3348 +
3349 +#define BU4712L_BOARD 0x045f
3350 +#define BCM94712LGR_BOARD 0x0460
3351 +#define BCM94320R_BOARD 0x0461
3352 +
3353 +#define BU5352_BOARD 0x0462
3354 +
3355 +#define BCM94318MPGH_BOARD 0x0463
3356 +
3357 +
3358 +#define BCM95352GR_BOARD 0x0467
3359 +
3360 +/* bcm95351agr */
3361 +#define BCM95351AGR_BOARD 0x0470
3362 +
3363 +/* # of GPIO pins */
3364 +#define GPIO_NUMPINS 16
3365 +
3366 +#endif /* _BCMDEVS_H */
3367 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3368 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3369 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-04-27 20:08:35.000000000 +0200
3370 @@ -0,0 +1,198 @@
3371 +/*
3372 + * local version of endian.h - byte order defines
3373 + *
3374 + * Copyright 2006, Broadcom Corporation
3375 + * All Rights Reserved.
3376 + *
3377 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3378 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3379 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3380 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3381 + *
3382 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3383 +*/
3384 +
3385 +#ifndef _BCMENDIAN_H_
3386 +#define _BCMENDIAN_H_
3387 +
3388 +#include <typedefs.h>
3389 +
3390 +/* Byte swap a 16 bit value */
3391 +#define BCMSWAP16(val) \
3392 + ((uint16)(\
3393 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3394 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3395 +
3396 +/* Byte swap a 32 bit value */
3397 +#define BCMSWAP32(val) \
3398 + ((uint32)(\
3399 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3400 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3401 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3402 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3403 +
3404 +/* 2 Byte swap a 32 bit value */
3405 +#define BCMSWAP32BY16(val) \
3406 + ((uint32)(\
3407 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3408 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3409 +
3410 +
3411 +static INLINE uint16
3412 +bcmswap16(uint16 val)
3413 +{
3414 + return BCMSWAP16(val);
3415 +}
3416 +
3417 +static INLINE uint32
3418 +bcmswap32(uint32 val)
3419 +{
3420 + return BCMSWAP32(val);
3421 +}
3422 +
3423 +static INLINE uint32
3424 +bcmswap32by16(uint32 val)
3425 +{
3426 + return BCMSWAP32BY16(val);
3427 +}
3428 +
3429 +/* buf - start of buffer of shorts to swap */
3430 +/* len - byte length of buffer */
3431 +static INLINE void
3432 +bcmswap16_buf(uint16 *buf, uint len)
3433 +{
3434 + len = len/2;
3435 +
3436 + while (len--) {
3437 + *buf = bcmswap16(*buf);
3438 + buf++;
3439 + }
3440 +}
3441 +
3442 +#ifndef hton16
3443 +#ifndef IL_BIGENDIAN
3444 +#define HTON16(i) BCMSWAP16(i)
3445 +#define hton16(i) bcmswap16(i)
3446 +#define hton32(i) bcmswap32(i)
3447 +#define ntoh16(i) bcmswap16(i)
3448 +#define ntoh32(i) bcmswap32(i)
3449 +#define ltoh16(i) (i)
3450 +#define ltoh32(i) (i)
3451 +#define htol16(i) (i)
3452 +#define htol32(i) (i)
3453 +#else
3454 +#define HTON16(i) (i)
3455 +#define hton16(i) (i)
3456 +#define hton32(i) (i)
3457 +#define ntoh16(i) (i)
3458 +#define ntoh32(i) (i)
3459 +#define ltoh16(i) bcmswap16(i)
3460 +#define ltoh32(i) bcmswap32(i)
3461 +#define htol16(i) bcmswap16(i)
3462 +#define htol32(i) bcmswap32(i)
3463 +#endif /* IL_BIGENDIAN */
3464 +#endif /* hton16 */
3465 +
3466 +#ifndef IL_BIGENDIAN
3467 +#define ltoh16_buf(buf, i)
3468 +#define htol16_buf(buf, i)
3469 +#else
3470 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3471 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3472 +#endif /* IL_BIGENDIAN */
3473 +
3474 +/*
3475 +* store 16-bit value to unaligned little endian byte array.
3476 +*/
3477 +static INLINE void
3478 +htol16_ua_store(uint16 val, uint8 *bytes)
3479 +{
3480 + bytes[0] = val&0xff;
3481 + bytes[1] = val>>8;
3482 +}
3483 +
3484 +/*
3485 +* store 32-bit value to unaligned little endian byte array.
3486 +*/
3487 +static INLINE void
3488 +htol32_ua_store(uint32 val, uint8 *bytes)
3489 +{
3490 + bytes[0] = val&0xff;
3491 + bytes[1] = (val>>8)&0xff;
3492 + bytes[2] = (val>>16)&0xff;
3493 + bytes[3] = val>>24;
3494 +}
3495 +
3496 +/*
3497 +* store 16-bit value to unaligned network(big) endian byte array.
3498 +*/
3499 +static INLINE void
3500 +hton16_ua_store(uint16 val, uint8 *bytes)
3501 +{
3502 + bytes[1] = val&0xff;
3503 + bytes[0] = val>>8;
3504 +}
3505 +
3506 +/*
3507 +* store 32-bit value to unaligned network(big) endian byte array.
3508 +*/
3509 +static INLINE void
3510 +hton32_ua_store(uint32 val, uint8 *bytes)
3511 +{
3512 + bytes[3] = val&0xff;
3513 + bytes[2] = (val>>8)&0xff;
3514 + bytes[1] = (val>>16)&0xff;
3515 + bytes[0] = val>>24;
3516 +}
3517 +
3518 +/*
3519 +* load 16-bit value from unaligned little endian byte array.
3520 +*/
3521 +static INLINE uint16
3522 +ltoh16_ua(void *bytes)
3523 +{
3524 + return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
3525 +}
3526 +
3527 +/*
3528 +* load 32-bit value from unaligned little endian byte array.
3529 +*/
3530 +static INLINE uint32
3531 +ltoh32_ua(void *bytes)
3532 +{
3533 + return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
3534 + (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
3535 +}
3536 +
3537 +/*
3538 +* load 16-bit value from unaligned big(network) endian byte array.
3539 +*/
3540 +static INLINE uint16
3541 +ntoh16_ua(void *bytes)
3542 +{
3543 + return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
3544 +}
3545 +
3546 +/*
3547 +* load 32-bit value from unaligned big(network) endian byte array.
3548 +*/
3549 +static INLINE uint32
3550 +ntoh32_ua(void *bytes)
3551 +{
3552 + return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
3553 + (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
3554 +}
3555 +
3556 +#define ltoh_ua(ptr) (\
3557 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3558 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
3559 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
3560 +)
3561 +
3562 +#define ntoh_ua(ptr) (\
3563 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3564 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
3565 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
3566 +)
3567 +
3568 +#endif /* _BCMENDIAN_H_ */
3569 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
3570 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
3571 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-04-27 23:29:18.000000000 +0200
3572 @@ -0,0 +1,159 @@
3573 +/*
3574 + * NVRAM variable manipulation
3575 + *
3576 + * Copyright 2006, Broadcom Corporation
3577 + * All Rights Reserved.
3578 + *
3579 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3580 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3581 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3582 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3583 + *
3584 + * $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
3585 + */
3586 +
3587 +#ifndef _bcmnvram_h_
3588 +#define _bcmnvram_h_
3589 +
3590 +#ifndef _LANGUAGE_ASSEMBLY
3591 +
3592 +#include <typedefs.h>
3593 +#include <bcmdefs.h>
3594 +
3595 +struct nvram_header {
3596 + uint32 magic;
3597 + uint32 len;
3598 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
3599 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
3600 + uint32 config_ncdl; /* ncdl values for memc */
3601 +};
3602 +
3603 +struct nvram_tuple {
3604 + char *name;
3605 + char *value;
3606 + struct nvram_tuple *next;
3607 +};
3608 +
3609 +/*
3610 + * Initialize NVRAM access. May be unnecessary or undefined on certain
3611 + * platforms.
3612 + */
3613 +extern int nvram_init(void *sbh);
3614 +
3615 +/*
3616 + * Disable NVRAM access. May be unnecessary or undefined on certain
3617 + * platforms.
3618 + */
3619 +extern void nvram_exit(void *sbh);
3620 +
3621 +/*
3622 + * Get the value of an NVRAM variable. The pointer returned may be
3623 + * invalid after a set.
3624 + * @param name name of variable to get
3625 + * @return value of variable or NULL if undefined
3626 + */
3627 +extern char * nvram_get(const char *name);
3628 +
3629 +/*
3630 + * Read the reset GPIO value from the nvram and set the GPIO
3631 + * as input
3632 + */
3633 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
3634 +extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
3635 +extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
3636 +
3637 +/*
3638 + * Get the value of an NVRAM variable.
3639 + * @param name name of variable to get
3640 + * @return value of variable or NUL if undefined
3641 + */
3642 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
3643 +
3644 +#define nvram_safe_unset(name) ({ \
3645 + if(nvram_get(name)) \
3646 + nvram_unset(name); \
3647 +})
3648 +
3649 +#define nvram_safe_set(name, value) ({ \
3650 + if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
3651 + nvram_set(name, value); \
3652 +})
3653 +
3654 +/*
3655 + * Match an NVRAM variable.
3656 + * @param name name of variable to match
3657 + * @param match value to compare against value of variable
3658 + * @return TRUE if variable is defined and its value is string equal
3659 + * to match or FALSE otherwise
3660 + */
3661 +static INLINE int
3662 +nvram_match(char *name, char *match) {
3663 + const char *value = nvram_get(name);
3664 + return (value && !strcmp(value, match));
3665 +}
3666 +
3667 +/*
3668 + * Inversely match an NVRAM variable.
3669 + * @param name name of variable to match
3670 + * @param match value to compare against value of variable
3671 + * @return TRUE if variable is defined and its value is not string
3672 + * equal to invmatch or FALSE otherwise
3673 + */
3674 +static INLINE int
3675 +nvram_invmatch(char *name, char *invmatch) {
3676 + const char *value = nvram_get(name);
3677 + return (value && strcmp(value, invmatch));
3678 +}
3679 +
3680 +/*
3681 + * Set the value of an NVRAM variable. The name and value strings are
3682 + * copied into private storage. Pointers to previously set values
3683 + * may become invalid. The new value may be immediately
3684 + * retrieved but will not be permanently stored until a commit.
3685 + * @param name name of variable to set
3686 + * @param value value of variable
3687 + * @return 0 on success and errno on failure
3688 + */
3689 +extern int nvram_set(const char *name, const char *value);
3690 +
3691 +/*
3692 + * Unset an NVRAM variable. Pointers to previously set values
3693 + * remain valid until a set.
3694 + * @param name name of variable to unset
3695 + * @return 0 on success and errno on failure
3696 + * NOTE: use nvram_commit to commit this change to flash.
3697 + */
3698 +extern int nvram_unset(const char *name);
3699 +
3700 +/*
3701 + * Commit NVRAM variables to permanent storage. All pointers to values
3702 + * may be invalid after a commit.
3703 + * NVRAM values are undefined after a commit.
3704 + * @return 0 on success and errno on failure
3705 + */
3706 +extern int nvram_commit(void);
3707 +
3708 +/*
3709 + * Get all NVRAM variables (format name=value\0 ... \0\0).
3710 + * @param buf buffer to store variables
3711 + * @param count size of buffer in bytes
3712 + * @return 0 on success and errno on failure
3713 + */
3714 +extern int nvram_getall(char *buf, int count);
3715 +
3716 +extern int file2nvram(char *filename, char *varname);
3717 +extern int nvram2file(char *varname, char *filename);
3718 +
3719 +#endif /* _LANGUAGE_ASSEMBLY */
3720 +
3721 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
3722 +#define NVRAM_CLEAR_MAGIC 0x0
3723 +#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
3724 +#define NVRAM_VERSION 1
3725 +#define NVRAM_HEADER_SIZE 20
3726 +#define NVRAM_SPACE 0x8000
3727 +
3728 +#define NVRAM_MAX_VALUE_LEN 255
3729 +#define NVRAM_MAX_PARAM_LEN 64
3730 +
3731 +#endif /* _bcmnvram_h_ */
3732 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
3733 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
3734 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-04-27 20:27:33.000000000 +0200
3735 @@ -0,0 +1,108 @@
3736 +/*
3737 + * Misc useful routines to access NIC local SROM/OTP .
3738 + *
3739 + * Copyright 2006, Broadcom Corporation
3740 + * All Rights Reserved.
3741 + *
3742 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3743 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3744 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3745 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3746 + *
3747 + * $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
3748 + */
3749 +
3750 +#ifndef _bcmsrom_h_
3751 +#define _bcmsrom_h_
3752 +
3753 +/* Maximum srom: 4 Kilobits == 512 bytes */
3754 +#define SROM_MAX 512
3755 +
3756 +/* SROM Rev 4: Reallocate the software part of the srom to accomodate
3757 + * MIMO features. It assumes up to two PCIE functions and 440 bytes
3758 + * of useable srom i.e. the useable storage in chips with OTP that
3759 + * implements hardware redundancy.
3760 + */
3761 +
3762 +#define SROM4_WORDS 220
3763 +
3764 +#define SROM4_SIGN 32
3765 +#define SROM4_SIGNATURE 0x5372
3766 +
3767 +#define SROM4_BREV 33
3768 +
3769 +#define SROM4_BFL0 34
3770 +#define SROM4_BFL1 35
3771 +#define SROM4_BFL2 36
3772 +#define SROM4_BFL3 37
3773 +
3774 +#define SROM4_MACHI 38
3775 +#define SROM4_MACMID 39
3776 +#define SROM4_MACLO 40
3777 +
3778 +#define SROM4_CCODE 41
3779 +#define SROM4_REGREV 42
3780 +
3781 +#define SROM4_LEDBH10 43
3782 +#define SROM4_LEDBH32 44
3783 +
3784 +#define SROM4_LEDDC 45
3785 +
3786 +#define SROM4_AA 46
3787 +#define SROM4_AA2G_MASK 0x00ff
3788 +#define SROM4_AA2G_SHIFT 0
3789 +#define SROM4_AA5G_MASK 0xff00
3790 +#define SROM4_AA5G_SHIFT 8
3791 +
3792 +#define SROM4_AG10 47
3793 +#define SROM4_AG32 48
3794 +
3795 +#define SROM4_TXPID2G 49
3796 +#define SROM4_TXPID5G 51
3797 +#define SROM4_TXPID5GL 53
3798 +#define SROM4_TXPID5GH 55
3799 +
3800 +/* Per-path fields */
3801 +#define MAX_PATH 4
3802 +#define SROM4_PATH0 64
3803 +#define SROM4_PATH1 87
3804 +#define SROM4_PATH2 110
3805 +#define SROM4_PATH3 133
3806 +
3807 +#define SROM4_2G_ITT_MAXP 0
3808 +#define SROM4_2G_PA 1
3809 +#define SROM4_5G_ITT_MAXP 5
3810 +#define SROM4_5GLH_MAXP 6
3811 +#define SROM4_5G_PA 7
3812 +#define SROM4_5GL_PA 11
3813 +#define SROM4_5GH_PA 15
3814 +
3815 +/* Fields in the ITT_MAXP and 5GLH_MAXP words */
3816 +#define B2G_MAXP_MASK 0xff
3817 +#define B2G_ITT_SHIFT 8
3818 +#define B5G_MAXP_MASK 0xff
3819 +#define B5G_ITT_SHIFT 8
3820 +#define B5GH_MAXP_MASK 0xff
3821 +#define B5GL_MAXP_SHIFT 8
3822 +
3823 +/* All the miriad power offsets */
3824 +#define SROM4_2G_CCKPO 156
3825 +#define SROM4_2G_OFDMPO 157
3826 +#define SROM4_5G_OFDMPO 159
3827 +#define SROM4_5GL_OFDMPO 161
3828 +#define SROM4_5GH_OFDMPO 163
3829 +#define SROM4_2G_MCSPO 165
3830 +#define SROM4_5G_MCSPO 173
3831 +#define SROM4_5GL_MCSPO 181
3832 +#define SROM4_5GH_MCSPO 189
3833 +#define SROM4_CCDPO 197
3834 +#define SROM4_STBCPO 198
3835 +#define SROM4_BW40PO 199
3836 +#define SROM4_BWDUPPO 200
3837 +
3838 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
3839 +
3840 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3841 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3842 +
3843 +#endif /* _bcmsrom_h_ */
3844 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
3845 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
3846 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-05-02 01:52:12.000000000 +0200
3847 @@ -0,0 +1,433 @@
3848 +/*
3849 + * Misc useful os-independent macros and functions.
3850 + *
3851 + * Copyright 2006, Broadcom Corporation
3852 + * All Rights Reserved.
3853 + *
3854 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3855 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3856 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3857 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3858 + * $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
3859 + */
3860 +
3861 +#ifndef _bcmutils_h_
3862 +#define _bcmutils_h_
3863 +
3864 +/* ** driver-only section ** */
3865 +#ifdef BCMDRIVER
3866 +
3867 +#define _BCM_U 0x01 /* upper */
3868 +#define _BCM_L 0x02 /* lower */
3869 +#define _BCM_D 0x04 /* digit */
3870 +#define _BCM_C 0x08 /* cntrl */
3871 +#define _BCM_P 0x10 /* punct */
3872 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
3873 +#define _BCM_X 0x40 /* hex digit */
3874 +#define _BCM_SP 0x80 /* hard space (0x20) */
3875 +
3876 +#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
3877 +
3878 +extern unsigned char bcm_ctype[];
3879 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
3880 +
3881 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
3882 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
3883 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
3884 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
3885 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
3886 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
3887 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
3888 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
3889 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
3890 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
3891 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
3892 +
3893 +/*
3894 + * Spin at most 'us' microseconds while 'exp' is true.
3895 + * Caller should explicitly test 'exp' when this completes
3896 + * and take appropriate error action if 'exp' is still true.
3897 + */
3898 +#define SPINWAIT(exp, us) { \
3899 + uint countdown = (us) + 9; \
3900 + while ((exp) && (countdown >= 10)) {\
3901 + OSL_DELAY(10); \
3902 + countdown -= 10; \
3903 + } \
3904 +}
3905 +
3906 +struct ether_addr {
3907 + uint8 octet[6];
3908 +} __attribute__((packed));
3909 +
3910 +/* string */
3911 +extern uchar bcm_toupper(uchar c);
3912 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
3913 +extern char *bcmstrstr(char *haystack, char *needle);
3914 +extern char *bcmstrcat(char *dest, const char *src);
3915 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
3916 +/* ethernet address */
3917 +extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
3918 +/* variable access */
3919 +extern char *getvar(char *vars, char *name);
3920 +extern int getintvar(char *vars, char *name);
3921 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
3922 +#ifdef BCMPERFSTATS
3923 +extern void bcm_perf_enable(void);
3924 +extern void bcmstats(char *fmt);
3925 +extern void bcmlog(char *fmt, uint a1, uint a2);
3926 +extern void bcmdumplog(char *buf, int size);
3927 +extern int bcmdumplogent(char *buf, uint idx);
3928 +#else
3929 +#define bcm_perf_enable()
3930 +#define bcmstats(fmt)
3931 +#define bcmlog(fmt, a1, a2)
3932 +#define bcmdumplog(buf, size) *buf = '\0'
3933 +#define bcmdumplogent(buf, idx) -1
3934 +#endif /* BCMPERFSTATS */
3935 +extern char *bcm_nvram_vars(uint *length);
3936 +extern int bcm_nvram_cache(void *sbh);
3937 +
3938 +/* Support for sharing code across in-driver iovar implementations.
3939 + * The intent is that a driver use this structure to map iovar names
3940 + * to its (private) iovar identifiers, and the lookup function to
3941 + * find the entry. Macros are provided to map ids and get/set actions
3942 + * into a single number space for a switch statement.
3943 + */
3944 +
3945 +/* iovar structure */
3946 +typedef struct bcm_iovar {
3947 + const char *name; /* name for lookup and display */
3948 + uint16 varid; /* id for switch */
3949 + uint16 flags; /* driver-specific flag bits */
3950 + uint16 type; /* base type of argument */
3951 + uint16 minlen; /* min length for buffer vars */
3952 +} bcm_iovar_t;
3953 +
3954 +/* varid definitions are per-driver, may use these get/set bits */
3955 +
3956 +/* IOVar action bits for id mapping */
3957 +#define IOV_GET 0 /* Get an iovar */
3958 +#define IOV_SET 1 /* Set an iovar */
3959 +
3960 +/* Varid to actionid mapping */
3961 +#define IOV_GVAL(id) ((id)*2)
3962 +#define IOV_SVAL(id) (((id)*2)+IOV_SET)
3963 +#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
3964 +
3965 +/* flags are per-driver based on driver attributes */
3966 +
3967 +/* Base type definitions */
3968 +#define IOVT_VOID 0 /* no value (implictly set only) */
3969 +#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
3970 +#define IOVT_INT8 2 /* integer values are range-checked */
3971 +#define IOVT_UINT8 3 /* unsigned int 8 bits */
3972 +#define IOVT_INT16 4 /* int 16 bits */
3973 +#define IOVT_UINT16 5 /* unsigned int 16 bits */
3974 +#define IOVT_INT32 6 /* int 32 bits */
3975 +#define IOVT_UINT32 7 /* unsigned int 32 bits */
3976 +#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
3977 +
3978 +extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
3979 +extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
3980 +
3981 +#endif /* #ifdef BCMDRIVER */
3982 +
3983 +/* ** driver/apps-shared section ** */
3984 +
3985 +#define BCME_STRLEN 64 /* Max string length for BCM errors */
3986 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
3987 +
3988 +
3989 +/*
3990 + * error codes could be added but the defined ones shouldn't be changed/deleted
3991 + * these error codes are exposed to the user code
3992 + * when ever a new error code is added to this list
3993 + * please update errorstring table with the related error string and
3994 + * update osl files with os specific errorcode map
3995 +*/
3996 +
3997 +#define BCME_OK 0 /* Success */
3998 +#define BCME_ERROR -1 /* Error generic */
3999 +#define BCME_BADARG -2 /* Bad Argument */
4000 +#define BCME_BADOPTION -3 /* Bad option */
4001 +#define BCME_NOTUP -4 /* Not up */
4002 +#define BCME_NOTDOWN -5 /* Not down */
4003 +#define BCME_NOTAP -6 /* Not AP */
4004 +#define BCME_NOTSTA -7 /* Not STA */
4005 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
4006 +#define BCME_RADIOOFF -9 /* Radio Off */
4007 +#define BCME_NOTBANDLOCKED -10 /* Not band locked */
4008 +#define BCME_NOCLK -11 /* No Clock */
4009 +#define BCME_BADRATESET -12 /* BAD Rate valueset */
4010 +#define BCME_BADBAND -13 /* BAD Band */
4011 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
4012 +#define BCME_BUFTOOLONG -15 /* Buffer too long */
4013 +#define BCME_BUSY -16 /* Busy */
4014 +#define BCME_NOTASSOCIATED -17 /* Not Associated */
4015 +#define BCME_BADSSIDLEN -18 /* Bad SSID len */
4016 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
4017 +#define BCME_BADCHAN -20 /* Bad Channel */
4018 +#define BCME_BADADDR -21 /* Bad Address */
4019 +#define BCME_NORESOURCE -22 /* Not Enough Resources */
4020 +#define BCME_UNSUPPORTED -23 /* Unsupported */
4021 +#define BCME_BADLEN -24 /* Bad length */
4022 +#define BCME_NOTREADY -25 /* Not Ready */
4023 +#define BCME_EPERM -26 /* Not Permitted */
4024 +#define BCME_NOMEM -27 /* No Memory */
4025 +#define BCME_ASSOCIATED -28 /* Associated */
4026 +#define BCME_RANGE -29 /* Not In Range */
4027 +#define BCME_NOTFOUND -30 /* Not Found */
4028 +#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
4029 +#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
4030 +#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
4031 +#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
4032 +#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
4033 +#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
4034 +#define BCME_LAST BCME_DONGLE_DOWN
4035 +
4036 +/* These are collection of BCME Error strings */
4037 +#define BCMERRSTRINGTABLE { \
4038 + "OK", \
4039 + "Undefined error", \
4040 + "Bad Argument", \
4041 + "Bad Option", \
4042 + "Not up", \
4043 + "Not down", \
4044 + "Not AP", \
4045 + "Not STA", \
4046 + "Bad Key Index", \
4047 + "Radio Off", \
4048 + "Not band locked", \
4049 + "No clock", \
4050 + "Bad Rate valueset", \
4051 + "Bad Band", \
4052 + "Buffer too short", \
4053 + "Buffer too long", \
4054 + "Busy", \
4055 + "Not Associated", \
4056 + "Bad SSID len", \
4057 + "Out of Range Channel", \
4058 + "Bad Channel", \
4059 + "Bad Address", \
4060 + "Not Enough Resources", \
4061 + "Unsupported", \
4062 + "Bad length", \
4063 + "Not Ready", \
4064 + "Not Permitted", \
4065 + "No Memory", \
4066 + "Associated", \
4067 + "Not In Range", \
4068 + "Not Found", \
4069 + "WME Not Enabled", \
4070 + "TSPEC Not Found", \
4071 + "ACM Not Supported", \
4072 + "Not WME Association", \
4073 + "SDIO Bus Error", \
4074 + "Dongle Not Accessible" \
4075 +}
4076 +
4077 +#ifndef ABS
4078 +#define ABS(a) (((a) < 0)?-(a):(a))
4079 +#endif /* ABS */
4080 +
4081 +#ifndef MIN
4082 +#define MIN(a, b) (((a) < (b))?(a):(b))
4083 +#endif /* MIN */
4084 +
4085 +#ifndef MAX
4086 +#define MAX(a, b) (((a) > (b))?(a):(b))
4087 +#endif /* MAX */
4088 +
4089 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
4090 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
4091 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
4092 +#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
4093 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
4094 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
4095 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
4096 +
4097 +/* bit map related macros */
4098 +#ifndef setbit
4099 +#ifndef NBBY /* the BSD family defines NBBY */
4100 +#define NBBY 8 /* 8 bits per byte */
4101 +#endif /* #ifndef NBBY */
4102 +#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
4103 +#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
4104 +#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
4105 +#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
4106 +#endif /* setbit */
4107 +
4108 +#define NBITS(type) (sizeof(type) * 8)
4109 +#define NBITVAL(nbits) (1 << (nbits))
4110 +#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
4111 +#define NBITMASK(nbits) MAXBITVAL(nbits)
4112 +#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
4113 +
4114 +/* basic mux operation - can be optimized on several architectures */
4115 +#define MUX(pred, true, false) ((pred) ? (true) : (false))
4116 +
4117 +/* modulo inc/dec - assumes x E [0, bound - 1] */
4118 +#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
4119 +#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
4120 +
4121 +/* modulo inc/dec, bound = 2^k */
4122 +#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
4123 +#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
4124 +
4125 +/* modulo add/sub - assumes x, y E [0, bound - 1] */
4126 +#define MODADD(x, y, bound) \
4127 + MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
4128 +#define MODSUB(x, y, bound) \
4129 + MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
4130 +
4131 +/* module add/sub, bound = 2^k */
4132 +#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
4133 +#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
4134 +
4135 +/* crc defines */
4136 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
4137 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
4138 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
4139 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
4140 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
4141 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
4142 +
4143 +/* bcm_format_flags() bit description structure */
4144 +typedef struct bcm_bit_desc {
4145 + uint32 bit;
4146 + char* name;
4147 +} bcm_bit_desc_t;
4148 +
4149 +/* tag_ID/length/value_buffer tuple */
4150 +typedef struct bcm_tlv {
4151 + uint8 id;
4152 + uint8 len;
4153 + uint8 data[1];
4154 +} bcm_tlv_t;
4155 +
4156 +/* Check that bcm_tlv_t fits into the given buflen */
4157 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
4158 +
4159 +/* buffer length for ethernet address from bcm_ether_ntoa() */
4160 +#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
4161 +
4162 +/* unaligned load and store macros */
4163 +#ifdef IL_BIGENDIAN
4164 +static INLINE uint32
4165 +load32_ua(uint8 *a)
4166 +{
4167 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
4168 +}
4169 +
4170 +static INLINE void
4171 +store32_ua(uint8 *a, uint32 v)
4172 +{
4173 + a[0] = (v >> 24) & 0xff;
4174 + a[1] = (v >> 16) & 0xff;
4175 + a[2] = (v >> 8) & 0xff;
4176 + a[3] = v & 0xff;
4177 +}
4178 +
4179 +static INLINE uint16
4180 +load16_ua(uint8 *a)
4181 +{
4182 + return ((a[0] << 8) | a[1]);
4183 +}
4184 +
4185 +static INLINE void
4186 +store16_ua(uint8 *a, uint16 v)
4187 +{
4188 + a[0] = (v >> 8) & 0xff;
4189 + a[1] = v & 0xff;
4190 +}
4191 +
4192 +#else
4193 +
4194 +static INLINE uint32
4195 +load32_ua(uint8 *a)
4196 +{
4197 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
4198 +}
4199 +
4200 +static INLINE void
4201 +store32_ua(uint8 *a, uint32 v)
4202 +{
4203 + a[3] = (v >> 24) & 0xff;
4204 + a[2] = (v >> 16) & 0xff;
4205 + a[1] = (v >> 8) & 0xff;
4206 + a[0] = v & 0xff;
4207 +}
4208 +
4209 +static INLINE uint16
4210 +load16_ua(uint8 *a)
4211 +{
4212 + return ((a[1] << 8) | a[0]);
4213 +}
4214 +
4215 +static INLINE void
4216 +store16_ua(uint8 *a, uint16 v)
4217 +{
4218 + a[1] = (v >> 8) & 0xff;
4219 + a[0] = v & 0xff;
4220 +}
4221 +
4222 +#endif /* IL_BIGENDIAN */
4223 +
4224 +/* externs */
4225 +/* crc */
4226 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
4227 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
4228 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
4229 +/* format/print */
4230 +extern void printfbig(char *buf);
4231 +
4232 +/* IE parsing */
4233 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
4234 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
4235 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
4236 +
4237 +/* bcmerror */
4238 +extern const char *bcmerrorstr(int bcmerror);
4239 +
4240 +/* multi-bool data type: set of bools, mbool is true if any is set */
4241 +typedef uint32 mbool;
4242 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
4243 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
4244 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
4245 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
4246 +
4247 +/* power conversion */
4248 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
4249 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
4250 +
4251 +/* generic datastruct to help dump routines */
4252 +struct fielddesc {
4253 + char *nameandfmt;
4254 + uint32 offset;
4255 + uint32 len;
4256 +};
4257 +
4258 +/* Buffer structure for collecting string-formatted data
4259 +* using bcm_bprintf() API.
4260 +* Use bcm_binit() to initialize before use
4261 +*/
4262 +struct bcmstrbuf
4263 +{
4264 + char *buf; /* pointer to current position in origbuf */
4265 + uint size; /* current (residual) size in bytes */
4266 + char *origbuf; /* unmodified pointer to orignal buffer */
4267 + uint origsize; /* unmodified orignal buffer size in bytes */
4268 +};
4269 +
4270 +extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
4271 +extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
4272 +
4273 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
4274 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
4275 + char *buf, uint32 bufsize);
4276 +
4277 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
4278 +extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
4279 +
4280 +#endif /* _bcmutils_h_ */
4281 diff -urN linux.old/arch/mips/bcm947xx/include/hndcpu.h linux.dev/arch/mips/bcm947xx/include/hndcpu.h
4282 --- linux.old/arch/mips/bcm947xx/include/hndcpu.h 1970-01-01 01:00:00.000000000 +0100
4283 +++ linux.dev/arch/mips/bcm947xx/include/hndcpu.h 2006-04-27 22:14:38.000000000 +0200
4284 @@ -0,0 +1,28 @@
4285 +/*
4286 + * HND SiliconBackplane MIPS/ARM cores software interface.
4287 + *
4288 + * Copyright 2006, Broadcom Corporation
4289 + * All Rights Reserved.
4290 + *
4291 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4292 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4293 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4294 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4295 + *
4296 + * $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4297 + */
4298 +
4299 +#ifndef _hndcpu_h_
4300 +#define _hndcpu_h_
4301 +
4302 +#if defined(mips)
4303 +#include <hndmips.h>
4304 +#elif defined(__ARM_ARCH_4T__)
4305 +#include <hndarm.h>
4306 +#endif
4307 +
4308 +extern uint sb_irq(sb_t *sbh);
4309 +extern uint32 sb_cpu_clock(sb_t *sbh);
4310 +extern void sb_cpu_wait(void);
4311 +
4312 +#endif /* _hndcpu_h_ */
4313 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
4314 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
4315 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-04-27 20:43:42.000000000 +0200
4316 @@ -0,0 +1,45 @@
4317 +/*
4318 + * HND SiliconBackplane MIPS core software interface.
4319 + *
4320 + * Copyright 2006, Broadcom Corporation
4321 + * All Rights Reserved.
4322 + *
4323 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4324 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4325 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4326 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4327 + *
4328 + * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
4329 + */
4330 +
4331 +#ifndef _hndmips_h_
4332 +#define _hndmips_h_
4333 +
4334 +extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
4335 +extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
4336 +extern void enable_pfc(uint32 mode);
4337 +extern uint32 sb_memc_get_ncdl(sb_t *sbh);
4338 +
4339 +#if defined(BCMPERFSTATS)
4340 +/* enable counting - exclusive version. Only one set of counters allowed at a time */
4341 +extern void hndmips_perf_instrcount_enable(void);
4342 +extern void hndmips_perf_icachecount_enable(void);
4343 +extern void hndmips_perf_dcachecount_enable(void);
4344 +/* start and stop counting */
4345 +#define hndmips_perf_start01() \
4346 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
4347 +#define hndmips_perf_stop01() \
4348 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
4349 +/* retrieve coutners - counters *decrement* */
4350 +#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
4351 +#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
4352 +#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
4353 +/* enable counting - modular version. Each counters can be enabled separately. */
4354 +extern void hndmips_perf_icache_hit_enable(void);
4355 +extern void hndmips_perf_icache_miss_enable(void);
4356 +extern uint32 hndmips_perf_read_instrcount(void);
4357 +extern uint32 hndmips_perf_read_cache_miss(void);
4358 +extern uint32 hndmips_perf_read_cache_hit(void);
4359 +#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
4360 +
4361 +#endif /* _hndmips_h_ */
4362 diff -urN linux.old/arch/mips/bcm947xx/include/hndpci.h linux.dev/arch/mips/bcm947xx/include/hndpci.h
4363 --- linux.old/arch/mips/bcm947xx/include/hndpci.h 1970-01-01 01:00:00.000000000 +0100
4364 +++ linux.dev/arch/mips/bcm947xx/include/hndpci.h 2006-04-27 20:36:48.000000000 +0200
4365 @@ -0,0 +1,30 @@
4366 +/*
4367 + * HND SiliconBackplane PCI core software interface.
4368 + *
4369 + * $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4370 + * Copyright 2006, Broadcom Corporation
4371 + * All Rights Reserved.
4372 + *
4373 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4374 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4375 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4376 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4377 + */
4378 +
4379 +#ifndef _hndpci_h_
4380 +#define _hndpci_h_
4381 +
4382 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4383 + int len);
4384 +extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4385 + int len);
4386 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4387 + int len);
4388 +extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4389 + int len);
4390 +extern void sbpci_ban(uint16 core);
4391 +extern int sbpci_init(sb_t *sbh);
4392 +extern int sbpci_init_pci(sb_t *sbh);
4393 +extern void sbpci_check(sb_t *sbh);
4394 +
4395 +#endif /* _hndpci_h_ */
4396 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
4397 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
4398 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-04-27 20:10:08.000000000 +0200
4399 @@ -0,0 +1,417 @@
4400 +/*
4401 + * Linux-specific abstractions to gain some independence from linux kernel versions.
4402 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
4403 + *
4404 + * Copyright 2006, Broadcom Corporation
4405 + * All Rights Reserved.
4406 + *
4407 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4408 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4409 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4410 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4411 + *
4412 + * $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
4413 + */
4414 +
4415 +#ifndef _linuxver_h_
4416 +#define _linuxver_h_
4417 +
4418 +#include <linux/config.h>
4419 +#include <linux/version.h>
4420 +
4421 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
4422 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
4423 +#ifdef __UNDEF_NO_VERSION__
4424 +#undef __NO_VERSION__
4425 +#else
4426 +#define __NO_VERSION__
4427 +#endif
4428 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
4429 +
4430 +#if defined(MODULE) && defined(MODVERSIONS)
4431 +#include <linux/modversions.h>
4432 +#endif
4433 +
4434 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
4435 +#include <linux/moduleparam.h>
4436 +#endif
4437 +
4438 +
4439 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
4440 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
4441 +#define module_param_string(_name_, _string_, _size_, _perm_) \
4442 + MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
4443 +#endif
4444 +
4445 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
4446 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
4447 +#include <linux/malloc.h>
4448 +#else
4449 +#include <linux/slab.h>
4450 +#endif
4451 +
4452 +#include <linux/types.h>
4453 +#include <linux/init.h>
4454 +#include <linux/mm.h>
4455 +#include <linux/string.h>
4456 +#include <linux/pci.h>
4457 +#include <linux/interrupt.h>
4458 +#include <linux/netdevice.h>
4459 +#include <asm/io.h>
4460 +
4461 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
4462 +#include <linux/workqueue.h>
4463 +#else
4464 +#include <linux/tqueue.h>
4465 +#ifndef work_struct
4466 +#define work_struct tq_struct
4467 +#endif
4468 +#ifndef INIT_WORK
4469 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
4470 +#endif
4471 +#ifndef schedule_work
4472 +#define schedule_work(_work) schedule_task((_work))
4473 +#endif
4474 +#ifndef flush_scheduled_work
4475 +#define flush_scheduled_work() flush_scheduled_tasks()
4476 +#endif
4477 +#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
4478 +
4479 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4480 +/* Some distributions have their own 2.6.x compatibility layers */
4481 +#ifndef IRQ_NONE
4482 +typedef void irqreturn_t;
4483 +#define IRQ_NONE
4484 +#define IRQ_HANDLED
4485 +#define IRQ_RETVAL(x)
4486 +#endif
4487 +#else
4488 +typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
4489 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
4490 +
4491 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
4492 +
4493 +#include <pcmcia/version.h>
4494 +#include <pcmcia/cs_types.h>
4495 +#include <pcmcia/cs.h>
4496 +#include <pcmcia/cistpl.h>
4497 +#include <pcmcia/cisreg.h>
4498 +#include <pcmcia/ds.h>
4499 +
4500 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69))
4501 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
4502 + * does this, but it's not in 2.4 so we do our own for now.
4503 + */
4504 +static inline void
4505 +cs_error(client_handle_t handle, int func, int ret)
4506 +{
4507 + error_info_t err = { func, ret };
4508 + CardServices(ReportError, handle, &err);
4509 +}
4510 +#endif
4511 +
4512 +#endif /* CONFIG_PCMCIA */
4513 +
4514 +#ifndef __exit
4515 +#define __exit
4516 +#endif
4517 +#ifndef __devexit
4518 +#define __devexit
4519 +#endif
4520 +#ifndef __devinit
4521 +#define __devinit __init
4522 +#endif
4523 +#ifndef __devinitdata
4524 +#define __devinitdata
4525 +#endif
4526 +#ifndef __devexit_p
4527 +#define __devexit_p(x) x
4528 +#endif
4529 +
4530 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
4531 +
4532 +#define pci_get_drvdata(dev) (dev)->sysdata
4533 +#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
4534 +
4535 +/*
4536 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
4537 + */
4538 +
4539 +struct pci_device_id {
4540 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
4541 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
4542 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
4543 + unsigned long driver_data; /* Data private to the driver */
4544 +};
4545 +
4546 +struct pci_driver {
4547 + struct list_head node;
4548 + char *name;
4549 + const struct pci_device_id *id_table; /* NULL if wants all devices */
4550 + int (*probe)(struct pci_dev *dev,
4551 + const struct pci_device_id *id); /* New device inserted */
4552 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug
4553 + * capable driver)
4554 + */
4555 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
4556 + void (*resume)(struct pci_dev *dev); /* Device woken up */
4557 +};
4558 +
4559 +#define MODULE_DEVICE_TABLE(type, name)
4560 +#define PCI_ANY_ID (~0)
4561 +
4562 +/* compatpci.c */
4563 +#define pci_module_init pci_register_driver
4564 +extern int pci_register_driver(struct pci_driver *drv);
4565 +extern void pci_unregister_driver(struct pci_driver *drv);
4566 +
4567 +#endif /* PCI registration */
4568 +
4569 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
4570 +#ifdef MODULE
4571 +#define module_init(x) int init_module(void) { return x(); }
4572 +#define module_exit(x) void cleanup_module(void) { x(); }
4573 +#else
4574 +#define module_init(x) __initcall(x);
4575 +#define module_exit(x) __exitcall(x);
4576 +#endif
4577 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
4578 +
4579 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
4580 +#define list_for_each(pos, head) \
4581 + for (pos = (head)->next; pos != (head); pos = pos->next)
4582 +#endif
4583 +
4584 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
4585 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
4586 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
4587 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
4588 +#endif
4589 +
4590 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
4591 +#define pci_enable_device(dev) do { } while (0)
4592 +#endif
4593 +
4594 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
4595 +#define net_device device
4596 +#endif
4597 +
4598 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
4599 +
4600 +/*
4601 + * DMA mapping
4602 + *
4603 + * See linux/Documentation/DMA-mapping.txt
4604 + */
4605 +
4606 +#ifndef PCI_DMA_TODEVICE
4607 +#define PCI_DMA_TODEVICE 1
4608 +#define PCI_DMA_FROMDEVICE 2
4609 +#endif
4610 +
4611 +typedef u32 dma_addr_t;
4612 +
4613 +/* Pure 2^n version of get_order */
4614 +static inline int get_order(unsigned long size)
4615 +{
4616 + int order;
4617 +
4618 + size = (size-1) >> (PAGE_SHIFT-1);
4619 + order = -1;
4620 + do {
4621 + size >>= 1;
4622 + order++;
4623 + } while (size);
4624 + return order;
4625 +}
4626 +
4627 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
4628 + dma_addr_t *dma_handle)
4629 +{
4630 + void *ret;
4631 + int gfp = GFP_ATOMIC | GFP_DMA;
4632 +
4633 + ret = (void *)__get_free_pages(gfp, get_order(size));
4634 +
4635 + if (ret != NULL) {
4636 + memset(ret, 0, size);
4637 + *dma_handle = virt_to_bus(ret);
4638 + }
4639 + return ret;
4640 +}
4641 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
4642 + void *vaddr, dma_addr_t dma_handle)
4643 +{
4644 + free_pages((unsigned long)vaddr, get_order(size));
4645 +}
4646 +#ifdef ILSIM
4647 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
4648 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
4649 +#else
4650 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
4651 +#define pci_unmap_single(cookie, address, size, dir)
4652 +#endif
4653 +
4654 +#endif /* DMA mapping */
4655 +
4656 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
4657 +
4658 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
4659 +#define netif_down(dev) do { (dev)->start = 0; } while (0)
4660 +
4661 +/* pcmcia-cs provides its own netdevice compatibility layer */
4662 +#ifndef _COMPAT_NETDEVICE_H
4663 +
4664 +/*
4665 + * SoftNet
4666 + *
4667 + * For pre-softnet kernels we need to tell the upper layer not to
4668 + * re-enter start_xmit() while we are in there. However softnet
4669 + * guarantees not to enter while we are in there so there is no need
4670 + * to do the netif_stop_queue() dance unless the transmit queue really
4671 + * gets stuck. This should also improve performance according to tests
4672 + * done by Aman Singla.
4673 + */
4674 +
4675 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
4676 +#define netif_wake_queue(dev) \
4677 + do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
4678 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
4679 +
4680 +static inline void netif_start_queue(struct net_device *dev)
4681 +{
4682 + dev->tbusy = 0;
4683 + dev->interrupt = 0;
4684 + dev->start = 1;
4685 +}
4686 +
4687 +#define netif_queue_stopped(dev) (dev)->tbusy
4688 +#define netif_running(dev) (dev)->start
4689 +
4690 +#endif /* _COMPAT_NETDEVICE_H */
4691 +
4692 +#define netif_device_attach(dev) netif_start_queue(dev)
4693 +#define netif_device_detach(dev) netif_stop_queue(dev)
4694 +
4695 +/* 2.4.x renamed bottom halves to tasklets */
4696 +#define tasklet_struct tq_struct
4697 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
4698 +{
4699 + queue_task(tasklet, &tq_immediate);
4700 + mark_bh(IMMEDIATE_BH);
4701 +}
4702 +
4703 +static inline void tasklet_init(struct tasklet_struct *tasklet,
4704 + void (*func)(unsigned long),
4705 + unsigned long data)
4706 +{
4707 + tasklet->next = NULL;
4708 + tasklet->sync = 0;
4709 + tasklet->routine = (void (*)(void *))func;
4710 + tasklet->data = (void *)data;
4711 +}
4712 +#define tasklet_kill(tasklet) { do{} while (0); }
4713 +
4714 +/* 2.4.x introduced del_timer_sync() */
4715 +#define del_timer_sync(timer) del_timer(timer)
4716 +
4717 +#else
4718 +
4719 +#define netif_down(dev)
4720 +
4721 +#endif /* SoftNet */
4722 +
4723 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
4724 +
4725 +/*
4726 + * Emit code to initialise a tq_struct's routine and data pointers
4727 + */
4728 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
4729 + do { \
4730 + (_tq)->routine = _routine; \
4731 + (_tq)->data = _data; \
4732 + } while (0)
4733 +
4734 +/*
4735 + * Emit code to initialise all of a tq_struct
4736 + */
4737 +#define INIT_TQUEUE(_tq, _routine, _data) \
4738 + do { \
4739 + INIT_LIST_HEAD(&(_tq)->list); \
4740 + (_tq)->sync = 0; \
4741 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
4742 + } while (0)
4743 +
4744 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
4745 +
4746 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
4747 +
4748 +/* Power management related routines */
4749 +
4750 +static inline int
4751 +pci_save_state(struct pci_dev *dev, u32 *buffer)
4752 +{
4753 + int i;
4754 + if (buffer) {
4755 + for (i = 0; i < 16; i++)
4756 + pci_read_config_dword(dev, i * 4, &buffer[i]);
4757 + }
4758 + return 0;
4759 +}
4760 +
4761 +static inline int
4762 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
4763 +{
4764 + int i;
4765 +
4766 + if (buffer) {
4767 + for (i = 0; i < 16; i++)
4768 + pci_write_config_dword(dev, i * 4, buffer[i]);
4769 + }
4770 + /*
4771 + * otherwise, write the context information we know from bootup.
4772 + * This works around a problem where warm-booting from Windows
4773 + * combined with a D3(hot)->D0 transition causes PCI config
4774 + * header data to be forgotten.
4775 + */
4776 + else {
4777 + for (i = 0; i < 6; i ++)
4778 + pci_write_config_dword(dev,
4779 + PCI_BASE_ADDRESS_0 + (i * 4),
4780 + pci_resource_start(dev, i));
4781 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
4782 + }
4783 + return 0;
4784 +}
4785 +
4786 +#endif /* PCI power management */
4787 +
4788 +/* Old cp0 access macros deprecated in 2.4.19 */
4789 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
4790 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
4791 +#endif
4792 +
4793 +/* Module refcount handled internally in 2.6.x */
4794 +#ifndef SET_MODULE_OWNER
4795 +#define SET_MODULE_OWNER(dev) do {} while (0)
4796 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
4797 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
4798 +#else
4799 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
4800 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
4801 +#endif
4802 +
4803 +#ifndef SET_NETDEV_DEV
4804 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
4805 +#endif
4806 +
4807 +#ifndef HAVE_FREE_NETDEV
4808 +#define free_netdev(dev) kfree(dev)
4809 +#endif
4810 +
4811 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4812 +/* struct packet_type redefined in 2.6.x */
4813 +#define af_packet_priv data
4814 +#endif
4815 +
4816 +#endif /* _linuxver_h_ */
4817 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
4818 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
4819 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-04-27 22:12:20.000000000 +0200
4820 @@ -0,0 +1,541 @@
4821 +/*
4822 + * HND Run Time Environment for standalone MIPS programs.
4823 + *
4824 + * Copyright 2006, Broadcom Corporation
4825 + * All Rights Reserved.
4826 + *
4827 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4828 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4829 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4830 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4831 + *
4832 + * $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
4833 + */
4834 +
4835 +#ifndef _MISPINC_H
4836 +#define _MISPINC_H
4837 +
4838 +
4839 +/* MIPS defines */
4840 +
4841 +#ifdef _LANGUAGE_ASSEMBLY
4842 +
4843 +/*
4844 + * Symbolic register names for 32 bit ABI
4845 + */
4846 +#define zero $0 /* wired zero */
4847 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
4848 +#define v0 $2 /* return value */
4849 +#define v1 $3
4850 +#define a0 $4 /* argument registers */
4851 +#define a1 $5
4852 +#define a2 $6
4853 +#define a3 $7
4854 +#define t0 $8 /* caller saved */
4855 +#define t1 $9
4856 +#define t2 $10
4857 +#define t3 $11
4858 +#define t4 $12
4859 +#define t5 $13
4860 +#define t6 $14
4861 +#define t7 $15
4862 +#define s0 $16 /* callee saved */
4863 +#define s1 $17
4864 +#define s2 $18
4865 +#define s3 $19
4866 +#define s4 $20
4867 +#define s5 $21
4868 +#define s6 $22
4869 +#define s7 $23
4870 +#define t8 $24 /* caller saved */
4871 +#define t9 $25
4872 +#define jp $25 /* PIC jump register */
4873 +#define k0 $26 /* kernel scratch */
4874 +#define k1 $27
4875 +#define gp $28 /* global pointer */
4876 +#define sp $29 /* stack pointer */
4877 +#define fp $30 /* frame pointer */
4878 +#define s8 $30 /* same like fp! */
4879 +#define ra $31 /* return address */
4880 +
4881 +
4882 +/* CP0 Registers */
4883 +
4884 +#define C0_INX $0
4885 +#define C0_RAND $1
4886 +#define C0_TLBLO0 $2
4887 +#define C0_TLBLO C0_TLBLO0
4888 +#define C0_TLBLO1 $3
4889 +#define C0_CTEXT $4
4890 +#define C0_PGMASK $5
4891 +#define C0_WIRED $6
4892 +#define C0_BADVADDR $8
4893 +#define C0_COUNT $9
4894 +#define C0_TLBHI $10
4895 +#define C0_COMPARE $11
4896 +#define C0_SR $12
4897 +#define C0_STATUS C0_SR
4898 +#define C0_CAUSE $13
4899 +#define C0_EPC $14
4900 +#define C0_PRID $15
4901 +#define C0_CONFIG $16
4902 +#define C0_LLADDR $17
4903 +#define C0_WATCHLO $18
4904 +#define C0_WATCHHI $19
4905 +#define C0_XCTEXT $20
4906 +#define C0_DIAGNOSTIC $22
4907 +#define C0_BROADCOM C0_DIAGNOSTIC
4908 +#define C0_PERFORMANCE $25
4909 +#define C0_ECC $26
4910 +#define C0_CACHEERR $27
4911 +#define C0_TAGLO $28
4912 +#define C0_TAGHI $29
4913 +#define C0_ERREPC $30
4914 +#define C0_DESAVE $31
4915 +
4916 +/*
4917 + * LEAF - declare leaf routine
4918 + */
4919 +#define LEAF(symbol) \
4920 + .globl symbol; \
4921 + .align 2; \
4922 + .type symbol, @function; \
4923 + .ent symbol, 0; \
4924 +symbol: .frame sp, 0, ra
4925 +
4926 +/*
4927 + * END - mark end of function
4928 + */
4929 +#define END(function) \
4930 + .end function; \
4931 + .size function, . - function
4932 +
4933 +#define _ULCAST_
4934 +
4935 +#define MFC0_SEL(dst, src, sel) \
4936 + .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
4937 +
4938 +
4939 +#define MTC0_SEL(dst, src, sel) \
4940 + .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
4941 +
4942 +#else
4943 +
4944 +/*
4945 + * The following macros are especially useful for __asm__
4946 + * inline assembler.
4947 + */
4948 +#ifndef __STR
4949 +#define __STR(x) #x
4950 +#endif
4951 +#ifndef STR
4952 +#define STR(x) __STR(x)
4953 +#endif
4954 +
4955 +#define _ULCAST_ (unsigned long)
4956 +
4957 +
4958 +/* CP0 Registers */
4959 +
4960 +#define C0_INX 0 /* CP0: TLB Index */
4961 +#define C0_RAND 1 /* CP0: TLB Random */
4962 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4963 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4964 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4965 +#define C0_CTEXT 4 /* CP0: Context */
4966 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4967 +#define C0_WIRED 6 /* CP0: TLB Wired */
4968 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4969 +#define C0_COUNT 9 /* CP0: Count */
4970 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4971 +#define C0_COMPARE 11 /* CP0: Compare */
4972 +#define C0_SR 12 /* CP0: Processor Status */
4973 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4974 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4975 +#define C0_EPC 14 /* CP0: Exception PC */
4976 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4977 +#define C0_CONFIG 16 /* CP0: Config */
4978 +#define C0_LLADDR 17 /* CP0: LLAddr */
4979 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4980 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4981 +#define C0_XCTEXT 20 /* CP0: XContext */
4982 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4983 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4984 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4985 +#define C0_ECC 26 /* CP0: ECC */
4986 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4987 +#define C0_TAGLO 28 /* CP0: TagLo */
4988 +#define C0_TAGHI 29 /* CP0: TagHi */
4989 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4990 +#define C0_DESAVE 31 /* CP0: DebugSave */
4991 +
4992 +#endif /* _LANGUAGE_ASSEMBLY */
4993 +
4994 +/*
4995 + * Memory segments (32bit kernel mode addresses)
4996 + */
4997 +#undef KUSEG
4998 +#undef KSEG0
4999 +#undef KSEG1
5000 +#undef KSEG2
5001 +#undef KSEG3
5002 +#define KUSEG 0x00000000
5003 +#define KSEG0 0x80000000
5004 +#define KSEG1 0xa0000000
5005 +#define KSEG2 0xc0000000
5006 +#define KSEG3 0xe0000000
5007 +#define PHYSADDR_MASK 0x1fffffff
5008 +
5009 +/*
5010 + * Map an address to a certain kernel segment
5011 + */
5012 +#undef PHYSADDR
5013 +#undef KSEG0ADDR
5014 +#undef KSEG1ADDR
5015 +#undef KSEG2ADDR
5016 +#undef KSEG3ADDR
5017 +
5018 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
5019 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
5020 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
5021 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
5022 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
5023 +
5024 +
5025 +#ifndef Index_Invalidate_I
5026 +/*
5027 + * Cache Operations
5028 + */
5029 +#define Index_Invalidate_I 0x00
5030 +#define Index_Writeback_Inv_D 0x01
5031 +#define Index_Invalidate_SI 0x02
5032 +#define Index_Writeback_Inv_SD 0x03
5033 +#define Index_Load_Tag_I 0x04
5034 +#define Index_Load_Tag_D 0x05
5035 +#define Index_Load_Tag_SI 0x06
5036 +#define Index_Load_Tag_SD 0x07
5037 +#define Index_Store_Tag_I 0x08
5038 +#define Index_Store_Tag_D 0x09
5039 +#define Index_Store_Tag_SI 0x0A
5040 +#define Index_Store_Tag_SD 0x0B
5041 +#define Create_Dirty_Excl_D 0x0d
5042 +#define Create_Dirty_Excl_SD 0x0f
5043 +#define Hit_Invalidate_I 0x10
5044 +#define Hit_Invalidate_D 0x11
5045 +#define Hit_Invalidate_SI 0x12
5046 +#define Hit_Invalidate_SD 0x13
5047 +#define Fill_I 0x14
5048 +#define Hit_Writeback_Inv_D 0x15
5049 + /* 0x16 is unused */
5050 +#define Hit_Writeback_Inv_SD 0x17
5051 +#define R5K_Page_Invalidate_S 0x17
5052 +#define Hit_Writeback_I 0x18
5053 +#define Hit_Writeback_D 0x19
5054 + /* 0x1a is unused */
5055 +#define Hit_Writeback_SD 0x1b
5056 + /* 0x1c is unused */
5057 + /* 0x1e is unused */
5058 +#define Hit_Set_Virtual_SI 0x1e
5059 +#define Hit_Set_Virtual_SD 0x1f
5060 +#endif /* !Index_Invalidate_I */
5061 +
5062 +
5063 +/*
5064 + * R4x00 interrupt enable / cause bits
5065 + */
5066 +#define IE_SW0 (_ULCAST_(1) << 8)
5067 +#define IE_SW1 (_ULCAST_(1) << 9)
5068 +#define IE_IRQ0 (_ULCAST_(1) << 10)
5069 +#define IE_IRQ1 (_ULCAST_(1) << 11)
5070 +#define IE_IRQ2 (_ULCAST_(1) << 12)
5071 +#define IE_IRQ3 (_ULCAST_(1) << 13)
5072 +#define IE_IRQ4 (_ULCAST_(1) << 14)
5073 +#define IE_IRQ5 (_ULCAST_(1) << 15)
5074 +
5075 +#ifndef ST0_UM
5076 +/*
5077 + * Bitfields in the mips32 cp0 status register
5078 + */
5079 +#define ST0_IE 0x00000001
5080 +#define ST0_EXL 0x00000002
5081 +#define ST0_ERL 0x00000004
5082 +#define ST0_UM 0x00000010
5083 +#define ST0_SWINT0 0x00000100
5084 +#define ST0_SWINT1 0x00000200
5085 +#define ST0_HWINT0 0x00000400
5086 +#define ST0_HWINT1 0x00000800
5087 +#define ST0_HWINT2 0x00001000
5088 +#define ST0_HWINT3 0x00002000
5089 +#define ST0_HWINT4 0x00004000
5090 +#define ST0_HWINT5 0x00008000
5091 +#define ST0_IM 0x0000ff00
5092 +#define ST0_NMI 0x00080000
5093 +#define ST0_SR 0x00100000
5094 +#define ST0_TS 0x00200000
5095 +#define ST0_BEV 0x00400000
5096 +#define ST0_RE 0x02000000
5097 +#define ST0_RP 0x08000000
5098 +#define ST0_CU 0xf0000000
5099 +#define ST0_CU0 0x10000000
5100 +#define ST0_CU1 0x20000000
5101 +#define ST0_CU2 0x40000000
5102 +#define ST0_CU3 0x80000000
5103 +#endif /* !ST0_UM */
5104 +
5105 +
5106 +/*
5107 + * Bitfields in the mips32 cp0 cause register
5108 + */
5109 +#define C_EXC 0x0000007c
5110 +#define C_EXC_SHIFT 2
5111 +#define C_INT 0x0000ff00
5112 +#define C_INT_SHIFT 8
5113 +#define C_SW0 (_ULCAST_(1) << 8)
5114 +#define C_SW1 (_ULCAST_(1) << 9)
5115 +#define C_IRQ0 (_ULCAST_(1) << 10)
5116 +#define C_IRQ1 (_ULCAST_(1) << 11)
5117 +#define C_IRQ2 (_ULCAST_(1) << 12)
5118 +#define C_IRQ3 (_ULCAST_(1) << 13)
5119 +#define C_IRQ4 (_ULCAST_(1) << 14)
5120 +#define C_IRQ5 (_ULCAST_(1) << 15)
5121 +#define C_WP 0x00400000
5122 +#define C_IV 0x00800000
5123 +#define C_CE 0x30000000
5124 +#define C_CE_SHIFT 28
5125 +#define C_BD 0x80000000
5126 +
5127 +/* Values in C_EXC */
5128 +#define EXC_INT 0
5129 +#define EXC_TLBM 1
5130 +#define EXC_TLBL 2
5131 +#define EXC_TLBS 3
5132 +#define EXC_AEL 4
5133 +#define EXC_AES 5
5134 +#define EXC_IBE 6
5135 +#define EXC_DBE 7
5136 +#define EXC_SYS 8
5137 +#define EXC_BPT 9
5138 +#define EXC_RI 10
5139 +#define EXC_CU 11
5140 +#define EXC_OV 12
5141 +#define EXC_TR 13
5142 +#define EXC_WATCH 23
5143 +#define EXC_MCHK 24
5144 +
5145 +
5146 +/*
5147 + * Bits in the cp0 config register.
5148 + */
5149 +#define CONF_CM_CACHABLE_NO_WA 0
5150 +#define CONF_CM_CACHABLE_WA 1
5151 +#define CONF_CM_UNCACHED 2
5152 +#define CONF_CM_CACHABLE_NONCOHERENT 3
5153 +#define CONF_CM_CACHABLE_CE 4
5154 +#define CONF_CM_CACHABLE_COW 5
5155 +#define CONF_CM_CACHABLE_CUW 6
5156 +#define CONF_CM_CACHABLE_ACCELERATED 7
5157 +#define CONF_CM_CMASK 7
5158 +#define CONF_CU (_ULCAST_(1) << 3)
5159 +#define CONF_DB (_ULCAST_(1) << 4)
5160 +#define CONF_IB (_ULCAST_(1) << 5)
5161 +#define CONF_SE (_ULCAST_(1) << 12)
5162 +#ifndef CONF_BE /* duplicate in mipsregs.h */
5163 +#define CONF_BE (_ULCAST_(1) << 15)
5164 +#endif
5165 +#define CONF_SC (_ULCAST_(1) << 17)
5166 +#define CONF_AC (_ULCAST_(1) << 23)
5167 +#define CONF_HALT (_ULCAST_(1) << 25)
5168 +#ifndef CONF_M /* duplicate in mipsregs.h */
5169 +#define CONF_M (_ULCAST_(1) << 31)
5170 +#endif
5171 +
5172 +
5173 +/*
5174 + * Bits in the cp0 config register select 1.
5175 + */
5176 +#define CONF1_FP 0x00000001 /* FPU present */
5177 +#define CONF1_EP 0x00000002 /* EJTAG present */
5178 +#define CONF1_CA 0x00000004 /* mips16 implemented */
5179 +#define CONF1_WR 0x00000008 /* Watch registers present */
5180 +#define CONF1_PC 0x00000010 /* Performance counters present */
5181 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
5182 +#define CONF1_DA_MASK 0x00000380
5183 +#define CONF1_DA_BASE 1
5184 +#define CONF1_DL_SHIFT 10 /* D$ line size */
5185 +#define CONF1_DL_MASK 0x00001c00
5186 +#define CONF1_DL_BASE 2
5187 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
5188 +#define CONF1_DS_MASK 0x0000e000
5189 +#define CONF1_DS_BASE 64
5190 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
5191 +#define CONF1_IA_MASK 0x00070000
5192 +#define CONF1_IA_BASE 1
5193 +#define CONF1_IL_SHIFT 19 /* I$ line size */
5194 +#define CONF1_IL_MASK 0x00380000
5195 +#define CONF1_IL_BASE 2
5196 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
5197 +#define CONF1_IS_MASK 0x01c00000
5198 +#define CONF1_IS_BASE 64
5199 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
5200 +#define CONF1_MS_SHIFT 25
5201 +
5202 +/* PRID register */
5203 +#define PRID_COPT_MASK 0xff000000
5204 +#define PRID_COMP_MASK 0x00ff0000
5205 +#define PRID_IMP_MASK 0x0000ff00
5206 +#define PRID_REV_MASK 0x000000ff
5207 +
5208 +#define PRID_COMP_LEGACY 0x000000
5209 +#define PRID_COMP_MIPS 0x010000
5210 +#define PRID_COMP_BROADCOM 0x020000
5211 +#define PRID_COMP_ALCHEMY 0x030000
5212 +#define PRID_COMP_SIBYTE 0x040000
5213 +#define PRID_IMP_BCM4710 0x4000
5214 +#define PRID_IMP_BCM3302 0x9000
5215 +#define PRID_IMP_BCM3303 0x9100
5216 +
5217 +#define PRID_IMP_UNKNOWN 0xff00
5218 +
5219 +#define BCM330X(id) \
5220 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5221 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
5222 + ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5223 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
5224 +
5225 +/* Bits in C0_BROADCOM */
5226 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
5227 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
5228 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
5229 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
5230 +#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
5231 +
5232 +/* PreFetch Cache aka Read Ahead Cache */
5233 +
5234 +#define PFC_CR0 0xff400000 /* control reg 0 */
5235 +#define PFC_CR1 0xff400004 /* control reg 1 */
5236 +
5237 +/* PFC operations */
5238 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
5239 +#define PFC_D 0x00000002 /* Enable PFC use for data */
5240 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
5241 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
5242 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
5243 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
5244 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
5245 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
5246 +#define PFC_BRR 0x40000000 /* Bus error indication */
5247 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
5248 +
5249 +/* Handy defaults */
5250 +#define PFC_DISABLED 0
5251 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
5252 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
5253 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
5254 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
5255 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
5256 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
5257 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
5258 +
5259 +#ifndef _LANGUAGE_ASSEMBLY
5260 +
5261 +/*
5262 + * Macros to access the system control coprocessor
5263 + */
5264 +
5265 +#define MFC0(source, sel) \
5266 +({ \
5267 + int __res; \
5268 + __asm__ __volatile__(" \
5269 + .set\tnoreorder; \
5270 + .set\tnoat; \
5271 + .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
5272 + move\t%0, $1; \
5273 + .set\tat; \
5274 + .set\treorder" \
5275 + :"=r" (__res) \
5276 + : \
5277 + :"$1"); \
5278 + __res; \
5279 +})
5280 +
5281 +#define MTC0(source, sel, value) \
5282 +do { \
5283 + __asm__ __volatile__(" \
5284 + .set\tnoreorder; \
5285 + .set\tnoat; \
5286 + move\t$1, %z0; \
5287 + .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
5288 + .set\tat; \
5289 + .set\treorder" \
5290 + : \
5291 + :"jr" (value) \
5292 + :"$1"); \
5293 +} while (0)
5294 +
5295 +#define get_c0_count() \
5296 +({ \
5297 + int __res; \
5298 + __asm__ __volatile__(" \
5299 + .set\tnoreorder; \
5300 + .set\tnoat; \
5301 + mfc0\t%0, $9; \
5302 + .set\tat; \
5303 + .set\treorder" \
5304 + :"=r" (__res)); \
5305 + __res; \
5306 +})
5307 +
5308 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
5309 +{
5310 + uint lsz, sets, ways;
5311 +
5312 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
5313 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
5314 + lsz = CONF1_IL_BASE << lsz;
5315 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
5316 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
5317 + *size = lsz * sets * ways;
5318 + *lsize = lsz;
5319 +}
5320 +
5321 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
5322 +{
5323 + uint lsz, sets, ways;
5324 +
5325 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
5326 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
5327 + lsz = CONF1_DL_BASE << lsz;
5328 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
5329 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
5330 + *size = lsz * sets * ways;
5331 + *lsize = lsz;
5332 +}
5333 +
5334 +#define cache_op(base, op) \
5335 + __asm__ __volatile__(" \
5336 + .set noreorder; \
5337 + .set mips3; \
5338 + cache %1, (%0); \
5339 + .set mips0; \
5340 + .set reorder" \
5341 + : \
5342 + : "r" (base), \
5343 + "i" (op));
5344 +
5345 +#define cache_unroll4(base, delta, op) \
5346 + __asm__ __volatile__(" \
5347 + .set noreorder; \
5348 + .set mips3; \
5349 + cache %1, 0(%0); \
5350 + cache %1, delta(%0); \
5351 + cache %1, (2 * delta)(%0); \
5352 + cache %1, (3 * delta)(%0); \
5353 + .set mips0; \
5354 + .set reorder" \
5355 + : \
5356 + : "r" (base), \
5357 + "i" (op));
5358 +
5359 +#endif /* !_LANGUAGE_ASSEMBLY */
5360 +
5361 +#endif /* _MISPINC_H */
5362 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
5363 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
5364 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-05-02 17:40:43.000000000 +0200
5365 @@ -0,0 +1,179 @@
5366 +#ifndef __osl_h
5367 +#define __osl_h
5368 +
5369 +#include <linux/delay.h>
5370 +#include <typedefs.h>
5371 +#include <linuxver.h>
5372 +#include <bcmutils.h>
5373 +#include <pcicfg.h>
5374 +
5375 +#define ASSERT(n)
5376 +
5377 +/* Pkttag flag should be part of public information */
5378 +struct osl_pubinfo {
5379 + bool pkttag;
5380 + uint pktalloced; /* Number of allocated packet buffers */
5381 +};
5382 +
5383 +struct osl_info {
5384 + struct osl_pubinfo pub;
5385 + uint magic;
5386 + void *pdev;
5387 + uint malloced;
5388 + uint failed;
5389 + void *dbgmem_list;
5390 +};
5391 +
5392 +typedef struct osl_info osl_t;
5393 +
5394 +#define PCI_CFG_RETRY 10
5395 +
5396 +/* map/unmap direction */
5397 +#define DMA_TX 1 /* TX direction for DMA */
5398 +#define DMA_RX 2 /* RX direction for DMA */
5399 +
5400 +#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
5401 +#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
5402 +#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
5403 +
5404 +/* bcopy, bcmp, and bzero */
5405 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
5406 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
5407 +#define bzero(b, len) memset((b), '\0', (len))
5408 +
5409 +/* uncached virtual address */
5410 +#ifdef mips
5411 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
5412 +#include <asm/addrspace.h>
5413 +#else
5414 +#define OSL_UNCACHED(va) (va)
5415 +#endif /* mips */
5416 +
5417 +
5418 +#ifndef IL_BIGENDIAN
5419 +#define R_REG(osh, r) (\
5420 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
5421 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
5422 + readl((volatile uint32*)(r)) \
5423 +)
5424 +#define W_REG(osh, r, v) do { \
5425 + switch (sizeof(*(r))) { \
5426 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
5427 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
5428 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5429 + } \
5430 +} while (0)
5431 +#else /* IL_BIGENDIAN */
5432 +#define R_REG(osh, r) ({ \
5433 + __typeof(*(r)) __osl_v; \
5434 + switch (sizeof(*(r))) { \
5435 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
5436 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
5437 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
5438 + } \
5439 + __osl_v; \
5440 +})
5441 +#define W_REG(osh, r, v) do { \
5442 + switch (sizeof(*(r))) { \
5443 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
5444 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
5445 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5446 + } \
5447 +} while (0)
5448 +#endif /* IL_BIGENDIAN */
5449 +
5450 +/* dereference an address that may cause a bus exception */
5451 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
5452 +#include <asm/paccess.h>
5453 +
5454 +/* map/unmap physical to virtual I/O */
5455 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
5456 +#define REG_UNMAP(va) iounmap((void *)(va))
5457 +
5458 +/* shared (dma-able) memory access macros */
5459 +#define R_SM(r) *(r)
5460 +#define W_SM(r, v) (*(r) = (v))
5461 +#define BZERO_SM(r, len) memset((r), '\0', (len))
5462 +
5463 +#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
5464 +#define MFREE(osh, addr, size) kfree((addr))
5465 +#define MALLOCED(osh) (0)
5466 +
5467 +#define osl_delay OSL_DELAY
5468 +static inline void OSL_DELAY(uint usec)
5469 +{
5470 + uint d;
5471 +
5472 + while (usec > 0) {
5473 + d = MIN(usec, 1000);
5474 + udelay(d);
5475 + usec -= d;
5476 + }
5477 +}
5478 +
5479 +static inline void
5480 +bcm_mdelay(uint ms)
5481 +{
5482 + uint i;
5483 +
5484 + for (i = 0; i < ms; i++) {
5485 + OSL_DELAY(1000);
5486 + }
5487 +}
5488 +
5489 +
5490 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
5491 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
5492 +
5493 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
5494 + osl_pci_read_config((osh), (offset), (size))
5495 +
5496 +static inline uint32
5497 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
5498 +{
5499 + uint val;
5500 + uint retry = PCI_CFG_RETRY;
5501 +
5502 + do {
5503 + pci_read_config_dword(osh->pdev, offset, &val);
5504 + if (val != 0xffffffff)
5505 + break;
5506 + } while (retry--);
5507 +
5508 + return (val);
5509 +}
5510 +
5511 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
5512 + osl_pci_write_config((osh), (offset), (size), (val))
5513 +static inline void
5514 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
5515 +{
5516 + uint retry = PCI_CFG_RETRY;
5517 +
5518 + do {
5519 + pci_write_config_dword(osh->pdev, offset, val);
5520 + if (offset != PCI_BAR0_WIN)
5521 + break;
5522 + if (osl_pci_read_config(osh, offset, size) == val)
5523 + break;
5524 + } while (retry--);
5525 +}
5526 +
5527 +
5528 +/* return bus # for the pci device pointed by osh->pdev */
5529 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
5530 +static inline uint
5531 +osl_pci_bus(osl_t *osh)
5532 +{
5533 + return ((struct pci_dev *)osh->pdev)->bus->number;
5534 +}
5535 +
5536 +/* return slot # for the pci device pointed by osh->pdev */
5537 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
5538 +static inline uint
5539 +osl_pci_slot(osl_t *osh)
5540 +{
5541 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
5542 +}
5543 +
5544 +#endif
5545 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
5546 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
5547 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-04-27 20:31:41.000000000 +0200
5548 @@ -0,0 +1,495 @@
5549 +/*
5550 + * pcicfg.h: PCI configuration constants and structures.
5551 + *
5552 + * Copyright 2006, Broadcom Corporation
5553 + * All Rights Reserved.
5554 + *
5555 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5556 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5557 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5558 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5559 + *
5560 + * $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
5561 + */
5562 +
5563 +#ifndef _h_pcicfg_
5564 +#define _h_pcicfg_
5565 +
5566 +/* The following inside ifndef's so we don't collide with NTDDK.H */
5567 +#ifndef PCI_MAX_BUS
5568 +#define PCI_MAX_BUS 0x100
5569 +#endif
5570 +#ifndef PCI_MAX_DEVICES
5571 +#define PCI_MAX_DEVICES 0x20
5572 +#endif
5573 +#ifndef PCI_MAX_FUNCTION
5574 +#define PCI_MAX_FUNCTION 0x8
5575 +#endif
5576 +
5577 +#ifndef PCI_INVALID_VENDORID
5578 +#define PCI_INVALID_VENDORID 0xffff
5579 +#endif
5580 +#ifndef PCI_INVALID_DEVICEID
5581 +#define PCI_INVALID_DEVICEID 0xffff
5582 +#endif
5583 +
5584 +
5585 +/* Convert between bus-slot-function-register and config addresses */
5586 +
5587 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
5588 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
5589 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
5590 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
5591 +
5592 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
5593 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
5594 +#define PCICFG_FUN_MASK 7 /* Function mask */
5595 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
5596 +
5597 +#define PCI_CONFIG_ADDR(b, s, f, o) \
5598 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
5599 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
5600 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
5601 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
5602 +
5603 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
5604 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
5605 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
5606 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
5607 +
5608 +/* PCIE Config space accessing MACROS */
5609 +
5610 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
5611 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
5612 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
5613 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
5614 +
5615 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
5616 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
5617 +#define PCIECFG_FUN_MASK 7 /* Function mask */
5618 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
5619 +
5620 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
5621 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
5622 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
5623 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
5624 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
5625 +
5626 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
5627 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
5628 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
5629 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
5630 +
5631 +/* The actual config space */
5632 +
5633 +#define PCI_BAR_MAX 6
5634 +
5635 +#define PCI_ROM_BAR 8
5636 +
5637 +#define PCR_RSVDA_MAX 2
5638 +
5639 +/* Bits in PCI bars' flags */
5640 +
5641 +#define PCIBAR_FLAGS 0xf
5642 +#define PCIBAR_IO 0x1
5643 +#define PCIBAR_MEM1M 0x2
5644 +#define PCIBAR_MEM64 0x4
5645 +#define PCIBAR_PREFETCH 0x8
5646 +#define PCIBAR_MEM32_MASK 0xFFFFFF80
5647 +
5648 +/* pci config status reg has a bit to indicate that capability ptr is present */
5649 +
5650 +#define PCI_CAPPTR_PRESENT 0x0010
5651 +
5652 +typedef struct _pci_config_regs {
5653 + unsigned short vendor;
5654 + unsigned short device;
5655 + unsigned short command;
5656 + unsigned short status;
5657 + unsigned char rev_id;
5658 + unsigned char prog_if;
5659 + unsigned char sub_class;
5660 + unsigned char base_class;
5661 + unsigned char cache_line_size;
5662 + unsigned char latency_timer;
5663 + unsigned char header_type;
5664 + unsigned char bist;
5665 + unsigned long base[PCI_BAR_MAX];
5666 + unsigned long cardbus_cis;
5667 + unsigned short subsys_vendor;
5668 + unsigned short subsys_id;
5669 + unsigned long baserom;
5670 + unsigned long rsvd_a[PCR_RSVDA_MAX];
5671 + unsigned char int_line;
5672 + unsigned char int_pin;
5673 + unsigned char min_gnt;
5674 + unsigned char max_lat;
5675 + unsigned char dev_dep[192];
5676 +} pci_config_regs;
5677 +
5678 +#define SZPCR (sizeof (pci_config_regs))
5679 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
5680 +
5681 +/* A structure for the config registers is nice, but in most
5682 + * systems the config space is not memory mapped, so we need
5683 + * filed offsetts. :-(
5684 + */
5685 +#define PCI_CFG_VID 0
5686 +#define PCI_CFG_DID 2
5687 +#define PCI_CFG_CMD 4
5688 +#define PCI_CFG_STAT 6
5689 +#define PCI_CFG_REV 8
5690 +#define PCI_CFG_PROGIF 9
5691 +#define PCI_CFG_SUBCL 0xa
5692 +#define PCI_CFG_BASECL 0xb
5693 +#define PCI_CFG_CLSZ 0xc
5694 +#define PCI_CFG_LATTIM 0xd
5695 +#define PCI_CFG_HDR 0xe
5696 +#define PCI_CFG_BIST 0xf
5697 +#define PCI_CFG_BAR0 0x10
5698 +#define PCI_CFG_BAR1 0x14
5699 +#define PCI_CFG_BAR2 0x18
5700 +#define PCI_CFG_BAR3 0x1c
5701 +#define PCI_CFG_BAR4 0x20
5702 +#define PCI_CFG_BAR5 0x24
5703 +#define PCI_CFG_CIS 0x28
5704 +#define PCI_CFG_SVID 0x2c
5705 +#define PCI_CFG_SSID 0x2e
5706 +#define PCI_CFG_ROMBAR 0x30
5707 +#define PCI_CFG_CAPPTR 0x34
5708 +#define PCI_CFG_INT 0x3c
5709 +#define PCI_CFG_PIN 0x3d
5710 +#define PCI_CFG_MINGNT 0x3e
5711 +#define PCI_CFG_MAXLAT 0x3f
5712 +
5713 +#ifdef __NetBSD__
5714 +#undef PCI_CLASS_DISPLAY
5715 +#undef PCI_CLASS_MEMORY
5716 +#undef PCI_CLASS_BRIDGE
5717 +#undef PCI_CLASS_INPUT
5718 +#undef PCI_CLASS_DOCK
5719 +#endif /* __NetBSD__ */
5720 +
5721 +/* Classes and subclasses */
5722 +
5723 +typedef enum {
5724 + PCI_CLASS_OLD = 0,
5725 + PCI_CLASS_DASDI,
5726 + PCI_CLASS_NET,
5727 + PCI_CLASS_DISPLAY,
5728 + PCI_CLASS_MMEDIA,
5729 + PCI_CLASS_MEMORY,
5730 + PCI_CLASS_BRIDGE,
5731 + PCI_CLASS_COMM,
5732 + PCI_CLASS_BASE,
5733 + PCI_CLASS_INPUT,
5734 + PCI_CLASS_DOCK,
5735 + PCI_CLASS_CPU,
5736 + PCI_CLASS_SERIAL,
5737 + PCI_CLASS_INTELLIGENT = 0xe,
5738 + PCI_CLASS_SATELLITE,
5739 + PCI_CLASS_CRYPT,
5740 + PCI_CLASS_DSP,
5741 + PCI_CLASS_XOR = 0xfe
5742 +} pci_classes;
5743 +
5744 +typedef enum {
5745 + PCI_DASDI_SCSI,
5746 + PCI_DASDI_IDE,
5747 + PCI_DASDI_FLOPPY,
5748 + PCI_DASDI_IPI,
5749 + PCI_DASDI_RAID,
5750 + PCI_DASDI_OTHER = 0x80
5751 +} pci_dasdi_subclasses;
5752 +
5753 +typedef enum {
5754 + PCI_NET_ETHER,
5755 + PCI_NET_TOKEN,
5756 + PCI_NET_FDDI,
5757 + PCI_NET_ATM,
5758 + PCI_NET_OTHER = 0x80
5759 +} pci_net_subclasses;
5760 +
5761 +typedef enum {
5762 + PCI_DISPLAY_VGA,
5763 + PCI_DISPLAY_XGA,
5764 + PCI_DISPLAY_3D,
5765 + PCI_DISPLAY_OTHER = 0x80
5766 +} pci_display_subclasses;
5767 +
5768 +typedef enum {
5769 + PCI_MMEDIA_VIDEO,
5770 + PCI_MMEDIA_AUDIO,
5771 + PCI_MMEDIA_PHONE,
5772 + PCI_MEDIA_OTHER = 0x80
5773 +} pci_mmedia_subclasses;
5774 +
5775 +typedef enum {
5776 + PCI_MEMORY_RAM,
5777 + PCI_MEMORY_FLASH,
5778 + PCI_MEMORY_OTHER = 0x80
5779 +} pci_memory_subclasses;
5780 +
5781 +typedef enum {
5782 + PCI_BRIDGE_HOST,
5783 + PCI_BRIDGE_ISA,
5784 + PCI_BRIDGE_EISA,
5785 + PCI_BRIDGE_MC,
5786 + PCI_BRIDGE_PCI,
5787 + PCI_BRIDGE_PCMCIA,
5788 + PCI_BRIDGE_NUBUS,
5789 + PCI_BRIDGE_CARDBUS,
5790 + PCI_BRIDGE_RACEWAY,
5791 + PCI_BRIDGE_OTHER = 0x80
5792 +} pci_bridge_subclasses;
5793 +
5794 +typedef enum {
5795 + PCI_COMM_UART,
5796 + PCI_COMM_PARALLEL,
5797 + PCI_COMM_MULTIUART,
5798 + PCI_COMM_MODEM,
5799 + PCI_COMM_OTHER = 0x80
5800 +} pci_comm_subclasses;
5801 +
5802 +typedef enum {
5803 + PCI_BASE_PIC,
5804 + PCI_BASE_DMA,
5805 + PCI_BASE_TIMER,
5806 + PCI_BASE_RTC,
5807 + PCI_BASE_PCI_HOTPLUG,
5808 + PCI_BASE_OTHER = 0x80
5809 +} pci_base_subclasses;
5810 +
5811 +typedef enum {
5812 + PCI_INPUT_KBD,
5813 + PCI_INPUT_PEN,
5814 + PCI_INPUT_MOUSE,
5815 + PCI_INPUT_SCANNER,
5816 + PCI_INPUT_GAMEPORT,
5817 + PCI_INPUT_OTHER = 0x80
5818 +} pci_input_subclasses;
5819 +
5820 +typedef enum {
5821 + PCI_DOCK_GENERIC,
5822 + PCI_DOCK_OTHER = 0x80
5823 +} pci_dock_subclasses;
5824 +
5825 +typedef enum {
5826 + PCI_CPU_386,
5827 + PCI_CPU_486,
5828 + PCI_CPU_PENTIUM,
5829 + PCI_CPU_ALPHA = 0x10,
5830 + PCI_CPU_POWERPC = 0x20,
5831 + PCI_CPU_MIPS = 0x30,
5832 + PCI_CPU_COPROC = 0x40,
5833 + PCI_CPU_OTHER = 0x80
5834 +} pci_cpu_subclasses;
5835 +
5836 +typedef enum {
5837 + PCI_SERIAL_IEEE1394,
5838 + PCI_SERIAL_ACCESS,
5839 + PCI_SERIAL_SSA,
5840 + PCI_SERIAL_USB,
5841 + PCI_SERIAL_FIBER,
5842 + PCI_SERIAL_SMBUS,
5843 + PCI_SERIAL_OTHER = 0x80
5844 +} pci_serial_subclasses;
5845 +
5846 +typedef enum {
5847 + PCI_INTELLIGENT_I2O
5848 +} pci_intelligent_subclasses;
5849 +
5850 +typedef enum {
5851 + PCI_SATELLITE_TV,
5852 + PCI_SATELLITE_AUDIO,
5853 + PCI_SATELLITE_VOICE,
5854 + PCI_SATELLITE_DATA,
5855 + PCI_SATELLITE_OTHER = 0x80
5856 +} pci_satellite_subclasses;
5857 +
5858 +typedef enum {
5859 + PCI_CRYPT_NETWORK,
5860 + PCI_CRYPT_ENTERTAINMENT,
5861 + PCI_CRYPT_OTHER = 0x80
5862 +} pci_crypt_subclasses;
5863 +
5864 +typedef enum {
5865 + PCI_DSP_DPIO,
5866 + PCI_DSP_OTHER = 0x80
5867 +} pci_dsp_subclasses;
5868 +
5869 +typedef enum {
5870 + PCI_XOR_QDMA,
5871 + PCI_XOR_OTHER = 0x80
5872 +} pci_xor_subclasses;
5873 +
5874 +/* Header types */
5875 +typedef enum {
5876 + PCI_HEADER_NORMAL,
5877 + PCI_HEADER_BRIDGE,
5878 + PCI_HEADER_CARDBUS
5879 +} pci_header_types;
5880 +
5881 +
5882 +/* Overlay for a PCI-to-PCI bridge */
5883 +
5884 +#define PPB_RSVDA_MAX 2
5885 +#define PPB_RSVDD_MAX 8
5886 +
5887 +typedef struct _ppb_config_regs {
5888 + unsigned short vendor;
5889 + unsigned short device;
5890 + unsigned short command;
5891 + unsigned short status;
5892 + unsigned char rev_id;
5893 + unsigned char prog_if;
5894 + unsigned char sub_class;
5895 + unsigned char base_class;
5896 + unsigned char cache_line_size;
5897 + unsigned char latency_timer;
5898 + unsigned char header_type;
5899 + unsigned char bist;
5900 + unsigned long rsvd_a[PPB_RSVDA_MAX];
5901 + unsigned char prim_bus;
5902 + unsigned char sec_bus;
5903 + unsigned char sub_bus;
5904 + unsigned char sec_lat;
5905 + unsigned char io_base;
5906 + unsigned char io_lim;
5907 + unsigned short sec_status;
5908 + unsigned short mem_base;
5909 + unsigned short mem_lim;
5910 + unsigned short pf_mem_base;
5911 + unsigned short pf_mem_lim;
5912 + unsigned long pf_mem_base_hi;
5913 + unsigned long pf_mem_lim_hi;
5914 + unsigned short io_base_hi;
5915 + unsigned short io_lim_hi;
5916 + unsigned short subsys_vendor;
5917 + unsigned short subsys_id;
5918 + unsigned long rsvd_b;
5919 + unsigned char rsvd_c;
5920 + unsigned char int_pin;
5921 + unsigned short bridge_ctrl;
5922 + unsigned char chip_ctrl;
5923 + unsigned char diag_ctrl;
5924 + unsigned short arb_ctrl;
5925 + unsigned long rsvd_d[PPB_RSVDD_MAX];
5926 + unsigned char dev_dep[192];
5927 +} ppb_config_regs;
5928 +
5929 +
5930 +/* PCI CAPABILITY DEFINES */
5931 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
5932 +#define PCI_CAP_MSICAP_ID 0x05
5933 +#define PCI_CAP_PCIECAP_ID 0x10
5934 +
5935 +/* Data structure to define the Message Signalled Interrupt facility
5936 + * Valid for PCI and PCIE configurations
5937 + */
5938 +typedef struct _pciconfig_cap_msi {
5939 + unsigned char capID;
5940 + unsigned char nextptr;
5941 + unsigned short msgctrl;
5942 + unsigned int msgaddr;
5943 +} pciconfig_cap_msi;
5944 +
5945 +/* Data structure to define the Power managment facility
5946 + * Valid for PCI and PCIE configurations
5947 + */
5948 +typedef struct _pciconfig_cap_pwrmgmt {
5949 + unsigned char capID;
5950 + unsigned char nextptr;
5951 + unsigned short pme_cap;
5952 + unsigned short pme_sts_ctrl;
5953 + unsigned char pme_bridge_ext;
5954 + unsigned char data;
5955 +} pciconfig_cap_pwrmgmt;
5956 +
5957 +/* Data structure to define the PCIE capability */
5958 +typedef struct _pciconfig_cap_pcie {
5959 + unsigned char capID;
5960 + unsigned char nextptr;
5961 + unsigned short pcie_cap;
5962 + unsigned int dev_cap;
5963 + unsigned short dev_ctrl;
5964 + unsigned short dev_status;
5965 + unsigned int link_cap;
5966 + unsigned short link_ctrl;
5967 + unsigned short link_status;
5968 +} pciconfig_cap_pcie;
5969 +
5970 +/* PCIE Enhanced CAPABILITY DEFINES */
5971 +#define PCIE_EXTCFG_OFFSET 0x100
5972 +#define PCIE_ADVERRREP_CAPID 0x0001
5973 +#define PCIE_VC_CAPID 0x0002
5974 +#define PCIE_DEVSNUM_CAPID 0x0003
5975 +#define PCIE_PWRBUDGET_CAPID 0x0004
5976 +
5977 +/* Header to define the PCIE specific capabilities in the extended config space */
5978 +typedef struct _pcie_enhanced_caphdr {
5979 + unsigned short capID;
5980 + unsigned short cap_ver : 4;
5981 + unsigned short next_ptr : 12;
5982 +} pcie_enhanced_caphdr;
5983 +
5984 +
5985 +/* Everything below is BRCM HND proprietary */
5986 +
5987 +
5988 +/* Brcm PCI configuration registers */
5989 +#define cap_list rsvd_a[0]
5990 +#define bar0_window dev_dep[0x80 - 0x40]
5991 +#define bar1_window dev_dep[0x84 - 0x40]
5992 +#define sprom_control dev_dep[0x88 - 0x40]
5993 +
5994 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
5995 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
5996 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
5997 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
5998 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
5999 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
6000 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
6001 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
6002 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
6003 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
6004 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
6005 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
6006 +
6007 +#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
6008 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
6009 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
6010 +#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
6011 + * 8KB window, so their address is the "regular"
6012 + * address plus 4K
6013 + */
6014 +#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
6015 +
6016 +/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
6017 +#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
6018 +#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
6019 +#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
6020 +
6021 +/* PCI_INT_STATUS */
6022 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
6023 +
6024 +/* PCI_INT_MASK */
6025 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
6026 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
6027 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
6028 +
6029 +/* PCI_SPROM_CONTROL */
6030 +#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
6031 +#define SPROM_LOCKED 0x08 /* SPROM Locked */
6032 +#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
6033 +#define SPROM_WRITEEN 0x10 /* SPROM write enable */
6034 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
6035 +#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
6036 +
6037 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
6038 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
6039 +
6040 +/* PCI_CFG_CMD_STAT */
6041 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
6042 +
6043 +#endif /* _h_pcicfg_ */
6044 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
6045 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6046 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-04-27 22:11:01.000000000 +0200
6047 @@ -0,0 +1,516 @@
6048 +/*
6049 + * SiliconBackplane Chipcommon core hardware definitions.
6050 + *
6051 + * The chipcommon core provides chip identification, SB control,
6052 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6053 + * gpio interface, extbus, and support for serial and parallel flashes.
6054 + *
6055 + * $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
6056 + * Copyright 2006, Broadcom Corporation
6057 + * All Rights Reserved.
6058 + *
6059 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6060 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6061 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6062 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6063 + *
6064 + */
6065 +
6066 +#ifndef _SBCHIPC_H
6067 +#define _SBCHIPC_H
6068 +
6069 +
6070 +#ifndef _LANGUAGE_ASSEMBLY
6071 +
6072 +/* cpp contortions to concatenate w/arg prescan */
6073 +#ifndef PAD
6074 +#define _PADLINE(line) pad ## line
6075 +#define _XSTR(line) _PADLINE(line)
6076 +#define PAD _XSTR(__LINE__)
6077 +#endif /* PAD */
6078 +
6079 +typedef volatile struct {
6080 + uint32 chipid; /* 0x0 */
6081 + uint32 capabilities;
6082 + uint32 corecontrol; /* corerev >= 1 */
6083 + uint32 bist;
6084 +
6085 + /* OTP */
6086 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6087 + uint32 otpcontrol;
6088 + uint32 otpprog;
6089 + uint32 PAD;
6090 +
6091 + /* Interrupt control */
6092 + uint32 intstatus; /* 0x20 */
6093 + uint32 intmask;
6094 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6095 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6096 +
6097 + /* Jtag Master */
6098 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6099 + uint32 jtagir;
6100 + uint32 jtagdr;
6101 + uint32 jtagctrl;
6102 +
6103 + /* serial flash interface registers */
6104 + uint32 flashcontrol; /* 0x40 */
6105 + uint32 flashaddress;
6106 + uint32 flashdata;
6107 + uint32 PAD[1];
6108 +
6109 + /* Silicon backplane configuration broadcast control */
6110 + uint32 broadcastaddress; /* 0x50 */
6111 + uint32 broadcastdata;
6112 + uint32 PAD[2];
6113 +
6114 + /* gpio - cleared only by power-on-reset */
6115 + uint32 gpioin; /* 0x60 */
6116 + uint32 gpioout;
6117 + uint32 gpioouten;
6118 + uint32 gpiocontrol;
6119 + uint32 gpiointpolarity;
6120 + uint32 gpiointmask;
6121 + uint32 PAD[2];
6122 +
6123 + /* Watchdog timer */
6124 + uint32 watchdog; /* 0x80 */
6125 + uint32 PAD[1];
6126 +
6127 + /* GPIO based LED powersave registers corerev >= 16 */
6128 + uint32 gpiotimerval; /* 0x88 */
6129 + uint32 gpiotimeroutmask;
6130 +
6131 + /* clock control */
6132 + uint32 clockcontrol_n; /* 0x90 */
6133 + uint32 clockcontrol_sb; /* aka m0 */
6134 + uint32 clockcontrol_pci; /* aka m1 */
6135 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6136 + uint32 clockcontrol_m3; /* cpu */
6137 + uint32 clkdiv; /* corerev >= 3 */
6138 + uint32 PAD[2];
6139 +
6140 + /* pll delay registers (corerev >= 4) */
6141 + uint32 pll_on_delay; /* 0xb0 */
6142 + uint32 fref_sel_delay;
6143 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6144 + uint32 PAD[1];
6145 +
6146 + /* Instaclock registers (corerev >= 10) */
6147 + uint32 system_clk_ctl; /* 0xc0 */
6148 + uint32 clkstatestretch;
6149 + uint32 PAD[14];
6150 +
6151 + /* ExtBus control registers (corerev >= 3) */
6152 + uint32 pcmcia_config; /* 0x100 */
6153 + uint32 pcmcia_memwait;
6154 + uint32 pcmcia_attrwait;
6155 + uint32 pcmcia_iowait;
6156 + uint32 ide_config;
6157 + uint32 ide_memwait;
6158 + uint32 ide_attrwait;
6159 + uint32 ide_iowait;
6160 + uint32 prog_config;
6161 + uint32 prog_waitcount;
6162 + uint32 flash_config;
6163 + uint32 flash_waitcount;
6164 + uint32 PAD[44];
6165 +
6166 + /* Clock control and hardware workarounds */
6167 + uint32 clk_ctl_st;
6168 + uint32 hw_war;
6169 + uint32 PAD[70];
6170 +
6171 + /* uarts */
6172 + uint8 uart0data; /* 0x300 */
6173 + uint8 uart0imr;
6174 + uint8 uart0fcr;
6175 + uint8 uart0lcr;
6176 + uint8 uart0mcr;
6177 + uint8 uart0lsr;
6178 + uint8 uart0msr;
6179 + uint8 uart0scratch;
6180 + uint8 PAD[248]; /* corerev >= 1 */
6181 +
6182 + uint8 uart1data; /* 0x400 */
6183 + uint8 uart1imr;
6184 + uint8 uart1fcr;
6185 + uint8 uart1lcr;
6186 + uint8 uart1mcr;
6187 + uint8 uart1lsr;
6188 + uint8 uart1msr;
6189 + uint8 uart1scratch;
6190 +} chipcregs_t;
6191 +
6192 +#endif /* _LANGUAGE_ASSEMBLY */
6193 +
6194 +#define CC_CHIPID 0
6195 +#define CC_CAPABILITIES 4
6196 +#define CC_JTAGCMD 0x30
6197 +#define CC_JTAGIR 0x34
6198 +#define CC_JTAGDR 0x38
6199 +#define CC_JTAGCTRL 0x3c
6200 +#define CC_WATCHDOG 0x80
6201 +#define CC_CLKC_N 0x90
6202 +#define CC_CLKC_M0 0x94
6203 +#define CC_CLKC_M1 0x98
6204 +#define CC_CLKC_M2 0x9c
6205 +#define CC_CLKC_M3 0xa0
6206 +#define CC_CLKDIV 0xa4
6207 +#define CC_SYS_CLK_CTL 0xc0
6208 +#define CC_OTP 0x800
6209 +
6210 +/* chipid */
6211 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6212 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6213 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6214 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6215 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6216 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6217 +#define CID_CC_SHIFT 24
6218 +
6219 +/* capabilities */
6220 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6221 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6222 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6223 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6224 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6225 +#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
6226 +#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
6227 +#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
6228 +#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
6229 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6230 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6231 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6232 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6233 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6234 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6235 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6236 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6237 +#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
6238 +
6239 +/* PLL type */
6240 +#define PLL_NONE 0x00000000
6241 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6242 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6243 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6244 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6245 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6246 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6247 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6248 +
6249 +/* corecontrol */
6250 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6251 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6252 +
6253 +/* chipcontrol */
6254 +#define CHIPCTRL_4321A0_DEFAULT 0x3a4
6255 +#define CHIPCTRL_4321A1_DEFAULT 0x0a4
6256 +
6257 +/* Fields in the otpstatus register */
6258 +#define OTPS_PROGFAIL 0x80000000
6259 +#define OTPS_PROTECT 0x00000007
6260 +#define OTPS_HW_PROTECT 0x00000001
6261 +#define OTPS_SW_PROTECT 0x00000002
6262 +#define OTPS_CID_PROTECT 0x00000004
6263 +
6264 +/* Fields in the otpcontrol register */
6265 +#define OTPC_RECWAIT 0xff000000
6266 +#define OTPC_PROGWAIT 0x00ffff00
6267 +#define OTPC_PRW_SHIFT 8
6268 +#define OTPC_MAXFAIL 0x00000038
6269 +#define OTPC_VSEL 0x00000006
6270 +#define OTPC_SELVL 0x00000001
6271 +
6272 +/* Fields in otpprog */
6273 +#define OTPP_COL_MASK 0x000000ff
6274 +#define OTPP_ROW_MASK 0x0000ff00
6275 +#define OTPP_ROW_SHIFT 8
6276 +#define OTPP_READERR 0x10000000
6277 +#define OTPP_VALUE 0x20000000
6278 +#define OTPP_VALUE_SHIFT 29
6279 +#define OTPP_READ 0x40000000
6280 +#define OTPP_START 0x80000000
6281 +#define OTPP_BUSY 0x80000000
6282 +
6283 +/* jtagcmd */
6284 +#define JCMD_START 0x80000000
6285 +#define JCMD_BUSY 0x80000000
6286 +#define JCMD_PAUSE 0x40000000
6287 +#define JCMD0_ACC_MASK 0x0000f000
6288 +#define JCMD0_ACC_IRDR 0x00000000
6289 +#define JCMD0_ACC_DR 0x00001000
6290 +#define JCMD0_ACC_IR 0x00002000
6291 +#define JCMD0_ACC_RESET 0x00003000
6292 +#define JCMD0_ACC_IRPDR 0x00004000
6293 +#define JCMD0_ACC_PDR 0x00005000
6294 +#define JCMD0_IRW_MASK 0x00000f00
6295 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6296 +#define JCMD_ACC_IRDR 0x00000000
6297 +#define JCMD_ACC_DR 0x00010000
6298 +#define JCMD_ACC_IR 0x00020000
6299 +#define JCMD_ACC_RESET 0x00030000
6300 +#define JCMD_ACC_IRPDR 0x00040000
6301 +#define JCMD_ACC_PDR 0x00050000
6302 +#define JCMD_IRW_MASK 0x00001f00
6303 +#define JCMD_IRW_SHIFT 8
6304 +#define JCMD_DRW_MASK 0x0000003f
6305 +
6306 +/* jtagctrl */
6307 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6308 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6309 +#define JCTRL_EN 1 /* Enable Jtag master */
6310 +
6311 +/* Fields in clkdiv */
6312 +#define CLKD_SFLASH 0x0f000000
6313 +#define CLKD_SFLASH_SHIFT 24
6314 +#define CLKD_OTP 0x000f0000
6315 +#define CLKD_OTP_SHIFT 16
6316 +#define CLKD_JTAG 0x00000f00
6317 +#define CLKD_JTAG_SHIFT 8
6318 +#define CLKD_UART 0x000000ff
6319 +
6320 +/* intstatus/intmask */
6321 +#define CI_GPIO 0x00000001 /* gpio intr */
6322 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6323 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6324 +
6325 +/* slow_clk_ctl */
6326 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6327 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6328 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6329 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6330 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6331 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
6332 + * 0: LPO is enabled
6333 + */
6334 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
6335 + * 0: power logic control
6336 + */
6337 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
6338 + * PLL clock disable requests from core
6339 + */
6340 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
6341 + * disable crystal when appropriate
6342 + */
6343 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6344 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6345 +#define SCC_CD_SHIFT 16
6346 +
6347 +/* system_clk_ctl */
6348 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6349 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6350 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6351 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6352 +#define SYCC_HR 0x00000010 /* Force HT */
6353 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
6354 +#define SYCC_CD_SHIFT 16
6355 +
6356 +/* gpiotimerval */
6357 +#define GPIO_ONTIME_SHIFT 16
6358 +
6359 +/* clockcontrol_n */
6360 +#define CN_N1_MASK 0x3f /* n1 control */
6361 +#define CN_N2_MASK 0x3f00 /* n2 control */
6362 +#define CN_N2_SHIFT 8
6363 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6364 +#define CN_PLLC_SHIFT 16
6365 +
6366 +/* clockcontrol_sb/pci/uart */
6367 +#define CC_M1_MASK 0x3f /* m1 control */
6368 +#define CC_M2_MASK 0x3f00 /* m2 control */
6369 +#define CC_M2_SHIFT 8
6370 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6371 +#define CC_M3_SHIFT 16
6372 +#define CC_MC_MASK 0x1f000000 /* mux control */
6373 +#define CC_MC_SHIFT 24
6374 +
6375 +/* N3M Clock control magic field values */
6376 +#define CC_F6_2 0x02 /* A factor of 2 in */
6377 +#define CC_F6_3 0x03 /* 6-bit fields like */
6378 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6379 +#define CC_F6_5 0x09
6380 +#define CC_F6_6 0x11
6381 +#define CC_F6_7 0x21
6382 +
6383 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6384 +
6385 +#define CC_MC_BYPASS 0x08
6386 +#define CC_MC_M1 0x04
6387 +#define CC_MC_M1M2 0x02
6388 +#define CC_MC_M1M2M3 0x01
6389 +#define CC_MC_M1M3 0x11
6390 +
6391 +/* Type 2 Clock control magic field values */
6392 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6393 +#define CC_T2M2_BIAS 3 /* m2 bias */
6394 +
6395 +#define CC_T2MC_M1BYP 1
6396 +#define CC_T2MC_M2BYP 2
6397 +#define CC_T2MC_M3BYP 4
6398 +
6399 +/* Type 6 Clock control magic field values */
6400 +#define CC_T6_MMASK 1 /* bits of interest in m */
6401 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6402 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6403 +#define SB2MIPS_T6(sb) (2 * (sb))
6404 +
6405 +/* Common clock base */
6406 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6407 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6408 +
6409 +/* Clock control values for 200Mhz in 5350 */
6410 +#define CLKC_5350_N 0x0311
6411 +#define CLKC_5350_M 0x04020009
6412 +
6413 +/* Flash types in the chipcommon capabilities register */
6414 +#define FLASH_NONE 0x000 /* No flash */
6415 +#define SFLASH_ST 0x100 /* ST serial flash */
6416 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6417 +#define PFLASH 0x700 /* Parallel flash */
6418 +
6419 +/* Bits in the ExtBus config registers */
6420 +#define CC_CFG_EN 0x0001 /* Enable */
6421 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6422 +#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
6423 +#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
6424 +#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
6425 +#define CC_CFG_EM_IDE 0x0006 /* IDE */
6426 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6427 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6428 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6429 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6430 +
6431 +/* ExtBus address space */
6432 +#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
6433 +#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
6434 +#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
6435 +#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
6436 +#define CC_EB_IDE 0x1a800000 /* IDE memory base */
6437 +#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
6438 +#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
6439 +#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
6440 +#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
6441 +
6442 +
6443 +/* Start/busy bit in flashcontrol */
6444 +#define SFLASH_OPCODE 0x000000ff
6445 +#define SFLASH_ACTION 0x00000700
6446 +#define SFLASH_START 0x80000000
6447 +#define SFLASH_BUSY SFLASH_START
6448 +
6449 +/* flashcontrol action codes */
6450 +#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
6451 +#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
6452 +#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
6453 +#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
6454 +#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
6455 +#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
6456 +#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
6457 +
6458 +/* flashcontrol action+opcodes for ST flashes */
6459 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6460 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6461 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6462 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6463 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6464 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6465 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6466 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6467 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6468 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6469 +
6470 +/* Status register bits for ST flashes */
6471 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6472 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6473 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6474 +#define SFLASH_ST_BP_SHIFT 2
6475 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6476 +
6477 +/* flashcontrol action+opcodes for Atmel flashes */
6478 +#define SFLASH_AT_READ 0x07e8
6479 +#define SFLASH_AT_PAGE_READ 0x07d2
6480 +#define SFLASH_AT_BUF1_READ
6481 +#define SFLASH_AT_BUF2_READ
6482 +#define SFLASH_AT_STATUS 0x01d7
6483 +#define SFLASH_AT_BUF1_WRITE 0x0384
6484 +#define SFLASH_AT_BUF2_WRITE 0x0387
6485 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6486 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6487 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6488 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6489 +#define SFLASH_AT_PAGE_ERASE 0x0281
6490 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6491 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6492 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6493 +#define SFLASH_AT_BUF1_LOAD 0x0253
6494 +#define SFLASH_AT_BUF2_LOAD 0x0255
6495 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6496 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6497 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6498 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6499 +
6500 +/* Status register bits for Atmel flashes */
6501 +#define SFLASH_AT_READY 0x80
6502 +#define SFLASH_AT_MISMATCH 0x40
6503 +#define SFLASH_AT_ID_MASK 0x38
6504 +#define SFLASH_AT_ID_SHIFT 3
6505 +
6506 +/* OTP regions */
6507 +#define OTP_HW_REGION OTPS_HW_PROTECT
6508 +#define OTP_SW_REGION OTPS_SW_PROTECT
6509 +#define OTP_CID_REGION OTPS_CID_PROTECT
6510 +
6511 +/* OTP regions (Byte offsets from otp size) */
6512 +#define OTP_SWLIM_OFF (-8)
6513 +#define OTP_CIDBASE_OFF 0
6514 +#define OTP_CIDLIM_OFF 8
6515 +
6516 +/* Predefined OTP words (Word offset from otp size) */
6517 +#define OTP_BOUNDARY_OFF (-4)
6518 +#define OTP_HWSIGN_OFF (-3)
6519 +#define OTP_SWSIGN_OFF (-2)
6520 +#define OTP_CIDSIGN_OFF (-1)
6521 +
6522 +#define OTP_CID_OFF 0
6523 +#define OTP_PKG_OFF 1
6524 +#define OTP_FID_OFF 2
6525 +#define OTP_RSV_OFF 3
6526 +#define OTP_LIM_OFF 4
6527 +
6528 +#define OTP_SIGNATURE 0x578a
6529 +#define OTP_MAGIC 0x4e56
6530 +
6531 +/*
6532 + * These are the UART port assignments, expressed as offsets from the base
6533 + * register. These assignments should hold for any serial port based on
6534 + * a 8250, 16450, or 16550(A).
6535 + */
6536 +
6537 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
6538 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
6539 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
6540 +#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
6541 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
6542 +#define UART_IIR 2 /* In: Interrupt Identity Register */
6543 +#define UART_FCR 2 /* Out: FIFO Control Register */
6544 +#define UART_LCR 3 /* Out: Line Control Register */
6545 +#define UART_MCR 4 /* Out: Modem Control Register */
6546 +#define UART_LSR 5 /* In: Line Status Register */
6547 +#define UART_MSR 6 /* In: Modem Status Register */
6548 +#define UART_SCR 7 /* I/O: Scratch Register */
6549 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
6550 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
6551 +#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
6552 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
6553 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
6554 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
6555 +#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
6556 +
6557 +/* Interrupt Enable Register (IER) bits */
6558 +#define UART_IER_EDSSI 8 /* enable modem status interrupt */
6559 +#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
6560 +#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
6561 +#define UART_IER_ERBFI 1 /* enable data available interrupt */
6562 +
6563 +#endif /* _SBCHIPC_H */
6564 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6565 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6566 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-04-27 22:14:11.000000000 +0200
6567 @@ -0,0 +1,369 @@
6568 +/*
6569 + * Broadcom SiliconBackplane hardware register definitions.
6570 + *
6571 + * Copyright 2006, Broadcom Corporation
6572 + * All Rights Reserved.
6573 + *
6574 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6575 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6576 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6577 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6578 + *
6579 + * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
6580 + */
6581 +
6582 +#ifndef _SBCONFIG_H
6583 +#define _SBCONFIG_H
6584 +
6585 +/* cpp contortions to concatenate w/arg prescan */
6586 +#ifndef PAD
6587 +#define _PADLINE(line) pad ## line
6588 +#define _XSTR(line) _PADLINE(line)
6589 +#define PAD _XSTR(__LINE__)
6590 +#endif
6591 +
6592 +/*
6593 + * SiliconBackplane Address Map.
6594 + * All regions may not exist on all chips.
6595 + */
6596 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6597 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6598 +#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
6599 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6600 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6601 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6602 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6603 +
6604 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6605 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6606 +
6607 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6608 +#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
6609 +#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
6610 +
6611 +#define SB_ROM 0x20000000 /* ARM ROM */
6612 +#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
6613 +#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
6614 +#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
6615 +
6616 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6617 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6618 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
6619 + * (2 ZettaBytes), low 32 bits
6620 + */
6621 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
6622 + * (2 ZettaBytes), high 32 bits
6623 + */
6624 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6625 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6626 +
6627 +
6628 +/* enumeration space related defs */
6629 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6630 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6631 +#define SB_MAXFUNCS 4 /* max. # functions per core */
6632 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6633 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6634 +
6635 +/* mips address */
6636 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6637 +
6638 +/*
6639 + * Sonics Configuration Space Registers.
6640 + */
6641 +#define SBIPSFLAG 0x08
6642 +#define SBTPSFLAG 0x18
6643 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6644 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6645 +#define SBADMATCH3 0x60
6646 +#define SBADMATCH2 0x68
6647 +#define SBADMATCH1 0x70
6648 +#define SBIMSTATE 0x90
6649 +#define SBINTVEC 0x94
6650 +#define SBTMSTATELOW 0x98
6651 +#define SBTMSTATEHIGH 0x9c
6652 +#define SBBWA0 0xa0
6653 +#define SBIMCONFIGLOW 0xa8
6654 +#define SBIMCONFIGHIGH 0xac
6655 +#define SBADMATCH0 0xb0
6656 +#define SBTMCONFIGLOW 0xb8
6657 +#define SBTMCONFIGHIGH 0xbc
6658 +#define SBBCONFIG 0xc0
6659 +#define SBBSTATE 0xc8
6660 +#define SBACTCNFG 0xd8
6661 +#define SBFLAGST 0xe8
6662 +#define SBIDLOW 0xf8
6663 +#define SBIDHIGH 0xfc
6664 +
6665 +/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
6666 + * a few registers *below* that line. I think it would be very confusing to try
6667 + * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
6668 + */
6669 +
6670 +#define SBIMERRLOGA 0xea8
6671 +#define SBIMERRLOG 0xeb0
6672 +#define SBTMPORTCONNID0 0xed8
6673 +#define SBTMPORTLOCK0 0xef8
6674 +
6675 +#ifndef _LANGUAGE_ASSEMBLY
6676 +
6677 +typedef volatile struct _sbconfig {
6678 + uint32 PAD[2];
6679 + uint32 sbipsflag; /* initiator port ocp slave flag */
6680 + uint32 PAD[3];
6681 + uint32 sbtpsflag; /* target port ocp slave flag */
6682 + uint32 PAD[11];
6683 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6684 + uint32 PAD;
6685 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6686 + uint32 PAD[3];
6687 + uint32 sbadmatch3; /* address match3 */
6688 + uint32 PAD;
6689 + uint32 sbadmatch2; /* address match2 */
6690 + uint32 PAD;
6691 + uint32 sbadmatch1; /* address match1 */
6692 + uint32 PAD[7];
6693 + uint32 sbimstate; /* initiator agent state */
6694 + uint32 sbintvec; /* interrupt mask */
6695 + uint32 sbtmstatelow; /* target state */
6696 + uint32 sbtmstatehigh; /* target state */
6697 + uint32 sbbwa0; /* bandwidth allocation table0 */
6698 + uint32 PAD;
6699 + uint32 sbimconfiglow; /* initiator configuration */
6700 + uint32 sbimconfighigh; /* initiator configuration */
6701 + uint32 sbadmatch0; /* address match0 */
6702 + uint32 PAD;
6703 + uint32 sbtmconfiglow; /* target configuration */
6704 + uint32 sbtmconfighigh; /* target configuration */
6705 + uint32 sbbconfig; /* broadcast configuration */
6706 + uint32 PAD;
6707 + uint32 sbbstate; /* broadcast state */
6708 + uint32 PAD[3];
6709 + uint32 sbactcnfg; /* activate configuration */
6710 + uint32 PAD[3];
6711 + uint32 sbflagst; /* current sbflags */
6712 + uint32 PAD[3];
6713 + uint32 sbidlow; /* identification */
6714 + uint32 sbidhigh; /* identification */
6715 +} sbconfig_t;
6716 +
6717 +#endif /* _LANGUAGE_ASSEMBLY */
6718 +
6719 +/* sbipsflag */
6720 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6721 +#define SBIPS_INT1_SHIFT 0
6722 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6723 +#define SBIPS_INT2_SHIFT 8
6724 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6725 +#define SBIPS_INT3_SHIFT 16
6726 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6727 +#define SBIPS_INT4_SHIFT 24
6728 +
6729 +/* sbtpsflag */
6730 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6731 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6732 +
6733 +/* sbtmerrlog */
6734 +#define SBTMEL_CM 0x00000007 /* command */
6735 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6736 +#define SBTMEL_EC 0x0f000000 /* error code */
6737 +#define SBTMEL_ME 0x80000000 /* multiple error */
6738 +
6739 +/* sbimstate */
6740 +#define SBIM_PC 0xf /* pipecount */
6741 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6742 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6743 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6744 +#define SBIM_AP_TK 0x20 /* use token only */
6745 +#define SBIM_AP_RSV 0x30 /* reserved */
6746 +#define SBIM_IBE 0x20000 /* inbanderror */
6747 +#define SBIM_TO 0x40000 /* timeout */
6748 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6749 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6750 +
6751 +/* sbtmstatelow */
6752 +#define SBTML_RESET 0x1 /* reset */
6753 +#define SBTML_REJ_MASK 0x6 /* reject */
6754 +#define SBTML_REJ_SHIFT 1
6755 +#define SBTML_CLK 0x10000 /* clock enable */
6756 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6757 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6758 +#define SBTML_PE 0x40000000 /* pme enable */
6759 +#define SBTML_BE 0x80000000 /* bist enable */
6760 +
6761 +/* sbtmstatehigh */
6762 +#define SBTMH_SERR 0x1 /* serror */
6763 +#define SBTMH_INT 0x2 /* interrupt */
6764 +#define SBTMH_BUSY 0x4 /* busy */
6765 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6766 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6767 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
6768 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6769 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6770 +#define SBTMH_BISTD 0x80000000 /* bist done */
6771 +
6772 +
6773 +/* sbbwa0 */
6774 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6775 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6776 +#define SBBWA_TAB1_SHIFT 16
6777 +
6778 +/* sbimconfiglow */
6779 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6780 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6781 +#define SBIMCL_RTO_SHIFT 4
6782 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6783 +#define SBIMCL_CID_SHIFT 16
6784 +
6785 +/* sbimconfighigh */
6786 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6787 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6788 +#define SBIMCH_TEM_SHIFT 4
6789 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6790 +#define SBIMCH_BEM_SHIFT 6
6791 +
6792 +/* sbadmatch0 */
6793 +#define SBAM_TYPE_MASK 0x3 /* address type */
6794 +#define SBAM_AD64 0x4 /* reserved */
6795 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6796 +#define SBAM_ADINT0_SHIFT 3
6797 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6798 +#define SBAM_ADINT1_SHIFT 3
6799 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6800 +#define SBAM_ADINT2_SHIFT 3
6801 +#define SBAM_ADEN 0x400 /* enable */
6802 +#define SBAM_ADNEG 0x800 /* negative decode */
6803 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6804 +#define SBAM_BASE0_SHIFT 8
6805 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6806 +#define SBAM_BASE1_SHIFT 12
6807 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6808 +#define SBAM_BASE2_SHIFT 16
6809 +
6810 +/* sbtmconfiglow */
6811 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6812 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6813 +#define SBTMCL_CO_SHIFT 11
6814 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6815 +#define SBTMCL_IF_SHIFT 18
6816 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6817 +#define SBTMCL_IM_SHIFT 24
6818 +
6819 +/* sbtmconfighigh */
6820 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6821 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6822 +#define SBTMCH_RM_SHIFT 2
6823 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6824 +#define SBTMCH_SM_SHIFT 4
6825 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6826 +#define SBTMCH_EM_SHIFT 8
6827 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6828 +#define SBTMCH_IM_SHIFT 10
6829 +
6830 +/* sbbconfig */
6831 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6832 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6833 +#define SBBC_MAX0_SHIFT 16
6834 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6835 +#define SBBC_MAX1_SHIFT 20
6836 +
6837 +/* sbbstate */
6838 +#define SBBS_SRD 0x1 /* st reg disable */
6839 +#define SBBS_HRD 0x2 /* hold reg disable */
6840 +
6841 +/* sbidlow */
6842 +#define SBIDL_CS_MASK 0x3 /* config space */
6843 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6844 +#define SBIDL_AR_SHIFT 3
6845 +#define SBIDL_SYNCH 0x40 /* sync */
6846 +#define SBIDL_INIT 0x80 /* initiator */
6847 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6848 +#define SBIDL_MINLAT_SHIFT 8
6849 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6850 +#define SBIDL_MAXLAT_SHIFT 12
6851 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6852 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6853 +#define SBIDL_CW_SHIFT 18
6854 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6855 +#define SBIDL_TP_SHIFT 20
6856 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6857 +#define SBIDL_IP_SHIFT 24
6858 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6859 +#define SBIDL_RV_SHIFT 28
6860 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
6861 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
6862 +
6863 +/* sbidhigh */
6864 +#define SBIDH_RC_MASK 0x000f /* revision code */
6865 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
6866 +#define SBIDH_RCE_SHIFT 8
6867 +#define SBCOREREV(sbidh) \
6868 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
6869 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
6870 +#define SBIDH_CC_SHIFT 4
6871 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
6872 +#define SBIDH_VC_SHIFT 16
6873 +
6874 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
6875 +
6876 +/* vendor codes */
6877 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
6878 +
6879 +/* core codes */
6880 +#define SB_NODEV 0x700 /* Invalid coreid */
6881 +#define SB_CC 0x800 /* chipcommon core */
6882 +#define SB_ILINE20 0x801 /* iline20 core */
6883 +#define SB_SDRAM 0x803 /* sdram core */
6884 +#define SB_PCI 0x804 /* pci core */
6885 +#define SB_MIPS 0x805 /* mips core */
6886 +#define SB_ENET 0x806 /* enet mac core */
6887 +#define SB_CODEC 0x807 /* v90 codec core */
6888 +#define SB_USB 0x808 /* usb 1.1 host/device core */
6889 +#define SB_ADSL 0x809 /* ADSL core */
6890 +#define SB_ILINE100 0x80a /* iline100 core */
6891 +#define SB_IPSEC 0x80b /* ipsec core */
6892 +#define SB_PCMCIA 0x80d /* pcmcia core */
6893 +#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
6894 +#define SB_SOCRAM 0x80e /* internal memory core */
6895 +#define SB_MEMC 0x80f /* memc sdram core */
6896 +#define SB_EXTIF 0x811 /* external interface core */
6897 +#define SB_D11 0x812 /* 802.11 MAC core */
6898 +#define SB_MIPS33 0x816 /* mips3302 core */
6899 +#define SB_USB11H 0x817 /* usb 1.1 host core */
6900 +#define SB_USB11D 0x818 /* usb 1.1 device core */
6901 +#define SB_USB20H 0x819 /* usb 2.0 host core */
6902 +#define SB_USB20D 0x81a /* usb 2.0 device core */
6903 +#define SB_SDIOH 0x81b /* sdio host core */
6904 +#define SB_ROBO 0x81c /* roboswitch core */
6905 +#define SB_ATA100 0x81d /* parallel ATA core */
6906 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
6907 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
6908 +#define SB_PCIE 0x820 /* pci express core */
6909 +#define SB_MIMO 0x821 /* MIMO phy core */
6910 +#define SB_SRAMC 0x822 /* SRAM controller core */
6911 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
6912 +#define SB_ARM11 0x824 /* ARM 1176 core */
6913 +#define SB_ARM7 0x825 /* ARM 7tdmi core */
6914 +
6915 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
6916 +
6917 +/* Not really related to Silicon Backplane, but a couple of software
6918 + * conventions for the use the flash space:
6919 + */
6920 +
6921 +/* Minumum amount of flash we support */
6922 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
6923 +
6924 +/* A boot/binary may have an embedded block that describes its size */
6925 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
6926 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
6927 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
6928 +#define BISZ_TXTST_IDX 1 /* 1: text start */
6929 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
6930 +#define BISZ_DATAST_IDX 3 /* 3: text start */
6931 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
6932 +#define BISZ_BSSST_IDX 5 /* 5: text start */
6933 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
6934 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
6935 +
6936 +#endif /* _SBCONFIG_H */
6937 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
6938 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
6939 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-04-27 22:13:03.000000000 +0200
6940 @@ -0,0 +1,243 @@
6941 +/*
6942 + * Hardware-specific External Interface I/O core definitions
6943 + * for the BCM47xx family of SiliconBackplane-based chips.
6944 + *
6945 + * The External Interface core supports a total of three external chip selects
6946 + * supporting external interfaces. One of the external chip selects is
6947 + * used for Flash, one is used for PCMCIA, and the other may be
6948 + * programmed to support either a synchronous interface or an
6949 + * asynchronous interface. The asynchronous interface can be used to
6950 + * support external devices such as UARTs and the BCM2019 Bluetooth
6951 + * baseband processor.
6952 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
6953 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
6954 + *
6955 + * Copyright 2006, Broadcom Corporation
6956 + * All Rights Reserved.
6957 + *
6958 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6959 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6960 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6961 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6962 + *
6963 + * $Id: sbextif.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
6964 + */
6965 +
6966 +#ifndef _SBEXTIF_H
6967 +#define _SBEXTIF_H
6968 +
6969 +/* external interface address space */
6970 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
6971 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
6972 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
6973 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
6974 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6975 +
6976 +/* cpp contortions to concatenate w/arg prescan */
6977 +#ifndef PAD
6978 +#define _PADLINE(line) pad ## line
6979 +#define _XSTR(line) _PADLINE(line)
6980 +#define PAD _XSTR(__LINE__)
6981 +#endif /* PAD */
6982 +
6983 +/*
6984 + * The multiple instances of output and output enable registers
6985 + * are present to allow driver software for multiple cores to control
6986 + * gpio outputs without needing to share a single register pair.
6987 + */
6988 +struct gpiouser {
6989 + uint32 out;
6990 + uint32 outen;
6991 +};
6992 +#define NGPIOUSER 5
6993 +
6994 +typedef volatile struct {
6995 + uint32 corecontrol;
6996 + uint32 extstatus;
6997 + uint32 PAD[2];
6998 +
6999 + /* pcmcia control registers */
7000 + uint32 pcmcia_config;
7001 + uint32 pcmcia_memwait;
7002 + uint32 pcmcia_attrwait;
7003 + uint32 pcmcia_iowait;
7004 +
7005 + /* programmable interface control registers */
7006 + uint32 prog_config;
7007 + uint32 prog_waitcount;
7008 +
7009 + /* flash control registers */
7010 + uint32 flash_config;
7011 + uint32 flash_waitcount;
7012 + uint32 PAD[4];
7013 +
7014 + uint32 watchdog;
7015 +
7016 + /* clock control */
7017 + uint32 clockcontrol_n;
7018 + uint32 clockcontrol_sb;
7019 + uint32 clockcontrol_pci;
7020 + uint32 clockcontrol_mii;
7021 + uint32 PAD[3];
7022 +
7023 + /* gpio */
7024 + uint32 gpioin;
7025 + struct gpiouser gpio[NGPIOUSER];
7026 + uint32 PAD;
7027 + uint32 ejtagouten;
7028 + uint32 gpiointpolarity;
7029 + uint32 gpiointmask;
7030 + uint32 PAD[153];
7031 +
7032 + uint8 uartdata;
7033 + uint8 PAD[3];
7034 + uint8 uartimer;
7035 + uint8 PAD[3];
7036 + uint8 uartfcr;
7037 + uint8 PAD[3];
7038 + uint8 uartlcr;
7039 + uint8 PAD[3];
7040 + uint8 uartmcr;
7041 + uint8 PAD[3];
7042 + uint8 uartlsr;
7043 + uint8 PAD[3];
7044 + uint8 uartmsr;
7045 + uint8 PAD[3];
7046 + uint8 uartscratch;
7047 + uint8 PAD[3];
7048 +} extifregs_t;
7049 +
7050 +/* corecontrol */
7051 +#define CC_UE (1 << 0) /* uart enable */
7052 +
7053 +/* extstatus */
7054 +#define ES_EM (1 << 0) /* endian mode (ro) */
7055 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7056 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7057 +
7058 +/* gpio bit mask */
7059 +#define GPIO_BIT0 (1 << 0)
7060 +#define GPIO_BIT1 (1 << 1)
7061 +#define GPIO_BIT2 (1 << 2)
7062 +#define GPIO_BIT3 (1 << 3)
7063 +#define GPIO_BIT4 (1 << 4)
7064 +#define GPIO_BIT5 (1 << 5)
7065 +#define GPIO_BIT6 (1 << 6)
7066 +#define GPIO_BIT7 (1 << 7)
7067 +
7068 +
7069 +/* pcmcia/prog/flash_config */
7070 +#define CF_EN (1 << 0) /* enable */
7071 +#define CF_EM_MASK 0xe /* mode */
7072 +#define CF_EM_SHIFT 1
7073 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7074 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7075 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7076 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7077 +#define CF_BS (1 << 5) /* byteswap */
7078 +#define CF_CD_MASK 0xc0 /* clock divider */
7079 +#define CF_CD_SHIFT 6
7080 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7081 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7082 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7083 +#define CF_CE (1 << 8) /* clock enable */
7084 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7085 +
7086 +/* pcmcia_memwait */
7087 +#define PM_W0_MASK 0x3f /* waitcount0 */
7088 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7089 +#define PM_W1_SHIFT 8
7090 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7091 +#define PM_W2_SHIFT 16
7092 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7093 +#define PM_W3_SHIFT 24
7094 +
7095 +/* pcmcia_attrwait */
7096 +#define PA_W0_MASK 0x3f /* waitcount0 */
7097 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7098 +#define PA_W1_SHIFT 8
7099 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7100 +#define PA_W2_SHIFT 16
7101 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7102 +#define PA_W3_SHIFT 24
7103 +
7104 +/* pcmcia_iowait */
7105 +#define PI_W0_MASK 0x3f /* waitcount0 */
7106 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7107 +#define PI_W1_SHIFT 8
7108 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7109 +#define PI_W2_SHIFT 16
7110 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7111 +#define PI_W3_SHIFT 24
7112 +
7113 +/* prog_waitcount */
7114 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7115 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7116 +#define PW_W1_SHIFT 8
7117 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7118 +#define PW_W2_SHIFT 16
7119 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7120 +#define PW_W3_SHIFT 24
7121 +
7122 +#define PW_W0 0x0000000c
7123 +#define PW_W1 0x00000a00
7124 +#define PW_W2 0x00020000
7125 +#define PW_W3 0x01000000
7126 +
7127 +/* flash_waitcount */
7128 +#define FW_W0_MASK 0x1f /* waitcount0 */
7129 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7130 +#define FW_W1_SHIFT 8
7131 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7132 +#define FW_W2_SHIFT 16
7133 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7134 +#define FW_W3_SHIFT 24
7135 +
7136 +/* watchdog */
7137 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7138 +
7139 +/* clockcontrol_n */
7140 +#define CN_N1_MASK 0x3f /* n1 control */
7141 +#define CN_N2_MASK 0x3f00 /* n2 control */
7142 +#define CN_N2_SHIFT 8
7143 +
7144 +/* clockcontrol_sb/pci/mii */
7145 +#define CC_M1_MASK 0x3f /* m1 control */
7146 +#define CC_M2_MASK 0x3f00 /* m2 control */
7147 +#define CC_M2_SHIFT 8
7148 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7149 +#define CC_M3_SHIFT 16
7150 +#define CC_MC_MASK 0x1f000000 /* mux control */
7151 +#define CC_MC_SHIFT 24
7152 +
7153 +/* Clock control default values */
7154 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7155 +#define CC_DEF_100 0x04020011
7156 +#define CC_DEF_33 0x11030011
7157 +#define CC_DEF_25 0x11050011
7158 +
7159 +/* Clock control values for 125Mhz */
7160 +#define CC_125_N 0x0802
7161 +#define CC_125_M 0x04020009
7162 +#define CC_125_M25 0x11090009
7163 +#define CC_125_M33 0x11090005
7164 +
7165 +/* Clock control magic field values */
7166 +#define CC_F6_2 0x02 /* A factor of 2 in */
7167 +#define CC_F6_3 0x03 /* 6-bit fields like */
7168 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7169 +#define CC_F6_5 0x09
7170 +#define CC_F6_6 0x11
7171 +#define CC_F6_7 0x21
7172 +
7173 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7174 +
7175 +#define CC_MC_BYPASS 0x08
7176 +#define CC_MC_M1 0x04
7177 +#define CC_MC_M1M2 0x02
7178 +#define CC_MC_M1M2M3 0x01
7179 +#define CC_MC_M1M3 0x11
7180 +
7181 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7182 +
7183 +#endif /* _SBEXTIF_H */
7184 diff -urN linux.old/arch/mips/bcm947xx/include/sbhndmips.h linux.dev/arch/mips/bcm947xx/include/sbhndmips.h
7185 --- linux.old/arch/mips/bcm947xx/include/sbhndmips.h 1970-01-01 01:00:00.000000000 +0100
7186 +++ linux.dev/arch/mips/bcm947xx/include/sbhndmips.h 2006-04-27 20:43:56.000000000 +0200
7187 @@ -0,0 +1,47 @@
7188 +/*
7189 + * Broadcom SiliconBackplane MIPS definitions
7190 + *
7191 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7192 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7193 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7194 + * interface. The core revision is stored in the SB ID register in SB
7195 + * configuration space.
7196 + *
7197 + * Copyright 2006, Broadcom Corporation
7198 + * All Rights Reserved.
7199 + *
7200 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7201 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7202 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7203 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7204 + *
7205 + * $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
7206 + */
7207 +
7208 +#ifndef _sbhndmips_h_
7209 +#define _sbhndmips_h_
7210 +
7211 +#include <mipsinc.h>
7212 +
7213 +#ifndef _LANGUAGE_ASSEMBLY
7214 +
7215 +/* cpp contortions to concatenate w/arg prescan */
7216 +#ifndef PAD
7217 +#define _PADLINE(line) pad ## line
7218 +#define _XSTR(line) _PADLINE(line)
7219 +#define PAD _XSTR(__LINE__)
7220 +#endif /* PAD */
7221 +
7222 +typedef volatile struct {
7223 + uint32 corecontrol;
7224 + uint32 PAD[2];
7225 + uint32 biststatus;
7226 + uint32 PAD[4];
7227 + uint32 intstatus;
7228 + uint32 intmask;
7229 + uint32 timer;
7230 +} mipsregs_t;
7231 +
7232 +#endif /* _LANGUAGE_ASSEMBLY */
7233 +
7234 +#endif /* _sbhndmips_h_ */
7235 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7236 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7237 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-04-27 22:12:41.000000000 +0200
7238 @@ -0,0 +1,147 @@
7239 +/*
7240 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7241 + *
7242 + * Copyright 2006, Broadcom Corporation
7243 + * All Rights Reserved.
7244 + *
7245 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7246 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7247 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7248 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7249 + *
7250 + * $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
7251 + */
7252 +
7253 +#ifndef _SBMEMC_H
7254 +#define _SBMEMC_H
7255 +
7256 +#ifdef _LANGUAGE_ASSEMBLY
7257 +
7258 +#define MEMC_CONTROL 0x00
7259 +#define MEMC_CONFIG 0x04
7260 +#define MEMC_REFRESH 0x08
7261 +#define MEMC_BISTSTAT 0x0c
7262 +#define MEMC_MODEBUF 0x10
7263 +#define MEMC_BKCLS 0x14
7264 +#define MEMC_PRIORINV 0x18
7265 +#define MEMC_DRAMTIM 0x1c
7266 +#define MEMC_INTSTAT 0x20
7267 +#define MEMC_INTMASK 0x24
7268 +#define MEMC_INTINFO 0x28
7269 +#define MEMC_NCDLCTL 0x30
7270 +#define MEMC_RDNCDLCOR 0x34
7271 +#define MEMC_WRNCDLCOR 0x38
7272 +#define MEMC_MISCDLYCTL 0x3c
7273 +#define MEMC_DQSGATENCDL 0x40
7274 +#define MEMC_SPARE 0x44
7275 +#define MEMC_TPADDR 0x48
7276 +#define MEMC_TPDATA 0x4c
7277 +#define MEMC_BARRIER 0x50
7278 +#define MEMC_CORE 0x54
7279 +
7280 +#else /* !_LANGUAGE_ASSEMBLY */
7281 +
7282 +/* Sonics side: MEMC core registers */
7283 +typedef volatile struct sbmemcregs {
7284 + uint32 control;
7285 + uint32 config;
7286 + uint32 refresh;
7287 + uint32 biststat;
7288 + uint32 modebuf;
7289 + uint32 bkcls;
7290 + uint32 priorinv;
7291 + uint32 dramtim;
7292 + uint32 intstat;
7293 + uint32 intmask;
7294 + uint32 intinfo;
7295 + uint32 reserved1;
7296 + uint32 ncdlctl;
7297 + uint32 rdncdlcor;
7298 + uint32 wrncdlcor;
7299 + uint32 miscdlyctl;
7300 + uint32 dqsgatencdl;
7301 + uint32 spare;
7302 + uint32 tpaddr;
7303 + uint32 tpdata;
7304 + uint32 barrier;
7305 + uint32 core;
7306 +} sbmemcregs_t;
7307 +
7308 +#endif /* _LANGUAGE_ASSEMBLY */
7309 +
7310 +/* MEMC Core Init values (OCP ID 0x80f) */
7311 +
7312 +/* For sdr: */
7313 +#define MEMC_SD_CONFIG_INIT 0x00048000
7314 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7315 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7316 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7317 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7318 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7319 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7320 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7321 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7322 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7323 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7324 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7325 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7326 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7327 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7328 +
7329 +
7330 +/* This is for SDRM8X8X4 */
7331 +#define MEMC_SDR_INIT 0x0008
7332 +#define MEMC_SDR_MODE 0x32
7333 +#define MEMC_SDR_NCDL 0x00020032
7334 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7335 +
7336 +/* For ddr: */
7337 +#define MEMC_CONFIG_INIT 0x00048000
7338 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7339 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7340 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7341 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
7342 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7343 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7344 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7345 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7346 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7347 +#define MEMC_NCDLCTL_INIT 0x00002001
7348 +#define MEMC_CONTROL_INIT0 0x00000002
7349 +#define MEMC_CONTROL_INIT1 0x00000008
7350 +#define MEMC_MODEBUF_INIT0 0x00004000
7351 +#define MEMC_CONTROL_INIT2 0x00000010
7352 +#define MEMC_MODEBUF_INIT1 0x00000100
7353 +#define MEMC_CONTROL_INIT3 0x00000010
7354 +#define MEMC_CONTROL_INIT4 0x00000008
7355 +#define MEMC_REFRESH_INIT 0x0000840f
7356 +#define MEMC_CONTROL_INIT5 0x00000004
7357 +#define MEMC_MODEBUF_INIT2 0x00000000
7358 +#define MEMC_CONTROL_INIT6 0x00000010
7359 +#define MEMC_CONTROL_INIT7 0x00000001
7360 +
7361 +
7362 +/* This is for DDRM16X16X2 */
7363 +#define MEMC_DDR_INIT 0x0009
7364 +#define MEMC_DDR_MODE 0x62
7365 +#define MEMC_DDR_NCDL 0x0005050a
7366 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7367 +
7368 +/* mask for sdr/ddr calibration registers */
7369 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7370 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7371 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7372 +
7373 +/* masks for miscdlyctl registers */
7374 +#define MEMC_MISC_SM_MASK 0x30000000
7375 +#define MEMC_MISC_SM_SHIFT 28
7376 +#define MEMC_MISC_SD_MASK 0x0f000000
7377 +#define MEMC_MISC_SD_SHIFT 24
7378 +
7379 +/* hw threshhold for calculating wr/rd for sdr memc */
7380 +#define MEMC_CD_THRESHOLD 128
7381 +
7382 +/* Low bit of init register says if memc is ddr or sdr */
7383 +#define MEMC_CONFIG_DDR 0x00000001
7384 +
7385 +#endif /* _SBMEMC_H */
7386 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
7387 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7388 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-05-02 17:20:14.000000000 +0200
7389 @@ -0,0 +1,114 @@
7390 +/*
7391 + * HND SiliconBackplane PCI core hardware definitions.
7392 + *
7393 + * Copyright 2006, Broadcom Corporation
7394 + * All Rights Reserved.
7395 + *
7396 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7397 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7398 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7399 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7400 + *
7401 + * $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
7402 + */
7403 +
7404 +#ifndef _sbpci_h_
7405 +#define _sbpci_h_
7406 +
7407 +#ifndef _LANGUAGE_ASSEMBLY
7408 +
7409 +/* cpp contortions to concatenate w/arg prescan */
7410 +#ifndef PAD
7411 +#define _PADLINE(line) pad ## line
7412 +#define _XSTR(line) _PADLINE(line)
7413 +#define PAD _XSTR(__LINE__)
7414 +#endif
7415 +
7416 +/* Sonics side: PCI core and host control registers */
7417 +typedef struct sbpciregs {
7418 + uint32 control; /* PCI control */
7419 + uint32 PAD[3];
7420 + uint32 arbcontrol; /* PCI arbiter control */
7421 + uint32 PAD[3];
7422 + uint32 intstatus; /* Interrupt status */
7423 + uint32 intmask; /* Interrupt mask */
7424 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7425 + uint32 PAD[9];
7426 + uint32 bcastaddr; /* Sonics broadcast address */
7427 + uint32 bcastdata; /* Sonics broadcast data */
7428 + uint32 PAD[2];
7429 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7430 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7431 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7432 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7433 + uint32 PAD[36];
7434 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7435 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7436 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7437 + uint32 PAD[189];
7438 + uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
7439 + uint16 sprom[36]; /* SPROM shadow Area */
7440 + uint32 PAD[46];
7441 +} sbpciregs_t;
7442 +
7443 +#endif /* _LANGUAGE_ASSEMBLY */
7444 +
7445 +/* PCI control */
7446 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7447 +#define PCI_RST 0x02 /* Value driven out to pin */
7448 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7449 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7450 +
7451 +/* PCI arbiter control */
7452 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7453 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7454 +/* ParkID - for PCI corerev >= 8 */
7455 +#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
7456 +#define PCI_PARKID_SHIFT 2
7457 +#define PCI_PARKID_EXT0 0 /* External master 0 */
7458 +#define PCI_PARKID_EXT1 1 /* External master 1 */
7459 +#define PCI_PARKID_EXT2 2 /* External master 2 */
7460 +#define PCI_PARKID_INT 3 /* Internal master */
7461 +#define PCI_PARKID_LAST 4 /* Last active master */
7462 +
7463 +/* Interrupt status/mask */
7464 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7465 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7466 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7467 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7468 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7469 +
7470 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7471 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7472 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7473 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7474 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7475 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7476 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7477 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7478 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7479 +
7480 +/* Sonics broadcast address */
7481 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7482 +
7483 +/* Sonics to PCI translation types */
7484 +#define SBTOPCI0_MASK 0xfc000000
7485 +#define SBTOPCI1_MASK 0xfc000000
7486 +#define SBTOPCI2_MASK 0xc0000000
7487 +#define SBTOPCI_MEM 0
7488 +#define SBTOPCI_IO 1
7489 +#define SBTOPCI_CFG0 2
7490 +#define SBTOPCI_CFG1 3
7491 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7492 +#define SBTOPCI_BURST 0x8 /* burst enable */
7493 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7494 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7495 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7496 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7497 +
7498 +/* PCI core index in SROM shadow area */
7499 +#define SRSH_PI_OFFSET 0 /* first word */
7500 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
7501 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
7502 +
7503 +#endif /* _sbpci_h_ */
7504 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
7505 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
7506 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2006-04-27 20:42:22.000000000 +0200
7507 @@ -0,0 +1,200 @@
7508 +/*
7509 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
7510 + *
7511 + * Copyright 2006, Broadcom Corporation
7512 + * All Rights Reserved.
7513 + *
7514 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7515 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7516 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7517 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7518 + *
7519 + * $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
7520 + */
7521 +
7522 +#ifndef _SBPCIE_H
7523 +#define _SBPCIE_H
7524 +
7525 +/* cpp contortions to concatenate w/arg prescan */
7526 +#ifndef PAD
7527 +#define _PADLINE(line) pad ## line
7528 +#define _XSTR(line) _PADLINE(line)
7529 +#define PAD _XSTR(__LINE__)
7530 +#endif
7531 +
7532 +/* PCIE Enumeration space offsets */
7533 +#define PCIE_CORE_CONFIG_OFFSET 0x0
7534 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
7535 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
7536 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
7537 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
7538 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
7539 +#define PCIE_SBCONFIG_OFFSET 0xE00
7540 +
7541 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
7542 +#define PCIE_DEV_BAR0_SIZE 0x4000
7543 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
7544 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
7545 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
7546 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
7547 +
7548 +/* SB side: PCIE core and host control registers */
7549 +typedef struct sbpcieregs {
7550 + uint32 PAD[3];
7551 + uint32 biststatus; /* bist Status: 0x00C */
7552 + uint32 PAD[6];
7553 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
7554 + uint32 PAD[54];
7555 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
7556 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
7557 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
7558 + uint32 PAD[4];
7559 +
7560 + /* pcie core supports in direct access to config space */
7561 + uint32 configaddr; /* pcie config space access: Address field: 0x120 */
7562 + uint32 configdata; /* pcie config space access: Data field: 0x124 */
7563 +
7564 + /* mdio access to serdes */
7565 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
7566 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
7567 +
7568 + /* pcie protocol phy/dllp/tlp register access mechanism */
7569 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
7570 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
7571 +
7572 + uint32 PAD[434];
7573 + uint16 sprom[36]; /* SPROM shadow Area */
7574 +} sbpcieregs_t;
7575 +
7576 +/* SB to PCIE translation masks */
7577 +#define SBTOPCIE0_MASK 0xfc000000
7578 +#define SBTOPCIE1_MASK 0xfc000000
7579 +#define SBTOPCIE2_MASK 0xc0000000
7580 +
7581 +/* Access type bits (0:1) */
7582 +#define SBTOPCIE_MEM 0
7583 +#define SBTOPCIE_IO 1
7584 +#define SBTOPCIE_CFG0 2
7585 +#define SBTOPCIE_CFG1 3
7586 +
7587 +/* Prefetch enable bit 2 */
7588 +#define SBTOPCIE_PF 4
7589 +
7590 +/* Write Burst enable for memory write bit 3 */
7591 +#define SBTOPCIE_WR_BURST 8
7592 +
7593 +/* config access */
7594 +#define CONFIGADDR_FUNC_MASK 0x7000
7595 +#define CONFIGADDR_FUNC_SHF 12
7596 +#define CONFIGADDR_REG_MASK 0x0FFF
7597 +#define CONFIGADDR_REG_SHF 0
7598 +
7599 +/* PCIE protocol regs Indirect Address */
7600 +#define PCIEADDR_PROT_MASK 0x300
7601 +#define PCIEADDR_PROT_SHF 8
7602 +#define PCIEADDR_PL_TLP 0
7603 +#define PCIEADDR_PL_DLLP 1
7604 +#define PCIEADDR_PL_PLP 2
7605 +
7606 +/* PCIE protocol PHY diagnostic registers */
7607 +#define PCIE_PLP_MODEREG 0x200 /* Mode */
7608 +#define PCIE_PLP_STATUSREG 0x204 /* Status */
7609 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
7610 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
7611 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
7612 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
7613 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
7614 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
7615 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
7616 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
7617 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
7618 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
7619 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
7620 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
7621 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
7622 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
7623 +
7624 +/* PCIE protocol DLLP diagnostic registers */
7625 +#define PCIE_DLLP_LCREG 0x100 /* Link Control */
7626 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
7627 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
7628 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
7629 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
7630 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
7631 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
7632 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
7633 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
7634 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
7635 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
7636 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
7637 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
7638 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
7639 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
7640 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
7641 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
7642 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
7643 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
7644 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
7645 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
7646 +
7647 +/* PCIE protocol TLP diagnostic registers */
7648 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
7649 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
7650 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
7651 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
7652 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
7653 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
7654 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
7655 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
7656 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
7657 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
7658 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
7659 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
7660 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
7661 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
7662 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
7663 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
7664 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
7665 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
7666 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
7667 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
7668 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
7669 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
7670 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
7671 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
7672 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
7673 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
7674 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
7675 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
7676 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
7677 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
7678 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
7679 +
7680 +/* MDIO control */
7681 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
7682 +#define MDIOCTL_DIVISOR_VAL 0x2
7683 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
7684 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
7685 +
7686 +/* MDIO Data */
7687 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
7688 +#define MDIODATA_TA 0x00020000 /* Turnaround */
7689 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
7690 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
7691 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
7692 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
7693 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
7694 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
7695 +#define MDIODATA_START 0x40000000 /* start of Transaction */
7696 +
7697 +/* MDIO devices (SERDES modules) */
7698 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
7699 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
7700 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
7701 +
7702 +/* SERDES registers */
7703 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
7704 +#define SERDES_RX_CDR 6 /* CDR */
7705 +#define SERDES_RX_CDRBW 7 /* CDR BW */
7706 +
7707 +#endif /* _SBPCIE_H */
7708 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
7709 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7710 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2006-04-27 20:29:47.000000000 +0200
7711 @@ -0,0 +1,147 @@
7712 +/*
7713 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7714 + *
7715 + * Copyright 2006, Broadcom Corporation
7716 + * All Rights Reserved.
7717 + *
7718 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7719 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7720 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7721 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7722 + *
7723 + * $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
7724 + */
7725 +
7726 +#ifndef _SBPCMCIA_H
7727 +#define _SBPCMCIA_H
7728 +
7729 +
7730 +/* All the addresses that are offsets in attribute space are divided
7731 + * by two to account for the fact that odd bytes are invalid in
7732 + * attribute space and our read/write routines make the space appear
7733 + * as if they didn't exist. Still we want to show the original numbers
7734 + * as documented in the hnd_pcmcia core manual.
7735 + */
7736 +
7737 +/* PCMCIA Function Configuration Registers */
7738 +#define PCMCIA_FCR (0x700 / 2)
7739 +
7740 +#define FCR0_OFF 0
7741 +#define FCR1_OFF (0x40 / 2)
7742 +#define FCR2_OFF (0x80 / 2)
7743 +#define FCR3_OFF (0xc0 / 2)
7744 +
7745 +#define PCMCIA_FCR0 (0x700 / 2)
7746 +#define PCMCIA_FCR1 (0x740 / 2)
7747 +#define PCMCIA_FCR2 (0x780 / 2)
7748 +#define PCMCIA_FCR3 (0x7c0 / 2)
7749 +
7750 +/* Standard PCMCIA FCR registers */
7751 +
7752 +#define PCMCIA_COR 0
7753 +
7754 +#define COR_RST 0x80
7755 +#define COR_LEV 0x40
7756 +#define COR_IRQEN 0x04
7757 +#define COR_BLREN 0x01
7758 +#define COR_FUNEN 0x01
7759 +
7760 +
7761 +#define PCICIA_FCSR (2 / 2)
7762 +#define PCICIA_PRR (4 / 2)
7763 +#define PCICIA_SCR (6 / 2)
7764 +#define PCICIA_ESR (8 / 2)
7765 +
7766 +
7767 +#define PCM_MEMOFF 0x0000
7768 +#define F0_MEMOFF 0x1000
7769 +#define F1_MEMOFF 0x2000
7770 +#define F2_MEMOFF 0x3000
7771 +#define F3_MEMOFF 0x4000
7772 +
7773 +/* Memory base in the function fcr's */
7774 +#define MEM_ADDR0 (0x728 / 2)
7775 +#define MEM_ADDR1 (0x72a / 2)
7776 +#define MEM_ADDR2 (0x72c / 2)
7777 +
7778 +/* PCMCIA base plus Srom access in fcr0: */
7779 +#define PCMCIA_ADDR0 (0x072e / 2)
7780 +#define PCMCIA_ADDR1 (0x0730 / 2)
7781 +#define PCMCIA_ADDR2 (0x0732 / 2)
7782 +
7783 +#define MEM_SEG (0x0734 / 2)
7784 +#define SROM_CS (0x0736 / 2)
7785 +#define SROM_DATAL (0x0738 / 2)
7786 +#define SROM_DATAH (0x073a / 2)
7787 +#define SROM_ADDRL (0x073c / 2)
7788 +#define SROM_ADDRH (0x073e / 2)
7789 +
7790 +/* Values for srom_cs: */
7791 +#define SROM_IDLE 0
7792 +#define SROM_WRITE 1
7793 +#define SROM_READ 2
7794 +#define SROM_WEN 4
7795 +#define SROM_WDS 7
7796 +#define SROM_DONE 8
7797 +
7798 +/* CIS stuff */
7799 +
7800 +/* The CIS stops where the FCRs start */
7801 +#define CIS_SIZE PCMCIA_FCR
7802 +
7803 +/* Standard tuples we know about */
7804 +
7805 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7806 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7807 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7808 +
7809 +/* Function extensions for LANs */
7810 +
7811 +#define LAN_TECH 1 /* Technology type */
7812 +#define LAN_SPEED 2 /* Raw bit rate */
7813 +#define LAN_MEDIA 3 /* Transmission media */
7814 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7815 +#define LAN_CONN 5 /* Connector standard */
7816 +
7817 +
7818 +/* CFTable */
7819 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7820 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7821 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7822 +
7823 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7824 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7825 + */
7826 +
7827 +#define CISTPL_BRCM_HNBU 0x80
7828 +
7829 +/* Subtypes of BRCM_HNBU: */
7830 +
7831 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
7832 +#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
7833 +#define HNBU_BOARDREV 0x02 /* One byte board revision */
7834 +#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
7835 + * or 9 (sromrev > 1) bytes
7836 + */
7837 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
7838 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
7839 +#define HNBU_AA 0x06 /* Antennas available */
7840 +#define HNBU_AG 0x07 /* Antenna gain */
7841 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
7842 +#define HNBU_LEDS 0x09 /* LED set */
7843 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
7844 + * in rev 2
7845 + */
7846 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
7847 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
7848 +#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
7849 +
7850 +
7851 +/* sbtmstatelow */
7852 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7853 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7854 +
7855 +/* sbtmstatehigh */
7856 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7857 +
7858 +#endif /* _SBPCMCIA_H */
7859 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
7860 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7861 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-04-27 20:36:08.000000000 +0200
7862 @@ -0,0 +1,85 @@
7863 +/*
7864 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7865 + *
7866 + * Copyright 2006, Broadcom Corporation
7867 + * All Rights Reserved.
7868 + *
7869 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7870 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7871 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7872 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7873 + *
7874 + * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
7875 + */
7876 +
7877 +#ifndef _SBSDRAM_H
7878 +#define _SBSDRAM_H
7879 +
7880 +#ifndef _LANGUAGE_ASSEMBLY
7881 +
7882 +/* Sonics side: SDRAM core registers */
7883 +typedef volatile struct sbsdramregs {
7884 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7885 + uint32 config; /* Initializes external SDRAM mode register */
7886 + uint32 refresh; /* Controls external SDRAM refresh rate */
7887 + uint32 pad1;
7888 + uint32 pad2;
7889 +} sbsdramregs_t;
7890 +
7891 +/* SDRAM simulation */
7892 +#ifdef RAMSZ
7893 +#define SDRAMSZ RAMSZ
7894 +#else
7895 +#define SDRAMSZ (4 * 1024 * 1024)
7896 +#endif
7897 +
7898 +extern uchar sdrambuf[SDRAMSZ];
7899 +
7900 +#endif /* _LANGUAGE_ASSEMBLY */
7901 +
7902 +/* SDRAM initialization control (initcontrol) register bits */
7903 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7904 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7905 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7906 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7907 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7908 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7909 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7910 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7911 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7912 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7913 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7914 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7915 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7916 +
7917 +/* SDRAM configuration (config) register bits */
7918 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7919 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7920 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7921 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7922 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7923 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7924 +
7925 +/* SDRAM refresh control (refresh) register bits */
7926 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7927 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7928 +
7929 +/* SDRAM Core default Init values (OCP ID 0x803) */
7930 +#define SDRAM_INIT MEM4MX16X2
7931 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7932 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7933 +
7934 +#define MEM1MX16 0x009 /* 2 MB */
7935 +#define MEM1MX16X2 0x409 /* 4 MB */
7936 +#define MEM2MX8X2 0x809 /* 4 MB */
7937 +#define MEM2MX8X4 0xc09 /* 8 MB */
7938 +#define MEM2MX32 0x439 /* 8 MB */
7939 +#define MEM4MX16 0x019 /* 8 MB */
7940 +#define MEM4MX16X2 0x419 /* 16 MB */
7941 +#define MEM8MX8X2 0x819 /* 16 MB */
7942 +#define MEM8MX16 0x829 /* 16 MB */
7943 +#define MEM4MX32 0x429 /* 16 MB */
7944 +#define MEM8MX8X4 0xc19 /* 32 MB */
7945 +#define MEM8MX16X2 0xc29 /* 32 MB */
7946 +
7947 +#endif /* _SBSDRAM_H */
7948 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
7949 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7950 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2006-04-27 22:13:19.000000000 +0200
7951 @@ -0,0 +1,64 @@
7952 +/*
7953 + * BCM47XX Sonics SiliconBackplane embedded ram core
7954 + *
7955 + * Copyright 2006, Broadcom Corporation
7956 + * All Rights Reserved.
7957 + *
7958 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7959 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7960 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7961 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7962 + *
7963 + * $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
7964 + */
7965 +
7966 +#ifndef _SBSOCRAM_H
7967 +#define _SBSOCRAM_H
7968 +
7969 +#define SR_COREINFO 0x00
7970 +#define SR_BWALLOC 0x04
7971 +#define SR_BISTSTAT 0x0c
7972 +#define SR_BANKINDEX 0x10
7973 +#define SR_BANKSTBYCTL 0x14
7974 +
7975 +
7976 +#ifndef _LANGUAGE_ASSEMBLY
7977 +
7978 +/* Memcsocram core registers */
7979 +typedef volatile struct sbsocramregs {
7980 + uint32 coreinfo;
7981 + uint32 bwalloc;
7982 + uint32 PAD;
7983 + uint32 biststat;
7984 + uint32 bankidx;
7985 + uint32 standbyctrl;
7986 +} sbsocramregs_t;
7987 +
7988 +#endif
7989 +
7990 +/* Coreinfo register */
7991 +#define SRCI_PT_MASK 0x30000
7992 +#define SRCI_PT_SHIFT 16
7993 +
7994 +/* In corerev 0, the memory size is 2 to the power of the
7995 + * base plus 16 plus to the contents of the memsize field plus 1.
7996 + */
7997 +#define SRCI_MS0_MASK 0xf
7998 +#define SR_MS0_BASE 16
7999 +
8000 +/*
8001 + * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
8002 + * the memory size is number of banks times bank size.
8003 + * The same applies to rom size.
8004 + */
8005 +#define SRCI_ROMNB_MASK 0xf000
8006 +#define SRCI_ROMNB_SHIFT 12
8007 +#define SRCI_ROMBSZ_MASK 0xf00
8008 +#define SRCI_ROMBSZ_SHIFT 8
8009 +#define SRCI_SRNB_MASK 0xf0
8010 +#define SRCI_SRNB_SHIFT 4
8011 +#define SRCI_SRBSZ_MASK 0xf
8012 +#define SRCI_SRBSZ_SHIFT 0
8013 +
8014 +#define SR_BSZ_BASE 14
8015 +#endif /* _SBSOCRAM_H */
8016 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
8017 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
8018 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-04-27 23:09:25.000000000 +0200
8019 @@ -0,0 +1,150 @@
8020 +/*
8021 + * Misc utility routines for accessing chip-specific features
8022 + * of Broadcom HNBU SiliconBackplane-based chips.
8023 + *
8024 + * Copyright 2006, Broadcom Corporation
8025 + * All Rights Reserved.
8026 + *
8027 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8028 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8029 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8030 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8031 + *
8032 + * $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
8033 + */
8034 +
8035 +#ifndef _sbutils_h_
8036 +#define _sbutils_h_
8037 +
8038 +/*
8039 + * Datastructure to export all chip specific common variables
8040 + * public (read-only) portion of sbutils handle returned by
8041 + * sb_attach()/sb_kattach()
8042 +*/
8043 +
8044 +struct sb_pub {
8045 +
8046 + uint bustype; /* SB_BUS, PCI_BUS */
8047 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
8048 + uint buscorerev; /* buscore rev */
8049 + uint buscoreidx; /* buscore index */
8050 + int ccrev; /* chip common core rev */
8051 + uint boardtype; /* board type */
8052 + uint boardvendor; /* board vendor */
8053 + uint chip; /* chip number */
8054 + uint chiprev; /* chip revision */
8055 + uint chippkg; /* chip package option */
8056 + uint sonicsrev; /* sonics backplane rev */
8057 +};
8058 +
8059 +typedef const struct sb_pub sb_t;
8060 +
8061 +/*
8062 + * Many of the routines below take an 'sbh' handle as their first arg.
8063 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8064 + * At any one time, the sbh is logically focused on one particular sb core
8065 + * (the "current core").
8066 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8067 + */
8068 +
8069 +#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
8070 +/* exported externs */
8071 +extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
8072 + void *sdh, char **vars, uint *varsz);
8073 +extern sb_t *sb_kattach(void);
8074 +extern void sb_detach(sb_t *sbh);
8075 +extern uint sb_chip(sb_t *sbh);
8076 +extern uint sb_chiprev(sb_t *sbh);
8077 +extern uint sb_chipcrev(sb_t *sbh);
8078 +extern uint sb_chippkg(sb_t *sbh);
8079 +extern uint sb_pcirev(sb_t *sbh);
8080 +extern bool sb_war16165(sb_t *sbh);
8081 +extern uint sb_pcmciarev(sb_t *sbh);
8082 +extern uint sb_boardvendor(sb_t *sbh);
8083 +extern uint sb_boardtype(sb_t *sbh);
8084 +extern uint sb_bus(sb_t *sbh);
8085 +extern uint sb_buscoretype(sb_t *sbh);
8086 +extern uint sb_buscorerev(sb_t *sbh);
8087 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8088 +extern uint sb_coreid(sb_t *sbh);
8089 +extern uint sb_coreidx(sb_t *sbh);
8090 +extern uint sb_coreunit(sb_t *sbh);
8091 +extern uint sb_corevendor(sb_t *sbh);
8092 +extern uint sb_corerev(sb_t *sbh);
8093 +extern void *sb_osh(sb_t *sbh);
8094 +extern void sb_setosh(sb_t *sbh, osl_t *osh);
8095 +extern void *sb_coreregs(sb_t *sbh);
8096 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8097 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8098 +extern bool sb_iscoreup(sb_t *sbh);
8099 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8100 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8101 +extern int sb_corebist(sb_t *sbh);
8102 +extern void sb_commit(sb_t *sbh);
8103 +extern uint32 sb_base(uint32 admatch);
8104 +extern uint32 sb_size(uint32 admatch);
8105 +extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
8106 +extern void sb_core_tofixup(sb_t *sbh);
8107 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8108 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8109 +extern uint32 sb_clock(sb_t *sbh);
8110 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8111 +extern void sb_pcmcia_init(sb_t *sbh);
8112 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8113 +extern void *sb_gpiosetcore(sb_t *sbh);
8114 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8115 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8116 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8117 +extern uint32 sb_gpioin(sb_t *sbh);
8118 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8119 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8120 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8121 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8122 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8123 +
8124 +extern void sb_clkctl_init(sb_t *sbh);
8125 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8126 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8127 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8128 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
8129 + void *intrsenabled_fn, void *intr_arg);
8130 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8131 +extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
8132 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
8133 + uint8 *pciheader);
8134 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8135 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8136 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8137 +extern bool sb_backplane64(sb_t *sbh);
8138 +extern void sb_btcgpiowar(sb_t *sbh);
8139 +
8140 +
8141 +
8142 +
8143 +extern bool sb_deviceremoved(sb_t *sbh);
8144 +extern uint32 sb_socram_size(sb_t *sbh);
8145 +
8146 +/*
8147 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8148 +* The returned path is NULL terminated and has trailing '/'.
8149 +* Return 0 on success, nonzero otherwise.
8150 +*/
8151 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8152 +
8153 +/* clkctl xtal what flags */
8154 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8155 +#define PLL 0x2 /* main chip pll */
8156 +
8157 +/* clkctl clk mode */
8158 +#define CLK_FAST 0 /* force fast (pll) clock */
8159 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8160 +
8161 +
8162 +/* GPIO usage priorities */
8163 +#define GPIO_DRV_PRIORITY 0 /* Driver */
8164 +#define GPIO_APP_PRIORITY 1 /* Application */
8165 +
8166 +/* device path */
8167 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8168 +
8169 +#endif /* _sbutils_h_ */
8170 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8171 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8172 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-04-27 22:13:51.000000000 +0200
8173 @@ -0,0 +1,36 @@
8174 +/*
8175 + * Broadcom SiliconBackplane chipcommon serial flash interface
8176 + *
8177 + * Copyright 2006, Broadcom Corporation
8178 + * All Rights Reserved.
8179 + *
8180 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8181 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8182 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8183 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8184 + *
8185 + * $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
8186 + */
8187 +
8188 +#ifndef _sflash_h_
8189 +#define _sflash_h_
8190 +
8191 +#include <typedefs.h>
8192 +#include <sbchipc.h>
8193 +
8194 +struct sflash {
8195 + uint blocksize; /* Block size */
8196 + uint numblocks; /* Number of blocks */
8197 + uint32 type; /* Type */
8198 + uint size; /* Total size in bytes */
8199 +};
8200 +
8201 +/* Utility functions */
8202 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8203 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8204 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8205 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8206 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8207 +extern struct sflash * sflash_init(chipcregs_t *cc);
8208 +
8209 +#endif /* _sflash_h_ */
8210 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8211 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8212 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-04-27 19:24:19.000000000 +0200
8213 @@ -0,0 +1,33 @@
8214 +/*
8215 + * TRX image file header format.
8216 + *
8217 + * Copyright 2005, Broadcom Corporation
8218 + * All Rights Reserved.
8219 + *
8220 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8221 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8222 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8223 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8224 + *
8225 + * $Id$
8226 + */
8227 +
8228 +#include <typedefs.h>
8229 +
8230 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8231 +#define TRX_VERSION 1
8232 +#define TRX_MAX_LEN 0x3A0000
8233 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8234 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8235 +#define TRX_MAX_OFFSET 3
8236 +
8237 +struct trx_header {
8238 + uint32 magic; /* "HDR0" */
8239 + uint32 len; /* Length of file including header */
8240 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8241 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8242 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8243 +};
8244 +
8245 +/* Compatibility */
8246 +typedef struct trx_header TRXHDR, *PTRXHDR;
8247 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8248 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8249 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-04-27 23:47:30.000000000 +0200
8250 @@ -0,0 +1,361 @@
8251 +/*
8252 + * Copyright 2006, Broadcom Corporation
8253 + * All Rights Reserved.
8254 + *
8255 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8256 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8257 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8258 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8259 + * $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
8260 + */
8261 +
8262 +#ifndef _TYPEDEFS_H_
8263 +#define _TYPEDEFS_H_
8264 +
8265 +
8266 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8267 + * typedef file "site_typedefs.h".
8268 + *
8269 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8270 + * section of this file makes inferences about the compile environment
8271 + * based on defined symbols and possibly compiler pragmas.
8272 + *
8273 + * Following these two sections is the "Default Typedefs"
8274 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8275 + * defined. This section has a default set of typedefs and a few
8276 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8277 + */
8278 +
8279 +#ifdef SITE_TYPEDEFS
8280 +
8281 +/*
8282 + * Site Specific Typedefs
8283 + *
8284 + */
8285 +
8286 +#include "site_typedefs.h"
8287 +
8288 +#else
8289 +
8290 +/*
8291 + * Inferred Typedefs
8292 + *
8293 + */
8294 +
8295 +/* Infer the compile environment based on preprocessor symbols and pramas.
8296 + * Override type definitions as needed, and include configuration dependent
8297 + * header files to define types.
8298 + */
8299 +
8300 +#ifdef __cplusplus
8301 +
8302 +#define TYPEDEF_BOOL
8303 +#ifndef FALSE
8304 +#define FALSE false
8305 +#endif
8306 +#ifndef TRUE
8307 +#define TRUE true
8308 +#endif
8309 +
8310 +#else /* ! __cplusplus */
8311 +
8312 +#if defined(_WIN32)
8313 +
8314 +#define TYPEDEF_BOOL
8315 +typedef unsigned char bool; /* consistent w/BOOL */
8316 +
8317 +#endif /* _WIN32 */
8318 +
8319 +#endif /* ! __cplusplus */
8320 +
8321 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8322 +#if defined(_WIN64)
8323 +#include <basetsd.h>
8324 +#define TYPEDEF_UINTPTR
8325 +typedef ULONG_PTR uintptr;
8326 +#endif
8327 +
8328 +
8329 +#if defined(_MINOSL_)
8330 +#define _NEED_SIZE_T_
8331 +#endif
8332 +
8333 +#if defined(_NEED_SIZE_T_)
8334 +typedef long unsigned int size_t;
8335 +#endif
8336 +
8337 +#ifdef __DJGPP__
8338 +typedef long unsigned int size_t;
8339 +#endif /* __DJGPP__ */
8340 +
8341 +#ifdef _MSC_VER /* Microsoft C */
8342 +#define TYPEDEF_INT64
8343 +#define TYPEDEF_UINT64
8344 +typedef signed __int64 int64;
8345 +typedef unsigned __int64 uint64;
8346 +#endif
8347 +
8348 +#if defined(MACOSX)
8349 +#define TYPEDEF_BOOL
8350 +#endif
8351 +
8352 +#if defined(__NetBSD__)
8353 +#define TYPEDEF_ULONG
8354 +#endif
8355 +
8356 +
8357 +#if defined(linux)
8358 +#define TYPEDEF_UINT
8359 +#define TYPEDEF_USHORT
8360 +#define TYPEDEF_ULONG
8361 +#endif
8362 +
8363 +#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
8364 + !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
8365 +#define TYPEDEF_UINT
8366 +#define TYPEDEF_USHORT
8367 +#endif
8368 +
8369 +
8370 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8371 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8372 +#define TYPEDEF_INT64
8373 +#define TYPEDEF_UINT64
8374 +#endif
8375 +
8376 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8377 + * for singned or unsigned
8378 + */
8379 +#if defined(__ICL)
8380 +
8381 +#define TYPEDEF_INT64
8382 +
8383 +#if defined(__STDC__)
8384 +#define TYPEDEF_UINT64
8385 +#endif
8386 +
8387 +#endif /* __ICL */
8388 +
8389 +#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
8390 + !defined(__DJGPP__)
8391 +
8392 +/* pick up ushort & uint from standard types.h */
8393 +#if defined(linux) && defined(__KERNEL__)
8394 +
8395 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8396 +
8397 +#else
8398 +
8399 +#include <sys/types.h>
8400 +
8401 +#endif
8402 +
8403 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
8404 +
8405 +#if defined(MACOSX)
8406 +
8407 +#ifdef __BIG_ENDIAN__
8408 +#define IL_BIGENDIAN
8409 +#else
8410 +#ifdef IL_BIGENDIAN
8411 +#error "IL_BIGENDIAN was defined for a little-endian compile"
8412 +#endif
8413 +#endif /* __BIG_ENDIAN__ */
8414 +
8415 +#if !defined(__cplusplus)
8416 +
8417 +#if defined(__i386__)
8418 +typedef unsigned char bool;
8419 +#else
8420 +typedef unsigned int bool;
8421 +#endif
8422 +#define TYPE_BOOL 1
8423 +enum {
8424 + false = 0,
8425 + true = 1
8426 +};
8427 +
8428 +#if defined(KERNEL)
8429 +#include <IOKit/IOTypes.h>
8430 +#endif /* KERNEL */
8431 +
8432 +#endif /* __cplusplus */
8433 +
8434 +#endif /* MACOSX */
8435 +
8436 +
8437 +/* use the default typedefs in the next section of this file */
8438 +#define USE_TYPEDEF_DEFAULTS
8439 +
8440 +#endif /* SITE_TYPEDEFS */
8441 +
8442 +
8443 +/*
8444 + * Default Typedefs
8445 + *
8446 + */
8447 +
8448 +#ifdef USE_TYPEDEF_DEFAULTS
8449 +#undef USE_TYPEDEF_DEFAULTS
8450 +
8451 +#ifndef TYPEDEF_BOOL
8452 +typedef /* @abstract@ */ unsigned char bool;
8453 +#endif
8454 +
8455 +/* define uchar, ushort, uint, ulong */
8456 +
8457 +#ifndef TYPEDEF_UCHAR
8458 +typedef unsigned char uchar;
8459 +#endif
8460 +
8461 +#ifndef TYPEDEF_USHORT
8462 +typedef unsigned short ushort;
8463 +#endif
8464 +
8465 +#ifndef TYPEDEF_UINT
8466 +typedef unsigned int uint;
8467 +#endif
8468 +
8469 +#ifndef TYPEDEF_ULONG
8470 +typedef unsigned long ulong;
8471 +#endif
8472 +
8473 +/* define [u]int8/16/32/64, uintptr */
8474 +
8475 +#ifndef TYPEDEF_UINT8
8476 +typedef unsigned char uint8;
8477 +#endif
8478 +
8479 +#ifndef TYPEDEF_UINT16
8480 +typedef unsigned short uint16;
8481 +#endif
8482 +
8483 +#ifndef TYPEDEF_UINT32
8484 +typedef unsigned int uint32;
8485 +#endif
8486 +
8487 +#ifndef TYPEDEF_UINT64
8488 +typedef unsigned long long uint64;
8489 +#endif
8490 +
8491 +#ifndef TYPEDEF_UINTPTR
8492 +typedef unsigned int uintptr;
8493 +#endif
8494 +
8495 +#ifndef TYPEDEF_INT8
8496 +typedef signed char int8;
8497 +#endif
8498 +
8499 +#ifndef TYPEDEF_INT16
8500 +typedef signed short int16;
8501 +#endif
8502 +
8503 +#ifndef TYPEDEF_INT32
8504 +typedef signed int int32;
8505 +#endif
8506 +
8507 +#ifndef TYPEDEF_INT64
8508 +typedef signed long long int64;
8509 +#endif
8510 +
8511 +/* define float32/64, float_t */
8512 +
8513 +#ifndef TYPEDEF_FLOAT32
8514 +typedef float float32;
8515 +#endif
8516 +
8517 +#ifndef TYPEDEF_FLOAT64
8518 +typedef double float64;
8519 +#endif
8520 +
8521 +/*
8522 + * abstracted floating point type allows for compile time selection of
8523 + * single or double precision arithmetic. Compiling with -DFLOAT32
8524 + * selects single precision; the default is double precision.
8525 + */
8526 +
8527 +#ifndef TYPEDEF_FLOAT_T
8528 +
8529 +#if defined(FLOAT32)
8530 +typedef float32 float_t;
8531 +#else /* default to double precision floating point */
8532 +typedef float64 float_t;
8533 +#endif
8534 +
8535 +#endif /* TYPEDEF_FLOAT_T */
8536 +
8537 +/* define macro values */
8538 +
8539 +#ifndef FALSE
8540 +#define FALSE 0
8541 +#endif
8542 +
8543 +#ifndef TRUE
8544 +#define TRUE 1 /* TRUE */
8545 +#endif
8546 +
8547 +#ifndef NULL
8548 +#define NULL 0
8549 +#endif
8550 +
8551 +#ifndef OFF
8552 +#define OFF 0
8553 +#endif
8554 +
8555 +#ifndef ON
8556 +#define ON 1 /* ON = 1 */
8557 +#endif
8558 +
8559 +#define AUTO (-1) /* Auto = -1 */
8560 +
8561 +/* define PTRSZ, INLINE */
8562 +
8563 +#ifndef PTRSZ
8564 +#define PTRSZ sizeof(char*)
8565 +#endif
8566 +
8567 +#ifndef INLINE
8568 +
8569 +#ifdef _MSC_VER
8570 +
8571 +#define INLINE __inline
8572 +
8573 +#elif __GNUC__
8574 +
8575 +#define INLINE __inline__
8576 +
8577 +#else
8578 +
8579 +#define INLINE
8580 +
8581 +#endif /* _MSC_VER */
8582 +
8583 +#endif /* INLINE */
8584 +
8585 +#undef TYPEDEF_BOOL
8586 +#undef TYPEDEF_UCHAR
8587 +#undef TYPEDEF_USHORT
8588 +#undef TYPEDEF_UINT
8589 +#undef TYPEDEF_ULONG
8590 +#undef TYPEDEF_UINT8
8591 +#undef TYPEDEF_UINT16
8592 +#undef TYPEDEF_UINT32
8593 +#undef TYPEDEF_UINT64
8594 +#undef TYPEDEF_UINTPTR
8595 +#undef TYPEDEF_INT8
8596 +#undef TYPEDEF_INT16
8597 +#undef TYPEDEF_INT32
8598 +#undef TYPEDEF_INT64
8599 +#undef TYPEDEF_FLOAT32
8600 +#undef TYPEDEF_FLOAT64
8601 +#undef TYPEDEF_FLOAT_T
8602 +
8603 +#endif /* USE_TYPEDEF_DEFAULTS */
8604 +
8605 +/*
8606 + * Including the bcmdefs.h here, to make sure everyone including typedefs.h
8607 + * gets this automatically
8608 +*/
8609 +#include "bcmdefs.h"
8610 +
8611 +#endif /* _TYPEDEFS_H_ */
8612 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
8613 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
8614 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2006-04-27 23:11:58.000000000 +0200
8615 @@ -0,0 +1,315 @@
8616 +/*
8617 + * NVRAM variable manipulation (common)
8618 + *
8619 + * Copyright 2004, Broadcom Corporation
8620 + * All Rights Reserved.
8621 + *
8622 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8623 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8624 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8625 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8626 + *
8627 + */
8628 +
8629 +#include <typedefs.h>
8630 +#include <osl.h>
8631 +#include <bcmendian.h>
8632 +#include <bcmnvram.h>
8633 +#include <bcmutils.h>
8634 +#include <sbsdram.h>
8635 +
8636 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
8637 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
8638 +extern int BCMINIT(_nvram_read)(void *buf);
8639 +
8640 +char * BCMINIT(_nvram_get)(const char *name);
8641 +int BCMINIT(_nvram_set)(const char *name, const char *value);
8642 +int BCMINIT(_nvram_unset)(const char *name);
8643 +int BCMINIT(_nvram_getall)(char *buf, int count);
8644 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
8645 +int BCMINIT(_nvram_init)(void);
8646 +void BCMINIT(_nvram_exit)(void);
8647 +
8648 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
8649 +static struct nvram_tuple * nvram_dead;
8650 +
8651 +/* Free all tuples. Should be locked. */
8652 +static void
8653 +BCMINITFN(nvram_free)(void)
8654 +{
8655 + uint i;
8656 + struct nvram_tuple *t, *next;
8657 +
8658 + /* Free hash table */
8659 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8660 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
8661 + next = t->next;
8662 + BCMINIT(_nvram_free)(t);
8663 + }
8664 + BCMINIT(nvram_hash)[i] = NULL;
8665 + }
8666 +
8667 + /* Free dead table */
8668 + for (t = nvram_dead; t; t = next) {
8669 + next = t->next;
8670 + BCMINIT(_nvram_free)(t);
8671 + }
8672 + nvram_dead = NULL;
8673 +
8674 + /* Indicate to per-port code that all tuples have been freed */
8675 + BCMINIT(_nvram_free)(NULL);
8676 +}
8677 +
8678 +/* String hash */
8679 +static INLINE uint
8680 +hash(const char *s)
8681 +{
8682 + uint hash = 0;
8683 +
8684 + while (*s)
8685 + hash = 31 * hash + *s++;
8686 +
8687 + return hash;
8688 +}
8689 +
8690 +/* (Re)initialize the hash table. Should be locked. */
8691 +static int
8692 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
8693 +{
8694 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
8695 +
8696 + /* (Re)initialize hash table */
8697 + BCMINIT(nvram_free)();
8698 +
8699 + /* Parse and set "name=value\0 ... \0\0" */
8700 + name = (char *) &header[1];
8701 + end = (char *) header + NVRAM_SPACE - 2;
8702 + end[0] = end[1] = '\0';
8703 + for (; *name; name = value + strlen(value) + 1) {
8704 + if (!(eq = strchr(name, '=')))
8705 + break;
8706 + *eq = '\0';
8707 + value = eq + 1;
8708 + BCMINIT(_nvram_set)(name, value);
8709 + *eq = '=';
8710 + }
8711 +
8712 + /* Set special SDRAM parameters */
8713 + if (!BCMINIT(_nvram_get)("sdram_init")) {
8714 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
8715 + BCMINIT(_nvram_set)("sdram_init", buf);
8716 + }
8717 + if (!BCMINIT(_nvram_get)("sdram_config")) {
8718 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
8719 + BCMINIT(_nvram_set)("sdram_config", buf);
8720 + }
8721 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
8722 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
8723 + BCMINIT(_nvram_set)("sdram_refresh", buf);
8724 + }
8725 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
8726 + sprintf(buf, "0x%08X", header->config_ncdl);
8727 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
8728 + }
8729 +
8730 + return 0;
8731 +}
8732 +
8733 +/* Get the value of an NVRAM variable. Should be locked. */
8734 +char *
8735 +BCMINITFN(_nvram_get)(const char *name)
8736 +{
8737 + uint i;
8738 + struct nvram_tuple *t;
8739 + char *value;
8740 +
8741 + if (!name)
8742 + return NULL;
8743 +
8744 + /* Hash the name */
8745 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8746 +
8747 + /* Find the associated tuple in the hash table */
8748 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
8749 +
8750 + value = t ? t->value : NULL;
8751 +
8752 + return value;
8753 +}
8754 +
8755 +/* Get the value of an NVRAM variable. Should be locked. */
8756 +int
8757 +BCMINITFN(_nvram_set)(const char *name, const char *value)
8758 +{
8759 + uint i;
8760 + struct nvram_tuple *t, *u, **prev;
8761 +
8762 + /* Hash the name */
8763 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8764 +
8765 + /* Find the associated tuple in the hash table */
8766 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8767 +
8768 + /* (Re)allocate tuple */
8769 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
8770 + return -12; /* -ENOMEM */
8771 +
8772 + /* Value reallocated */
8773 + if (t && t == u)
8774 + return 0;
8775 +
8776 + /* Move old tuple to the dead table */
8777 + if (t) {
8778 + *prev = t->next;
8779 + t->next = nvram_dead;
8780 + nvram_dead = t;
8781 + }
8782 +
8783 + /* Add new tuple to the hash table */
8784 + u->next = BCMINIT(nvram_hash)[i];
8785 + BCMINIT(nvram_hash)[i] = u;
8786 +
8787 + return 0;
8788 +}
8789 +
8790 +/* Unset the value of an NVRAM variable. Should be locked. */
8791 +int
8792 +BCMINITFN(_nvram_unset)(const char *name)
8793 +{
8794 + uint i;
8795 + struct nvram_tuple *t, **prev;
8796 +
8797 + if (!name)
8798 + return 0;
8799 +
8800 + /* Hash the name */
8801 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8802 +
8803 + /* Find the associated tuple in the hash table */
8804 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8805 +
8806 + /* Move it to the dead table */
8807 + if (t) {
8808 + *prev = t->next;
8809 + t->next = nvram_dead;
8810 + nvram_dead = t;
8811 + }
8812 +
8813 + return 0;
8814 +}
8815 +
8816 +/* Get all NVRAM variables. Should be locked. */
8817 +int
8818 +BCMINITFN(_nvram_getall)(char *buf, int count)
8819 +{
8820 + uint i;
8821 + struct nvram_tuple *t;
8822 + int len = 0;
8823 +
8824 + bzero(buf, count);
8825 +
8826 + /* Write name=value\0 ... \0\0 */
8827 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8828 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8829 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
8830 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
8831 + else
8832 + break;
8833 + }
8834 + }
8835 +
8836 + return 0;
8837 +}
8838 +
8839 +/* Regenerate NVRAM. Should be locked. */
8840 +int
8841 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
8842 +{
8843 + char *init, *config, *refresh, *ncdl;
8844 + char *ptr, *end;
8845 + int i;
8846 + struct nvram_tuple *t;
8847 + struct nvram_header tmp;
8848 + uint8 crc;
8849 +
8850 + /* Regenerate header */
8851 + header->magic = NVRAM_MAGIC;
8852 + header->crc_ver_init = (NVRAM_VERSION << 8);
8853 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
8854 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
8855 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
8856 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
8857 + header->crc_ver_init |= SDRAM_INIT << 16;
8858 + header->config_refresh = SDRAM_CONFIG;
8859 + header->config_refresh |= SDRAM_REFRESH << 16;
8860 + header->config_ncdl = 0;
8861 + } else {
8862 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
8863 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
8864 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
8865 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
8866 + }
8867 +
8868 + /* Clear data area */
8869 + ptr = (char *) header + sizeof(struct nvram_header);
8870 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
8871 +
8872 + /* Leave space for a double NUL at the end */
8873 + end = (char *) header + NVRAM_SPACE - 2;
8874 +
8875 + /* Write out all tuples */
8876 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8877 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8878 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
8879 + break;
8880 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
8881 + }
8882 + }
8883 +
8884 + /* End with a double NUL */
8885 + ptr += 2;
8886 +
8887 + /* Set new length */
8888 + header->len = ROUNDUP(ptr - (char *) header, 4);
8889 +
8890 + /* Little-endian CRC8 over the last 11 bytes of the header */
8891 + tmp.crc_ver_init = htol32(header->crc_ver_init);
8892 + tmp.config_refresh = htol32(header->config_refresh);
8893 + tmp.config_ncdl = htol32(header->config_ncdl);
8894 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
8895 +
8896 + /* Continue CRC8 over data bytes */
8897 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
8898 +
8899 + /* Set new CRC8 */
8900 + header->crc_ver_init |= crc;
8901 +
8902 + /* Reinitialize hash table */
8903 + return BCMINIT(nvram_rehash)(header);
8904 +}
8905 +
8906 +/* Initialize hash table. Should be locked. */
8907 +int
8908 +BCMINITFN(_nvram_init)(void)
8909 +{
8910 + struct nvram_header *header;
8911 + int ret;
8912 +
8913 + if (!(header = (struct nvram_header *) kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
8914 + return -12; /* -ENOMEM */
8915 + }
8916 +
8917 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
8918 + header->magic == NVRAM_MAGIC)
8919 + BCMINIT(nvram_rehash)(header);
8920 +
8921 + kfree(header);
8922 + return ret;
8923 +}
8924 +
8925 +/* Free hash table. Should be locked. */
8926 +void
8927 +BCMINITFN(_nvram_exit)(void)
8928 +{
8929 + BCMINIT(nvram_free)();
8930 +}
8931 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
8932 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
8933 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2006-04-27 23:30:07.000000000 +0200
8934 @@ -0,0 +1,723 @@
8935 +/*
8936 + * NVRAM variable manipulation (Linux kernel half)
8937 + *
8938 + * Copyright 2006, Broadcom Corporation
8939 + * All Rights Reserved.
8940 + *
8941 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8942 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8943 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8944 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8945 + *
8946 + * $Id: nvram_linux.c,v 1.19 2006/04/08 07:12:42 honor Exp $
8947 + */
8948 +
8949 +#include <linux/config.h>
8950 +#include <linux/init.h>
8951 +#include <linux/module.h>
8952 +#include <linux/kernel.h>
8953 +#include <linux/string.h>
8954 +#include <linux/interrupt.h>
8955 +#include <linux/spinlock.h>
8956 +#include <linux/slab.h>
8957 +#include <linux/bootmem.h>
8958 +#include <linux/wrapper.h>
8959 +#include <linux/fs.h>
8960 +#include <linux/miscdevice.h>
8961 +#include <linux/mtd/mtd.h>
8962 +#include <asm/addrspace.h>
8963 +#include <asm/io.h>
8964 +#include <asm/uaccess.h>
8965 +
8966 +#include <typedefs.h>
8967 +#include <osl.h>
8968 +#include <bcmendian.h>
8969 +#include <bcmnvram.h>
8970 +#include <bcmutils.h>
8971 +#include <sbconfig.h>
8972 +#include <sbchipc.h>
8973 +#include <sbutils.h>
8974 +#include <hndmips.h>
8975 +#include <sflash.h>
8976 +
8977 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
8978 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
8979 +
8980 +#ifdef MODULE
8981 +
8982 +#define early_nvram_get(name) nvram_get(name)
8983 +
8984 +#else /* !MODULE */
8985 +
8986 +/* Global SB handle */
8987 +extern void *bcm947xx_sbh;
8988 +extern spinlock_t bcm947xx_sbh_lock;
8989 +
8990 +static int cfe_env;
8991 +extern char *cfe_env_get(char *nv_buf, const char *name);
8992 +
8993 +/* Convenience */
8994 +#define sbh bcm947xx_sbh
8995 +#define sbh_lock bcm947xx_sbh_lock
8996 +#define KB * 1024
8997 +#define MB * 1024 * 1024
8998 +
8999 +/* Probe for NVRAM header */
9000 +static void __init
9001 +early_nvram_init(void)
9002 +{
9003 + struct nvram_header *header;
9004 + chipcregs_t *cc;
9005 + struct sflash *info = NULL;
9006 + int i;
9007 + uint32 base, off, lim;
9008 + u32 *src, *dst;
9009 +
9010 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
9011 + base = KSEG1ADDR(SB_FLASH2);
9012 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
9013 + case PFLASH:
9014 + lim = SB_FLASH2_SZ;
9015 + break;
9016 +
9017 + case SFLASH_ST:
9018 + case SFLASH_AT:
9019 + if ((info = sflash_init(cc)) == NULL)
9020 + return;
9021 + lim = info->size;
9022 + break;
9023 +
9024 + case FLASH_NONE:
9025 + default:
9026 + return;
9027 + }
9028 + } else {
9029 + /* extif assumed, Stop at 4 MB */
9030 + base = KSEG1ADDR(SB_FLASH1);
9031 + lim = SB_FLASH1_SZ;
9032 + }
9033 +
9034 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
9035 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
9036 + dst = (u32 *) nvram_buf;
9037 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
9038 + printk("early_nvram_init: WGT634U NVRAM found.\n");
9039 +
9040 + for (i = 0; i < 0x1ff0; i++) {
9041 + if (*src == 0xFFFFFFFF)
9042 + break;
9043 + *dst++ = *src++;
9044 + }
9045 + cfe_env = 1;
9046 + return;
9047 + }
9048 +
9049 + off = FLASH_MIN;
9050 + while (off <= lim) {
9051 + /* Windowed flash access */
9052 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9053 + if (header->magic == NVRAM_MAGIC)
9054 + goto found;
9055 + off <<= 1;
9056 + }
9057 +
9058 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9059 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
9060 + if (header->magic == NVRAM_MAGIC)
9061 + goto found;
9062 +
9063 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
9064 + if (header->magic == NVRAM_MAGIC)
9065 + goto found;
9066 +
9067 + printk("early_nvram_init: NVRAM not found\n");
9068 + return;
9069 +
9070 +found:
9071 + src = (u32 *) header;
9072 + dst = (u32 *) nvram_buf;
9073 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9074 + *dst++ = *src++;
9075 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9076 + *dst++ = ltoh32(*src++);
9077 +}
9078 +
9079 +/* Early (before mm or mtd) read-only access to NVRAM */
9080 +static char * __init
9081 +early_nvram_get(const char *name)
9082 +{
9083 + char *var, *value, *end, *eq;
9084 +
9085 + if (!name)
9086 + return NULL;
9087 +
9088 + /* Too early? */
9089 + if (sbh == NULL)
9090 + return NULL;
9091 +
9092 + if (!nvram_buf[0])
9093 + early_nvram_init();
9094 +
9095 + if (cfe_env)
9096 + return cfe_env_get(nvram_buf, name);
9097 +
9098 + /* Look for name=value and return value */
9099 + var = &nvram_buf[sizeof(struct nvram_header)];
9100 + end = nvram_buf + sizeof(nvram_buf) - 2;
9101 + end[0] = end[1] = '\0';
9102 + for (; *var; var = value + strlen(value) + 1) {
9103 + if (!(eq = strchr(var, '=')))
9104 + break;
9105 + value = eq + 1;
9106 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9107 + return value;
9108 + }
9109 +
9110 + return NULL;
9111 +}
9112 +
9113 +static int __init
9114 +early_nvram_getall(char *buf, int count)
9115 +{
9116 + char *var, *end;
9117 + int len = 0;
9118 +
9119 + /* Too early? */
9120 + if (sbh == NULL)
9121 + return -1;
9122 +
9123 + if (!nvram_buf[0])
9124 + early_nvram_init();
9125 +
9126 + bzero(buf, count);
9127 +
9128 + /* Write name=value\0 ... \0\0 */
9129 + var = &nvram_buf[sizeof(struct nvram_header)];
9130 + end = nvram_buf + sizeof(nvram_buf) - 2;
9131 + end[0] = end[1] = '\0';
9132 + for (; *var; var += strlen(var) + 1) {
9133 + if ((count - len) <= (strlen(var) + 1))
9134 + break;
9135 + len += sprintf(buf + len, "%s", var) + 1;
9136 + }
9137 +
9138 + return 0;
9139 +}
9140 +#endif /* !MODULE */
9141 +
9142 +extern char * _nvram_get(const char *name);
9143 +extern int _nvram_set(const char *name, const char *value);
9144 +extern int _nvram_unset(const char *name);
9145 +extern int _nvram_getall(char *buf, int count);
9146 +extern int _nvram_commit(struct nvram_header *header);
9147 +extern int _nvram_init(void *sbh);
9148 +extern void _nvram_exit(void);
9149 +
9150 +/* Globals */
9151 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9152 +static struct semaphore nvram_sem;
9153 +static unsigned long nvram_offset = 0;
9154 +static int nvram_major = -1;
9155 +static devfs_handle_t nvram_handle = NULL;
9156 +static struct mtd_info *nvram_mtd = NULL;
9157 +
9158 +int
9159 +_nvram_read(char *buf)
9160 +{
9161 + struct nvram_header *header = (struct nvram_header *) buf;
9162 + size_t len;
9163 +
9164 + if (!nvram_mtd ||
9165 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9166 + len != NVRAM_SPACE ||
9167 + header->magic != NVRAM_MAGIC) {
9168 + /* Maybe we can recover some data from early initialization */
9169 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9170 + }
9171 +
9172 + return 0;
9173 +}
9174 +
9175 +struct nvram_tuple *
9176 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9177 +{
9178 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9179 + return NULL;
9180 +
9181 + if (!t) {
9182 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9183 + return NULL;
9184 +
9185 + /* Copy name */
9186 + t->name = (char *) &t[1];
9187 + strcpy(t->name, name);
9188 +
9189 + t->value = NULL;
9190 + }
9191 +
9192 + /* Copy value */
9193 + if (!t->value || strcmp(t->value, value)) {
9194 + t->value = &nvram_buf[nvram_offset];
9195 + strcpy(t->value, value);
9196 + nvram_offset += strlen(value) + 1;
9197 + }
9198 +
9199 + return t;
9200 +}
9201 +
9202 +void
9203 +_nvram_free(struct nvram_tuple *t)
9204 +{
9205 + if (!t)
9206 + nvram_offset = 0;
9207 + else
9208 + kfree(t);
9209 +}
9210 +
9211 +int
9212 +nvram_set(const char *name, const char *value)
9213 +{
9214 + unsigned long flags;
9215 + int ret;
9216 + struct nvram_header *header;
9217 +
9218 + spin_lock_irqsave(&nvram_lock, flags);
9219 + if ((ret = _nvram_set(name, value))) {
9220 + /* Consolidate space and try again */
9221 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9222 + if (_nvram_commit(header) == 0)
9223 + ret = _nvram_set(name, value);
9224 + kfree(header);
9225 + }
9226 + }
9227 + spin_unlock_irqrestore(&nvram_lock, flags);
9228 +
9229 + return ret;
9230 +}
9231 +
9232 +char *
9233 +real_nvram_get(const char *name)
9234 +{
9235 + unsigned long flags;
9236 + char *value;
9237 +
9238 + spin_lock_irqsave(&nvram_lock, flags);
9239 + value = _nvram_get(name);
9240 + spin_unlock_irqrestore(&nvram_lock, flags);
9241 +
9242 + return value;
9243 +}
9244 +
9245 +char *
9246 +nvram_get(const char *name)
9247 +{
9248 + if (nvram_major >= 0)
9249 + return real_nvram_get(name);
9250 + else
9251 + return early_nvram_get(name);
9252 +}
9253 +
9254 +int
9255 +nvram_unset(const char *name)
9256 +{
9257 + unsigned long flags;
9258 + int ret;
9259 +
9260 + spin_lock_irqsave(&nvram_lock, flags);
9261 + ret = _nvram_unset(name);
9262 + spin_unlock_irqrestore(&nvram_lock, flags);
9263 +
9264 + return ret;
9265 +}
9266 +
9267 +static void
9268 +erase_callback(struct erase_info *done)
9269 +{
9270 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9271 + wake_up(wait_q);
9272 +}
9273 +
9274 +int
9275 +nvram_commit(void)
9276 +{
9277 + char *buf;
9278 + size_t erasesize, len, magic_len;
9279 + unsigned int i;
9280 + int ret;
9281 + struct nvram_header *header;
9282 + unsigned long flags;
9283 + u_int32_t offset;
9284 + DECLARE_WAITQUEUE(wait, current);
9285 + wait_queue_head_t wait_q;
9286 + struct erase_info erase;
9287 + u_int32_t magic_offset = 0; /* Offset for writing MAGIC # */
9288 +
9289 + if (!nvram_mtd) {
9290 + printk("nvram_commit: NVRAM not found\n");
9291 + return -ENODEV;
9292 + }
9293 +
9294 + if (in_interrupt()) {
9295 + printk("nvram_commit: not committing in interrupt\n");
9296 + return -EINVAL;
9297 + }
9298 +
9299 + /* Backup sector blocks to be erased */
9300 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9301 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9302 + printk("nvram_commit: out of memory\n");
9303 + return -ENOMEM;
9304 + }
9305 +
9306 + down(&nvram_sem);
9307 +
9308 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9309 + offset = nvram_mtd->size - erasesize;
9310 + len = 0;
9311 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9312 + if (ret || len != i) {
9313 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9314 + ret = -EIO;
9315 + goto done;
9316 + }
9317 + header = (struct nvram_header *)(buf + i);
9318 + magic_offset = i + ((void *)&header->magic - (void *)header);
9319 + } else {
9320 + offset = nvram_mtd->size - NVRAM_SPACE;
9321 + magic_offset = ((void *)&header->magic - (void *)header);
9322 + header = (struct nvram_header *)buf;
9323 + }
9324 +
9325 + /* clear the existing magic # to mark the NVRAM as unusable
9326 + we can pull MAGIC bits low without erase */
9327 + header->magic = NVRAM_CLEAR_MAGIC; /* All zeros magic */
9328 +
9329 + /* Unlock sector blocks (for Intel 28F320C3B flash) , 20060309 */
9330 + if(nvram_mtd->unlock)
9331 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9332 +
9333 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9334 + &magic_len, (char *)&header->magic);
9335 + if (ret || magic_len != sizeof(header->magic)) {
9336 + printk("nvram_commit: clear MAGIC error\n");
9337 + ret = -EIO;
9338 + goto done;
9339 + }
9340 +
9341 + header->magic = NVRAM_MAGIC; /* reset MAGIC before we regenerate the NVRAM,
9342 + otherwise we'll have an incorrect CRC */
9343 + /* Regenerate NVRAM */
9344 + spin_lock_irqsave(&nvram_lock, flags);
9345 + ret = _nvram_commit(header);
9346 + spin_unlock_irqrestore(&nvram_lock, flags);
9347 + if (ret)
9348 + goto done;
9349 +
9350 + /* Erase sector blocks */
9351 + init_waitqueue_head(&wait_q);
9352 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9353 + erase.mtd = nvram_mtd;
9354 + erase.addr = offset;
9355 + erase.len = nvram_mtd->erasesize;
9356 + erase.callback = erase_callback;
9357 + erase.priv = (u_long) &wait_q;
9358 +
9359 + set_current_state(TASK_INTERRUPTIBLE);
9360 + add_wait_queue(&wait_q, &wait);
9361 +
9362 + /* Unlock sector blocks */
9363 + if (nvram_mtd->unlock)
9364 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9365 +
9366 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9367 + set_current_state(TASK_RUNNING);
9368 + remove_wait_queue(&wait_q, &wait);
9369 + printk("nvram_commit: erase error\n");
9370 + goto done;
9371 + }
9372 +
9373 + /* Wait for erase to finish */
9374 + schedule();
9375 + remove_wait_queue(&wait_q, &wait);
9376 + }
9377 +
9378 + /* Write partition up to end of data area */
9379 + header->magic = NVRAM_INVALID_MAGIC; /* All ones magic */
9380 + offset = nvram_mtd->size - erasesize;
9381 + i = erasesize - NVRAM_SPACE + header->len;
9382 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9383 + if (ret || len != i) {
9384 + printk("nvram_commit: write error\n");
9385 + ret = -EIO;
9386 + goto done;
9387 + }
9388 +
9389 + /* Now mark the NVRAM in flash as "valid" by setting the correct
9390 + MAGIC # */
9391 + header->magic = NVRAM_MAGIC;
9392 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9393 + &magic_len, (char *)&header->magic);
9394 + if (ret || magic_len != sizeof(header->magic)) {
9395 + printk("nvram_commit: write MAGIC error\n");
9396 + ret = -EIO;
9397 + goto done;
9398 + }
9399 +
9400 + /*
9401 + * Reading a few bytes back here will put the device
9402 + * back to the correct mode on certain flashes */
9403 + offset = nvram_mtd->size - erasesize;
9404 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9405 +
9406 + done:
9407 + up(&nvram_sem);
9408 + kfree(buf);
9409 +
9410 + return ret;
9411 +}
9412 +
9413 +int
9414 +nvram_getall(char *buf, int count)
9415 +{
9416 + unsigned long flags;
9417 + int ret;
9418 +
9419 + spin_lock_irqsave(&nvram_lock, flags);
9420 + if (nvram_major >= 0)
9421 + ret = _nvram_getall(buf, count);
9422 + else
9423 + ret = early_nvram_getall(buf, count);
9424 + spin_unlock_irqrestore(&nvram_lock, flags);
9425 +
9426 + return ret;
9427 +}
9428 +
9429 +
9430 +
9431 +
9432 +
9433 +
9434 +
9435 +/* User mode interface below */
9436 +
9437 +static ssize_t
9438 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9439 +{
9440 + char tmp[100], *name = tmp, *value;
9441 + ssize_t ret;
9442 + unsigned long off;
9443 +
9444 + if (count > sizeof(tmp)) {
9445 + if (!(name = kmalloc(count, GFP_KERNEL)))
9446 + return -ENOMEM;
9447 + }
9448 +
9449 + if (copy_from_user(name, buf, count)) {
9450 + ret = -EFAULT;
9451 + goto done;
9452 + }
9453 +
9454 + if (*name == '\0') {
9455 + /* Get all variables */
9456 + ret = nvram_getall(name, count);
9457 + if (ret == 0) {
9458 + if (copy_to_user(buf, name, count)) {
9459 + ret = -EFAULT;
9460 + goto done;
9461 + }
9462 + ret = count;
9463 + }
9464 + } else {
9465 + if (!(value = nvram_get(name))) {
9466 + ret = 0;
9467 + goto done;
9468 + }
9469 +
9470 + /* Provide the offset into mmap() space */
9471 + off = (unsigned long) value - (unsigned long) nvram_buf;
9472 +
9473 + if (put_user(off, (unsigned long *) buf)) {
9474 + ret = -EFAULT;
9475 + goto done;
9476 + }
9477 +
9478 + ret = sizeof(unsigned long);
9479 + }
9480 +
9481 + flush_cache_all();
9482 +
9483 +done:
9484 + if (name != tmp)
9485 + kfree(name);
9486 +
9487 + return ret;
9488 +}
9489 +
9490 +static ssize_t
9491 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
9492 +{
9493 + char tmp[100], *name = tmp, *value;
9494 + ssize_t ret;
9495 +
9496 + if (count > sizeof(tmp)) {
9497 + if (!(name = kmalloc(count, GFP_KERNEL)))
9498 + return -ENOMEM;
9499 + }
9500 +
9501 + if (copy_from_user(name, buf, count)) {
9502 + ret = -EFAULT;
9503 + goto done;
9504 + }
9505 +
9506 + value = name;
9507 + name = strsep(&value, "=");
9508 + if (value)
9509 + ret = nvram_set(name, value) ? : count;
9510 + else
9511 + ret = nvram_unset(name) ? : count;
9512 +
9513 + done:
9514 + if (name != tmp)
9515 + kfree(name);
9516 +
9517 + return ret;
9518 +}
9519 +
9520 +static int
9521 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
9522 +{
9523 + if (cmd != NVRAM_MAGIC)
9524 + return -EINVAL;
9525 +
9526 + return nvram_commit();
9527 +}
9528 +
9529 +static int
9530 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
9531 +{
9532 + unsigned long offset = virt_to_phys(nvram_buf);
9533 +
9534 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
9535 + vma->vm_page_prot))
9536 + return -EAGAIN;
9537 +
9538 + return 0;
9539 +}
9540 +
9541 +static int
9542 +dev_nvram_open(struct inode *inode, struct file * file)
9543 +{
9544 + MOD_INC_USE_COUNT;
9545 + return 0;
9546 +}
9547 +
9548 +static int
9549 +dev_nvram_release(struct inode *inode, struct file * file)
9550 +{
9551 + MOD_DEC_USE_COUNT;
9552 + return 0;
9553 +}
9554 +
9555 +static struct file_operations dev_nvram_fops = {
9556 + owner: THIS_MODULE,
9557 + open: dev_nvram_open,
9558 + release: dev_nvram_release,
9559 + read: dev_nvram_read,
9560 + write: dev_nvram_write,
9561 + ioctl: dev_nvram_ioctl,
9562 + mmap: dev_nvram_mmap,
9563 +};
9564 +
9565 +static void
9566 +dev_nvram_exit(void)
9567 +{
9568 + int order = 0;
9569 + struct page *page, *end;
9570 +
9571 + if (nvram_handle)
9572 + devfs_unregister(nvram_handle);
9573 +
9574 + if (nvram_major >= 0)
9575 + devfs_unregister_chrdev(nvram_major, "nvram");
9576 +
9577 + if (nvram_mtd)
9578 + put_mtd_device(nvram_mtd);
9579 +
9580 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9581 + order++;
9582 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9583 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9584 + mem_map_unreserve(page);
9585 +
9586 + _nvram_exit();
9587 +}
9588 +
9589 +static int __init
9590 +dev_nvram_init(void)
9591 +{
9592 + int order = 0, ret = 0;
9593 + struct page *page, *end;
9594 + unsigned int i;
9595 +
9596 + /* Allocate and reserve memory to mmap() */
9597 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9598 + order++;
9599 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9600 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9601 + mem_map_reserve(page);
9602 +
9603 +#ifdef CONFIG_MTD
9604 + /* Find associated MTD device */
9605 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
9606 + nvram_mtd = get_mtd_device(NULL, i);
9607 + if (nvram_mtd) {
9608 + if (!strcmp(nvram_mtd->name, "nvram") &&
9609 + nvram_mtd->size >= NVRAM_SPACE)
9610 + break;
9611 + put_mtd_device(nvram_mtd);
9612 + }
9613 + }
9614 + if (i >= MAX_MTD_DEVICES)
9615 + nvram_mtd = NULL;
9616 +#endif
9617 +
9618 + /* Initialize hash table lock */
9619 + spin_lock_init(&nvram_lock);
9620 +
9621 + /* Initialize commit semaphore */
9622 + init_MUTEX(&nvram_sem);
9623 +
9624 + /* Register char device */
9625 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
9626 + ret = nvram_major;
9627 + goto err;
9628 + }
9629 +
9630 + /* Initialize hash table */
9631 + _nvram_init(sbh);
9632 +
9633 + /* Create /dev/nvram handle */
9634 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
9635 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
9636 +
9637 + /* Set the SDRAM NCDL value into NVRAM if not already done */
9638 + if (getintvar(NULL, "sdram_ncdl") == 0) {
9639 + unsigned int ncdl;
9640 + char buf[] = "0x00000000";
9641 +
9642 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
9643 + sprintf(buf, "0x%08x", ncdl);
9644 + nvram_set("sdram_ncdl", buf);
9645 + nvram_commit();
9646 + }
9647 + }
9648 +
9649 + return 0;
9650 +
9651 + err:
9652 + dev_nvram_exit();
9653 + return ret;
9654 +}
9655 +
9656 +module_init(dev_nvram_init);
9657 +module_exit(dev_nvram_exit);
9658 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
9659 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
9660 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2006-04-27 23:42:50.000000000 +0200
9661 @@ -0,0 +1,380 @@
9662 +/*
9663 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
9664 + *
9665 + * Copyright 2006, Broadcom Corporation
9666 + * All Rights Reserved.
9667 + *
9668 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9669 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9670 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9671 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9672 + *
9673 + * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
9674 + */
9675 +
9676 +#include <linux/config.h>
9677 +#include <linux/types.h>
9678 +#include <linux/kernel.h>
9679 +#include <linux/sched.h>
9680 +#include <linux/pci.h>
9681 +#include <linux/init.h>
9682 +#include <linux/delay.h>
9683 +#include <asm/io.h>
9684 +#include <asm/irq.h>
9685 +#include <asm/paccess.h>
9686 +
9687 +#include <typedefs.h>
9688 +#include <osl.h>
9689 +#include <bcmutils.h>
9690 +#include <sbconfig.h>
9691 +#include <sbutils.h>
9692 +#include <hndpci.h>
9693 +#include <pcicfg.h>
9694 +#include <bcmdevs.h>
9695 +#include <bcmnvram.h>
9696 +
9697 +/* Global SB handle */
9698 +extern sb_t *bcm947xx_sbh;
9699 +extern spinlock_t bcm947xx_sbh_lock;
9700 +
9701 +/* Convenience */
9702 +#define sbh bcm947xx_sbh
9703 +#define sbh_lock bcm947xx_sbh_lock
9704 +
9705 +static int
9706 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
9707 +{
9708 + unsigned long flags;
9709 + int ret;
9710 +
9711 + spin_lock_irqsave(&sbh_lock, flags);
9712 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9713 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9714 + spin_unlock_irqrestore(&sbh_lock, flags);
9715 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9716 +}
9717 +
9718 +static int
9719 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
9720 +{
9721 + unsigned long flags;
9722 + int ret;
9723 +
9724 + spin_lock_irqsave(&sbh_lock, flags);
9725 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9726 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9727 + spin_unlock_irqrestore(&sbh_lock, flags);
9728 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9729 +}
9730 +
9731 +static int
9732 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
9733 +{
9734 + unsigned long flags;
9735 + int ret;
9736 +
9737 + spin_lock_irqsave(&sbh_lock, flags);
9738 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9739 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9740 + spin_unlock_irqrestore(&sbh_lock, flags);
9741 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9742 +}
9743 +
9744 +static int
9745 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
9746 +{
9747 + unsigned long flags;
9748 + int ret;
9749 +
9750 + spin_lock_irqsave(&sbh_lock, flags);
9751 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9752 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9753 + spin_unlock_irqrestore(&sbh_lock, flags);
9754 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9755 +}
9756 +
9757 +static int
9758 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
9759 +{
9760 + unsigned long flags;
9761 + int ret;
9762 +
9763 + spin_lock_irqsave(&sbh_lock, flags);
9764 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9765 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9766 + spin_unlock_irqrestore(&sbh_lock, flags);
9767 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9768 +}
9769 +
9770 +static int
9771 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
9772 +{
9773 + unsigned long flags;
9774 + int ret;
9775 +
9776 + spin_lock_irqsave(&sbh_lock, flags);
9777 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9778 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9779 + spin_unlock_irqrestore(&sbh_lock, flags);
9780 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9781 +}
9782 +
9783 +static struct pci_ops pcibios_ops = {
9784 + sbpci_read_config_byte,
9785 + sbpci_read_config_word,
9786 + sbpci_read_config_dword,
9787 + sbpci_write_config_byte,
9788 + sbpci_write_config_word,
9789 + sbpci_write_config_dword
9790 +};
9791 +
9792 +
9793 +void __init
9794 +pcibios_init(void)
9795 +{
9796 + ulong flags;
9797 +
9798 + if (!(sbh = sb_kattach()))
9799 + panic("sb_kattach failed");
9800 + spin_lock_init(&sbh_lock);
9801 +
9802 + spin_lock_irqsave(&sbh_lock, flags);
9803 + sbpci_init(sbh);
9804 + spin_unlock_irqrestore(&sbh_lock, flags);
9805 +
9806 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
9807 +
9808 + /* Scan the SB bus */
9809 + pci_scan_bus(0, &pcibios_ops, NULL);
9810 +
9811 +}
9812 +
9813 +char * __init
9814 +pcibios_setup(char *str)
9815 +{
9816 + if (!strncmp(str, "ban=", 4)) {
9817 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
9818 + return NULL;
9819 + }
9820 +
9821 + return (str);
9822 +}
9823 +
9824 +static u32 pci_iobase = 0x100;
9825 +static u32 pci_membase = SB_PCI_DMA;
9826 +
9827 +void __init
9828 +pcibios_fixup_bus(struct pci_bus *b)
9829 +{
9830 + struct list_head *ln;
9831 + struct pci_dev *d;
9832 + struct resource *res;
9833 + int pos, size;
9834 + u32 *base;
9835 + u8 irq;
9836 +
9837 + printk("PCI: Fixing up bus %d\n", b->number);
9838 +
9839 + /* Fix up SB */
9840 + if (b->number == 0) {
9841 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9842 + d = pci_dev_b(ln);
9843 + /* Fix up interrupt lines */
9844 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
9845 + d->irq = irq + 2;
9846 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9847 + }
9848 + }
9849 +
9850 + /* Fix up external PCI */
9851 + else {
9852 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9853 + d = pci_dev_b(ln);
9854 + /* Fix up resource bases */
9855 + for (pos = 0; pos < 6; pos++) {
9856 + res = &d->resource[pos];
9857 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
9858 + if (res->end) {
9859 + size = res->end - res->start + 1;
9860 + if (*base & (size - 1))
9861 + *base = (*base + size) & ~(size - 1);
9862 + res->start = *base;
9863 + res->end = res->start + size - 1;
9864 + *base += size;
9865 + pci_write_config_dword(d,
9866 + PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
9867 + }
9868 + /* Fix up PCI bridge BAR0 only */
9869 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
9870 + break;
9871 + }
9872 + /* Fix up interrupt lines */
9873 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
9874 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
9875 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9876 + }
9877 + }
9878 +}
9879 +
9880 +unsigned int
9881 +pcibios_assign_all_busses(void)
9882 +{
9883 + return 1;
9884 +}
9885 +
9886 +void
9887 +pcibios_align_resource(void *data, struct resource *res,
9888 + unsigned long size, unsigned long align)
9889 +{
9890 +}
9891 +
9892 +int
9893 +pcibios_enable_resources(struct pci_dev *dev)
9894 +{
9895 + u16 cmd, old_cmd;
9896 + int idx;
9897 + struct resource *r;
9898 +
9899 + /* External PCI only */
9900 + if (dev->bus->number == 0)
9901 + return 0;
9902 +
9903 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
9904 + old_cmd = cmd;
9905 + for (idx = 0; idx < 6; idx++) {
9906 + r = &dev->resource[idx];
9907 + if (r->flags & IORESOURCE_IO)
9908 + cmd |= PCI_COMMAND_IO;
9909 + if (r->flags & IORESOURCE_MEM)
9910 + cmd |= PCI_COMMAND_MEMORY;
9911 + }
9912 + if (dev->resource[PCI_ROM_RESOURCE].start)
9913 + cmd |= PCI_COMMAND_MEMORY;
9914 + if (cmd != old_cmd) {
9915 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
9916 + pci_write_config_word(dev, PCI_COMMAND, cmd);
9917 + }
9918 + return 0;
9919 +}
9920 +
9921 +int
9922 +pcibios_enable_device(struct pci_dev *dev, int mask)
9923 +{
9924 + ulong flags;
9925 + uint coreidx;
9926 + void *regs;
9927 +
9928 + /* External PCI device enable */
9929 + if (dev->bus->number != 0)
9930 + return pcibios_enable_resources(dev);
9931 +
9932 + /* These cores come out of reset enabled */
9933 + if (dev->device == SB_MIPS ||
9934 + dev->device == SB_MIPS33 ||
9935 + dev->device == SB_EXTIF ||
9936 + dev->device == SB_CC)
9937 + return 0;
9938 +
9939 + spin_lock_irqsave(&sbh_lock, flags);
9940 + coreidx = sb_coreidx(sbh);
9941 + regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
9942 + if (!regs)
9943 + return PCIBIOS_DEVICE_NOT_FOUND;
9944 +
9945 + /*
9946 + * The USB core requires a special bit to be set during core
9947 + * reset to enable host (OHCI) mode. Resetting the SB core in
9948 + * pcibios_enable_device() is a hack for compatibility with
9949 + * vanilla usb-ohci so that it does not have to know about
9950 + * SB. A driver that wants to use the USB core in device mode
9951 + * should know about SB and should reset the bit back to 0
9952 + * after calling pcibios_enable_device().
9953 + */
9954 + if (sb_coreid(sbh) == SB_USB) {
9955 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
9956 + sb_core_reset(sbh, 1 << 29, 0);
9957 + }
9958 + /*
9959 + * USB 2.0 special considerations:
9960 + *
9961 + * 1. Since the core supports both OHCI and EHCI functions, it must
9962 + * only be reset once.
9963 + *
9964 + * 2. In addition to the standard SB reset sequence, the Host Control
9965 + * Register must be programmed to bring the USB core and various
9966 + * phy components out of reset.
9967 + */
9968 + else if (sb_coreid(sbh) == SB_USB20H) {
9969 + if (!sb_iscoreup(sbh)) {
9970 + sb_core_reset(sbh, 0, 0);
9971 + writel(0x7FF, (ulong)regs + 0x200);
9972 + udelay(1);
9973 + }
9974 + } else
9975 + sb_core_reset(sbh, 0, 0);
9976 +
9977 + sb_setcoreidx(sbh, coreidx);
9978 + spin_unlock_irqrestore(&sbh_lock, flags);
9979 +
9980 + return 0;
9981 +}
9982 +
9983 +void
9984 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
9985 + struct resource *res, int resource)
9986 +{
9987 + unsigned long where, size;
9988 + u32 reg;
9989 +
9990 + /* External PCI only */
9991 + if (dev->bus->number == 0)
9992 + return;
9993 +
9994 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
9995 + size = res->end - res->start;
9996 + pci_read_config_dword(dev, where, &reg);
9997 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
9998 + pci_write_config_dword(dev, where, reg);
9999 +}
10000 +
10001 +static void __init
10002 +quirk_sbpci_bridge(struct pci_dev *dev)
10003 +{
10004 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
10005 + return;
10006 +
10007 + printk("PCI: Fixing up bridge\n");
10008 +
10009 + /* Enable PCI bridge bus mastering and memory space */
10010 + pci_set_master(dev);
10011 + pcibios_enable_resources(dev);
10012 +
10013 + /* Enable PCI bridge BAR1 prefetch and burst */
10014 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
10015 +}
10016 +
10017 +struct pci_fixup pcibios_fixups[] = {
10018 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
10019 + { 0 }
10020 +};
10021 +
10022 +/*
10023 + * If we set up a device for bus mastering, we need to check the latency
10024 + * timer as certain crappy BIOSes forget to set it properly.
10025 + */
10026 +unsigned int pcibios_max_latency = 255;
10027 +
10028 +void pcibios_set_master(struct pci_dev *dev)
10029 +{
10030 + u8 lat;
10031 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10032 + if (lat < 16)
10033 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10034 + else if (lat > pcibios_max_latency)
10035 + lat = pcibios_max_latency;
10036 + else
10037 + return;
10038 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10039 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10040 +}
10041 +
10042 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
10043 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10044 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-04-27 19:24:19.000000000 +0200
10045 @@ -0,0 +1,41 @@
10046 +/*
10047 + * Early initialization code for BCM94710 boards
10048 + *
10049 + * Copyright 2004, Broadcom Corporation
10050 + * All Rights Reserved.
10051 + *
10052 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10053 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10054 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10055 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10056 + *
10057 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10058 + */
10059 +
10060 +#include <linux/config.h>
10061 +#include <linux/init.h>
10062 +#include <linux/kernel.h>
10063 +#include <linux/types.h>
10064 +#include <asm/bootinfo.h>
10065 +
10066 +void __init
10067 +prom_init(int argc, const char **argv)
10068 +{
10069 + unsigned long mem;
10070 +
10071 + mips_machgroup = MACH_GROUP_BRCM;
10072 + mips_machtype = MACH_BCM947XX;
10073 +
10074 + /* Figure out memory size by finding aliases */
10075 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10076 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10077 + *(unsigned long *)(prom_init))
10078 + break;
10079 + }
10080 + add_memory_region(0, mem, BOOT_MEM_RAM);
10081 +}
10082 +
10083 +void __init
10084 +prom_free_prom_memory(void)
10085 +{
10086 +}
10087 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
10088 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10089 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2006-05-02 04:43:13.000000000 +0200
10090 @@ -0,0 +1,1145 @@
10091 +/*
10092 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10093 + *
10094 + * Copyright 2006, Broadcom Corporation
10095 + * All Rights Reserved.
10096 + *
10097 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10098 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10099 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10100 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10101 + *
10102 + * $Id: hndmips.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
10103 + */
10104 +
10105 +#include <typedefs.h>
10106 +#include <bcmdefs.h>
10107 +#include <osl.h>
10108 +#include <bcmutils.h>
10109 +#include <sbutils.h>
10110 +#include <bcmdevs.h>
10111 +#include <bcmnvram.h>
10112 +#include <sbconfig.h>
10113 +#include <sbextif.h>
10114 +#include <sbchipc.h>
10115 +#include <sbmemc.h>
10116 +#include <mipsinc.h>
10117 +#include <sbhndmips.h>
10118 +#include <hndcpu.h>
10119 +
10120 +/* sbipsflag register format, indexed by irq. */
10121 +static const uint32 sbips_int_mask[] = {
10122 + 0, /* placeholder */
10123 + SBIPS_INT1_MASK,
10124 + SBIPS_INT2_MASK,
10125 + SBIPS_INT3_MASK,
10126 + SBIPS_INT4_MASK
10127 +};
10128 +
10129 +static const uint32 sbips_int_shift[] = {
10130 + 0, /* placeholder */
10131 + SBIPS_INT1_SHIFT,
10132 + SBIPS_INT2_SHIFT,
10133 + SBIPS_INT3_SHIFT,
10134 + SBIPS_INT4_SHIFT
10135 +};
10136 +
10137 +/*
10138 + * Map SB cores sharing the MIPS hardware IRQ0 to virtual dedicated OS IRQs.
10139 + * Per-port BSP code is required to provide necessary translations between
10140 + * the shared MIPS IRQ and the virtual OS IRQs based on SB core flag.
10141 + *
10142 + * See sb_irq() for the mapping.
10143 + */
10144 +static uint shirq_map_base = 0;
10145 +
10146 +/* Returns the SB interrupt flag of the current core. */
10147 +static uint32
10148 +sb_getflag(sb_t *sbh)
10149 +{
10150 + osl_t *osh;
10151 + void *regs;
10152 + sbconfig_t *sb;
10153 +
10154 + osh = sb_osh(sbh);
10155 + regs = sb_coreregs(sbh);
10156 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10157 +
10158 + return (R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK);
10159 +}
10160 +
10161 +/*
10162 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10163 + * 0 is returned.
10164 + */
10165 +static uint
10166 +sb_getirq(sb_t *sbh)
10167 +{
10168 + osl_t *osh;
10169 + uint idx;
10170 + void *regs;
10171 + sbconfig_t *sb;
10172 + uint32 flag, sbipsflag;
10173 + uint irq = 0;
10174 +
10175 + osh = sb_osh(sbh);
10176 + flag = sb_getflag(sbh);
10177 +
10178 + idx = sb_coreidx(sbh);
10179 +
10180 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10181 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10182 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10183 +
10184 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10185 + sbipsflag = R_REG(osh, &sb->sbipsflag);
10186 + for (irq = 1; irq <= 4; irq++) {
10187 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10188 + break;
10189 + }
10190 + if (irq == 5)
10191 + irq = 0;
10192 + }
10193 +
10194 + sb_setcoreidx(sbh, idx);
10195 +
10196 + return irq;
10197 +}
10198 +
10199 +/*
10200 + * Return the MIPS IRQ assignment of the current core. If necessary
10201 + * map cores sharing the MIPS hw IRQ0 to virtual dedicated OS IRQs.
10202 + */
10203 +uint
10204 +sb_irq(sb_t *sbh)
10205 +{
10206 + uint irq = sb_getirq(sbh);
10207 + if (irq == 0 && shirq_map_base)
10208 + irq = sb_getflag(sbh) + shirq_map_base;
10209 + return irq;
10210 +}
10211 +
10212 +/* Clears the specified MIPS IRQ. */
10213 +static void
10214 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
10215 +{
10216 + osl_t *osh;
10217 + void *regs;
10218 + sbconfig_t *sb;
10219 +
10220 + osh = sb_osh(sbh);
10221 +
10222 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10223 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10224 + ASSERT(regs);
10225 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10226 +
10227 + if (irq == 0)
10228 + W_REG(osh, &sb->sbintvec, 0);
10229 + else
10230 + OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]);
10231 +}
10232 +
10233 +/*
10234 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10235 + * IRQ 0 may be assigned more than once.
10236 + *
10237 + * The old assignment to the specified core is removed first.
10238 + */
10239 +static void
10240 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
10241 +{
10242 + osl_t *osh;
10243 + void *regs;
10244 + sbconfig_t *sb;
10245 + uint32 flag;
10246 + uint oldirq;
10247 +
10248 + osh = sb_osh(sbh);
10249 +
10250 + regs = sb_setcore(sbh, coreid, coreunit);
10251 + ASSERT(regs);
10252 + flag = sb_getflag(sbh);
10253 + oldirq = sb_getirq(sbh);
10254 + if (oldirq)
10255 + sb_clearirq(sbh, oldirq);
10256 +
10257 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10258 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10259 + ASSERT(regs);
10260 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10261 +
10262 + if (!oldirq)
10263 + AND_REG(osh, &sb->sbintvec, ~(1 << flag));
10264 +
10265 + if (irq == 0)
10266 + OR_REG(osh, &sb->sbintvec, 1 << flag);
10267 + else {
10268 + flag <<= sbips_int_shift[irq];
10269 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10270 + flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq];
10271 + W_REG(osh, &sb->sbipsflag, flag);
10272 + }
10273 +}
10274 +
10275 +/*
10276 + * Initializes clocks and interrupts. SB and NVRAM access must be
10277 + * initialized prior to calling.
10278 + *
10279 + * 'shirqmap' enables virtual dedicated OS IRQ mapping if non-zero.
10280 + */
10281 +void
10282 +BCMINITFN(sb_mips_init)(sb_t *sbh, uint shirqmap)
10283 +{
10284 + osl_t *osh;
10285 + ulong hz, ns, tmp;
10286 + extifregs_t *eir;
10287 + chipcregs_t *cc;
10288 + char *value;
10289 + uint irq;
10290 +
10291 + osh = sb_osh(sbh);
10292 +
10293 + /* Figure out current SB clock speed */
10294 + if ((hz = sb_clock(sbh)) == 0)
10295 + hz = 100000000;
10296 + ns = 1000000000 / hz;
10297 +
10298 + /* Setup external interface timing */
10299 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10300 + /* Initialize extif so we can get to the LEDs and external UART */
10301 + W_REG(osh, &eir->prog_config, CF_EN);
10302 +
10303 + /* Set timing for the flash */
10304 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10305 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10306 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10307 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10308 +
10309 + /* Set programmable interface timing for external uart */
10310 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10311 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10312 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10313 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10314 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10315 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10316 + /* Set timing for the flash */
10317 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10318 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10319 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10320 + if ((sb_corerev(sbh) < 9) ||
10321 + (BCMINIT(sb_chip)(sbh) == 0x5365))
10322 + W_REG(osh, &cc->flash_waitcount, tmp);
10323 +
10324 + if ((sb_corerev(sbh) < 9) ||
10325 + ((sb_chip(sbh) == BCM5350_CHIP_ID) && sb_chiprev(sbh) == 0) ||
10326 + (BCMINIT(sb_chip)(sbh) == 0x5365)) {
10327 + W_REG(osh, &cc->pcmcia_memwait, tmp);
10328 + }
10329 +
10330 + /* Save shared IRQ mapping base */
10331 + shirq_map_base = shirqmap;
10332 + }
10333 +
10334 + /* Chip specific initialization */
10335 + switch (sb_chip(sbh)) {
10336 + case BCM4710_CHIP_ID:
10337 + /* Clear interrupt map */
10338 + for (irq = 0; irq <= 4; irq++)
10339 + sb_clearirq(sbh, irq);
10340 + sb_setirq(sbh, 0, SB_CODEC, 0);
10341 + sb_setirq(sbh, 0, SB_EXTIF, 0);
10342 + sb_setirq(sbh, 2, SB_ENET, 1);
10343 + sb_setirq(sbh, 3, SB_ILINE20, 0);
10344 + sb_setirq(sbh, 4, SB_PCI, 0);
10345 + ASSERT(eir);
10346 + value = nvram_get("et0phyaddr");
10347 + if (value && !strcmp(value, "31")) {
10348 + /* Enable internal UART */
10349 + W_REG(osh, &eir->corecontrol, CC_UE);
10350 + /* Give USB its own interrupt */
10351 + sb_setirq(sbh, 1, SB_USB, 0);
10352 + } else {
10353 + /* Disable internal UART */
10354 + W_REG(osh, &eir->corecontrol, 0);
10355 + /* Give Ethernet its own interrupt */
10356 + sb_setirq(sbh, 1, SB_ENET, 0);
10357 + sb_setirq(sbh, 0, SB_USB, 0);
10358 + }
10359 + break;
10360 + case BCM5350_CHIP_ID:
10361 + /* Clear interrupt map */
10362 + for (irq = 0; irq <= 4; irq++)
10363 + sb_clearirq(sbh, irq);
10364 + sb_setirq(sbh, 0, SB_CC, 0);
10365 + sb_setirq(sbh, 0, SB_MIPS33, 0);
10366 + sb_setirq(sbh, 1, SB_D11, 0);
10367 + sb_setirq(sbh, 2, SB_ENET, 0);
10368 + sb_setirq(sbh, 3, SB_PCI, 0);
10369 + sb_setirq(sbh, 4, SB_USB, 0);
10370 + break;
10371 + case BCM4785_CHIP_ID:
10372 + /* Reassign PCI to irq 4 */
10373 + sb_setirq(sbh, 4, SB_PCI, 0);
10374 + break;
10375 + }
10376 +}
10377 +
10378 +uint32
10379 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
10380 +{
10381 + extifregs_t *eir;
10382 + chipcregs_t *cc;
10383 + uint32 n, m;
10384 + uint idx;
10385 + uint32 pll_type, rate = 0;
10386 +
10387 + /* get index of the current core */
10388 + idx = sb_coreidx(sbh);
10389 + pll_type = PLL_TYPE1;
10390 +
10391 + /* switch to extif or chipc core */
10392 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10393 + n = R_REG(osh, &eir->clockcontrol_n);
10394 + m = R_REG(osh, &eir->clockcontrol_sb);
10395 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10396 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10397 + n = R_REG(osh, &cc->clockcontrol_n);
10398 + if ((pll_type == PLL_TYPE2) ||
10399 + (pll_type == PLL_TYPE4) ||
10400 + (pll_type == PLL_TYPE6) ||
10401 + (pll_type == PLL_TYPE7))
10402 + m = R_REG(osh, &cc->clockcontrol_m3);
10403 + else if (pll_type == PLL_TYPE5) {
10404 + rate = 200000000;
10405 + goto out;
10406 + }
10407 + else if (pll_type == PLL_TYPE3) {
10408 + if (sb_chip(sbh) == BCM5365_CHIP_ID) {
10409 + rate = 200000000;
10410 + goto out;
10411 + }
10412 + /* 5350 uses m2 to control mips */
10413 + else
10414 + m = R_REG(osh, &cc->clockcontrol_m2);
10415 + } else
10416 + m = R_REG(osh, &cc->clockcontrol_sb);
10417 + } else
10418 + goto out;
10419 +
10420 +
10421 + /* calculate rate */
10422 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
10423 + rate = 100000000;
10424 + else
10425 + rate = sb_clock_rate(pll_type, n, m);
10426 +
10427 + if (pll_type == PLL_TYPE6)
10428 + rate = SB2MIPS_T6(rate);
10429 +
10430 +out:
10431 + /* switch back to previous core */
10432 + sb_setcoreidx(sbh, idx);
10433 +
10434 + return rate;
10435 +}
10436 +
10437 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
10438 +
10439 +static void
10440 +BCMINITFN(handler)(void)
10441 +{
10442 + __asm__(
10443 + ".set\tmips32\n\t"
10444 + "ssnop\n\t"
10445 + "ssnop\n\t"
10446 + /* Disable interrupts */
10447 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
10448 + "mfc0 $15, $12\n\t"
10449 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
10450 + "li $14, -31746\n\t"
10451 + "and $15, $15, $14\n\t"
10452 + "mtc0 $15, $12\n\t"
10453 + "eret\n\t"
10454 + "nop\n\t"
10455 + "nop\n\t"
10456 + ".set\tmips0");
10457 +}
10458 +
10459 +/* The following MUST come right after handler() */
10460 +static void
10461 +BCMINITFN(afterhandler)(void)
10462 +{
10463 +}
10464 +
10465 +/*
10466 + * Set the MIPS, backplane and PCI clocks as closely as possible.
10467 + *
10468 + * MIPS clocks synchronization function has been moved from PLL in chipcommon
10469 + * core rev. 15 to a DLL inside the MIPS core in 4785.
10470 + */
10471 +bool
10472 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
10473 +{
10474 + extifregs_t *eir = NULL;
10475 + chipcregs_t *cc = NULL;
10476 + mipsregs_t *mipsr = NULL;
10477 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
10478 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
10479 + uint32 pll_type, sync_mode;
10480 + uint ic_size, ic_lsize;
10481 + uint idx, i;
10482 +
10483 + /* PLL configuration: type 1 */
10484 + typedef struct {
10485 + uint32 mipsclock;
10486 + uint16 n;
10487 + uint32 sb;
10488 + uint32 pci33;
10489 + uint32 pci25;
10490 + } n3m_table_t;
10491 + static n3m_table_t BCMINITDATA(type1_table)[] = {
10492 + /* 96.000 32.000 24.000 */
10493 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 },
10494 + /* 100.000 33.333 25.000 */
10495 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 },
10496 + /* 104.000 31.200 24.960 */
10497 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 },
10498 + /* 108.000 32.400 24.923 */
10499 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 },
10500 + /* 112.000 32.000 24.889 */
10501 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 },
10502 + /* 115.200 32.000 24.000 */
10503 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 },
10504 + /* 120.000 30.000 24.000 */
10505 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 },
10506 + /* 124.800 31.200 24.960 */
10507 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 },
10508 + /* 128.000 32.000 24.000 */
10509 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 },
10510 + /* 132.000 33.000 24.750 */
10511 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 },
10512 + /* 136.000 32.640 24.727 */
10513 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 },
10514 + /* 140.000 30.000 24.706 */
10515 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 },
10516 + /* 144.000 30.857 24.686 */
10517 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 },
10518 + /* 150.857 33.000 24.000 */
10519 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 },
10520 + /* 152.000 32.571 24.000 */
10521 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 },
10522 + /* 156.000 31.200 24.960 */
10523 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 },
10524 + /* 160.000 32.000 24.000 */
10525 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 },
10526 + /* 163.200 32.640 24.727 */
10527 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 },
10528 + /* 168.000 32.000 24.889 */
10529 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 },
10530 + /* 176.000 33.000 24.000 */
10531 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 },
10532 + };
10533 +
10534 + /* PLL configuration: type 3 */
10535 + typedef struct {
10536 + uint32 mipsclock;
10537 + uint16 n;
10538 + uint32 m2; /* that is the clockcontrol_m2 */
10539 + } type3_table_t;
10540 + static type3_table_t type3_table[] = {
10541 + /* for 5350, mips clock is always double sb clock */
10542 + { 150000000, 0x311, 0x4020005 },
10543 + { 200000000, 0x311, 0x4020003 },
10544 + };
10545 +
10546 + /* PLL configuration: type 2, 4, 7 */
10547 + typedef struct {
10548 + uint32 mipsclock;
10549 + uint32 sbclock;
10550 + uint16 n;
10551 + uint32 sb;
10552 + uint32 pci33;
10553 + uint32 m2;
10554 + uint32 m3;
10555 + uint32 ratio_cfg;
10556 + uint32 ratio_parm;
10557 + uint32 d11_r1;
10558 + uint32 d11_r2;
10559 + } n4m_table_t;
10560 + static n4m_table_t BCMINITDATA(type2_table)[] = {
10561 + { 120000000, 60000000, 0x0303, 0x01000200, 0x01000600, 0x01000200, 0x05000200, 11,
10562 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10563 + { 150000000, 75000000, 0x0303, 0x01000100, 0x01000600, 0x01000100, 0x05000100, 11,
10564 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10565 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8,
10566 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10567 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11,
10568 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10569 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11,
10570 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10571 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10572 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10573 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10574 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10575 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10576 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10577 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8,
10578 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10579 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10580 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10581 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11,
10582 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10583 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11,
10584 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10585 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10586 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10587 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10588 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10589 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10590 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10591 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10592 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10593 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10594 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10595 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01010100, 0x05000100, 8,
10596 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10597 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01010100, 0x05000100, 11,
10598 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10599 + { 330000000, 132000000, 0x0903, 0x01000200, 0x00020200, 0x01010100, 0x05000100, 0,
10600 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10601 + { 330000000, 146666666, 0x0903, 0x01010000, 0x00020200, 0x01010100, 0x05000100, 0,
10602 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10603 + { 330000000, 165000000, 0x0903, 0x01000100, 0x00020200, 0x01010100, 0x05000100, 0,
10604 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10605 + { 360000000, 120000000, 0x0a03, 0x01000300, 0x00010201, 0x01010200, 0x05000100, 0,
10606 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10607 + { 360000000, 144000000, 0x0a03, 0x01000200, 0x00010201, 0x01010200, 0x05000100, 0,
10608 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10609 + { 360000000, 160000000, 0x0a03, 0x01010000, 0x00010201, 0x01010200, 0x05000100, 0,
10610 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10611 + { 360000000, 180000000, 0x0a03, 0x01000100, 0x00010201, 0x01010200, 0x05000100, 0,
10612 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10613 + { 390000000, 130000000, 0x0b03, 0x01010100, 0x00020101, 0x01020100, 0x05000100, 0,
10614 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10615 + { 390000000, 156000000, 0x0b03, 0x01000200, 0x00020101, 0x01020100, 0x05000100, 0,
10616 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10617 + { 390000000, 173000000, 0x0b03, 0x01010000, 0x00020101, 0x01020100, 0x05000100, 0,
10618 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10619 + { 390000000, 195000000, 0x0b03, 0x01000100, 0x00020101, 0x01020100, 0x05000100, 0,
10620 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10621 + };
10622 + static n4m_table_t BCMINITDATA(type4_table)[] = {
10623 + { 120000000, 60000000, 0x0009, 0x11020009, 0x01030203, 0x11020009, 0x04000009, 11,
10624 + 0x0aaa0555 },
10625 + { 150000000, 75000000, 0x0009, 0x11050002, 0x01030203, 0x11050002, 0x04000005, 11,
10626 + 0x0aaa0555 },
10627 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10628 + 0x0aaa0555 },
10629 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11,
10630 + 0x0aaa0555 },
10631 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10632 + 0x0aaa0555 },
10633 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10634 + 0x0aaa0555 },
10635 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11,
10636 + 0x0aaa0555 },
10637 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10638 + 0x0aaa0555 },
10639 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10640 + 0x0aaa0555 },
10641 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11,
10642 + 0x0aaa0555 },
10643 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8,
10644 + 0x012a00a9 },
10645 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10646 + 0x0aaa0555 },
10647 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13,
10648 + 0x254a14a9 },
10649 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11,
10650 + 0x0aaa0555 },
10651 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9,
10652 + 0x02520129 },
10653 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10654 + 0x0aaa0555 },
10655 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10656 + 0x0aaa0555 },
10657 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13,
10658 + 0x254a14a9 },
10659 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10660 + 0x254a14a9 },
10661 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10662 + 0x254a14a9 },
10663 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9,
10664 + 0x02520129 },
10665 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11,
10666 + 0x0aaa0555 }
10667 + };
10668 + static n4m_table_t BCMINITDATA(type7_table)[] = {
10669 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10670 + 0x0aaa0555 },
10671 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10672 + 0x0aaa0555 },
10673 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10674 + 0x0aaa0555 },
10675 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11,
10676 + 0x0aaa0555 },
10677 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10678 + 0x0aaa0555 },
10679 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10680 + 0x0aaa0555 },
10681 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10682 + 0x0aaa0555 },
10683 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11,
10684 + 0x0aaa0555 },
10685 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10686 + 0x0aaa0555 },
10687 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10688 + 0x0aaa0555 },
10689 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10690 + 0x0aaa0555 },
10691 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10692 + 0x0aaa0555 },
10693 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11,
10694 + 0x0aaa0555 },
10695 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11,
10696 + 0x0aaa0555 }
10697 + };
10698 +
10699 + ulong start, end, dst;
10700 + bool ret = FALSE;
10701 +
10702 + volatile uint32 *dll_ctrl = (volatile uint32 *)0xff400008;
10703 + volatile uint32 *dll_r1 = (volatile uint32 *)0xff400010;
10704 + volatile uint32 *dll_r2 = (volatile uint32 *)0xff400018;
10705 +
10706 + /* get index of the current core */
10707 + idx = sb_coreidx(sbh);
10708 + clockcontrol_m2 = NULL;
10709 +
10710 + /* switch to extif or chipc core */
10711 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10712 + pll_type = PLL_TYPE1;
10713 + clockcontrol_n = &eir->clockcontrol_n;
10714 + clockcontrol_sb = &eir->clockcontrol_sb;
10715 + clockcontrol_pci = &eir->clockcontrol_pci;
10716 + clockcontrol_m2 = &cc->clockcontrol_m2;
10717 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10718 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10719 + if (pll_type == PLL_TYPE6) {
10720 + clockcontrol_n = NULL;
10721 + clockcontrol_sb = NULL;
10722 + clockcontrol_pci = NULL;
10723 + } else {
10724 + clockcontrol_n = &cc->clockcontrol_n;
10725 + clockcontrol_sb = &cc->clockcontrol_sb;
10726 + clockcontrol_pci = &cc->clockcontrol_pci;
10727 + clockcontrol_m2 = &cc->clockcontrol_m2;
10728 + }
10729 + } else
10730 + goto done;
10731 +
10732 + if (pll_type == PLL_TYPE6) {
10733 + /* Silence compilers */
10734 + orig_n = orig_sb = orig_pci = 0;
10735 + } else {
10736 + /* Store the current clock register values */
10737 + orig_n = R_REG(osh, clockcontrol_n);
10738 + orig_sb = R_REG(osh, clockcontrol_sb);
10739 + orig_pci = R_REG(osh, clockcontrol_pci);
10740 + }
10741 +
10742 + if (pll_type == PLL_TYPE1) {
10743 + /* Keep the current PCI clock if not specified */
10744 + if (pciclock == 0) {
10745 + pciclock = sb_clock_rate(pll_type, R_REG(osh, clockcontrol_n),
10746 + R_REG(osh, clockcontrol_pci));
10747 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
10748 + }
10749 +
10750 + /* Search for the closest MIPS clock less than or equal to a preferred value */
10751 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
10752 + ASSERT(type1_table[i].mipsclock ==
10753 + sb_clock_rate(pll_type, type1_table[i].n,
10754 + type1_table[i].sb));
10755 + if (type1_table[i].mipsclock > mipsclock)
10756 + break;
10757 + }
10758 + if (i == 0) {
10759 + ret = FALSE;
10760 + goto done;
10761 + } else {
10762 + ret = TRUE;
10763 + i--;
10764 + }
10765 + ASSERT(type1_table[i].mipsclock <= mipsclock);
10766 +
10767 + /* No PLL change */
10768 + if ((orig_n == type1_table[i].n) &&
10769 + (orig_sb == type1_table[i].sb) &&
10770 + (orig_pci == type1_table[i].pci33))
10771 + goto done;
10772 +
10773 + /* Set the PLL controls */
10774 + W_REG(osh, clockcontrol_n, type1_table[i].n);
10775 + W_REG(osh, clockcontrol_sb, type1_table[i].sb);
10776 + if (pciclock == 25000000)
10777 + W_REG(osh, clockcontrol_pci, type1_table[i].pci25);
10778 + else
10779 + W_REG(osh, clockcontrol_pci, type1_table[i].pci33);
10780 +
10781 + /* Reset */
10782 + sb_watchdog(sbh, 1);
10783 + while (1);
10784 + } else if (pll_type == PLL_TYPE3) {
10785 + /* 5350 */
10786 + if (sb_chip(sbh) != BCM5365_CHIP_ID) {
10787 + /*
10788 + * Search for the closest MIPS clock less than or equal to
10789 + * a preferred value.
10790 + */
10791 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
10792 + if (type3_table[i].mipsclock > mipsclock)
10793 + break;
10794 + }
10795 + if (i == 0) {
10796 + ret = FALSE;
10797 + goto done;
10798 + } else {
10799 + ret = TRUE;
10800 + i--;
10801 + }
10802 + ASSERT(type3_table[i].mipsclock <= mipsclock);
10803 +
10804 + /* No PLL change */
10805 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10806 + if ((orig_n == type3_table[i].n) &&
10807 + (orig_m2 == type3_table[i].m2)) {
10808 + goto done;
10809 + }
10810 +
10811 + /* Set the PLL controls */
10812 + W_REG(osh, clockcontrol_n, type3_table[i].n);
10813 + W_REG(osh, clockcontrol_m2, type3_table[i].m2);
10814 +
10815 + /* Reset */
10816 + sb_watchdog(sbh, 1);
10817 + while (1);
10818 + }
10819 + } else if ((pll_type == PLL_TYPE2) ||
10820 + (pll_type == PLL_TYPE4) ||
10821 + (pll_type == PLL_TYPE6) ||
10822 + (pll_type == PLL_TYPE7)) {
10823 + n4m_table_t *table = NULL, *te;
10824 + uint tabsz = 0;
10825 +
10826 + ASSERT(cc);
10827 +
10828 + orig_mips = R_REG(osh, &cc->clockcontrol_m3);
10829 +
10830 + switch (pll_type) {
10831 + case PLL_TYPE6: {
10832 + uint32 new_mips = 0;
10833 +
10834 + ret = TRUE;
10835 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
10836 + new_mips = CC_T6_MMASK;
10837 +
10838 + if (orig_mips == new_mips)
10839 + goto done;
10840 +
10841 + W_REG(osh, &cc->clockcontrol_m3, new_mips);
10842 + goto end_fill;
10843 + }
10844 + case PLL_TYPE2:
10845 + table = type2_table;
10846 + tabsz = ARRAYSIZE(type2_table);
10847 + break;
10848 + case PLL_TYPE4:
10849 + table = type4_table;
10850 + tabsz = ARRAYSIZE(type4_table);
10851 + break;
10852 + case PLL_TYPE7:
10853 + table = type7_table;
10854 + tabsz = ARRAYSIZE(type7_table);
10855 + break;
10856 + default:
10857 + ASSERT("No table for plltype" == NULL);
10858 + break;
10859 + }
10860 +
10861 + /* Store the current clock register values */
10862 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10863 + orig_ratio_parm = 0;
10864 + orig_ratio_cfg = 0;
10865 +
10866 + /* Look up current ratio */
10867 + for (i = 0; i < tabsz; i++) {
10868 + if ((orig_n == table[i].n) &&
10869 + (orig_sb == table[i].sb) &&
10870 + (orig_pci == table[i].pci33) &&
10871 + (orig_m2 == table[i].m2) &&
10872 + (orig_mips == table[i].m3)) {
10873 + orig_ratio_parm = table[i].ratio_parm;
10874 + orig_ratio_cfg = table[i].ratio_cfg;
10875 + break;
10876 + }
10877 + }
10878 +
10879 + /* Search for the closest MIPS clock greater or equal to a preferred value */
10880 + for (i = 0; i < tabsz; i++) {
10881 + ASSERT(table[i].mipsclock ==
10882 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
10883 + if ((mipsclock <= table[i].mipsclock) &&
10884 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
10885 + break;
10886 + }
10887 + if (i == tabsz) {
10888 + ret = FALSE;
10889 + goto done;
10890 + } else {
10891 + te = &table[i];
10892 + ret = TRUE;
10893 + }
10894 +
10895 + /* No PLL change */
10896 + if ((orig_n == te->n) &&
10897 + (orig_sb == te->sb) &&
10898 + (orig_pci == te->pci33) &&
10899 + (orig_m2 == te->m2) &&
10900 + (orig_mips == te->m3))
10901 + goto done;
10902 +
10903 + /* Set the PLL controls */
10904 + W_REG(osh, clockcontrol_n, te->n);
10905 + W_REG(osh, clockcontrol_sb, te->sb);
10906 + W_REG(osh, clockcontrol_pci, te->pci33);
10907 + W_REG(osh, &cc->clockcontrol_m2, te->m2);
10908 + W_REG(osh, &cc->clockcontrol_m3, te->m3);
10909 +
10910 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
10911 + if ((pll_type == PLL_TYPE7) && (te->sb != te->m2) &&
10912 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
10913 + W_REG(osh, &cc->chipcontrol,
10914 + R_REG(osh, &cc->chipcontrol) | 0x100);
10915 +
10916 + /* No ratio change */
10917 + if (sb_chip(sbh) != BCM4785_CHIP_ID) {
10918 + if (orig_ratio_parm == te->ratio_parm)
10919 + goto end_fill;
10920 + }
10921 +
10922 + /* Preload the code into the cache */
10923 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
10924 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10925 + start = ((ulong) &&start_fill_4785) & ~(ic_lsize - 1);
10926 + end = ((ulong) &&end_fill_4785 + (ic_lsize - 1)) & ~(ic_lsize - 1);
10927 + }
10928 + else {
10929 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
10930 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
10931 + }
10932 + while (start < end) {
10933 + cache_op(start, Fill_I);
10934 + start += ic_lsize;
10935 + }
10936 +
10937 + /* Copy the handler */
10938 + start = (ulong) &handler;
10939 + end = (ulong) &afterhandler;
10940 + dst = KSEG1ADDR(0x180);
10941 + for (i = 0; i < (end - start); i += 4)
10942 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
10943 +
10944 + /* Preload the handler into the cache one line at a time */
10945 + for (i = 0; i < (end - start); i += ic_lsize)
10946 + cache_op(dst + i, Fill_I);
10947 +
10948 + /* Clear BEV bit */
10949 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
10950 +
10951 + /* Enable interrupts */
10952 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
10953 +
10954 + /* 4785 clock freq change procedures */
10955 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10956 + start_fill_4785:
10957 + /* Switch to async */
10958 + MTC0(C0_BROADCOM, 4, (1 << 22));
10959 +
10960 + /* Set clock ratio in MIPS */
10961 + *dll_r1 = (*dll_r1 & 0xfffffff0) | (te->d11_r1 - 1);
10962 + *dll_r2 = te->d11_r2;
10963 +
10964 + /* Enable new settings in MIPS */
10965 + *dll_r1 = *dll_r1 | 0xc0000000;
10966 +
10967 + /* Set active cfg */
10968 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) | (1 << 3) | 1);
10969 +
10970 + /* Fake soft reset (clock cfg registers not reset) */
10971 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10972 +
10973 + /* Clear active cfg */
10974 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) & ~(1 << 3));
10975 +
10976 + /* set watchdog timer */
10977 + W_REG(osh, &cc->watchdog, 20);
10978 + (void) R_REG(osh, &cc->chipid);
10979 +
10980 + /* wait for timer interrupt */
10981 + __asm__ __volatile__(
10982 + ".set\tmips3\n\t"
10983 + "sync\n\t"
10984 + "wait\n\t"
10985 + ".set\tmips0");
10986 + end_fill_4785:
10987 + while (1);
10988 + }
10989 + /* Generic clock freq change procedures */
10990 + else {
10991 + /* Enable MIPS timer interrupt */
10992 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
10993 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
10994 + ASSERT(mipsr);
10995 + W_REG(osh, &mipsr->intmask, 1);
10996 +
10997 + start_fill:
10998 + /* step 1, set clock ratios */
10999 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
11000 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
11001 +
11002 + /* step 2: program timer intr */
11003 + W_REG(osh, &mipsr->timer, 100);
11004 + (void) R_REG(osh, &mipsr->timer);
11005 +
11006 + /* step 3, switch to async */
11007 + sync_mode = MFC0(C0_BROADCOM, 4);
11008 + MTC0(C0_BROADCOM, 4, 1 << 22);
11009 +
11010 + /* step 4, set cfg active */
11011 + MTC0(C0_BROADCOM, 2, (1 << 3) | 1);
11012 +
11013 + /* steps 5 & 6 */
11014 + __asm__ __volatile__(
11015 + ".set\tmips3\n\t"
11016 + "wait\n\t"
11017 + ".set\tmips0");
11018 +
11019 + /* step 7, clear cfg active */
11020 + MTC0(C0_BROADCOM, 2, 0);
11021 +
11022 + /* Additional Step: set back to orig sync mode */
11023 + MTC0(C0_BROADCOM, 4, sync_mode);
11024 +
11025 + /* step 8, fake soft reset */
11026 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
11027 +
11028 + end_fill:
11029 + /* set watchdog timer */
11030 + W_REG(osh, &cc->watchdog, 20);
11031 + (void) R_REG(osh, &cc->chipid);
11032 +
11033 + /* wait for timer interrupt */
11034 + __asm__ __volatile__(
11035 + ".set\tmips3\n\t"
11036 + "sync\n\t"
11037 + "wait\n\t"
11038 + ".set\tmips0");
11039 + while (1);
11040 + }
11041 + }
11042 +
11043 +done:
11044 + /* Enable 4785 DLL */
11045 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
11046 + uint32 tmp;
11047 +
11048 + /* set mask to 1e, enable DLL (bit 0) */
11049 + *dll_ctrl |= 0x0041e021;
11050 +
11051 + /* enable aggressive hardware mode */
11052 + *dll_ctrl |= 0x00000080;
11053 +
11054 + /* wait for lock flag to clear */
11055 + while ((*dll_ctrl & 0x2) == 0);
11056 +
11057 + /* clear sticky flags (clear on write 1) */
11058 + tmp = *dll_ctrl;
11059 + *dll_ctrl = tmp;
11060 +
11061 + /* set mask to 5b'10001 */
11062 + *dll_ctrl = (*dll_ctrl & 0xfffc1fff) | 0x00022000;
11063 +
11064 + /* enable sync mode */
11065 + MTC0(C0_BROADCOM, 4, MFC0(C0_BROADCOM, 4) & 0xfe3fffff);
11066 + (void)MFC0(C0_BROADCOM, 4);
11067 + }
11068 +
11069 + /* switch back to previous core */
11070 + sb_setcoreidx(sbh, idx);
11071 +
11072 + return ret;
11073 +}
11074 +
11075 +void
11076 +BCMINITFN(enable_pfc)(uint32 mode)
11077 +{
11078 + ulong start, end;
11079 + uint ic_size, ic_lsize;
11080 +
11081 + /* If auto then choose the correct mode for this
11082 + * platform, currently we only ever select one mode
11083 + */
11084 + if (mode == PFC_AUTO)
11085 + mode = PFC_INST;
11086 +
11087 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11088 +
11089 + /* enable prefetch cache if available */
11090 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
11091 + start = ((ulong) &&setpfc_start) & ~(ic_lsize - 1);
11092 + end = ((ulong) &&setpfc_end + (ic_lsize - 1)) & ~(ic_lsize - 1);
11093 +
11094 + /* Preload setpfc code into the cache one line at a time */
11095 + while (start < end) {
11096 + cache_op(start, Fill_I);
11097 + start += ic_lsize;
11098 + }
11099 +
11100 + /* Now set the pfc */
11101 + setpfc_start:
11102 + /* write range */
11103 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
11104 +
11105 + /* enable */
11106 + *(volatile uint32 *)PFC_CR0 = mode;
11107 + setpfc_end:
11108 + /* Compiler foder */
11109 + ic_size = 0;
11110 + }
11111 +}
11112 +
11113 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11114 +uint32
11115 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
11116 +{
11117 + osl_t *osh;
11118 + sbmemcregs_t *memc;
11119 + uint32 ret = 0;
11120 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11121 + uint idx, rev;
11122 +
11123 + osh = sb_osh(sbh);
11124 +
11125 + idx = sb_coreidx(sbh);
11126 +
11127 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11128 + if (memc == 0)
11129 + goto out;
11130 +
11131 + rev = sb_corerev(sbh);
11132 +
11133 + config = R_REG(osh, &memc->config);
11134 + wr = R_REG(osh, &memc->wrncdlcor);
11135 + rd = R_REG(osh, &memc->rdncdlcor);
11136 + misc = R_REG(osh, &memc->miscdlyctl);
11137 + dqsg = R_REG(osh, &memc->dqsgatencdl);
11138 +
11139 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11140 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11141 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11142 +
11143 + if (config & MEMC_CONFIG_DDR) {
11144 + ret = (wr << 16) | (rd << 8) | dqsg;
11145 + } else {
11146 + if (rev > 0)
11147 + cd = rd;
11148 + else
11149 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11150 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11151 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11152 + ret = (sm << 16) | (sd << 8) | cd;
11153 + }
11154 +
11155 +out:
11156 + /* switch back to previous core */
11157 + sb_setcoreidx(sbh, idx);
11158 +
11159 + return ret;
11160 +}
11161 +
11162 +#if defined(BCMPERFSTATS)
11163 +/*
11164 + * CP0 Register 25 supports 4 semi-independent 32bit performance counters.
11165 + * $25 select 0, 1, 2, and 3 are the counters. The counters *decrement* (who thought this one up?)
11166 + * $25 select 4 and 5 each contain 2-16bit control fields, one for each of the 4 counters
11167 + * $25 select 6 is the global perf control register.
11168 + */
11169 +/* enable and start instruction counting */
11170 +
11171 +void
11172 +hndmips_perf_instrcount_enable()
11173 +{
11174 + MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */
11175 + MTC0(C0_PERFORMANCE, 4,
11176 + 0x8044 | MFC0(C0_PERFORMANCE, 4)); /* enable instruction counting for counter 0 */
11177 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */
11178 +}
11179 +
11180 +/* enable and start I$ hit and I$ miss counting */
11181 +void
11182 +hndmips_perf_icachecount_enable(void)
11183 +{
11184 + MTC0(C0_PERFORMANCE, 6, 0x80000218); /* enable I$ counting */
11185 + MTC0(C0_PERFORMANCE, 4, 0x80148018); /* count I$ hits in cntr 0 and misses in cntr 1 */
11186 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # I$ hits */
11187 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # I$ misses */
11188 +}
11189 +
11190 +/* enable and start D$ hit and I$ miss counting */
11191 +void
11192 +hndmips_perf_dcachecount_enable(void)
11193 +{
11194 + MTC0(C0_PERFORMANCE, 6, 0x80000211); /* enable D$ counting */
11195 + MTC0(C0_PERFORMANCE, 4, 0x80248028); /* count D$ hits in cntr 0 and misses in cntr 1 */
11196 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # D$ hits */
11197 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # D$ misses */
11198 +}
11199 +
11200 +void
11201 +hndmips_perf_icache_miss_enable()
11202 +{
11203 + MTC0(C0_PERFORMANCE, 4,
11204 + 0x80140000 | MFC0(C0_PERFORMANCE, 4)); /* enable cache misses counting for counter 1 */
11205 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter one */
11206 +}
11207 +
11208 +
11209 +void
11210 +hndmips_perf_icache_hit_enable()
11211 +{
11212 + MTC0(C0_PERFORMANCE, 5, 0x8018 | MFC0(C0_PERFORMANCE, 5));
11213 + /* enable cache hits counting for counter 2 */
11214 + MTC0(C0_PERFORMANCE, 2, 0); /* zero counter 2 */
11215 +}
11216 +
11217 +uint32
11218 +hndmips_perf_read_instrcount()
11219 +{
11220 + return -(long)(MFC0(C0_PERFORMANCE, 0));
11221 +}
11222 +
11223 +uint32
11224 +hndmips_perf_read_cache_miss()
11225 +{
11226 + return -(long)(MFC0(C0_PERFORMANCE, 1));
11227 +}
11228 +
11229 +uint32
11230 +hndmips_perf_read_cache_hit()
11231 +{
11232 + return -(long)(MFC0(C0_PERFORMANCE, 2));
11233 +}
11234 +
11235 +#endif /* BCMINTERNAL | BCMPERFSTATS */
11236 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
11237 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11238 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2006-05-02 17:37:13.000000000 +0200
11239 @@ -0,0 +1,768 @@
11240 +/*
11241 + * Low-Level PCI and SB support for BCM47xx
11242 + *
11243 + * Copyright 2006, Broadcom Corporation
11244 + * All Rights Reserved.
11245 + *
11246 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11247 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11248 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11249 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11250 + *
11251 + * $Id: hndpci.c,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
11252 + */
11253 +
11254 +#include <typedefs.h>
11255 +#include <osl.h>
11256 +#include <pcicfg.h>
11257 +#include <bcmdevs.h>
11258 +#include <sbconfig.h>
11259 +#include <bcmutils.h>
11260 +#include <sbutils.h>
11261 +#include <sbpci.h>
11262 +#include <bcmendian.h>
11263 +#include <bcmnvram.h>
11264 +#include <hndcpu.h>
11265 +#include <hndmips.h>
11266 +#include <hndpci.h>
11267 +
11268 +/* debug/trace */
11269 +#ifdef BCMDBG_PCI
11270 +#define PCI_MSG(args) printf args
11271 +#else
11272 +#define PCI_MSG(args)
11273 +#endif /* BCMDBG_PCI */
11274 +
11275 +/* Can free sbpci_init() memory after boot */
11276 +#ifndef linux
11277 +#define __init
11278 +#endif /* linux */
11279 +
11280 +/* Emulated configuration space */
11281 +typedef struct {
11282 + int n;
11283 + uint size0;
11284 + uint size1;
11285 + uint size2;
11286 + uint size3;
11287 +} sb_bar_cfg_t;
11288 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11289 +static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
11290 +
11291 +/* Links to emulated and real PCI configuration spaces */
11292 +#define MAXFUNCS 2
11293 +typedef struct {
11294 + pci_config_regs *emu; /* emulated PCI config */
11295 + pci_config_regs *pci; /* real PCI config */
11296 + sb_bar_cfg_t *bar; /* region sizes */
11297 +} sb_pci_cfg_t;
11298 +static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
11299 +
11300 +/* Special emulated config space for non-existing device */
11301 +static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
11302 +
11303 +/* Banned cores */
11304 +static uint16 pci_ban[SB_MAXCORES] = { 0 };
11305 +static uint pci_banned = 0;
11306 +
11307 +/* CardBus mode */
11308 +static bool cardbus = FALSE;
11309 +
11310 +/* Disable PCI host core */
11311 +static bool pci_disabled = FALSE;
11312 +
11313 +/* Host bridge slot #, default to 0 */
11314 +static uint8 pci_hbslot = 0;
11315 +
11316 +/* Internal macros */
11317 +#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
11318 +#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
11319 + * access host bridge PCI cfg space
11320 + * from SB
11321 + */
11322 +
11323 +/*
11324 + * Functions for accessing external PCI configuration space
11325 + */
11326 +
11327 +/* Assume one-hot slot wiring */
11328 +#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
11329 +
11330 +static uint32
11331 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
11332 +{
11333 + uint coreidx;
11334 + sbpciregs_t *regs;
11335 + uint32 addr = 0;
11336 + osl_t *osh;
11337 +
11338 + /* CardBusMode supports only one device */
11339 + if (cardbus && dev > 1)
11340 + return 0;
11341 +
11342 + osh = sb_osh(sbh);
11343 +
11344 + coreidx = sb_coreidx(sbh);
11345 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11346 +
11347 + /* Type 0 transaction */
11348 + if (bus == 1) {
11349 + /* Skip unwired slots */
11350 + if (dev < PCI_SLOT_MAX) {
11351 + uint32 win;
11352 +
11353 + /* Slide the PCI window to the appropriate slot */
11354 + win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
11355 + W_REG(osh, &regs->sbtopci1, win);
11356 + addr = SB_PCI_CFG |
11357 + ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
11358 + (func << PCICFG_FUN_SHIFT) |
11359 + (off & ~3);
11360 + }
11361 + } else {
11362 + /* Type 1 transaction */
11363 + W_REG(osh, &regs->sbtopci1, SBTOPCI_CFG1);
11364 + addr = SB_PCI_CFG |
11365 + (bus << PCICFG_BUS_SHIFT) |
11366 + (dev << PCICFG_SLOT_SHIFT) |
11367 + (func << PCICFG_FUN_SHIFT) |
11368 + (off & ~3);
11369 + }
11370 +
11371 + sb_setcoreidx(sbh, coreidx);
11372 +
11373 + return addr;
11374 +}
11375 +
11376 +/*
11377 + * Read host bridge PCI config registers from Silicon Backplane (>=rev8).
11378 + *
11379 + * It returns TRUE to indicate that access to the host bridge's pci config
11380 + * from SB is ok, and values in 'addr' and 'val' are valid.
11381 + *
11382 + * It can only read registers at multiple of 4-bytes. Callers must pick up
11383 + * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
11384 + * the register address where value in 'val' is read.
11385 + */
11386 +static bool
11387 +sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
11388 + uint32 **addr, uint32 *val)
11389 +{
11390 + sbpciregs_t *regs;
11391 + osl_t *osh;
11392 + uint coreidx;
11393 + bool ret = FALSE;
11394 +
11395 + /* sanity check */
11396 + ASSERT(bus == 1);
11397 + ASSERT(dev == pci_hbslot);
11398 + ASSERT(func == 0);
11399 +
11400 + osh = sb_osh(sbh);
11401 +
11402 + /* read pci config when core rev >= 8 */
11403 + coreidx = sb_coreidx(sbh);
11404 + regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
11405 + if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
11406 + *addr = (uint32 *)&regs->pcicfg[func][off >> 2];
11407 + *val = R_REG(osh, *addr);
11408 + ret = TRUE;
11409 + }
11410 + sb_setcoreidx(sbh, coreidx);
11411 +
11412 + return ret;
11413 +}
11414 +
11415 +int
11416 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11417 +{
11418 + uint32 addr = 0, *reg = NULL, val;
11419 + int ret = 0;
11420 +
11421 + /*
11422 + * Set value to -1 when:
11423 + * flag 'pci_disabled' is true;
11424 + * value of 'addr' is zero;
11425 + * REG_MAP() fails;
11426 + * BUSPROBE() fails;
11427 + */
11428 + if (pci_disabled)
11429 + val = 0xffffffff;
11430 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11431 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11432 + ;
11433 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11434 + ((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
11435 + (BUSPROBE(val, reg) != 0))
11436 + val = 0xffffffff;
11437 +
11438 + PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
11439 + __FUNCTION__, val, reg, addr, len, off, buf));
11440 +
11441 + val >>= 8 * (off & 3);
11442 + if (len == 4)
11443 + *((uint32 *) buf) = val;
11444 + else if (len == 2)
11445 + *((uint16 *) buf) = (uint16) val;
11446 + else if (len == 1)
11447 + *((uint8 *) buf) = (uint8) val;
11448 + else
11449 + ret = -1;
11450 +
11451 + if (reg && addr)
11452 + REG_UNMAP(reg);
11453 +
11454 + return ret;
11455 +}
11456 +
11457 +int
11458 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11459 +{
11460 + osl_t *osh;
11461 + uint32 addr = 0, *reg = NULL, val;
11462 + int ret = 0;
11463 +
11464 + osh = sb_osh(sbh);
11465 +
11466 + /*
11467 + * Ignore write attempt when:
11468 + * flag 'pci_disabled' is true;
11469 + * value of 'addr' is zero;
11470 + * REG_MAP() fails;
11471 + * BUSPROBE() fails;
11472 + */
11473 + if (pci_disabled)
11474 + return 0;
11475 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11476 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11477 + ;
11478 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11479 + ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
11480 + (BUSPROBE(val, reg) != 0))
11481 + goto done;
11482 +
11483 + if (len == 4)
11484 + val = *((uint32 *) buf);
11485 + else if (len == 2) {
11486 + val &= ~(0xffff << (8 * (off & 3)));
11487 + val |= *((uint16 *) buf) << (8 * (off & 3));
11488 + } else if (len == 1) {
11489 + val &= ~(0xff << (8 * (off & 3)));
11490 + val |= *((uint8 *) buf) << (8 * (off & 3));
11491 + } else {
11492 + ret = -1;
11493 + goto done;
11494 + }
11495 +
11496 + PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
11497 +
11498 + W_REG(osh, reg, val);
11499 +
11500 +done:
11501 + if (reg && addr)
11502 + REG_UNMAP(reg);
11503 +
11504 + return ret;
11505 +}
11506 +
11507 +/*
11508 + * Must access emulated PCI configuration at these locations even when
11509 + * the real PCI config space exists and is accessible.
11510 + *
11511 + * PCI_CFG_VID (0x00)
11512 + * PCI_CFG_DID (0x02)
11513 + * PCI_CFG_PROGIF (0x09)
11514 + * PCI_CFG_SUBCL (0x0a)
11515 + * PCI_CFG_BASECL (0x0b)
11516 + * PCI_CFG_HDR (0x0e)
11517 + * PCI_CFG_INT (0x3c)
11518 + * PCI_CFG_PIN (0x3d)
11519 + */
11520 +#define FORCE_EMUCFG(off, len) \
11521 + ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
11522 + (off == PCI_CFG_PROGIF) || \
11523 + (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
11524 + (off == PCI_CFG_HDR) || \
11525 + (off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
11526 +
11527 +/* Sync the emulation registers and the real PCI config registers. */
11528 +static void
11529 +sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11530 + uint off, uint len)
11531 +{
11532 + osl_t *osh;
11533 + uint oldidx;
11534 +
11535 + ASSERT(cfg);
11536 + ASSERT(cfg->emu);
11537 + ASSERT(cfg->pci);
11538 +
11539 + /* decide if real PCI config register access is necessary */
11540 + if (FORCE_EMUCFG(off, len))
11541 + return;
11542 +
11543 + osh = sb_osh(sbh);
11544 +
11545 + /* access to the real pci config space only when the core is up */
11546 + oldidx = sb_coreidx(sbh);
11547 + sb_setcoreidx(sbh, coreidx);
11548 + if (sb_iscoreup(sbh)) {
11549 + if (len == 4)
11550 + *(uint32 *)((ulong)cfg->emu + off) =
11551 + htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
11552 + else if (len == 2)
11553 + *(uint16 *)((ulong)cfg->emu + off) =
11554 + htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
11555 + else if (len == 1)
11556 + *(uint8 *)((ulong)cfg->emu + off) =
11557 + R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
11558 + }
11559 + sb_setcoreidx(sbh, oldidx);
11560 +}
11561 +
11562 +static void
11563 +sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11564 + uint off, uint len)
11565 +{
11566 + osl_t *osh;
11567 + uint oldidx;
11568 +
11569 + ASSERT(cfg);
11570 + ASSERT(cfg->emu);
11571 + ASSERT(cfg->pci);
11572 +
11573 + osh = sb_osh(sbh);
11574 +
11575 + /* decide if real PCI config register access is necessary */
11576 + if (FORCE_EMUCFG(off, len))
11577 + return;
11578 +
11579 + /* access to the real pci config space only when the core is up */
11580 + oldidx = sb_coreidx(sbh);
11581 + sb_setcoreidx(sbh, coreidx);
11582 + if (sb_iscoreup(sbh)) {
11583 + if (len == 4)
11584 + W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
11585 + ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
11586 + else if (len == 2)
11587 + W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
11588 + ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
11589 + else if (len == 1)
11590 + W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
11591 + *(uint8 *)((ulong)cfg->emu + off));
11592 + }
11593 + sb_setcoreidx(sbh, oldidx);
11594 +}
11595 +
11596 +/*
11597 + * Functions for accessing translated SB configuration space
11598 + */
11599 +static int
11600 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11601 +{
11602 + pci_config_regs *cfg;
11603 +
11604 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11605 + return -1;
11606 + cfg = sb_pci_cfg[dev][func].emu;
11607 +
11608 + ASSERT(ISALIGNED(off, len));
11609 + ASSERT(ISALIGNED((uintptr)buf, len));
11610 +
11611 + /* use special config space if the device does not exist */
11612 + if (!cfg)
11613 + cfg = &sb_pci_null;
11614 + /* sync emulation with real PCI config if necessary */
11615 + else if (sb_pci_cfg[dev][func].pci)
11616 + sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11617 +
11618 + if (len == 4)
11619 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11620 + else if (len == 2)
11621 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11622 + else if (len == 1)
11623 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11624 + else
11625 + return -1;
11626 +
11627 + return 0;
11628 +}
11629 +
11630 +static int
11631 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11632 +{
11633 + uint coreidx;
11634 + void *regs;
11635 + pci_config_regs *cfg;
11636 + osl_t *osh;
11637 + sb_bar_cfg_t *bar;
11638 +
11639 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11640 + return -1;
11641 + cfg = sb_pci_cfg[dev][func].emu;
11642 + if (!cfg)
11643 + return -1;
11644 +
11645 + ASSERT(ISALIGNED(off, len));
11646 + ASSERT(ISALIGNED((uintptr)buf, len));
11647 +
11648 + osh = sb_osh(sbh);
11649 +
11650 + /* Emulate BAR sizing */
11651 + if (off >= OFFSETOF(pci_config_regs, base[0]) &&
11652 + off <= OFFSETOF(pci_config_regs, base[3]) &&
11653 + len == 4 && *((uint32 *) buf) == ~0) {
11654 + coreidx = sb_coreidx(sbh);
11655 + if ((regs = sb_setcoreidx(sbh, dev))) {
11656 + bar = sb_pci_cfg[dev][func].bar;
11657 + /* Highest numbered address match register */
11658 + if (off == OFFSETOF(pci_config_regs, base[0]))
11659 + cfg->base[0] = ~(bar->size0 - 1);
11660 + else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
11661 + cfg->base[1] = ~(bar->size1 - 1);
11662 + else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
11663 + cfg->base[2] = ~(bar->size2 - 1);
11664 + else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
11665 + cfg->base[3] = ~(bar->size3 - 1);
11666 + }
11667 + sb_setcoreidx(sbh, coreidx);
11668 + }
11669 + else if (len == 4)
11670 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11671 + else if (len == 2)
11672 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11673 + else if (len == 1)
11674 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11675 + else
11676 + return -1;
11677 +
11678 + /* sync emulation with real PCI config if necessary */
11679 + if (sb_pci_cfg[dev][func].pci)
11680 + sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11681 +
11682 + return 0;
11683 +}
11684 +
11685 +int
11686 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11687 +{
11688 + if (bus == 0)
11689 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11690 + else
11691 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11692 +}
11693 +
11694 +int
11695 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11696 +{
11697 + if (bus == 0)
11698 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11699 + else
11700 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11701 +}
11702 +
11703 +void
11704 +sbpci_ban(uint16 core)
11705 +{
11706 + if (pci_banned < ARRAYSIZE(pci_ban))
11707 + pci_ban[pci_banned++] = core;
11708 +}
11709 +
11710 +/*
11711 + * Initiliaze PCI core. Return 0 after a successful initialization.
11712 + * Otherwise return -1 to indicate there is no PCI core and return 1
11713 + * to indicate PCI core is disabled.
11714 + */
11715 +int __init
11716 +sbpci_init_pci(sb_t *sbh)
11717 +{
11718 + uint chip, chiprev, chippkg, host;
11719 + uint32 boardflags;
11720 + sbpciregs_t *pci;
11721 + sbconfig_t *sb;
11722 + uint32 val;
11723 + int ret = 0;
11724 + char *hbslot;
11725 + osl_t *osh;
11726 +
11727 + chip = sb_chip(sbh);
11728 + chiprev = sb_chiprev(sbh);
11729 + chippkg = sb_chippkg(sbh);
11730 +
11731 + osh = sb_osh(sbh);
11732 +
11733 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
11734 + printk("PCI: no core\n");
11735 + pci_disabled = TRUE;
11736 + return -1;
11737 + }
11738 +
11739 + if ((chip == 0x4710) && (chiprev == 0))
11740 + pci_disabled = TRUE;
11741 +
11742 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11743 +
11744 + boardflags = (uint32) getintvar(NULL, "boardflags");
11745 +
11746 + /*
11747 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11748 + * PCI is bonded out, some boards may leave the pins
11749 + * floating.
11750 + */
11751 + if (((chip == BCM4712_CHIP_ID) &&
11752 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11753 + (chippkg == BCM4712MID_PKG_ID))) ||
11754 + (boardflags & BFL_NOPCI))
11755 + pci_disabled = TRUE;
11756 +
11757 + /* Enable the core */
11758 + sb_core_reset(sbh, 0, 0);
11759 +
11760 + /*
11761 + * If the PCI core should not be touched (disabled, not bonded
11762 + * out, or pins floating), do not even attempt to access core
11763 + * registers. Otherwise, try to determine if it is in host
11764 + * mode.
11765 + */
11766 + if (pci_disabled)
11767 + host = 0;
11768 + else
11769 + host = !BUSPROBE(val, &pci->control);
11770 +
11771 + if (!host) {
11772 + ret = 1;
11773 +
11774 + /* Disable PCI interrupts in client mode */
11775 + W_REG(osh, &sb->sbintvec, 0);
11776 +
11777 + /* Disable the PCI bridge in client mode */
11778 + sbpci_ban(SB_PCI);
11779 + sb_core_disable(sbh, 0);
11780 +
11781 + printk("PCI: Disabled\n");
11782 + } else {
11783 + printk("PCI: Initializing host\n");
11784 +
11785 + /* Disable PCI SBReqeustTimeout for BCM4785 */
11786 + if (chip == BCM4785_CHIP_ID) {
11787 + AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
11788 + sb_commit(sbh);
11789 + }
11790 +
11791 + /* Reset the external PCI bus and enable the clock */
11792 + W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
11793 + W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
11794 + OSL_DELAY(150); /* delay > 100 us */
11795 + W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
11796 + /* Use internal arbiter and park REQ/GRNT at external master 0 */
11797 + W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
11798 + OSL_DELAY(1); /* delay 1 us */
11799 + if (sb_corerev(sbh) >= 8) {
11800 + val = getintvar(NULL, "parkid");
11801 + ASSERT(val <= PCI_PARKID_LAST);
11802 + OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
11803 + OSL_DELAY(1);
11804 + }
11805 +
11806 + /* Enable CardBusMode */
11807 + cardbus = getintvar(NULL, "cardbus") == 1;
11808 + if (cardbus) {
11809 + printk("PCI: Enabling CardBus\n");
11810 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11811 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
11812 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
11813 + W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
11814 + }
11815 +
11816 + /* 64 MB I/O access window */
11817 + W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
11818 + /* 64 MB configuration access window */
11819 + W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
11820 + /* 1 GB memory access window */
11821 + W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11822 +
11823 + /* Host bridge slot # nvram overwrite */
11824 + if ((hbslot = nvram_get("pcihbslot"))) {
11825 + pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
11826 + ASSERT(pci_hbslot < PCI_MAX_DEVICES);
11827 + }
11828 +
11829 + /* Enable PCI bridge BAR0 prefetch and burst */
11830 + val = 6;
11831 + sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
11832 +
11833 + /* Enable PCI interrupts */
11834 + W_REG(osh, &pci->intmask, PCI_INTA);
11835 + }
11836 +
11837 + return ret;
11838 +}
11839 +
11840 +/*
11841 + * Get the PCI region address and size information.
11842 + */
11843 +static void __init
11844 +sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
11845 +{
11846 + osl_t *osh;
11847 + uint16 coreid;
11848 + void *regs;
11849 + sbconfig_t *sb;
11850 + uint32 base;
11851 +
11852 + osh = sb_osh(sbh);
11853 + coreid = sb_coreid(sbh);
11854 + regs = sb_coreregs(sbh);
11855 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11856 +
11857 + switch (coreid) {
11858 + case SB_USB20H:
11859 + base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11860 +
11861 + cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
11862 + cfg->base[1] = 0;
11863 + cfg->base[2] = 0;
11864 + cfg->base[3] = 0;
11865 + cfg->base[4] = 0;
11866 + cfg->base[5] = 0;
11867 + bar->n = 1;
11868 + bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
11869 + bar->size1 = 0;
11870 + bar->size2 = 0;
11871 + bar->size3 = 0;
11872 + break;
11873 + default:
11874 + cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11875 + cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
11876 + cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
11877 + cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
11878 + cfg->base[4] = 0;
11879 + cfg->base[5] = 0;
11880 + bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11881 + bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
11882 + bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
11883 + bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
11884 + bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
11885 + break;
11886 + }
11887 +}
11888 +
11889 +/*
11890 + * Construct PCI config spaces for SB cores so that they
11891 + * can be accessed as if they were PCI devices.
11892 + */
11893 +static void __init
11894 +sbpci_init_cores(sb_t *sbh)
11895 +{
11896 + uint chiprev, coreidx, i;
11897 + sbconfig_t *sb;
11898 + pci_config_regs *cfg, *pci;
11899 + sb_bar_cfg_t *bar;
11900 + void *regs;
11901 + osl_t *osh;
11902 + uint16 vendor, device;
11903 + uint16 coreid;
11904 + uint8 class, subclass, progif;
11905 + uint dev;
11906 + uint8 header;
11907 + uint func;
11908 +
11909 + chiprev = sb_chiprev(sbh);
11910 + coreidx = sb_coreidx(sbh);
11911 +
11912 + osh = sb_osh(sbh);
11913 +
11914 + /* Scan the SB bus */
11915 + bzero(sb_config_regs, sizeof(sb_config_regs));
11916 + bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
11917 + bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
11918 + memset(&sb_pci_null, -1, sizeof(sb_pci_null));
11919 + cfg = sb_config_regs;
11920 + bar = sb_bar_cfg;
11921 + for (dev = 0; dev < SB_MAXCORES; dev ++) {
11922 + /* Check if the core exists */
11923 + if (!(regs = sb_setcoreidx(sbh, dev)))
11924 + continue;
11925 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11926 +
11927 + /* Check if this core is banned */
11928 + coreid = sb_coreid(sbh);
11929 + for (i = 0; i < pci_banned; i++)
11930 + if (coreid == pci_ban[i])
11931 + break;
11932 + if (i < pci_banned)
11933 + continue;
11934 +
11935 + for (func = 0; func < MAXFUNCS; ++func) {
11936 + /* Make sure we won't go beyond the limit */
11937 + if (cfg >= &sb_config_regs[SB_MAXCORES]) {
11938 + printk("PCI: too many emulated devices\n");
11939 + goto done;
11940 + }
11941 +
11942 + /* Convert core id to pci id */
11943 + if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
11944 + &progif, &header))
11945 + continue;
11946 +
11947 + /*
11948 + * Differentiate real PCI config from emulated.
11949 + * non zero 'pci' indicate there is a real PCI config space
11950 + * for this device.
11951 + */
11952 + switch (device) {
11953 + case BCM47XX_GIGETH_ID:
11954 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11955 + break;
11956 + case BCM47XX_SATAXOR_ID:
11957 + pci = (pci_config_regs *)((uint32)regs + 0x400);
11958 + break;
11959 + case BCM47XX_ATA100_ID:
11960 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11961 + break;
11962 + default:
11963 + pci = NULL;
11964 + break;
11965 + }
11966 + /* Supported translations */
11967 + cfg->vendor = htol16(vendor);
11968 + cfg->device = htol16(device);
11969 + cfg->rev_id = chiprev;
11970 + cfg->prog_if = progif;
11971 + cfg->sub_class = subclass;
11972 + cfg->base_class = class;
11973 + cfg->header_type = header;
11974 + sbpci_init_regions(sbh, func, cfg, bar);
11975 + /* Save core interrupt flag */
11976 + cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
11977 + /* Save core interrupt assignment */
11978 + cfg->int_line = sb_irq(sbh);
11979 + /* Indicate there is no SROM */
11980 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
11981 +
11982 + /* Point to the PCI config spaces */
11983 + sb_pci_cfg[dev][func].emu = cfg;
11984 + sb_pci_cfg[dev][func].pci = pci;
11985 + sb_pci_cfg[dev][func].bar = bar;
11986 + cfg ++;
11987 + bar ++;
11988 + }
11989 + }
11990 +
11991 +done:
11992 + sb_setcoreidx(sbh, coreidx);
11993 +}
11994 +
11995 +/*
11996 + * Initialize PCI core and construct PCI config spaces for SB cores.
11997 + * Must propagate sbpci_init_pci() return value to the caller to let
11998 + * them know the PCI core initialization status.
11999 + */
12000 +int __init
12001 +sbpci_init(sb_t *sbh)
12002 +{
12003 + int status = sbpci_init_pci(sbh);
12004 + sbpci_init_cores(sbh);
12005 + return status;
12006 +}
12007 +
12008 diff -urN linux.old/arch/mips/bcm947xx/sbutils.c linux.dev/arch/mips/bcm947xx/sbutils.c
12009 --- linux.old/arch/mips/bcm947xx/sbutils.c 1970-01-01 01:00:00.000000000 +0100
12010 +++ linux.dev/arch/mips/bcm947xx/sbutils.c 2006-05-02 04:33:16.000000000 +0200
12011 @@ -0,0 +1,3081 @@
12012 +/*
12013 + * Misc utility routines for accessing chip-specific features
12014 + * of the SiliconBackplane-based Broadcom chips.
12015 + *
12016 + * Copyright 2006, Broadcom Corporation
12017 + * All Rights Reserved.
12018 + *
12019 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12020 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12021 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12022 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12023 + * $Id: sbutils.c,v 1.10 2006/04/08 07:12:42 honor Exp $
12024 + */
12025 +
12026 +#include <typedefs.h>
12027 +#include <bcmdefs.h>
12028 +#include <osl.h>
12029 +#include <bcmutils.h>
12030 +#include <sbutils.h>
12031 +#include <bcmdevs.h>
12032 +#include <sbconfig.h>
12033 +#include <sbchipc.h>
12034 +#include <sbpci.h>
12035 +#include <sbpcie.h>
12036 +#include <pcicfg.h>
12037 +#include <sbpcmcia.h>
12038 +#include <sbextif.h>
12039 +#include <sbsocram.h>
12040 +#include <bcmsrom.h>
12041 +#ifdef __mips__
12042 +#include <mipsinc.h>
12043 +#endif /* __mips__ */
12044 +
12045 +/* debug/trace */
12046 +#define SB_ERROR(args)
12047 +
12048 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
12049 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
12050 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
12051 +
12052 +/* misc sb info needed by some of the routines */
12053 +typedef struct sb_info {
12054 +
12055 + struct sb_pub sb; /* back plane public state (must be first field) */
12056 +
12057 + void *osh; /* osl os handle */
12058 + void *sdh; /* bcmsdh handle */
12059 +
12060 + void *curmap; /* current regs va */
12061 + void *regs[SB_MAXCORES]; /* other regs va */
12062 +
12063 + uint curidx; /* current core index */
12064 + uint dev_coreid; /* the core provides driver functions */
12065 +
12066 + bool memseg; /* flag to toggle MEM_SEG register */
12067 +
12068 + uint gpioidx; /* gpio control core index */
12069 + uint gpioid; /* gpio control coretype */
12070 +
12071 + uint numcores; /* # discovered cores */
12072 + uint coreid[SB_MAXCORES]; /* id of each core */
12073 +
12074 + void *intr_arg; /* interrupt callback function arg */
12075 + sb_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
12076 + sb_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
12077 + sb_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
12078 +
12079 +} sb_info_t;
12080 +
12081 +/* local prototypes */
12082 +static sb_info_t * sb_doattach(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12083 + uint bustype, void *sdh, char **vars, uint *varsz);
12084 +static void sb_scan(sb_info_t *si);
12085 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
12086 +static uint _sb_coreidx(sb_info_t *si);
12087 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
12088 +static uint sb_pcidev2chip(uint pcidev);
12089 +static uint sb_chip2numcores(uint chip);
12090 +static bool sb_ispcie(sb_info_t *si);
12091 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
12092 +static int sb_pci_fixcfg(sb_info_t *si);
12093 +
12094 +/* routines to access mdio slave device registers */
12095 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
12096 +static void sb_war30841(sb_info_t *si);
12097 +
12098 +/* delay needed between the mdio control/ mdiodata register data access */
12099 +#define PR28829_DELAY() OSL_DELAY(10)
12100 +
12101 +/* size that can take bitfielddump */
12102 +#define BITFIELD_DUMP_SIZE 32
12103 +
12104 +/* global variable to indicate reservation/release of gpio's */
12105 +static uint32 sb_gpioreservation = 0;
12106 +
12107 +#define SB_INFO(sbh) (sb_info_t*)sbh
12108 +#define SET_SBREG(si, r, mask, val) \
12109 + W_SBREG((si), (r), ((R_SBREG((si), (r)) & ~(mask)) | (val)))
12110 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && \
12111 + ISALIGNED((x), SB_CORE_SIZE))
12112 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
12113 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
12114 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
12115 +#define BADIDX (SB_MAXCORES+1)
12116 +#define NOREV -1 /* Invalid rev */
12117 +
12118 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
12119 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
12120 +
12121 +/* sonicsrev */
12122 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
12123 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
12124 +
12125 +#define R_SBREG(si, sbr) sb_read_sbreg((si), (sbr))
12126 +#define W_SBREG(si, sbr, v) sb_write_sbreg((si), (sbr), (v))
12127 +#define AND_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) & (v)))
12128 +#define OR_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) | (v)))
12129 +
12130 +/*
12131 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
12132 + * after core switching to avoid invalid register accesss inside ISR.
12133 + */
12134 +#define INTR_OFF(si, intr_val) \
12135 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12136 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
12137 +#define INTR_RESTORE(si, intr_val) \
12138 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12139 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
12140 +
12141 +/* dynamic clock control defines */
12142 +#define LPOMINFREQ 25000 /* low power oscillator min */
12143 +#define LPOMAXFREQ 43000 /* low power oscillator max */
12144 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
12145 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
12146 +#define PCIMINFREQ 25000000 /* 25 MHz */
12147 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
12148 +
12149 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
12150 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
12151 +
12152 +/* different register spaces to access thr'u pcie indirect access */
12153 +#define PCIE_CONFIGREGS 1 /* Access to config space */
12154 +#define PCIE_PCIEREGS 2 /* Access to pcie registers */
12155 +
12156 +/* GPIO Based LED powersave defines */
12157 +#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
12158 +#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
12159 +
12160 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
12161 +
12162 +static uint32
12163 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
12164 +{
12165 + uint8 tmp;
12166 + uint32 val, intr_val = 0;
12167 +
12168 +
12169 + /*
12170 + * compact flash only has 11 bits address, while we needs 12 bits address.
12171 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12172 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12173 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12174 + */
12175 + if (si->memseg) {
12176 + INTR_OFF(si, intr_val);
12177 + tmp = 1;
12178 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12179 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12180 + }
12181 +
12182 + val = R_REG(si->osh, sbr);
12183 +
12184 + if (si->memseg) {
12185 + tmp = 0;
12186 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12187 + INTR_RESTORE(si, intr_val);
12188 + }
12189 +
12190 + return (val);
12191 +}
12192 +
12193 +static void
12194 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
12195 +{
12196 + uint8 tmp;
12197 + volatile uint32 dummy;
12198 + uint32 intr_val = 0;
12199 +
12200 +
12201 + /*
12202 + * compact flash only has 11 bits address, while we needs 12 bits address.
12203 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12204 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12205 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12206 + */
12207 + if (si->memseg) {
12208 + INTR_OFF(si, intr_val);
12209 + tmp = 1;
12210 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12211 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12212 + }
12213 +
12214 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12215 +#ifdef IL_BIGENDIAN
12216 + dummy = R_REG(si->osh, sbr);
12217 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12218 + dummy = R_REG(si->osh, sbr);
12219 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12220 +#else
12221 + dummy = R_REG(si->osh, sbr);
12222 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12223 + dummy = R_REG(si->osh, sbr);
12224 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12225 +#endif /* IL_BIGENDIAN */
12226 + } else
12227 + W_REG(si->osh, sbr, v);
12228 +
12229 + if (si->memseg) {
12230 + tmp = 0;
12231 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12232 + INTR_RESTORE(si, intr_val);
12233 + }
12234 +}
12235 +
12236 +/*
12237 + * Allocate a sb handle.
12238 + * devid - pci device id (used to determine chip#)
12239 + * osh - opaque OS handle
12240 + * regs - virtual address of initial core registers
12241 + * bustype - pci/pcmcia/sb/sdio/etc
12242 + * vars - pointer to a pointer area for "environment" variables
12243 + * varsz - pointer to int to return the size of the vars
12244 + */
12245 +sb_t *
12246 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
12247 + uint bustype, void *sdh, char **vars, uint *varsz)
12248 +{
12249 + sb_info_t *si;
12250 +
12251 + /* alloc sb_info_t */
12252 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
12253 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
12254 + return (NULL);
12255 + }
12256 +
12257 + if (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, (uint*)varsz) == NULL) {
12258 + MFREE(osh, si, sizeof(sb_info_t));
12259 + return (NULL);
12260 + }
12261 +
12262 + return (sb_t *)si;
12263 +}
12264 +
12265 +/* Using sb_kattach depends on SB_BUS support, either implicit */
12266 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
12267 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12268 +
12269 +/* global kernel resource */
12270 +static sb_info_t ksi;
12271 +static bool ksi_attached = FALSE;
12272 +
12273 +/* generic kernel variant of sb_attach() */
12274 +sb_t *
12275 +BCMINITFN(sb_kattach)(void)
12276 +{
12277 + osl_t *osh = NULL;
12278 + uint32 *regs;
12279 +
12280 + if (!ksi_attached) {
12281 + uint32 cid;
12282 +
12283 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
12284 + cid = R_REG(osh, (uint32 *)regs);
12285 + if (((cid & CID_ID_MASK) == BCM4712_CHIP_ID) &&
12286 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
12287 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
12288 + uint32 *scc, val;
12289 +
12290 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
12291 + val = R_REG(osh, scc);
12292 + SB_ERROR((" initial scc = 0x%x\n", val));
12293 + val |= SCC_SS_XTAL;
12294 + W_REG(osh, scc, val);
12295 + }
12296 +
12297 + if (sb_doattach(&ksi, BCM4710_DEVICE_ID, osh, (void*)regs,
12298 + SB_BUS, NULL, NULL, NULL) == NULL) {
12299 + return NULL;
12300 + }
12301 + else
12302 + ksi_attached = TRUE;
12303 + }
12304 +
12305 + return (sb_t *)&ksi;
12306 +}
12307 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12308 +
12309 +static sb_info_t *
12310 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12311 + uint bustype, void *sdh, char **vars, uint *varsz)
12312 +{
12313 + uint origidx;
12314 + chipcregs_t *cc;
12315 + sbconfig_t *sb;
12316 + uint32 w;
12317 +
12318 + ASSERT(GOODREGS(regs));
12319 +
12320 + bzero((uchar*)si, sizeof(sb_info_t));
12321 +
12322 + si->sb.buscoreidx = si->gpioidx = BADIDX;
12323 +
12324 + si->curmap = regs;
12325 + si->sdh = sdh;
12326 + si->osh = osh;
12327 +
12328 + /* check to see if we are a sb core mimic'ing a pci core */
12329 + if (bustype == PCI_BUS) {
12330 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff) {
12331 + SB_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SB "
12332 + "devid:0x%x\n", __FUNCTION__, devid));
12333 + bustype = SB_BUS;
12334 + }
12335 + }
12336 +
12337 + si->sb.bustype = bustype;
12338 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
12339 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
12340 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
12341 + return NULL;
12342 + }
12343 +
12344 + /* need to set memseg flag for CF card first before any sb registers access */
12345 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
12346 + si->memseg = TRUE;
12347 +
12348 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
12349 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
12350 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
12351 +
12352 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12353 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12354 + if (!GOODCOREADDR(w))
12355 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32), SB_ENUM_BASE);
12356 + }
12357 +
12358 + /* initialize current core index value */
12359 + si->curidx = _sb_coreidx(si);
12360 +
12361 + if (si->curidx == BADIDX) {
12362 + SB_ERROR(("sb_doattach: bad core index\n"));
12363 + return NULL;
12364 + }
12365 +
12366 + /* get sonics backplane revision */
12367 + sb = REGS2SB(si->curmap);
12368 + si->sb.sonicsrev = (R_SBREG(si, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
12369 +
12370 + /* keep and reuse the initial register mapping */
12371 + origidx = si->curidx;
12372 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12373 + si->regs[origidx] = regs;
12374 +
12375 + /* is core-0 a chipcommon core? */
12376 + si->numcores = 1;
12377 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
12378 + if (sb_coreid(&si->sb) != SB_CC)
12379 + cc = NULL;
12380 +
12381 + /* determine chip id and rev */
12382 + if (cc) {
12383 + /* chip common core found! */
12384 + si->sb.chip = R_REG(si->osh, &cc->chipid) & CID_ID_MASK;
12385 + si->sb.chiprev = (R_REG(si->osh, &cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
12386 + si->sb.chippkg = (R_REG(si->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
12387 + } else {
12388 + /* no chip common core -- must convert device id to chip id */
12389 + if ((si->sb.chip = sb_pcidev2chip(devid)) == 0) {
12390 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
12391 + sb_setcoreidx(&si->sb, origidx);
12392 + return NULL;
12393 + }
12394 + }
12395 +
12396 + /* get chipcommon rev */
12397 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
12398 +
12399 + /* determine numcores */
12400 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
12401 + si->numcores = (R_REG(si->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
12402 + else
12403 + si->numcores = sb_chip2numcores(si->sb.chip);
12404 +
12405 + /* return to original core */
12406 + sb_setcoreidx(&si->sb, origidx);
12407 +
12408 + /* sanity checks */
12409 + ASSERT(si->sb.chip);
12410 +
12411 + /* scan for cores */
12412 + sb_scan(si);
12413 +
12414 + /* fixup necessary chip/core configurations */
12415 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12416 + if (sb_pci_fixcfg(si)) {
12417 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
12418 + return NULL;
12419 + }
12420 + }
12421 +
12422 + /* srom_var_init() depends on sb_scan() info */
12423 + if (srom_var_init(si, si->sb.bustype, si->curmap, si->osh, vars, varsz)) {
12424 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
12425 + return (NULL);
12426 + }
12427 +
12428 + if (cc == NULL) {
12429 + /*
12430 + * The chip revision number is hardwired into all
12431 + * of the pci function config rev fields and is
12432 + * independent from the individual core revision numbers.
12433 + * For example, the "A0" silicon of each chip is chip rev 0.
12434 + * For PCMCIA we get it from the CIS instead.
12435 + */
12436 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12437 + ASSERT(vars);
12438 + si->sb.chiprev = getintvar(*vars, "chiprev");
12439 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12440 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_REV, sizeof(uint32));
12441 + si->sb.chiprev = w & 0xff;
12442 + } else
12443 + si->sb.chiprev = 0;
12444 + }
12445 +
12446 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12447 + w = getintvar(*vars, "regwindowsz");
12448 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
12449 + }
12450 +
12451 + /* gpio control core is required */
12452 + if (!GOODIDX(si->gpioidx)) {
12453 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
12454 + return NULL;
12455 + }
12456 +
12457 + /* get boardtype and boardrev */
12458 + switch (BUSTYPE(si->sb.bustype)) {
12459 + case PCI_BUS:
12460 + /* do a pci config read to get subsystem id and subvendor id */
12461 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_SVID, sizeof(uint32));
12462 + si->sb.boardvendor = w & 0xffff;
12463 + si->sb.boardtype = (w >> 16) & 0xffff;
12464 + break;
12465 +
12466 + case PCMCIA_BUS:
12467 + case SDIO_BUS:
12468 + si->sb.boardvendor = getintvar(*vars, "manfid");
12469 + si->sb.boardtype = getintvar(*vars, "prodid");
12470 + break;
12471 +
12472 + case SB_BUS:
12473 + case JTAG_BUS:
12474 + si->sb.boardvendor = VENDOR_BROADCOM;
12475 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
12476 + si->sb.boardtype = 0xffff;
12477 + break;
12478 + }
12479 +
12480 + if (si->sb.boardtype == 0) {
12481 + SB_ERROR(("sb_doattach: unknown board type\n"));
12482 + ASSERT(si->sb.boardtype);
12483 + }
12484 +
12485 + /* setup the GPIO based LED powersave register */
12486 + if (si->sb.ccrev >= 16) {
12487 + if ((vars == NULL) || ((w = getintvar(*vars, "leddc")) == 0))
12488 + w = DEFAULT_GPIOTIMERVAL;
12489 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
12490 + }
12491 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1)) {
12492 + /* set proper clk setup delays before forcing HT */
12493 + sb_clkctl_init((void *)si);
12494 + sb_corereg((void*)si, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl),
12495 + SYCC_HR, SYCC_HR);
12496 + }
12497 +
12498 +
12499 + return (si);
12500 +}
12501 +
12502 +uint
12503 +sb_coreid(sb_t *sbh)
12504 +{
12505 + sb_info_t *si;
12506 + sbconfig_t *sb;
12507 +
12508 + si = SB_INFO(sbh);
12509 + sb = REGS2SB(si->curmap);
12510 +
12511 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
12512 +}
12513 +
12514 +uint
12515 +sb_coreidx(sb_t *sbh)
12516 +{
12517 + sb_info_t *si;
12518 +
12519 + si = SB_INFO(sbh);
12520 + return (si->curidx);
12521 +}
12522 +
12523 +/* return current index of core */
12524 +static uint
12525 +_sb_coreidx(sb_info_t *si)
12526 +{
12527 + sbconfig_t *sb;
12528 + uint32 sbaddr = 0;
12529 +
12530 + ASSERT(si);
12531 +
12532 + switch (BUSTYPE(si->sb.bustype)) {
12533 + case SB_BUS:
12534 + sb = REGS2SB(si->curmap);
12535 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
12536 + break;
12537 +
12538 + case PCI_BUS:
12539 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12540 + break;
12541 +
12542 + case PCMCIA_BUS: {
12543 + uint8 tmp = 0;
12544 +
12545 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
12546 + sbaddr = (uint)tmp << 12;
12547 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
12548 + sbaddr |= (uint)tmp << 16;
12549 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
12550 + sbaddr |= (uint)tmp << 24;
12551 + break;
12552 + }
12553 +
12554 +#ifdef BCMJTAG
12555 + case JTAG_BUS:
12556 + sbaddr = (uint32)si->curmap;
12557 + break;
12558 +#endif /* BCMJTAG */
12559 +
12560 + default:
12561 + ASSERT(0);
12562 + }
12563 +
12564 + if (!GOODCOREADDR(sbaddr))
12565 + return BADIDX;
12566 +
12567 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
12568 +}
12569 +
12570 +uint
12571 +sb_corevendor(sb_t *sbh)
12572 +{
12573 + sb_info_t *si;
12574 + sbconfig_t *sb;
12575 +
12576 + si = SB_INFO(sbh);
12577 + sb = REGS2SB(si->curmap);
12578 +
12579 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
12580 +}
12581 +
12582 +uint
12583 +sb_corerev(sb_t *sbh)
12584 +{
12585 + sb_info_t *si;
12586 + sbconfig_t *sb;
12587 + uint sbidh;
12588 +
12589 + si = SB_INFO(sbh);
12590 + sb = REGS2SB(si->curmap);
12591 + sbidh = R_SBREG(si, &sb->sbidhigh);
12592 +
12593 + return (SBCOREREV(sbidh));
12594 +}
12595 +
12596 +void *
12597 +sb_osh(sb_t *sbh)
12598 +{
12599 + sb_info_t *si;
12600 +
12601 + si = SB_INFO(sbh);
12602 + return si->osh;
12603 +}
12604 +
12605 +void
12606 +sb_setosh(sb_t *sbh, osl_t *osh)
12607 +{
12608 + sb_info_t *si;
12609 +
12610 + si = SB_INFO(sbh);
12611 + if (si->osh != NULL) {
12612 + SB_ERROR(("osh is already set....\n"));
12613 + ASSERT(!si->osh);
12614 + }
12615 + si->osh = osh;
12616 +}
12617 +
12618 +/* set/clear sbtmstatelow core-specific flags */
12619 +uint32
12620 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
12621 +{
12622 + sb_info_t *si;
12623 + sbconfig_t *sb;
12624 + uint32 w;
12625 +
12626 + si = SB_INFO(sbh);
12627 + sb = REGS2SB(si->curmap);
12628 +
12629 + ASSERT((val & ~mask) == 0);
12630 +
12631 + /* mask and set */
12632 + if (mask || val) {
12633 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
12634 + W_SBREG(si, &sb->sbtmstatelow, w);
12635 + }
12636 +
12637 + /* return the new value */
12638 + return (R_SBREG(si, &sb->sbtmstatelow));
12639 +}
12640 +
12641 +/* set/clear sbtmstatehigh core-specific flags */
12642 +uint32
12643 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
12644 +{
12645 + sb_info_t *si;
12646 + sbconfig_t *sb;
12647 + uint32 w;
12648 +
12649 + si = SB_INFO(sbh);
12650 + sb = REGS2SB(si->curmap);
12651 +
12652 + ASSERT((val & ~mask) == 0);
12653 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
12654 +
12655 + /* mask and set */
12656 + if (mask || val) {
12657 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
12658 + W_SBREG(si, &sb->sbtmstatehigh, w);
12659 + }
12660 +
12661 + /* return the new value */
12662 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
12663 +}
12664 +
12665 +/* Run bist on current core. Caller needs to take care of core-specific bist hazards */
12666 +int
12667 +sb_corebist(sb_t *sbh)
12668 +{
12669 + uint32 sblo;
12670 + sb_info_t *si;
12671 + sbconfig_t *sb;
12672 + int result = 0;
12673 +
12674 + si = SB_INFO(sbh);
12675 + sb = REGS2SB(si->curmap);
12676 +
12677 + sblo = R_SBREG(si, &sb->sbtmstatelow);
12678 + W_SBREG(si, &sb->sbtmstatelow, (sblo | SBTML_FGC | SBTML_BE));
12679 +
12680 + SPINWAIT(((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTD) == 0), 100000);
12681 +
12682 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTF)
12683 + result = BCME_ERROR;
12684 +
12685 + W_SBREG(si, &sb->sbtmstatelow, sblo);
12686 +
12687 + return result;
12688 +}
12689 +
12690 +bool
12691 +sb_iscoreup(sb_t *sbh)
12692 +{
12693 + sb_info_t *si;
12694 + sbconfig_t *sb;
12695 +
12696 + si = SB_INFO(sbh);
12697 + sb = REGS2SB(si->curmap);
12698 +
12699 + return ((R_SBREG(si, &sb->sbtmstatelow) &
12700 + (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
12701 +}
12702 +
12703 +/*
12704 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
12705 + * switch back to the original core, and return the new value.
12706 + *
12707 + * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
12708 + *
12709 + * Also, when using pci/pcie, we can optimize away the core switching for pci registers
12710 + * and (on newer pci cores) chipcommon registers.
12711 + */
12712 +static uint
12713 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
12714 +{
12715 + uint origidx = 0;
12716 + uint32 *r = NULL;
12717 + uint w;
12718 + uint intr_val = 0;
12719 + bool fast = FALSE;
12720 +
12721 + ASSERT(GOODIDX(coreidx));
12722 + ASSERT(regoff < SB_CORE_SIZE);
12723 + ASSERT((val & ~mask) == 0);
12724 +
12725 +#ifdef notyet
12726 + if (si->sb.bustype == SB_BUS) {
12727 + /* If internal bus, we can always get at everything */
12728 + fast = TRUE;
12729 + r = (uint32 *)((uchar *)si->regs[coreidx] + regoff);
12730 + } else if (si->sb.bustype == PCI_BUS) {
12731 + /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
12732 +
12733 + if ((si->coreid[coreidx] == SB_CC) &&
12734 + ((si->sb.buscoretype == SB_PCIE) ||
12735 + (si->sb.buscorerev >= 13))) {
12736 + /* Chipc registers are mapped at 12KB */
12737 +
12738 + fast = TRUE;
12739 + r = (uint32 *)((char *)si->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
12740 + } else if (si->sb.buscoreidx == coreidx) {
12741 + /* pci registers are at either in the last 2KB of an 8KB window
12742 + * or, in pcie and pci rev 13 at 8KB
12743 + */
12744 + fast = TRUE;
12745 + if ((si->sb.buscoretype == SB_PCIE) ||
12746 + (si->sb.buscorerev >= 13))
12747 + r = (uint32 *)((char *)si->curmap +
12748 + PCI_16KB0_PCIREGS_OFFSET + regoff);
12749 + else
12750 + r = (uint32 *)((char *)si->curmap +
12751 + ((regoff >= SBCONFIGOFF) ?
12752 + PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
12753 + regoff);
12754 + }
12755 + }
12756 +#endif /* notyet */
12757 +
12758 + if (!fast) {
12759 + INTR_OFF(si, intr_val);
12760 +
12761 + /* save current core index */
12762 + origidx = sb_coreidx(&si->sb);
12763 +
12764 + /* switch core */
12765 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
12766 + }
12767 + ASSERT(r);
12768 +
12769 + /* mask and set */
12770 + if (mask || val) {
12771 + if (regoff >= SBCONFIGOFF) {
12772 + w = (R_SBREG(si, r) & ~mask) | val;
12773 + W_SBREG(si, r, w);
12774 + } else {
12775 + w = (R_REG(si->osh, r) & ~mask) | val;
12776 + W_REG(si->osh, r, w);
12777 + }
12778 + }
12779 +
12780 + /* readback */
12781 + if (regoff >= SBCONFIGOFF)
12782 + w = R_SBREG(si, r);
12783 + else
12784 + w = R_REG(si->osh, r);
12785 +
12786 + if (!fast) {
12787 + /* restore core index */
12788 + if (origidx != coreidx)
12789 + sb_setcoreidx(&si->sb, origidx);
12790 +
12791 + INTR_RESTORE(si, intr_val);
12792 + }
12793 +
12794 + return (w);
12795 +}
12796 +
12797 +#define DWORD_ALIGN(x) (x & ~(0x03))
12798 +#define BYTE_POS(x) (x & 0x3)
12799 +#define WORD_POS(x) (x & 0x1)
12800 +
12801 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
12802 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
12803 +
12804 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
12805 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
12806 +
12807 +#define read_pci_cfg_byte(a) \
12808 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
12809 +
12810 +#define read_pci_cfg_write(a) \
12811 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
12812 +
12813 +
12814 +/* return TRUE if requested capability exists in the PCI config space */
12815 +static bool
12816 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
12817 +{
12818 + uint8 cap_id;
12819 + uint8 cap_ptr;
12820 + uint32 bufsize;
12821 + uint8 byte_val;
12822 +
12823 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
12824 + return FALSE;
12825 +
12826 + /* check for Header type 0 */
12827 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
12828 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
12829 + return FALSE;
12830 +
12831 + /* check if the capability pointer field exists */
12832 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
12833 + if (!(byte_val & PCI_CAPPTR_PRESENT))
12834 + return FALSE;
12835 +
12836 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
12837 + /* check if the capability pointer is 0x00 */
12838 + if (cap_ptr == 0x00)
12839 + return FALSE;
12840 +
12841 +
12842 + /* loop thr'u the capability list and see if the pcie capabilty exists */
12843 +
12844 + cap_id = read_pci_cfg_byte(cap_ptr);
12845 +
12846 + while (cap_id != req_cap_id) {
12847 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
12848 + if (cap_ptr == 0x00) break;
12849 + cap_id = read_pci_cfg_byte(cap_ptr);
12850 + }
12851 + if (cap_id != req_cap_id) {
12852 + return FALSE;
12853 + }
12854 + /* found the caller requested capability */
12855 + if ((buf != NULL) && (buflen != NULL)) {
12856 + bufsize = *buflen;
12857 + if (!bufsize) goto end;
12858 + *buflen = 0;
12859 + /* copy the cpability data excluding cap ID and next ptr */
12860 + cap_ptr += 2;
12861 + if ((bufsize + cap_ptr) > SZPCR)
12862 + bufsize = SZPCR - cap_ptr;
12863 + *buflen = bufsize;
12864 + while (bufsize--) {
12865 + *buf = read_pci_cfg_byte(cap_ptr);
12866 + cap_ptr++;
12867 + buf++;
12868 + }
12869 + }
12870 +end:
12871 + return TRUE;
12872 +}
12873 +
12874 +/* return TRUE if PCIE capability exists the pci config space */
12875 +static inline bool
12876 +sb_ispcie(sb_info_t *si)
12877 +{
12878 + return (sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
12879 +}
12880 +
12881 +/* scan the sb enumerated space to identify all cores */
12882 +static void
12883 +BCMINITFN(sb_scan)(sb_info_t *si)
12884 +{
12885 + uint origidx;
12886 + uint i;
12887 + bool pci;
12888 + bool pcie;
12889 + uint pciidx;
12890 + uint pcieidx;
12891 + uint pcirev;
12892 + uint pcierev;
12893 +
12894 +
12895 + /* numcores should already be set */
12896 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
12897 +
12898 + /* save current core index */
12899 + origidx = sb_coreidx(&si->sb);
12900 +
12901 + si->sb.buscorerev = NOREV;
12902 + si->sb.buscoreidx = BADIDX;
12903 +
12904 + si->gpioidx = BADIDX;
12905 +
12906 + pci = pcie = FALSE;
12907 + pcirev = pcierev = NOREV;
12908 + pciidx = pcieidx = BADIDX;
12909 +
12910 + for (i = 0; i < si->numcores; i++) {
12911 + sb_setcoreidx(&si->sb, i);
12912 + si->coreid[i] = sb_coreid(&si->sb);
12913 +
12914 + if (si->coreid[i] == SB_PCI) {
12915 + pciidx = i;
12916 + pcirev = sb_corerev(&si->sb);
12917 + pci = TRUE;
12918 + } else if (si->coreid[i] == SB_PCIE) {
12919 + pcieidx = i;
12920 + pcierev = sb_corerev(&si->sb);
12921 + pcie = TRUE;
12922 + } else if (si->coreid[i] == SB_PCMCIA) {
12923 + si->sb.buscorerev = sb_corerev(&si->sb);
12924 + si->sb.buscoretype = si->coreid[i];
12925 + si->sb.buscoreidx = i;
12926 + }
12927 + }
12928 + if (pci && pcie) {
12929 + if (sb_ispcie(si))
12930 + pci = FALSE;
12931 + else
12932 + pcie = FALSE;
12933 + }
12934 + if (pci) {
12935 + si->sb.buscoretype = SB_PCI;
12936 + si->sb.buscorerev = pcirev;
12937 + si->sb.buscoreidx = pciidx;
12938 + } else if (pcie) {
12939 + si->sb.buscoretype = SB_PCIE;
12940 + si->sb.buscorerev = pcierev;
12941 + si->sb.buscoreidx = pcieidx;
12942 + }
12943 +
12944 + /*
12945 + * Find the gpio "controlling core" type and index.
12946 + * Precedence:
12947 + * - if there's a chip common core - use that
12948 + * - else if there's a pci core (rev >= 2) - use that
12949 + * - else there had better be an extif core (4710 only)
12950 + */
12951 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
12952 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
12953 + si->gpioid = SB_CC;
12954 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
12955 + si->gpioidx = si->sb.buscoreidx;
12956 + si->gpioid = SB_PCI;
12957 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
12958 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
12959 + si->gpioid = SB_EXTIF;
12960 + } else
12961 + ASSERT(si->gpioidx != BADIDX);
12962 +
12963 + /* return to original core index */
12964 + sb_setcoreidx(&si->sb, origidx);
12965 +}
12966 +
12967 +/* may be called with core in reset */
12968 +void
12969 +sb_detach(sb_t *sbh)
12970 +{
12971 + sb_info_t *si;
12972 + uint idx;
12973 +
12974 + si = SB_INFO(sbh);
12975 +
12976 + if (si == NULL)
12977 + return;
12978 +
12979 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12980 + for (idx = 0; idx < SB_MAXCORES; idx++)
12981 + if (si->regs[idx]) {
12982 + REG_UNMAP(si->regs[idx]);
12983 + si->regs[idx] = NULL;
12984 + }
12985 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12986 + if (si != &ksi)
12987 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12988 + MFREE(si->osh, si, sizeof(sb_info_t));
12989 +
12990 +}
12991 +
12992 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
12993 +static uint
12994 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
12995 +{
12996 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
12997 + return (BCM4710_CHIP_ID);
12998 + if ((pcidev >= BCM4402_ENET_ID) && (pcidev <= BCM4402_V90_ID))
12999 + return (BCM4402_CHIP_ID);
13000 + if (pcidev == BCM4401_ENET_ID)
13001 + return (BCM4402_CHIP_ID);
13002 +
13003 + return (0);
13004 +}
13005 +
13006 +/* convert chip number to number of i/o cores */
13007 +static uint
13008 +BCMINITFN(sb_chip2numcores)(uint chip)
13009 +{
13010 + if (chip == BCM4710_CHIP_ID)
13011 + return (9);
13012 + if (chip == BCM4402_CHIP_ID)
13013 + return (3);
13014 + if (chip == BCM4306_CHIP_ID) /* < 4306c0 */
13015 + return (6);
13016 + if (chip == BCM4704_CHIP_ID)
13017 + return (9);
13018 + if (chip == BCM5365_CHIP_ID)
13019 + return (7);
13020 +
13021 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
13022 + ASSERT(0);
13023 + return (1);
13024 +}
13025 +
13026 +/* return index of coreid or BADIDX if not found */
13027 +static uint
13028 +sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit)
13029 +{
13030 + uint found;
13031 + uint i;
13032 +
13033 + found = 0;
13034 +
13035 + for (i = 0; i < si->numcores; i++)
13036 + if (si->coreid[i] == coreid) {
13037 + if (found == coreunit)
13038 + return (i);
13039 + found++;
13040 + }
13041 +
13042 + return (BADIDX);
13043 +}
13044 +
13045 +/*
13046 + * this function changes logical "focus" to the indiciated core,
13047 + * must be called with interrupt off.
13048 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13049 + */
13050 +void*
13051 +sb_setcoreidx(sb_t *sbh, uint coreidx)
13052 +{
13053 + sb_info_t *si;
13054 + uint32 sbaddr;
13055 + uint8 tmp;
13056 +
13057 + si = SB_INFO(sbh);
13058 +
13059 + if (coreidx >= si->numcores)
13060 + return (NULL);
13061 +
13062 + /*
13063 + * If the user has provided an interrupt mask enabled function,
13064 + * then assert interrupts are disabled before switching the core.
13065 + */
13066 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
13067 +
13068 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
13069 +
13070 + switch (BUSTYPE(si->sb.bustype)) {
13071 + case SB_BUS:
13072 + /* map new one */
13073 + if (!si->regs[coreidx]) {
13074 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
13075 + ASSERT(GOODREGS(si->regs[coreidx]));
13076 + }
13077 + si->curmap = si->regs[coreidx];
13078 + break;
13079 +
13080 + case PCI_BUS:
13081 + /* point bar0 window */
13082 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
13083 + break;
13084 +
13085 + case PCMCIA_BUS:
13086 + tmp = (sbaddr >> 12) & 0x0f;
13087 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13088 + tmp = (sbaddr >> 16) & 0xff;
13089 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13090 + tmp = (sbaddr >> 24) & 0xff;
13091 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13092 + break;
13093 +#ifdef BCMJTAG
13094 + case JTAG_BUS:
13095 + /* map new one */
13096 + if (!si->regs[coreidx]) {
13097 + si->regs[coreidx] = (void *)sbaddr;
13098 + ASSERT(GOODREGS(si->regs[coreidx]));
13099 + }
13100 + si->curmap = si->regs[coreidx];
13101 + break;
13102 +#endif /* BCMJTAG */
13103 + }
13104 +
13105 + si->curidx = coreidx;
13106 +
13107 + return (si->curmap);
13108 +}
13109 +
13110 +/*
13111 + * this function changes logical "focus" to the indiciated core,
13112 + * must be called with interrupt off.
13113 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13114 + */
13115 +void*
13116 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
13117 +{
13118 + sb_info_t *si;
13119 + uint idx;
13120 +
13121 + si = SB_INFO(sbh);
13122 + idx = sb_findcoreidx(si, coreid, coreunit);
13123 + if (!GOODIDX(idx))
13124 + return (NULL);
13125 +
13126 + return (sb_setcoreidx(sbh, idx));
13127 +}
13128 +
13129 +/* return chip number */
13130 +uint
13131 +sb_chip(sb_t *sbh)
13132 +{
13133 + sb_info_t *si;
13134 +
13135 + si = SB_INFO(sbh);
13136 + return (si->sb.chip);
13137 +}
13138 +
13139 +/* return chip revision number */
13140 +uint
13141 +sb_chiprev(sb_t *sbh)
13142 +{
13143 + sb_info_t *si;
13144 +
13145 + si = SB_INFO(sbh);
13146 + return (si->sb.chiprev);
13147 +}
13148 +
13149 +/* return chip common revision number */
13150 +uint
13151 +sb_chipcrev(sb_t *sbh)
13152 +{
13153 + sb_info_t *si;
13154 +
13155 + si = SB_INFO(sbh);
13156 + return (si->sb.ccrev);
13157 +}
13158 +
13159 +/* return chip package option */
13160 +uint
13161 +sb_chippkg(sb_t *sbh)
13162 +{
13163 + sb_info_t *si;
13164 +
13165 + si = SB_INFO(sbh);
13166 + return (si->sb.chippkg);
13167 +}
13168 +
13169 +/* return PCI core rev. */
13170 +uint
13171 +sb_pcirev(sb_t *sbh)
13172 +{
13173 + sb_info_t *si;
13174 +
13175 + si = SB_INFO(sbh);
13176 + return (si->sb.buscorerev);
13177 +}
13178 +
13179 +bool
13180 +BCMINITFN(sb_war16165)(sb_t *sbh)
13181 +{
13182 + sb_info_t *si;
13183 +
13184 + si = SB_INFO(sbh);
13185 +
13186 + return (PCI(si) && (si->sb.buscorerev <= 10));
13187 +}
13188 +
13189 +static void
13190 +BCMINITFN(sb_war30841)(sb_info_t *si)
13191 +{
13192 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
13193 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
13194 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
13195 +}
13196 +
13197 +/* return PCMCIA core rev. */
13198 +uint
13199 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
13200 +{
13201 + sb_info_t *si;
13202 +
13203 + si = SB_INFO(sbh);
13204 + return (si->sb.buscorerev);
13205 +}
13206 +
13207 +/* return board vendor id */
13208 +uint
13209 +sb_boardvendor(sb_t *sbh)
13210 +{
13211 + sb_info_t *si;
13212 +
13213 + si = SB_INFO(sbh);
13214 + return (si->sb.boardvendor);
13215 +}
13216 +
13217 +/* return boardtype */
13218 +uint
13219 +sb_boardtype(sb_t *sbh)
13220 +{
13221 + sb_info_t *si;
13222 + char *var;
13223 +
13224 + si = SB_INFO(sbh);
13225 +
13226 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
13227 + /* boardtype format is a hex string */
13228 + si->sb.boardtype = getintvar(NULL, "boardtype");
13229 +
13230 + /* backward compatibility for older boardtype string format */
13231 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
13232 + if (!strcmp(var, "bcm94710dev"))
13233 + si->sb.boardtype = BCM94710D_BOARD;
13234 + else if (!strcmp(var, "bcm94710ap"))
13235 + si->sb.boardtype = BCM94710AP_BOARD;
13236 + else if (!strcmp(var, "bu4710"))
13237 + si->sb.boardtype = BU4710_BOARD;
13238 + else if (!strcmp(var, "bcm94702mn"))
13239 + si->sb.boardtype = BCM94702MN_BOARD;
13240 + else if (!strcmp(var, "bcm94710r1"))
13241 + si->sb.boardtype = BCM94710R1_BOARD;
13242 + else if (!strcmp(var, "bcm94710r4"))
13243 + si->sb.boardtype = BCM94710R4_BOARD;
13244 + else if (!strcmp(var, "bcm94702cpci"))
13245 + si->sb.boardtype = BCM94702CPCI_BOARD;
13246 + else if (!strcmp(var, "bcm95380_rr"))
13247 + si->sb.boardtype = BCM95380RR_BOARD;
13248 + }
13249 + }
13250 +
13251 + return (si->sb.boardtype);
13252 +}
13253 +
13254 +/* return bus type of sbh device */
13255 +uint
13256 +sb_bus(sb_t *sbh)
13257 +{
13258 + sb_info_t *si;
13259 +
13260 + si = SB_INFO(sbh);
13261 + return (si->sb.bustype);
13262 +}
13263 +
13264 +/* return bus core type */
13265 +uint
13266 +sb_buscoretype(sb_t *sbh)
13267 +{
13268 + sb_info_t *si;
13269 +
13270 + si = SB_INFO(sbh);
13271 +
13272 + return (si->sb.buscoretype);
13273 +}
13274 +
13275 +/* return bus core revision */
13276 +uint
13277 +sb_buscorerev(sb_t *sbh)
13278 +{
13279 + sb_info_t *si;
13280 + si = SB_INFO(sbh);
13281 +
13282 + return (si->sb.buscorerev);
13283 +}
13284 +
13285 +/* return list of found cores */
13286 +uint
13287 +sb_corelist(sb_t *sbh, uint coreid[])
13288 +{
13289 + sb_info_t *si;
13290 +
13291 + si = SB_INFO(sbh);
13292 +
13293 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof(uint)));
13294 + return (si->numcores);
13295 +}
13296 +
13297 +/* return current register mapping */
13298 +void *
13299 +sb_coreregs(sb_t *sbh)
13300 +{
13301 + sb_info_t *si;
13302 +
13303 + si = SB_INFO(sbh);
13304 + ASSERT(GOODREGS(si->curmap));
13305 +
13306 + return (si->curmap);
13307 +}
13308 +
13309 +
13310 +/* do buffered registers update */
13311 +void
13312 +sb_commit(sb_t *sbh)
13313 +{
13314 + sb_info_t *si;
13315 + uint origidx;
13316 + uint intr_val = 0;
13317 +
13318 + si = SB_INFO(sbh);
13319 +
13320 + origidx = si->curidx;
13321 + ASSERT(GOODIDX(origidx));
13322 +
13323 + INTR_OFF(si, intr_val);
13324 +
13325 + /* switch over to chipcommon core if there is one, else use pci */
13326 + if (si->sb.ccrev != NOREV) {
13327 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
13328 +
13329 + /* do the buffer registers update */
13330 + W_REG(si->osh, &ccregs->broadcastaddress, SB_COMMIT);
13331 + W_REG(si->osh, &ccregs->broadcastdata, 0x0);
13332 + } else if (PCI(si)) {
13333 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
13334 +
13335 + /* do the buffer registers update */
13336 + W_REG(si->osh, &pciregs->bcastaddr, SB_COMMIT);
13337 + W_REG(si->osh, &pciregs->bcastdata, 0x0);
13338 + } else
13339 + ASSERT(0);
13340 +
13341 + /* restore core index */
13342 + sb_setcoreidx(sbh, origidx);
13343 + INTR_RESTORE(si, intr_val);
13344 +}
13345 +
13346 +/* reset and re-enable a core
13347 + * inputs:
13348 + * bits - core specific bits that are set during and after reset sequence
13349 + * resetbits - core specific bits that are set only during reset sequence
13350 + */
13351 +void
13352 +sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits)
13353 +{
13354 + sb_info_t *si;
13355 + sbconfig_t *sb;
13356 + volatile uint32 dummy;
13357 +
13358 + si = SB_INFO(sbh);
13359 + ASSERT(GOODREGS(si->curmap));
13360 + sb = REGS2SB(si->curmap);
13361 +
13362 + /*
13363 + * Must do the disable sequence first to work for arbitrary current core state.
13364 + */
13365 + sb_core_disable(sbh, (bits | resetbits));
13366 +
13367 + /*
13368 + * Now do the initialization sequence.
13369 + */
13370 +
13371 + /* set reset while enabling the clock and forcing them on throughout the core */
13372 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits | resetbits));
13373 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13374 + OSL_DELAY(1);
13375 +
13376 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
13377 + W_SBREG(si, &sb->sbtmstatehigh, 0);
13378 + }
13379 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
13380 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
13381 + }
13382 +
13383 + /* clear reset and allow it to propagate throughout the core */
13384 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
13385 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13386 + OSL_DELAY(1);
13387 +
13388 + /* leave clock enabled */
13389 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
13390 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13391 + OSL_DELAY(1);
13392 +}
13393 +
13394 +void
13395 +sb_core_tofixup(sb_t *sbh)
13396 +{
13397 + sb_info_t *si;
13398 + sbconfig_t *sb;
13399 +
13400 + si = SB_INFO(sbh);
13401 +
13402 + if ((BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) ||
13403 + (PCI(si) && (si->sb.buscorerev >= 5)))
13404 + return;
13405 +
13406 + ASSERT(GOODREGS(si->curmap));
13407 + sb = REGS2SB(si->curmap);
13408 +
13409 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
13410 + SET_SBREG(si, &sb->sbimconfiglow,
13411 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13412 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
13413 + } else {
13414 + if (sb_coreid(sbh) == SB_PCI) {
13415 + SET_SBREG(si, &sb->sbimconfiglow,
13416 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13417 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13418 + } else {
13419 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
13420 + }
13421 + }
13422 +
13423 + sb_commit(sbh);
13424 +}
13425 +
13426 +/*
13427 + * Set the initiator timeout for the "master core".
13428 + * The master core is defined to be the core in control
13429 + * of the chip and so it issues accesses to non-memory
13430 + * locations (Because of dma *any* core can access memeory).
13431 + *
13432 + * The routine uses the bus to decide who is the master:
13433 + * SB_BUS => mips
13434 + * JTAG_BUS => chipc
13435 + * PCI_BUS => pci or pcie
13436 + * PCMCIA_BUS => pcmcia
13437 + * SDIO_BUS => pcmcia
13438 + *
13439 + * This routine exists so callers can disable initiator
13440 + * timeouts so accesses to very slow devices like otp
13441 + * won't cause an abort. The routine allows arbitrary
13442 + * settings of the service and request timeouts, though.
13443 + *
13444 + * Returns the timeout state before changing it or -1
13445 + * on error.
13446 + */
13447 +
13448 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
13449 +
13450 +uint32
13451 +sb_set_initiator_to(sb_t *sbh, uint32 to)
13452 +{
13453 + sb_info_t *si;
13454 + uint origidx, idx;
13455 + uint intr_val = 0;
13456 + uint32 tmp, ret = 0xffffffff;
13457 + sbconfig_t *sb;
13458 +
13459 + si = SB_INFO(sbh);
13460 +
13461 + if ((to & ~TO_MASK) != 0)
13462 + return ret;
13463 +
13464 + /* Figure out the master core */
13465 + idx = BADIDX;
13466 + switch (BUSTYPE(si->sb.bustype)) {
13467 + case PCI_BUS:
13468 + idx = si->sb.buscoreidx;
13469 + break;
13470 + case JTAG_BUS:
13471 + idx = SB_CC_IDX;
13472 + break;
13473 + case PCMCIA_BUS:
13474 + case SDIO_BUS:
13475 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
13476 + break;
13477 + case SB_BUS:
13478 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
13479 + idx = sb_findcoreidx(si, SB_MIPS, 0);
13480 + break;
13481 + default:
13482 + ASSERT(0);
13483 + }
13484 + if (idx == BADIDX)
13485 + return ret;
13486 +
13487 + INTR_OFF(si, intr_val);
13488 + origidx = sb_coreidx(sbh);
13489 +
13490 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
13491 +
13492 + tmp = R_SBREG(si, &sb->sbimconfiglow);
13493 + ret = tmp & TO_MASK;
13494 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
13495 +
13496 + sb_commit(sbh);
13497 + sb_setcoreidx(sbh, origidx);
13498 + INTR_RESTORE(si, intr_val);
13499 + return ret;
13500 +}
13501 +
13502 +void
13503 +sb_core_disable(sb_t *sbh, uint32 bits)
13504 +{
13505 + sb_info_t *si;
13506 + volatile uint32 dummy;
13507 + uint32 rej;
13508 + sbconfig_t *sb;
13509 +
13510 + si = SB_INFO(sbh);
13511 +
13512 + ASSERT(GOODREGS(si->curmap));
13513 + sb = REGS2SB(si->curmap);
13514 +
13515 + /* if core is already in reset, just return */
13516 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
13517 + return;
13518 +
13519 + /* reject value changed between sonics 2.2 and 2.3 */
13520 + if (si->sb.sonicsrev == SONICS_2_2)
13521 + rej = (1 << SBTML_REJ_SHIFT);
13522 + else
13523 + rej = (2 << SBTML_REJ_SHIFT);
13524 +
13525 + /* if clocks are not enabled, put into reset and return */
13526 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
13527 + goto disable;
13528 +
13529 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
13530 + OR_SBREG(si, &sb->sbtmstatelow, rej);
13531 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13532 + OSL_DELAY(1);
13533 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
13534 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY)
13535 + SB_ERROR(("%s: target state still busy\n", __FUNCTION__));
13536 +
13537 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
13538 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
13539 + dummy = R_SBREG(si, &sb->sbimstate);
13540 + OSL_DELAY(1);
13541 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
13542 + }
13543 +
13544 + /* set reset and reject while enabling the clocks */
13545 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
13546 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13547 + OSL_DELAY(10);
13548 +
13549 + /* don't forget to clear the initiator reject bit */
13550 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
13551 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
13552 +
13553 +disable:
13554 + /* leave reset and reject asserted */
13555 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
13556 + OSL_DELAY(1);
13557 +}
13558 +
13559 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
13560 +void
13561 +sb_watchdog(sb_t *sbh, uint ticks)
13562 +{
13563 + sb_info_t *si = SB_INFO(sbh);
13564 +
13565 + /* make sure we come up in fast clock mode */
13566 + sb_clkctl_clk(sbh, CLK_FAST);
13567 +
13568 + /* instant NMI */
13569 + switch (si->gpioid) {
13570 + case SB_CC:
13571 +#ifdef __mips__
13572 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1)
13573 + MTC0(C0_BROADCOM, 4, (1 << 22));
13574 +#endif /* __mips__ */
13575 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
13576 +#ifdef __mips__
13577 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1) {
13578 + __asm__ __volatile__ (
13579 + ".set\tmips3\n\t"
13580 + "sync\n\t"
13581 + "wait\n\t"
13582 + ".set\tmips0"
13583 + );
13584 + while (1);
13585 + }
13586 +#endif /* __mips__ */
13587 + break;
13588 + case SB_EXTIF:
13589 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
13590 + break;
13591 + }
13592 +}
13593 +
13594 +/* initialize the pcmcia core */
13595 +void
13596 +sb_pcmcia_init(sb_t *sbh)
13597 +{
13598 + sb_info_t *si;
13599 + uint8 cor = 0;
13600 +
13601 + si = SB_INFO(sbh);
13602 +
13603 + /* enable d11 mac interrupts */
13604 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13605 + cor |= COR_IRQEN | COR_FUNEN;
13606 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13607 +
13608 +}
13609 +
13610 +
13611 +/*
13612 + * Configure the pci core for pci client (NIC) action
13613 + * coremask is the bitvec of cores by index to be enabled.
13614 + */
13615 +void
13616 +BCMINITFN(sb_pci_setup)(sb_t *sbh, uint coremask)
13617 +{
13618 + sb_info_t *si;
13619 + sbconfig_t *sb;
13620 + sbpciregs_t *pciregs;
13621 + uint32 sbflag;
13622 + uint32 w;
13623 + uint idx;
13624 + int reg_val;
13625 +
13626 + si = SB_INFO(sbh);
13627 +
13628 + /* if not pci bus, we're done */
13629 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
13630 + return;
13631 +
13632 + ASSERT(PCI(si) || PCIE(si));
13633 + ASSERT(si->sb.buscoreidx != BADIDX);
13634 +
13635 + /* get current core index */
13636 + idx = si->curidx;
13637 +
13638 + /* we interrupt on this backplane flag number */
13639 + ASSERT(GOODREGS(si->curmap));
13640 + sb = REGS2SB(si->curmap);
13641 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
13642 +
13643 + /* switch over to pci core */
13644 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
13645 + sb = REGS2SB(pciregs);
13646 +
13647 + /*
13648 + * Enable sb->pci interrupts. Assume
13649 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
13650 + */
13651 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
13652 + /* pci config write to set this core bit in PCIIntMask */
13653 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
13654 + w |= (coremask << PCI_SBIM_SHIFT);
13655 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
13656 + } else {
13657 + /* set sbintvec bit for our flag number */
13658 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
13659 + }
13660 +
13661 + if (PCI(si)) {
13662 + OR_REG(si->osh, &pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
13663 + if (si->sb.buscorerev >= 11)
13664 + OR_REG(si->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
13665 + if (si->sb.buscorerev < 5) {
13666 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13667 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13668 + sb_commit(sbh);
13669 + }
13670 + }
13671 +
13672 +#ifdef PCIE_SUPPOER
13673 + /* PCIE workarounds */
13674 + if (PCIE(si)) {
13675 + if ((si->sb.buscorerev == 0) || (si->sb.buscorerev == 1)) {
13676 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13677 + PCIE_TLP_WORKAROUNDSREG);
13678 + reg_val |= 0x8;
13679 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS,
13680 + PCIE_TLP_WORKAROUNDSREG, reg_val);
13681 + }
13682 +
13683 + if (si->sb.buscorerev == 1) {
13684 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13685 + PCIE_DLLP_LCREG);
13686 + reg_val |= (0x40);
13687 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
13688 + }
13689 +
13690 + if (si->sb.buscorerev == 0)
13691 + sb_war30841(si);
13692 + }
13693 +#endif
13694 +
13695 + /* switch back to previous core */
13696 + sb_setcoreidx(sbh, idx);
13697 +}
13698 +
13699 +uint32
13700 +sb_base(uint32 admatch)
13701 +{
13702 + uint32 base;
13703 + uint type;
13704 +
13705 + type = admatch & SBAM_TYPE_MASK;
13706 + ASSERT(type < 3);
13707 +
13708 + base = 0;
13709 +
13710 + if (type == 0) {
13711 + base = admatch & SBAM_BASE0_MASK;
13712 + } else if (type == 1) {
13713 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13714 + base = admatch & SBAM_BASE1_MASK;
13715 + } else if (type == 2) {
13716 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13717 + base = admatch & SBAM_BASE2_MASK;
13718 + }
13719 +
13720 + return (base);
13721 +}
13722 +
13723 +uint32
13724 +sb_size(uint32 admatch)
13725 +{
13726 + uint32 size;
13727 + uint type;
13728 +
13729 + type = admatch & SBAM_TYPE_MASK;
13730 + ASSERT(type < 3);
13731 +
13732 + size = 0;
13733 +
13734 + if (type == 0) {
13735 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
13736 + } else if (type == 1) {
13737 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13738 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
13739 + } else if (type == 2) {
13740 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13741 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
13742 + }
13743 +
13744 + return (size);
13745 +}
13746 +
13747 +/* return the core-type instantiation # of the current core */
13748 +uint
13749 +sb_coreunit(sb_t *sbh)
13750 +{
13751 + sb_info_t *si;
13752 + uint idx;
13753 + uint coreid;
13754 + uint coreunit;
13755 + uint i;
13756 +
13757 + si = SB_INFO(sbh);
13758 + coreunit = 0;
13759 +
13760 + idx = si->curidx;
13761 +
13762 + ASSERT(GOODREGS(si->curmap));
13763 + coreid = sb_coreid(sbh);
13764 +
13765 + /* count the cores of our type */
13766 + for (i = 0; i < idx; i++)
13767 + if (si->coreid[i] == coreid)
13768 + coreunit++;
13769 +
13770 + return (coreunit);
13771 +}
13772 +
13773 +static INLINE uint32
13774 +factor6(uint32 x)
13775 +{
13776 + switch (x) {
13777 + case CC_F6_2: return 2;
13778 + case CC_F6_3: return 3;
13779 + case CC_F6_4: return 4;
13780 + case CC_F6_5: return 5;
13781 + case CC_F6_6: return 6;
13782 + case CC_F6_7: return 7;
13783 + default: return 0;
13784 + }
13785 +}
13786 +
13787 +/* calculate the speed the SB would run at given a set of clockcontrol values */
13788 +uint32
13789 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
13790 +{
13791 + uint32 n1, n2, clock, m1, m2, m3, mc;
13792 +
13793 + n1 = n & CN_N1_MASK;
13794 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
13795 +
13796 + if (pll_type == PLL_TYPE6) {
13797 + if (m & CC_T6_MMASK)
13798 + return CC_T6_M1;
13799 + else
13800 + return CC_T6_M0;
13801 + } else if ((pll_type == PLL_TYPE1) ||
13802 + (pll_type == PLL_TYPE3) ||
13803 + (pll_type == PLL_TYPE4) ||
13804 + (pll_type == PLL_TYPE7)) {
13805 + n1 = factor6(n1);
13806 + n2 += CC_F5_BIAS;
13807 + } else if (pll_type == PLL_TYPE2) {
13808 + n1 += CC_T2_BIAS;
13809 + n2 += CC_T2_BIAS;
13810 + ASSERT((n1 >= 2) && (n1 <= 7));
13811 + ASSERT((n2 >= 5) && (n2 <= 23));
13812 + } else if (pll_type == PLL_TYPE5) {
13813 + return (100000000);
13814 + } else
13815 + ASSERT(0);
13816 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
13817 + if ((pll_type == PLL_TYPE3) ||
13818 + (pll_type == PLL_TYPE7)) {
13819 + clock = CC_CLOCK_BASE2 * n1 * n2;
13820 + } else
13821 + clock = CC_CLOCK_BASE1 * n1 * n2;
13822 +
13823 + if (clock == 0)
13824 + return 0;
13825 +
13826 + m1 = m & CC_M1_MASK;
13827 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
13828 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
13829 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
13830 +
13831 + if ((pll_type == PLL_TYPE1) ||
13832 + (pll_type == PLL_TYPE3) ||
13833 + (pll_type == PLL_TYPE4) ||
13834 + (pll_type == PLL_TYPE7)) {
13835 + m1 = factor6(m1);
13836 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
13837 + m2 += CC_F5_BIAS;
13838 + else
13839 + m2 = factor6(m2);
13840 + m3 = factor6(m3);
13841 +
13842 + switch (mc) {
13843 + case CC_MC_BYPASS: return (clock);
13844 + case CC_MC_M1: return (clock / m1);
13845 + case CC_MC_M1M2: return (clock / (m1 * m2));
13846 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
13847 + case CC_MC_M1M3: return (clock / (m1 * m3));
13848 + default: return (0);
13849 + }
13850 + } else {
13851 + ASSERT(pll_type == PLL_TYPE2);
13852 +
13853 + m1 += CC_T2_BIAS;
13854 + m2 += CC_T2M2_BIAS;
13855 + m3 += CC_T2_BIAS;
13856 + ASSERT((m1 >= 2) && (m1 <= 7));
13857 + ASSERT((m2 >= 3) && (m2 <= 10));
13858 + ASSERT((m3 >= 2) && (m3 <= 7));
13859 +
13860 + if ((mc & CC_T2MC_M1BYP) == 0)
13861 + clock /= m1;
13862 + if ((mc & CC_T2MC_M2BYP) == 0)
13863 + clock /= m2;
13864 + if ((mc & CC_T2MC_M3BYP) == 0)
13865 + clock /= m3;
13866 +
13867 + return (clock);
13868 + }
13869 +}
13870 +
13871 +/* returns the current speed the SB is running at */
13872 +uint32
13873 +sb_clock(sb_t *sbh)
13874 +{
13875 + sb_info_t *si;
13876 + extifregs_t *eir;
13877 + chipcregs_t *cc;
13878 + uint32 n, m;
13879 + uint idx;
13880 + uint32 pll_type, rate;
13881 + uint intr_val = 0;
13882 +
13883 + si = SB_INFO(sbh);
13884 + idx = si->curidx;
13885 + pll_type = PLL_TYPE1;
13886 +
13887 + INTR_OFF(si, intr_val);
13888 +
13889 + /* switch to extif or chipc core */
13890 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
13891 + n = R_REG(si->osh, &eir->clockcontrol_n);
13892 + m = R_REG(si->osh, &eir->clockcontrol_sb);
13893 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
13894 + pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
13895 + if (pll_type == PLL_NONE) {
13896 + INTR_RESTORE(si, intr_val);
13897 + return 80000000;
13898 + }
13899 + n = R_REG(si->osh, &cc->clockcontrol_n);
13900 + if (pll_type == PLL_TYPE6)
13901 + m = R_REG(si->osh, &cc->clockcontrol_m3);
13902 + else if ((pll_type == PLL_TYPE3) && !(BCMINIT(sb_chip)(sbh) == 0x5365))
13903 + m = R_REG(si->osh, &cc->clockcontrol_m2);
13904 + else
13905 + m = R_REG(si->osh, &cc->clockcontrol_sb);
13906 + } else {
13907 + INTR_RESTORE(si, intr_val);
13908 + return 0;
13909 + }
13910 +
13911 + /* calculate rate */
13912 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
13913 + rate = 100000000;
13914 + else {
13915 + rate = sb_clock_rate(pll_type, n, m);
13916 +
13917 + if (pll_type == PLL_TYPE3)
13918 + rate = rate / 2;
13919 + }
13920 +
13921 + /* switch back to previous core */
13922 + sb_setcoreidx(sbh, idx);
13923 +
13924 + INTR_RESTORE(si, intr_val);
13925 +
13926 + return rate;
13927 +}
13928 +
13929 +/* change logical "focus" to the gpio core for optimized access */
13930 +void*
13931 +sb_gpiosetcore(sb_t *sbh)
13932 +{
13933 + sb_info_t *si;
13934 +
13935 + si = SB_INFO(sbh);
13936 +
13937 + return (sb_setcoreidx(sbh, si->gpioidx));
13938 +}
13939 +
13940 +/* mask&set gpiocontrol bits */
13941 +uint32
13942 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13943 +{
13944 + sb_info_t *si;
13945 + uint regoff;
13946 +
13947 + si = SB_INFO(sbh);
13948 + regoff = 0;
13949 +
13950 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13951 +
13952 + /* gpios could be shared on router platforms */
13953 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13954 + mask = priority ? (sb_gpioreservation & mask) :
13955 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13956 + val &= mask;
13957 + }
13958 +
13959 + switch (si->gpioid) {
13960 + case SB_CC:
13961 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
13962 + break;
13963 +
13964 + case SB_PCI:
13965 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
13966 + break;
13967 +
13968 + case SB_EXTIF:
13969 + return (0);
13970 + }
13971 +
13972 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13973 +}
13974 +
13975 +/* mask&set gpio output enable bits */
13976 +uint32
13977 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13978 +{
13979 + sb_info_t *si;
13980 + uint regoff;
13981 +
13982 + si = SB_INFO(sbh);
13983 + regoff = 0;
13984 +
13985 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13986 +
13987 + /* gpios could be shared on router platforms */
13988 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13989 + mask = priority ? (sb_gpioreservation & mask) :
13990 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13991 + val &= mask;
13992 + }
13993 +
13994 + switch (si->gpioid) {
13995 + case SB_CC:
13996 + regoff = OFFSETOF(chipcregs_t, gpioouten);
13997 + break;
13998 +
13999 + case SB_PCI:
14000 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
14001 + break;
14002 +
14003 + case SB_EXTIF:
14004 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
14005 + break;
14006 + }
14007 +
14008 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14009 +}
14010 +
14011 +/* mask&set gpio output bits */
14012 +uint32
14013 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14014 +{
14015 + sb_info_t *si;
14016 + uint regoff;
14017 +
14018 + si = SB_INFO(sbh);
14019 + regoff = 0;
14020 +
14021 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14022 +
14023 + /* gpios could be shared on router platforms */
14024 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14025 + mask = priority ? (sb_gpioreservation & mask) :
14026 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14027 + val &= mask;
14028 + }
14029 +
14030 + switch (si->gpioid) {
14031 + case SB_CC:
14032 + regoff = OFFSETOF(chipcregs_t, gpioout);
14033 + break;
14034 +
14035 + case SB_PCI:
14036 + regoff = OFFSETOF(sbpciregs_t, gpioout);
14037 + break;
14038 +
14039 + case SB_EXTIF:
14040 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
14041 + break;
14042 + }
14043 +
14044 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14045 +}
14046 +
14047 +/* reserve one gpio */
14048 +uint32
14049 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14050 +{
14051 + sb_info_t *si;
14052 +
14053 + si = SB_INFO(sbh);
14054 +
14055 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14056 +
14057 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14058 + * reserve/release GPIO
14059 + */
14060 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14061 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14062 + return -1;
14063 + }
14064 + /* make sure only one bit is set */
14065 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14066 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14067 + return -1;
14068 + }
14069 +
14070 + /* already reserved */
14071 + if (sb_gpioreservation & gpio_bitmask)
14072 + return -1;
14073 + /* set reservation */
14074 + sb_gpioreservation |= gpio_bitmask;
14075 +
14076 + return sb_gpioreservation;
14077 +}
14078 +
14079 +/* release one gpio */
14080 +/*
14081 + * releasing the gpio doesn't change the current value on the GPIO last write value
14082 + * persists till some one overwrites it
14083 +*/
14084 +
14085 +uint32
14086 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14087 +{
14088 + sb_info_t *si;
14089 +
14090 + si = SB_INFO(sbh);
14091 +
14092 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14093 +
14094 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14095 + * reserve/release GPIO
14096 + */
14097 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14098 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14099 + return -1;
14100 + }
14101 + /* make sure only one bit is set */
14102 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14103 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14104 + return -1;
14105 + }
14106 +
14107 + /* already released */
14108 + if (!(sb_gpioreservation & gpio_bitmask))
14109 + return -1;
14110 +
14111 + /* clear reservation */
14112 + sb_gpioreservation &= ~gpio_bitmask;
14113 +
14114 + return sb_gpioreservation;
14115 +}
14116 +
14117 +/* return the current gpioin register value */
14118 +uint32
14119 +sb_gpioin(sb_t *sbh)
14120 +{
14121 + sb_info_t *si;
14122 + uint regoff;
14123 +
14124 + si = SB_INFO(sbh);
14125 + regoff = 0;
14126 +
14127 + switch (si->gpioid) {
14128 + case SB_CC:
14129 + regoff = OFFSETOF(chipcregs_t, gpioin);
14130 + break;
14131 +
14132 + case SB_PCI:
14133 + regoff = OFFSETOF(sbpciregs_t, gpioin);
14134 + break;
14135 +
14136 + case SB_EXTIF:
14137 + regoff = OFFSETOF(extifregs_t, gpioin);
14138 + break;
14139 + }
14140 +
14141 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
14142 +}
14143 +
14144 +/* mask&set gpio interrupt polarity bits */
14145 +uint32
14146 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14147 +{
14148 + sb_info_t *si;
14149 + uint regoff;
14150 +
14151 + si = SB_INFO(sbh);
14152 + regoff = 0;
14153 +
14154 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14155 +
14156 + /* gpios could be shared on router platforms */
14157 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14158 + mask = priority ? (sb_gpioreservation & mask) :
14159 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14160 + val &= mask;
14161 + }
14162 +
14163 + switch (si->gpioid) {
14164 + case SB_CC:
14165 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
14166 + break;
14167 +
14168 + case SB_PCI:
14169 + /* pci gpio implementation does not support interrupt polarity */
14170 + ASSERT(0);
14171 + break;
14172 +
14173 + case SB_EXTIF:
14174 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
14175 + break;
14176 + }
14177 +
14178 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14179 +}
14180 +
14181 +/* mask&set gpio interrupt mask bits */
14182 +uint32
14183 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14184 +{
14185 + sb_info_t *si;
14186 + uint regoff;
14187 +
14188 + si = SB_INFO(sbh);
14189 + regoff = 0;
14190 +
14191 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14192 +
14193 + /* gpios could be shared on router platforms */
14194 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14195 + mask = priority ? (sb_gpioreservation & mask) :
14196 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14197 + val &= mask;
14198 + }
14199 +
14200 + switch (si->gpioid) {
14201 + case SB_CC:
14202 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
14203 + break;
14204 +
14205 + case SB_PCI:
14206 + /* pci gpio implementation does not support interrupt mask */
14207 + ASSERT(0);
14208 + break;
14209 +
14210 + case SB_EXTIF:
14211 + regoff = OFFSETOF(extifregs_t, gpiointmask);
14212 + break;
14213 + }
14214 +
14215 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14216 +}
14217 +
14218 +/* assign the gpio to an led */
14219 +uint32
14220 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
14221 +{
14222 + sb_info_t *si;
14223 +
14224 + si = SB_INFO(sbh);
14225 + if (si->sb.ccrev < 16)
14226 + return -1;
14227 +
14228 + /* gpio led powersave reg */
14229 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
14230 +}
14231 +
14232 +/* mask & set gpio timer val */
14233 +uint32
14234 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
14235 +{
14236 + sb_info_t *si;
14237 + si = SB_INFO(sbh);
14238 +
14239 + if (si->sb.ccrev < 16)
14240 + return -1;
14241 +
14242 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
14243 +}
14244 +
14245 +
14246 +/* return the slow clock source - LPO, XTAL, or PCI */
14247 +static uint
14248 +sb_slowclk_src(sb_info_t *si)
14249 +{
14250 + chipcregs_t *cc;
14251 +
14252 +
14253 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14254 +
14255 + if (si->sb.ccrev < 6) {
14256 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS) &&
14257 + (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)) &
14258 + PCI_CFG_GPIO_SCS))
14259 + return (SCC_SS_PCI);
14260 + else
14261 + return (SCC_SS_XTAL);
14262 + } else if (si->sb.ccrev < 10) {
14263 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14264 + return (R_REG(si->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
14265 + } else /* Insta-clock */
14266 + return (SCC_SS_XTAL);
14267 +}
14268 +
14269 +/* return the ILP (slowclock) min or max frequency */
14270 +static uint
14271 +sb_slowclk_freq(sb_info_t *si, bool max)
14272 +{
14273 + chipcregs_t *cc;
14274 + uint32 slowclk;
14275 + uint div;
14276 +
14277 +
14278 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14279 +
14280 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14281 +
14282 + /* shouldn't be here unless we've established the chip has dynamic clk control */
14283 + ASSERT(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL);
14284 +
14285 + slowclk = sb_slowclk_src(si);
14286 + if (si->sb.ccrev < 6) {
14287 + if (slowclk == SCC_SS_PCI)
14288 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
14289 + else
14290 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
14291 + } else if (si->sb.ccrev < 10) {
14292 + div = 4 * (((R_REG(si->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
14293 + if (slowclk == SCC_SS_LPO)
14294 + return (max? LPOMAXFREQ : LPOMINFREQ);
14295 + else if (slowclk == SCC_SS_XTAL)
14296 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
14297 + else if (slowclk == SCC_SS_PCI)
14298 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
14299 + else
14300 + ASSERT(0);
14301 + } else {
14302 + /* Chipc rev 10 is InstaClock */
14303 + div = R_REG(si->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
14304 + div = 4 * (div + 1);
14305 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
14306 + }
14307 + return (0);
14308 +}
14309 +
14310 +static void
14311 +BCMINITFN(sb_clkctl_setdelay)(sb_info_t *si, void *chipcregs)
14312 +{
14313 + chipcregs_t * cc;
14314 + uint slowmaxfreq, pll_delay, slowclk;
14315 + uint pll_on_delay, fref_sel_delay;
14316 +
14317 + pll_delay = PLL_DELAY;
14318 +
14319 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
14320 + * since the xtal will also be powered down by dynamic clk control logic.
14321 + */
14322 +
14323 + slowclk = sb_slowclk_src(si);
14324 + if (slowclk != SCC_SS_XTAL)
14325 + pll_delay += XTAL_ON_DELAY;
14326 +
14327 + /* Starting with 4318 it is ILP that is used for the delays */
14328 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
14329 +
14330 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
14331 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
14332 +
14333 + cc = (chipcregs_t *)chipcregs;
14334 + W_REG(si->osh, &cc->pll_on_delay, pll_on_delay);
14335 + W_REG(si->osh, &cc->fref_sel_delay, fref_sel_delay);
14336 +}
14337 +
14338 +/* initialize power control delay registers */
14339 +void
14340 +BCMINITFN(sb_clkctl_init)(sb_t *sbh)
14341 +{
14342 + sb_info_t *si;
14343 + uint origidx;
14344 + chipcregs_t *cc;
14345 +
14346 + si = SB_INFO(sbh);
14347 +
14348 + origidx = si->curidx;
14349 +
14350 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14351 + return;
14352 +
14353 + if ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev < 2))
14354 + W_REG(si->osh, &cc->chipcontrol,
14355 + (si->sb.chiprev == 0) ? CHIPCTRL_4321A0_DEFAULT : CHIPCTRL_4321A1_DEFAULT);
14356 +
14357 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14358 + goto done;
14359 +
14360 + /* set all Instaclk chip ILP to 1 MHz */
14361 + else if (si->sb.ccrev >= 10)
14362 + SET_REG(si->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
14363 + (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
14364 +
14365 + sb_clkctl_setdelay(si, (void *)cc);
14366 +
14367 +done:
14368 + sb_setcoreidx(sbh, origidx);
14369 +}
14370 +
14371 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
14372 +uint16
14373 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
14374 +{
14375 + sb_info_t *si;
14376 + uint origidx;
14377 + chipcregs_t *cc;
14378 + uint slowminfreq;
14379 + uint16 fpdelay;
14380 + uint intr_val = 0;
14381 +
14382 + si = SB_INFO(sbh);
14383 + fpdelay = 0;
14384 + origidx = si->curidx;
14385 +
14386 + INTR_OFF(si, intr_val);
14387 +
14388 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14389 + goto done;
14390 +
14391 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14392 + goto done;
14393 +
14394 + slowminfreq = sb_slowclk_freq(si, FALSE);
14395 + fpdelay = (((R_REG(si->osh, &cc->pll_on_delay) + 2) * 1000000) +
14396 + (slowminfreq - 1)) / slowminfreq;
14397 +
14398 +done:
14399 + sb_setcoreidx(sbh, origidx);
14400 + INTR_RESTORE(si, intr_val);
14401 + return (fpdelay);
14402 +}
14403 +
14404 +/* turn primary xtal and/or pll off/on */
14405 +int
14406 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
14407 +{
14408 + sb_info_t *si;
14409 + uint32 in, out, outen;
14410 +
14411 + si = SB_INFO(sbh);
14412 +
14413 + switch (BUSTYPE(si->sb.bustype)) {
14414 +
14415 +
14416 + case PCMCIA_BUS:
14417 + return (0);
14418 +
14419 +
14420 + case PCI_BUS:
14421 +
14422 + /* pcie core doesn't have any mapping to control the xtal pu */
14423 + if (PCIE(si))
14424 + return -1;
14425 +
14426 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof(uint32));
14427 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32));
14428 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32));
14429 +
14430 + /*
14431 + * Avoid glitching the clock if GPRS is already using it.
14432 + * We can't actually read the state of the PLLPD so we infer it
14433 + * by the value of XTAL_PU which *is* readable via gpioin.
14434 + */
14435 + if (on && (in & PCI_CFG_GPIO_XTAL))
14436 + return (0);
14437 +
14438 + if (what & XTAL)
14439 + outen |= PCI_CFG_GPIO_XTAL;
14440 + if (what & PLL)
14441 + outen |= PCI_CFG_GPIO_PLL;
14442 +
14443 + if (on) {
14444 + /* turn primary xtal on */
14445 + if (what & XTAL) {
14446 + out |= PCI_CFG_GPIO_XTAL;
14447 + if (what & PLL)
14448 + out |= PCI_CFG_GPIO_PLL;
14449 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14450 + sizeof(uint32), out);
14451 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN,
14452 + sizeof(uint32), outen);
14453 + OSL_DELAY(XTAL_ON_DELAY);
14454 + }
14455 +
14456 + /* turn pll on */
14457 + if (what & PLL) {
14458 + out &= ~PCI_CFG_GPIO_PLL;
14459 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14460 + sizeof(uint32), out);
14461 + OSL_DELAY(2000);
14462 + }
14463 + } else {
14464 + if (what & XTAL)
14465 + out &= ~PCI_CFG_GPIO_XTAL;
14466 + if (what & PLL)
14467 + out |= PCI_CFG_GPIO_PLL;
14468 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32), out);
14469 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32),
14470 + outen);
14471 + }
14472 +
14473 + default:
14474 + return (-1);
14475 + }
14476 +
14477 + return (0);
14478 +}
14479 +
14480 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
14481 +/* returns true if we are forcing fast clock */
14482 +bool
14483 +sb_clkctl_clk(sb_t *sbh, uint mode)
14484 +{
14485 + sb_info_t *si;
14486 + uint origidx;
14487 + chipcregs_t *cc;
14488 + uint32 scc;
14489 + uint intr_val = 0;
14490 +
14491 + si = SB_INFO(sbh);
14492 +
14493 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
14494 + if (si->sb.ccrev < 6)
14495 + return (FALSE);
14496 +
14497 +
14498 + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
14499 + ASSERT(si->sb.ccrev != 10);
14500 +
14501 + INTR_OFF(si, intr_val);
14502 +
14503 + origidx = si->curidx;
14504 +
14505 + if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) &&
14506 + (BUSTYPE(si->sb.bustype) == SB_BUS) && (si->sb.ccrev >= 10))
14507 + goto done;
14508 +
14509 + /* PR32414WAR "Force HT clock on" all the time, no dynamic clk ctl */
14510 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1))
14511 + goto done;
14512 +
14513 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
14514 + ASSERT(cc != NULL);
14515 +
14516 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14517 + goto done;
14518 +
14519 + switch (mode) {
14520 + case CLK_FAST: /* force fast (pll) clock */
14521 + if (si->sb.ccrev < 10) {
14522 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
14523 + sb_clkctl_xtal(&si->sb, XTAL, ON);
14524 +
14525 + SET_REG(si->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
14526 + } else
14527 + OR_REG(si->osh, &cc->system_clk_ctl, SYCC_HR);
14528 + /* wait for the PLL */
14529 + OSL_DELAY(PLL_DELAY);
14530 + break;
14531 +
14532 + case CLK_DYNAMIC: /* enable dynamic clock control */
14533 +
14534 + if (si->sb.ccrev < 10) {
14535 + scc = R_REG(si->osh, &cc->slow_clk_ctl);
14536 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
14537 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
14538 + scc |= SCC_XC;
14539 + W_REG(si->osh, &cc->slow_clk_ctl, scc);
14540 +
14541 + /* for dynamic control, we have to release our xtal_pu "force on" */
14542 + if (scc & SCC_XC)
14543 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
14544 + } else {
14545 + /* Instaclock */
14546 + AND_REG(si->osh, &cc->system_clk_ctl, ~SYCC_HR);
14547 + }
14548 + break;
14549 +
14550 + default:
14551 + ASSERT(0);
14552 + }
14553 +
14554 +done:
14555 + sb_setcoreidx(sbh, origidx);
14556 + INTR_RESTORE(si, intr_val);
14557 + return (mode == CLK_FAST);
14558 +}
14559 +
14560 +/* register driver interrupt disabling and restoring callback functions */
14561 +void
14562 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
14563 + void *intrsenabled_fn, void *intr_arg)
14564 +{
14565 + sb_info_t *si;
14566 +
14567 + si = SB_INFO(sbh);
14568 + si->intr_arg = intr_arg;
14569 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
14570 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
14571 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
14572 + /* save current core id. when this function called, the current core
14573 + * must be the core which provides driver functions(il, et, wl, etc.)
14574 + */
14575 + si->dev_coreid = si->coreid[si->curidx];
14576 +}
14577 +
14578 +
14579 +int
14580 +sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
14581 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
14582 + uint8 *pciheader)
14583 +{
14584 + uint16 vendor = 0xffff, device = 0xffff;
14585 + uint core, unit;
14586 + uint chip, chippkg;
14587 + uint nfunc;
14588 + char varname[SB_DEVPATH_BUFSZ + 8];
14589 + uint8 class, subclass, progif;
14590 + char devpath[SB_DEVPATH_BUFSZ];
14591 + uint8 header;
14592 +
14593 + core = sb_coreid(sbh);
14594 + unit = sb_coreunit(sbh);
14595 +
14596 + chip = sb_chip(sbh);
14597 + chippkg = sb_chippkg(sbh);
14598 +
14599 + progif = 0;
14600 + header = PCI_HEADER_NORMAL;
14601 +
14602 + /* Verify whether the function exists for the core */
14603 + nfunc = (core == SB_USB20H) ? 2 : 1;
14604 + if (func >= nfunc)
14605 + return BCME_ERROR;
14606 +
14607 + /* Known vendor translations */
14608 + switch (sb_corevendor(sbh)) {
14609 + case SB_VEND_BCM:
14610 + vendor = VENDOR_BROADCOM;
14611 + break;
14612 + default:
14613 + return BCME_ERROR;
14614 + }
14615 +
14616 + /* Determine class based on known core codes */
14617 + switch (core) {
14618 + case SB_ILINE20:
14619 + class = PCI_CLASS_NET;
14620 + subclass = PCI_NET_ETHER;
14621 + device = BCM47XX_ILINE_ID;
14622 + break;
14623 + case SB_ENET:
14624 + class = PCI_CLASS_NET;
14625 + subclass = PCI_NET_ETHER;
14626 + device = BCM47XX_ENET_ID;
14627 + break;
14628 + case SB_GIGETH:
14629 + class = PCI_CLASS_NET;
14630 + subclass = PCI_NET_ETHER;
14631 + device = BCM47XX_GIGETH_ID;
14632 + break;
14633 + case SB_SDRAM:
14634 + case SB_MEMC:
14635 + class = PCI_CLASS_MEMORY;
14636 + subclass = PCI_MEMORY_RAM;
14637 + device = (uint16)core;
14638 + break;
14639 + case SB_PCI:
14640 + case SB_PCIE:
14641 + class = PCI_CLASS_BRIDGE;
14642 + subclass = PCI_BRIDGE_PCI;
14643 + device = (uint16)core;
14644 + header = PCI_HEADER_BRIDGE;
14645 + break;
14646 + case SB_MIPS:
14647 + case SB_MIPS33:
14648 + class = PCI_CLASS_CPU;
14649 + subclass = PCI_CPU_MIPS;
14650 + device = (uint16)core;
14651 + break;
14652 + case SB_CODEC:
14653 + class = PCI_CLASS_COMM;
14654 + subclass = PCI_COMM_MODEM;
14655 + device = BCM47XX_V90_ID;
14656 + break;
14657 + case SB_USB:
14658 + class = PCI_CLASS_SERIAL;
14659 + subclass = PCI_SERIAL_USB;
14660 + progif = 0x10; /* OHCI */
14661 + device = BCM47XX_USB_ID;
14662 + break;
14663 + case SB_USB11H:
14664 + class = PCI_CLASS_SERIAL;
14665 + subclass = PCI_SERIAL_USB;
14666 + progif = 0x10; /* OHCI */
14667 + device = BCM47XX_USBH_ID;
14668 + break;
14669 + case SB_USB20H:
14670 + class = PCI_CLASS_SERIAL;
14671 + subclass = PCI_SERIAL_USB;
14672 + progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI */
14673 + device = BCM47XX_USB20H_ID;
14674 + header = 0x80; /* multifunction */
14675 + break;
14676 + case SB_USB11D:
14677 + class = PCI_CLASS_SERIAL;
14678 + subclass = PCI_SERIAL_USB;
14679 + device = BCM47XX_USBD_ID;
14680 + break;
14681 + case SB_USB20D:
14682 + class = PCI_CLASS_SERIAL;
14683 + subclass = PCI_SERIAL_USB;
14684 + device = BCM47XX_USB20D_ID;
14685 + break;
14686 + case SB_IPSEC:
14687 + class = PCI_CLASS_CRYPT;
14688 + subclass = PCI_CRYPT_NETWORK;
14689 + device = BCM47XX_IPSEC_ID;
14690 + break;
14691 + case SB_ROBO:
14692 + class = PCI_CLASS_NET;
14693 + subclass = PCI_NET_OTHER;
14694 + device = BCM47XX_ROBO_ID;
14695 + break;
14696 + case SB_EXTIF:
14697 + case SB_CC:
14698 + class = PCI_CLASS_MEMORY;
14699 + subclass = PCI_MEMORY_FLASH;
14700 + device = (uint16)core;
14701 + break;
14702 + case SB_D11:
14703 + class = PCI_CLASS_NET;
14704 + subclass = PCI_NET_OTHER;
14705 + /* Let nvram variable override core ID */
14706 + sb_devpath(sbh, devpath, sizeof(devpath));
14707 + sprintf(varname, "%sdevid", devpath);
14708 + if ((device = (uint16)getintvar(NULL, varname)))
14709 + break;
14710 + /*
14711 + * no longer support wl%did, but keep the code
14712 + * here for backward compatibility.
14713 + */
14714 + sprintf(varname, "wl%did", unit);
14715 + if ((device = (uint16)getintvar(NULL, varname)))
14716 + break;
14717 + /* Chip specific conversion */
14718 + if (chip == BCM4712_CHIP_ID) {
14719 + if (chippkg == BCM4712SMALL_PKG_ID)
14720 + device = BCM4306_D11G_ID;
14721 + else
14722 + device = BCM4306_D11DUAL_ID;
14723 + break;
14724 + }
14725 + /* ignore it */
14726 + device = 0xffff;
14727 + break;
14728 + case SB_SATAXOR:
14729 + class = PCI_CLASS_XOR;
14730 + subclass = PCI_XOR_QDMA;
14731 + device = BCM47XX_SATAXOR_ID;
14732 + break;
14733 + case SB_ATA100:
14734 + class = PCI_CLASS_DASDI;
14735 + subclass = PCI_DASDI_IDE;
14736 + device = BCM47XX_ATA100_ID;
14737 + break;
14738 +
14739 + default:
14740 + class = subclass = progif = 0xff;
14741 + device = (uint16)core;
14742 + break;
14743 + }
14744 +
14745 + *pcivendor = vendor;
14746 + *pcidevice = device;
14747 + *pciclass = class;
14748 + *pcisubclass = subclass;
14749 + *pciprogif = progif;
14750 + *pciheader = header;
14751 +
14752 + return 0;
14753 +}
14754 +
14755 +
14756 +
14757 +/* use the mdio interface to write to mdio slaves */
14758 +static int
14759 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
14760 +{
14761 + uint mdiodata;
14762 + uint i = 0;
14763 + sbpcieregs_t *pcieregs;
14764 +
14765 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
14766 + ASSERT(pcieregs);
14767 +
14768 + /* enable mdio access to SERDES */
14769 + W_REG(si->osh, (&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
14770 +
14771 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
14772 + (physmedia << MDIODATA_DEVADDR_SHF) |
14773 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
14774 +
14775 + W_REG(si->osh, (&pcieregs->mdiodata), mdiodata);
14776 +
14777 + PR28829_DELAY();
14778 +
14779 + /* retry till the transaction is complete */
14780 + while (i < 10) {
14781 + if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
14782 + /* Disable mdio access to SERDES */
14783 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14784 + return 0;
14785 + }
14786 + OSL_DELAY(1000);
14787 + i++;
14788 + }
14789 +
14790 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
14791 + /* Disable mdio access to SERDES */
14792 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14793 + ASSERT(0);
14794 + return 1;
14795 +
14796 +}
14797 +
14798 +/* indirect way to read pcie config regs */
14799 +uint
14800 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
14801 +{
14802 + sb_info_t *si;
14803 + sb_t *sbh;
14804 + uint retval = 0xFFFFFFFF;
14805 + sbpcieregs_t *pcieregs;
14806 + uint addrtype;
14807 +
14808 + sbh = (sb_t *)sb;
14809 + si = SB_INFO(sbh);
14810 + ASSERT(PCIE(si));
14811 +
14812 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14813 + ASSERT(pcieregs);
14814 +
14815 + addrtype = (uint)((uintptr)arg1);
14816 + switch (addrtype) {
14817 + case PCIE_CONFIGREGS:
14818 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14819 + retval = R_REG(si->osh, &(pcieregs->configdata));
14820 + break;
14821 + case PCIE_PCIEREGS:
14822 + W_REG(si->osh, &(pcieregs->pcieaddr), offset);
14823 + retval = R_REG(si->osh, &(pcieregs->pciedata));
14824 + break;
14825 + default:
14826 + ASSERT(0);
14827 + break;
14828 + }
14829 + return retval;
14830 +}
14831 +
14832 +/* indirect way to write pcie config/mdio/pciecore regs */
14833 +uint
14834 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
14835 +{
14836 + sb_info_t *si;
14837 + sbpcieregs_t *pcieregs;
14838 + uint addrtype;
14839 +
14840 + si = SB_INFO(sbh);
14841 + ASSERT(PCIE(si));
14842 +
14843 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14844 + ASSERT(pcieregs);
14845 +
14846 + addrtype = (uint)((uintptr)arg1);
14847 +
14848 + switch (addrtype) {
14849 + case PCIE_CONFIGREGS:
14850 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14851 + W_REG(si->osh, (&pcieregs->configdata), val);
14852 + break;
14853 + case PCIE_PCIEREGS:
14854 + W_REG(si->osh, (&pcieregs->pcieaddr), offset);
14855 + W_REG(si->osh, (&pcieregs->pciedata), val);
14856 + break;
14857 + default:
14858 + ASSERT(0);
14859 + break;
14860 + }
14861 + return 0;
14862 +}
14863 +
14864 +/* Build device path. Support SB, PCI, and JTAG for now. */
14865 +int
14866 +sb_devpath(sb_t *sbh, char *path, int size)
14867 +{
14868 + ASSERT(path);
14869 + ASSERT(size >= SB_DEVPATH_BUFSZ);
14870 +
14871 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
14872 + case SB_BUS:
14873 + case JTAG_BUS:
14874 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
14875 + break;
14876 + case PCI_BUS:
14877 + ASSERT((SB_INFO(sbh))->osh);
14878 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
14879 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
14880 + break;
14881 + case PCMCIA_BUS:
14882 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
14883 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
14884 + sprintf(path, "pc/%u/%u/", 1, 1);
14885 + break;
14886 + case SDIO_BUS:
14887 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
14888 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
14889 + break;
14890 + default:
14891 + ASSERT(0);
14892 + break;
14893 + }
14894 +
14895 + return 0;
14896 +}
14897 +
14898 +/*
14899 + * Fixup SROMless PCI device's configuration.
14900 + * The current core may be changed upon return.
14901 + */
14902 +static int
14903 +sb_pci_fixcfg(sb_info_t *si)
14904 +{
14905 + uint origidx, pciidx;
14906 + sbpciregs_t *pciregs;
14907 + sbpcieregs_t *pcieregs;
14908 + uint16 val16, *reg16;
14909 + char name[SB_DEVPATH_BUFSZ+16], *value;
14910 + char devpath[SB_DEVPATH_BUFSZ];
14911 +
14912 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
14913 +
14914 + /* Fixup PI in SROM shadow area to enable the correct PCI core access */
14915 + /* save the current index */
14916 + origidx = sb_coreidx(&si->sb);
14917 +
14918 + /* check 'pi' is correct and fix it if not */
14919 + if (si->sb.buscoretype == SB_PCIE) {
14920 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
14921 + ASSERT(pcieregs);
14922 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
14923 + } else if (si->sb.buscoretype == SB_PCI) {
14924 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
14925 + ASSERT(pciregs);
14926 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
14927 + } else {
14928 + ASSERT(0);
14929 + return -1;
14930 + }
14931 + pciidx = sb_coreidx(&si->sb);
14932 + val16 = R_REG(si->osh, reg16);
14933 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
14934 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
14935 + W_REG(si->osh, reg16, val16);
14936 + }
14937 +
14938 + /* restore the original index */
14939 + sb_setcoreidx(&si->sb, origidx);
14940 +
14941 + /*
14942 + * Fixup bar0window in PCI config space to make the core indicated
14943 + * by the nvram variable the current core.
14944 + * !Do it last, it may change the current core!
14945 + */
14946 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
14947 + return -1;
14948 + sprintf(name, "%sb0w", devpath);
14949 + if ((value = getvar(NULL, name))) {
14950 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
14951 + bcm_strtoul(value, NULL, 16));
14952 + /* update curidx since the current core is changed */
14953 + si->curidx = _sb_coreidx(si);
14954 + if (si->curidx == BADIDX) {
14955 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
14956 + return -1;
14957 + }
14958 + }
14959 +
14960 + return 0;
14961 +}
14962 +
14963 +static uint
14964 +sb_chipc_capability(sb_t *sbh)
14965 +{
14966 + sb_info_t *si;
14967 +
14968 + si = SB_INFO(sbh);
14969 +
14970 + /* Make sure that there is ChipCommon core present */
14971 + if (si->coreid[SB_CC_IDX] == SB_CC)
14972 + return (sb_corereg(si, SB_CC_IDX, OFFSETOF(chipcregs_t, capabilities),
14973 + 0, 0));
14974 + return 0;
14975 +}
14976 +
14977 +/* Return ADDR64 capability of the backplane */
14978 +bool
14979 +sb_backplane64(sb_t *sbh)
14980 +{
14981 + return ((sb_chipc_capability(sbh) & CAP_BKPLN64) != 0);
14982 +}
14983 +
14984 +void
14985 +sb_btcgpiowar(sb_t *sbh)
14986 +{
14987 + sb_info_t *si;
14988 + uint origidx;
14989 + uint intr_val = 0;
14990 + chipcregs_t *cc;
14991 + si = SB_INFO(sbh);
14992 +
14993 + /* Make sure that there is ChipCommon core present &&
14994 + * UART_TX is strapped to 1
14995 + */
14996 + if (!(sb_chipc_capability(sbh) & CAP_UARTGPIO))
14997 + return;
14998 +
14999 + /* sb_corereg cannot be used as we have to guarantee 8-bit read/writes */
15000 + INTR_OFF(si, intr_val);
15001 +
15002 + origidx = sb_coreidx(sbh);
15003 +
15004 + cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
15005 + if (cc == NULL)
15006 + goto end;
15007 +
15008 + W_REG(si->osh, &cc->uart0mcr, R_REG(si->osh, &cc->uart0mcr) | 0x04);
15009 +
15010 +end:
15011 + /* restore the original index */
15012 + sb_setcoreidx(sbh, origidx);
15013 +
15014 + INTR_RESTORE(si, intr_val);
15015 +}
15016 +
15017 +/* check if the device is removed */
15018 +bool
15019 +sb_deviceremoved(sb_t *sbh)
15020 +{
15021 + uint32 w;
15022 + sb_info_t *si;
15023 +
15024 + si = SB_INFO(sbh);
15025 +
15026 + switch (BUSTYPE(si->sb.bustype)) {
15027 + case PCI_BUS:
15028 + ASSERT(si->osh);
15029 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_VID, sizeof(uint32));
15030 + if ((w & 0xFFFF) != VENDOR_BROADCOM)
15031 + return TRUE;
15032 + else
15033 + return FALSE;
15034 + default:
15035 + return FALSE;
15036 + }
15037 + return FALSE;
15038 +}
15039 +
15040 +/* Return the RAM size of the SOCRAM core */
15041 +uint32
15042 +sb_socram_size(sb_t *sbh)
15043 +{
15044 + sb_info_t *si;
15045 + uint origidx;
15046 + uint intr_val = 0;
15047 +
15048 + sbsocramregs_t *regs;
15049 + bool wasup;
15050 + uint corerev;
15051 + uint32 coreinfo;
15052 + uint memsize = 0;
15053 +
15054 + si = SB_INFO(sbh);
15055 + ASSERT(si);
15056 +
15057 + /* Block ints and save current core */
15058 + INTR_OFF(si, intr_val);
15059 + origidx = sb_coreidx(sbh);
15060 +
15061 + /* Switch to SOCRAM core */
15062 + if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0)))
15063 + goto done;
15064 +
15065 + /* Get info for determining size */
15066 + if (!(wasup = sb_iscoreup(sbh)))
15067 + sb_core_reset(sbh, 0, 0);
15068 + corerev = sb_corerev(sbh);
15069 + coreinfo = R_REG(si->osh, &regs->coreinfo);
15070 +
15071 + /* Calculate size from coreinfo based on rev */
15072 + switch (corerev) {
15073 + case 0:
15074 + memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
15075 + break;
15076 + default: /* rev >= 1 */
15077 + memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
15078 + memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
15079 + break;
15080 + }
15081 +
15082 + /* Return to previous state and core */
15083 + if (!wasup)
15084 + sb_core_disable(sbh, 0);
15085 + sb_setcoreidx(sbh, origidx);
15086 +
15087 +done:
15088 + INTR_RESTORE(si, intr_val);
15089 + return memsize;
15090 +}
15091 +
15092 +
15093 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
15094 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
15095 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-04-27 23:22:53.000000000 +0200
15096 @@ -0,0 +1,241 @@
15097 +/*
15098 + * Generic setup routines for Broadcom MIPS boards
15099 + *
15100 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
15101 + *
15102 + * This program is free software; you can redistribute it and/or modify it
15103 + * under the terms of the GNU General Public License as published by the
15104 + * Free Software Foundation; either version 2 of the License, or (at your
15105 + * option) any later version.
15106 + *
15107 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15108 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15109 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15110 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15111 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15112 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15113 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
15114 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15115 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
15116 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15117 + *
15118 + * You should have received a copy of the GNU General Public License along
15119 + * with this program; if not, write to the Free Software Foundation, Inc.,
15120 + * 675 Mass Ave, Cambridge, MA 02139, USA.
15121 + *
15122 + *
15123 + * Copyright 2005, Broadcom Corporation
15124 + * All Rights Reserved.
15125 + *
15126 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15127 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15128 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15129 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15130 + *
15131 + */
15132 +
15133 +#include <linux/config.h>
15134 +#include <linux/init.h>
15135 +#include <linux/kernel.h>
15136 +#include <linux/module.h>
15137 +#include <linux/serialP.h>
15138 +#include <linux/ide.h>
15139 +#include <asm/bootinfo.h>
15140 +#include <asm/cpu.h>
15141 +#include <asm/time.h>
15142 +#include <asm/reboot.h>
15143 +
15144 +#include <typedefs.h>
15145 +#include <osl.h>
15146 +#include <sbutils.h>
15147 +#include <bcmutils.h>
15148 +#include <bcmnvram.h>
15149 +#include <sbhndmips.h>
15150 +#include <hndmips.h>
15151 +#include <trxhdr.h>
15152 +
15153 +/* Virtual IRQ base, after last hw IRQ */
15154 +#define SBMIPS_VIRTIRQ_BASE 6
15155 +
15156 +/* # IRQs, hw and sw IRQs */
15157 +#define SBMIPS_NUMIRQS 8
15158 +
15159 +/* Global SB handle */
15160 +sb_t *bcm947xx_sbh = NULL;
15161 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
15162 +
15163 +/* Convenience */
15164 +#define sbh bcm947xx_sbh
15165 +#define sbh_lock bcm947xx_sbh_lock
15166 +
15167 +extern void bcm947xx_time_init(void);
15168 +extern void bcm947xx_timer_setup(struct irqaction *irq);
15169 +
15170 +#ifdef CONFIG_REMOTE_DEBUG
15171 +extern void set_debug_traps(void);
15172 +extern void rs_kgdb_hook(struct serial_state *);
15173 +extern void breakpoint(void);
15174 +#endif
15175 +
15176 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15177 +extern struct ide_ops std_ide_ops;
15178 +#endif
15179 +
15180 +/* Kernel command line */
15181 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
15182 +extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
15183 +
15184 +void
15185 +bcm947xx_machine_restart(char *command)
15186 +{
15187 + printk("Please stand by while rebooting the system...\n");
15188 +
15189 + /* Set the watchdog timer to reset immediately */
15190 + __cli();
15191 + sb_watchdog(sbh, 1);
15192 + while (1);
15193 +}
15194 +
15195 +void
15196 +bcm947xx_machine_halt(void)
15197 +{
15198 + printk("System halted\n");
15199 +
15200 + /* Disable interrupts and watchdog and spin forever */
15201 + __cli();
15202 + sb_watchdog(sbh, 0);
15203 + while (1);
15204 +}
15205 +
15206 +#ifdef CONFIG_SERIAL
15207 +
15208 +static int ser_line = 0;
15209 +
15210 +typedef struct {
15211 + void *regs;
15212 + uint irq;
15213 + uint baud_base;
15214 + uint reg_shift;
15215 +} serial_port;
15216 +
15217 +static serial_port ports[4];
15218 +static int num_ports = 0;
15219 +
15220 +static void
15221 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
15222 +{
15223 + ports[num_ports].regs = regs;
15224 + ports[num_ports].irq = irq;
15225 + ports[num_ports].baud_base = baud_base;
15226 + ports[num_ports].reg_shift = reg_shift;
15227 + num_ports++;
15228 +}
15229 +
15230 +static void
15231 +do_serial_add(serial_port *port)
15232 +{
15233 + void *regs;
15234 + uint irq;
15235 + uint baud_base;
15236 + uint reg_shift;
15237 + struct serial_struct s;
15238 +
15239 + regs = port->regs;
15240 + irq = port->irq;
15241 + baud_base = port->baud_base;
15242 + reg_shift = port->reg_shift;
15243 +
15244 + memset(&s, 0, sizeof(s));
15245 +
15246 + s.line = ser_line++;
15247 + s.iomem_base = regs;
15248 + s.irq = irq + 2;
15249 + s.baud_base = baud_base / 16;
15250 + s.flags = ASYNC_BOOT_AUTOCONF;
15251 + s.io_type = SERIAL_IO_MEM;
15252 + s.iomem_reg_shift = reg_shift;
15253 +
15254 + if (early_serial_setup(&s) != 0) {
15255 + printk(KERN_ERR "Serial setup failed!\n");
15256 + }
15257 +}
15258 +
15259 +#endif /* CONFIG_SERIAL */
15260 +
15261 +void __init
15262 +brcm_setup(void)
15263 +{
15264 + char *s;
15265 + int i;
15266 + char *value;
15267 +
15268 + /* Get global SB handle */
15269 + sbh = sb_kattach();
15270 +
15271 + /* Initialize clocks and interrupts */
15272 + sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
15273 +
15274 + if (BCM330X(current_cpu_data.processor_id) &&
15275 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
15276 + /*
15277 + * Now that the sbh is inited set the proper PFC value
15278 + */
15279 + printk("Setting the PFC to its default value\n");
15280 + enable_pfc(PFC_AUTO);
15281 + }
15282 +
15283 +
15284 +#ifdef CONFIG_SERIAL
15285 + sb_serial_init(sbh, serial_add);
15286 +
15287 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
15288 + /* Initialize UARTs */
15289 + s = nvram_get("kernel_args");
15290 + if (!s) s = "";
15291 + if (!strncmp(s, "console=ttyS1", 13)) {
15292 + for (i = num_ports; i; i--)
15293 + do_serial_add(&ports[i - 1]);
15294 + } else {
15295 + for (i = 0; i < num_ports; i++)
15296 + do_serial_add(&ports[i]);
15297 + }
15298 +#endif
15299 +
15300 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15301 + ide_ops = &std_ide_ops;
15302 +#endif
15303 +
15304 + /* Override default command line arguments */
15305 + value = nvram_get("kernel_cmdline");
15306 + if (value && strlen(value) && strncmp(value, "empty", 5))
15307 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
15308 +
15309 +
15310 + /* Generic setup */
15311 + _machine_restart = bcm947xx_machine_restart;
15312 + _machine_halt = bcm947xx_machine_halt;
15313 + _machine_power_off = bcm947xx_machine_halt;
15314 +
15315 + board_time_init = bcm947xx_time_init;
15316 + board_timer_setup = bcm947xx_timer_setup;
15317 +}
15318 +
15319 +const char *
15320 +get_system_type(void)
15321 +{
15322 + static char s[32];
15323 +
15324 + if (bcm947xx_sbh) {
15325 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
15326 + sb_chiprev(bcm947xx_sbh));
15327 + return s;
15328 + }
15329 + else
15330 + return "Broadcom BCM947XX";
15331 +}
15332 +
15333 +void __init
15334 +bus_error_init(void)
15335 +{
15336 +}
15337 +
15338 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
15339 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
15340 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2006-04-27 22:11:27.000000000 +0200
15341 @@ -0,0 +1,422 @@
15342 +/*
15343 + * Broadcom SiliconBackplane chipcommon serial flash interface
15344 + *
15345 + * Copyright 2006, Broadcom Corporation
15346 + * All Rights Reserved.
15347 + *
15348 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15349 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15350 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15351 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15352 + *
15353 + * $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
15354 + */
15355 +
15356 +#include <osl.h>
15357 +#include <typedefs.h>
15358 +#include <sbconfig.h>
15359 +#include <sbchipc.h>
15360 +#include <mipsinc.h>
15361 +#include <bcmutils.h>
15362 +#include <bcmdevs.h>
15363 +#include <sflash.h>
15364 +
15365 +/* Private global state */
15366 +static struct sflash sflash;
15367 +
15368 +/* Issue a serial flash command */
15369 +static INLINE void
15370 +sflash_cmd(chipcregs_t *cc, uint opcode)
15371 +{
15372 + W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
15373 + while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
15374 +}
15375 +
15376 +/* Initialize serial flash access */
15377 +struct sflash *
15378 +sflash_init(chipcregs_t *cc)
15379 +{
15380 + uint32 id, id2;
15381 +
15382 + bzero(&sflash, sizeof(sflash));
15383 +
15384 + sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
15385 +
15386 + switch (sflash.type) {
15387 + case SFLASH_ST:
15388 + /* Probe for ST chips */
15389 + sflash_cmd(cc, SFLASH_ST_DP);
15390 + sflash_cmd(cc, SFLASH_ST_RES);
15391 + id = R_REG(NULL, &cc->flashdata);
15392 + switch (id) {
15393 + case 0x11:
15394 + /* ST M25P20 2 Mbit Serial Flash */
15395 + sflash.blocksize = 64 * 1024;
15396 + sflash.numblocks = 4;
15397 + break;
15398 + case 0x12:
15399 + /* ST M25P40 4 Mbit Serial Flash */
15400 + sflash.blocksize = 64 * 1024;
15401 + sflash.numblocks = 8;
15402 + break;
15403 + case 0x13:
15404 + /* ST M25P80 8 Mbit Serial Flash */
15405 + sflash.blocksize = 64 * 1024;
15406 + sflash.numblocks = 16;
15407 + break;
15408 + case 0x14:
15409 + /* ST M25P16 16 Mbit Serial Flash */
15410 + sflash.blocksize = 64 * 1024;
15411 + sflash.numblocks = 32;
15412 + break;
15413 + case 0x15:
15414 + /* ST M25P32 32 Mbit Serial Flash */
15415 + sflash.blocksize = 64 * 1024;
15416 + sflash.numblocks = 64;
15417 + break;
15418 + case 0x16:
15419 + /* ST M25P64 64 Mbit Serial Flash */
15420 + sflash.blocksize = 64 * 1024;
15421 + sflash.numblocks = 128;
15422 + break;
15423 + case 0xbf:
15424 + W_REG(NULL, &cc->flashaddress, 1);
15425 + sflash_cmd(cc, SFLASH_ST_RES);
15426 + id2 = R_REG(NULL, &cc->flashdata);
15427 + if (id2 == 0x44) {
15428 + /* SST M25VF80 4 Mbit Serial Flash */
15429 + sflash.blocksize = 64 * 1024;
15430 + sflash.numblocks = 8;
15431 + }
15432 + break;
15433 + }
15434 + break;
15435 +
15436 + case SFLASH_AT:
15437 + /* Probe for Atmel chips */
15438 + sflash_cmd(cc, SFLASH_AT_STATUS);
15439 + id = R_REG(NULL, &cc->flashdata) & 0x3c;
15440 + switch (id) {
15441 + case 0xc:
15442 + /* Atmel AT45DB011 1Mbit Serial Flash */
15443 + sflash.blocksize = 256;
15444 + sflash.numblocks = 512;
15445 + break;
15446 + case 0x14:
15447 + /* Atmel AT45DB021 2Mbit Serial Flash */
15448 + sflash.blocksize = 256;
15449 + sflash.numblocks = 1024;
15450 + break;
15451 + case 0x1c:
15452 + /* Atmel AT45DB041 4Mbit Serial Flash */
15453 + sflash.blocksize = 256;
15454 + sflash.numblocks = 2048;
15455 + break;
15456 + case 0x24:
15457 + /* Atmel AT45DB081 8Mbit Serial Flash */
15458 + sflash.blocksize = 256;
15459 + sflash.numblocks = 4096;
15460 + break;
15461 + case 0x2c:
15462 + /* Atmel AT45DB161 16Mbit Serial Flash */
15463 + sflash.blocksize = 512;
15464 + sflash.numblocks = 4096;
15465 + break;
15466 + case 0x34:
15467 + /* Atmel AT45DB321 32Mbit Serial Flash */
15468 + sflash.blocksize = 512;
15469 + sflash.numblocks = 8192;
15470 + break;
15471 + case 0x3c:
15472 + /* Atmel AT45DB642 64Mbit Serial Flash */
15473 + sflash.blocksize = 1024;
15474 + sflash.numblocks = 8192;
15475 + break;
15476 + }
15477 + break;
15478 + }
15479 +
15480 + sflash.size = sflash.blocksize * sflash.numblocks;
15481 + return sflash.size ? &sflash : NULL;
15482 +}
15483 +
15484 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
15485 +int
15486 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
15487 +{
15488 + int cnt;
15489 + uint32 *from, *to;
15490 +
15491 + if (!len)
15492 + return 0;
15493 +
15494 + if ((offset + len) > sflash.size)
15495 + return -22;
15496 +
15497 + if ((len >= 4) && (offset & 3))
15498 + cnt = 4 - (offset & 3);
15499 + else if ((len >= 4) && ((uint32)buf & 3))
15500 + cnt = 4 - ((uint32)buf & 3);
15501 + else
15502 + cnt = len;
15503 +
15504 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
15505 + to = (uint32 *)buf;
15506 +
15507 + if (cnt < 4) {
15508 + bcopy(from, to, cnt);
15509 + return cnt;
15510 + }
15511 +
15512 + while (cnt >= 4) {
15513 + *to++ = *from++;
15514 + cnt -= 4;
15515 + }
15516 +
15517 + return (len - cnt);
15518 +}
15519 +
15520 +/* Poll for command completion. Returns zero when complete. */
15521 +int
15522 +sflash_poll(chipcregs_t *cc, uint offset)
15523 +{
15524 + if (offset >= sflash.size)
15525 + return -22;
15526 +
15527 + switch (sflash.type) {
15528 + case SFLASH_ST:
15529 + /* Check for ST Write In Progress bit */
15530 + sflash_cmd(cc, SFLASH_ST_RDSR);
15531 + return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
15532 + case SFLASH_AT:
15533 + /* Check for Atmel Ready bit */
15534 + sflash_cmd(cc, SFLASH_AT_STATUS);
15535 + return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
15536 + }
15537 +
15538 + return 0;
15539 +}
15540 +
15541 +/* Write len bytes starting at offset into buf. Returns number of bytes
15542 + * written. Caller should poll for completion.
15543 + */
15544 +int
15545 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15546 +{
15547 + struct sflash *sfl;
15548 + int ret = 0;
15549 + bool is4712b0;
15550 + uint32 page, byte, mask;
15551 +
15552 + if (!len)
15553 + return 0;
15554 +
15555 + if ((offset + len) > sflash.size)
15556 + return -22;
15557 +
15558 + sfl = &sflash;
15559 + switch (sfl->type) {
15560 + case SFLASH_ST:
15561 + mask = R_REG(NULL, &cc->chipid);
15562 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
15563 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
15564 + /* Enable writes */
15565 + sflash_cmd(cc, SFLASH_ST_WREN);
15566 + if (is4712b0) {
15567 + mask = 1 << 14;
15568 + W_REG(NULL, &cc->flashaddress, offset);
15569 + W_REG(NULL, &cc->flashdata, *buf++);
15570 + /* Set chip select */
15571 + OR_REG(NULL, &cc->gpioout, mask);
15572 + /* Issue a page program with the first byte */
15573 + sflash_cmd(cc, SFLASH_ST_PP);
15574 + ret = 1;
15575 + offset++;
15576 + len--;
15577 + while (len > 0) {
15578 + if ((offset & 255) == 0) {
15579 + /* Page boundary, drop cs and return */
15580 + AND_REG(NULL, &cc->gpioout, ~mask);
15581 + if (!sflash_poll(cc, offset)) {
15582 + /* Flash rejected command */
15583 + return -11;
15584 + }
15585 + return ret;
15586 + } else {
15587 + /* Write single byte */
15588 + sflash_cmd(cc, *buf++);
15589 + }
15590 + ret++;
15591 + offset++;
15592 + len--;
15593 + }
15594 + /* All done, drop cs if needed */
15595 + if ((offset & 255) != 1) {
15596 + /* Drop cs */
15597 + AND_REG(NULL, &cc->gpioout, ~mask);
15598 + if (!sflash_poll(cc, offset)) {
15599 + /* Flash rejected command */
15600 + return -12;
15601 + }
15602 + }
15603 + } else {
15604 + ret = 1;
15605 + W_REG(NULL, &cc->flashaddress, offset);
15606 + W_REG(NULL, &cc->flashdata, *buf);
15607 + /* Page program */
15608 + sflash_cmd(cc, SFLASH_ST_PP);
15609 + }
15610 + break;
15611 + case SFLASH_AT:
15612 + mask = sfl->blocksize - 1;
15613 + page = (offset & ~mask) << 1;
15614 + byte = offset & mask;
15615 + /* Read main memory page into buffer 1 */
15616 + if (byte || (len < sfl->blocksize)) {
15617 + W_REG(NULL, &cc->flashaddress, page);
15618 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
15619 + /* 250 us for AT45DB321B */
15620 + SPINWAIT(sflash_poll(cc, offset), 1000);
15621 + ASSERT(!sflash_poll(cc, offset));
15622 + }
15623 + /* Write into buffer 1 */
15624 + for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
15625 + W_REG(NULL, &cc->flashaddress, byte++);
15626 + W_REG(NULL, &cc->flashdata, *buf++);
15627 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
15628 + }
15629 + /* Write buffer 1 into main memory page */
15630 + W_REG(NULL, &cc->flashaddress, page);
15631 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
15632 + break;
15633 + }
15634 +
15635 + return ret;
15636 +}
15637 +
15638 +/* Erase a region. Returns number of bytes scheduled for erasure.
15639 + * Caller should poll for completion.
15640 + */
15641 +int
15642 +sflash_erase(chipcregs_t *cc, uint offset)
15643 +{
15644 + struct sflash *sfl;
15645 +
15646 + if (offset >= sflash.size)
15647 + return -22;
15648 +
15649 + sfl = &sflash;
15650 + switch (sfl->type) {
15651 + case SFLASH_ST:
15652 + sflash_cmd(cc, SFLASH_ST_WREN);
15653 + W_REG(NULL, &cc->flashaddress, offset);
15654 + sflash_cmd(cc, SFLASH_ST_SE);
15655 + return sfl->blocksize;
15656 + case SFLASH_AT:
15657 + W_REG(NULL, &cc->flashaddress, offset << 1);
15658 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
15659 + return sfl->blocksize;
15660 + }
15661 +
15662 + return 0;
15663 +}
15664 +
15665 +/*
15666 + * writes the appropriate range of flash, a NULL buf simply erases
15667 + * the region of flash
15668 + */
15669 +int
15670 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15671 +{
15672 + struct sflash *sfl;
15673 + uchar *block = NULL, *cur_ptr, *blk_ptr;
15674 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
15675 + uint blk_offset, blk_len, copied;
15676 + int bytes, ret = 0;
15677 +
15678 + /* Check address range */
15679 + if (len <= 0)
15680 + return 0;
15681 +
15682 + sfl = &sflash;
15683 + if ((offset + len) > sfl->size)
15684 + return -1;
15685 +
15686 + blocksize = sfl->blocksize;
15687 + mask = blocksize - 1;
15688 +
15689 + /* Allocate a block of mem */
15690 + if (!(block = MALLOC(NULL, blocksize)))
15691 + return -1;
15692 +
15693 + while (len) {
15694 + /* Align offset */
15695 + cur_offset = offset & ~mask;
15696 + cur_length = blocksize;
15697 + cur_ptr = block;
15698 +
15699 + remainder = blocksize - (offset & mask);
15700 + if (len < remainder)
15701 + cur_retlen = len;
15702 + else
15703 + cur_retlen = remainder;
15704 +
15705 + /* buf == NULL means erase only */
15706 + if (buf) {
15707 + /* Copy existing data into holding block if necessary */
15708 + if ((offset & mask) || (len < blocksize)) {
15709 + blk_offset = cur_offset;
15710 + blk_len = cur_length;
15711 + blk_ptr = cur_ptr;
15712 +
15713 + /* Copy entire block */
15714 + while (blk_len) {
15715 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
15716 + blk_offset += copied;
15717 + blk_len -= copied;
15718 + blk_ptr += copied;
15719 + }
15720 + }
15721 +
15722 + /* Copy input data into holding block */
15723 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
15724 + }
15725 +
15726 + /* Erase block */
15727 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
15728 + goto done;
15729 + while (sflash_poll(cc, (uint) cur_offset));
15730 +
15731 + /* buf == NULL means erase only */
15732 + if (!buf) {
15733 + offset += cur_retlen;
15734 + len -= cur_retlen;
15735 + continue;
15736 + }
15737 +
15738 + /* Write holding block */
15739 + while (cur_length > 0) {
15740 + if ((bytes = sflash_write(cc,
15741 + (uint) cur_offset,
15742 + (uint) cur_length,
15743 + (uchar *) cur_ptr)) < 0) {
15744 + ret = bytes;
15745 + goto done;
15746 + }
15747 + while (sflash_poll(cc, (uint) cur_offset));
15748 + cur_offset += bytes;
15749 + cur_length -= bytes;
15750 + cur_ptr += bytes;
15751 + }
15752 +
15753 + offset += cur_retlen;
15754 + len -= cur_retlen;
15755 + buf += cur_retlen;
15756 + }
15757 +
15758 + ret = len;
15759 +done:
15760 + if (block)
15761 + MFREE(NULL, block, blocksize);
15762 + return ret;
15763 +}
15764 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
15765 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
15766 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-04-28 00:45:40.000000000 +0200
15767 @@ -0,0 +1,119 @@
15768 +/*
15769 + * Copyright 2006, Broadcom Corporation
15770 + * All Rights Reserved.
15771 + *
15772 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15773 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15774 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15775 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15776 + *
15777 + * $Id: time.c,v 1.1.1.10 2006/02/27 03:42:55 honor Exp $
15778 + */
15779 +#include <linux/config.h>
15780 +#include <linux/init.h>
15781 +#include <linux/kernel.h>
15782 +#include <linux/sched.h>
15783 +#include <linux/serial_reg.h>
15784 +#include <linux/interrupt.h>
15785 +#include <asm/addrspace.h>
15786 +#include <asm/io.h>
15787 +#include <asm/time.h>
15788 +
15789 +#include <typedefs.h>
15790 +#include <osl.h>
15791 +#include <bcmnvram.h>
15792 +#include <sbconfig.h>
15793 +#include <sbextif.h>
15794 +#include <sbutils.h>
15795 +#include <hndmips.h>
15796 +#include <mipsinc.h>
15797 +#include <hndcpu.h>
15798 +
15799 +/* Global SB handle */
15800 +extern void *bcm947xx_sbh;
15801 +extern spinlock_t bcm947xx_sbh_lock;
15802 +
15803 +/* Convenience */
15804 +#define sbh bcm947xx_sbh
15805 +#define sbh_lock bcm947xx_sbh_lock
15806 +
15807 +extern int panic_timeout;
15808 +static int watchdog = 0;
15809 +static u8 *mcr = NULL;
15810 +
15811 +void __init
15812 +bcm947xx_time_init(void)
15813 +{
15814 + unsigned int hz;
15815 + extifregs_t *eir;
15816 +
15817 + /*
15818 + * Use deterministic values for initial counter interrupt
15819 + * so that calibrate delay avoids encountering a counter wrap.
15820 + */
15821 + write_c0_count(0);
15822 + write_c0_compare(0xffff);
15823 +
15824 + if (!(hz = sb_cpu_clock(sbh)))
15825 + hz = 100000000;
15826 +
15827 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
15828 + (hz + 500000) / 1000000);
15829 +
15830 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
15831 + mips_hpt_frequency = hz / 2;
15832 +
15833 + /* Set watchdog interval in ms */
15834 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
15835 +
15836 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
15837 + if (watchdog > 0) {
15838 + if (watchdog < 3000)
15839 + watchdog = 3000;
15840 + }
15841 +
15842 + /* Set panic timeout in seconds */
15843 + panic_timeout = watchdog / 1000;
15844 +
15845 + /* Setup blink */
15846 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
15847 + sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
15848 + unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
15849 + mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
15850 + }
15851 +}
15852 +
15853 +static void
15854 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
15855 +{
15856 + /* Generic MIPS timer code */
15857 + timer_interrupt(irq, dev_id, regs);
15858 +
15859 + /* Set the watchdog timer to reset after the specified number of ms */
15860 + if (watchdog > 0)
15861 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
15862 +
15863 +#ifdef CONFIG_HWSIM
15864 + (*((int *)0xa0000f1c))++;
15865 +#else
15866 + /* Blink one of the LEDs in the external UART */
15867 + if (mcr && !(jiffies % (HZ/2)))
15868 + writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
15869 +#endif
15870 +}
15871 +
15872 +static struct irqaction bcm947xx_timer_irqaction = {
15873 + bcm947xx_timer_interrupt,
15874 + SA_INTERRUPT,
15875 + 0,
15876 + "timer",
15877 + NULL,
15878 + NULL
15879 +};
15880 +
15881 +void __init
15882 +bcm947xx_timer_setup(struct irqaction *irq)
15883 +{
15884 + /* Enable the timer interrupt */
15885 + setup_irq(7, &bcm947xx_timer_irqaction);
15886 +}
15887 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
15888 --- linux.old/arch/mips/config-shared.in 2006-04-27 18:04:37.000000000 +0200
15889 +++ linux.dev/arch/mips/config-shared.in 2006-04-27 19:24:19.000000000 +0200
15890 @@ -208,6 +208,14 @@
15891 fi
15892 define_bool CONFIG_MIPS_RTC y
15893 fi
15894 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
15895 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
15896 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15897 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
15898 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
15899 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
15900 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
15901 +fi
15902 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
15903 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
15904 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
15905 @@ -229,6 +237,11 @@
15906 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
15907
15908 #
15909 +# Provide an option for a default kernel command line
15910 +#
15911 +string 'Default kernel command string' CONFIG_CMDLINE ""
15912 +
15913 +#
15914 # Select some configuration options automatically based on user selections.
15915 #
15916 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
15917 @@ -554,6 +567,13 @@
15918 define_bool CONFIG_SWAP_IO_SPACE_L y
15919 define_bool CONFIG_BOOT_ELF32 y
15920 fi
15921 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15922 + define_bool CONFIG_PCI y
15923 + define_bool CONFIG_NONCOHERENT_IO y
15924 + define_bool CONFIG_NEW_TIME_C y
15925 + define_bool CONFIG_NEW_IRQ y
15926 + define_bool CONFIG_HND y
15927 +fi
15928 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
15929 define_bool CONFIG_ARC32 y
15930 define_bool CONFIG_ARC_MEMORY y
15931 @@ -1042,7 +1062,11 @@
15932
15933 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
15934 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
15935 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
15936 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15937 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
15938 +else
15939 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
15940 +fi
15941 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
15942 if [ "$CONFIG_KGDB" = "y" ]; then
15943 define_bool CONFIG_DEBUG_INFO y
15944 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
15945 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-04-27 18:04:37.000000000 +0200
15946 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-04-27 19:24:19.000000000 +0200
15947 @@ -162,7 +162,7 @@
15948
15949 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
15950 {
15951 - switch (c->processor_id & 0xff00) {
15952 + switch (c->processor_id & PRID_IMP_MASK) {
15953 case PRID_IMP_R2000:
15954 c->cputype = CPU_R2000;
15955 c->isa_level = MIPS_CPU_ISA_I;
15956 @@ -172,7 +172,7 @@
15957 c->tlbsize = 64;
15958 break;
15959 case PRID_IMP_R3000:
15960 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
15961 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
15962 if (cpu_has_confreg())
15963 c->cputype = CPU_R3081E;
15964 else
15965 @@ -187,12 +187,12 @@
15966 break;
15967 case PRID_IMP_R4000:
15968 if (read_c0_config() & CONF_SC) {
15969 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15970 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15971 c->cputype = CPU_R4400PC;
15972 else
15973 c->cputype = CPU_R4000PC;
15974 } else {
15975 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15976 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15977 c->cputype = CPU_R4400SC;
15978 else
15979 c->cputype = CPU_R4000SC;
15980 @@ -438,7 +438,7 @@
15981 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
15982 {
15983 decode_config1(c);
15984 - switch (c->processor_id & 0xff00) {
15985 + switch (c->processor_id & PRID_IMP_MASK) {
15986 case PRID_IMP_4KC:
15987 c->cputype = CPU_4KC;
15988 c->isa_level = MIPS_CPU_ISA_M32;
15989 @@ -479,10 +479,10 @@
15990 {
15991 decode_config1(c);
15992 c->options |= MIPS_CPU_PREFETCH;
15993 - switch (c->processor_id & 0xff00) {
15994 + switch (c->processor_id & PRID_IMP_MASK) {
15995 case PRID_IMP_AU1_REV1:
15996 case PRID_IMP_AU1_REV2:
15997 - switch ((c->processor_id >> 24) & 0xff) {
15998 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
15999 case 0:
16000 c->cputype = CPU_AU1000;
16001 break;
16002 @@ -510,10 +510,34 @@
16003 }
16004 }
16005
16006 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
16007 +{
16008 + decode_config1(c);
16009 + c->options |= MIPS_CPU_PREFETCH;
16010 + switch (c->processor_id & PRID_IMP_MASK) {
16011 + case PRID_IMP_BCM4710:
16012 + c->cputype = CPU_BCM4710;
16013 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
16014 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
16015 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
16016 + break;
16017 + case PRID_IMP_4KC:
16018 + case PRID_IMP_BCM3302:
16019 + c->cputype = CPU_BCM3302;
16020 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
16021 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
16022 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
16023 + break;
16024 + default:
16025 + c->cputype = CPU_UNKNOWN;
16026 + break;
16027 + }
16028 +}
16029 +
16030 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
16031 {
16032 decode_config1(c);
16033 - switch (c->processor_id & 0xff00) {
16034 + switch (c->processor_id & PRID_IMP_MASK) {
16035 case PRID_IMP_SB1:
16036 c->cputype = CPU_SB1;
16037 c->isa_level = MIPS_CPU_ISA_M64;
16038 @@ -535,7 +559,7 @@
16039 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
16040 {
16041 decode_config1(c);
16042 - switch (c->processor_id & 0xff00) {
16043 + switch (c->processor_id & PRID_IMP_MASK) {
16044 case PRID_IMP_SR71000:
16045 c->cputype = CPU_SR71000;
16046 c->isa_level = MIPS_CPU_ISA_M64;
16047 @@ -560,7 +584,7 @@
16048 c->cputype = CPU_UNKNOWN;
16049
16050 c->processor_id = read_c0_prid();
16051 - switch (c->processor_id & 0xff0000) {
16052 + switch (c->processor_id & PRID_COMP_MASK) {
16053
16054 case PRID_COMP_LEGACY:
16055 cpu_probe_legacy(c);
16056 @@ -571,6 +595,9 @@
16057 case PRID_COMP_ALCHEMY:
16058 cpu_probe_alchemy(c);
16059 break;
16060 + case PRID_COMP_BROADCOM:
16061 + cpu_probe_broadcom(c);
16062 + break;
16063 case PRID_COMP_SIBYTE:
16064 cpu_probe_sibyte(c);
16065 break;
16066 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
16067 --- linux.old/arch/mips/kernel/head.S 2006-04-27 18:04:37.000000000 +0200
16068 +++ linux.dev/arch/mips/kernel/head.S 2006-04-27 19:24:19.000000000 +0200
16069 @@ -28,12 +28,20 @@
16070 #include <asm/mipsregs.h>
16071 #include <asm/stackframe.h>
16072
16073 +#ifdef CONFIG_BCM4710
16074 +#undef eret
16075 +#define eret nop; nop; eret
16076 +#endif
16077 +
16078 .text
16079 + j kernel_entry
16080 + nop
16081 +
16082 /*
16083 * Reserved space for exception handlers.
16084 * Necessary for machines which link their kernels at KSEG0.
16085 */
16086 - .fill 0x400
16087 + .fill 0x3f4
16088
16089 /* The following two symbols are used for kernel profiling. */
16090 EXPORT(stext)
16091 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
16092 --- linux.old/arch/mips/kernel/proc.c 2006-04-27 18:04:37.000000000 +0200
16093 +++ linux.dev/arch/mips/kernel/proc.c 2006-04-27 19:24:19.000000000 +0200
16094 @@ -78,9 +78,10 @@
16095 [CPU_AU1550] "Au1550",
16096 [CPU_24K] "MIPS 24K",
16097 [CPU_AU1200] "Au1200",
16098 + [CPU_BCM4710] "BCM4710",
16099 + [CPU_BCM3302] "BCM3302",
16100 };
16101
16102 -
16103 static int show_cpuinfo(struct seq_file *m, void *v)
16104 {
16105 unsigned int version = current_cpu_data.processor_id;
16106 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
16107 --- linux.old/arch/mips/kernel/setup.c 2006-04-27 18:04:37.000000000 +0200
16108 +++ linux.dev/arch/mips/kernel/setup.c 2006-04-27 19:24:19.000000000 +0200
16109 @@ -493,6 +493,7 @@
16110 void swarm_setup(void);
16111 void hp_setup(void);
16112 void au1x00_setup(void);
16113 + void brcm_setup(void);
16114 void frame_info_init(void);
16115
16116 frame_info_init();
16117 @@ -691,6 +692,11 @@
16118 pmc_yosemite_setup();
16119 break;
16120 #endif
16121 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
16122 + case MACH_GROUP_BRCM:
16123 + brcm_setup();
16124 + break;
16125 +#endif
16126 default:
16127 panic("Unsupported architecture");
16128 }
16129 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
16130 --- linux.old/arch/mips/kernel/traps.c 2006-04-27 18:04:37.000000000 +0200
16131 +++ linux.dev/arch/mips/kernel/traps.c 2006-04-27 19:24:19.000000000 +0200
16132 @@ -920,6 +920,7 @@
16133 void __init trap_init(void)
16134 {
16135 extern char except_vec1_generic;
16136 + extern char except_vec2_generic;
16137 extern char except_vec3_generic, except_vec3_r4000;
16138 extern char except_vec_ejtag_debug;
16139 extern char except_vec4;
16140 @@ -927,6 +928,7 @@
16141
16142 /* Copy the generic exception handler code to it's final destination. */
16143 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
16144 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
16145
16146 /*
16147 * Setup default vectors
16148 @@ -985,6 +987,12 @@
16149 set_except_vector(13, handle_tr);
16150 set_except_vector(22, handle_mdmx);
16151
16152 + if (current_cpu_data.cputype == CPU_SB1) {
16153 + /* Enable timer interrupt and scd mapped interrupt */
16154 + clear_c0_status(0xf000);
16155 + set_c0_status(0xc00);
16156 + }
16157 +
16158 if (cpu_has_fpu && !cpu_has_nofpuex)
16159 set_except_vector(15, handle_fpe);
16160
16161 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16162 --- linux.old/arch/mips/mm/c-r4k.c 2006-04-27 18:04:37.000000000 +0200
16163 +++ linux.dev/arch/mips/mm/c-r4k.c 2006-04-27 19:24:19.000000000 +0200
16164 @@ -1166,3 +1166,47 @@
16165 build_clear_page();
16166 build_copy_page();
16167 }
16168 +
16169 +#ifdef CONFIG_BCM4704
16170 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
16171 +{
16172 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
16173 + int i;
16174 + for (i = 0; i < nbytes; i += ic_lsize)
16175 + fill_icache_line((addr + i));
16176 +}
16177 +
16178 +/*
16179 + * This must be run from the cache on 4704A0
16180 + * so there are no mips core BIU ops in progress
16181 + * when the PFC is enabled.
16182 + */
16183 +#define PFC_CR0 0xff400000 /* control reg 0 */
16184 +#define PFC_CR1 0xff400004 /* control reg 1 */
16185 +static void __init enable_pfc(u32 mode)
16186 +{
16187 + /* write range */
16188 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
16189 +
16190 + /* enable */
16191 + *(volatile u32 *)PFC_CR0 = mode;
16192 +}
16193 +#endif
16194 +
16195 +
16196 +void check_enable_mips_pfc(int val)
16197 +{
16198 +
16199 +#ifdef CONFIG_BCM4704
16200 + struct cpuinfo_mips *c = &current_cpu_data;
16201 +
16202 + /* enable prefetch cache */
16203 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
16204 + && (read_c0_diag() & (1 << 29))) {
16205 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
16206 + enable_pfc(val);
16207 + }
16208 +#endif
16209 +}
16210 +
16211 +
16212 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
16213 --- linux.old/arch/mips/pci/Makefile 2006-04-27 18:04:37.000000000 +0200
16214 +++ linux.dev/arch/mips/pci/Makefile 2006-04-27 19:24:19.000000000 +0200
16215 @@ -13,7 +13,9 @@
16216 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
16217 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
16218 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
16219 +ifndef CONFIG_BCM947XX
16220 obj-y += pci.o
16221 +endif
16222 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
16223
16224 include $(TOPDIR)/Rules.make
16225 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
16226 --- linux.old/drivers/char/serial.c 2006-04-27 18:04:37.000000000 +0200
16227 +++ linux.dev/drivers/char/serial.c 2006-04-27 19:24:19.000000000 +0200
16228 @@ -444,6 +444,10 @@
16229 return inb(info->port+1);
16230 #endif
16231 case SERIAL_IO_MEM:
16232 +#ifdef CONFIG_BCM4310
16233 + readb((unsigned long) info->iomem_base +
16234 + (UART_SCR<<info->iomem_reg_shift));
16235 +#endif
16236 return readb((unsigned long) info->iomem_base +
16237 (offset<<info->iomem_reg_shift));
16238 default:
16239 @@ -464,6 +468,9 @@
16240 case SERIAL_IO_MEM:
16241 writeb(value, (unsigned long) info->iomem_base +
16242 (offset<<info->iomem_reg_shift));
16243 +#ifdef CONFIG_BCM4704
16244 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
16245 +#endif
16246 break;
16247 default:
16248 outb(value, info->port+offset);
16249 @@ -1728,7 +1735,7 @@
16250 /* Special case since 134 is really 134.5 */
16251 quot = (2*baud_base / 269);
16252 else if (baud)
16253 - quot = baud_base / baud;
16254 + quot = (baud_base + (baud / 2)) / baud;
16255 }
16256 /* If the quotient is zero refuse the change */
16257 if (!quot && old_termios) {
16258 @@ -1745,12 +1752,12 @@
16259 /* Special case since 134 is really 134.5 */
16260 quot = (2*baud_base / 269);
16261 else if (baud)
16262 - quot = baud_base / baud;
16263 + quot = (baud_base + (baud / 2)) / baud;
16264 }
16265 }
16266 /* As a last resort, if the quotient is zero, default to 9600 bps */
16267 if (!quot)
16268 - quot = baud_base / 9600;
16269 + quot = (baud_base + 4800) / 9600;
16270 /*
16271 * Work around a bug in the Oxford Semiconductor 952 rev B
16272 * chip which causes it to seriously miscalculate baud rates
16273 @@ -5994,6 +6001,13 @@
16274 * Divisor, bytesize and parity
16275 */
16276 state = rs_table + co->index;
16277 + /*
16278 + * Safe guard: state structure must have been initialized
16279 + */
16280 + if (state->iomem_base == NULL) {
16281 + printk("!unable to setup serial console!\n");
16282 + return -1;
16283 + }
16284 if (doflow)
16285 state->flags |= ASYNC_CONS_FLOW;
16286 info = &async_sercons;
16287 @@ -6007,7 +6021,7 @@
16288 info->io_type = state->io_type;
16289 info->iomem_base = state->iomem_base;
16290 info->iomem_reg_shift = state->iomem_reg_shift;
16291 - quot = state->baud_base / baud;
16292 + quot = (state->baud_base + (baud / 2)) / baud;
16293 cval = cflag & (CSIZE | CSTOPB);
16294 #if defined(__powerpc__) || defined(__alpha__)
16295 cval >>= 8;
16296 diff -urN linux.old/drivers/net/Config.in linux.dev/drivers/net/Config.in
16297 --- linux.old/drivers/net/Config.in 2006-04-27 18:04:38.000000000 +0200
16298 +++ linux.dev/drivers/net/Config.in 2006-04-27 19:24:19.000000000 +0200
16299 @@ -2,6 +2,8 @@
16300 # Network device configuration
16301 #
16302
16303 +tristate 'Broadcom Home Network Division' CONFIG_HND $CONFIG_PCI
16304 +
16305 source drivers/net/arcnet/Config.in
16306
16307 tristate 'Dummy net driver support' CONFIG_DUMMY
16308 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
16309 --- linux.old/drivers/net/Makefile 2006-04-27 18:04:38.000000000 +0200
16310 +++ linux.dev/drivers/net/Makefile 2006-05-04 01:41:03.000000000 +0200
16311 @@ -3,6 +3,8 @@
16312 # Makefile for the Linux network (ethercard) device drivers.
16313 #
16314
16315 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
16316 +
16317 obj-y :=
16318 obj-m :=
16319 obj-n :=
16320 @@ -39,6 +41,7 @@
16321 obj-$(CONFIG_ISDN) += slhc.o
16322 endif
16323
16324 +subdir-$(CONFIG_WL) += wl
16325 subdir-$(CONFIG_NET_PCMCIA) += pcmcia
16326 subdir-$(CONFIG_NET_WIRELESS) += wireless
16327 subdir-$(CONFIG_TULIP) += tulip
16328 diff -urN linux.old/drivers/net/wireless/Config.in linux.dev/drivers/net/wireless/Config.in
16329 --- linux.old/drivers/net/wireless/Config.in 2006-04-27 18:04:38.000000000 +0200
16330 +++ linux.dev/drivers/net/wireless/Config.in 2006-05-04 01:42:48.000000000 +0200
16331 @@ -13,6 +13,7 @@
16332 fi
16333
16334 if [ "$CONFIG_PCI" = "y" ]; then
16335 + dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support' CONFIG_WL
16336 dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
16337 dep_tristate ' Hermes in TMD7160/NCP130 based PCI adaptor support (Pheecom WL-PCI etc.) (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
16338 dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
16339 diff -urN linux.old/drivers/net/wl/patchtable.pl linux.dev/drivers/net/wl/patchtable.pl
16340 --- linux.old/drivers/net/wl/patchtable.pl 1970-01-01 01:00:00.000000000 +0100
16341 +++ linux.dev/drivers/net/wl/patchtable.pl 2006-04-28 01:33:52.000000000 +0200
16342 @@ -0,0 +1,54 @@
16343 +#!/usr/bin/perl
16344 +use strict;
16345 +
16346 +my $TABLE = pack("V", 0xbadc0ded);
16347 +my $TABLE_SIZE = 512;
16348 +my $SLT1 = "\x01\x00\x00\x00";
16349 +my $SLT2 = "\x02\x00\x00\x00";
16350 +my $ACKW = "\x03\x00\x00\x00";
16351 +my $PTABLE_END = "\xff\xff\xff\xff";
16352 +
16353 +my $addr = "";
16354 +my $opcode = "";
16355 +my $function = "";
16356 +
16357 +sub add_entry {
16358 + my $key = shift;
16359 + my $value = shift;
16360 + my $default = shift;
16361 +
16362 + $TABLE .= $key;
16363 + $TABLE .= pack("V", $value);
16364 + $TABLE .= pack("V", $default);
16365 +}
16366 +
16367 +while (<>) {
16368 + $addr = $opcode = "";
16369 + /^\w{8}\s*<(.*)>:$/ and $function = $1;
16370 + /^\s*(\w+):\s*(\w{8})\s*/ and do {
16371 + $addr = $1;
16372 + $opcode = $2;
16373 + };
16374 +
16375 + ($function eq 'wlc_update_slot_timing') and do {
16376 + # li a2,9 -- short slot time
16377 + ($opcode eq '24060009') and add_entry($SLT1, hex($addr), hex($opcode));
16378 + # li v0,519 -- 510 + short slot time
16379 + ($opcode eq '24020207') and add_entry($SLT2, hex($addr), hex($opcode));
16380 +
16381 + # li a2,20 -- long slot time
16382 + ($opcode eq '24060014') and add_entry($SLT1, hex($addr), hex($opcode));
16383 + # li v0,530 -- 510 + long slot time
16384 + ($opcode eq '24020212') and add_entry($SLT2, hex($addr), hex($opcode));
16385 + };
16386 + ($function eq 'wlc_d11hdrs') and do {
16387 + # ori s6,s6,0x1 -- ack flag (new)
16388 + ($opcode eq '36d60001') and add_entry($ACKW, hex($addr), hex($opcode));
16389 + # ori s3,s3,0x1 -- ack flag (old)
16390 + ($opcode eq '36730001') and add_entry($ACKW, hex($addr), hex($opcode));
16391 + }
16392 +}
16393 +
16394 +$TABLE .= $PTABLE_END;
16395 +$TABLE .= ("\x00" x ($TABLE_SIZE - length($TABLE)));
16396 +print $TABLE;
16397 diff -urN linux.old/drivers/net/wl/Makefile linux.dev/drivers/net/wl/Makefile
16398 --- linux.old/drivers/net/wl/Makefile 1970-01-01 01:00:00.000000000 +0100
16399 +++ linux.dev/drivers/net/wl/Makefile 2006-04-28 01:33:52.000000000 +0200
16400 @@ -0,0 +1,32 @@
16401 +#
16402 +# Makefile for the Broadcom wl driver
16403 +#
16404 +# Copyright 2004, Broadcom Corporation
16405 +# All Rights Reserved.
16406 +#
16407 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
16408 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
16409 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16410 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16411 +#
16412 +# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
16413 +
16414 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
16415 +
16416 +O_TARGET := wl_link.o
16417 +
16418 +obj-y := wl_mod.o
16419 +obj-y += bcmutils.o hnddma.o linux_osl.o
16420 +
16421 +obj-m := $(O_TARGET)
16422 +
16423 +wl_mod.o: wl_apsta.o
16424 + sed -e 's,eth%d,wl%d\x00,g' < $< > $@
16425 +
16426 +wl.o: wl_link.o
16427 + $(OBJDUMP) -d $< | perl patchtable.pl > patchtable.bin
16428 + cat wl_link.o patchtable.bin > $@
16429 +
16430 +modules: wl.o
16431 +
16432 +include $(TOPDIR)/Rules.make
16433 diff -urN linux.old/drivers/net/wl/bcmip.h linux.dev/drivers/net/wl/bcmip.h
16434 --- linux.old/drivers/net/wl/bcmip.h 1970-01-01 01:00:00.000000000 +0100
16435 +++ linux.dev/drivers/net/wl/bcmip.h 2006-04-28 02:11:28.000000000 +0200
16436 @@ -0,0 +1,101 @@
16437 +/*
16438 + * Copyright 2006, Broadcom Corporation
16439 + * All Rights Reserved.
16440 + *
16441 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
16442 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
16443 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16444 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16445 + *
16446 + * Fundamental constants relating to IP Protocol
16447 + *
16448 + * $Id: bcmip.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
16449 + */
16450 +
16451 +#ifndef _bcmip_h_
16452 +#define _bcmip_h_
16453 +
16454 +/* IPV4 and IPV6 common */
16455 +#define IP_VER_OFFSET 0x0 /* offset to version field */
16456 +#define IP_VER_MASK 0xf0 /* version mask */
16457 +#define IP_VER_SHIFT 4 /* version shift */
16458 +#define IP_VER_4 4 /* version number for IPV4 */
16459 +#define IP_VER_6 6 /* version number for IPV6 */
16460 +
16461 +#define IP_VER(ip_body) \
16462 + ((((uint8 *)(ip_body))[IP_VER_OFFSET] & IP_VER_MASK) >> IP_VER_SHIFT)
16463 +
16464 +#define IP_PROT_ICMP 0x1 /* ICMP protocol */
16465 +#define IP_PROT_TCP 0x6 /* TCP protocol */
16466 +#define IP_PROT_UDP 0x11 /* UDP protocol type */
16467 +
16468 +/* IPV4 field offsets */
16469 +#define IPV4_VER_HL_OFFSET 0 /* version and ihl byte offset */
16470 +#define IPV4_TOS_OFFSET 1 /* type of service offset */
16471 +#define IPV4_PROT_OFFSET 9 /* protocol type offset */
16472 +#define IPV4_CHKSUM_OFFSET 10 /* IP header checksum offset */
16473 +#define IPV4_SRC_IP_OFFSET 12 /* src IP addr offset */
16474 +#define IPV4_DEST_IP_OFFSET 16 /* dest IP addr offset */
16475 +
16476 +/* IPV4 field decodes */
16477 +#define IPV4_VER_MASK 0xf0 /* IPV4 version mask */
16478 +#define IPV4_VER_SHIFT 4 /* IPV4 version shift */
16479 +
16480 +#define IPV4_HLEN_MASK 0x0f /* IPV4 header length mask */
16481 +#define IPV4_HLEN(ipv4_body) (4 * (((uint8 *)(ipv4_body))[IPV4_VER_HL_OFFSET] & IPV4_HLEN_MASK))
16482 +
16483 +#define IPV4_ADDR_LEN 4 /* IPV4 address length */
16484 +
16485 +#define IPV4_ADDR_NULL(a) ((((uint8 *)(a))[0] | ((uint8 *)(a))[1] | \
16486 + ((uint8 *)(a))[2] | ((uint8 *)(a))[3]) == 0)
16487 +
16488 +#define IPV4_TOS_DSCP_MASK 0xfc /* DiffServ codepoint mask */
16489 +#define IPV4_TOS_DSCP_SHIFT 2 /* DiffServ codepoint shift */
16490 +
16491 +#define IPV4_TOS(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_TOS_OFFSET])
16492 +
16493 +#define IPV4_TOS_PREC_MASK 0xe0 /* Historical precedence mask */
16494 +#define IPV4_TOS_PREC_SHIFT 5 /* Historical precedence shift */
16495 +
16496 +#define IPV4_TOS_LOWDELAY 0x10 /* Lowest delay requested */
16497 +#define IPV4_TOS_THROUGHPUT 0x8 /* Best throughput requested */
16498 +#define IPV4_TOS_RELIABILITY 0x4 /* Most reliable delivery requested */
16499 +
16500 +#define IPV4_PROT(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_PROT_OFFSET])
16501 +
16502 +#define IPV4_ADDR_STR_LEN 16 /* Max IP address length in string format */
16503 +
16504 +/* IPV6 field offsets */
16505 +#define IPV6_PAYLOAD_LEN_OFFSET 4 /* payload length offset */
16506 +#define IPV6_NEXT_HDR_OFFSET 6 /* next header/protocol offset */
16507 +#define IPV6_HOP_LIMIT_OFFSET 7 /* hop limit offset */
16508 +#define IPV6_SRC_IP_OFFSET 8 /* src IP addr offset */
16509 +#define IPV6_DEST_IP_OFFSET 24 /* dst IP addr offset */
16510 +
16511 +/* IPV6 field decodes */
16512 +#define IPV6_TRAFFIC_CLASS(ipv6_body) \
16513 + (((((uint8 *)(ipv6_body))[0] & 0x0f) << 4) | \
16514 + ((((uint8 *)(ipv6_body))[1] & 0xf0) >> 4))
16515 +
16516 +#define IPV6_FLOW_LABEL(ipv6_body) \
16517 + (((((uint8 *)(ipv6_body))[1] & 0x0f) << 16) | \
16518 + (((uint8 *)(ipv6_body))[2] << 8) | \
16519 + (((uint8 *)(ipv6_body))[3]))
16520 +
16521 +#define IPV6_PAYLOAD_LEN(ipv6_body) \
16522 + ((((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 0] << 8) | \
16523 + ((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 1])
16524 +
16525 +#define IPV6_NEXT_HDR(ipv6_body) \
16526 + (((uint8 *)(ipv6_body))[IPV6_NEXT_HDR_OFFSET])
16527 +
16528 +#define IPV6_PROT(ipv6_body) IPV6_NEXT_HDR(ipv6_body)
16529 +
16530 +#define IPV6_ADDR_LEN 16 /* IPV6 address length */
16531 +
16532 +/* IPV4 TOS or IPV6 Traffic Classifier or 0 */
16533 +#define IP_TOS(ip_body) \
16534 + (IP_VER(ip_body) == IP_VER_4 ? IPV4_TOS(ip_body) : \
16535 + IP_VER(ip_body) == IP_VER_6 ? IPV6_TRAFFIC_CLASS(ip_body) : 0)
16536 +
16537 +#endif /* _bcmip_h_ */
16538 diff -urN linux.old/drivers/net/wl/bcmutils.c linux.dev/drivers/net/wl/bcmutils.c
16539 --- linux.old/drivers/net/wl/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
16540 +++ linux.dev/drivers/net/wl/bcmutils.c 2006-04-28 02:27:20.000000000 +0200
16541 @@ -0,0 +1,857 @@
16542 +/*
16543 + * Misc useful OS-independent routines.
16544 + *
16545 + * Copyright 2006, Broadcom Corporation
16546 + * All Rights Reserved.
16547 + *
16548 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
16549 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
16550 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16551 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16552 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
16553 + */
16554 +
16555 +#include <typedefs.h>
16556 +#include <bcmdefs.h>
16557 +#include <stdarg.h>
16558 +#include <osl.h>
16559 +#include "linux_osl.h"
16560 +#include "pktq.h"
16561 +#include <bcmutils.h>
16562 +#include <sbutils.h>
16563 +#include <bcmnvram.h>
16564 +#include <bcmendian.h>
16565 +#include <bcmdevs.h>
16566 +#include "bcmip.h"
16567 +
16568 +#define ETHER_TYPE_8021Q 0x8100
16569 +#define ETHER_TYPE_IP 0x0800
16570 +#define VLAN_PRI_SHIFT 13
16571 +#define VLAN_PRI_MASK 7
16572 +
16573 +
16574 +struct ether_header {
16575 + uint8 ether_dhost[6];
16576 + uint8 ether_shost[6];
16577 + uint16 ether_type;
16578 +} __attribute__((packed));
16579 +
16580 +
16581 +struct ethervlan_header {
16582 + uint8 ether_dhost[6];
16583 + uint8 ether_shost[6];
16584 + uint16 vlan_type; /* 0x8100 */
16585 + uint16 vlan_tag; /* priority, cfi and vid */
16586 + uint16 ether_type;
16587 +};
16588 +
16589 +/* copy a pkt buffer chain into a buffer */
16590 +uint
16591 +pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
16592 +{
16593 + uint n, ret = 0;
16594 +
16595 + if (len < 0)
16596 + len = 4096; /* "infinite" */
16597 +
16598 + /* skip 'offset' bytes */
16599 + for (; p && offset; p = PKTNEXT(osh, p)) {
16600 + if (offset < (uint)PKTLEN(osh, p))
16601 + break;
16602 + offset -= PKTLEN(osh, p);
16603 + }
16604 +
16605 + if (!p)
16606 + return 0;
16607 +
16608 + /* copy the data */
16609 + for (; p && len; p = PKTNEXT(osh, p)) {
16610 + n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
16611 + bcopy(PKTDATA(osh, p) + offset, buf, n);
16612 + buf += n;
16613 + len -= n;
16614 + ret += n;
16615 + offset = 0;
16616 + }
16617 +
16618 + return ret;
16619 +}
16620 +
16621 +/* return total length of buffer chain */
16622 +uint
16623 +pkttotlen(osl_t *osh, void *p)
16624 +{
16625 + uint total;
16626 +
16627 + total = 0;
16628 + for (; p; p = PKTNEXT(osh, p))
16629 + total += PKTLEN(osh, p);
16630 + return (total);
16631 +}
16632 +
16633 +/* return the last buffer of chained pkt */
16634 +void *
16635 +pktlast(osl_t *osh, void *p)
16636 +{
16637 + for (; PKTNEXT(osh, p); p = PKTNEXT(osh, p))
16638 + ;
16639 +
16640 + return (p);
16641 +}
16642 +
16643 +
16644 +/*
16645 + * osl multiple-precedence packet queue
16646 + * hi_prec is always >= the number of the highest non-empty queue
16647 + */
16648 +void *
16649 +pktq_penq(struct pktq *pq, int prec, void *p)
16650 +{
16651 + struct pktq_prec *q;
16652 +
16653 + ASSERT(prec >= 0 && prec < pq->num_prec);
16654 + ASSERT(PKTLINK(p) == NULL); /* queueing chains not allowed */
16655 +
16656 + ASSERT(!pktq_full(pq));
16657 + ASSERT(!pktq_pfull(pq, prec));
16658 +
16659 + q = &pq->q[prec];
16660 +
16661 + if (q->head)
16662 + PKTSETLINK(q->tail, p);
16663 + else
16664 + q->head = p;
16665 +
16666 + q->tail = p;
16667 + q->len++;
16668 +
16669 + pq->len++;
16670 +
16671 + if (pq->hi_prec < prec)
16672 + pq->hi_prec = (uint8)prec;
16673 +
16674 + return p;
16675 +}
16676 +
16677 +void *
16678 +pktq_penq_head(struct pktq *pq, int prec, void *p)
16679 +{
16680 + struct pktq_prec *q;
16681 +
16682 + ASSERT(prec >= 0 && prec < pq->num_prec);
16683 + ASSERT(PKTLINK(p) == NULL); /* queueing chains not allowed */
16684 +
16685 + ASSERT(!pktq_full(pq));
16686 + ASSERT(!pktq_pfull(pq, prec));
16687 +
16688 + q = &pq->q[prec];
16689 +
16690 + if (q->head == NULL)
16691 + q->tail = p;
16692 +
16693 + PKTSETLINK(p, q->head);
16694 + q->head = p;
16695 + q->len++;
16696 +
16697 + pq->len++;
16698 +
16699 + if (pq->hi_prec < prec)
16700 + pq->hi_prec = (uint8)prec;
16701 +
16702 + return p;
16703 +}
16704 +
16705 +void *
16706 +pktq_pdeq(struct pktq *pq, int prec)
16707 +{
16708 + struct pktq_prec *q;
16709 + void *p;
16710 +
16711 + ASSERT(prec >= 0 && prec < pq->num_prec);
16712 +
16713 + q = &pq->q[prec];
16714 +
16715 + if ((p = q->head) == NULL)
16716 + return NULL;
16717 +
16718 + if ((q->head = PKTLINK(p)) == NULL)
16719 + q->tail = NULL;
16720 +
16721 + q->len--;
16722 +
16723 + pq->len--;
16724 +
16725 + PKTSETLINK(p, NULL);
16726 +
16727 + return p;
16728 +}
16729 +
16730 +void *
16731 +pktq_pdeq_tail(struct pktq *pq, int prec)
16732 +{
16733 + struct pktq_prec *q;
16734 + void *p, *prev;
16735 +
16736 + ASSERT(prec >= 0 && prec < pq->num_prec);
16737 +
16738 + q = &pq->q[prec];
16739 +
16740 + if ((p = q->head) == NULL)
16741 + return NULL;
16742 +
16743 + for (prev = NULL; p != q->tail; p = PKTLINK(p))
16744 + prev = p;
16745 +
16746 + if (prev)
16747 + PKTSETLINK(prev, NULL);
16748 + else
16749 + q->head = NULL;
16750 +
16751 + q->tail = prev;
16752 + q->len--;
16753 +
16754 + pq->len--;
16755 +
16756 + return p;
16757 +}
16758 +
16759 +void
16760 +pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir)
16761 +{
16762 + struct pktq_prec *q;
16763 + void *p;
16764 +
16765 + q = &pq->q[prec];
16766 + p = q->head;
16767 + while (p) {
16768 + q->head = PKTLINK(p);
16769 + PKTSETLINK(p, NULL);
16770 + PKTFREE(osh, p, dir);
16771 + q->len--;
16772 + pq->len--;
16773 + p = q->head;
16774 + }
16775 + ASSERT(q->len == 0);
16776 + q->tail = NULL;
16777 +}
16778 +
16779 +bool
16780 +pktq_pdel(struct pktq *pq, void *pktbuf, int prec)
16781 +{
16782 + struct pktq_prec *q;
16783 + void *p;
16784 +
16785 + ASSERT(prec >= 0 && prec < pq->num_prec);
16786 +
16787 + if (!pktbuf)
16788 + return FALSE;
16789 +
16790 + q = &pq->q[prec];
16791 +
16792 + if (q->head == pktbuf) {
16793 + if ((q->head = PKTLINK(pktbuf)) == NULL)
16794 + q->tail = NULL;
16795 + } else {
16796 + for (p = q->head; p && PKTLINK(p) != pktbuf; p = PKTLINK(p))
16797 + ;
16798 + if (p == NULL)
16799 + return FALSE;
16800 +
16801 + PKTSETLINK(p, PKTLINK(pktbuf));
16802 + if (q->tail == pktbuf)
16803 + q->tail = p;
16804 + }
16805 +
16806 + q->len--;
16807 + pq->len--;
16808 + PKTSETLINK(pktbuf, NULL);
16809 + return TRUE;
16810 +}
16811 +
16812 +void
16813 +pktq_init(struct pktq *pq, int num_prec, int max_len)
16814 +{
16815 + int prec;
16816 +
16817 + ASSERT(num_prec > 0 && num_prec <= PKTQ_MAX_PREC);
16818 +
16819 + bzero(pq, sizeof(*pq));
16820 +
16821 + pq->num_prec = (uint16)num_prec;
16822 +
16823 + pq->max = (uint16)max_len;
16824 +
16825 + for (prec = 0; prec < num_prec; prec++)
16826 + pq->q[prec].max = pq->max;
16827 +}
16828 +
16829 +void *
16830 +pktq_deq(struct pktq *pq, int *prec_out)
16831 +{
16832 + struct pktq_prec *q;
16833 + void *p;
16834 + int prec;
16835 +
16836 + if (pq->len == 0)
16837 + return NULL;
16838 +
16839 + while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
16840 + pq->hi_prec--;
16841 +
16842 + q = &pq->q[prec];
16843 +
16844 + if ((p = q->head) == NULL)
16845 + return NULL;
16846 +
16847 + if ((q->head = PKTLINK(p)) == NULL)
16848 + q->tail = NULL;
16849 +
16850 + q->len--;
16851 +
16852 + pq->len--;
16853 +
16854 + if (prec_out)
16855 + *prec_out = prec;
16856 +
16857 + PKTSETLINK(p, NULL);
16858 +
16859 + return p;
16860 +}
16861 +
16862 +void *
16863 +pktq_deq_tail(struct pktq *pq, int *prec_out)
16864 +{
16865 + struct pktq_prec *q;
16866 + void *p, *prev;
16867 + int prec;
16868 +
16869 + if (pq->len == 0)
16870 + return NULL;
16871 +
16872 + for (prec = 0; prec < pq->hi_prec; prec++)
16873 + if (pq->q[prec].head)
16874 + break;
16875 +
16876 + q = &pq->q[prec];
16877 +
16878 + if ((p = q->head) == NULL)
16879 + return NULL;
16880 +
16881 + for (prev = NULL; p != q->tail; p = PKTLINK(p))
16882 + prev = p;
16883 +
16884 + if (prev)
16885 + PKTSETLINK(prev, NULL);
16886 + else
16887 + q->head = NULL;
16888 +
16889 + q->tail = prev;
16890 + q->len--;
16891 +
16892 + pq->len--;
16893 +
16894 + if (prec_out)
16895 + *prec_out = prec;
16896 +
16897 + PKTSETLINK(p, NULL);
16898 +
16899 + return p;
16900 +}
16901 +
16902 +void *
16903 +pktq_peek(struct pktq *pq, int *prec_out)
16904 +{
16905 + int prec;
16906 +
16907 + if (pq->len == 0)
16908 + return NULL;
16909 +
16910 + while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
16911 + pq->hi_prec--;
16912 +
16913 + if (prec_out)
16914 + *prec_out = prec;
16915 +
16916 + return (pq->q[prec].head);
16917 +}
16918 +
16919 +void *
16920 +pktq_peek_tail(struct pktq *pq, int *prec_out)
16921 +{
16922 + int prec;
16923 +
16924 + if (pq->len == 0)
16925 + return NULL;
16926 +
16927 + for (prec = 0; prec < pq->hi_prec; prec++)
16928 + if (pq->q[prec].head)
16929 + break;
16930 +
16931 + if (prec_out)
16932 + *prec_out = prec;
16933 +
16934 + return (pq->q[prec].tail);
16935 +}
16936 +
16937 +void
16938 +pktq_flush(osl_t *osh, struct pktq *pq, bool dir)
16939 +{
16940 + int prec;
16941 + for (prec = 0; prec < pq->num_prec; prec++)
16942 + pktq_pflush(osh, pq, prec, dir);
16943 + ASSERT(pq->len == 0);
16944 +}
16945 +
16946 +/* Return sum of lengths of a specific set of precedences */
16947 +int
16948 +pktq_mlen(struct pktq *pq, uint prec_bmp)
16949 +{
16950 + int prec, len;
16951 +
16952 + len = 0;
16953 +
16954 + for (prec = 0; prec <= pq->hi_prec; prec++)
16955 + if (prec_bmp & (1 << prec))
16956 + len += pq->q[prec].len;
16957 +
16958 + return len;
16959 +}
16960 +
16961 +/* Priority dequeue from a specific set of precedences */
16962 +void *
16963 +pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out)
16964 +{
16965 + struct pktq_prec *q;
16966 + void *p;
16967 + int prec;
16968 +
16969 + if (pq->len == 0)
16970 + return NULL;
16971 +
16972 + while ((prec = pq->hi_prec) > 0 && pq->q[prec].head == NULL)
16973 + pq->hi_prec--;
16974 +
16975 + while ((prec_bmp & (1 << prec)) == 0 || pq->q[prec].head == NULL)
16976 + if (prec-- == 0)
16977 + return NULL;
16978 +
16979 + q = &pq->q[prec];
16980 +
16981 + if ((p = q->head) == NULL)
16982 + return NULL;
16983 +
16984 + if ((q->head = PKTLINK(p)) == NULL)
16985 + q->tail = NULL;
16986 +
16987 + q->len--;
16988 +
16989 + if (prec_out)
16990 + *prec_out = prec;
16991 +
16992 + pq->len--;
16993 +
16994 + PKTSETLINK(p, NULL);
16995 +
16996 + return p;
16997 +}
16998 +
16999 +char*
17000 +bcmstrcat(char *dest, const char *src)
17001 +{
17002 + strcpy(&dest[strlen(dest)], src);
17003 + return (dest);
17004 +}
17005 +
17006 +char*
17007 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
17008 +{
17009 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
17010 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
17011 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
17012 + return (buf);
17013 +}
17014 +
17015 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
17016 +int
17017 +bcm_ether_atoe(char *p, struct ether_addr *ea)
17018 +{
17019 + int i = 0;
17020 +
17021 + for (;;) {
17022 + ea->octet[i++] = (char) bcm_strtoul(p, &p, 16);
17023 + if (!*p++ || i == 6)
17024 + break;
17025 + }
17026 +
17027 + return (i == 6);
17028 +}
17029 +
17030 +/* Takes an Ethernet frame and sets out-of-bound PKTPRIO
17031 + * Also updates the inplace vlan tag if requested
17032 + */
17033 +void
17034 +pktsetprio(void *pkt, bool update_vtag)
17035 +{
17036 + struct ether_header *eh;
17037 + struct ethervlan_header *evh;
17038 + uint8 *pktdata;
17039 + int priority = 0;
17040 +
17041 + pktdata = (uint8 *) PKTDATA(NULL, pkt);
17042 + ASSERT(ISALIGNED((uintptr)pktdata, sizeof(uint16)));
17043 +
17044 + eh = (struct ether_header *) pktdata;
17045 +
17046 + if (ntoh16(eh->ether_type) == ETHER_TYPE_8021Q) {
17047 + uint16 vlan_tag;
17048 + int vlan_prio, dscp_prio = 0;
17049 +
17050 + evh = (struct ethervlan_header *)eh;
17051 +
17052 + vlan_tag = ntoh16(evh->vlan_tag);
17053 + vlan_prio = (int) (vlan_tag >> VLAN_PRI_SHIFT) & VLAN_PRI_MASK;
17054 +
17055 + if (ntoh16(evh->ether_type) == ETHER_TYPE_IP) {
17056 + uint8 *ip_body = pktdata + sizeof(struct ethervlan_header);
17057 + uint8 tos_tc = IP_TOS(ip_body);
17058 + dscp_prio = (int)(tos_tc >> IPV4_TOS_PREC_SHIFT);
17059 + }
17060 +
17061 + /* DSCP priority gets precedence over 802.1P (vlan tag) */
17062 + priority = (dscp_prio != 0) ? dscp_prio : vlan_prio;
17063 +
17064 + /*
17065 + * If the DSCP priority is not the same as the VLAN priority,
17066 + * then overwrite the priority field in the vlan tag, with the
17067 + * DSCP priority value. This is required for Linux APs because
17068 + * the VLAN driver on Linux, overwrites the skb->priority field
17069 + * with the priority value in the vlan tag
17070 + */
17071 + if (update_vtag && (priority != vlan_prio)) {
17072 + vlan_tag &= ~(VLAN_PRI_MASK << VLAN_PRI_SHIFT);
17073 + vlan_tag |= (uint16)priority << VLAN_PRI_SHIFT;
17074 + evh->vlan_tag = hton16(vlan_tag);
17075 + }
17076 + } else if (ntoh16(eh->ether_type) == ETHER_TYPE_IP) {
17077 + uint8 *ip_body = pktdata + sizeof(struct ether_header);
17078 + uint8 tos_tc = IP_TOS(ip_body);
17079 + priority = (int)(tos_tc >> IPV4_TOS_PREC_SHIFT);
17080 + }
17081 +
17082 + ASSERT(priority >= 0 && priority <= MAXPRIO);
17083 + PKTSETPRIO(pkt, priority);
17084 +}
17085 +
17086 +static char bcm_undeferrstr[BCME_STRLEN];
17087 +
17088 +static const char *bcmerrorstrtable[] = BCMERRSTRINGTABLE;
17089 +
17090 +/* Convert the Error codes into related Error strings */
17091 +const char *
17092 +bcmerrorstr(int bcmerror)
17093 +{
17094 + int abs_bcmerror;
17095 +
17096 + abs_bcmerror = ABS(bcmerror);
17097 +
17098 + /* check if someone added a bcmerror code but forgot to add errorstring */
17099 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(bcmerrorstrtable) - 1));
17100 + if ((bcmerror > 0) || (abs_bcmerror > ABS(BCME_LAST))) {
17101 + sprintf(bcm_undeferrstr, "undefined Error %d", bcmerror);
17102 + return bcm_undeferrstr;
17103 + }
17104 +
17105 + ASSERT((strlen((char*)bcmerrorstrtable[abs_bcmerror])) < BCME_STRLEN);
17106 +
17107 + return bcmerrorstrtable[abs_bcmerror];
17108 +}
17109 +
17110 +
17111 +int
17112 +bcm_iovar_lencheck(const bcm_iovar_t *vi, void *arg, int len, bool set)
17113 +{
17114 + int bcmerror = 0;
17115 +
17116 + /* length check on io buf */
17117 + switch (vi->type) {
17118 + case IOVT_BOOL:
17119 + case IOVT_INT8:
17120 + case IOVT_INT16:
17121 + case IOVT_INT32:
17122 + case IOVT_UINT8:
17123 + case IOVT_UINT16:
17124 + case IOVT_UINT32:
17125 + /* all integers are int32 sized args at the ioctl interface */
17126 + if (len < (int)sizeof(int)) {
17127 + bcmerror = BCME_BUFTOOSHORT;
17128 + }
17129 + break;
17130 +
17131 + case IOVT_BUFFER:
17132 + /* buffer must meet minimum length requirement */
17133 + if (len < vi->minlen) {
17134 + bcmerror = BCME_BUFTOOSHORT;
17135 + }
17136 + break;
17137 +
17138 + case IOVT_VOID:
17139 + if (!set) {
17140 + /* Cannot return nil... */
17141 + bcmerror = BCME_UNSUPPORTED;
17142 + } else if (len) {
17143 + /* Set is an action w/o parameters */
17144 + bcmerror = BCME_BUFTOOLONG;
17145 + }
17146 + break;
17147 +
17148 + default:
17149 + /* unknown type for length check in iovar info */
17150 + ASSERT(0);
17151 + bcmerror = BCME_UNSUPPORTED;
17152 + }
17153 +
17154 + return bcmerror;
17155 +}
17156 +
17157 +#define CRC_INNER_LOOP(n, c, x) \
17158 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
17159 +
17160 +static uint32 crc32_table[256] = {
17161 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
17162 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
17163 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
17164 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
17165 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
17166 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
17167 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
17168 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
17169 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
17170 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
17171 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
17172 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
17173 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
17174 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
17175 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
17176 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
17177 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
17178 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
17179 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
17180 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
17181 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
17182 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
17183 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
17184 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
17185 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
17186 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
17187 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
17188 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
17189 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
17190 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
17191 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
17192 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
17193 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
17194 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
17195 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
17196 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
17197 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
17198 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
17199 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
17200 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
17201 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
17202 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
17203 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
17204 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
17205 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
17206 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
17207 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
17208 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
17209 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
17210 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
17211 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
17212 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
17213 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
17214 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
17215 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
17216 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
17217 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
17218 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
17219 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
17220 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
17221 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
17222 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
17223 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
17224 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
17225 +};
17226 +
17227 +uint32
17228 +hndcrc32(
17229 + uint8 *pdata, /* pointer to array of data to process */
17230 + uint nbytes, /* number of input data bytes to process */
17231 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
17232 +)
17233 +{
17234 + uint8 *pend;
17235 +#ifdef __mips__
17236 + uint8 tmp[4];
17237 + ulong *tptr = (ulong *)tmp;
17238 +
17239 + /* in case the beginning of the buffer isn't aligned */
17240 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
17241 + nbytes -= (pend - pdata);
17242 + while (pdata < pend)
17243 + CRC_INNER_LOOP(32, crc, *pdata++);
17244 +
17245 + /* handle bulk of data as 32-bit words */
17246 + pend = pdata + (nbytes & 0xfffffffc);
17247 + while (pdata < pend) {
17248 + *tptr = *(ulong *)pdata;
17249 + pdata += sizeof(ulong *);
17250 + CRC_INNER_LOOP(32, crc, tmp[0]);
17251 + CRC_INNER_LOOP(32, crc, tmp[1]);
17252 + CRC_INNER_LOOP(32, crc, tmp[2]);
17253 + CRC_INNER_LOOP(32, crc, tmp[3]);
17254 + }
17255 +
17256 + /* 1-3 bytes at end of buffer */
17257 + pend = pdata + (nbytes & 0x03);
17258 + while (pdata < pend)
17259 + CRC_INNER_LOOP(32, crc, *pdata++);
17260 +#else
17261 + pend = pdata + nbytes;
17262 + while (pdata < pend)
17263 + CRC_INNER_LOOP(32, crc, *pdata++);
17264 +#endif /* __mips__ */
17265 +
17266 + return crc;
17267 +}
17268 +
17269 +
17270 +/*
17271 + * Advance from the current 1-byte tag/1-byte length/variable-length value
17272 + * triple, to the next, returning a pointer to the next.
17273 + * If the current or next TLV is invalid (does not fit in given buffer length),
17274 + * NULL is returned.
17275 + * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
17276 + * by the TLV paramter's length if it is valid.
17277 + */
17278 +bcm_tlv_t *
17279 +bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
17280 +{
17281 + int len;
17282 +
17283 + /* validate current elt */
17284 + if (!bcm_valid_tlv(elt, *buflen))
17285 + return NULL;
17286 +
17287 + /* advance to next elt */
17288 + len = elt->len;
17289 + elt = (bcm_tlv_t*)(elt->data + len);
17290 + *buflen -= (2 + len);
17291 +
17292 + /* validate next elt */
17293 + if (!bcm_valid_tlv(elt, *buflen))
17294 + return NULL;
17295 +
17296 + return elt;
17297 +}
17298 +
17299 +/*
17300 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
17301 + * triples, returning a pointer to the substring whose first element
17302 + * matches tag
17303 + */
17304 +bcm_tlv_t *
17305 +bcm_parse_tlvs(void *buf, int buflen, uint key)
17306 +{
17307 + bcm_tlv_t *elt;
17308 + int totlen;
17309 +
17310 + elt = (bcm_tlv_t*)buf;
17311 + totlen = buflen;
17312 +
17313 + /* find tagged parameter */
17314 + while (totlen >= 2) {
17315 + int len = elt->len;
17316 +
17317 + /* validate remaining totlen */
17318 + if ((elt->id == key) && (totlen >= (len + 2)))
17319 + return (elt);
17320 +
17321 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
17322 + totlen -= (len + 2);
17323 + }
17324 +
17325 + return NULL;
17326 +}
17327 +
17328 +/*
17329 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
17330 + * triples, returning a pointer to the substring whose first element
17331 + * matches tag. Stop parsing when we see an element whose ID is greater
17332 + * than the target key.
17333 + */
17334 +bcm_tlv_t *
17335 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
17336 +{
17337 + bcm_tlv_t *elt;
17338 + int totlen;
17339 +
17340 + elt = (bcm_tlv_t*)buf;
17341 + totlen = buflen;
17342 +
17343 + /* find tagged parameter */
17344 + while (totlen >= 2) {
17345 + uint id = elt->id;
17346 + int len = elt->len;
17347 +
17348 + /* Punt if we start seeing IDs > than target key */
17349 + if (id > key)
17350 + return (NULL);
17351 +
17352 + /* validate remaining totlen */
17353 + if ((id == key) && (totlen >= (len + 2)))
17354 + return (elt);
17355 +
17356 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
17357 + totlen -= (len + 2);
17358 + }
17359 + return NULL;
17360 +}
17361 +
17362 +
17363 +/* Initialization of bcmstrbuf structure */
17364 +void
17365 +bcm_binit(struct bcmstrbuf *b, char *buf, uint size)
17366 +{
17367 + b->origsize = b->size = size;
17368 + b->origbuf = b->buf = buf;
17369 +}
17370 +
17371 +/* Buffer sprintf wrapper to guard against buffer overflow */
17372 +int
17373 +bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...)
17374 +{
17375 + va_list ap;
17376 + int r;
17377 +
17378 + va_start(ap, fmt);
17379 + r = vsnprintf(b->buf, b->size, fmt, ap);
17380 +
17381 + /* Non Ansi C99 compliant returns -1,
17382 + * Ansi compliant return r >= b->size,
17383 + * bcmstdlib returns 0, handle all
17384 + */
17385 + if ((r == -1) || (r >= (int)b->size) || (r == 0))
17386 + {
17387 + b->size = 0;
17388 + }
17389 + else
17390 + {
17391 + b->size -= r;
17392 + b->buf += r;
17393 + }
17394 +
17395 + va_end(ap);
17396 +
17397 + return r;
17398 +}
17399 diff -urN linux.old/drivers/net/wl/hnddma.c linux.dev/drivers/net/wl/hnddma.c
17400 --- linux.old/drivers/net/wl/hnddma.c 1970-01-01 01:00:00.000000000 +0100
17401 +++ linux.dev/drivers/net/wl/hnddma.c 2006-05-02 17:42:13.000000000 +0200
17402 @@ -0,0 +1,1157 @@
17403 +/*
17404 + * Generic Broadcom Home Networking Division (HND) DMA module.
17405 + * This supports the following chips: BCM42xx, 44xx, 47xx .
17406 + *
17407 + * Copyright 2006, Broadcom Corporation
17408 + * All Rights Reserved.
17409 + *
17410 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
17411 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
17412 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
17413 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
17414 + *
17415 + * $Id: hnddma.c,v 1.11 2006/04/08 07:12:42 honor Exp $
17416 + */
17417 +
17418 +#include <typedefs.h>
17419 +#include <bcmdefs.h>
17420 +#include <osl.h>
17421 +#include "linux_osl.h"
17422 +#include <bcmendian.h>
17423 +#include <sbconfig.h>
17424 +#include <bcmutils.h>
17425 +#include <bcmdevs.h>
17426 +#include <sbutils.h>
17427 +
17428 +#include "sbhnddma.h"
17429 +#include "hnddma.h"
17430 +
17431 +/* debug/trace */
17432 +#define DMA_ERROR(args)
17433 +#define DMA_TRACE(args)
17434 +
17435 +/* default dma message level (if input msg_level pointer is null in dma_attach()) */
17436 +static uint dma_msg_level =
17437 + 0;
17438 +
17439 +#define MAXNAMEL 8 /* 8 char names */
17440 +
17441 +#define DI_INFO(dmah) (dma_info_t *)dmah
17442 +
17443 +/* dma engine software state */
17444 +typedef struct dma_info {
17445 + struct hnddma_pub hnddma; /* exported structure, don't use hnddma_t,
17446 + * which could be const
17447 + */
17448 + uint *msg_level; /* message level pointer */
17449 + char name[MAXNAMEL]; /* callers name for diag msgs */
17450 +
17451 + void *osh; /* os handle */
17452 + sb_t *sbh; /* sb handle */
17453 +
17454 + bool dma64; /* dma64 enabled */
17455 + bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
17456 +
17457 + dma32regs_t *d32txregs; /* 32 bits dma tx engine registers */
17458 + dma32regs_t *d32rxregs; /* 32 bits dma rx engine registers */
17459 + dma64regs_t *d64txregs; /* 64 bits dma tx engine registers */
17460 + dma64regs_t *d64rxregs; /* 64 bits dma rx engine registers */
17461 +
17462 + uint32 dma64align; /* either 8k or 4k depends on number of dd */
17463 + dma32dd_t *txd32; /* pointer to dma32 tx descriptor ring */
17464 + dma64dd_t *txd64; /* pointer to dma64 tx descriptor ring */
17465 + uint ntxd; /* # tx descriptors tunable */
17466 + uint txin; /* index of next descriptor to reclaim */
17467 + uint txout; /* index of next descriptor to post */
17468 + void **txp; /* pointer to parallel array of pointers to packets */
17469 + osldma_t *tx_dmah; /* DMA TX descriptor ring handle */
17470 + osldma_t **txp_dmah; /* DMA TX packet data handle */
17471 + ulong txdpa; /* physical address of descriptor ring */
17472 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
17473 + uint txdalloc; /* #bytes allocated for the ring */
17474 +
17475 + dma32dd_t *rxd32; /* pointer to dma32 rx descriptor ring */
17476 + dma64dd_t *rxd64; /* pointer to dma64 rx descriptor ring */
17477 + uint nrxd; /* # rx descriptors tunable */
17478 + uint rxin; /* index of next descriptor to reclaim */
17479 + uint rxout; /* index of next descriptor to post */
17480 + void **rxp; /* pointer to parallel array of pointers to packets */
17481 + osldma_t *rx_dmah; /* DMA RX descriptor ring handle */
17482 + osldma_t **rxp_dmah; /* DMA RX packet data handle */
17483 + ulong rxdpa; /* physical address of descriptor ring */
17484 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
17485 + uint rxdalloc; /* #bytes allocated for the ring */
17486 +
17487 + /* tunables */
17488 + uint rxbufsize; /* rx buffer size in bytes,
17489 + not including the extra headroom
17490 + */
17491 + uint nrxpost; /* # rx buffers to keep posted */
17492 + uint rxoffset; /* rxcontrol offset */
17493 + uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
17494 + uint ddoffsethigh; /* high 32 bits */
17495 + uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
17496 + uint dataoffsethigh; /* high 32 bits */
17497 +} dma_info_t;
17498 +
17499 +/* descriptor bumping macros */
17500 +#define XXD(x, n) ((x) & ((n) - 1)) /* faster than %, but n must be power of 2 */
17501 +#define TXD(x) XXD((x), di->ntxd)
17502 +#define RXD(x) XXD((x), di->nrxd)
17503 +#define NEXTTXD(i) TXD(i + 1)
17504 +#define PREVTXD(i) TXD(i - 1)
17505 +#define NEXTRXD(i) RXD(i + 1)
17506 +#define NTXDACTIVE(h, t) TXD(t - h)
17507 +#define NRXDACTIVE(h, t) RXD(t - h)
17508 +
17509 +/* macros to convert between byte offsets and indexes */
17510 +#define B2I(bytes, type) ((bytes) / sizeof(type))
17511 +#define I2B(index, type) ((index) * sizeof(type))
17512 +
17513 +#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
17514 +#define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
17515 +
17516 +
17517 +/* common prototypes */
17518 +static bool _dma_isaddrext(dma_info_t *di);
17519 +static bool dma32_alloc(dma_info_t *di, uint direction);
17520 +static void _dma_detach(dma_info_t *di);
17521 +static void _dma_ddtable_init(dma_info_t *di, uint direction, ulong pa);
17522 +static void _dma_rxinit(dma_info_t *di);
17523 +static void *_dma_rx(dma_info_t *di);
17524 +static void _dma_rxfill(dma_info_t *di);
17525 +static void _dma_rxreclaim(dma_info_t *di);
17526 +static void _dma_rxenable(dma_info_t *di);
17527 +static void * _dma_getnextrxp(dma_info_t *di, bool forceall);
17528 +
17529 +static void _dma_txblock(dma_info_t *di);
17530 +static void _dma_txunblock(dma_info_t *di);
17531 +static uint _dma_txactive(dma_info_t *di);
17532 +
17533 +static void* _dma_peeknexttxp(dma_info_t *di);
17534 +static uintptr _dma_getvar(dma_info_t *di, char *name);
17535 +static void _dma_counterreset(dma_info_t *di);
17536 +static void _dma_fifoloopbackenable(dma_info_t *di);
17537 +
17538 +/* ** 32 bit DMA prototypes */
17539 +static bool dma32_alloc(dma_info_t *di, uint direction);
17540 +static bool dma32_txreset(dma_info_t *di);
17541 +static bool dma32_rxreset(dma_info_t *di);
17542 +static bool dma32_txsuspendedidle(dma_info_t *di);
17543 +static int dma32_txfast(dma_info_t *di, void *p0, bool commit);
17544 +static void *dma32_getnexttxp(dma_info_t *di, bool forceall);
17545 +static void *dma32_getnextrxp(dma_info_t *di, bool forceall);
17546 +static void dma32_txrotate(dma_info_t *di);
17547 +static bool dma32_rxidle(dma_info_t *di);
17548 +static void dma32_txinit(dma_info_t *di);
17549 +static bool dma32_txenabled(dma_info_t *di);
17550 +static void dma32_txsuspend(dma_info_t *di);
17551 +static void dma32_txresume(dma_info_t *di);
17552 +static bool dma32_txsuspended(dma_info_t *di);
17553 +static void dma32_txreclaim(dma_info_t *di, bool forceall);
17554 +static bool dma32_txstopped(dma_info_t *di);
17555 +static bool dma32_rxstopped(dma_info_t *di);
17556 +static bool dma32_rxenabled(dma_info_t *di);
17557 +static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs);
17558 +
17559 +
17560 +static di_fcn_t dma32proc = {
17561 + (di_detach_t)_dma_detach,
17562 + (di_txinit_t)dma32_txinit,
17563 + (di_txreset_t)dma32_txreset,
17564 + (di_txenabled_t)dma32_txenabled,
17565 + (di_txsuspend_t)dma32_txsuspend,
17566 + (di_txresume_t)dma32_txresume,
17567 + (di_txsuspended_t)dma32_txsuspended,
17568 + (di_txsuspendedidle_t)dma32_txsuspendedidle,
17569 + (di_txfast_t)dma32_txfast,
17570 + (di_txstopped_t)dma32_txstopped,
17571 + (di_txreclaim_t)dma32_txreclaim,
17572 + (di_getnexttxp_t)dma32_getnexttxp,
17573 + (di_peeknexttxp_t)_dma_peeknexttxp,
17574 + (di_txblock_t)_dma_txblock,
17575 + (di_txunblock_t)_dma_txunblock,
17576 + (di_txactive_t)_dma_txactive,
17577 + (di_txrotate_t)dma32_txrotate,
17578 +
17579 + (di_rxinit_t)_dma_rxinit,
17580 + (di_rxreset_t)dma32_rxreset,
17581 + (di_rxidle_t)dma32_rxidle,
17582 + (di_rxstopped_t)dma32_rxstopped,
17583 + (di_rxenable_t)_dma_rxenable,
17584 + (di_rxenabled_t)dma32_rxenabled,
17585 + (di_rx_t)_dma_rx,
17586 + (di_rxfill_t)_dma_rxfill,
17587 + (di_rxreclaim_t)_dma_rxreclaim,
17588 + (di_getnextrxp_t)_dma_getnextrxp,
17589 +
17590 + (di_fifoloopbackenable_t)_dma_fifoloopbackenable,
17591 + (di_getvar_t)_dma_getvar,
17592 + (di_counterreset_t)_dma_counterreset,
17593 +
17594 + NULL,
17595 + NULL,
17596 + NULL,
17597 + 34
17598 +};
17599 +
17600 +hnddma_t *
17601 +dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
17602 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level)
17603 +{
17604 + dma_info_t *di;
17605 + uint size;
17606 +
17607 + /* allocate private info structure */
17608 + if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
17609 + return (NULL);
17610 + }
17611 + bzero((char *)di, sizeof(dma_info_t));
17612 +
17613 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
17614 +
17615 + /* old chips w/o sb is no longer supported */
17616 + ASSERT(sbh != NULL);
17617 +
17618 + /* check arguments */
17619 + ASSERT(ISPOWEROF2(ntxd));
17620 + ASSERT(ISPOWEROF2(nrxd));
17621 + if (nrxd == 0)
17622 + ASSERT(dmaregsrx == NULL);
17623 + if (ntxd == 0)
17624 + ASSERT(dmaregstx == NULL);
17625 +
17626 +
17627 + /* init dma reg pointer */
17628 + ASSERT(ntxd <= D32MAXDD);
17629 + ASSERT(nrxd <= D32MAXDD);
17630 + di->d32txregs = (dma32regs_t *)dmaregstx;
17631 + di->d32rxregs = (dma32regs_t *)dmaregsrx;
17632 +
17633 + DMA_TRACE(("%s: dma_attach: %s osh %p ntxd %d nrxd %d rxbufsize %d nrxpost %d "
17634 + "rxoffset %d dmaregstx %p dmaregsrx %p\n",
17635 + name, "DMA32", osh, ntxd, nrxd, rxbufsize,
17636 + nrxpost, rxoffset, dmaregstx, dmaregsrx));
17637 +
17638 + /* make a private copy of our callers name */
17639 + strncpy(di->name, name, MAXNAMEL);
17640 + di->name[MAXNAMEL-1] = '\0';
17641 +
17642 + di->osh = osh;
17643 + di->sbh = sbh;
17644 +
17645 + /* save tunables */
17646 + di->ntxd = ntxd;
17647 + di->nrxd = nrxd;
17648 +
17649 + /* the actual dma size doesn't include the extra headroom */
17650 + if (rxbufsize > BCMEXTRAHDROOM)
17651 + di->rxbufsize = rxbufsize - BCMEXTRAHDROOM;
17652 + else
17653 + di->rxbufsize = rxbufsize;
17654 +
17655 + di->nrxpost = nrxpost;
17656 + di->rxoffset = rxoffset;
17657 +
17658 + /*
17659 + * figure out the DMA physical address offset for dd and data
17660 + * for old chips w/o sb, use zero
17661 + * for new chips w sb,
17662 + * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
17663 + * Other bus: use zero
17664 + * SB_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
17665 + */
17666 + di->ddoffsetlow = 0;
17667 + di->dataoffsetlow = 0;
17668 + /* for pci bus, add offset */
17669 + if (sbh->bustype == PCI_BUS) {
17670 + di->ddoffsetlow = SB_PCI_DMA;
17671 + di->ddoffsethigh = 0;
17672 + di->dataoffsetlow = di->ddoffsetlow;
17673 + di->dataoffsethigh = di->ddoffsethigh;
17674 + }
17675 +
17676 +#if defined(__mips__) && defined(IL_BIGENDIAN)
17677 + di->dataoffsetlow = di->dataoffsetlow + SB_SDRAM_SWAPPED;
17678 +#endif
17679 +
17680 + di->addrext = _dma_isaddrext(di);
17681 +
17682 + /* allocate tx packet pointer vector */
17683 + if (ntxd) {
17684 + size = ntxd * sizeof(void *);
17685 + if ((di->txp = MALLOC(osh, size)) == NULL) {
17686 + DMA_ERROR(("%s: dma_attach: out of tx memory, malloced %d bytes\n",
17687 + di->name, MALLOCED(osh)));
17688 + goto fail;
17689 + }
17690 + bzero((char *)di->txp, size);
17691 + }
17692 +
17693 + /* allocate rx packet pointer vector */
17694 + if (nrxd) {
17695 + size = nrxd * sizeof(void *);
17696 + if ((di->rxp = MALLOC(osh, size)) == NULL) {
17697 + DMA_ERROR(("%s: dma_attach: out of rx memory, malloced %d bytes\n",
17698 + di->name, MALLOCED(osh)));
17699 + goto fail;
17700 + }
17701 + bzero((char *)di->rxp, size);
17702 + }
17703 +
17704 + /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
17705 + if (ntxd) {
17706 + if (!dma32_alloc(di, DMA_TX))
17707 + goto fail;
17708 + }
17709 +
17710 + /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
17711 + if (nrxd) {
17712 + if (!dma32_alloc(di, DMA_RX))
17713 + goto fail;
17714 + }
17715 +
17716 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->txdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17717 + DMA_ERROR(("%s: dma_attach: txdpa 0x%lx: addrext not supported\n",
17718 + di->name, di->txdpa));
17719 + goto fail;
17720 + }
17721 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->rxdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17722 + DMA_ERROR(("%s: dma_attach: rxdpa 0x%lx: addrext not supported\n",
17723 + di->name, di->rxdpa));
17724 + goto fail;
17725 + }
17726 +
17727 + DMA_TRACE(("ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x dataoffsethigh "
17728 + "0x%x addrext %d\n", di->ddoffsetlow, di->ddoffsethigh, di->dataoffsetlow,
17729 + di->dataoffsethigh, di->addrext));
17730 +
17731 + /* allocate tx packet pointer vector and DMA mapping vectors */
17732 + if (ntxd) {
17733 +
17734 + size = ntxd * sizeof(osldma_t **);
17735 + if ((di->txp_dmah = (osldma_t **)MALLOC(osh, size)) == NULL)
17736 + goto fail;
17737 + bzero((char*)di->txp_dmah, size);
17738 + }else
17739 + di->txp_dmah = NULL;
17740 +
17741 + /* allocate rx packet pointer vector and DMA mapping vectors */
17742 + if (nrxd) {
17743 +
17744 + size = nrxd * sizeof(osldma_t **);
17745 + if ((di->rxp_dmah = (osldma_t **)MALLOC(osh, size)) == NULL)
17746 + goto fail;
17747 + bzero((char*)di->rxp_dmah, size);
17748 +
17749 + } else
17750 + di->rxp_dmah = NULL;
17751 +
17752 + /* initialize opsvec of function pointers */
17753 + di->hnddma.di_fn = dma32proc;
17754 +
17755 + return ((hnddma_t *)di);
17756 +
17757 +fail:
17758 + _dma_detach(di);
17759 + return (NULL);
17760 +}
17761 +
17762 +/* init the tx or rx descriptor */
17763 +static INLINE void
17764 +dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, ulong pa, uint outidx, uint32 *flags,
17765 + uint32 bufcount)
17766 +{
17767 + /* dma32 uses 32 bits control to fit both flags and bufcounter */
17768 + *flags = *flags | (bufcount & CTRL_BC_MASK);
17769 +
17770 + if ((di->dataoffsetlow != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17771 + W_SM(&ddring[outidx].addr, BUS_SWAP32(pa + di->dataoffsetlow));
17772 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags));
17773 + } else {
17774 + /* address extension */
17775 + uint32 ae;
17776 + ASSERT(di->addrext);
17777 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17778 + pa &= ~PCI32ADDR_HIGH;
17779 +
17780 + *flags |= (ae << CTRL_AE_SHIFT);
17781 + W_SM(&ddring[outidx].addr, BUS_SWAP32(pa + di->dataoffsetlow));
17782 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags));
17783 + }
17784 +}
17785 +
17786 +static bool
17787 +_dma32_addrext(osl_t *osh, dma32regs_t *dma32regs)
17788 +{
17789 + uint32 w;
17790 +
17791 + OR_REG(osh, &dma32regs->control, XC_AE);
17792 + w = R_REG(osh, &dma32regs->control);
17793 + AND_REG(osh, &dma32regs->control, ~XC_AE);
17794 + return ((w & XC_AE) == XC_AE);
17795 +}
17796 +
17797 +/* !! may be called with core in reset */
17798 +static void
17799 +_dma_detach(dma_info_t *di)
17800 +{
17801 + if (di == NULL)
17802 + return;
17803 +
17804 + DMA_TRACE(("%s: dma_detach\n", di->name));
17805 +
17806 + /* shouldn't be here if descriptors are unreclaimed */
17807 + ASSERT(di->txin == di->txout);
17808 + ASSERT(di->rxin == di->rxout);
17809 +
17810 + /* free dma descriptor rings */
17811 + if (di->txd32)
17812 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd32 - di->txdalign),
17813 + di->txdalloc, (di->txdpa - di->txdalign), &di->tx_dmah);
17814 + if (di->rxd32)
17815 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd32 - di->rxdalign),
17816 + di->rxdalloc, (di->rxdpa - di->rxdalign), &di->rx_dmah);
17817 +
17818 + /* free packet pointer vectors */
17819 + if (di->txp)
17820 + MFREE(di->osh, (void *)di->txp, (di->ntxd * sizeof(void *)));
17821 + if (di->rxp)
17822 + MFREE(di->osh, (void *)di->rxp, (di->nrxd * sizeof(void *)));
17823 +
17824 + /* free tx packet DMA handles */
17825 + if (di->txp_dmah)
17826 + MFREE(di->osh, (void *)di->txp_dmah, di->ntxd * sizeof(osldma_t **));
17827 +
17828 + /* free rx packet DMA handles */
17829 + if (di->rxp_dmah)
17830 + MFREE(di->osh, (void *)di->rxp_dmah, di->nrxd * sizeof(osldma_t **));
17831 +
17832 + /* free our private info structure */
17833 + MFREE(di->osh, (void *)di, sizeof(dma_info_t));
17834 +
17835 +}
17836 +
17837 +/* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
17838 +static bool
17839 +_dma_isaddrext(dma_info_t *di)
17840 +{
17841 + if (di->d32txregs)
17842 + return (_dma32_addrext(di->osh, di->d32txregs));
17843 + else if (di->d32rxregs)
17844 + return (_dma32_addrext(di->osh, di->d32rxregs));
17845 + return FALSE;
17846 +}
17847 +
17848 +/* initialize descriptor table base address */
17849 +static void
17850 +_dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
17851 +{
17852 + if ((di->ddoffsetlow != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17853 + if (direction == DMA_TX)
17854 + W_REG(di->osh, &di->d32txregs->addr, (pa + di->ddoffsetlow));
17855 + else
17856 + W_REG(di->osh, &di->d32rxregs->addr, (pa + di->ddoffsetlow));
17857 + } else {
17858 + /* dma32 address extension */
17859 + uint32 ae;
17860 + ASSERT(di->addrext);
17861 +
17862 + /* shift the high bit(s) from pa to ae */
17863 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17864 + pa &= ~PCI32ADDR_HIGH;
17865 +
17866 + if (direction == DMA_TX) {
17867 + W_REG(di->osh, &di->d32txregs->addr, (pa + di->ddoffsetlow));
17868 + SET_REG(di->osh, &di->d32txregs->control, XC_AE, ae <<XC_AE_SHIFT);
17869 + } else {
17870 + W_REG(di->osh, &di->d32rxregs->addr, (pa + di->ddoffsetlow));
17871 + SET_REG(di->osh, &di->d32rxregs->control, RC_AE, ae <<RC_AE_SHIFT);
17872 + }
17873 + }
17874 +}
17875 +
17876 +static void
17877 +_dma_fifoloopbackenable(dma_info_t *di)
17878 +{
17879 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
17880 + OR_REG(di->osh, &di->d32txregs->control, XC_LE);
17881 +}
17882 +
17883 +static void
17884 +_dma_rxinit(dma_info_t *di)
17885 +{
17886 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
17887 +
17888 + if (di->nrxd == 0)
17889 + return;
17890 +
17891 + di->rxin = di->rxout = 0;
17892 +
17893 + /* clear rx descriptor ring */
17894 + BZERO_SM((void *)di->rxd32, (di->nrxd * sizeof(dma32dd_t)));
17895 + _dma_rxenable(di);
17896 + _dma_ddtable_init(di, DMA_RX, di->rxdpa);
17897 +}
17898 +
17899 +static void
17900 +_dma_rxenable(dma_info_t *di)
17901 +{
17902 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
17903 +
17904 + W_REG(di->osh, &di->d32rxregs->control, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
17905 +}
17906 +
17907 +/* !! rx entry routine, returns a pointer to the next frame received,
17908 + * or NULL if there are no more
17909 + */
17910 +static void *
17911 +_dma_rx(dma_info_t *di)
17912 +{
17913 + void *p;
17914 + uint len;
17915 + int skiplen = 0;
17916 +
17917 + while ((p = _dma_getnextrxp(di, FALSE))) {
17918 + /* skip giant packets which span multiple rx descriptors */
17919 + if (skiplen > 0) {
17920 + skiplen -= di->rxbufsize;
17921 + if (skiplen < 0)
17922 + skiplen = 0;
17923 + PKTFREE(di->osh, p, FALSE);
17924 + continue;
17925 + }
17926 +
17927 + len = ltoh16(*(uint16*)(PKTDATA(di->osh, p)));
17928 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
17929 +
17930 + /* bad frame length check */
17931 + if (len > (di->rxbufsize - di->rxoffset)) {
17932 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
17933 + if (len > 0)
17934 + skiplen = len - (di->rxbufsize - di->rxoffset);
17935 + PKTFREE(di->osh, p, FALSE);
17936 + di->hnddma.rxgiants++;
17937 + continue;
17938 + }
17939 +
17940 + /* set actual length */
17941 + PKTSETLEN(di->osh, p, (di->rxoffset + len));
17942 +
17943 + break;
17944 + }
17945 +
17946 + return (p);
17947 +}
17948 +
17949 +/* post receive buffers */
17950 +static void
17951 +_dma_rxfill(dma_info_t *di)
17952 +{
17953 + void *p;
17954 + uint rxin, rxout;
17955 + uint32 flags = 0;
17956 + uint n;
17957 + uint i;
17958 + uint32 pa;
17959 + uint extra_offset = 0;
17960 +
17961 + /*
17962 + * Determine how many receive buffers we're lacking
17963 + * from the full complement, allocate, initialize,
17964 + * and post them, then update the chip rx lastdscr.
17965 + */
17966 +
17967 + rxin = di->rxin;
17968 + rxout = di->rxout;
17969 +
17970 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
17971 +
17972 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
17973 +
17974 + if (di->rxbufsize > BCMEXTRAHDROOM)
17975 + extra_offset = BCMEXTRAHDROOM;
17976 +
17977 + for (i = 0; i < n; i++) {
17978 + /* the di->rxbufsize doesn't include the extra headroom, we need to add it to the
17979 + size to be allocated
17980 + */
17981 + if ((p = PKTGET(di->osh, di->rxbufsize + extra_offset,
17982 + FALSE)) == NULL) {
17983 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
17984 + di->hnddma.rxnobuf++;
17985 + break;
17986 + }
17987 + /* reserve an extra headroom, if applicable */
17988 + if (extra_offset)
17989 + PKTPULL(di->osh, p, extra_offset);
17990 +
17991 + /* Do a cached write instead of uncached write since DMA_MAP
17992 + * will flush the cache.
17993 + */
17994 + *(uint32*)(PKTDATA(di->osh, p)) = 0;
17995 +
17996 + pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->osh, p),
17997 + di->rxbufsize, DMA_RX, p);
17998 +
17999 + ASSERT(ISALIGNED(pa, 4));
18000 +
18001 + /* save the free packet pointer */
18002 + ASSERT(di->rxp[rxout] == NULL);
18003 + di->rxp[rxout] = p;
18004 +
18005 + /* reset flags for each descriptor */
18006 + flags = 0;
18007 + if (rxout == (di->nrxd - 1))
18008 + flags = CTRL_EOT;
18009 + dma32_dd_upd(di, di->rxd32, pa, rxout, &flags, di->rxbufsize);
18010 + rxout = NEXTRXD(rxout);
18011 + }
18012 +
18013 + di->rxout = rxout;
18014 +
18015 + /* update the chip lastdscr pointer */
18016 + W_REG(di->osh, &di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
18017 +}
18018 +
18019 +/* like getnexttxp but no reclaim */
18020 +static void *
18021 +_dma_peeknexttxp(dma_info_t *di)
18022 +{
18023 + uint end, i;
18024 +
18025 + if (di->ntxd == 0)
18026 + return (NULL);
18027 +
18028 + end = B2I(R_REG(di->osh, &di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
18029 +
18030 + for (i = di->txin; i != end; i = NEXTTXD(i))
18031 + if (di->txp[i])
18032 + return (di->txp[i]);
18033 +
18034 + return (NULL);
18035 +}
18036 +
18037 +static void
18038 +_dma_rxreclaim(dma_info_t *di)
18039 +{
18040 + void *p;
18041 +
18042 + /* "unused local" warning suppression for OSLs that
18043 + * define PKTFREE() without using the di->osh arg
18044 + */
18045 + di = di;
18046 +
18047 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
18048 +
18049 + while ((p = _dma_getnextrxp(di, TRUE)))
18050 + PKTFREE(di->osh, p, FALSE);
18051 +}
18052 +
18053 +static void *
18054 +_dma_getnextrxp(dma_info_t *di, bool forceall)
18055 +{
18056 + if (di->nrxd == 0)
18057 + return (NULL);
18058 +
18059 + return dma32_getnextrxp(di, forceall);
18060 +}
18061 +
18062 +static void
18063 +_dma_txblock(dma_info_t *di)
18064 +{
18065 + di->hnddma.txavail = 0;
18066 +}
18067 +
18068 +static void
18069 +_dma_txunblock(dma_info_t *di)
18070 +{
18071 + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18072 +}
18073 +
18074 +static uint
18075 +_dma_txactive(dma_info_t *di)
18076 +{
18077 + return (NTXDACTIVE(di->txin, di->txout));
18078 +}
18079 +
18080 +static void
18081 +_dma_counterreset(dma_info_t *di)
18082 +{
18083 + /* reset all software counter */
18084 + di->hnddma.rxgiants = 0;
18085 + di->hnddma.rxnobuf = 0;
18086 + di->hnddma.txnobuf = 0;
18087 +}
18088 +
18089 +/* get the address of the var in order to change later */
18090 +static uintptr
18091 +_dma_getvar(dma_info_t *di, char *name)
18092 +{
18093 + if (!strcmp(name, "&txavail"))
18094 + return ((uintptr) &(di->hnddma.txavail));
18095 + else {
18096 + ASSERT(0);
18097 + }
18098 + return (0);
18099 +}
18100 +
18101 +void
18102 +dma_txpioloopback(osl_t *osh, dma32regs_t *regs)
18103 +{
18104 + OR_REG(osh, &regs->control, XC_LE);
18105 +}
18106 +
18107 +
18108 +
18109 +/* 32 bits DMA functions */
18110 +static void
18111 +dma32_txinit(dma_info_t *di)
18112 +{
18113 + DMA_TRACE(("%s: dma_txinit\n", di->name));
18114 +
18115 + if (di->ntxd == 0)
18116 + return;
18117 +
18118 + di->txin = di->txout = 0;
18119 + di->hnddma.txavail = di->ntxd - 1;
18120 +
18121 + /* clear tx descriptor ring */
18122 + BZERO_SM((void *)di->txd32, (di->ntxd * sizeof(dma32dd_t)));
18123 + W_REG(di->osh, &di->d32txregs->control, XC_XE);
18124 + _dma_ddtable_init(di, DMA_TX, di->txdpa);
18125 +}
18126 +
18127 +static bool
18128 +dma32_txenabled(dma_info_t *di)
18129 +{
18130 + uint32 xc;
18131 +
18132 + /* If the chip is dead, it is not enabled :-) */
18133 + xc = R_REG(di->osh, &di->d32txregs->control);
18134 + return ((xc != 0xffffffff) && (xc & XC_XE));
18135 +}
18136 +
18137 +static void
18138 +dma32_txsuspend(dma_info_t *di)
18139 +{
18140 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
18141 +
18142 + if (di->ntxd == 0)
18143 + return;
18144 +
18145 + OR_REG(di->osh, &di->d32txregs->control, XC_SE);
18146 +}
18147 +
18148 +static void
18149 +dma32_txresume(dma_info_t *di)
18150 +{
18151 + DMA_TRACE(("%s: dma_txresume\n", di->name));
18152 +
18153 + if (di->ntxd == 0)
18154 + return;
18155 +
18156 + AND_REG(di->osh, &di->d32txregs->control, ~XC_SE);
18157 +}
18158 +
18159 +static bool
18160 +dma32_txsuspended(dma_info_t *di)
18161 +{
18162 + return (di->ntxd == 0) || ((R_REG(di->osh, &di->d32txregs->control) & XC_SE) == XC_SE);
18163 +}
18164 +
18165 +static void
18166 +dma32_txreclaim(dma_info_t *di, bool forceall)
18167 +{
18168 + void *p;
18169 +
18170 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
18171 +
18172 + while ((p = dma32_getnexttxp(di, forceall)))
18173 + PKTFREE(di->osh, p, TRUE);
18174 +}
18175 +
18176 +static bool
18177 +dma32_txstopped(dma_info_t *di)
18178 +{
18179 + return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) == XS_XS_STOPPED);
18180 +}
18181 +
18182 +static bool
18183 +dma32_rxstopped(dma_info_t *di)
18184 +{
18185 + return ((R_REG(di->osh, &di->d32rxregs->status) & RS_RS_MASK) == RS_RS_STOPPED);
18186 +}
18187 +
18188 +static bool
18189 +dma32_alloc(dma_info_t *di, uint direction)
18190 +{
18191 + uint size;
18192 + uint ddlen;
18193 + void *va;
18194 +
18195 + ddlen = sizeof(dma32dd_t);
18196 +
18197 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
18198 +
18199 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, D32RINGALIGN))
18200 + size += D32RINGALIGN;
18201 +
18202 +
18203 + if (direction == DMA_TX) {
18204 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa, &di->tx_dmah)) == NULL) {
18205 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n",
18206 + di->name));
18207 + return FALSE;
18208 + }
18209 +
18210 + di->txd32 = (dma32dd_t *) ROUNDUP((uintptr)va, D32RINGALIGN);
18211 + di->txdalign = (uint)((int8*)di->txd32 - (int8*)va);
18212 + di->txdpa += di->txdalign;
18213 + di->txdalloc = size;
18214 + ASSERT(ISALIGNED((uintptr)di->txd32, D32RINGALIGN));
18215 + } else {
18216 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa, &di->rx_dmah)) == NULL) {
18217 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n",
18218 + di->name));
18219 + return FALSE;
18220 + }
18221 + di->rxd32 = (dma32dd_t *) ROUNDUP((uintptr)va, D32RINGALIGN);
18222 + di->rxdalign = (uint)((int8*)di->rxd32 - (int8*)va);
18223 + di->rxdpa += di->rxdalign;
18224 + di->rxdalloc = size;
18225 + ASSERT(ISALIGNED((uintptr)di->rxd32, D32RINGALIGN));
18226 + }
18227 +
18228 + return TRUE;
18229 +}
18230 +
18231 +static bool
18232 +dma32_txreset(dma_info_t *di)
18233 +{
18234 + uint32 status;
18235 +
18236 + if (di->ntxd == 0)
18237 + return TRUE;
18238 +
18239 + /* suspend tx DMA first */
18240 + W_REG(di->osh, &di->d32txregs->control, XC_SE);
18241 + SPINWAIT(((status = (R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK))
18242 + != XS_XS_DISABLED) &&
18243 + (status != XS_XS_IDLE) &&
18244 + (status != XS_XS_STOPPED),
18245 + (10000));
18246 +
18247 + W_REG(di->osh, &di->d32txregs->control, 0);
18248 + SPINWAIT(((status = (R_REG(di->osh,
18249 + &di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED),
18250 + 10000);
18251 +
18252 + /* wait for the last transaction to complete */
18253 + OSL_DELAY(300);
18254 +
18255 + return (status == XS_XS_DISABLED);
18256 +}
18257 +
18258 +static bool
18259 +dma32_rxidle(dma_info_t *di)
18260 +{
18261 + DMA_TRACE(("%s: dma_rxidle\n", di->name));
18262 +
18263 + if (di->nrxd == 0)
18264 + return TRUE;
18265 +
18266 + return ((R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK) ==
18267 + R_REG(di->osh, &di->d32rxregs->ptr));
18268 +}
18269 +
18270 +static bool
18271 +dma32_rxreset(dma_info_t *di)
18272 +{
18273 + uint32 status;
18274 +
18275 + if (di->nrxd == 0)
18276 + return TRUE;
18277 +
18278 + W_REG(di->osh, &di->d32rxregs->control, 0);
18279 + SPINWAIT(((status = (R_REG(di->osh,
18280 + &di->d32rxregs->status) & RS_RS_MASK)) != RS_RS_DISABLED),
18281 + 10000);
18282 +
18283 + return (status == RS_RS_DISABLED);
18284 +}
18285 +
18286 +static bool
18287 +dma32_rxenabled(dma_info_t *di)
18288 +{
18289 + uint32 rc;
18290 +
18291 + rc = R_REG(di->osh, &di->d32rxregs->control);
18292 + return ((rc != 0xffffffff) && (rc & RC_RE));
18293 +}
18294 +
18295 +static bool
18296 +dma32_txsuspendedidle(dma_info_t *di)
18297 +{
18298 + if (di->ntxd == 0)
18299 + return TRUE;
18300 +
18301 + if (!(R_REG(di->osh, &di->d32txregs->control) & XC_SE))
18302 + return 0;
18303 +
18304 + if ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
18305 + return 0;
18306 +
18307 + OSL_DELAY(2);
18308 + return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) == XS_XS_IDLE);
18309 +}
18310 +
18311 +/* !! tx entry routine
18312 + * supports full 32bit dma engine buffer addressing so
18313 + * dma buffers can cross 4 Kbyte page boundaries.
18314 + */
18315 +static int
18316 +dma32_txfast(dma_info_t *di, void *p0, bool commit)
18317 +{
18318 + void *p, *next;
18319 + uchar *data;
18320 + uint len;
18321 + uint txout;
18322 + uint32 flags = 0;
18323 + uint32 pa;
18324 +
18325 + DMA_TRACE(("%s: dma_txfast\n", di->name));
18326 +
18327 + txout = di->txout;
18328 +
18329 + /*
18330 + * Walk the chain of packet buffers
18331 + * allocating and initializing transmit descriptor entries.
18332 + */
18333 + for (p = p0; p; p = next) {
18334 + data = PKTDATA(di->osh, p);
18335 + len = PKTLEN(di->osh, p);
18336 + next = PKTNEXT(di->osh, p);
18337 +
18338 + /* return nonzero if out of tx descriptors */
18339 + if (NEXTTXD(txout) == di->txin)
18340 + goto outoftxd;
18341 +
18342 + if (len == 0)
18343 + continue;
18344 +
18345 + /* get physical address of buffer start */
18346 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
18347 +
18348 + flags = 0;
18349 + if (p == p0)
18350 + flags |= CTRL_SOF;
18351 + if (next == NULL)
18352 + flags |= (CTRL_IOC | CTRL_EOF);
18353 + if (txout == (di->ntxd - 1))
18354 + flags |= CTRL_EOT;
18355 +
18356 + dma32_dd_upd(di, di->txd32, pa, txout, &flags, len);
18357 + ASSERT(di->txp[txout] == NULL);
18358 +
18359 + txout = NEXTTXD(txout);
18360 + }
18361 +
18362 + /* if last txd eof not set, fix it */
18363 + if (!(flags & CTRL_EOF))
18364 + W_SM(&di->txd32[PREVTXD(txout)].ctrl, BUS_SWAP32(flags | CTRL_IOC | CTRL_EOF));
18365 +
18366 + /* save the packet */
18367 + di->txp[PREVTXD(txout)] = p0;
18368 +
18369 + /* bump the tx descriptor index */
18370 + di->txout = txout;
18371 +
18372 + /* kick the chip */
18373 + if (commit)
18374 + W_REG(di->osh, &di->d32txregs->ptr, I2B(txout, dma32dd_t));
18375 +
18376 + /* tx flow control */
18377 + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18378 +
18379 + return (0);
18380 +
18381 +outoftxd:
18382 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
18383 + PKTFREE(di->osh, p0, TRUE);
18384 + di->hnddma.txavail = 0;
18385 + di->hnddma.txnobuf++;
18386 + return (-1);
18387 +}
18388 +
18389 +/*
18390 + * Reclaim next completed txd (txds if using chained buffers) and
18391 + * return associated packet.
18392 + * If 'force' is true, reclaim txd(s) and return associated packet
18393 + * regardless of the value of the hardware "curr" pointer.
18394 + */
18395 +static void *
18396 +dma32_getnexttxp(dma_info_t *di, bool forceall)
18397 +{
18398 + uint start, end, i;
18399 + void *txp;
18400 +
18401 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
18402 +
18403 + if (di->ntxd == 0)
18404 + return (NULL);
18405 +
18406 + txp = NULL;
18407 +
18408 + start = di->txin;
18409 + if (forceall)
18410 + end = di->txout;
18411 + else
18412 + end = B2I(R_REG(di->osh, &di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
18413 +
18414 + if ((start == 0) && (end > di->txout))
18415 + goto bogus;
18416 +
18417 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
18418 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd32[i].addr)) - di->dataoffsetlow),
18419 + (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) & CTRL_BC_MASK),
18420 + DMA_TX, di->txp[i]);
18421 +
18422 + W_SM(&di->txd32[i].addr, 0xdeadbeef);
18423 + txp = di->txp[i];
18424 + di->txp[i] = NULL;
18425 + }
18426 +
18427 + di->txin = i;
18428 +
18429 + /* tx flow control */
18430 + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18431 +
18432 + return (txp);
18433 +
18434 +bogus:
18435 +/*
18436 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
18437 + start, end, di->txout, forceall));
18438 +*/
18439 + return (NULL);
18440 +}
18441 +
18442 +static void *
18443 +dma32_getnextrxp(dma_info_t *di, bool forceall)
18444 +{
18445 + uint i;
18446 + void *rxp;
18447 +
18448 + /* if forcing, dma engine must be disabled */
18449 + ASSERT(!forceall || !dma32_rxenabled(di));
18450 +
18451 + i = di->rxin;
18452 +
18453 + /* return if no packets posted */
18454 + if (i == di->rxout)
18455 + return (NULL);
18456 +
18457 + /* ignore curr if forceall */
18458 + if (!forceall && (i == B2I(R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK, dma32dd_t)))
18459 + return (NULL);
18460 +
18461 + /* get the packet pointer that corresponds to the rx descriptor */
18462 + rxp = di->rxp[i];
18463 + ASSERT(rxp);
18464 + di->rxp[i] = NULL;
18465 +
18466 + /* clear this packet from the descriptor ring */
18467 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) - di->dataoffsetlow),
18468 + di->rxbufsize, DMA_RX, rxp);
18469 +
18470 + W_SM(&di->rxd32[i].addr, 0xdeadbeef);
18471 +
18472 + di->rxin = NEXTRXD(i);
18473 +
18474 + return (rxp);
18475 +}
18476 +
18477 +/*
18478 + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
18479 + */
18480 +static void
18481 +dma32_txrotate(dma_info_t *di)
18482 +{
18483 + uint ad;
18484 + uint nactive;
18485 + uint rot;
18486 + uint old, new;
18487 + uint32 w;
18488 + uint first, last;
18489 +
18490 + ASSERT(dma32_txsuspendedidle(di));
18491 +
18492 + nactive = _dma_txactive(di);
18493 + ad = B2I(((R_REG(di->osh, &di->d32txregs->status) & XS_AD_MASK) >> XS_AD_SHIFT), dma32dd_t);
18494 + rot = TXD(ad - di->txin);
18495 +
18496 + ASSERT(rot < di->ntxd);
18497 +
18498 + /* full-ring case is a lot harder - don't worry about this */
18499 + if (rot >= (di->ntxd - nactive)) {
18500 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
18501 + return;
18502 + }
18503 +
18504 + first = di->txin;
18505 + last = PREVTXD(di->txout);
18506 +
18507 + /* move entries starting at last and moving backwards to first */
18508 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
18509 + new = TXD(old + rot);
18510 +
18511 + /*
18512 + * Move the tx dma descriptor.
18513 + * EOT is set only in the last entry in the ring.
18514 + */
18515 + w = BUS_SWAP32(R_SM(&di->txd32[old].ctrl)) & ~CTRL_EOT;
18516 + if (new == (di->ntxd - 1))
18517 + w |= CTRL_EOT;
18518 + W_SM(&di->txd32[new].ctrl, BUS_SWAP32(w));
18519 + W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
18520 +
18521 + /* zap the old tx dma descriptor address field */
18522 + W_SM(&di->txd32[old].addr, BUS_SWAP32(0xdeadbeef));
18523 +
18524 + /* move the corresponding txp[] entry */
18525 + ASSERT(di->txp[new] == NULL);
18526 + di->txp[new] = di->txp[old];
18527 + di->txp[old] = NULL;
18528 + }
18529 +
18530 + /* update txin and txout */
18531 + di->txin = ad;
18532 + di->txout = TXD(di->txout + rot);
18533 + di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18534 +
18535 + /* kick the chip */
18536 + W_REG(di->osh, &di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
18537 +}
18538 +
18539 +
18540 +uint
18541 +dma_addrwidth(sb_t *sbh, void *dmaregs)
18542 +{
18543 + dma32regs_t *dma32regs;
18544 + osl_t *osh;
18545 +
18546 + osh = sb_osh(sbh);
18547 +
18548 + /* Start checking for 32-bit / 30-bit addressing */
18549 + dma32regs = (dma32regs_t *)dmaregs;
18550 +
18551 + /* For System Backplane, PCIE bus or addrext feature, 32-bits ok */
18552 + if ((BUSTYPE(sbh->bustype) == SB_BUS) ||
18553 + ((BUSTYPE(sbh->bustype) == PCI_BUS) && sbh->buscoretype == SB_PCIE) ||
18554 + (_dma32_addrext(osh, dma32regs)))
18555 + return (DMADDRWIDTH_32);
18556 +
18557 + /* Fallthru */
18558 + return (DMADDRWIDTH_30);
18559 +}
18560 diff -urN linux.old/drivers/net/wl/hnddma.h linux.dev/drivers/net/wl/hnddma.h
18561 --- linux.old/drivers/net/wl/hnddma.h 1970-01-01 01:00:00.000000000 +0100
18562 +++ linux.dev/drivers/net/wl/hnddma.h 2006-04-28 02:20:44.000000000 +0200
18563 @@ -0,0 +1,156 @@
18564 +/*
18565 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
18566 + * This supports the following chips: BCM42xx, 44xx, 47xx .
18567 + *
18568 + * Copyright 2006, Broadcom Corporation
18569 + * All Rights Reserved.
18570 + *
18571 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18572 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18573 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18574 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18575 + * $Id: hnddma.h,v 1.1.1.13 2006/04/08 06:13:39 honor Exp $
18576 + */
18577 +
18578 +#ifndef _hnddma_h_
18579 +#define _hnddma_h_
18580 +
18581 +typedef const struct hnddma_pub hnddma_t;
18582 +
18583 +/* dma function type */
18584 +typedef void (*di_detach_t)(hnddma_t *dmah);
18585 +typedef bool (*di_txreset_t)(hnddma_t *dmah);
18586 +typedef bool (*di_rxreset_t)(hnddma_t *dmah);
18587 +typedef bool (*di_rxidle_t)(hnddma_t *dmah);
18588 +typedef void (*di_txinit_t)(hnddma_t *dmah);
18589 +typedef bool (*di_txenabled_t)(hnddma_t *dmah);
18590 +typedef void (*di_rxinit_t)(hnddma_t *dmah);
18591 +typedef void (*di_txsuspend_t)(hnddma_t *dmah);
18592 +typedef void (*di_txresume_t)(hnddma_t *dmah);
18593 +typedef bool (*di_txsuspended_t)(hnddma_t *dmah);
18594 +typedef bool (*di_txsuspendedidle_t)(hnddma_t *dmah);
18595 +typedef int (*di_txfast_t)(hnddma_t *dmah, void *p, bool commit);
18596 +typedef void (*di_fifoloopbackenable_t)(hnddma_t *dmah);
18597 +typedef bool (*di_txstopped_t)(hnddma_t *dmah);
18598 +typedef bool (*di_rxstopped_t)(hnddma_t *dmah);
18599 +typedef bool (*di_rxenable_t)(hnddma_t *dmah);
18600 +typedef bool (*di_rxenabled_t)(hnddma_t *dmah);
18601 +typedef void* (*di_rx_t)(hnddma_t *dmah);
18602 +typedef void (*di_rxfill_t)(hnddma_t *dmah);
18603 +typedef void (*di_txreclaim_t)(hnddma_t *dmah, bool forceall);
18604 +typedef void (*di_rxreclaim_t)(hnddma_t *dmah);
18605 +typedef uintptr (*di_getvar_t)(hnddma_t *dmah, char *name);
18606 +typedef void* (*di_getnexttxp_t)(hnddma_t *dmah, bool forceall);
18607 +typedef void* (*di_getnextrxp_t)(hnddma_t *dmah, bool forceall);
18608 +typedef void* (*di_peeknexttxp_t)(hnddma_t *dmah);
18609 +typedef void (*di_txblock_t)(hnddma_t *dmah);
18610 +typedef void (*di_txunblock_t)(hnddma_t *dmah);
18611 +typedef uint (*di_txactive_t)(hnddma_t *dmah);
18612 +typedef void (*di_txrotate_t)(hnddma_t *dmah);
18613 +typedef void (*di_counterreset_t)(hnddma_t *dmah);
18614 +typedef char* (*di_dump_t)(hnddma_t *dmah, struct bcmstrbuf *b, bool dumpring);
18615 +typedef char* (*di_dumptx_t)(hnddma_t *dmah, struct bcmstrbuf *b, bool dumpring);
18616 +typedef char* (*di_dumprx_t)(hnddma_t *dmah, struct bcmstrbuf *b, bool dumpring);
18617 +
18618 +/* dma opsvec */
18619 +typedef struct di_fcn_s {
18620 + di_detach_t detach;
18621 + di_txinit_t txinit;
18622 + di_txreset_t txreset;
18623 + di_txenabled_t txenabled;
18624 + di_txsuspend_t txsuspend;
18625 + di_txresume_t txresume;
18626 + di_txsuspended_t txsuspended;
18627 + di_txsuspendedidle_t txsuspendedidle;
18628 + di_txfast_t txfast;
18629 + di_txstopped_t txstopped;
18630 + di_txreclaim_t txreclaim;
18631 + di_getnexttxp_t getnexttxp;
18632 + di_peeknexttxp_t peeknexttxp;
18633 + di_txblock_t txblock;
18634 + di_txunblock_t txunblock;
18635 + di_txactive_t txactive;
18636 + di_txrotate_t txrotate;
18637 +
18638 + di_rxinit_t rxinit;
18639 + di_rxreset_t rxreset;
18640 + di_rxidle_t rxidle;
18641 + di_rxstopped_t rxstopped;
18642 + di_rxenable_t rxenable;
18643 + di_rxenabled_t rxenabled;
18644 + di_rx_t rx;
18645 + di_rxfill_t rxfill;
18646 + di_rxreclaim_t rxreclaim;
18647 + di_getnextrxp_t getnextrxp;
18648 +
18649 + di_fifoloopbackenable_t fifoloopbackenable;
18650 + di_getvar_t d_getvar;
18651 + di_counterreset_t counterreset;
18652 + di_dump_t dump;
18653 + di_dumptx_t dumptx;
18654 + di_dumprx_t dumprx;
18655 + uint endnum;
18656 +} di_fcn_t;
18657 +
18658 +/*
18659 + * Exported data structure (read-only)
18660 + */
18661 +/* export structure */
18662 +struct hnddma_pub {
18663 + di_fcn_t di_fn; /* DMA function pointers */
18664 + uint txavail; /* # free tx descriptors */
18665 +
18666 + /* rx error counters */
18667 + uint rxgiants; /* rx giant frames */
18668 + uint rxnobuf; /* rx out of dma descriptors */
18669 + /* tx error counters */
18670 + uint txnobuf; /* tx out of dma descriptors */
18671 +};
18672 +
18673 +
18674 +extern hnddma_t * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
18675 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset,
18676 + uint *msg_level);
18677 +#define dma_detach(di) ((di)->di_fn.detach(di))
18678 +#define dma_txreset(di) ((di)->di_fn.txreset(di))
18679 +#define dma_rxreset(di) ((di)->di_fn.rxreset(di))
18680 +#define dma_rxidle(di) ((di)->di_fn.rxidle(di))
18681 +#define dma_txinit(di) ((di)->di_fn.txinit(di))
18682 +#define dma_txenabled(di) ((di)->di_fn.txenabled(di))
18683 +#define dma_rxinit(di) ((di)->di_fn.rxinit(di))
18684 +#define dma_txsuspend(di) ((di)->di_fn.txsuspend(di))
18685 +#define dma_txresume(di) ((di)->di_fn.txresume(di))
18686 +#define dma_txsuspended(di) ((di)->di_fn.txsuspended(di))
18687 +#define dma_txsuspendedidle(di) ((di)->di_fn.txsuspendedidle(di))
18688 +#define dma_txfast(di, p, commit) ((di)->di_fn.txfast(di, p, commit))
18689 +#define dma_fifoloopbackenable(di) ((di)->di_fn.fifoloopbackenable(di))
18690 +#define dma_txstopped(di) ((di)->di_fn.txstopped(di))
18691 +#define dma_rxstopped(di) ((di)->di_fn.rxstopped(di))
18692 +#define dma_rxenable(di) ((di)->di_fn.rxenable(di))
18693 +#define dma_rxenabled(di) ((di)->di_fn.rxenabled(di))
18694 +#define dma_rx(di) ((di)->di_fn.rx(di))
18695 +#define dma_rxfill(di) ((di)->di_fn.rxfill(di))
18696 +#define dma_txreclaim(di, forceall) ((di)->di_fn.txreclaim(di, forceall))
18697 +#define dma_rxreclaim(di) ((di)->di_fn.rxreclaim(di))
18698 +#define dma_getvar(di, name) ((di)->di_fn.d_getvar(di, name))
18699 +#define dma_getnexttxp(di, forceall) ((di)->di_fn.getnexttxp(di, forceall))
18700 +#define dma_getnextrxp(di, forceall) ((di)->di_fn.getnextrxp(di, forceall))
18701 +#define dma_peeknexttxp(di) ((di)->di_fn.peeknexttxp(di))
18702 +#define dma_txblock(di) ((di)->di_fn.txblock(di))
18703 +#define dma_txunblock(di) ((di)->di_fn.txunblock(di))
18704 +#define dma_txactive(di) ((di)->di_fn.txactive(di))
18705 +#define dma_txrotate(di) ((di)->di_fn.txrotate(di))
18706 +#define dma_counterreset(di) ((di)->di_fn.counterreset(di))
18707 +
18708 +#define DMA_DUMP_SIZE 2048
18709 +/* return addresswidth allowed
18710 + * This needs to be done after SB attach but before dma attach.
18711 + * SB attach provides ability to probe backplane and dma core capabilities
18712 + * This info is needed by DMA_ALLOC_CONSISTENT in dma attach
18713 + */
18714 +extern uint dma_addrwidth(sb_t *sbh, void *dmaregs);
18715 +
18716 +/* pio helpers */
18717 +void dma_txpioloopback(osl_t *osh, dma32regs_t *);
18718 +
18719 +#endif /* _hnddma_h_ */
18720 diff -urN linux.old/drivers/net/wl/linux_osl.c linux.dev/drivers/net/wl/linux_osl.c
18721 --- linux.old/drivers/net/wl/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
18722 +++ linux.dev/drivers/net/wl/linux_osl.c 2006-04-28 02:29:46.000000000 +0200
18723 @@ -0,0 +1,269 @@
18724 +/*
18725 + * Linux OS Independent Layer
18726 + *
18727 + * Copyright 2006, Broadcom Corporation
18728 + * All Rights Reserved.
18729 + *
18730 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18731 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18732 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18733 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18734 + *
18735 + * $Id: linux_osl.c,v 1.1.1.14 2006/04/08 06:13:39 honor Exp $
18736 + */
18737 +
18738 +#define LINUX_OSL
18739 +
18740 +#include <typedefs.h>
18741 +#include <bcmendian.h>
18742 +#include <linux/module.h>
18743 +#include <linuxver.h>
18744 +#include <bcmdefs.h>
18745 +#include <osl.h>
18746 +#include "linux_osl.h"
18747 +#include <bcmutils.h>
18748 +#include <linux/delay.h>
18749 +#ifdef mips
18750 +#include <asm/paccess.h>
18751 +#endif /* mips */
18752 +#include <pcicfg.h>
18753 +
18754 +#define PCI_CFG_RETRY 10
18755 +
18756 +#define OS_HANDLE_MAGIC 0x1234abcd /* Magic # to recognise osh */
18757 +#define BCM_MEM_FILENAME_LEN 24 /* Mem. filename length */
18758 +
18759 +typedef struct bcm_mem_link {
18760 + struct bcm_mem_link *prev;
18761 + struct bcm_mem_link *next;
18762 + uint size;
18763 + int line;
18764 + char file[BCM_MEM_FILENAME_LEN];
18765 +} bcm_mem_link_t;
18766 +
18767 +static int16 linuxbcmerrormap[] = \
18768 +{ 0, /* 0 */
18769 + -EINVAL, /* BCME_ERROR */
18770 + -EINVAL, /* BCME_BADARG */
18771 + -EINVAL, /* BCME_BADOPTION */
18772 + -EINVAL, /* BCME_NOTUP */
18773 + -EINVAL, /* BCME_NOTDOWN */
18774 + -EINVAL, /* BCME_NOTAP */
18775 + -EINVAL, /* BCME_NOTSTA */
18776 + -EINVAL, /* BCME_BADKEYIDX */
18777 + -EINVAL, /* BCME_RADIOOFF */
18778 + -EINVAL, /* BCME_NOTBANDLOCKED */
18779 + -EINVAL, /* BCME_NOCLK */
18780 + -EINVAL, /* BCME_BADRATESET */
18781 + -EINVAL, /* BCME_BADBAND */
18782 + -E2BIG, /* BCME_BUFTOOSHORT */
18783 + -E2BIG, /* BCME_BUFTOOLONG */
18784 + -EBUSY, /* BCME_BUSY */
18785 + -EINVAL, /* BCME_NOTASSOCIATED */
18786 + -EINVAL, /* BCME_BADSSIDLEN */
18787 + -EINVAL, /* BCME_OUTOFRANGECHAN */
18788 + -EINVAL, /* BCME_BADCHAN */
18789 + -EFAULT, /* BCME_BADADDR */
18790 + -ENOMEM, /* BCME_NORESOURCE */
18791 + -EOPNOTSUPP, /* BCME_UNSUPPORTED */
18792 + -EMSGSIZE, /* BCME_BADLENGTH */
18793 + -EINVAL, /* BCME_NOTREADY */
18794 + -EPERM, /* BCME_NOTPERMITTED */
18795 + -ENOMEM, /* BCME_NOMEM */
18796 + -EINVAL, /* BCME_ASSOCIATED */
18797 + -ERANGE, /* BCME_RANGE */
18798 + -EINVAL, /* BCME_NOTFOUND */
18799 + -EINVAL, /* BCME_WME_NOT_ENABLED */
18800 + -EINVAL, /* BCME_TSPEC_NOTFOUND */
18801 + -EINVAL, /* BCME_ACM_NOTSUPPORTED */
18802 + -EINVAL, /* BCME_NOT_WME_ASSOCIATION */
18803 + -EIO, /* BCME_SDIO_ERROR */
18804 + -ENODEV /* BCME_DONGLE_DOWN */
18805 +};
18806 +
18807 +/* translate bcmerrors into linux errors */
18808 +int
18809 +osl_error(int bcmerror)
18810 +{
18811 + int abs_bcmerror;
18812 + int array_size = ARRAYSIZE(linuxbcmerrormap);
18813 +
18814 + abs_bcmerror = ABS(bcmerror);
18815 +
18816 + if (bcmerror > 0)
18817 + abs_bcmerror = 0;
18818 +
18819 + else if (abs_bcmerror >= array_size)
18820 + abs_bcmerror = BCME_ERROR;
18821 +
18822 + return linuxbcmerrormap[abs_bcmerror];
18823 +}
18824 +
18825 +osl_t *
18826 +osl_attach(void *pdev, bool pkttag)
18827 +{
18828 + osl_t *osh;
18829 +
18830 + osh = kmalloc(sizeof(osl_t), GFP_ATOMIC);
18831 + ASSERT(osh);
18832 +
18833 + bzero(osh, sizeof(osl_t));
18834 +
18835 + /*
18836 + * check the cases where
18837 + * 1.Error code Added to bcmerror table, but forgot to add it to the OS
18838 + * dependent error code
18839 + * 2. Error code is added to the bcmerror table, but forgot to add the
18840 + * corresponding errorstring(dummy call to bcmerrorstr)
18841 + */
18842 + bcmerrorstr(0);
18843 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
18844 +
18845 + osh->magic = OS_HANDLE_MAGIC;
18846 + osh->malloced = 0;
18847 + osh->failed = 0;
18848 + osh->dbgmem_list = NULL;
18849 + osh->pdev = pdev;
18850 + osh->pub.pkttag = pkttag;
18851 +
18852 + return osh;
18853 +}
18854 +
18855 +void
18856 +osl_detach(osl_t *osh)
18857 +{
18858 + if (osh == NULL)
18859 + return;
18860 +
18861 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18862 + kfree(osh);
18863 +}
18864 +
18865 +/* Return a new packet. zero out pkttag */
18866 +void*
18867 +osl_pktget(osl_t *osh, uint len, bool send)
18868 +{
18869 + struct sk_buff *skb;
18870 +
18871 + if ((skb = dev_alloc_skb(len))) {
18872 + skb_put(skb, len);
18873 + skb->priority = 0;
18874 +
18875 +#ifdef BCMDBG_PKT
18876 + pktlist_add(&(osh->pktlist), (void *) skb);
18877 +#endif /* BCMDBG_PKT */
18878 +
18879 + osh->pub.pktalloced++;
18880 + }
18881 +
18882 + return ((void*) skb);
18883 +}
18884 +
18885 +/* Free the driver packet. Free the tag if present */
18886 +void
18887 +osl_pktfree(osl_t *osh, void *p)
18888 +{
18889 + struct sk_buff *skb, *nskb;
18890 +
18891 + skb = (struct sk_buff*) p;
18892 +
18893 + /* perversion: we use skb->next to chain multi-skb packets */
18894 + while (skb) {
18895 + nskb = skb->next;
18896 + skb->next = NULL;
18897 +
18898 +#ifdef BCMDBG_PKT
18899 + pktlist_remove(&(osh->pktlist), (void *) skb);
18900 +#endif /* BCMDBG_PKT */
18901 +
18902 + if (skb->destructor) {
18903 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists
18904 + */
18905 + dev_kfree_skb_any(skb);
18906 + } else {
18907 + /* can free immediately (even in_irq()) if destructor does not exist */
18908 + dev_kfree_skb(skb);
18909 + }
18910 +
18911 + osh->pub.pktalloced--;
18912 +
18913 + skb = nskb;
18914 + }
18915 +}
18916 +
18917 +void*
18918 +osl_malloc(osl_t *osh, uint size)
18919 +{
18920 + void *addr;
18921 +
18922 + /* only ASSERT if osh is defined */
18923 + if (osh)
18924 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18925 +
18926 + if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
18927 + if (osh)
18928 + osh->failed++;
18929 + return (NULL);
18930 + }
18931 + if (osh)
18932 + osh->malloced += size;
18933 +
18934 + return (addr);
18935 +}
18936 +
18937 +void
18938 +osl_mfree(osl_t *osh, void *addr, uint size)
18939 +{
18940 + if (osh) {
18941 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18942 + osh->malloced -= size;
18943 + }
18944 + kfree(addr);
18945 +}
18946 +
18947 +uint
18948 +osl_malloced(osl_t *osh)
18949 +{
18950 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18951 + return (osh->malloced);
18952 +}
18953 +
18954 +uint osl_malloc_failed(osl_t *osh)
18955 +{
18956 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18957 + return (osh->failed);
18958 +}
18959 +
18960 +#undef osl_delay
18961 +void
18962 +osl_delay(uint usec)
18963 +{
18964 + OSL_DELAY(usec);
18965 +}
18966 +
18967 +/* Clone a packet.
18968 + * The pkttag contents are NOT cloned.
18969 + */
18970 +void *
18971 +osl_pktdup(osl_t *osh, void *skb)
18972 +{
18973 + void * p;
18974 +
18975 + if ((p = skb_clone((struct sk_buff*)skb, GFP_ATOMIC)) == NULL)
18976 + return NULL;
18977 +
18978 + /* skb_clone copies skb->cb.. we don't want that */
18979 + if (osh->pub.pkttag)
18980 + bzero((void*)((struct sk_buff *)p)->cb, OSL_PKTTAG_SZ);
18981 +
18982 + /* Increment the packet counter */
18983 + osh->pub.pktalloced++;
18984 + return (p);
18985 +}
18986 +
18987 +uint
18988 +osl_pktalloced(osl_t *osh)
18989 +{
18990 + return (osh->pub.pktalloced);
18991 +}
18992 +
18993 diff -urN linux.old/drivers/net/wl/linux_osl.h linux.dev/drivers/net/wl/linux_osl.h
18994 --- linux.old/drivers/net/wl/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
18995 +++ linux.dev/drivers/net/wl/linux_osl.h 2006-05-02 17:44:29.000000000 +0200
18996 @@ -0,0 +1,171 @@
18997 +/*
18998 + * Linux OS Independent Layer
18999 + *
19000 + * Copyright 2006, Broadcom Corporation
19001 + * All Rights Reserved.
19002 + *
19003 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19004 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19005 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19006 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19007 + *
19008 + * $Id: linux_osl.h,v 1.1.1.13 2006/04/08 06:13:39 honor Exp $
19009 + */
19010 +
19011 +#ifndef _linux_osl_h_
19012 +#define _linux_osl_h_
19013 +
19014 +#include <typedefs.h>
19015 +#include <linuxver.h>
19016 +#include <osl.h>
19017 +
19018 +#define OSL_PKTTAG_SZ 32 /* Size of PktTag */
19019 +
19020 +/* osl handle type forward declaration */
19021 +typedef struct osl_dmainfo osldma_t;
19022 +
19023 +/* OSL initialization */
19024 +extern osl_t *osl_attach(void *pdev, bool pkttag);
19025 +extern void osl_detach(osl_t *osh);
19026 +
19027 +/* host/bus architecture-specific byte swap */
19028 +#define BUS_SWAP32(v) (v)
19029 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
19030 +
19031 +extern void *osl_malloc(osl_t *osh, uint size);
19032 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
19033 +extern uint osl_malloced(osl_t *osh);
19034 +extern uint osl_malloc_failed(osl_t *osh);
19035 +
19036 +/* API for DMA addressing capability */
19037 +#define DMA_MAP(osh, va, size, direction, p) \
19038 + osl_dma_map((osh), (va), (size), (direction))
19039 +#define DMA_UNMAP(osh, pa, size, direction, p) \
19040 + osl_dma_unmap((osh), (pa), (size), (direction))
19041 +static inline uint
19042 +osl_dma_map(void *osh, void *va, uint size, int direction)
19043 +{
19044 + int dir;
19045 + struct pci_dev *dev;
19046 +
19047 + dev = (osh == NULL ? NULL : ((osl_t *)osh)->pdev);
19048 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
19049 + return (pci_map_single(dev, va, size, dir));
19050 +}
19051 +
19052 +static inline void
19053 +osl_dma_unmap(void *osh, uint pa, uint size, int direction)
19054 +{
19055 + int dir;
19056 + struct pci_dev *dev;
19057 +
19058 + dev = (osh == NULL ? NULL : ((osl_t *)osh)->pdev);
19059 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
19060 + pci_unmap_single(dev, (uint32)pa, size, dir);
19061 +}
19062 +
19063 +#define OSL_DMADDRWIDTH(osh, addrwidth) do {} while (0)
19064 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
19065 +#define DMA_ALLOC_CONSISTENT(osh, size, pap, dmah) \
19066 + osl_dma_alloc_consistent((osh), (size), (pap))
19067 +#define DMA_FREE_CONSISTENT(osh, va, size, pa, dmah) \
19068 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
19069 +static inline void*
19070 +osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
19071 +{
19072 + return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
19073 +}
19074 +
19075 +static inline void
19076 +osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
19077 +{
19078 + pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
19079 +}
19080 +
19081 +
19082 +/* register access macros */
19083 +#if defined(BCMJTAG)
19084 +#include <bcmjtag.h>
19085 +#define R_REG(osh, r) bcmjtag_read(NULL, (uint32)(r), sizeof(*(r)))
19086 +#define W_REG(osh, r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof(*(r)))
19087 +#endif /* defined(BCMSDIO) */
19088 +
19089 +/* packet primitives */
19090 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
19091 +#define PKTFREE(osh, skb, send) osl_pktfree((osh), (skb))
19092 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
19093 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
19094 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh, skb)-(((struct sk_buff*)(skb))->head))
19095 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
19096 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
19097 +#define PKTSETNEXT(osh, skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
19098 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
19099 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
19100 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
19101 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
19102 +#define PKTTAG(skb) ((void*)(((struct sk_buff*)(skb))->cb))
19103 +#define PKTALLOCED(osh) osl_pktalloced((osh))
19104 +#define PKTLIST_DUMP(osh, buf)
19105 +
19106 +/* Convert a native(OS) packet to driver packet.
19107 + * In the process, native packet is destroyed, there is no copying
19108 + * Also, a packettag is zeroed out
19109 + */
19110 +static INLINE void *
19111 +osl_pkt_frmnative(struct osl_pubinfo *osh, struct sk_buff *skb)
19112 +{
19113 + struct sk_buff *nskb;
19114 +
19115 + if (osh->pkttag)
19116 + bzero((void*)skb->cb, OSL_PKTTAG_SZ);
19117 +
19118 + /* Increment the packet counter */
19119 + for (nskb = skb; nskb; nskb = nskb->next) {
19120 + osh->pktalloced++;
19121 + }
19122 +
19123 + return (void *)skb;
19124 +}
19125 +#define PKTFRMNATIVE(osh, skb) osl_pkt_frmnative(((struct osl_pubinfo *)osh), \
19126 + (struct sk_buff*)(skb))
19127 +
19128 +/* Convert a driver packet to native(OS) packet
19129 + * In the process, packettag is zeroed out before sending up
19130 + * IP code depends on skb->cb to be setup correctly with various options
19131 + * In our case, that means it should be 0
19132 + */
19133 +static INLINE struct sk_buff *
19134 +osl_pkt_tonative(struct osl_pubinfo *osh, void *pkt)
19135 +{
19136 + struct sk_buff *nskb;
19137 +
19138 + if (osh->pkttag)
19139 + bzero(((struct sk_buff*)pkt)->cb, OSL_PKTTAG_SZ);
19140 +
19141 + /* Decrement the packet counter */
19142 + for (nskb = (struct sk_buff *)pkt; nskb; nskb = nskb->next) {
19143 + osh->pktalloced--;
19144 + }
19145 +
19146 + return (struct sk_buff *)pkt;
19147 +}
19148 +#define PKTTONATIVE(osh, pkt) osl_pkt_tonative((struct osl_pubinfo *)(osh), (pkt))
19149 +
19150 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
19151 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
19152 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
19153 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
19154 +#define PKTSHARED(skb) (((struct sk_buff*)(skb))->cloned)
19155 +
19156 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
19157 +extern void osl_pktfree(osl_t *osh, void *skb);
19158 +extern void *osl_pktdup(osl_t *osh, void *skb);
19159 +extern uint osl_pktalloced(osl_t *osh);
19160 +
19161 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
19162 +extern int osl_error(int bcmerror);
19163 +
19164 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
19165 +#define PKTBUFSZ 2048 /* largest reasonable packet buffer, driver uses for ethernet MTU */
19166 +
19167 +#endif /* _linux_osl_h_ */
19168 diff -urN linux.old/drivers/net/wl/pktq.h linux.dev/drivers/net/wl/pktq.h
19169 --- linux.old/drivers/net/wl/pktq.h 1970-01-01 01:00:00.000000000 +0100
19170 +++ linux.dev/drivers/net/wl/pktq.h 2006-04-28 02:11:49.000000000 +0200
19171 @@ -0,0 +1,97 @@
19172 +/*
19173 + * Misc useful os-independent macros and functions.
19174 + *
19175 + * Copyright 2006, Broadcom Corporation
19176 + * All Rights Reserved.
19177 + *
19178 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19179 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19180 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19181 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19182 + * $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
19183 + */
19184 +
19185 +#ifndef _pktq_h_
19186 +#define _pktq_h_
19187 +#include <osl.h>
19188 +
19189 +/* osl multi-precedence packet queue */
19190 +
19191 +#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */
19192 +#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */
19193 +
19194 +struct pktq {
19195 + struct pktq_prec {
19196 + void *head; /* first packet to dequeue */
19197 + void *tail; /* last packet to dequeue */
19198 + uint16 len; /* number of queued packets */
19199 + uint16 max; /* maximum number of queued packets */
19200 + } q[PKTQ_MAX_PREC];
19201 + uint16 num_prec; /* number of precedences in use */
19202 + uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
19203 + uint16 max; /* total max packets */
19204 + uint16 len; /* total number of packets */
19205 +};
19206 +
19207 +#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
19208 +
19209 +/* forward definition of ether_addr structure used by some function prototypes */
19210 +
19211 +struct ether_addr;
19212 +
19213 +/* operations on a specific precedence in packet queue */
19214 +
19215 +#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max))
19216 +#define pktq_plen(pq, prec) ((pq)->q[prec].len)
19217 +#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len)
19218 +#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max)
19219 +#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0)
19220 +
19221 +#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
19222 +#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
19223 +
19224 +extern void *pktq_penq(struct pktq *pq, int prec, void *p);
19225 +extern void *pktq_penq_head(struct pktq *pq, int prec, void *p);
19226 +extern void *pktq_pdeq(struct pktq *pq, int prec);
19227 +extern void *pktq_pdeq_tail(struct pktq *pq, int prec);
19228 +/* Empty the queue at particular precedence level */
19229 +extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir);
19230 +/* Remove a specified packet from its queue */
19231 +extern bool pktq_pdel(struct pktq *pq, void *p, int prec);
19232 +
19233 +/* operations on a set of precedences in packet queue */
19234 +
19235 +extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
19236 +extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
19237 +
19238 +/* operations on packet queue as a whole */
19239 +
19240 +#define pktq_len(pq) ((int)(pq)->len)
19241 +#define pktq_max(pq) ((int)(pq)->max)
19242 +#define pktq_avail(pq) ((int)((pq)->max - (pq)->len))
19243 +#define pktq_full(pq) ((pq)->len >= (pq)->max)
19244 +#define pktq_empty(pq) ((pq)->len == 0)
19245 +
19246 +/* operations for single precedence queues */
19247 +#define pktenq(pq, p) pktq_penq((pq), 0, (p))
19248 +#define pktenq_head(pq, p) pktq_penq_head((pq), 0, (p))
19249 +#define pktdeq(pq) pktq_pdeq((pq), 0)
19250 +#define pktdeq_tail(pq) pktq_pdeq_tail((pq), 0)
19251 +
19252 +extern void pktq_init(struct pktq *pq, int num_prec, int max_len);
19253 +/* prec_out may be NULL if caller is not interested in return value */
19254 +extern void *pktq_deq(struct pktq *pq, int *prec_out);
19255 +extern void *pktq_deq_tail(struct pktq *pq, int *prec_out);
19256 +extern void *pktq_peek(struct pktq *pq, int *prec_out);
19257 +extern void *pktq_peek_tail(struct pktq *pq, int *prec_out);
19258 +extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir); /* Empty the entire queue */
19259 +
19260 +/* externs */
19261 +/* packet */
19262 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
19263 +extern uint pkttotlen(osl_t *osh, void *p);
19264 +extern void *pktlast(osl_t *osh, void *p);
19265 +
19266 +extern void pktsetprio(void *pkt, bool update_vtag);
19267 +
19268 +#endif /* _pktq_h_ */
19269 diff -urN linux.old/drivers/net/wl/sbhnddma.h linux.dev/drivers/net/wl/sbhnddma.h
19270 --- linux.old/drivers/net/wl/sbhnddma.h 1970-01-01 01:00:00.000000000 +0100
19271 +++ linux.dev/drivers/net/wl/sbhnddma.h 2006-04-28 02:20:47.000000000 +0200
19272 @@ -0,0 +1,284 @@
19273 +/*
19274 + * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
19275 + * This supports the following chips: BCM42xx, 44xx, 47xx .
19276 + *
19277 + * Copyright 2006, Broadcom Corporation
19278 + * All Rights Reserved.
19279 + *
19280 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19281 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19282 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19283 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19284 + *
19285 + * $Id: sbhnddma.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
19286 + */
19287 +
19288 +#ifndef _sbhnddma_h_
19289 +#define _sbhnddma_h_
19290 +
19291 +/* DMA structure:
19292 + * support two DMA engines: 32 bits address or 64 bit addressing
19293 + * basic DMA register set is per channel(transmit or receive)
19294 + * a pair of channels is defined for convenience
19295 + */
19296 +
19297 +
19298 +/* 32 bits addressing */
19299 +
19300 +/* dma registers per channel(xmt or rcv) */
19301 +typedef volatile struct {
19302 + uint32 control; /* enable, et al */
19303 + uint32 addr; /* descriptor ring base address (4K aligned) */
19304 + uint32 ptr; /* last descriptor posted to chip */
19305 + uint32 status; /* current active descriptor, et al */
19306 +} dma32regs_t;
19307 +
19308 +typedef volatile struct {
19309 + dma32regs_t xmt; /* dma tx channel */
19310 + dma32regs_t rcv; /* dma rx channel */
19311 +} dma32regp_t;
19312 +
19313 +typedef volatile struct { /* diag access */
19314 + uint32 fifoaddr; /* diag address */
19315 + uint32 fifodatalow; /* low 32bits of data */
19316 + uint32 fifodatahigh; /* high 32bits of data */
19317 + uint32 pad; /* reserved */
19318 +} dma32diag_t;
19319 +
19320 +/*
19321 + * DMA Descriptor
19322 + * Descriptors are only read by the hardware, never written back.
19323 + */
19324 +typedef volatile struct {
19325 + uint32 ctrl; /* misc control bits & bufcount */
19326 + uint32 addr; /* data buffer address */
19327 +} dma32dd_t;
19328 +
19329 +/*
19330 + * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
19331 + */
19332 +#define D32MAXRINGSZ 4096
19333 +#define D32RINGALIGN 4096
19334 +#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
19335 +
19336 +/* transmit channel control */
19337 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
19338 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
19339 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
19340 +#define XC_FL ((uint32)1 << 4) /* flush request */
19341 +#define XC_AE ((uint32)3 << 16) /* address extension bits */
19342 +#define XC_AE_SHIFT 16
19343 +
19344 +/* transmit descriptor table pointer */
19345 +#define XP_LD_MASK 0xfff /* last valid descriptor */
19346 +
19347 +/* transmit channel status */
19348 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
19349 +#define XS_XS_MASK 0xf000 /* transmit state */
19350 +#define XS_XS_SHIFT 12
19351 +#define XS_XS_DISABLED 0x0000 /* disabled */
19352 +#define XS_XS_ACTIVE 0x1000 /* active */
19353 +#define XS_XS_IDLE 0x2000 /* idle wait */
19354 +#define XS_XS_STOPPED 0x3000 /* stopped */
19355 +#define XS_XS_SUSP 0x4000 /* suspend pending */
19356 +#define XS_XE_MASK 0xf0000 /* transmit errors */
19357 +#define XS_XE_SHIFT 16
19358 +#define XS_XE_NOERR 0x00000 /* no error */
19359 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
19360 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
19361 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
19362 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
19363 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
19364 +#define XS_AD_SHIFT 20
19365 +
19366 +/* receive channel control */
19367 +#define RC_RE ((uint32)1 << 0) /* receive enable */
19368 +#define RC_RO_MASK 0xfe /* receive frame offset */
19369 +#define RC_RO_SHIFT 1
19370 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
19371 +#define RC_AE ((uint32)3 << 16) /* address extension bits */
19372 +#define RC_AE_SHIFT 16
19373 +
19374 +/* receive descriptor table pointer */
19375 +#define RP_LD_MASK 0xfff /* last valid descriptor */
19376 +
19377 +/* receive channel status */
19378 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
19379 +#define RS_RS_MASK 0xf000 /* receive state */
19380 +#define RS_RS_SHIFT 12
19381 +#define RS_RS_DISABLED 0x0000 /* disabled */
19382 +#define RS_RS_ACTIVE 0x1000 /* active */
19383 +#define RS_RS_IDLE 0x2000 /* idle wait */
19384 +#define RS_RS_STOPPED 0x3000 /* reserved */
19385 +#define RS_RE_MASK 0xf0000 /* receive errors */
19386 +#define RS_RE_SHIFT 16
19387 +#define RS_RE_NOERR 0x00000 /* no error */
19388 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
19389 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
19390 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
19391 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
19392 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
19393 +#define RS_AD_SHIFT 20
19394 +
19395 +/* fifoaddr */
19396 +#define FA_OFF_MASK 0xffff /* offset */
19397 +#define FA_SEL_MASK 0xf0000 /* select */
19398 +#define FA_SEL_SHIFT 16
19399 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
19400 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
19401 +#define FA_SEL_RDD 0x40000 /* receive dma data */
19402 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
19403 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
19404 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
19405 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
19406 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
19407 +#define FA_SEL_RSD 0xe0000 /* receive frame status data */
19408 +#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
19409 +
19410 +/* descriptor control flags */
19411 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
19412 +#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
19413 +#define CTRL_AE_SHIFT 16
19414 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
19415 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
19416 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
19417 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
19418 +
19419 +/* control flags in the range [27:20] are core-specific and not defined here */
19420 +#define CTRL_CORE_MASK 0x0ff00000
19421 +
19422 +/* 64 bits addressing */
19423 +
19424 +/* dma registers per channel(xmt or rcv) */
19425 +typedef volatile struct {
19426 + uint32 control; /* enable, et al */
19427 + uint32 ptr; /* last descriptor posted to chip */
19428 + uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
19429 + uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
19430 + uint32 status0; /* current descriptor, xmt state */
19431 + uint32 status1; /* active descriptor, xmt error */
19432 +} dma64regs_t;
19433 +
19434 +typedef volatile struct {
19435 + dma64regs_t tx; /* dma64 tx channel */
19436 + dma64regs_t rx; /* dma64 rx channel */
19437 +} dma64regp_t;
19438 +
19439 +typedef volatile struct { /* diag access */
19440 + uint32 fifoaddr; /* diag address */
19441 + uint32 fifodatalow; /* low 32bits of data */
19442 + uint32 fifodatahigh; /* high 32bits of data */
19443 + uint32 pad; /* reserved */
19444 +} dma64diag_t;
19445 +
19446 +/*
19447 + * DMA Descriptor
19448 + * Descriptors are only read by the hardware, never written back.
19449 + */
19450 +typedef volatile struct {
19451 + uint32 ctrl1; /* misc control bits & bufcount */
19452 + uint32 ctrl2; /* buffer count and address extension */
19453 + uint32 addrlow; /* memory address of the date buffer, bits 31:0 */
19454 + uint32 addrhigh; /* memory address of the date buffer, bits 63:32 */
19455 +} dma64dd_t;
19456 +
19457 +/*
19458 + * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
19459 + */
19460 +#define D64MAXRINGSZ 8192
19461 +#define D64RINGALIGN 8192
19462 +#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
19463 +
19464 +/* transmit channel control */
19465 +#define D64_XC_XE 0x00000001 /* transmit enable */
19466 +#define D64_XC_SE 0x00000002 /* transmit suspend request */
19467 +#define D64_XC_LE 0x00000004 /* loopback enable */
19468 +#define D64_XC_FL 0x00000010 /* flush request */
19469 +#define D64_XC_AE 0x00030000 /* address extension bits */
19470 +#define D64_XC_AE_SHIFT 16
19471 +
19472 +/* transmit descriptor table pointer */
19473 +#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
19474 +
19475 +/* transmit channel status */
19476 +#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
19477 +#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
19478 +#define D64_XS0_XS_SHIFT 28
19479 +#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
19480 +#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
19481 +#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
19482 +#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
19483 +#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
19484 +
19485 +#define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
19486 +#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
19487 +#define D64_XS1_XE_SHIFT 28
19488 +#define D64_XS1_XE_NOERR 0x00000000 /* no error */
19489 +#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
19490 +#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
19491 +#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
19492 +#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
19493 +#define D64_XS1_XE_COREE 0x50000000 /* core error */
19494 +
19495 +/* receive channel control */
19496 +#define D64_RC_RE 0x00000001 /* receive enable */
19497 +#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
19498 +#define D64_RC_RO_SHIFT 1
19499 +#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
19500 +#define D64_RC_AE 0x00030000 /* address extension bits */
19501 +#define D64_RC_AE_SHIFT 16
19502 +
19503 +/* receive descriptor table pointer */
19504 +#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
19505 +
19506 +/* receive channel status */
19507 +#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
19508 +#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
19509 +#define D64_RS0_RS_SHIFT 28
19510 +#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
19511 +#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
19512 +#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
19513 +#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
19514 +#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
19515 +
19516 +#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
19517 +#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
19518 +#define D64_RS1_RE_SHIFT 28
19519 +#define D64_RS1_RE_NOERR 0x00000000 /* no error */
19520 +#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
19521 +#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
19522 +#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
19523 +#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
19524 +#define D64_RS1_RE_COREE 0x50000000 /* core error */
19525 +
19526 +/* fifoaddr */
19527 +#define D64_FA_OFF_MASK 0xffff /* offset */
19528 +#define D64_FA_SEL_MASK 0xf0000 /* select */
19529 +#define D64_FA_SEL_SHIFT 16
19530 +#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
19531 +#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
19532 +#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
19533 +#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
19534 +#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
19535 +#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
19536 +#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
19537 +#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
19538 +#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
19539 +#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
19540 +
19541 +/* descriptor control flags 1 */
19542 +#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
19543 +#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
19544 +#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
19545 +#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
19546 +
19547 +/* descriptor control flags 2 */
19548 +#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
19549 +#define D64_CTRL2_AE 0x00030000 /* address extension bits */
19550 +#define D64_CTRL2_AE_SHIFT 16
19551 +
19552 +/* control flags in the range [27:20] are core-specific and not defined here */
19553 +#define D64_CTRL_CORE_MASK 0x0ff00000
19554 +
19555 +
19556 +#endif /* _sbhnddma_h_ */
19557 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
19558 --- linux.old/drivers/parport/Config.in 2006-04-27 18:04:38.000000000 +0200
19559 +++ linux.dev/drivers/parport/Config.in 2006-04-27 19:24:19.000000000 +0200
19560 @@ -11,6 +11,7 @@
19561 tristate 'Parallel port support' CONFIG_PARPORT
19562 if [ "$CONFIG_PARPORT" != "n" ]; then
19563 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
19564 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
19565 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
19566 if [ "$CONFIG_SERIAL" = "m" ]; then
19567 define_tristate CONFIG_PARPORT_PC_CML1 m
19568 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
19569 --- linux.old/drivers/parport/Makefile 2006-04-27 18:04:38.000000000 +0200
19570 +++ linux.dev/drivers/parport/Makefile 2006-04-27 19:24:19.000000000 +0200
19571 @@ -22,6 +22,7 @@
19572
19573 obj-$(CONFIG_PARPORT) += parport.o
19574 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
19575 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
19576 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
19577 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
19578 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
19579 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
19580 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
19581 +++ linux.dev/drivers/parport/parport_splink.c 2006-04-27 19:24:19.000000000 +0200
19582 @@ -0,0 +1,345 @@
19583 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
19584 + *
19585 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
19586 + * Based on parport_pc source
19587 + */
19588 +
19589 +#include <linux/config.h>
19590 +#include <linux/module.h>
19591 +#include <linux/init.h>
19592 +#include <linux/ioport.h>
19593 +#include <linux/kernel.h>
19594 +#include <linux/slab.h>
19595 +#include <linux/parport.h>
19596 +#include <linux/parport_pc.h>
19597 +
19598 +#define SPLINK_ADDRESS 0xBF800010
19599 +
19600 +#undef DEBUG
19601 +
19602 +#ifdef DEBUG
19603 +#define DPRINTK printk
19604 +#else
19605 +#define DPRINTK(stuff...)
19606 +#endif
19607 +
19608 +
19609 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
19610 + * it doesn't do any extra masking. */
19611 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
19612 + unsigned char mask,
19613 + unsigned char val)
19614 +{
19615 + struct parport_pc_private *priv = p->physport->private_data;
19616 + unsigned char *io = (unsigned char *) p->base;
19617 + unsigned char ctr = priv->ctr;
19618 +#ifdef DEBUG_PARPORT
19619 + printk (KERN_DEBUG
19620 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
19621 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
19622 +#endif
19623 + ctr = (ctr & ~mask) ^ val;
19624 + ctr &= priv->ctr_writable; /* only write writable bits. */
19625 + *(io+2) = ctr;
19626 + priv->ctr = ctr; /* Update soft copy */
19627 + return ctr;
19628 +}
19629 +
19630 +
19631 +
19632 +static void parport_splink_data_forward (struct parport *p)
19633 +{
19634 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
19635 + __parport_splink_frob_control (p, 0x20, 0);
19636 +}
19637 +
19638 +static void parport_splink_data_reverse (struct parport *p)
19639 +{
19640 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
19641 + __parport_splink_frob_control (p, 0x20, 0x20);
19642 +}
19643 +
19644 +/*
19645 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
19646 +{
19647 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
19648 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
19649 +}
19650 +*/
19651 +
19652 +static void parport_splink_enable_irq(struct parport *p)
19653 +{
19654 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
19655 + __parport_splink_frob_control (p, 0x10, 0x10);
19656 +}
19657 +
19658 +static void parport_splink_disable_irq(struct parport *p)
19659 +{
19660 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
19661 + __parport_splink_frob_control (p, 0x10, 0);
19662 +}
19663 +
19664 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
19665 +{
19666 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
19667 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
19668 + if (dev->irq_func &&
19669 + dev->port->irq != PARPORT_IRQ_NONE)
19670 + /* Set ackIntEn */
19671 + s->u.pc.ctr |= 0x10;
19672 +}
19673 +
19674 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
19675 +{
19676 + const struct parport_pc_private *priv = p->physport->private_data;
19677 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
19678 + s->u.pc.ctr = priv->ctr;
19679 +}
19680 +
19681 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
19682 +{
19683 + struct parport_pc_private *priv = p->physport->private_data;
19684 + unsigned char *io = (unsigned char *) p->base;
19685 + unsigned char ctr = s->u.pc.ctr;
19686 +
19687 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
19688 + *(io+2) = ctr;
19689 + priv->ctr = ctr;
19690 +}
19691 +
19692 +static void parport_splink_setup_interrupt(void) {
19693 + return;
19694 +}
19695 +
19696 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
19697 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
19698 + unsigned char *io = (unsigned char *) p->base;
19699 + *io = d;
19700 +}
19701 +
19702 +static unsigned char parport_splink_read_data(struct parport *p) {
19703 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
19704 + unsigned char *io = (unsigned char *) p->base;
19705 + return *io;
19706 +}
19707 +
19708 +static void parport_splink_write_control(struct parport *p, unsigned char d)
19709 +{
19710 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
19711 + PARPORT_CONTROL_AUTOFD |
19712 + PARPORT_CONTROL_INIT |
19713 + PARPORT_CONTROL_SELECT);
19714 +
19715 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
19716 + /* Take this out when drivers have adapted to the newer interface. */
19717 + if (d & 0x20) {
19718 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
19719 + p->name, p->cad->name);
19720 + parport_splink_data_reverse (p);
19721 + }
19722 +
19723 + __parport_splink_frob_control (p, wm, d & wm);
19724 +}
19725 +
19726 +static unsigned char parport_splink_read_control(struct parport *p)
19727 +{
19728 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
19729 + PARPORT_CONTROL_AUTOFD |
19730 + PARPORT_CONTROL_INIT |
19731 + PARPORT_CONTROL_SELECT);
19732 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
19733 + const struct parport_pc_private *priv = p->physport->private_data;
19734 + return priv->ctr & wm; /* Use soft copy */
19735 +}
19736 +
19737 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
19738 + unsigned char val)
19739 +{
19740 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
19741 + PARPORT_CONTROL_AUTOFD |
19742 + PARPORT_CONTROL_INIT |
19743 + PARPORT_CONTROL_SELECT);
19744 +
19745 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
19746 + /* Take this out when drivers have adapted to the newer interface. */
19747 + if (mask & 0x20) {
19748 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
19749 + p->name, p->cad->name,
19750 + (val & 0x20) ? "reverse" : "forward");
19751 + if (val & 0x20)
19752 + parport_splink_data_reverse (p);
19753 + else
19754 + parport_splink_data_forward (p);
19755 + }
19756 +
19757 + /* Restrict mask and val to control lines. */
19758 + mask &= wm;
19759 + val &= wm;
19760 +
19761 + return __parport_splink_frob_control (p, mask, val);
19762 +}
19763 +
19764 +static unsigned char parport_splink_read_status(struct parport *p)
19765 +{
19766 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
19767 + unsigned char *io = (unsigned char *) p->base;
19768 + return *(io+1);
19769 +}
19770 +
19771 +static void parport_splink_inc_use_count(void)
19772 +{
19773 +#ifdef MODULE
19774 + MOD_INC_USE_COUNT;
19775 +#endif
19776 +}
19777 +
19778 +static void parport_splink_dec_use_count(void)
19779 +{
19780 +#ifdef MODULE
19781 + MOD_DEC_USE_COUNT;
19782 +#endif
19783 +}
19784 +
19785 +static struct parport_operations parport_splink_ops =
19786 +{
19787 + parport_splink_write_data,
19788 + parport_splink_read_data,
19789 +
19790 + parport_splink_write_control,
19791 + parport_splink_read_control,
19792 + parport_splink_frob_control,
19793 +
19794 + parport_splink_read_status,
19795 +
19796 + parport_splink_enable_irq,
19797 + parport_splink_disable_irq,
19798 +
19799 + parport_splink_data_forward,
19800 + parport_splink_data_reverse,
19801 +
19802 + parport_splink_init_state,
19803 + parport_splink_save_state,
19804 + parport_splink_restore_state,
19805 +
19806 + parport_splink_inc_use_count,
19807 + parport_splink_dec_use_count,
19808 +
19809 + parport_ieee1284_epp_write_data,
19810 + parport_ieee1284_epp_read_data,
19811 + parport_ieee1284_epp_write_addr,
19812 + parport_ieee1284_epp_read_addr,
19813 +
19814 + parport_ieee1284_ecp_write_data,
19815 + parport_ieee1284_ecp_read_data,
19816 + parport_ieee1284_ecp_write_addr,
19817 +
19818 + parport_ieee1284_write_compat,
19819 + parport_ieee1284_read_nibble,
19820 + parport_ieee1284_read_byte,
19821 +};
19822 +
19823 +/* --- Initialisation code -------------------------------- */
19824 +
19825 +static struct parport *parport_splink_probe_port (unsigned long int base)
19826 +{
19827 + struct parport_pc_private *priv;
19828 + struct parport_operations *ops;
19829 + struct parport *p;
19830 +
19831 + if (check_mem_region(base, 3)) {
19832 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
19833 + return NULL;
19834 + }
19835 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
19836 + if (!priv) {
19837 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
19838 + return NULL;
19839 + }
19840 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
19841 + if (!ops) {
19842 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
19843 + base);
19844 + kfree (priv);
19845 + return NULL;
19846 + }
19847 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
19848 + priv->ctr = 0xc;
19849 + priv->ctr_writable = 0xff;
19850 +
19851 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
19852 + PARPORT_DMA_NONE, ops))) {
19853 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
19854 + base);
19855 + kfree (priv);
19856 + kfree (ops);
19857 + return NULL;
19858 + }
19859 +
19860 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
19861 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
19862 + p->private_data = priv;
19863 +
19864 + parport_proc_register(p);
19865 + request_mem_region (p->base, 3, p->name);
19866 +
19867 + /* Done probing. Now put the port into a sensible start-up state. */
19868 + parport_splink_write_data(p, 0);
19869 + parport_splink_data_forward (p);
19870 +
19871 + /* Now that we've told the sharing engine about the port, and
19872 + found out its characteristics, let the high-level drivers
19873 + know about it. */
19874 + parport_announce_port (p);
19875 +
19876 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
19877 + base);
19878 + return p;
19879 +}
19880 +
19881 +static void parport_splink_unregister_port(struct parport *p) {
19882 + struct parport_pc_private *priv = p->private_data;
19883 + struct parport_operations *ops = p->ops;
19884 +
19885 + if (p->irq != PARPORT_IRQ_NONE)
19886 + free_irq(p->irq, p);
19887 + release_mem_region(p->base, 3);
19888 + parport_proc_unregister(p);
19889 + kfree (priv);
19890 + parport_unregister_port(p);
19891 + kfree (ops);
19892 +}
19893 +
19894 +
19895 +int parport_splink_init(void)
19896 +{
19897 + int ret;
19898 +
19899 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
19900 + parport_splink_setup_interrupt();
19901 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
19902 +
19903 + return ret;
19904 +}
19905 +
19906 +void parport_splink_cleanup(void) {
19907 + struct parport *p = parport_enumerate(), *tmp;
19908 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
19909 + if (p->size) {
19910 + if (p->modes & PARPORT_MODE_PCSPP) {
19911 + while(p) {
19912 + tmp = p->next;
19913 + parport_splink_unregister_port(p);
19914 + p = tmp;
19915 + }
19916 + }
19917 + }
19918 +}
19919 +
19920 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
19921 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
19922 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
19923 +MODULE_LICENSE("GPL");
19924 +
19925 +module_init(parport_splink_init)
19926 +module_exit(parport_splink_cleanup)
19927 +
19928 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
19929 --- linux.old/include/asm-mips/bootinfo.h 2006-04-27 18:04:38.000000000 +0200
19930 +++ linux.dev/include/asm-mips/bootinfo.h 2006-04-27 19:24:19.000000000 +0200
19931 @@ -37,6 +37,7 @@
19932 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
19933 #define MACH_GROUP_LASAT 21
19934 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
19935 +#define MACH_GROUP_BRCM 23 /* Broadcom */
19936
19937 /*
19938 * Valid machtype values for group unknown (low order halfword of mips_machtype)
19939 @@ -197,6 +198,15 @@
19940 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
19941
19942 /*
19943 + * Valid machtypes for group Broadcom
19944 + */
19945 +#define MACH_BCM93725 0
19946 +#define MACH_BCM93725_VJ 1
19947 +#define MACH_BCM93730 2
19948 +#define MACH_BCM947XX 3
19949 +#define MACH_BCM933XX 4
19950 +
19951 +/*
19952 * Valid machtype for group TITAN
19953 */
19954 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
19955 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
19956 --- linux.old/include/asm-mips/cpu.h 2006-04-27 18:04:38.000000000 +0200
19957 +++ linux.dev/include/asm-mips/cpu.h 2006-04-27 19:24:19.000000000 +0200
19958 @@ -22,6 +22,11 @@
19959 spec.
19960 */
19961
19962 +#define PRID_COPT_MASK 0xff000000
19963 +#define PRID_COMP_MASK 0x00ff0000
19964 +#define PRID_IMP_MASK 0x0000ff00
19965 +#define PRID_REV_MASK 0x000000ff
19966 +
19967 #define PRID_COMP_LEGACY 0x000000
19968 #define PRID_COMP_MIPS 0x010000
19969 #define PRID_COMP_BROADCOM 0x020000
19970 @@ -58,6 +63,7 @@
19971 #define PRID_IMP_RM7000 0x2700
19972 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
19973 #define PRID_IMP_RM9000 0x3400
19974 +#define PRID_IMP_BCM4710 0x4000
19975 #define PRID_IMP_R5432 0x5400
19976 #define PRID_IMP_R5500 0x5500
19977 #define PRID_IMP_4KC 0x8000
19978 @@ -66,10 +72,16 @@
19979 #define PRID_IMP_4KEC 0x8400
19980 #define PRID_IMP_4KSC 0x8600
19981 #define PRID_IMP_25KF 0x8800
19982 +#define PRID_IMP_BCM3302 0x9000
19983 +#define PRID_IMP_BCM3303 0x9100
19984 #define PRID_IMP_24K 0x9300
19985
19986 #define PRID_IMP_UNKNOWN 0xff00
19987
19988 +#define BCM330X(id) \
19989 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
19990 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
19991 +
19992 /*
19993 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
19994 */
19995 @@ -174,7 +186,9 @@
19996 #define CPU_AU1550 57
19997 #define CPU_24K 58
19998 #define CPU_AU1200 59
19999 -#define CPU_LAST 59
20000 +#define CPU_BCM4710 60
20001 +#define CPU_BCM3302 61
20002 +#define CPU_LAST 61
20003
20004 /*
20005 * ISA Level encodings
20006 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
20007 --- linux.old/include/asm-mips/r4kcache.h 2006-04-27 18:04:38.000000000 +0200
20008 +++ linux.dev/include/asm-mips/r4kcache.h 2006-04-27 19:24:19.000000000 +0200
20009 @@ -658,4 +658,17 @@
20010 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
20011 }
20012
20013 +extern inline void fill_icache_line(unsigned long addr)
20014 +{
20015 + __asm__ __volatile__(
20016 + ".set noreorder\n\t"
20017 + ".set mips3\n\t"
20018 + "cache %1, (%0)\n\t"
20019 + ".set mips0\n\t"
20020 + ".set reorder"
20021 + :
20022 + : "r" (addr),
20023 + "i" (Fill));
20024 +}
20025 +
20026 #endif /* __ASM_R4KCACHE_H */
20027 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
20028 --- linux.old/include/asm-mips/serial.h 2006-04-27 18:04:38.000000000 +0200
20029 +++ linux.dev/include/asm-mips/serial.h 2006-04-27 19:24:19.000000000 +0200
20030 @@ -223,6 +223,13 @@
20031 #define TXX927_SERIAL_PORT_DEFNS
20032 #endif
20033
20034 +#ifdef CONFIG_BCM947XX
20035 +/* reserve 4 ports to be configured at runtime */
20036 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
20037 +#else
20038 +#define BCM947XX_SERIAL_PORT_DEFNS
20039 +#endif
20040 +
20041 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
20042 #define STD_SERIAL_PORT_DEFNS \
20043 /* UART CLK PORT IRQ FLAGS */ \
20044 @@ -470,6 +477,7 @@
20045 #define SERIAL_PORT_DFNS \
20046 ATLAS_SERIAL_PORT_DEFNS \
20047 AU1000_SERIAL_PORT_DEFNS \
20048 + BCM947XX_SERIAL_PORT_DEFNS \
20049 COBALT_SERIAL_PORT_DEFNS \
20050 DDB5477_SERIAL_PORT_DEFNS \
20051 EV96100_SERIAL_PORT_DEFNS \
20052 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
20053 --- linux.old/init/do_mounts.c 2006-04-27 18:04:38.000000000 +0200
20054 +++ linux.dev/init/do_mounts.c 2006-04-27 19:24:19.000000000 +0200
20055 @@ -254,7 +254,13 @@
20056 { "ftlb", 0x2c08 },
20057 { "ftlc", 0x2c10 },
20058 { "ftld", 0x2c18 },
20059 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
20060 { "mtdblock", 0x1f00 },
20061 + { "mtdblock0",0x1f00 },
20062 + { "mtdblock1",0x1f01 },
20063 + { "mtdblock2",0x1f02 },
20064 + { "mtdblock3",0x1f03 },
20065 +#endif
20066 { "nb", 0x2b00 },
20067 { NULL, 0 }
20068 };
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