d662b4c015141f4689243275b8d084d2af0cb468
[openwrt/svn-archive/archive.git] / openwrt / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -Naur linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
2 --- linux.old/arch/mips/Makefile 2006-04-06 15:38:09.000000000 +0200
3 +++ linux.dev/arch/mips/Makefile 2006-04-06 15:34:15.000000000 +0200
4 @@ -726,6 +726,19 @@
5 endif
6
7 #
8 +# Broadcom BCM947XX variants
9 +#
10 +ifdef CONFIG_BCM947XX
11 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
12 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
13 +LOADADDR := 0x80001000
14 +
15 +zImage: vmlinux
16 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
17 +export LOADADDR
18 +endif
19 +
20 +#
21 # Choosing incompatible machines durings configuration will result in
22 # error messages during linking. Select a default linkscript if
23 # none has been choosen above.
24 @@ -778,6 +791,7 @@
25 $(MAKE) -C arch/$(ARCH)/tools clean
26 $(MAKE) -C arch/mips/baget clean
27 $(MAKE) -C arch/mips/lasat clean
28 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
29
30 archmrproper:
31 @$(MAKEBOOT) mrproper
32 diff -Naur linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
33 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
34 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-04-06 15:34:14.000000000 +0200
35 @@ -0,0 +1,15 @@
36 +#
37 +# Makefile for the BCM947xx specific kernel interface routines
38 +# under Linux.
39 +#
40 +
41 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
42 +
43 +O_TARGET := bcm947xx.o
44 +
45 +export-objs := nvram_linux.o setup.o
46 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
47 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
48 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
49 +
50 +include $(TOPDIR)/Rules.make
51 diff -Naur linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
52 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
53 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-04-06 15:34:14.000000000 +0200
54 @@ -0,0 +1,234 @@
55 +/*
56 + * NVRAM variable manipulation (Linux kernel half)
57 + *
58 + * Copyright 2001-2003, Broadcom Corporation
59 + * All Rights Reserved.
60 + *
61 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
62 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
63 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
64 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
65 + *
66 + * $Id$
67 + */
68 +
69 +#include <linux/config.h>
70 +#include <linux/init.h>
71 +#include <linux/module.h>
72 +#include <linux/kernel.h>
73 +#include <linux/string.h>
74 +#include <asm/io.h>
75 +#include <asm/uaccess.h>
76 +
77 +#include <typedefs.h>
78 +#include <osl.h>
79 +#include <bcmendian.h>
80 +#include <bcmutils.h>
81 +
82 +#define NVRAM_SIZE (0x1ff0)
83 +static char _nvdata[NVRAM_SIZE] __initdata;
84 +static char _valuestr[256] __initdata;
85 +
86 +/*
87 + * TLV types. These codes are used in the "type-length-value"
88 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
89 + *
90 + * The layout of the flash/nvram is as follows:
91 + *
92 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
93 + *
94 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
95 + * The "length" field marks the length of the data section, not
96 + * including the type and length fields.
97 + *
98 + * Environment variables are stored as follows:
99 + *
100 + * <type_env> <length> <flags> <name> = <value>
101 + *
102 + * If bit 0 (low bit) is set, the length is an 8-bit value.
103 + * If bit 0 (low bit) is clear, the length is a 16-bit value
104 + *
105 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
106 + * indicates the size of the length field.
107 + *
108 + * Flags are from the constants below:
109 + *
110 + */
111 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
112 +#define ENV_LENGTH_8BITS 0x01
113 +
114 +#define ENV_TYPE_USER 0x80
115 +
116 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
117 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
118 +
119 +/*
120 + * The actual TLV types we support
121 + */
122 +
123 +#define ENV_TLV_TYPE_END 0x00
124 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
125 +
126 +/*
127 + * Environment variable flags
128 + */
129 +
130 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
131 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
132 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
133 +
134 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
135 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
136 +
137 +
138 +/* *********************************************************************
139 + * _nvram_read(buffer,offset,length)
140 + *
141 + * Read data from the NVRAM device
142 + *
143 + * Input parameters:
144 + * buffer - destination buffer
145 + * offset - offset of data to read
146 + * length - number of bytes to read
147 + *
148 + * Return value:
149 + * number of bytes read, or <0 if error occured
150 + ********************************************************************* */
151 +static int
152 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
153 +{
154 + int i;
155 + if (offset > NVRAM_SIZE)
156 + return -1;
157 +
158 + for ( i = 0; i < length; i++) {
159 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
160 + }
161 + return length;
162 +}
163 +
164 +
165 +static char*
166 +_strnchr(const char *dest,int c,size_t cnt)
167 +{
168 + while (*dest && (cnt > 0)) {
169 + if (*dest == c) return (char *) dest;
170 + dest++;
171 + cnt--;
172 + }
173 + return NULL;
174 +}
175 +
176 +
177 +
178 +/*
179 + * Core support API: Externally visible.
180 + */
181 +
182 +/*
183 + * Get the value of an NVRAM variable
184 + * @param name name of variable to get
185 + * @return value of variable or NULL if undefined
186 + */
187 +
188 +char*
189 +cfe_env_get(unsigned char *nv_buf, char* name)
190 +{
191 + int size;
192 + unsigned char *buffer;
193 + unsigned char *ptr;
194 + unsigned char *envval;
195 + unsigned int reclen;
196 + unsigned int rectype;
197 + int offset;
198 + int flg;
199 +
200 + size = NVRAM_SIZE;
201 + buffer = &_nvdata[0];
202 +
203 + ptr = buffer;
204 + offset = 0;
205 +
206 + /* Read the record type and length */
207 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
208 + goto error;
209 + }
210 +
211 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
212 +
213 + /* Adjust pointer for TLV type */
214 + rectype = *(ptr);
215 + offset++;
216 + size--;
217 +
218 + /*
219 + * Read the length. It can be either 1 or 2 bytes
220 + * depending on the code
221 + */
222 + if (rectype & ENV_LENGTH_8BITS) {
223 + /* Read the record type and length - 8 bits */
224 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
225 + goto error;
226 + }
227 + reclen = *(ptr);
228 + size--;
229 + offset++;
230 + }
231 + else {
232 + /* Read the record type and length - 16 bits, MSB first */
233 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
234 + goto error;
235 + }
236 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
237 + size -= 2;
238 + offset += 2;
239 + }
240 +
241 + if (reclen > size)
242 + break; /* should not happen, bad NVRAM */
243 +
244 + switch (rectype) {
245 + case ENV_TLV_TYPE_ENV:
246 + /* Read the TLV data */
247 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
248 + goto error;
249 + flg = *ptr++;
250 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
251 + if (envval) {
252 + *envval++ = '\0';
253 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
254 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
255 +#if 0
256 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
257 +#endif
258 + if(!strcmp(ptr, name)){
259 + return _valuestr;
260 + }
261 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
262 + return _valuestr;
263 + }
264 + break;
265 +
266 + default:
267 + /* Unknown TLV type, skip it. */
268 + break;
269 + }
270 +
271 + /*
272 + * Advance to next TLV
273 + */
274 +
275 + size -= (int)reclen;
276 + offset += reclen;
277 +
278 + /* Read the next record type */
279 + ptr = buffer;
280 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
281 + goto error;
282 + }
283 +
284 +error:
285 + return NULL;
286 +
287 +}
288 +
289 diff -Naur linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
290 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
291 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-04-06 15:34:14.000000000 +0200
292 @@ -0,0 +1,33 @@
293 +#
294 +# Makefile for Broadcom BCM947XX boards
295 +#
296 +# Copyright 2001-2003, Broadcom Corporation
297 +# All Rights Reserved.
298 +#
299 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
300 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
301 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
302 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
303 +#
304 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
305 +#
306 +
307 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
308 +SYSTEM ?= $(TOPDIR)/vmlinux
309 +
310 +all: vmlinuz
311 +
312 +# Don't build dependencies, this may die if $(CC) isn't gcc
313 +dep:
314 +
315 +# Create a gzipped version named vmlinuz for compatibility
316 +vmlinuz: piggy
317 + gzip -c9 $< > $@
318 +
319 +piggy: $(SYSTEM)
320 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
321 +
322 +mrproper: clean
323 +
324 +clean:
325 + rm -f vmlinuz piggy
326 diff -Naur linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
327 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
328 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-04-06 15:34:14.000000000 +0200
329 @@ -0,0 +1,15 @@
330 +#
331 +# Makefile for the BCM947xx specific kernel interface routines
332 +# under Linux.
333 +#
334 +
335 +.S.s:
336 + $(CPP) $(AFLAGS) $< -o $*.s
337 +.S.o:
338 + $(CC) $(AFLAGS) -c $< -o $*.o
339 +
340 +O_TARGET := brcm.o
341 +
342 +obj-y := int-handler.o irq.o
343 +
344 +include $(TOPDIR)/Rules.make
345 diff -Naur linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
346 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
347 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-04-06 15:34:14.000000000 +0200
348 @@ -0,0 +1,51 @@
349 +/*
350 + * Generic interrupt handler for Broadcom MIPS boards
351 + *
352 + * Copyright 2004, Broadcom Corporation
353 + * All Rights Reserved.
354 + *
355 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
356 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
357 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
358 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
359 + *
360 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
361 + */
362 +
363 +#include <linux/config.h>
364 +
365 +#include <asm/asm.h>
366 +#include <asm/mipsregs.h>
367 +#include <asm/regdef.h>
368 +#include <asm/stackframe.h>
369 +
370 +/*
371 + * MIPS IRQ Source
372 + * -------- ------
373 + * 0 Software (ignored)
374 + * 1 Software (ignored)
375 + * 2 Combined hardware interrupt (hw0)
376 + * 3 Hardware
377 + * 4 Hardware
378 + * 5 Hardware
379 + * 6 Hardware
380 + * 7 R4k timer
381 + */
382 +
383 + .text
384 + .set noreorder
385 + .set noat
386 + .align 5
387 + NESTED(brcmIRQ, PT_SIZE, sp)
388 + SAVE_ALL
389 + CLI
390 + .set at
391 + .set noreorder
392 +
393 + jal brcm_irq_dispatch
394 + move a0, sp
395 +
396 + j ret_from_irq
397 + nop
398 +
399 + END(brcmIRQ)
400 diff -Naur linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
401 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
402 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-04-06 15:34:14.000000000 +0200
403 @@ -0,0 +1,130 @@
404 +/*
405 + * Generic interrupt control functions for Broadcom MIPS boards
406 + *
407 + * Copyright 2004, Broadcom Corporation
408 + * All Rights Reserved.
409 + *
410 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
411 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
412 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
413 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
414 + *
415 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
416 + */
417 +
418 +#include <linux/config.h>
419 +#include <linux/init.h>
420 +#include <linux/kernel.h>
421 +#include <linux/types.h>
422 +#include <linux/interrupt.h>
423 +#include <linux/irq.h>
424 +
425 +#include <asm/irq.h>
426 +#include <asm/mipsregs.h>
427 +#include <asm/gdb-stub.h>
428 +
429 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
430 +
431 +extern asmlinkage void brcmIRQ(void);
432 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
433 +
434 +void
435 +brcm_irq_dispatch(struct pt_regs *regs)
436 +{
437 + u32 cause;
438 +
439 + cause = read_c0_cause() &
440 + read_c0_status() &
441 + CAUSEF_IP;
442 +
443 +#ifdef CONFIG_KERNPROF
444 + change_c0_status(cause | 1, 1);
445 +#else
446 + clear_c0_status(cause);
447 +#endif
448 +
449 + if (cause & CAUSEF_IP7)
450 + do_IRQ(7, regs);
451 + if (cause & CAUSEF_IP2)
452 + do_IRQ(2, regs);
453 + if (cause & CAUSEF_IP3)
454 + do_IRQ(3, regs);
455 + if (cause & CAUSEF_IP4)
456 + do_IRQ(4, regs);
457 + if (cause & CAUSEF_IP5)
458 + do_IRQ(5, regs);
459 + if (cause & CAUSEF_IP6)
460 + do_IRQ(6, regs);
461 +}
462 +
463 +static void
464 +enable_brcm_irq(unsigned int irq)
465 +{
466 + if (irq < 8)
467 + set_c0_status(1 << (irq + 8));
468 + else
469 + set_c0_status(IE_IRQ0);
470 +}
471 +
472 +static void
473 +disable_brcm_irq(unsigned int irq)
474 +{
475 + if (irq < 8)
476 + clear_c0_status(1 << (irq + 8));
477 + else
478 + clear_c0_status(IE_IRQ0);
479 +}
480 +
481 +static void
482 +ack_brcm_irq(unsigned int irq)
483 +{
484 + /* Already done in brcm_irq_dispatch */
485 +}
486 +
487 +static unsigned int
488 +startup_brcm_irq(unsigned int irq)
489 +{
490 + enable_brcm_irq(irq);
491 +
492 + return 0; /* never anything pending */
493 +}
494 +
495 +static void
496 +end_brcm_irq(unsigned int irq)
497 +{
498 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
499 + enable_brcm_irq(irq);
500 +}
501 +
502 +static struct hw_interrupt_type brcm_irq_type = {
503 + typename: "MIPS",
504 + startup: startup_brcm_irq,
505 + shutdown: disable_brcm_irq,
506 + enable: enable_brcm_irq,
507 + disable: disable_brcm_irq,
508 + ack: ack_brcm_irq,
509 + end: end_brcm_irq,
510 + NULL
511 +};
512 +
513 +void __init
514 +init_IRQ(void)
515 +{
516 + int i;
517 +
518 + for (i = 0; i < NR_IRQS; i++) {
519 + irq_desc[i].status = IRQ_DISABLED;
520 + irq_desc[i].action = 0;
521 + irq_desc[i].depth = 1;
522 + irq_desc[i].handler = &brcm_irq_type;
523 + }
524 +
525 + set_except_vector(0, brcmIRQ);
526 + change_c0_status(ST0_IM, ALLINTS);
527 +
528 +#ifdef CONFIG_REMOTE_DEBUG
529 + printk("Breaking into debugger...\n");
530 + set_debug_traps();
531 + breakpoint();
532 +#endif
533 +}
534 diff -Naur linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
535 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
536 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-04-06 15:34:14.000000000 +0200
537 @@ -0,0 +1,158 @@
538 +/*
539 + * GPIO char driver
540 + *
541 + * Copyright 2005, Broadcom Corporation
542 + * All Rights Reserved.
543 + *
544 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
545 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
546 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
547 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
548 + *
549 + * $Id$
550 + */
551 +
552 +#include <linux/module.h>
553 +#include <linux/init.h>
554 +#include <linux/fs.h>
555 +#include <linux/miscdevice.h>
556 +#include <asm/uaccess.h>
557 +
558 +#include <typedefs.h>
559 +#include <bcmutils.h>
560 +#include <sbutils.h>
561 +#include <bcmdevs.h>
562 +
563 +static sb_t *gpio_sbh;
564 +static int gpio_major;
565 +static devfs_handle_t gpio_dir;
566 +static struct {
567 + char *name;
568 + devfs_handle_t handle;
569 +} gpio_file[] = {
570 + { "in", NULL },
571 + { "out", NULL },
572 + { "outen", NULL },
573 + { "control", NULL }
574 +};
575 +
576 +static int
577 +gpio_open(struct inode *inode, struct file * file)
578 +{
579 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
580 + return -ENODEV;
581 +
582 + MOD_INC_USE_COUNT;
583 + return 0;
584 +}
585 +
586 +static int
587 +gpio_release(struct inode *inode, struct file * file)
588 +{
589 + MOD_DEC_USE_COUNT;
590 + return 0;
591 +}
592 +
593 +static ssize_t
594 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
595 +{
596 + u32 val;
597 +
598 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
599 + case 0:
600 + val = sb_gpioin(gpio_sbh);
601 + break;
602 + case 1:
603 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
604 + break;
605 + case 2:
606 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
607 + break;
608 + case 3:
609 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
610 + break;
611 + default:
612 + return -ENODEV;
613 + }
614 +
615 + if (put_user(val, (u32 *) buf))
616 + return -EFAULT;
617 +
618 + return sizeof(val);
619 +}
620 +
621 +static ssize_t
622 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
623 +{
624 + u32 val;
625 +
626 + if (get_user(val, (u32 *) buf))
627 + return -EFAULT;
628 +
629 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
630 + case 0:
631 + return -EACCES;
632 + case 1:
633 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
634 + break;
635 + case 2:
636 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
637 + break;
638 + case 3:
639 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
640 + break;
641 + default:
642 + return -ENODEV;
643 + }
644 +
645 + return sizeof(val);
646 +}
647 +
648 +static struct file_operations gpio_fops = {
649 + owner: THIS_MODULE,
650 + open: gpio_open,
651 + release: gpio_release,
652 + read: gpio_read,
653 + write: gpio_write,
654 +};
655 +
656 +static int __init
657 +gpio_init(void)
658 +{
659 + int i;
660 +
661 + if (!(gpio_sbh = sb_kattach()))
662 + return -ENODEV;
663 +
664 + sb_gpiosetcore(gpio_sbh);
665 +
666 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
667 + return gpio_major;
668 +
669 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
670 +
671 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
672 + gpio_file[i].handle = devfs_register(gpio_dir,
673 + gpio_file[i].name,
674 + DEVFS_FL_DEFAULT, gpio_major, i,
675 + S_IFCHR | S_IRUGO | S_IWUGO,
676 + &gpio_fops, NULL);
677 + }
678 +
679 + return 0;
680 +}
681 +
682 +static void __exit
683 +gpio_exit(void)
684 +{
685 + int i;
686 +
687 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
688 + devfs_unregister(gpio_file[i].handle);
689 + devfs_unregister(gpio_dir);
690 + devfs_unregister_chrdev(gpio_major, "gpio");
691 + sb_detach(gpio_sbh);
692 +}
693 +
694 +module_init(gpio_init);
695 +module_exit(gpio_exit);
696 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
697 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
698 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-04-06 15:34:14.000000000 +0200
699 @@ -0,0 +1,391 @@
700 +/*
701 + * Broadcom device-specific manifest constants.
702 + *
703 + * Copyright 2005, Broadcom Corporation
704 + * All Rights Reserved.
705 + *
706 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
707 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
708 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
709 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
710 + * $Id$
711 + */
712 +
713 +#ifndef _BCMDEVS_H
714 +#define _BCMDEVS_H
715 +
716 +
717 +/* Known PCI vendor Id's */
718 +#define VENDOR_EPIGRAM 0xfeda
719 +#define VENDOR_BROADCOM 0x14e4
720 +#define VENDOR_3COM 0x10b7
721 +#define VENDOR_NETGEAR 0x1385
722 +#define VENDOR_DIAMOND 0x1092
723 +#define VENDOR_DELL 0x1028
724 +#define VENDOR_HP 0x0e11
725 +#define VENDOR_APPLE 0x106b
726 +
727 +/* PCI Device Id's */
728 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
729 +#define BCM4211_DEVICE_ID 0x4211
730 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
731 +#define BCM4231_DEVICE_ID 0x4231
732 +
733 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
734 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
735 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
736 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
737 +
738 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
739 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
740 +
741 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
742 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
743 +
744 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
745 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
746 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
747 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
748 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
749 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
750 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
751 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
752 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
753 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
754 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
755 +
756 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
757 +
758 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
759 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
760 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
761 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
762 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
763 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
764 +
765 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
766 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
767 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
768 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
769 +
770 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
771 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
772 +
773 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
774 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
775 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
776 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
777 +
778 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
779 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
780 +#define BCM4306_D11G_ID2 0x4325
781 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
782 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
783 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
784 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
785 +
786 +#define BCM4309_PKG_ID 1 /* 4309 package id */
787 +
788 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
789 +#define BCM4303_PKG_ID 2 /* 4303 package id */
790 +
791 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
792 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
793 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
794 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
795 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
796 +
797 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
798 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
799 +
800 +
801 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
802 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
803 +
804 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
805 +
806 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
807 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
808 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
809 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
810 +
811 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
812 +
813 +/* Address map */
814 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
815 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
816 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
817 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
818 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
819 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
820 +
821 +/* Core register space */
822 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
823 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
824 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
825 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
826 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
827 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
828 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
829 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
830 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
831 +
832 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
833 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
834 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
835 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
836 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
837 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
838 +
839 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
840 +
841 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
842 +
843 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
844 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
845 +
846 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
847 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
848 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
849 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
850 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
851 +
852 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
853 +
854 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
855 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
856 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
857 +
858 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
859 +
860 +/* PCMCIA vendor Id's */
861 +
862 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
863 +
864 +/* SDIO vendor Id's */
865 +#define VENDOR_BROADCOM_SDIO 0x00BF
866 +
867 +
868 +/* boardflags */
869 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
870 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
871 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
872 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
873 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
874 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
875 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
876 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
877 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
878 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
879 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
880 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
881 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
882 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
883 +
884 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
885 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
886 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
887 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
888 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
889 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
890 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
891 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
892 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
893 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
894 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
895 +
896 +/* Bus types */
897 +#define SB_BUS 0 /* Silicon Backplane */
898 +#define PCI_BUS 1 /* PCI target */
899 +#define PCMCIA_BUS 2 /* PCMCIA target */
900 +#define SDIO_BUS 3 /* SDIO target */
901 +#define JTAG_BUS 4 /* JTAG */
902 +
903 +/* Allows optimization for single-bus support */
904 +#ifdef BCMBUSTYPE
905 +#define BUSTYPE(bus) (BCMBUSTYPE)
906 +#else
907 +#define BUSTYPE(bus) (bus)
908 +#endif
909 +
910 +/* power control defines */
911 +#define PLL_DELAY 150 /* us pll on delay */
912 +#define FREF_DELAY 200 /* us fref change delay */
913 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
914 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
915 +
916 +/* Reference Board Types */
917 +
918 +#define BU4710_BOARD 0x0400
919 +#define VSIM4710_BOARD 0x0401
920 +#define QT4710_BOARD 0x0402
921 +
922 +#define BU4610_BOARD 0x0403
923 +#define VSIM4610_BOARD 0x0404
924 +
925 +#define BU4307_BOARD 0x0405
926 +#define BCM94301CB_BOARD 0x0406
927 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
928 +#define BCM94301MP_BOARD 0x0407
929 +#define BCM94307MP_BOARD 0x0408
930 +#define BCMAP4307_BOARD 0x0409
931 +
932 +#define BU4309_BOARD 0x040a
933 +#define BCM94309CB_BOARD 0x040b
934 +#define BCM94309MP_BOARD 0x040c
935 +#define BCM4309AP_BOARD 0x040d
936 +
937 +#define BCM94302MP_BOARD 0x040e
938 +
939 +#define VSIM4310_BOARD 0x040f
940 +#define BU4711_BOARD 0x0410
941 +#define BCM94310U_BOARD 0x0411
942 +#define BCM94310AP_BOARD 0x0412
943 +#define BCM94310MP_BOARD 0x0414
944 +
945 +#define BU4306_BOARD 0x0416
946 +#define BCM94306CB_BOARD 0x0417
947 +#define BCM94306MP_BOARD 0x0418
948 +
949 +#define BCM94710D_BOARD 0x041a
950 +#define BCM94710R1_BOARD 0x041b
951 +#define BCM94710R4_BOARD 0x041c
952 +#define BCM94710AP_BOARD 0x041d
953 +
954 +
955 +#define BU2050_BOARD 0x041f
956 +
957 +
958 +#define BCM94309G_BOARD 0x0421
959 +
960 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
961 +
962 +#define BU4704_BOARD 0x0423
963 +#define BU4702_BOARD 0x0424
964 +
965 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
966 +
967 +#define BU4317_BOARD 0x0426
968 +
969 +
970 +#define BCM94702MN_BOARD 0x0428
971 +
972 +/* BCM4702 1U CompactPCI Board */
973 +#define BCM94702CPCI_BOARD 0x0429
974 +
975 +/* BCM4702 with BCM95380 VLAN Router */
976 +#define BCM95380RR_BOARD 0x042a
977 +
978 +/* cb4306 with SiGe PA */
979 +#define BCM94306CBSG_BOARD 0x042b
980 +
981 +/* mp4301 with 2050 radio */
982 +#define BCM94301MPL_BOARD 0x042c
983 +
984 +/* cb4306 with SiGe PA */
985 +#define PCSG94306_BOARD 0x042d
986 +
987 +/* bu4704 with sdram */
988 +#define BU4704SD_BOARD 0x042e
989 +
990 +/* Dual 11a/11g Router */
991 +#define BCM94704AGR_BOARD 0x042f
992 +
993 +/* 11a-only minipci */
994 +#define BCM94308MP_BOARD 0x0430
995 +
996 +
997 +
998 +/* BCM94317 boards */
999 +#define BCM94317CB_BOARD 0x0440
1000 +#define BCM94317MP_BOARD 0x0441
1001 +#define BCM94317PCMCIA_BOARD 0x0442
1002 +#define BCM94317SDIO_BOARD 0x0443
1003 +
1004 +#define BU4712_BOARD 0x0444
1005 +#define BU4712SD_BOARD 0x045d
1006 +#define BU4712L_BOARD 0x045f
1007 +
1008 +/* BCM4712 boards */
1009 +#define BCM94712AP_BOARD 0x0445
1010 +#define BCM94712P_BOARD 0x0446
1011 +
1012 +/* BCM4318 boards */
1013 +#define BU4318_BOARD 0x0447
1014 +#define CB4318_BOARD 0x0448
1015 +#define MPG4318_BOARD 0x0449
1016 +#define MP4318_BOARD 0x044a
1017 +#define SD4318_BOARD 0x044b
1018 +
1019 +/* BCM63XX boards */
1020 +#define BCM96338_BOARD 0x6338
1021 +#define BCM96345_BOARD 0x6345
1022 +#define BCM96348_BOARD 0x6348
1023 +
1024 +/* Another mp4306 with SiGe */
1025 +#define BCM94306P_BOARD 0x044c
1026 +
1027 +/* CF-like 4317 modules */
1028 +#define BCM94317CF_BOARD 0x044d
1029 +
1030 +/* mp4303 */
1031 +#define BCM94303MP_BOARD 0x044e
1032 +
1033 +/* mpsgh4306 */
1034 +#define BCM94306MPSGH_BOARD 0x044f
1035 +
1036 +/* BRCM 4306 w/ Front End Modules */
1037 +#define BCM94306MPM 0x0450
1038 +#define BCM94306MPL 0x0453
1039 +
1040 +/* 4712agr */
1041 +#define BCM94712AGR_BOARD 0x0451
1042 +
1043 +/* The real CF 4317 board */
1044 +#define CFI4317_BOARD 0x0452
1045 +
1046 +/* pcmcia 4303 */
1047 +#define PC4303_BOARD 0x0454
1048 +
1049 +/* 5350K */
1050 +#define BCM95350K_BOARD 0x0455
1051 +
1052 +/* 5350R */
1053 +#define BCM95350R_BOARD 0x0456
1054 +
1055 +/* 4306mplna */
1056 +#define BCM94306MPLNA_BOARD 0x0457
1057 +
1058 +/* 4320 boards */
1059 +#define BU4320_BOARD 0x0458
1060 +#define BU4320S_BOARD 0x0459
1061 +#define BCM94320PH_BOARD 0x045a
1062 +
1063 +/* 4306mph */
1064 +#define BCM94306MPH_BOARD 0x045b
1065 +
1066 +/* 4306pciv */
1067 +#define BCM94306PCIV_BOARD 0x045c
1068 +
1069 +#define BU4712SD_BOARD 0x045d
1070 +
1071 +#define BCM94320PFLSH_BOARD 0x045e
1072 +
1073 +#define BU4712L_BOARD 0x045f
1074 +#define BCM94712LGR_BOARD 0x0460
1075 +#define BCM94320R_BOARD 0x0461
1076 +
1077 +#define BU5352_BOARD 0x0462
1078 +
1079 +#define BCM94318MPGH_BOARD 0x0463
1080 +
1081 +
1082 +#define BCM95352GR_BOARD 0x0467
1083 +
1084 +/* bcm95351agr */
1085 +#define BCM95351AGR_BOARD 0x0470
1086 +
1087 +/* # of GPIO pins */
1088 +#define GPIO_NUMPINS 16
1089 +
1090 +#endif /* _BCMDEVS_H */
1091 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
1092 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
1093 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-04-06 15:34:14.000000000 +0200
1094 @@ -0,0 +1,152 @@
1095 +/*
1096 + * local version of endian.h - byte order defines
1097 + *
1098 + * Copyright 2005, Broadcom Corporation
1099 + * All Rights Reserved.
1100 + *
1101 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1102 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1103 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1104 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1105 + *
1106 + * $Id$
1107 +*/
1108 +
1109 +#ifndef _BCMENDIAN_H_
1110 +#define _BCMENDIAN_H_
1111 +
1112 +#include <typedefs.h>
1113 +
1114 +/* Byte swap a 16 bit value */
1115 +#define BCMSWAP16(val) \
1116 + ((uint16)( \
1117 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
1118 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
1119 +
1120 +/* Byte swap a 32 bit value */
1121 +#define BCMSWAP32(val) \
1122 + ((uint32)( \
1123 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
1124 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
1125 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
1126 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
1127 +
1128 +/* 2 Byte swap a 32 bit value */
1129 +#define BCMSWAP32BY16(val) \
1130 + ((uint32)( \
1131 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
1132 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
1133 +
1134 +
1135 +static INLINE uint16
1136 +bcmswap16(uint16 val)
1137 +{
1138 + return BCMSWAP16(val);
1139 +}
1140 +
1141 +static INLINE uint32
1142 +bcmswap32(uint32 val)
1143 +{
1144 + return BCMSWAP32(val);
1145 +}
1146 +
1147 +static INLINE uint32
1148 +bcmswap32by16(uint32 val)
1149 +{
1150 + return BCMSWAP32BY16(val);
1151 +}
1152 +
1153 +/* buf - start of buffer of shorts to swap */
1154 +/* len - byte length of buffer */
1155 +static INLINE void
1156 +bcmswap16_buf(uint16 *buf, uint len)
1157 +{
1158 + len = len/2;
1159 +
1160 + while(len--){
1161 + *buf = bcmswap16(*buf);
1162 + buf++;
1163 + }
1164 +}
1165 +
1166 +#ifndef hton16
1167 +#ifndef IL_BIGENDIAN
1168 +#define HTON16(i) BCMSWAP16(i)
1169 +#define hton16(i) bcmswap16(i)
1170 +#define hton32(i) bcmswap32(i)
1171 +#define ntoh16(i) bcmswap16(i)
1172 +#define ntoh32(i) bcmswap32(i)
1173 +#define ltoh16(i) (i)
1174 +#define ltoh32(i) (i)
1175 +#define htol16(i) (i)
1176 +#define htol32(i) (i)
1177 +#else
1178 +#define HTON16(i) (i)
1179 +#define hton16(i) (i)
1180 +#define hton32(i) (i)
1181 +#define ntoh16(i) (i)
1182 +#define ntoh32(i) (i)
1183 +#define ltoh16(i) bcmswap16(i)
1184 +#define ltoh32(i) bcmswap32(i)
1185 +#define htol16(i) bcmswap16(i)
1186 +#define htol32(i) bcmswap32(i)
1187 +#endif
1188 +#endif
1189 +
1190 +#ifndef IL_BIGENDIAN
1191 +#define ltoh16_buf(buf, i)
1192 +#define htol16_buf(buf, i)
1193 +#else
1194 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1195 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1196 +#endif
1197 +
1198 +/*
1199 +* load 16-bit value from unaligned little endian byte array.
1200 +*/
1201 +static INLINE uint16
1202 +ltoh16_ua(uint8 *bytes)
1203 +{
1204 + return (bytes[1]<<8)+bytes[0];
1205 +}
1206 +
1207 +/*
1208 +* load 32-bit value from unaligned little endian byte array.
1209 +*/
1210 +static INLINE uint32
1211 +ltoh32_ua(uint8 *bytes)
1212 +{
1213 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
1214 +}
1215 +
1216 +/*
1217 +* load 16-bit value from unaligned big(network) endian byte array.
1218 +*/
1219 +static INLINE uint16
1220 +ntoh16_ua(uint8 *bytes)
1221 +{
1222 + return (bytes[0]<<8)+bytes[1];
1223 +}
1224 +
1225 +/*
1226 +* load 32-bit value from unaligned big(network) endian byte array.
1227 +*/
1228 +static INLINE uint32
1229 +ntoh32_ua(uint8 *bytes)
1230 +{
1231 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
1232 +}
1233 +
1234 +#define ltoh_ua(ptr) ( \
1235 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1236 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
1237 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
1238 +)
1239 +
1240 +#define ntoh_ua(ptr) ( \
1241 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1242 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
1243 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
1244 +)
1245 +
1246 +#endif /* _BCMENDIAN_H_ */
1247 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
1248 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1249 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-04-06 15:34:14.000000000 +0200
1250 @@ -0,0 +1,141 @@
1251 +/*
1252 + * NVRAM variable manipulation
1253 + *
1254 + * Copyright 2005, Broadcom Corporation
1255 + * All Rights Reserved.
1256 + *
1257 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1258 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1259 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1260 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1261 + *
1262 + * $Id$
1263 + */
1264 +
1265 +#ifndef _bcmnvram_h_
1266 +#define _bcmnvram_h_
1267 +
1268 +#ifndef _LANGUAGE_ASSEMBLY
1269 +
1270 +#include <typedefs.h>
1271 +
1272 +struct nvram_header {
1273 + uint32 magic;
1274 + uint32 len;
1275 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
1276 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
1277 + uint32 config_ncdl; /* ncdl values for memc */
1278 +};
1279 +
1280 +struct nvram_tuple {
1281 + char *name;
1282 + char *value;
1283 + struct nvram_tuple *next;
1284 +};
1285 +
1286 +/*
1287 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1288 + * platforms.
1289 + */
1290 +extern int BCMINIT(nvram_init)(void *sbh);
1291 +
1292 +/*
1293 + * Disable NVRAM access. May be unnecessary or undefined on certain
1294 + * platforms.
1295 + */
1296 +extern void BCMINIT(nvram_exit)(void *sbh);
1297 +
1298 +/*
1299 + * Get the value of an NVRAM variable. The pointer returned may be
1300 + * invalid after a set.
1301 + * @param name name of variable to get
1302 + * @return value of variable or NULL if undefined
1303 + */
1304 +extern char * BCMINIT(nvram_get)(const char *name);
1305 +
1306 +/*
1307 + * Read the reset GPIO value from the nvram and set the GPIO
1308 + * as input
1309 + */
1310 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
1311 +
1312 +/*
1313 + * Get the value of an NVRAM variable.
1314 + * @param name name of variable to get
1315 + * @return value of variable or NUL if undefined
1316 + */
1317 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1318 +
1319 +/*
1320 + * Match an NVRAM variable.
1321 + * @param name name of variable to match
1322 + * @param match value to compare against value of variable
1323 + * @return TRUE if variable is defined and its value is string equal
1324 + * to match or FALSE otherwise
1325 + */
1326 +static INLINE int
1327 +nvram_match(char *name, char *match) {
1328 + const char *value = BCMINIT(nvram_get)(name);
1329 + return (value && !strcmp(value, match));
1330 +}
1331 +
1332 +/*
1333 + * Inversely match an NVRAM variable.
1334 + * @param name name of variable to match
1335 + * @param match value to compare against value of variable
1336 + * @return TRUE if variable is defined and its value is not string
1337 + * equal to invmatch or FALSE otherwise
1338 + */
1339 +static INLINE int
1340 +nvram_invmatch(char *name, char *invmatch) {
1341 + const char *value = BCMINIT(nvram_get)(name);
1342 + return (value && strcmp(value, invmatch));
1343 +}
1344 +
1345 +/*
1346 + * Set the value of an NVRAM variable. The name and value strings are
1347 + * copied into private storage. Pointers to previously set values
1348 + * may become invalid. The new value may be immediately
1349 + * retrieved but will not be permanently stored until a commit.
1350 + * @param name name of variable to set
1351 + * @param value value of variable
1352 + * @return 0 on success and errno on failure
1353 + */
1354 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1355 +
1356 +/*
1357 + * Unset an NVRAM variable. Pointers to previously set values
1358 + * remain valid until a set.
1359 + * @param name name of variable to unset
1360 + * @return 0 on success and errno on failure
1361 + * NOTE: use nvram_commit to commit this change to flash.
1362 + */
1363 +extern int BCMINIT(nvram_unset)(const char *name);
1364 +
1365 +/*
1366 + * Commit NVRAM variables to permanent storage. All pointers to values
1367 + * may be invalid after a commit.
1368 + * NVRAM values are undefined after a commit.
1369 + * @return 0 on success and errno on failure
1370 + */
1371 +extern int BCMINIT(nvram_commit)(void);
1372 +
1373 +/*
1374 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1375 + * @param buf buffer to store variables
1376 + * @param count size of buffer in bytes
1377 + * @return 0 on success and errno on failure
1378 + */
1379 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1380 +
1381 +#endif /* _LANGUAGE_ASSEMBLY */
1382 +
1383 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1384 +#define NVRAM_VERSION 1
1385 +#define NVRAM_HEADER_SIZE 20
1386 +#define NVRAM_SPACE 0x8000
1387 +
1388 +#define NVRAM_MAX_VALUE_LEN 255
1389 +#define NVRAM_MAX_PARAM_LEN 64
1390 +
1391 +#endif /* _bcmnvram_h_ */
1392 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
1393 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1394 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-04-06 15:34:14.000000000 +0200
1395 @@ -0,0 +1,23 @@
1396 +/*
1397 + * Misc useful routines to access NIC local SROM/OTP .
1398 + *
1399 + * Copyright 2005, Broadcom Corporation
1400 + * All Rights Reserved.
1401 + *
1402 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1403 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1404 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1405 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1406 + *
1407 + * $Id$
1408 + */
1409 +
1410 +#ifndef _bcmsrom_h_
1411 +#define _bcmsrom_h_
1412 +
1413 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
1414 +
1415 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1416 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1417 +
1418 +#endif /* _bcmsrom_h_ */
1419 diff -Naur linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
1420 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1421 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-04-06 17:07:30.000000000 +0200
1422 @@ -0,0 +1,287 @@
1423 +/*
1424 + * Misc useful os-independent macros and functions.
1425 + *
1426 + * Copyright 2005, Broadcom Corporation
1427 + * All Rights Reserved.
1428 + *
1429 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1430 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1431 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1432 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1433 + * $Id$
1434 + */
1435 +
1436 +#ifndef _bcmutils_h_
1437 +#define _bcmutils_h_
1438 +
1439 +/*** driver-only section ***/
1440 +#ifdef BCMDRIVER
1441 +#include <osl.h>
1442 +
1443 +#define _BCM_U 0x01 /* upper */
1444 +#define _BCM_L 0x02 /* lower */
1445 +#define _BCM_D 0x04 /* digit */
1446 +#define _BCM_C 0x08 /* cntrl */
1447 +#define _BCM_P 0x10 /* punct */
1448 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1449 +#define _BCM_X 0x40 /* hex digit */
1450 +#define _BCM_SP 0x80 /* hard space (0x20) */
1451 +
1452 +#define GPIO_PIN_NOTDEFINED 0x20
1453 +
1454 +extern unsigned char bcm_ctype[];
1455 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1456 +
1457 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1458 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1459 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1460 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1461 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1462 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1463 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1464 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1465 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1466 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1467 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1468 +
1469 +/*
1470 + * Spin at most 'us' microseconds while 'exp' is true.
1471 + * Caller should explicitly test 'exp' when this completes
1472 + * and take appropriate error action if 'exp' is still true.
1473 + */
1474 +#define SPINWAIT(exp, us) { \
1475 + uint countdown = (us) + 9; \
1476 + while ((exp) && (countdown >= 10)) {\
1477 + OSL_DELAY(10); \
1478 + countdown -= 10; \
1479 + } \
1480 +}
1481 +
1482 +/* string */
1483 +extern uint bcm_atoi(char *s);
1484 +extern uchar bcm_toupper(uchar c);
1485 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1486 +extern char *bcmstrstr(char *haystack, char *needle);
1487 +extern char *bcmstrcat(char *dest, const char *src);
1488 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1489 +/* ethernet address */
1490 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1491 +extern int bcm_ether_atoe(char *p, char *ea);
1492 +/* delay */
1493 +extern void bcm_mdelay(uint ms);
1494 +/* variable access */
1495 +extern char *getvar(char *vars, char *name);
1496 +extern int getintvar(char *vars, char *name);
1497 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1498 +#define bcmlog(fmt, a1, a2)
1499 +#define bcmdumplog(buf, size) *buf = '\0'
1500 +#define bcmdumplogent(buf, idx) -1
1501 +
1502 +#endif /* #ifdef BCMDRIVER */
1503 +
1504 +/*** driver/apps-shared section ***/
1505 +
1506 +#define BCME_STRLEN 64
1507 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
1508 +
1509 +
1510 +/*
1511 + * error codes could be added but the defined ones shouldn't be changed/deleted
1512 + * these error codes are exposed to the user code
1513 + * when ever a new error code is added to this list
1514 + * please update errorstring table with the related error string and
1515 + * update osl files with os specific errorcode map
1516 +*/
1517 +
1518 +#define BCME_ERROR -1 /* Error generic */
1519 +#define BCME_BADARG -2 /* Bad Argument */
1520 +#define BCME_BADOPTION -3 /* Bad option */
1521 +#define BCME_NOTUP -4 /* Not up */
1522 +#define BCME_NOTDOWN -5 /* Not down */
1523 +#define BCME_NOTAP -6 /* Not AP */
1524 +#define BCME_NOTSTA -7 /* Not STA */
1525 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
1526 +#define BCME_RADIOOFF -9 /* Radio Off */
1527 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
1528 +#define BCME_NOCLK -11 /* No Clock*/
1529 +#define BCME_BADRATESET -12 /* BAD RateSet*/
1530 +#define BCME_BADBAND -13 /* BAD Band */
1531 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
1532 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
1533 +#define BCME_BUSY -16 /* Busy*/
1534 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
1535 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
1536 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
1537 +#define BCME_BADCHAN -20 /* BAD Channel */
1538 +#define BCME_BADADDR -21 /* BAD Address*/
1539 +#define BCME_NORESOURCE -22 /* No resources*/
1540 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
1541 +#define BCME_BADLEN -24 /* Bad Length*/
1542 +#define BCME_NOTREADY -25 /* Not ready Yet*/
1543 +#define BCME_EPERM -26 /* Not Permitted */
1544 +#define BCME_NOMEM -27 /* No Memory */
1545 +#define BCME_ASSOCIATED -28 /* Associated */
1546 +#define BCME_RANGE -29 /* Range Error*/
1547 +#define BCME_NOTFOUND -30 /* Not found */
1548 +#define BCME_LAST BCME_NOTFOUND
1549 +
1550 +#ifndef ABS
1551 +#define ABS(a) (((a)<0)?-(a):(a))
1552 +#endif
1553 +
1554 +#ifndef MIN
1555 +#define MIN(a, b) (((a)<(b))?(a):(b))
1556 +#endif
1557 +
1558 +#ifndef MAX
1559 +#define MAX(a, b) (((a)>(b))?(a):(b))
1560 +#endif
1561 +
1562 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1563 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1564 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1565 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1566 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
1567 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1568 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1569 +
1570 +/* bit map related macros */
1571 +#ifndef setbit
1572 +#define NBBY 8 /* 8 bits per byte */
1573 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1574 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1575 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1576 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1577 +#endif
1578 +
1579 +#define NBITS(type) (sizeof(type) * 8)
1580 +#define NBITVAL(bits) (1 << (bits))
1581 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
1582 +
1583 +/* crc defines */
1584 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1585 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1586 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1587 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1588 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1589 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1590 +
1591 +/* bcm_format_flags() bit description structure */
1592 +typedef struct bcm_bit_desc {
1593 + uint32 bit;
1594 + char* name;
1595 +} bcm_bit_desc_t;
1596 +
1597 +/* tag_ID/length/value_buffer tuple */
1598 +typedef struct bcm_tlv {
1599 + uint8 id;
1600 + uint8 len;
1601 + uint8 data[1];
1602 +} bcm_tlv_t;
1603 +
1604 +/* Check that bcm_tlv_t fits into the given buflen */
1605 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
1606 +
1607 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1608 +#define ETHER_ADDR_STR_LEN 18
1609 +
1610 +/* unaligned load and store macros */
1611 +#ifdef IL_BIGENDIAN
1612 +static INLINE uint32
1613 +load32_ua(uint8 *a)
1614 +{
1615 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1616 +}
1617 +
1618 +static INLINE void
1619 +store32_ua(uint8 *a, uint32 v)
1620 +{
1621 + a[0] = (v >> 24) & 0xff;
1622 + a[1] = (v >> 16) & 0xff;
1623 + a[2] = (v >> 8) & 0xff;
1624 + a[3] = v & 0xff;
1625 +}
1626 +
1627 +static INLINE uint16
1628 +load16_ua(uint8 *a)
1629 +{
1630 + return ((a[0] << 8) | a[1]);
1631 +}
1632 +
1633 +static INLINE void
1634 +store16_ua(uint8 *a, uint16 v)
1635 +{
1636 + a[0] = (v >> 8) & 0xff;
1637 + a[1] = v & 0xff;
1638 +}
1639 +
1640 +#else
1641 +
1642 +static INLINE uint32
1643 +load32_ua(uint8 *a)
1644 +{
1645 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
1646 +}
1647 +
1648 +static INLINE void
1649 +store32_ua(uint8 *a, uint32 v)
1650 +{
1651 + a[3] = (v >> 24) & 0xff;
1652 + a[2] = (v >> 16) & 0xff;
1653 + a[1] = (v >> 8) & 0xff;
1654 + a[0] = v & 0xff;
1655 +}
1656 +
1657 +static INLINE uint16
1658 +load16_ua(uint8 *a)
1659 +{
1660 + return ((a[1] << 8) | a[0]);
1661 +}
1662 +
1663 +static INLINE void
1664 +store16_ua(uint8 *a, uint16 v)
1665 +{
1666 + a[1] = (v >> 8) & 0xff;
1667 + a[0] = v & 0xff;
1668 +}
1669 +
1670 +#endif
1671 +
1672 +/* externs */
1673 +/* crc */
1674 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
1675 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
1676 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
1677 +/* format/print */
1678 +/* IE parsing */
1679 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
1680 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
1681 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
1682 +
1683 +/* bcmerror*/
1684 +extern const char *bcmerrorstr(int bcmerror);
1685 +
1686 +/* multi-bool data type: set of bools, mbool is true if any is set */
1687 +typedef uint32 mbool;
1688 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
1689 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
1690 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
1691 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
1692 +
1693 +/* power conversion */
1694 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
1695 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
1696 +
1697 +/* generic datastruct to help dump routines */
1698 +struct fielddesc {
1699 + char *nameandfmt;
1700 + uint32 offset;
1701 + uint32 len;
1702 +};
1703 +
1704 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
1705 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
1706 +
1707 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
1708 +
1709 +#endif /* _bcmutils_h_ */
1710 diff -Naur linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
1711 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
1712 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-04-06 15:34:14.000000000 +0200
1713 @@ -0,0 +1,16 @@
1714 +/*
1715 + * Alternate include file for HND sbmips.h since CFE also ships with
1716 + * a sbmips.h.
1717 + *
1718 + * Copyright 2005, Broadcom Corporation
1719 + * All Rights Reserved.
1720 + *
1721 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1722 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1723 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1724 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1725 + *
1726 + * $Id$
1727 + */
1728 +
1729 +#include "sbmips.h"
1730 diff -Naur linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
1731 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
1732 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2006-04-06 15:34:14.000000000 +0200
1733 @@ -0,0 +1,371 @@
1734 +/*
1735 + * Linux OS Independent Layer
1736 + *
1737 + * Copyright 2005, Broadcom Corporation
1738 + * All Rights Reserved.
1739 + *
1740 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1741 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1742 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1743 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1744 + *
1745 + * $Id$
1746 + */
1747 +
1748 +#ifndef _linux_osl_h_
1749 +#define _linux_osl_h_
1750 +
1751 +#include <typedefs.h>
1752 +
1753 +/* use current 2.4.x calling conventions */
1754 +#include <linuxver.h>
1755 +
1756 +/* assert and panic */
1757 +#ifdef __GNUC__
1758 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
1759 +#if GCC_VERSION > 30100
1760 +#define ASSERT(exp) do {} while (0)
1761 +#else
1762 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
1763 +#define ASSERT(exp)
1764 +#endif
1765 +#endif
1766 +
1767 +/* microsecond delay */
1768 +#define OSL_DELAY(usec) osl_delay(usec)
1769 +extern void osl_delay(uint usec);
1770 +
1771 +/* PCMCIA attribute space access macros */
1772 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
1773 +struct pcmcia_dev {
1774 + dev_link_t link; /* PCMCIA device pointer */
1775 + dev_node_t node; /* PCMCIA node structure */
1776 + void *base; /* Mapped attribute memory window */
1777 + size_t size; /* Size of window */
1778 + void *drv; /* Driver data */
1779 +};
1780 +#endif
1781 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
1782 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
1783 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
1784 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
1785 +extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
1786 +extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
1787 +
1788 +/* PCI configuration space access macros */
1789 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
1790 + osl_pci_read_config((osh), (offset), (size))
1791 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
1792 + osl_pci_write_config((osh), (offset), (size), (val))
1793 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
1794 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
1795 +
1796 +/* PCI device bus # and slot # */
1797 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
1798 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
1799 +extern uint osl_pci_bus(osl_t *osh);
1800 +extern uint osl_pci_slot(osl_t *osh);
1801 +
1802 +/* OSL initialization */
1803 +extern osl_t *osl_attach(void *pdev);
1804 +extern void osl_detach(osl_t *osh);
1805 +
1806 +/* host/bus architecture-specific byte swap */
1807 +#define BUS_SWAP32(v) (v)
1808 +
1809 +/* general purpose memory allocation */
1810 +
1811 +#if defined(BCMDBG_MEM)
1812 +
1813 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
1814 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
1815 +#define MALLOCED(osh) osl_malloced((osh))
1816 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
1817 +extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
1818 +extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
1819 +extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
1820 +
1821 +#else
1822 +
1823 +#define MALLOC(osh, size) osl_malloc((osh), (size))
1824 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
1825 +#define MALLOCED(osh) osl_malloced((osh))
1826 +
1827 +#endif /* BCMDBG_MEM */
1828 +
1829 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
1830 +
1831 +extern void *osl_malloc(osl_t *osh, uint size);
1832 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
1833 +extern uint osl_malloced(osl_t *osh);
1834 +extern uint osl_malloc_failed(osl_t *osh);
1835 +
1836 +/* allocate/free shared (dma-able) consistent memory */
1837 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
1838 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
1839 + osl_dma_alloc_consistent((osh), (size), (pap))
1840 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
1841 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
1842 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
1843 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
1844 +
1845 +/* map/unmap direction */
1846 +#define DMA_TX 1
1847 +#define DMA_RX 2
1848 +
1849 +/* map/unmap shared (dma-able) memory */
1850 +#define DMA_MAP(osh, va, size, direction, p) \
1851 + osl_dma_map((osh), (va), (size), (direction))
1852 +#define DMA_UNMAP(osh, pa, size, direction, p) \
1853 + osl_dma_unmap((osh), (pa), (size), (direction))
1854 +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
1855 +extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
1856 +
1857 +/* register access macros */
1858 +#if defined(BCMJTAG)
1859 +#include <bcmjtag.h>
1860 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
1861 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
1862 +#endif
1863 +
1864 +/*
1865 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
1866 + * Macros expand to calls to functions defined in linux_osl.c .
1867 + */
1868 +#ifndef BINOSL
1869 +
1870 +/* string library, kernel mode */
1871 +#define printf(fmt, args...) printk(fmt, ## args)
1872 +#include <linux/kernel.h>
1873 +#include <linux/string.h>
1874 +
1875 +/* register access macros */
1876 +#if !defined(BCMJTAG)
1877 +#ifndef IL_BIGENDIAN
1878 +#define R_REG(r) ( \
1879 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
1880 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
1881 + readl((volatile uint32*)(r)) \
1882 +)
1883 +#define W_REG(r, v) do { \
1884 + switch (sizeof(*(r))) { \
1885 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
1886 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
1887 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
1888 + } \
1889 +} while (0)
1890 +#else /* IL_BIGENDIAN */
1891 +#define R_REG(r) ({ \
1892 + __typeof(*(r)) __osl_v; \
1893 + switch (sizeof(*(r))) { \
1894 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
1895 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
1896 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
1897 + } \
1898 + __osl_v; \
1899 +})
1900 +#define W_REG(r, v) do { \
1901 + switch (sizeof(*(r))) { \
1902 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
1903 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
1904 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
1905 + } \
1906 +} while (0)
1907 +#endif
1908 +#endif
1909 +
1910 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
1911 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
1912 +
1913 +/* bcopy, bcmp, and bzero */
1914 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
1915 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
1916 +#define bzero(b, len) memset((b), '\0', (len))
1917 +
1918 +/* uncached virtual address */
1919 +#ifdef mips
1920 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
1921 +#include <asm/addrspace.h>
1922 +#else
1923 +#define OSL_UNCACHED(va) (va)
1924 +#endif
1925 +
1926 +/* get processor cycle count */
1927 +#if defined(mips)
1928 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
1929 +#elif defined(__i386__)
1930 +#define OSL_GETCYCLES(x) rdtscl((x))
1931 +#else
1932 +#define OSL_GETCYCLES(x) ((x) = 0)
1933 +#endif
1934 +
1935 +/* dereference an address that may cause a bus exception */
1936 +#ifdef mips
1937 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
1938 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
1939 +#else
1940 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
1941 +#include <asm/paccess.h>
1942 +#endif
1943 +#else
1944 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
1945 +#endif
1946 +
1947 +/* map/unmap physical to virtual I/O */
1948 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
1949 +#define REG_UNMAP(va) iounmap((void *)(va))
1950 +
1951 +/* shared (dma-able) memory access macros */
1952 +#define R_SM(r) *(r)
1953 +#define W_SM(r, v) (*(r) = (v))
1954 +#define BZERO_SM(r, len) memset((r), '\0', (len))
1955 +
1956 +/* packet primitives */
1957 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
1958 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
1959 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
1960 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
1961 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
1962 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
1963 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
1964 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
1965 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
1966 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
1967 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
1968 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
1969 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
1970 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
1971 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
1972 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
1973 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
1974 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
1975 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
1976 +extern void osl_pktfree(void *skb);
1977 +
1978 +#else /* BINOSL */
1979 +
1980 +/* string library */
1981 +#ifndef LINUX_OSL
1982 +#undef printf
1983 +#define printf(fmt, args...) osl_printf((fmt), ## args)
1984 +#undef sprintf
1985 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
1986 +#undef strcmp
1987 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
1988 +#undef strncmp
1989 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
1990 +#undef strlen
1991 +#define strlen(s) osl_strlen((s))
1992 +#undef strcpy
1993 +#define strcpy(d, s) osl_strcpy((d), (s))
1994 +#undef strncpy
1995 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
1996 +#endif
1997 +extern int osl_printf(const char *format, ...);
1998 +extern int osl_sprintf(char *buf, const char *format, ...);
1999 +extern int osl_strcmp(const char *s1, const char *s2);
2000 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
2001 +extern int osl_strlen(const char *s);
2002 +extern char* osl_strcpy(char *d, const char *s);
2003 +extern char* osl_strncpy(char *d, const char *s, uint n);
2004 +
2005 +/* register access macros */
2006 +#if !defined(BCMJTAG)
2007 +#define R_REG(r) ( \
2008 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
2009 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
2010 + osl_readl((volatile uint32*)(r)) \
2011 +)
2012 +#define W_REG(r, v) do { \
2013 + switch (sizeof(*(r))) { \
2014 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
2015 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
2016 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
2017 + } \
2018 +} while (0)
2019 +#endif
2020 +
2021 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2022 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2023 +extern uint8 osl_readb(volatile uint8 *r);
2024 +extern uint16 osl_readw(volatile uint16 *r);
2025 +extern uint32 osl_readl(volatile uint32 *r);
2026 +extern void osl_writeb(uint8 v, volatile uint8 *r);
2027 +extern void osl_writew(uint16 v, volatile uint16 *r);
2028 +extern void osl_writel(uint32 v, volatile uint32 *r);
2029 +
2030 +/* bcopy, bcmp, and bzero */
2031 +extern void bcopy(const void *src, void *dst, int len);
2032 +extern int bcmp(const void *b1, const void *b2, int len);
2033 +extern void bzero(void *b, int len);
2034 +
2035 +/* uncached virtual address */
2036 +#define OSL_UNCACHED(va) osl_uncached((va))
2037 +extern void *osl_uncached(void *va);
2038 +
2039 +/* get processor cycle count */
2040 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
2041 +extern uint osl_getcycles(void);
2042 +
2043 +/* dereference an address that may target abort */
2044 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
2045 +extern int osl_busprobe(uint32 *val, uint32 addr);
2046 +
2047 +/* map/unmap physical to virtual */
2048 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
2049 +#define REG_UNMAP(va) osl_reg_unmap((va))
2050 +extern void *osl_reg_map(uint32 pa, uint size);
2051 +extern void osl_reg_unmap(void *va);
2052 +
2053 +/* shared (dma-able) memory access macros */
2054 +#define R_SM(r) *(r)
2055 +#define W_SM(r, v) (*(r) = (v))
2056 +#define BZERO_SM(r, len) bzero((r), (len))
2057 +
2058 +/* packet primitives */
2059 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
2060 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
2061 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
2062 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
2063 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
2064 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
2065 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
2066 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
2067 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
2068 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
2069 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
2070 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
2071 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
2072 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
2073 +#define PKTLINK(skb) osl_pktlink((skb))
2074 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
2075 +#define PKTPRIO(skb) osl_pktprio((skb))
2076 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
2077 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
2078 +extern void osl_pktfree(void *skb);
2079 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
2080 +extern uint osl_pktlen(osl_t *osh, void *skb);
2081 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
2082 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
2083 +extern void *osl_pktnext(osl_t *osh, void *skb);
2084 +extern void osl_pktsetnext(void *skb, void *x);
2085 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
2086 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
2087 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
2088 +extern void *osl_pktdup(osl_t *osh, void *skb);
2089 +extern void *osl_pktcookie(void *skb);
2090 +extern void osl_pktsetcookie(void *skb, void *x);
2091 +extern void *osl_pktlink(void *skb);
2092 +extern void osl_pktsetlink(void *skb, void *x);
2093 +extern uint osl_pktprio(void *skb);
2094 +extern void osl_pktsetprio(void *skb, uint x);
2095 +
2096 +#endif /* BINOSL */
2097 +
2098 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
2099 +extern int osl_error(int bcmerror);
2100 +
2101 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2102 +#define PKTBUFSZ 2048
2103 +
2104 +#endif /* _linux_osl_h_ */
2105 diff -Naur linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
2106 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
2107 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-04-06 15:34:14.000000000 +0200
2108 @@ -0,0 +1,411 @@
2109 +/*
2110 + * Linux-specific abstractions to gain some independence from linux kernel versions.
2111 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
2112 + *
2113 + * Copyright 2005, Broadcom Corporation
2114 + * All Rights Reserved.
2115 + *
2116 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2117 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2118 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2119 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2120 + *
2121 + * $Id$
2122 + */
2123 +
2124 +#ifndef _linuxver_h_
2125 +#define _linuxver_h_
2126 +
2127 +#include <linux/config.h>
2128 +#include <linux/version.h>
2129 +
2130 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
2131 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
2132 +#ifdef __UNDEF_NO_VERSION__
2133 +#undef __NO_VERSION__
2134 +#else
2135 +#define __NO_VERSION__
2136 +#endif
2137 +#endif
2138 +
2139 +#if defined(MODULE) && defined(MODVERSIONS)
2140 +#include <linux/modversions.h>
2141 +#endif
2142 +
2143 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
2144 +#include <linux/moduleparam.h>
2145 +#endif
2146 +
2147 +
2148 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
2149 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
2150 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
2151 +#endif
2152 +
2153 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
2154 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
2155 +#include <linux/malloc.h>
2156 +#else
2157 +#include <linux/slab.h>
2158 +#endif
2159 +
2160 +#include <linux/types.h>
2161 +#include <linux/init.h>
2162 +#include <linux/mm.h>
2163 +#include <linux/string.h>
2164 +#include <linux/pci.h>
2165 +#include <linux/interrupt.h>
2166 +#include <linux/netdevice.h>
2167 +#include <asm/io.h>
2168 +
2169 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
2170 +#include <linux/workqueue.h>
2171 +#else
2172 +#include <linux/tqueue.h>
2173 +#ifndef work_struct
2174 +#define work_struct tq_struct
2175 +#endif
2176 +#ifndef INIT_WORK
2177 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
2178 +#endif
2179 +#ifndef schedule_work
2180 +#define schedule_work(_work) schedule_task((_work))
2181 +#endif
2182 +#ifndef flush_scheduled_work
2183 +#define flush_scheduled_work() flush_scheduled_tasks()
2184 +#endif
2185 +#endif
2186 +
2187 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
2188 +/* Some distributions have their own 2.6.x compatibility layers */
2189 +#ifndef IRQ_NONE
2190 +typedef void irqreturn_t;
2191 +#define IRQ_NONE
2192 +#define IRQ_HANDLED
2193 +#define IRQ_RETVAL(x)
2194 +#endif
2195 +#else
2196 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
2197 +#endif
2198 +
2199 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2200 +
2201 +#include <pcmcia/version.h>
2202 +#include <pcmcia/cs_types.h>
2203 +#include <pcmcia/cs.h>
2204 +#include <pcmcia/cistpl.h>
2205 +#include <pcmcia/cisreg.h>
2206 +#include <pcmcia/ds.h>
2207 +
2208 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
2209 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
2210 + * does this, but it's not in 2.4 so we do our own for now. */
2211 +static inline void
2212 +cs_error(client_handle_t handle, int func, int ret)
2213 +{
2214 + error_info_t err = { func, ret };
2215 + CardServices(ReportError, handle, &err);
2216 +}
2217 +#endif
2218 +
2219 +#endif /* CONFIG_PCMCIA */
2220 +
2221 +#ifndef __exit
2222 +#define __exit
2223 +#endif
2224 +#ifndef __devexit
2225 +#define __devexit
2226 +#endif
2227 +#ifndef __devinit
2228 +#define __devinit __init
2229 +#endif
2230 +#ifndef __devinitdata
2231 +#define __devinitdata
2232 +#endif
2233 +#ifndef __devexit_p
2234 +#define __devexit_p(x) x
2235 +#endif
2236 +
2237 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
2238 +
2239 +#define pci_get_drvdata(dev) (dev)->sysdata
2240 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
2241 +
2242 +/*
2243 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
2244 + */
2245 +
2246 +struct pci_device_id {
2247 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
2248 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
2249 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
2250 + unsigned long driver_data; /* Data private to the driver */
2251 +};
2252 +
2253 +struct pci_driver {
2254 + struct list_head node;
2255 + char *name;
2256 + const struct pci_device_id *id_table; /* NULL if wants all devices */
2257 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
2258 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
2259 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
2260 + void (*resume)(struct pci_dev *dev); /* Device woken up */
2261 +};
2262 +
2263 +#define MODULE_DEVICE_TABLE(type, name)
2264 +#define PCI_ANY_ID (~0)
2265 +
2266 +/* compatpci.c */
2267 +#define pci_module_init pci_register_driver
2268 +extern int pci_register_driver(struct pci_driver *drv);
2269 +extern void pci_unregister_driver(struct pci_driver *drv);
2270 +
2271 +#endif /* PCI registration */
2272 +
2273 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
2274 +#ifdef MODULE
2275 +#define module_init(x) int init_module(void) { return x(); }
2276 +#define module_exit(x) void cleanup_module(void) { x(); }
2277 +#else
2278 +#define module_init(x) __initcall(x);
2279 +#define module_exit(x) __exitcall(x);
2280 +#endif
2281 +#endif
2282 +
2283 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
2284 +#define list_for_each(pos, head) \
2285 + for (pos = (head)->next; pos != (head); pos = pos->next)
2286 +#endif
2287 +
2288 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
2289 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
2290 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
2291 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
2292 +#endif
2293 +
2294 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
2295 +#define pci_enable_device(dev) do { } while (0)
2296 +#endif
2297 +
2298 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
2299 +#define net_device device
2300 +#endif
2301 +
2302 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
2303 +
2304 +/*
2305 + * DMA mapping
2306 + *
2307 + * See linux/Documentation/DMA-mapping.txt
2308 + */
2309 +
2310 +#ifndef PCI_DMA_TODEVICE
2311 +#define PCI_DMA_TODEVICE 1
2312 +#define PCI_DMA_FROMDEVICE 2
2313 +#endif
2314 +
2315 +typedef u32 dma_addr_t;
2316 +
2317 +/* Pure 2^n version of get_order */
2318 +static inline int get_order(unsigned long size)
2319 +{
2320 + int order;
2321 +
2322 + size = (size-1) >> (PAGE_SHIFT-1);
2323 + order = -1;
2324 + do {
2325 + size >>= 1;
2326 + order++;
2327 + } while (size);
2328 + return order;
2329 +}
2330 +
2331 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
2332 + dma_addr_t *dma_handle)
2333 +{
2334 + void *ret;
2335 + int gfp = GFP_ATOMIC | GFP_DMA;
2336 +
2337 + ret = (void *)__get_free_pages(gfp, get_order(size));
2338 +
2339 + if (ret != NULL) {
2340 + memset(ret, 0, size);
2341 + *dma_handle = virt_to_bus(ret);
2342 + }
2343 + return ret;
2344 +}
2345 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
2346 + void *vaddr, dma_addr_t dma_handle)
2347 +{
2348 + free_pages((unsigned long)vaddr, get_order(size));
2349 +}
2350 +#ifdef ILSIM
2351 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
2352 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
2353 +#else
2354 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
2355 +#define pci_unmap_single(cookie, address, size, dir)
2356 +#endif
2357 +
2358 +#endif /* DMA mapping */
2359 +
2360 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
2361 +
2362 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
2363 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
2364 +
2365 +/* pcmcia-cs provides its own netdevice compatibility layer */
2366 +#ifndef _COMPAT_NETDEVICE_H
2367 +
2368 +/*
2369 + * SoftNet
2370 + *
2371 + * For pre-softnet kernels we need to tell the upper layer not to
2372 + * re-enter start_xmit() while we are in there. However softnet
2373 + * guarantees not to enter while we are in there so there is no need
2374 + * to do the netif_stop_queue() dance unless the transmit queue really
2375 + * gets stuck. This should also improve performance according to tests
2376 + * done by Aman Singla.
2377 + */
2378 +
2379 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
2380 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
2381 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
2382 +
2383 +static inline void netif_start_queue(struct net_device *dev)
2384 +{
2385 + dev->tbusy = 0;
2386 + dev->interrupt = 0;
2387 + dev->start = 1;
2388 +}
2389 +
2390 +#define netif_queue_stopped(dev) (dev)->tbusy
2391 +#define netif_running(dev) (dev)->start
2392 +
2393 +#endif /* _COMPAT_NETDEVICE_H */
2394 +
2395 +#define netif_device_attach(dev) netif_start_queue(dev)
2396 +#define netif_device_detach(dev) netif_stop_queue(dev)
2397 +
2398 +/* 2.4.x renamed bottom halves to tasklets */
2399 +#define tasklet_struct tq_struct
2400 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
2401 +{
2402 + queue_task(tasklet, &tq_immediate);
2403 + mark_bh(IMMEDIATE_BH);
2404 +}
2405 +
2406 +static inline void tasklet_init(struct tasklet_struct *tasklet,
2407 + void (*func)(unsigned long),
2408 + unsigned long data)
2409 +{
2410 + tasklet->next = NULL;
2411 + tasklet->sync = 0;
2412 + tasklet->routine = (void (*)(void *))func;
2413 + tasklet->data = (void *)data;
2414 +}
2415 +#define tasklet_kill(tasklet) {do{} while(0);}
2416 +
2417 +/* 2.4.x introduced del_timer_sync() */
2418 +#define del_timer_sync(timer) del_timer(timer)
2419 +
2420 +#else
2421 +
2422 +#define netif_down(dev)
2423 +
2424 +#endif /* SoftNet */
2425 +
2426 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
2427 +
2428 +/*
2429 + * Emit code to initialise a tq_struct's routine and data pointers
2430 + */
2431 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
2432 + do { \
2433 + (_tq)->routine = _routine; \
2434 + (_tq)->data = _data; \
2435 + } while (0)
2436 +
2437 +/*
2438 + * Emit code to initialise all of a tq_struct
2439 + */
2440 +#define INIT_TQUEUE(_tq, _routine, _data) \
2441 + do { \
2442 + INIT_LIST_HEAD(&(_tq)->list); \
2443 + (_tq)->sync = 0; \
2444 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
2445 + } while (0)
2446 +
2447 +#endif
2448 +
2449 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
2450 +
2451 +/* Power management related routines */
2452 +
2453 +static inline int
2454 +pci_save_state(struct pci_dev *dev, u32 *buffer)
2455 +{
2456 + int i;
2457 + if (buffer) {
2458 + for (i = 0; i < 16; i++)
2459 + pci_read_config_dword(dev, i * 4,&buffer[i]);
2460 + }
2461 + return 0;
2462 +}
2463 +
2464 +static inline int
2465 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
2466 +{
2467 + int i;
2468 +
2469 + if (buffer) {
2470 + for (i = 0; i < 16; i++)
2471 + pci_write_config_dword(dev,i * 4, buffer[i]);
2472 + }
2473 + /*
2474 + * otherwise, write the context information we know from bootup.
2475 + * This works around a problem where warm-booting from Windows
2476 + * combined with a D3(hot)->D0 transition causes PCI config
2477 + * header data to be forgotten.
2478 + */
2479 + else {
2480 + for (i = 0; i < 6; i ++)
2481 + pci_write_config_dword(dev,
2482 + PCI_BASE_ADDRESS_0 + (i * 4),
2483 + pci_resource_start(dev, i));
2484 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
2485 + }
2486 + return 0;
2487 +}
2488 +
2489 +#endif /* PCI power management */
2490 +
2491 +/* Old cp0 access macros deprecated in 2.4.19 */
2492 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
2493 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
2494 +#endif
2495 +
2496 +/* Module refcount handled internally in 2.6.x */
2497 +#ifndef SET_MODULE_OWNER
2498 +#define SET_MODULE_OWNER(dev) do {} while (0)
2499 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
2500 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
2501 +#else
2502 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
2503 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
2504 +#endif
2505 +
2506 +#ifndef SET_NETDEV_DEV
2507 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
2508 +#endif
2509 +
2510 +#ifndef HAVE_FREE_NETDEV
2511 +#define free_netdev(dev) kfree(dev)
2512 +#endif
2513 +
2514 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
2515 +/* struct packet_type redefined in 2.6.x */
2516 +#define af_packet_priv data
2517 +#endif
2518 +
2519 +#endif /* _linuxver_h_ */
2520 diff -Naur linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
2521 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
2522 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-04-06 15:34:14.000000000 +0200
2523 @@ -0,0 +1,552 @@
2524 +/*
2525 + * HND Run Time Environment for standalone MIPS programs.
2526 + *
2527 + * Copyright 2005, Broadcom Corporation
2528 + * All Rights Reserved.
2529 + *
2530 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2531 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2532 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2533 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2534 + *
2535 + * $Id$
2536 + */
2537 +
2538 +#ifndef _MISPINC_H
2539 +#define _MISPINC_H
2540 +
2541 +
2542 +/* MIPS defines */
2543 +
2544 +#ifdef _LANGUAGE_ASSEMBLY
2545 +
2546 +/*
2547 + * Symbolic register names for 32 bit ABI
2548 + */
2549 +#define zero $0 /* wired zero */
2550 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
2551 +#define v0 $2 /* return value */
2552 +#define v1 $3
2553 +#define a0 $4 /* argument registers */
2554 +#define a1 $5
2555 +#define a2 $6
2556 +#define a3 $7
2557 +#define t0 $8 /* caller saved */
2558 +#define t1 $9
2559 +#define t2 $10
2560 +#define t3 $11
2561 +#define t4 $12
2562 +#define t5 $13
2563 +#define t6 $14
2564 +#define t7 $15
2565 +#define s0 $16 /* callee saved */
2566 +#define s1 $17
2567 +#define s2 $18
2568 +#define s3 $19
2569 +#define s4 $20
2570 +#define s5 $21
2571 +#define s6 $22
2572 +#define s7 $23
2573 +#define t8 $24 /* caller saved */
2574 +#define t9 $25
2575 +#define jp $25 /* PIC jump register */
2576 +#define k0 $26 /* kernel scratch */
2577 +#define k1 $27
2578 +#define gp $28 /* global pointer */
2579 +#define sp $29 /* stack pointer */
2580 +#define fp $30 /* frame pointer */
2581 +#define s8 $30 /* same like fp! */
2582 +#define ra $31 /* return address */
2583 +
2584 +
2585 +/*
2586 + * CP0 Registers
2587 + */
2588 +
2589 +#define C0_INX $0
2590 +#define C0_RAND $1
2591 +#define C0_TLBLO0 $2
2592 +#define C0_TLBLO C0_TLBLO0
2593 +#define C0_TLBLO1 $3
2594 +#define C0_CTEXT $4
2595 +#define C0_PGMASK $5
2596 +#define C0_WIRED $6
2597 +#define C0_BADVADDR $8
2598 +#define C0_COUNT $9
2599 +#define C0_TLBHI $10
2600 +#define C0_COMPARE $11
2601 +#define C0_SR $12
2602 +#define C0_STATUS C0_SR
2603 +#define C0_CAUSE $13
2604 +#define C0_EPC $14
2605 +#define C0_PRID $15
2606 +#define C0_CONFIG $16
2607 +#define C0_LLADDR $17
2608 +#define C0_WATCHLO $18
2609 +#define C0_WATCHHI $19
2610 +#define C0_XCTEXT $20
2611 +#define C0_DIAGNOSTIC $22
2612 +#define C0_BROADCOM C0_DIAGNOSTIC
2613 +#define C0_PERFORMANCE $25
2614 +#define C0_ECC $26
2615 +#define C0_CACHEERR $27
2616 +#define C0_TAGLO $28
2617 +#define C0_TAGHI $29
2618 +#define C0_ERREPC $30
2619 +#define C0_DESAVE $31
2620 +
2621 +/*
2622 + * LEAF - declare leaf routine
2623 + */
2624 +#define LEAF(symbol) \
2625 + .globl symbol; \
2626 + .align 2; \
2627 + .type symbol,@function; \
2628 + .ent symbol,0; \
2629 +symbol: .frame sp,0,ra
2630 +
2631 +/*
2632 + * END - mark end of function
2633 + */
2634 +#define END(function) \
2635 + .end function; \
2636 + .size function,.-function
2637 +
2638 +#define _ULCAST_
2639 +
2640 +#else
2641 +
2642 +/*
2643 + * The following macros are especially useful for __asm__
2644 + * inline assembler.
2645 + */
2646 +#ifndef __STR
2647 +#define __STR(x) #x
2648 +#endif
2649 +#ifndef STR
2650 +#define STR(x) __STR(x)
2651 +#endif
2652 +
2653 +#define _ULCAST_ (unsigned long)
2654 +
2655 +
2656 +/*
2657 + * CP0 Registers
2658 + */
2659 +
2660 +#define C0_INX 0 /* CP0: TLB Index */
2661 +#define C0_RAND 1 /* CP0: TLB Random */
2662 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
2663 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
2664 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
2665 +#define C0_CTEXT 4 /* CP0: Context */
2666 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
2667 +#define C0_WIRED 6 /* CP0: TLB Wired */
2668 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
2669 +#define C0_COUNT 9 /* CP0: Count */
2670 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
2671 +#define C0_COMPARE 11 /* CP0: Compare */
2672 +#define C0_SR 12 /* CP0: Processor Status */
2673 +#define C0_STATUS C0_SR /* CP0: Processor Status */
2674 +#define C0_CAUSE 13 /* CP0: Exception Cause */
2675 +#define C0_EPC 14 /* CP0: Exception PC */
2676 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
2677 +#define C0_CONFIG 16 /* CP0: Config */
2678 +#define C0_LLADDR 17 /* CP0: LLAddr */
2679 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
2680 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
2681 +#define C0_XCTEXT 20 /* CP0: XContext */
2682 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
2683 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
2684 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
2685 +#define C0_ECC 26 /* CP0: ECC */
2686 +#define C0_CACHEERR 27 /* CP0: CacheErr */
2687 +#define C0_TAGLO 28 /* CP0: TagLo */
2688 +#define C0_TAGHI 29 /* CP0: TagHi */
2689 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
2690 +#define C0_DESAVE 31 /* CP0: DebugSave */
2691 +
2692 +#endif /* _LANGUAGE_ASSEMBLY */
2693 +
2694 +/*
2695 + * Memory segments (32bit kernel mode addresses)
2696 + */
2697 +#undef KUSEG
2698 +#undef KSEG0
2699 +#undef KSEG1
2700 +#undef KSEG2
2701 +#undef KSEG3
2702 +#define KUSEG 0x00000000
2703 +#define KSEG0 0x80000000
2704 +#define KSEG1 0xa0000000
2705 +#define KSEG2 0xc0000000
2706 +#define KSEG3 0xe0000000
2707 +#define PHYSADDR_MASK 0x1fffffff
2708 +
2709 +/*
2710 + * Map an address to a certain kernel segment
2711 + */
2712 +#undef PHYSADDR
2713 +#undef KSEG0ADDR
2714 +#undef KSEG1ADDR
2715 +#undef KSEG2ADDR
2716 +#undef KSEG3ADDR
2717 +
2718 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
2719 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
2720 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
2721 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
2722 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
2723 +
2724 +
2725 +#ifndef Index_Invalidate_I
2726 +/*
2727 + * Cache Operations
2728 + */
2729 +#define Index_Invalidate_I 0x00
2730 +#define Index_Writeback_Inv_D 0x01
2731 +#define Index_Invalidate_SI 0x02
2732 +#define Index_Writeback_Inv_SD 0x03
2733 +#define Index_Load_Tag_I 0x04
2734 +#define Index_Load_Tag_D 0x05
2735 +#define Index_Load_Tag_SI 0x06
2736 +#define Index_Load_Tag_SD 0x07
2737 +#define Index_Store_Tag_I 0x08
2738 +#define Index_Store_Tag_D 0x09
2739 +#define Index_Store_Tag_SI 0x0A
2740 +#define Index_Store_Tag_SD 0x0B
2741 +#define Create_Dirty_Excl_D 0x0d
2742 +#define Create_Dirty_Excl_SD 0x0f
2743 +#define Hit_Invalidate_I 0x10
2744 +#define Hit_Invalidate_D 0x11
2745 +#define Hit_Invalidate_SI 0x12
2746 +#define Hit_Invalidate_SD 0x13
2747 +#define Fill_I 0x14
2748 +#define Hit_Writeback_Inv_D 0x15
2749 + /* 0x16 is unused */
2750 +#define Hit_Writeback_Inv_SD 0x17
2751 +#define R5K_Page_Invalidate_S 0x17
2752 +#define Hit_Writeback_I 0x18
2753 +#define Hit_Writeback_D 0x19
2754 + /* 0x1a is unused */
2755 +#define Hit_Writeback_SD 0x1b
2756 + /* 0x1c is unused */
2757 + /* 0x1e is unused */
2758 +#define Hit_Set_Virtual_SI 0x1e
2759 +#define Hit_Set_Virtual_SD 0x1f
2760 +#endif
2761 +
2762 +
2763 +/*
2764 + * R4x00 interrupt enable / cause bits
2765 + */
2766 +#define IE_SW0 (_ULCAST_(1) << 8)
2767 +#define IE_SW1 (_ULCAST_(1) << 9)
2768 +#define IE_IRQ0 (_ULCAST_(1) << 10)
2769 +#define IE_IRQ1 (_ULCAST_(1) << 11)
2770 +#define IE_IRQ2 (_ULCAST_(1) << 12)
2771 +#define IE_IRQ3 (_ULCAST_(1) << 13)
2772 +#define IE_IRQ4 (_ULCAST_(1) << 14)
2773 +#define IE_IRQ5 (_ULCAST_(1) << 15)
2774 +
2775 +#ifndef ST0_UM
2776 +/*
2777 + * Bitfields in the mips32 cp0 status register
2778 + */
2779 +#define ST0_IE 0x00000001
2780 +#define ST0_EXL 0x00000002
2781 +#define ST0_ERL 0x00000004
2782 +#define ST0_UM 0x00000010
2783 +#define ST0_SWINT0 0x00000100
2784 +#define ST0_SWINT1 0x00000200
2785 +#define ST0_HWINT0 0x00000400
2786 +#define ST0_HWINT1 0x00000800
2787 +#define ST0_HWINT2 0x00001000
2788 +#define ST0_HWINT3 0x00002000
2789 +#define ST0_HWINT4 0x00004000
2790 +#define ST0_HWINT5 0x00008000
2791 +#define ST0_IM 0x0000ff00
2792 +#define ST0_NMI 0x00080000
2793 +#define ST0_SR 0x00100000
2794 +#define ST0_TS 0x00200000
2795 +#define ST0_BEV 0x00400000
2796 +#define ST0_RE 0x02000000
2797 +#define ST0_RP 0x08000000
2798 +#define ST0_CU 0xf0000000
2799 +#define ST0_CU0 0x10000000
2800 +#define ST0_CU1 0x20000000
2801 +#define ST0_CU2 0x40000000
2802 +#define ST0_CU3 0x80000000
2803 +#endif
2804 +
2805 +
2806 +/*
2807 + * Bitfields in the mips32 cp0 cause register
2808 + */
2809 +#define C_EXC 0x0000007c
2810 +#define C_EXC_SHIFT 2
2811 +#define C_INT 0x0000ff00
2812 +#define C_INT_SHIFT 8
2813 +#define C_SW0 (_ULCAST_(1) << 8)
2814 +#define C_SW1 (_ULCAST_(1) << 9)
2815 +#define C_IRQ0 (_ULCAST_(1) << 10)
2816 +#define C_IRQ1 (_ULCAST_(1) << 11)
2817 +#define C_IRQ2 (_ULCAST_(1) << 12)
2818 +#define C_IRQ3 (_ULCAST_(1) << 13)
2819 +#define C_IRQ4 (_ULCAST_(1) << 14)
2820 +#define C_IRQ5 (_ULCAST_(1) << 15)
2821 +#define C_WP 0x00400000
2822 +#define C_IV 0x00800000
2823 +#define C_CE 0x30000000
2824 +#define C_CE_SHIFT 28
2825 +#define C_BD 0x80000000
2826 +
2827 +/* Values in C_EXC */
2828 +#define EXC_INT 0
2829 +#define EXC_TLBM 1
2830 +#define EXC_TLBL 2
2831 +#define EXC_TLBS 3
2832 +#define EXC_AEL 4
2833 +#define EXC_AES 5
2834 +#define EXC_IBE 6
2835 +#define EXC_DBE 7
2836 +#define EXC_SYS 8
2837 +#define EXC_BPT 9
2838 +#define EXC_RI 10
2839 +#define EXC_CU 11
2840 +#define EXC_OV 12
2841 +#define EXC_TR 13
2842 +#define EXC_WATCH 23
2843 +#define EXC_MCHK 24
2844 +
2845 +
2846 +/*
2847 + * Bits in the cp0 config register.
2848 + */
2849 +#define CONF_CM_CACHABLE_NO_WA 0
2850 +#define CONF_CM_CACHABLE_WA 1
2851 +#define CONF_CM_UNCACHED 2
2852 +#define CONF_CM_CACHABLE_NONCOHERENT 3
2853 +#define CONF_CM_CACHABLE_CE 4
2854 +#define CONF_CM_CACHABLE_COW 5
2855 +#define CONF_CM_CACHABLE_CUW 6
2856 +#define CONF_CM_CACHABLE_ACCELERATED 7
2857 +#define CONF_CM_CMASK 7
2858 +#define CONF_CU (_ULCAST_(1) << 3)
2859 +#define CONF_DB (_ULCAST_(1) << 4)
2860 +#define CONF_IB (_ULCAST_(1) << 5)
2861 +#define CONF_SE (_ULCAST_(1) << 12)
2862 +#define CONF_SC (_ULCAST_(1) << 17)
2863 +#define CONF_AC (_ULCAST_(1) << 23)
2864 +#define CONF_HALT (_ULCAST_(1) << 25)
2865 +
2866 +
2867 +/*
2868 + * Bits in the cp0 config register select 1.
2869 + */
2870 +#define CONF1_FP 0x00000001 /* FPU present */
2871 +#define CONF1_EP 0x00000002 /* EJTAG present */
2872 +#define CONF1_CA 0x00000004 /* mips16 implemented */
2873 +#define CONF1_WR 0x00000008 /* Watch registers present */
2874 +#define CONF1_PC 0x00000010 /* Performance counters present */
2875 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
2876 +#define CONF1_DA_MASK 0x00000380
2877 +#define CONF1_DA_BASE 1
2878 +#define CONF1_DL_SHIFT 10 /* D$ line size */
2879 +#define CONF1_DL_MASK 0x00001c00
2880 +#define CONF1_DL_BASE 2
2881 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
2882 +#define CONF1_DS_MASK 0x0000e000
2883 +#define CONF1_DS_BASE 64
2884 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
2885 +#define CONF1_IA_MASK 0x00070000
2886 +#define CONF1_IA_BASE 1
2887 +#define CONF1_IL_SHIFT 19 /* I$ line size */
2888 +#define CONF1_IL_MASK 0x00380000
2889 +#define CONF1_IL_BASE 2
2890 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
2891 +#define CONF1_IS_MASK 0x01c00000
2892 +#define CONF1_IS_BASE 64
2893 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
2894 +#define CONF1_MS_SHIFT 25
2895 +
2896 +/* PRID register */
2897 +#define PRID_COPT_MASK 0xff000000
2898 +#define PRID_COMP_MASK 0x00ff0000
2899 +#define PRID_IMP_MASK 0x0000ff00
2900 +#define PRID_REV_MASK 0x000000ff
2901 +
2902 +#define PRID_COMP_LEGACY 0x000000
2903 +#define PRID_COMP_MIPS 0x010000
2904 +#define PRID_COMP_BROADCOM 0x020000
2905 +#define PRID_COMP_ALCHEMY 0x030000
2906 +#define PRID_COMP_SIBYTE 0x040000
2907 +#define PRID_IMP_BCM4710 0x4000
2908 +#define PRID_IMP_BCM3302 0x9000
2909 +#define PRID_IMP_BCM3303 0x9100
2910 +
2911 +#define PRID_IMP_UNKNOWN 0xff00
2912 +
2913 +#define BCM330X(id) \
2914 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
2915 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
2916 +
2917 +/* Bits in C0_BROADCOM */
2918 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
2919 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
2920 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
2921 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
2922 +
2923 +/* PreFetch Cache aka Read Ahead Cache */
2924 +
2925 +#define PFC_CR0 0xff400000 /* control reg 0 */
2926 +#define PFC_CR1 0xff400004 /* control reg 1 */
2927 +
2928 +/* PFC operations */
2929 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
2930 +#define PFC_D 0x00000002 /* Enable PFC use for data */
2931 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
2932 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
2933 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
2934 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
2935 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
2936 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
2937 +#define PFC_BRR 0x40000000 /* Bus error indication */
2938 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
2939 +
2940 +/* Handy defaults */
2941 +#define PFC_DISABLED 0
2942 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
2943 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
2944 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
2945 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
2946 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
2947 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
2948 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
2949 +
2950 +
2951 +/*
2952 + * These are the UART port assignments, expressed as offsets from the base
2953 + * register. These assignments should hold for any serial port based on
2954 + * a 8250, 16450, or 16550(A).
2955 + */
2956 +
2957 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
2958 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
2959 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
2960 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
2961 +#define UART_LCR 3 /* Out: Line Control Register */
2962 +#define UART_MCR 4 /* Out: Modem Control Register */
2963 +#define UART_LSR 5 /* In: Line Status Register */
2964 +#define UART_MSR 6 /* In: Modem Status Register */
2965 +#define UART_SCR 7 /* I/O: Scratch Register */
2966 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
2967 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
2968 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
2969 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
2970 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
2971 +
2972 +
2973 +#ifndef _LANGUAGE_ASSEMBLY
2974 +
2975 +/*
2976 + * Macros to access the system control coprocessor
2977 + */
2978 +
2979 +#define MFC0(source, sel) \
2980 +({ \
2981 + int __res; \
2982 + __asm__ __volatile__( \
2983 + ".set\tnoreorder\n\t" \
2984 + ".set\tnoat\n\t" \
2985 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
2986 + "move\t%0,$1\n\t" \
2987 + ".set\tat\n\t" \
2988 + ".set\treorder" \
2989 + :"=r" (__res) \
2990 + : \
2991 + :"$1"); \
2992 + __res; \
2993 +})
2994 +
2995 +#define MTC0(source, sel, value) \
2996 +do { \
2997 + __asm__ __volatile__( \
2998 + ".set\tnoreorder\n\t" \
2999 + ".set\tnoat\n\t" \
3000 + "move\t$1,%z0\n\t" \
3001 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
3002 + ".set\tat\n\t" \
3003 + ".set\treorder" \
3004 + : \
3005 + :"jr" (value) \
3006 + :"$1"); \
3007 +} while (0)
3008 +
3009 +#define get_c0_count() \
3010 +({ \
3011 + int __res; \
3012 + __asm__ __volatile__( \
3013 + ".set\tnoreorder\n\t" \
3014 + ".set\tnoat\n\t" \
3015 + "mfc0\t%0,$9\n\t" \
3016 + ".set\tat\n\t" \
3017 + ".set\treorder" \
3018 + :"=r" (__res)); \
3019 + __res; \
3020 +})
3021 +
3022 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
3023 +{
3024 + uint lsz, sets, ways;
3025 +
3026 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
3027 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
3028 + lsz = CONF1_IL_BASE << lsz;
3029 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
3030 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
3031 + *size = lsz * sets * ways;
3032 + *lsize = lsz;
3033 +}
3034 +
3035 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
3036 +{
3037 + uint lsz, sets, ways;
3038 +
3039 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
3040 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
3041 + lsz = CONF1_DL_BASE << lsz;
3042 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
3043 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
3044 + *size = lsz * sets * ways;
3045 + *lsize = lsz;
3046 +}
3047 +
3048 +#define cache_op(base, op) \
3049 + __asm__ __volatile__(" \
3050 + .set noreorder; \
3051 + .set mips3; \
3052 + cache %1, (%0); \
3053 + .set mips0; \
3054 + .set reorder" \
3055 + : \
3056 + : "r" (base), \
3057 + "i" (op));
3058 +
3059 +#define cache_unroll4(base, delta, op) \
3060 + __asm__ __volatile__(" \
3061 + .set noreorder; \
3062 + .set mips3; \
3063 + cache %1,0(%0); \
3064 + cache %1,delta(%0); \
3065 + cache %1,(2 * delta)(%0); \
3066 + cache %1,(3 * delta)(%0); \
3067 + .set mips0; \
3068 + .set reorder" \
3069 + : \
3070 + : "r" (base), \
3071 + "i" (op));
3072 +
3073 +#endif /* !_LANGUAGE_ASSEMBLY */
3074 +
3075 +#endif /* _MISPINC_H */
3076 diff -Naur linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
3077 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
3078 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-04-06 15:34:14.000000000 +0200
3079 @@ -0,0 +1,42 @@
3080 +/*
3081 + * OS Abstraction Layer
3082 + *
3083 + * Copyright 2005, Broadcom Corporation
3084 + * All Rights Reserved.
3085 + *
3086 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3087 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3088 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3089 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3090 + * $Id$
3091 + */
3092 +
3093 +#ifndef _osl_h_
3094 +#define _osl_h_
3095 +
3096 +/* osl handle type forward declaration */
3097 +typedef struct os_handle osl_t;
3098 +
3099 +#if defined(linux)
3100 +#include <linux_osl.h>
3101 +#elif defined(NDIS)
3102 +#include <ndis_osl.h>
3103 +#elif defined(_CFE_)
3104 +#include <cfe_osl.h>
3105 +#elif defined(_HNDRTE_)
3106 +#include <hndrte_osl.h>
3107 +#elif defined(_MINOSL_)
3108 +#include <min_osl.h>
3109 +#elif PMON
3110 +#include <pmon_osl.h>
3111 +#elif defined(MACOSX)
3112 +#include <macosx_osl.h>
3113 +#else
3114 +#error "Unsupported OSL requested"
3115 +#endif
3116 +
3117 +/* handy */
3118 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
3119 +#define MAXPRIO 7 /* 0-7 */
3120 +
3121 +#endif /* _osl_h_ */
3122 diff -Naur linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
3123 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
3124 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-04-06 15:34:14.000000000 +0200
3125 @@ -0,0 +1,451 @@
3126 +/*
3127 + * pcicfg.h: PCI configuration constants and structures.
3128 + *
3129 + * Copyright 2005, Broadcom Corporation
3130 + * All Rights Reserved.
3131 + *
3132 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3133 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3134 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3135 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3136 + *
3137 + * $Id$
3138 + */
3139 +
3140 +#ifndef _h_pci_
3141 +#define _h_pci_
3142 +
3143 +/* The following inside ifndef's so we don't collide with NTDDK.H */
3144 +#ifndef PCI_MAX_BUS
3145 +#define PCI_MAX_BUS 0x100
3146 +#endif
3147 +#ifndef PCI_MAX_DEVICES
3148 +#define PCI_MAX_DEVICES 0x20
3149 +#endif
3150 +#ifndef PCI_MAX_FUNCTION
3151 +#define PCI_MAX_FUNCTION 0x8
3152 +#endif
3153 +
3154 +#ifndef PCI_INVALID_VENDORID
3155 +#define PCI_INVALID_VENDORID 0xffff
3156 +#endif
3157 +#ifndef PCI_INVALID_DEVICEID
3158 +#define PCI_INVALID_DEVICEID 0xffff
3159 +#endif
3160 +
3161 +
3162 +/* Convert between bus-slot-function-register and config addresses */
3163 +
3164 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
3165 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
3166 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
3167 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
3168 +
3169 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
3170 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
3171 +#define PCICFG_FUN_MASK 7 /* Function mask */
3172 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
3173 +
3174 +#define PCI_CONFIG_ADDR(b, s, f, o) \
3175 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
3176 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
3177 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
3178 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
3179 +
3180 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
3181 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
3182 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
3183 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
3184 +
3185 +/* PCIE Config space accessing MACROS*/
3186 +
3187 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
3188 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
3189 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
3190 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
3191 +
3192 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
3193 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
3194 +#define PCIECFG_FUN_MASK 7 /* Function mask */
3195 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
3196 +
3197 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
3198 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
3199 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
3200 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
3201 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
3202 +
3203 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
3204 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
3205 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
3206 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
3207 +
3208 +
3209 +/* The actual config space */
3210 +
3211 +#define PCI_BAR_MAX 6
3212 +
3213 +#define PCI_ROM_BAR 8
3214 +
3215 +#define PCR_RSVDA_MAX 2
3216 +
3217 +/* pci config status reg has a bit to indicate that capability ptr is present*/
3218 +
3219 +#define PCI_CAPPTR_PRESENT 0x0010
3220 +
3221 +typedef struct _pci_config_regs {
3222 + unsigned short vendor;
3223 + unsigned short device;
3224 + unsigned short command;
3225 + unsigned short status;
3226 + unsigned char rev_id;
3227 + unsigned char prog_if;
3228 + unsigned char sub_class;
3229 + unsigned char base_class;
3230 + unsigned char cache_line_size;
3231 + unsigned char latency_timer;
3232 + unsigned char header_type;
3233 + unsigned char bist;
3234 + unsigned long base[PCI_BAR_MAX];
3235 + unsigned long cardbus_cis;
3236 + unsigned short subsys_vendor;
3237 + unsigned short subsys_id;
3238 + unsigned long baserom;
3239 + unsigned long rsvd_a[PCR_RSVDA_MAX];
3240 + unsigned char int_line;
3241 + unsigned char int_pin;
3242 + unsigned char min_gnt;
3243 + unsigned char max_lat;
3244 + unsigned char dev_dep[192];
3245 +} pci_config_regs;
3246 +
3247 +#define SZPCR (sizeof (pci_config_regs))
3248 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
3249 +
3250 +/* A structure for the config registers is nice, but in most
3251 + * systems the config space is not memory mapped, so we need
3252 + * filed offsetts. :-(
3253 + */
3254 +#define PCI_CFG_VID 0
3255 +#define PCI_CFG_DID 2
3256 +#define PCI_CFG_CMD 4
3257 +#define PCI_CFG_STAT 6
3258 +#define PCI_CFG_REV 8
3259 +#define PCI_CFG_PROGIF 9
3260 +#define PCI_CFG_SUBCL 0xa
3261 +#define PCI_CFG_BASECL 0xb
3262 +#define PCI_CFG_CLSZ 0xc
3263 +#define PCI_CFG_LATTIM 0xd
3264 +#define PCI_CFG_HDR 0xe
3265 +#define PCI_CFG_BIST 0xf
3266 +#define PCI_CFG_BAR0 0x10
3267 +#define PCI_CFG_BAR1 0x14
3268 +#define PCI_CFG_BAR2 0x18
3269 +#define PCI_CFG_BAR3 0x1c
3270 +#define PCI_CFG_BAR4 0x20
3271 +#define PCI_CFG_BAR5 0x24
3272 +#define PCI_CFG_CIS 0x28
3273 +#define PCI_CFG_SVID 0x2c
3274 +#define PCI_CFG_SSID 0x2e
3275 +#define PCI_CFG_ROMBAR 0x30
3276 +#define PCI_CFG_CAPPTR 0x34
3277 +#define PCI_CFG_INT 0x3c
3278 +#define PCI_CFG_PIN 0x3d
3279 +#define PCI_CFG_MINGNT 0x3e
3280 +#define PCI_CFG_MAXLAT 0x3f
3281 +
3282 +/* Classes and subclasses */
3283 +
3284 +typedef enum {
3285 + PCI_CLASS_OLD = 0,
3286 + PCI_CLASS_DASDI,
3287 + PCI_CLASS_NET,
3288 + PCI_CLASS_DISPLAY,
3289 + PCI_CLASS_MMEDIA,
3290 + PCI_CLASS_MEMORY,
3291 + PCI_CLASS_BRIDGE,
3292 + PCI_CLASS_COMM,
3293 + PCI_CLASS_BASE,
3294 + PCI_CLASS_INPUT,
3295 + PCI_CLASS_DOCK,
3296 + PCI_CLASS_CPU,
3297 + PCI_CLASS_SERIAL,
3298 + PCI_CLASS_INTELLIGENT = 0xe,
3299 + PCI_CLASS_SATELLITE,
3300 + PCI_CLASS_CRYPT,
3301 + PCI_CLASS_DSP,
3302 + PCI_CLASS_MAX
3303 +} pci_classes;
3304 +
3305 +typedef enum {
3306 + PCI_DASDI_SCSI,
3307 + PCI_DASDI_IDE,
3308 + PCI_DASDI_FLOPPY,
3309 + PCI_DASDI_IPI,
3310 + PCI_DASDI_RAID,
3311 + PCI_DASDI_OTHER = 0x80
3312 +} pci_dasdi_subclasses;
3313 +
3314 +typedef enum {
3315 + PCI_NET_ETHER,
3316 + PCI_NET_TOKEN,
3317 + PCI_NET_FDDI,
3318 + PCI_NET_ATM,
3319 + PCI_NET_OTHER = 0x80
3320 +} pci_net_subclasses;
3321 +
3322 +typedef enum {
3323 + PCI_DISPLAY_VGA,
3324 + PCI_DISPLAY_XGA,
3325 + PCI_DISPLAY_3D,
3326 + PCI_DISPLAY_OTHER = 0x80
3327 +} pci_display_subclasses;
3328 +
3329 +typedef enum {
3330 + PCI_MMEDIA_VIDEO,
3331 + PCI_MMEDIA_AUDIO,
3332 + PCI_MMEDIA_PHONE,
3333 + PCI_MEDIA_OTHER = 0x80
3334 +} pci_mmedia_subclasses;
3335 +
3336 +typedef enum {
3337 + PCI_MEMORY_RAM,
3338 + PCI_MEMORY_FLASH,
3339 + PCI_MEMORY_OTHER = 0x80
3340 +} pci_memory_subclasses;
3341 +
3342 +typedef enum {
3343 + PCI_BRIDGE_HOST,
3344 + PCI_BRIDGE_ISA,
3345 + PCI_BRIDGE_EISA,
3346 + PCI_BRIDGE_MC,
3347 + PCI_BRIDGE_PCI,
3348 + PCI_BRIDGE_PCMCIA,
3349 + PCI_BRIDGE_NUBUS,
3350 + PCI_BRIDGE_CARDBUS,
3351 + PCI_BRIDGE_RACEWAY,
3352 + PCI_BRIDGE_OTHER = 0x80
3353 +} pci_bridge_subclasses;
3354 +
3355 +typedef enum {
3356 + PCI_COMM_UART,
3357 + PCI_COMM_PARALLEL,
3358 + PCI_COMM_MULTIUART,
3359 + PCI_COMM_MODEM,
3360 + PCI_COMM_OTHER = 0x80
3361 +} pci_comm_subclasses;
3362 +
3363 +typedef enum {
3364 + PCI_BASE_PIC,
3365 + PCI_BASE_DMA,
3366 + PCI_BASE_TIMER,
3367 + PCI_BASE_RTC,
3368 + PCI_BASE_PCI_HOTPLUG,
3369 + PCI_BASE_OTHER = 0x80
3370 +} pci_base_subclasses;
3371 +
3372 +typedef enum {
3373 + PCI_INPUT_KBD,
3374 + PCI_INPUT_PEN,
3375 + PCI_INPUT_MOUSE,
3376 + PCI_INPUT_SCANNER,
3377 + PCI_INPUT_GAMEPORT,
3378 + PCI_INPUT_OTHER = 0x80
3379 +} pci_input_subclasses;
3380 +
3381 +typedef enum {
3382 + PCI_DOCK_GENERIC,
3383 + PCI_DOCK_OTHER = 0x80
3384 +} pci_dock_subclasses;
3385 +
3386 +typedef enum {
3387 + PCI_CPU_386,
3388 + PCI_CPU_486,
3389 + PCI_CPU_PENTIUM,
3390 + PCI_CPU_ALPHA = 0x10,
3391 + PCI_CPU_POWERPC = 0x20,
3392 + PCI_CPU_MIPS = 0x30,
3393 + PCI_CPU_COPROC = 0x40,
3394 + PCI_CPU_OTHER = 0x80
3395 +} pci_cpu_subclasses;
3396 +
3397 +typedef enum {
3398 + PCI_SERIAL_IEEE1394,
3399 + PCI_SERIAL_ACCESS,
3400 + PCI_SERIAL_SSA,
3401 + PCI_SERIAL_USB,
3402 + PCI_SERIAL_FIBER,
3403 + PCI_SERIAL_SMBUS,
3404 + PCI_SERIAL_OTHER = 0x80
3405 +} pci_serial_subclasses;
3406 +
3407 +typedef enum {
3408 + PCI_INTELLIGENT_I2O,
3409 +} pci_intelligent_subclasses;
3410 +
3411 +typedef enum {
3412 + PCI_SATELLITE_TV,
3413 + PCI_SATELLITE_AUDIO,
3414 + PCI_SATELLITE_VOICE,
3415 + PCI_SATELLITE_DATA,
3416 + PCI_SATELLITE_OTHER = 0x80
3417 +} pci_satellite_subclasses;
3418 +
3419 +typedef enum {
3420 + PCI_CRYPT_NETWORK,
3421 + PCI_CRYPT_ENTERTAINMENT,
3422 + PCI_CRYPT_OTHER = 0x80
3423 +} pci_crypt_subclasses;
3424 +
3425 +typedef enum {
3426 + PCI_DSP_DPIO,
3427 + PCI_DSP_OTHER = 0x80
3428 +} pci_dsp_subclasses;
3429 +
3430 +/* Header types */
3431 +typedef enum {
3432 + PCI_HEADER_NORMAL,
3433 + PCI_HEADER_BRIDGE,
3434 + PCI_HEADER_CARDBUS
3435 +} pci_header_types;
3436 +
3437 +
3438 +/* Overlay for a PCI-to-PCI bridge */
3439 +
3440 +#define PPB_RSVDA_MAX 2
3441 +#define PPB_RSVDD_MAX 8
3442 +
3443 +typedef struct _ppb_config_regs {
3444 + unsigned short vendor;
3445 + unsigned short device;
3446 + unsigned short command;
3447 + unsigned short status;
3448 + unsigned char rev_id;
3449 + unsigned char prog_if;
3450 + unsigned char sub_class;
3451 + unsigned char base_class;
3452 + unsigned char cache_line_size;
3453 + unsigned char latency_timer;
3454 + unsigned char header_type;
3455 + unsigned char bist;
3456 + unsigned long rsvd_a[PPB_RSVDA_MAX];
3457 + unsigned char prim_bus;
3458 + unsigned char sec_bus;
3459 + unsigned char sub_bus;
3460 + unsigned char sec_lat;
3461 + unsigned char io_base;
3462 + unsigned char io_lim;
3463 + unsigned short sec_status;
3464 + unsigned short mem_base;
3465 + unsigned short mem_lim;
3466 + unsigned short pf_mem_base;
3467 + unsigned short pf_mem_lim;
3468 + unsigned long pf_mem_base_hi;
3469 + unsigned long pf_mem_lim_hi;
3470 + unsigned short io_base_hi;
3471 + unsigned short io_lim_hi;
3472 + unsigned short subsys_vendor;
3473 + unsigned short subsys_id;
3474 + unsigned long rsvd_b;
3475 + unsigned char rsvd_c;
3476 + unsigned char int_pin;
3477 + unsigned short bridge_ctrl;
3478 + unsigned char chip_ctrl;
3479 + unsigned char diag_ctrl;
3480 + unsigned short arb_ctrl;
3481 + unsigned long rsvd_d[PPB_RSVDD_MAX];
3482 + unsigned char dev_dep[192];
3483 +} ppb_config_regs;
3484 +
3485 +
3486 +/* PCI CAPABILITY DEFINES */
3487 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
3488 +#define PCI_CAP_MSICAP_ID 0x05
3489 +#define PCI_CAP_PCIECAP_ID 0x10
3490 +
3491 +/* Data structure to define the Message Signalled Interrupt facility
3492 + * Valid for PCI and PCIE configurations */
3493 +typedef struct _pciconfig_cap_msi {
3494 + unsigned char capID;
3495 + unsigned char nextptr;
3496 + unsigned short msgctrl;
3497 + unsigned int msgaddr;
3498 +} pciconfig_cap_msi;
3499 +
3500 +/* Data structure to define the Power managment facility
3501 + * Valid for PCI and PCIE configurations */
3502 +typedef struct _pciconfig_cap_pwrmgmt {
3503 + unsigned char capID;
3504 + unsigned char nextptr;
3505 + unsigned short pme_cap;
3506 + unsigned short pme_sts_ctrl;
3507 + unsigned char pme_bridge_ext;
3508 + unsigned char data;
3509 +} pciconfig_cap_pwrmgmt;
3510 +
3511 +/* Data structure to define the PCIE capability */
3512 +typedef struct _pciconfig_cap_pcie {
3513 + unsigned char capID;
3514 + unsigned char nextptr;
3515 + unsigned short pcie_cap;
3516 + unsigned int dev_cap;
3517 + unsigned short dev_ctrl;
3518 + unsigned short dev_status;
3519 + unsigned int link_cap;
3520 + unsigned short link_ctrl;
3521 + unsigned short link_status;
35