clean up brcm-2.4 system code
[openwrt/svn-archive/archive.git] / openwrt / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -Nur linux-2.4.32/arch/mips/bcm947xx/cfe_env.c linux-2.4.32-brcm/arch/mips/bcm947xx/cfe_env.c
2 --- linux-2.4.32/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/cfe_env.c 2005-12-19 01:56:35.104829500 +0100
4 @@ -0,0 +1,234 @@
5 +/*
6 + * NVRAM variable manipulation (Linux kernel half)
7 + *
8 + * Copyright 2001-2003, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + *
16 + * $Id$
17 + */
18 +
19 +#include <linux/config.h>
20 +#include <linux/init.h>
21 +#include <linux/module.h>
22 +#include <linux/kernel.h>
23 +#include <linux/string.h>
24 +#include <asm/io.h>
25 +#include <asm/uaccess.h>
26 +
27 +#include <typedefs.h>
28 +#include <osl.h>
29 +#include <bcmendian.h>
30 +#include <bcmutils.h>
31 +
32 +#define NVRAM_SIZE (0x1ff0)
33 +static char _nvdata[NVRAM_SIZE] __initdata;
34 +static char _valuestr[256] __initdata;
35 +
36 +/*
37 + * TLV types. These codes are used in the "type-length-value"
38 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
39 + *
40 + * The layout of the flash/nvram is as follows:
41 + *
42 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
43 + *
44 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
45 + * The "length" field marks the length of the data section, not
46 + * including the type and length fields.
47 + *
48 + * Environment variables are stored as follows:
49 + *
50 + * <type_env> <length> <flags> <name> = <value>
51 + *
52 + * If bit 0 (low bit) is set, the length is an 8-bit value.
53 + * If bit 0 (low bit) is clear, the length is a 16-bit value
54 + *
55 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
56 + * indicates the size of the length field.
57 + *
58 + * Flags are from the constants below:
59 + *
60 + */
61 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
62 +#define ENV_LENGTH_8BITS 0x01
63 +
64 +#define ENV_TYPE_USER 0x80
65 +
66 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
67 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
68 +
69 +/*
70 + * The actual TLV types we support
71 + */
72 +
73 +#define ENV_TLV_TYPE_END 0x00
74 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
75 +
76 +/*
77 + * Environment variable flags
78 + */
79 +
80 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
81 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
82 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
83 +
84 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
85 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
86 +
87 +
88 +/* *********************************************************************
89 + * _nvram_read(buffer,offset,length)
90 + *
91 + * Read data from the NVRAM device
92 + *
93 + * Input parameters:
94 + * buffer - destination buffer
95 + * offset - offset of data to read
96 + * length - number of bytes to read
97 + *
98 + * Return value:
99 + * number of bytes read, or <0 if error occured
100 + ********************************************************************* */
101 +static int
102 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
103 +{
104 + int i;
105 + if (offset > NVRAM_SIZE)
106 + return -1;
107 +
108 + for ( i = 0; i < length; i++) {
109 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
110 + }
111 + return length;
112 +}
113 +
114 +
115 +static char*
116 +_strnchr(const char *dest,int c,size_t cnt)
117 +{
118 + while (*dest && (cnt > 0)) {
119 + if (*dest == c) return (char *) dest;
120 + dest++;
121 + cnt--;
122 + }
123 + return NULL;
124 +}
125 +
126 +
127 +
128 +/*
129 + * Core support API: Externally visible.
130 + */
131 +
132 +/*
133 + * Get the value of an NVRAM variable
134 + * @param name name of variable to get
135 + * @return value of variable or NULL if undefined
136 + */
137 +
138 +char*
139 +cfe_env_get(unsigned char *nv_buf, char* name)
140 +{
141 + int size;
142 + unsigned char *buffer;
143 + unsigned char *ptr;
144 + unsigned char *envval;
145 + unsigned int reclen;
146 + unsigned int rectype;
147 + int offset;
148 + int flg;
149 +
150 + size = NVRAM_SIZE;
151 + buffer = &_nvdata[0];
152 +
153 + ptr = buffer;
154 + offset = 0;
155 +
156 + /* Read the record type and length */
157 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
158 + goto error;
159 + }
160 +
161 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
162 +
163 + /* Adjust pointer for TLV type */
164 + rectype = *(ptr);
165 + offset++;
166 + size--;
167 +
168 + /*
169 + * Read the length. It can be either 1 or 2 bytes
170 + * depending on the code
171 + */
172 + if (rectype & ENV_LENGTH_8BITS) {
173 + /* Read the record type and length - 8 bits */
174 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
175 + goto error;
176 + }
177 + reclen = *(ptr);
178 + size--;
179 + offset++;
180 + }
181 + else {
182 + /* Read the record type and length - 16 bits, MSB first */
183 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
184 + goto error;
185 + }
186 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
187 + size -= 2;
188 + offset += 2;
189 + }
190 +
191 + if (reclen > size)
192 + break; /* should not happen, bad NVRAM */
193 +
194 + switch (rectype) {
195 + case ENV_TLV_TYPE_ENV:
196 + /* Read the TLV data */
197 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
198 + goto error;
199 + flg = *ptr++;
200 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
201 + if (envval) {
202 + *envval++ = '\0';
203 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
204 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
205 +#if 0
206 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
207 +#endif
208 + if(!strcmp(ptr, name)){
209 + return _valuestr;
210 + }
211 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
212 + return _valuestr;
213 + }
214 + break;
215 +
216 + default:
217 + /* Unknown TLV type, skip it. */
218 + break;
219 + }
220 +
221 + /*
222 + * Advance to next TLV
223 + */
224 +
225 + size -= (int)reclen;
226 + offset += reclen;
227 +
228 + /* Read the next record type */
229 + ptr = buffer;
230 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
231 + goto error;
232 + }
233 +
234 +error:
235 + return NULL;
236 +
237 +}
238 +
239 diff -Nur linux-2.4.32/arch/mips/bcm947xx/compressed/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/compressed/Makefile
240 --- linux-2.4.32/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
241 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/compressed/Makefile 2005-12-16 23:39:10.668819500 +0100
242 @@ -0,0 +1,33 @@
243 +#
244 +# Makefile for Broadcom BCM947XX boards
245 +#
246 +# Copyright 2001-2003, Broadcom Corporation
247 +# All Rights Reserved.
248 +#
249 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
250 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
251 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
252 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
253 +#
254 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
255 +#
256 +
257 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
258 +SYSTEM ?= $(TOPDIR)/vmlinux
259 +
260 +all: vmlinuz
261 +
262 +# Don't build dependencies, this may die if $(CC) isn't gcc
263 +dep:
264 +
265 +# Create a gzipped version named vmlinuz for compatibility
266 +vmlinuz: piggy
267 + gzip -c9 $< > $@
268 +
269 +piggy: $(SYSTEM)
270 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
271 +
272 +mrproper: clean
273 +
274 +clean:
275 + rm -f vmlinuz piggy
276 diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/int-handler.S linux-2.4.32-brcm/arch/mips/bcm947xx/generic/int-handler.S
277 --- linux-2.4.32/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
278 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/int-handler.S 2005-12-16 23:39:10.668819500 +0100
279 @@ -0,0 +1,51 @@
280 +/*
281 + * Generic interrupt handler for Broadcom MIPS boards
282 + *
283 + * Copyright 2004, Broadcom Corporation
284 + * All Rights Reserved.
285 + *
286 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
287 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
288 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
289 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
290 + *
291 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
292 + */
293 +
294 +#include <linux/config.h>
295 +
296 +#include <asm/asm.h>
297 +#include <asm/mipsregs.h>
298 +#include <asm/regdef.h>
299 +#include <asm/stackframe.h>
300 +
301 +/*
302 + * MIPS IRQ Source
303 + * -------- ------
304 + * 0 Software (ignored)
305 + * 1 Software (ignored)
306 + * 2 Combined hardware interrupt (hw0)
307 + * 3 Hardware
308 + * 4 Hardware
309 + * 5 Hardware
310 + * 6 Hardware
311 + * 7 R4k timer
312 + */
313 +
314 + .text
315 + .set noreorder
316 + .set noat
317 + .align 5
318 + NESTED(brcmIRQ, PT_SIZE, sp)
319 + SAVE_ALL
320 + CLI
321 + .set at
322 + .set noreorder
323 +
324 + jal brcm_irq_dispatch
325 + move a0, sp
326 +
327 + j ret_from_irq
328 + nop
329 +
330 + END(brcmIRQ)
331 diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/irq.c linux-2.4.32-brcm/arch/mips/bcm947xx/generic/irq.c
332 --- linux-2.4.32/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
333 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/irq.c 2005-12-16 23:39:10.668819500 +0100
334 @@ -0,0 +1,130 @@
335 +/*
336 + * Generic interrupt control functions for Broadcom MIPS boards
337 + *
338 + * Copyright 2004, Broadcom Corporation
339 + * All Rights Reserved.
340 + *
341 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
342 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
343 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
344 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
345 + *
346 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
347 + */
348 +
349 +#include <linux/config.h>
350 +#include <linux/init.h>
351 +#include <linux/kernel.h>
352 +#include <linux/types.h>
353 +#include <linux/interrupt.h>
354 +#include <linux/irq.h>
355 +
356 +#include <asm/irq.h>
357 +#include <asm/mipsregs.h>
358 +#include <asm/gdb-stub.h>
359 +
360 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
361 +
362 +extern asmlinkage void brcmIRQ(void);
363 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
364 +
365 +void
366 +brcm_irq_dispatch(struct pt_regs *regs)
367 +{
368 + u32 cause;
369 +
370 + cause = read_c0_cause() &
371 + read_c0_status() &
372 + CAUSEF_IP;
373 +
374 +#ifdef CONFIG_KERNPROF
375 + change_c0_status(cause | 1, 1);
376 +#else
377 + clear_c0_status(cause);
378 +#endif
379 +
380 + if (cause & CAUSEF_IP7)
381 + do_IRQ(7, regs);
382 + if (cause & CAUSEF_IP2)
383 + do_IRQ(2, regs);
384 + if (cause & CAUSEF_IP3)
385 + do_IRQ(3, regs);
386 + if (cause & CAUSEF_IP4)
387 + do_IRQ(4, regs);
388 + if (cause & CAUSEF_IP5)
389 + do_IRQ(5, regs);
390 + if (cause & CAUSEF_IP6)
391 + do_IRQ(6, regs);
392 +}
393 +
394 +static void
395 +enable_brcm_irq(unsigned int irq)
396 +{
397 + if (irq < 8)
398 + set_c0_status(1 << (irq + 8));
399 + else
400 + set_c0_status(IE_IRQ0);
401 +}
402 +
403 +static void
404 +disable_brcm_irq(unsigned int irq)
405 +{
406 + if (irq < 8)
407 + clear_c0_status(1 << (irq + 8));
408 + else
409 + clear_c0_status(IE_IRQ0);
410 +}
411 +
412 +static void
413 +ack_brcm_irq(unsigned int irq)
414 +{
415 + /* Already done in brcm_irq_dispatch */
416 +}
417 +
418 +static unsigned int
419 +startup_brcm_irq(unsigned int irq)
420 +{
421 + enable_brcm_irq(irq);
422 +
423 + return 0; /* never anything pending */
424 +}
425 +
426 +static void
427 +end_brcm_irq(unsigned int irq)
428 +{
429 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
430 + enable_brcm_irq(irq);
431 +}
432 +
433 +static struct hw_interrupt_type brcm_irq_type = {
434 + typename: "MIPS",
435 + startup: startup_brcm_irq,
436 + shutdown: disable_brcm_irq,
437 + enable: enable_brcm_irq,
438 + disable: disable_brcm_irq,
439 + ack: ack_brcm_irq,
440 + end: end_brcm_irq,
441 + NULL
442 +};
443 +
444 +void __init
445 +init_IRQ(void)
446 +{
447 + int i;
448 +
449 + for (i = 0; i < NR_IRQS; i++) {
450 + irq_desc[i].status = IRQ_DISABLED;
451 + irq_desc[i].action = 0;
452 + irq_desc[i].depth = 1;
453 + irq_desc[i].handler = &brcm_irq_type;
454 + }
455 +
456 + set_except_vector(0, brcmIRQ);
457 + change_c0_status(ST0_IM, ALLINTS);
458 +
459 +#ifdef CONFIG_REMOTE_DEBUG
460 + printk("Breaking into debugger...\n");
461 + set_debug_traps();
462 + breakpoint();
463 +#endif
464 +}
465 diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/generic/Makefile
466 --- linux-2.4.32/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
467 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/Makefile 2005-12-16 23:39:10.668819500 +0100
468 @@ -0,0 +1,15 @@
469 +#
470 +# Makefile for the BCM947xx specific kernel interface routines
471 +# under Linux.
472 +#
473 +
474 +.S.s:
475 + $(CPP) $(AFLAGS) $< -o $*.s
476 +.S.o:
477 + $(CC) $(AFLAGS) -c $< -o $*.o
478 +
479 +O_TARGET := brcm.o
480 +
481 +obj-y := int-handler.o irq.o
482 +
483 +include $(TOPDIR)/Rules.make
484 diff -Nur linux-2.4.32/arch/mips/bcm947xx/gpio.c linux-2.4.32-brcm/arch/mips/bcm947xx/gpio.c
485 --- linux-2.4.32/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
486 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/gpio.c 2005-12-16 23:39:10.668819500 +0100
487 @@ -0,0 +1,158 @@
488 +/*
489 + * GPIO char driver
490 + *
491 + * Copyright 2005, Broadcom Corporation
492 + * All Rights Reserved.
493 + *
494 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
495 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
496 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
497 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
498 + *
499 + * $Id$
500 + */
501 +
502 +#include <linux/module.h>
503 +#include <linux/init.h>
504 +#include <linux/fs.h>
505 +#include <linux/miscdevice.h>
506 +#include <asm/uaccess.h>
507 +
508 +#include <typedefs.h>
509 +#include <bcmutils.h>
510 +#include <sbutils.h>
511 +#include <bcmdevs.h>
512 +
513 +static sb_t *gpio_sbh;
514 +static int gpio_major;
515 +static devfs_handle_t gpio_dir;
516 +static struct {
517 + char *name;
518 + devfs_handle_t handle;
519 +} gpio_file[] = {
520 + { "in", NULL },
521 + { "out", NULL },
522 + { "outen", NULL },
523 + { "control", NULL }
524 +};
525 +
526 +static int
527 +gpio_open(struct inode *inode, struct file * file)
528 +{
529 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
530 + return -ENODEV;
531 +
532 + MOD_INC_USE_COUNT;
533 + return 0;
534 +}
535 +
536 +static int
537 +gpio_release(struct inode *inode, struct file * file)
538 +{
539 + MOD_DEC_USE_COUNT;
540 + return 0;
541 +}
542 +
543 +static ssize_t
544 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
545 +{
546 + u32 val;
547 +
548 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
549 + case 0:
550 + val = sb_gpioin(gpio_sbh);
551 + break;
552 + case 1:
553 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
554 + break;
555 + case 2:
556 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
557 + break;
558 + case 3:
559 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
560 + break;
561 + default:
562 + return -ENODEV;
563 + }
564 +
565 + if (put_user(val, (u32 *) buf))
566 + return -EFAULT;
567 +
568 + return sizeof(val);
569 +}
570 +
571 +static ssize_t
572 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
573 +{
574 + u32 val;
575 +
576 + if (get_user(val, (u32 *) buf))
577 + return -EFAULT;
578 +
579 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
580 + case 0:
581 + return -EACCES;
582 + case 1:
583 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
584 + break;
585 + case 2:
586 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
587 + break;
588 + case 3:
589 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
590 + break;
591 + default:
592 + return -ENODEV;
593 + }
594 +
595 + return sizeof(val);
596 +}
597 +
598 +static struct file_operations gpio_fops = {
599 + owner: THIS_MODULE,
600 + open: gpio_open,
601 + release: gpio_release,
602 + read: gpio_read,
603 + write: gpio_write,
604 +};
605 +
606 +static int __init
607 +gpio_init(void)
608 +{
609 + int i;
610 +
611 + if (!(gpio_sbh = sb_kattach()))
612 + return -ENODEV;
613 +
614 + sb_gpiosetcore(gpio_sbh);
615 +
616 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
617 + return gpio_major;
618 +
619 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
620 +
621 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
622 + gpio_file[i].handle = devfs_register(gpio_dir,
623 + gpio_file[i].name,
624 + DEVFS_FL_DEFAULT, gpio_major, i,
625 + S_IFCHR | S_IRUGO | S_IWUGO,
626 + &gpio_fops, NULL);
627 + }
628 +
629 + return 0;
630 +}
631 +
632 +static void __exit
633 +gpio_exit(void)
634 +{
635 + int i;
636 +
637 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
638 + devfs_unregister(gpio_file[i].handle);
639 + devfs_unregister(gpio_dir);
640 + devfs_unregister_chrdev(gpio_major, "gpio");
641 + sb_detach(gpio_sbh);
642 +}
643 +
644 +module_init(gpio_init);
645 +module_exit(gpio_exit);
646 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmdevs.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmdevs.h
647 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
648 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmdevs.h 2005-12-16 23:39:10.672819750 +0100
649 @@ -0,0 +1,391 @@
650 +/*
651 + * Broadcom device-specific manifest constants.
652 + *
653 + * Copyright 2005, Broadcom Corporation
654 + * All Rights Reserved.
655 + *
656 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
657 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
658 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
659 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
660 + * $Id$
661 + */
662 +
663 +#ifndef _BCMDEVS_H
664 +#define _BCMDEVS_H
665 +
666 +
667 +/* Known PCI vendor Id's */
668 +#define VENDOR_EPIGRAM 0xfeda
669 +#define VENDOR_BROADCOM 0x14e4
670 +#define VENDOR_3COM 0x10b7
671 +#define VENDOR_NETGEAR 0x1385
672 +#define VENDOR_DIAMOND 0x1092
673 +#define VENDOR_DELL 0x1028
674 +#define VENDOR_HP 0x0e11
675 +#define VENDOR_APPLE 0x106b
676 +
677 +/* PCI Device Id's */
678 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
679 +#define BCM4211_DEVICE_ID 0x4211
680 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
681 +#define BCM4231_DEVICE_ID 0x4231
682 +
683 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
684 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
685 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
686 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
687 +
688 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
689 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
690 +
691 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
692 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
693 +
694 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
695 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
696 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
697 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
698 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
699 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
700 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
701 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
702 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
703 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
704 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
705 +
706 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
707 +
708 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
709 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
710 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
711 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
712 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
713 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
714 +
715 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
716 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
717 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
718 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
719 +
720 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
721 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
722 +
723 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
724 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
725 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
726 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
727 +
728 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
729 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
730 +#define BCM4306_D11G_ID2 0x4325
731 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
732 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
733 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
734 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
735 +
736 +#define BCM4309_PKG_ID 1 /* 4309 package id */
737 +
738 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
739 +#define BCM4303_PKG_ID 2 /* 4303 package id */
740 +
741 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
742 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
743 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
744 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
745 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
746 +
747 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
748 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
749 +
750 +
751 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
752 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
753 +
754 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
755 +
756 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
757 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
758 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
759 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
760 +
761 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
762 +
763 +/* Address map */
764 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
765 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
766 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
767 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
768 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
769 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
770 +
771 +/* Core register space */
772 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
773 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
774 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
775 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
776 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
777 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
778 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
779 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
780 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
781 +
782 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
783 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
784 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
785 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
786 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
787 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
788 +
789 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
790 +
791 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
792 +
793 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
794 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
795 +
796 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
797 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
798 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
799 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
800 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
801 +
802 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
803 +
804 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
805 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
806 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
807 +
808 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
809 +
810 +/* PCMCIA vendor Id's */
811 +
812 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
813 +
814 +/* SDIO vendor Id's */
815 +#define VENDOR_BROADCOM_SDIO 0x00BF
816 +
817 +
818 +/* boardflags */
819 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
820 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
821 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
822 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
823 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
824 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
825 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
826 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
827 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
828 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
829 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
830 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
831 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
832 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
833 +
834 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
835 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
836 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
837 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
838 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
839 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
840 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
841 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
842 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
843 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
844 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
845 +
846 +/* Bus types */
847 +#define SB_BUS 0 /* Silicon Backplane */
848 +#define PCI_BUS 1 /* PCI target */
849 +#define PCMCIA_BUS 2 /* PCMCIA target */
850 +#define SDIO_BUS 3 /* SDIO target */
851 +#define JTAG_BUS 4 /* JTAG */
852 +
853 +/* Allows optimization for single-bus support */
854 +#ifdef BCMBUSTYPE
855 +#define BUSTYPE(bus) (BCMBUSTYPE)
856 +#else
857 +#define BUSTYPE(bus) (bus)
858 +#endif
859 +
860 +/* power control defines */
861 +#define PLL_DELAY 150 /* us pll on delay */
862 +#define FREF_DELAY 200 /* us fref change delay */
863 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
864 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
865 +
866 +/* Reference Board Types */
867 +
868 +#define BU4710_BOARD 0x0400
869 +#define VSIM4710_BOARD 0x0401
870 +#define QT4710_BOARD 0x0402
871 +
872 +#define BU4610_BOARD 0x0403
873 +#define VSIM4610_BOARD 0x0404
874 +
875 +#define BU4307_BOARD 0x0405
876 +#define BCM94301CB_BOARD 0x0406
877 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
878 +#define BCM94301MP_BOARD 0x0407
879 +#define BCM94307MP_BOARD 0x0408
880 +#define BCMAP4307_BOARD 0x0409
881 +
882 +#define BU4309_BOARD 0x040a
883 +#define BCM94309CB_BOARD 0x040b
884 +#define BCM94309MP_BOARD 0x040c
885 +#define BCM4309AP_BOARD 0x040d
886 +
887 +#define BCM94302MP_BOARD 0x040e
888 +
889 +#define VSIM4310_BOARD 0x040f
890 +#define BU4711_BOARD 0x0410
891 +#define BCM94310U_BOARD 0x0411
892 +#define BCM94310AP_BOARD 0x0412
893 +#define BCM94310MP_BOARD 0x0414
894 +
895 +#define BU4306_BOARD 0x0416
896 +#define BCM94306CB_BOARD 0x0417
897 +#define BCM94306MP_BOARD 0x0418
898 +
899 +#define BCM94710D_BOARD 0x041a
900 +#define BCM94710R1_BOARD 0x041b
901 +#define BCM94710R4_BOARD 0x041c
902 +#define BCM94710AP_BOARD 0x041d
903 +
904 +
905 +#define BU2050_BOARD 0x041f
906 +
907 +
908 +#define BCM94309G_BOARD 0x0421
909 +
910 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
911 +
912 +#define BU4704_BOARD 0x0423
913 +#define BU4702_BOARD 0x0424
914 +
915 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
916 +
917 +#define BU4317_BOARD 0x0426
918 +
919 +
920 +#define BCM94702MN_BOARD 0x0428
921 +
922 +/* BCM4702 1U CompactPCI Board */
923 +#define BCM94702CPCI_BOARD 0x0429
924 +
925 +/* BCM4702 with BCM95380 VLAN Router */
926 +#define BCM95380RR_BOARD 0x042a
927 +
928 +/* cb4306 with SiGe PA */
929 +#define BCM94306CBSG_BOARD 0x042b
930 +
931 +/* mp4301 with 2050 radio */
932 +#define BCM94301MPL_BOARD 0x042c
933 +
934 +/* cb4306 with SiGe PA */
935 +#define PCSG94306_BOARD 0x042d
936 +
937 +/* bu4704 with sdram */
938 +#define BU4704SD_BOARD 0x042e
939 +
940 +/* Dual 11a/11g Router */
941 +#define BCM94704AGR_BOARD 0x042f
942 +
943 +/* 11a-only minipci */
944 +#define BCM94308MP_BOARD 0x0430
945 +
946 +
947 +
948 +/* BCM94317 boards */
949 +#define BCM94317CB_BOARD 0x0440
950 +#define BCM94317MP_BOARD 0x0441
951 +#define BCM94317PCMCIA_BOARD 0x0442
952 +#define BCM94317SDIO_BOARD 0x0443
953 +
954 +#define BU4712_BOARD 0x0444
955 +#define BU4712SD_BOARD 0x045d
956 +#define BU4712L_BOARD 0x045f
957 +
958 +/* BCM4712 boards */
959 +#define BCM94712AP_BOARD 0x0445
960 +#define BCM94712P_BOARD 0x0446
961 +
962 +/* BCM4318 boards */
963 +#define BU4318_BOARD 0x0447
964 +#define CB4318_BOARD 0x0448
965 +#define MPG4318_BOARD 0x0449
966 +#define MP4318_BOARD 0x044a
967 +#define SD4318_BOARD 0x044b
968 +
969 +/* BCM63XX boards */
970 +#define BCM96338_BOARD 0x6338
971 +#define BCM96345_BOARD 0x6345
972 +#define BCM96348_BOARD 0x6348
973 +
974 +/* Another mp4306 with SiGe */
975 +#define BCM94306P_BOARD 0x044c
976 +
977 +/* CF-like 4317 modules */
978 +#define BCM94317CF_BOARD 0x044d
979 +
980 +/* mp4303 */
981 +#define BCM94303MP_BOARD 0x044e
982 +
983 +/* mpsgh4306 */
984 +#define BCM94306MPSGH_BOARD 0x044f
985 +
986 +/* BRCM 4306 w/ Front End Modules */
987 +#define BCM94306MPM 0x0450
988 +#define BCM94306MPL 0x0453
989 +
990 +/* 4712agr */
991 +#define BCM94712AGR_BOARD 0x0451
992 +
993 +/* The real CF 4317 board */
994 +#define CFI4317_BOARD 0x0452
995 +
996 +/* pcmcia 4303 */
997 +#define PC4303_BOARD 0x0454
998 +
999 +/* 5350K */
1000 +#define BCM95350K_BOARD 0x0455
1001 +
1002 +/* 5350R */
1003 +#define BCM95350R_BOARD 0x0456
1004 +
1005 +/* 4306mplna */
1006 +#define BCM94306MPLNA_BOARD 0x0457
1007 +
1008 +/* 4320 boards */
1009 +#define BU4320_BOARD 0x0458
1010 +#define BU4320S_BOARD 0x0459
1011 +#define BCM94320PH_BOARD 0x045a
1012 +
1013 +/* 4306mph */
1014 +#define BCM94306MPH_BOARD 0x045b
1015 +
1016 +/* 4306pciv */
1017 +#define BCM94306PCIV_BOARD 0x045c
1018 +
1019 +#define BU4712SD_BOARD 0x045d
1020 +
1021 +#define BCM94320PFLSH_BOARD 0x045e
1022 +
1023 +#define BU4712L_BOARD 0x045f
1024 +#define BCM94712LGR_BOARD 0x0460
1025 +#define BCM94320R_BOARD 0x0461
1026 +
1027 +#define BU5352_BOARD 0x0462
1028 +
1029 +#define BCM94318MPGH_BOARD 0x0463
1030 +
1031 +
1032 +#define BCM95352GR_BOARD 0x0467
1033 +
1034 +/* bcm95351agr */
1035 +#define BCM95351AGR_BOARD 0x0470
1036 +
1037 +/* # of GPIO pins */
1038 +#define GPIO_NUMPINS 16
1039 +
1040 +#endif /* _BCMDEVS_H */
1041 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmendian.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmendian.h
1042 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
1043 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmendian.h 2005-12-16 23:39:10.672819750 +0100
1044 @@ -0,0 +1,152 @@
1045 +/*
1046 + * local version of endian.h - byte order defines
1047 + *
1048 + * Copyright 2005, Broadcom Corporation
1049 + * All Rights Reserved.
1050 + *
1051 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1052 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1053 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1054 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1055 + *
1056 + * $Id$
1057 +*/
1058 +
1059 +#ifndef _BCMENDIAN_H_
1060 +#define _BCMENDIAN_H_
1061 +
1062 +#include <typedefs.h>
1063 +
1064 +/* Byte swap a 16 bit value */
1065 +#define BCMSWAP16(val) \
1066 + ((uint16)( \
1067 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
1068 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
1069 +
1070 +/* Byte swap a 32 bit value */
1071 +#define BCMSWAP32(val) \
1072 + ((uint32)( \
1073 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
1074 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
1075 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
1076 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
1077 +
1078 +/* 2 Byte swap a 32 bit value */
1079 +#define BCMSWAP32BY16(val) \
1080 + ((uint32)( \
1081 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
1082 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
1083 +
1084 +
1085 +static INLINE uint16
1086 +bcmswap16(uint16 val)
1087 +{
1088 + return BCMSWAP16(val);
1089 +}
1090 +
1091 +static INLINE uint32
1092 +bcmswap32(uint32 val)
1093 +{
1094 + return BCMSWAP32(val);
1095 +}
1096 +
1097 +static INLINE uint32
1098 +bcmswap32by16(uint32 val)
1099 +{
1100 + return BCMSWAP32BY16(val);
1101 +}
1102 +
1103 +/* buf - start of buffer of shorts to swap */
1104 +/* len - byte length of buffer */
1105 +static INLINE void
1106 +bcmswap16_buf(uint16 *buf, uint len)
1107 +{
1108 + len = len/2;
1109 +
1110 + while(len--){
1111 + *buf = bcmswap16(*buf);
1112 + buf++;
1113 + }
1114 +}
1115 +
1116 +#ifndef hton16
1117 +#ifndef IL_BIGENDIAN
1118 +#define HTON16(i) BCMSWAP16(i)
1119 +#define hton16(i) bcmswap16(i)
1120 +#define hton32(i) bcmswap32(i)
1121 +#define ntoh16(i) bcmswap16(i)
1122 +#define ntoh32(i) bcmswap32(i)
1123 +#define ltoh16(i) (i)
1124 +#define ltoh32(i) (i)
1125 +#define htol16(i) (i)
1126 +#define htol32(i) (i)
1127 +#else
1128 +#define HTON16(i) (i)
1129 +#define hton16(i) (i)
1130 +#define hton32(i) (i)
1131 +#define ntoh16(i) (i)
1132 +#define ntoh32(i) (i)
1133 +#define ltoh16(i) bcmswap16(i)
1134 +#define ltoh32(i) bcmswap32(i)
1135 +#define htol16(i) bcmswap16(i)
1136 +#define htol32(i) bcmswap32(i)
1137 +#endif
1138 +#endif
1139 +
1140 +#ifndef IL_BIGENDIAN
1141 +#define ltoh16_buf(buf, i)
1142 +#define htol16_buf(buf, i)
1143 +#else
1144 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1145 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1146 +#endif
1147 +
1148 +/*
1149 +* load 16-bit value from unaligned little endian byte array.
1150 +*/
1151 +static INLINE uint16
1152 +ltoh16_ua(uint8 *bytes)
1153 +{
1154 + return (bytes[1]<<8)+bytes[0];
1155 +}
1156 +
1157 +/*
1158 +* load 32-bit value from unaligned little endian byte array.
1159 +*/
1160 +static INLINE uint32
1161 +ltoh32_ua(uint8 *bytes)
1162 +{
1163 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
1164 +}
1165 +
1166 +/*
1167 +* load 16-bit value from unaligned big(network) endian byte array.
1168 +*/
1169 +static INLINE uint16
1170 +ntoh16_ua(uint8 *bytes)
1171 +{
1172 + return (bytes[0]<<8)+bytes[1];
1173 +}
1174 +
1175 +/*
1176 +* load 32-bit value from unaligned big(network) endian byte array.
1177 +*/
1178 +static INLINE uint32
1179 +ntoh32_ua(uint8 *bytes)
1180 +{
1181 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
1182 +}
1183 +
1184 +#define ltoh_ua(ptr) ( \
1185 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1186 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
1187 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
1188 +)
1189 +
1190 +#define ntoh_ua(ptr) ( \
1191 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1192 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
1193 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
1194 +)
1195 +
1196 +#endif /* _BCMENDIAN_H_ */
1197 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmnvram.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmnvram.h
1198 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1199 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmnvram.h 2005-12-16 23:39:10.700821500 +0100
1200 @@ -0,0 +1,141 @@
1201 +/*
1202 + * NVRAM variable manipulation
1203 + *
1204 + * Copyright 2005, Broadcom Corporation
1205 + * All Rights Reserved.
1206 + *
1207 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1208 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1209 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1210 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1211 + *
1212 + * $Id$
1213 + */
1214 +
1215 +#ifndef _bcmnvram_h_
1216 +#define _bcmnvram_h_
1217 +
1218 +#ifndef _LANGUAGE_ASSEMBLY
1219 +
1220 +#include <typedefs.h>
1221 +
1222 +struct nvram_header {
1223 + uint32 magic;
1224 + uint32 len;
1225 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
1226 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
1227 + uint32 config_ncdl; /* ncdl values for memc */
1228 +};
1229 +
1230 +struct nvram_tuple {
1231 + char *name;
1232 + char *value;
1233 + struct nvram_tuple *next;
1234 +};
1235 +
1236 +/*
1237 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1238 + * platforms.
1239 + */
1240 +extern int BCMINIT(nvram_init)(void *sbh);
1241 +
1242 +/*
1243 + * Disable NVRAM access. May be unnecessary or undefined on certain
1244 + * platforms.
1245 + */
1246 +extern void BCMINIT(nvram_exit)(void *sbh);
1247 +
1248 +/*
1249 + * Get the value of an NVRAM variable. The pointer returned may be
1250 + * invalid after a set.
1251 + * @param name name of variable to get
1252 + * @return value of variable or NULL if undefined
1253 + */
1254 +extern char * BCMINIT(nvram_get)(const char *name);
1255 +
1256 +/*
1257 + * Read the reset GPIO value from the nvram and set the GPIO
1258 + * as input
1259 + */
1260 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
1261 +
1262 +/*
1263 + * Get the value of an NVRAM variable.
1264 + * @param name name of variable to get
1265 + * @return value of variable or NUL if undefined
1266 + */
1267 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1268 +
1269 +/*
1270 + * Match an NVRAM variable.
1271 + * @param name name of variable to match
1272 + * @param match value to compare against value of variable
1273 + * @return TRUE if variable is defined and its value is string equal
1274 + * to match or FALSE otherwise
1275 + */
1276 +static INLINE int
1277 +nvram_match(char *name, char *match) {
1278 + const char *value = BCMINIT(nvram_get)(name);
1279 + return (value && !strcmp(value, match));
1280 +}
1281 +
1282 +/*
1283 + * Inversely match an NVRAM variable.
1284 + * @param name name of variable to match
1285 + * @param match value to compare against value of variable
1286 + * @return TRUE if variable is defined and its value is not string
1287 + * equal to invmatch or FALSE otherwise
1288 + */
1289 +static INLINE int
1290 +nvram_invmatch(char *name, char *invmatch) {
1291 + const char *value = BCMINIT(nvram_get)(name);
1292 + return (value && strcmp(value, invmatch));
1293 +}
1294 +
1295 +/*
1296 + * Set the value of an NVRAM variable. The name and value strings are
1297 + * copied into private storage. Pointers to previously set values
1298 + * may become invalid. The new value may be immediately
1299 + * retrieved but will not be permanently stored until a commit.
1300 + * @param name name of variable to set
1301 + * @param value value of variable
1302 + * @return 0 on success and errno on failure
1303 + */
1304 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1305 +
1306 +/*
1307 + * Unset an NVRAM variable. Pointers to previously set values
1308 + * remain valid until a set.
1309 + * @param name name of variable to unset
1310 + * @return 0 on success and errno on failure
1311 + * NOTE: use nvram_commit to commit this change to flash.
1312 + */
1313 +extern int BCMINIT(nvram_unset)(const char *name);
1314 +
1315 +/*
1316 + * Commit NVRAM variables to permanent storage. All pointers to values
1317 + * may be invalid after a commit.
1318 + * NVRAM values are undefined after a commit.
1319 + * @return 0 on success and errno on failure
1320 + */
1321 +extern int BCMINIT(nvram_commit)(void);
1322 +
1323 +/*
1324 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1325 + * @param buf buffer to store variables
1326 + * @param count size of buffer in bytes
1327 + * @return 0 on success and errno on failure
1328 + */
1329 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1330 +
1331 +#endif /* _LANGUAGE_ASSEMBLY */
1332 +
1333 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1334 +#define NVRAM_VERSION 1
1335 +#define NVRAM_HEADER_SIZE 20
1336 +#define NVRAM_SPACE 0x8000
1337 +
1338 +#define NVRAM_MAX_VALUE_LEN 255
1339 +#define NVRAM_MAX_PARAM_LEN 64
1340 +
1341 +#endif /* _bcmnvram_h_ */
1342 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmsrom.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmsrom.h
1343 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1344 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmsrom.h 2005-12-16 23:39:10.704821750 +0100
1345 @@ -0,0 +1,23 @@
1346 +/*
1347 + * Misc useful routines to access NIC local SROM/OTP .
1348 + *
1349 + * Copyright 2005, Broadcom Corporation
1350 + * All Rights Reserved.
1351 + *
1352 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1353 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1354 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1355 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1356 + *
1357 + * $Id$
1358 + */
1359 +
1360 +#ifndef _bcmsrom_h_
1361 +#define _bcmsrom_h_
1362 +
1363 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
1364 +
1365 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1366 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1367 +
1368 +#endif /* _bcmsrom_h_ */
1369 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmutils.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmutils.h
1370 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1371 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmutils.h 2005-12-16 23:39:10.704821750 +0100
1372 @@ -0,0 +1,313 @@
1373 +/*
1374 + * Misc useful os-independent macros and functions.
1375 + *
1376 + * Copyright 2005, Broadcom Corporation
1377 + * All Rights Reserved.
1378 + *
1379 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1380 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1381 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1382 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1383 + * $Id$
1384 + */
1385 +
1386 +#ifndef _bcmutils_h_
1387 +#define _bcmutils_h_
1388 +
1389 +/*** driver-only section ***/
1390 +#ifdef BCMDRIVER
1391 +#include <osl.h>
1392 +
1393 +#define _BCM_U 0x01 /* upper */
1394 +#define _BCM_L 0x02 /* lower */
1395 +#define _BCM_D 0x04 /* digit */
1396 +#define _BCM_C 0x08 /* cntrl */
1397 +#define _BCM_P 0x10 /* punct */
1398 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1399 +#define _BCM_X 0x40 /* hex digit */
1400 +#define _BCM_SP 0x80 /* hard space (0x20) */
1401 +
1402 +#define GPIO_PIN_NOTDEFINED 0x20
1403 +
1404 +extern unsigned char bcm_ctype[];
1405 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1406 +
1407 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1408 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1409 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1410 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1411 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1412 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1413 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1414 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1415 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1416 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1417 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1418 +
1419 +/*
1420 + * Spin at most 'us' microseconds while 'exp' is true.
1421 + * Caller should explicitly test 'exp' when this completes
1422 + * and take appropriate error action if 'exp' is still true.
1423 + */
1424 +#define SPINWAIT(exp, us) { \
1425 + uint countdown = (us) + 9; \
1426 + while ((exp) && (countdown >= 10)) {\
1427 + OSL_DELAY(10); \
1428 + countdown -= 10; \
1429 + } \
1430 +}
1431 +
1432 +/* generic osl packet queue */
1433 +struct pktq {
1434 + void *head; /* first packet to dequeue */
1435 + void *tail; /* last packet to dequeue */
1436 + uint len; /* number of queued packets */
1437 + uint maxlen; /* maximum number of queued packets */
1438 + bool priority; /* enqueue by packet priority */
1439 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1440 +};
1441 +#define DEFAULT_QLEN 128
1442 +
1443 +#define pktq_len(q) ((q)->len)
1444 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1445 +#define pktq_head(q) ((q)->head)
1446 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1447 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1448 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1449 +
1450 +/* externs */
1451 +/* packet */
1452 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
1453 +extern uint pkttotlen(osl_t *osh, void *);
1454 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1455 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1456 +extern void *pktdeq(struct pktq *q);
1457 +extern void *pktdeqtail(struct pktq *q);
1458 +/* string */
1459 +extern uint bcm_atoi(char *s);
1460 +extern uchar bcm_toupper(uchar c);
1461 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1462 +extern char *bcmstrstr(char *haystack, char *needle);
1463 +extern char *bcmstrcat(char *dest, const char *src);
1464 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1465 +/* ethernet address */
1466 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1467 +extern int bcm_ether_atoe(char *p, char *ea);
1468 +/* delay */
1469 +extern void bcm_mdelay(uint ms);
1470 +/* variable access */
1471 +extern char *getvar(char *vars, char *name);
1472 +extern int getintvar(char *vars, char *name);
1473 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1474 +#define bcmlog(fmt, a1, a2)
1475 +#define bcmdumplog(buf, size) *buf = '\0'
1476 +#define bcmdumplogent(buf, idx) -1
1477 +
1478 +#endif /* #ifdef BCMDRIVER */
1479 +
1480 +/*** driver/apps-shared section ***/
1481 +
1482 +#define BCME_STRLEN 64
1483 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
1484 +
1485 +
1486 +/*
1487 + * error codes could be added but the defined ones shouldn't be changed/deleted
1488 + * these error codes are exposed to the user code
1489 + * when ever a new error code is added to this list
1490 + * please update errorstring table with the related error string and
1491 + * update osl files with os specific errorcode map
1492 +*/
1493 +
1494 +#define BCME_ERROR -1 /* Error generic */
1495 +#define BCME_BADARG -2 /* Bad Argument */
1496 +#define BCME_BADOPTION -3 /* Bad option */
1497 +#define BCME_NOTUP -4 /* Not up */
1498 +#define BCME_NOTDOWN -5 /* Not down */
1499 +#define BCME_NOTAP -6 /* Not AP */
1500 +#define BCME_NOTSTA -7 /* Not STA */
1501 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
1502 +#define BCME_RADIOOFF -9 /* Radio Off */
1503 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
1504 +#define BCME_NOCLK -11 /* No Clock*/
1505 +#define BCME_BADRATESET -12 /* BAD RateSet*/
1506 +#define BCME_BADBAND -13 /* BAD Band */
1507 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
1508 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
1509 +#define BCME_BUSY -16 /* Busy*/
1510 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
1511 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
1512 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
1513 +#define BCME_BADCHAN -20 /* BAD Channel */
1514 +#define BCME_BADADDR -21 /* BAD Address*/
1515 +#define BCME_NORESOURCE -22 /* No resources*/
1516 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
1517 +#define BCME_BADLEN -24 /* Bad Length*/
1518 +#define BCME_NOTREADY -25 /* Not ready Yet*/
1519 +#define BCME_EPERM -26 /* Not Permitted */
1520 +#define BCME_NOMEM -27 /* No Memory */
1521 +#define BCME_ASSOCIATED -28 /* Associated */
1522 +#define BCME_RANGE -29 /* Range Error*/
1523 +#define BCME_NOTFOUND -30 /* Not found */
1524 +#define BCME_LAST BCME_NOTFOUND
1525 +
1526 +#ifndef ABS
1527 +#define ABS(a) (((a)<0)?-(a):(a))
1528 +#endif
1529 +
1530 +#ifndef MIN
1531 +#define MIN(a, b) (((a)<(b))?(a):(b))
1532 +#endif
1533 +
1534 +#ifndef MAX
1535 +#define MAX(a, b) (((a)>(b))?(a):(b))
1536 +#endif
1537 +
1538 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1539 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1540 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1541 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1542 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
1543 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1544 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1545 +
1546 +/* bit map related macros */
1547 +#ifndef setbit
1548 +#define NBBY 8 /* 8 bits per byte */
1549 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1550 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1551 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1552 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1553 +#endif
1554 +
1555 +#define NBITS(type) (sizeof(type) * 8)
1556 +#define NBITVAL(bits) (1 << (bits))
1557 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
1558 +
1559 +/* crc defines */
1560 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1561 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1562 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1563 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1564 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1565 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1566 +
1567 +/* bcm_format_flags() bit description structure */
1568 +typedef struct bcm_bit_desc {
1569 + uint32 bit;
1570 + char* name;
1571 +} bcm_bit_desc_t;
1572 +
1573 +/* tag_ID/length/value_buffer tuple */
1574 +typedef struct bcm_tlv {
1575 + uint8 id;
1576 + uint8 len;
1577 + uint8 data[1];
1578 +} bcm_tlv_t;
1579 +
1580 +/* Check that bcm_tlv_t fits into the given buflen */
1581 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
1582 +
1583 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1584 +#define ETHER_ADDR_STR_LEN 18
1585 +
1586 +/* unaligned load and store macros */
1587 +#ifdef IL_BIGENDIAN
1588 +static INLINE uint32
1589 +load32_ua(uint8 *a)
1590 +{
1591 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1592 +}
1593 +
1594 +static INLINE void
1595 +store32_ua(uint8 *a, uint32 v)
1596 +{
1597 + a[0] = (v >> 24) & 0xff;
1598 + a[1] = (v >> 16) & 0xff;
1599 + a[2] = (v >> 8) & 0xff;
1600 + a[3] = v & 0xff;
1601 +}
1602 +
1603 +static INLINE uint16
1604 +load16_ua(uint8 *a)
1605 +{
1606 + return ((a[0] << 8) | a[1]);
1607 +}
1608 +
1609 +static INLINE void
1610 +store16_ua(uint8 *a, uint16 v)
1611 +{
1612 + a[0] = (v >> 8) & 0xff;
1613 + a[1] = v & 0xff;
1614 +}
1615 +
1616 +#else
1617 +
1618 +static INLINE uint32
1619 +load32_ua(uint8 *a)
1620 +{
1621 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
1622 +}
1623 +
1624 +static INLINE void
1625 +store32_ua(uint8 *a, uint32 v)
1626 +{
1627 + a[3] = (v >> 24) & 0xff;
1628 + a[2] = (v >> 16) & 0xff;
1629 + a[1] = (v >> 8) & 0xff;
1630 + a[0] = v & 0xff;
1631 +}
1632 +
1633 +static INLINE uint16
1634 +load16_ua(uint8 *a)
1635 +{
1636 + return ((a[1] << 8) | a[0]);
1637 +}
1638 +
1639 +static INLINE void
1640 +store16_ua(uint8 *a, uint16 v)
1641 +{
1642 + a[1] = (v >> 8) & 0xff;
1643 + a[0] = v & 0xff;
1644 +}
1645 +
1646 +#endif
1647 +
1648 +/* externs */
1649 +/* crc */
1650 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
1651 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
1652 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
1653 +/* format/print */
1654 +/* IE parsing */
1655 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
1656 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
1657 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
1658 +
1659 +/* bcmerror*/
1660 +extern const char *bcmerrorstr(int bcmerror);
1661 +
1662 +/* multi-bool data type: set of bools, mbool is true if any is set */
1663 +typedef uint32 mbool;
1664 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
1665 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
1666 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
1667 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
1668 +
1669 +/* power conversion */
1670 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
1671 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
1672 +
1673 +/* generic datastruct to help dump routines */
1674 +struct fielddesc {
1675 + char *nameandfmt;
1676 + uint32 offset;
1677 + uint32 len;
1678 +};
1679 +
1680 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
1681 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
1682 +
1683 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
1684 +
1685 +#endif /* _bcmutils_h_ */
1686 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/hnddma.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/hnddma.h
1687 --- linux-2.4.32/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
1688 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/hnddma.h 2005-12-16 23:39:10.708822000 +0100
1689 @@ -0,0 +1,71 @@
1690 +/*
1691 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
1692 + * This supports the following chips: BCM42xx, 44xx, 47xx .
1693 + *
1694 + * Copyright 2005, Broadcom Corporation
1695 + * All Rights Reserved.
1696 + *
1697 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1698 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1699 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1700 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1701 + * $Id$
1702 + */
1703 +
1704 +#ifndef _hnddma_h_
1705 +#define _hnddma_h_
1706 +
1707 +/* export structure */
1708 +typedef volatile struct {
1709 + /* rx error counters */
1710 + uint rxgiants; /* rx giant frames */
1711 + uint rxnobuf; /* rx out of dma descriptors */
1712 + /* tx error counters */
1713 + uint txnobuf; /* tx out of dma descriptors */
1714 +} hnddma_t;
1715 +
1716 +#ifndef di_t
1717 +#define di_t void
1718 +#endif
1719 +
1720 +#ifndef osl_t
1721 +#define osl_t void
1722 +#endif
1723 +
1724 +/* externs */
1725 +extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
1726 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
1727 +extern void dma_detach(di_t *di);
1728 +extern void dma_txreset(di_t *di);
1729 +extern void dma_rxreset(di_t *di);
1730 +extern void dma_txinit(di_t *di);
1731 +extern bool dma_txenabled(di_t *di);
1732 +extern void dma_rxinit(di_t *di);
1733 +extern void dma_rxenable(di_t *di);
1734 +extern bool dma_rxenabled(di_t *di);
1735 +extern void dma_txsuspend(di_t *di);
1736 +extern void dma_txresume(di_t *di);
1737 +extern bool dma_txsuspended(di_t *di);
1738 +extern bool dma_txsuspendedidle(di_t *di);
1739 +extern bool dma_txstopped(di_t *di);
1740 +extern bool dma_rxstopped(di_t *di);
1741 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
1742 +extern void dma_fifoloopbackenable(di_t *di);
1743 +extern void *dma_rx(di_t *di);
1744 +extern void dma_rxfill(di_t *di);
1745 +extern void dma_txreclaim(di_t *di, bool forceall);
1746 +extern void dma_rxreclaim(di_t *di);
1747 +extern uintptr dma_getvar(di_t *di, char *name);
1748 +extern void *dma_getnexttxp(di_t *di, bool forceall);
1749 +extern void *dma_peeknexttxp(di_t *di);
1750 +extern void *dma_getnextrxp(di_t *di, bool forceall);
1751 +extern void dma_txblock(di_t *di);
1752 +extern void dma_txunblock(di_t *di);
1753 +extern uint dma_txactive(di_t *di);
1754 +extern void dma_txrotate(di_t *di);
1755 +
1756 +extern void dma_rxpiomode(dma32regs_t *);
1757 +extern void dma_txpioloopback(dma32regs_t *);
1758 +
1759 +
1760 +#endif /* _hnddma_h_ */
1761 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/hndmips.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/hndmips.h
1762 --- linux-2.4.32/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
1763 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/hndmips.h 2005-12-16 23:39:10.708822000 +0100
1764 @@ -0,0 +1,16 @@
1765 +/*
1766 + * Alternate include file for HND sbmips.h since CFE also ships with
1767 + * a sbmips.h.
1768 + *
1769 + * Copyright 2005, Broadcom Corporation
1770 + * All Rights Reserved.
1771 + *
1772 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1773 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1774 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1775 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1776 + *
1777 + * $Id$
1778 + */
1779 +
1780 +#include "sbmips.h"
1781 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/linux_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/linux_osl.h
1782 --- linux-2.4.32/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
1783 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/linux_osl.h 2005-12-16 23:39:10.708822000 +0100
1784 @@ -0,0 +1,371 @@
1785 +/*
1786 + * Linux OS Independent Layer
1787 + *
1788 + * Copyright 2005, Broadcom Corporation
1789 + * All Rights Reserved.
1790 + *
1791 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1792 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1793 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1794 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1795 + *
1796 + * $Id$
1797 + */
1798 +
1799 +#ifndef _linux_osl_h_
1800 +#define _linux_osl_h_
1801 +
1802 +#include <typedefs.h>
1803 +
1804 +/* use current 2.4.x calling conventions */
1805 +#include <linuxver.h>
1806 +
1807 +/* assert and panic */
1808 +#ifdef __GNUC__
1809 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
1810 +#if GCC_VERSION > 30100
1811 +#define ASSERT(exp) do {} while (0)
1812 +#else
1813 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
1814 +#define ASSERT(exp)
1815 +#endif
1816 +#endif
1817 +
1818 +/* microsecond delay */
1819 +#define OSL_DELAY(usec) osl_delay(usec)
1820 +extern void osl_delay(uint usec);
1821 +
1822 +/* PCMCIA attribute space access macros */
1823 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
1824 +struct pcmcia_dev {
1825 + dev_link_t link; /* PCMCIA device pointer */
1826 + dev_node_t node; /* PCMCIA node structure */
1827 + void *base; /* Mapped attribute memory window */
1828 + size_t size; /* Size of window */
1829 + void *drv; /* Driver data */
1830 +};
1831 +#endif
1832 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
1833 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
1834 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
1835 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
1836 +extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
1837 +extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
1838 +
1839 +/* PCI configuration space access macros */
1840 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
1841 + osl_pci_read_config((osh), (offset), (size))
1842 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
1843 + osl_pci_write_config((osh), (offset), (size), (val))
1844 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
1845 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
1846 +
1847 +/* PCI device bus # and slot # */
1848 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
1849 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
1850 +extern uint osl_pci_bus(osl_t *osh);
1851 +extern uint osl_pci_slot(osl_t *osh);
1852 +
1853 +/* OSL initialization */
1854 +extern osl_t *osl_attach(void *pdev);
1855 +extern void osl_detach(osl_t *osh);
1856 +
1857 +/* host/bus architecture-specific byte swap */
1858 +#define BUS_SWAP32(v) (v)
1859 +
1860 +/* general purpose memory allocation */
1861 +
1862 +#if defined(BCMDBG_MEM)
1863 +
1864 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
1865 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
1866 +#define MALLOCED(osh) osl_malloced((osh))
1867 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
1868 +extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
1869 +extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
1870 +extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
1871 +
1872 +#else
1873 +
1874 +#define MALLOC(osh, size) osl_malloc((osh), (size))
1875 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
1876 +#define MALLOCED(osh) osl_malloced((osh))
1877 +
1878 +#endif /* BCMDBG_MEM */
1879 +
1880 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
1881 +
1882 +extern void *osl_malloc(osl_t *osh, uint size);
1883 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
1884 +extern uint osl_malloced(osl_t *osh);
1885 +extern uint osl_malloc_failed(osl_t *osh);
1886 +
1887 +/* allocate/free shared (dma-able) consistent memory */
1888 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
1889 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
1890 + osl_dma_alloc_consistent((osh), (size), (pap))
1891 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
1892 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
1893 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
1894 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
1895 +
1896 +/* map/unmap direction */
1897 +#define DMA_TX 1
1898 +#define DMA_RX 2
1899 +
1900 +/* map/unmap shared (dma-able) memory */
1901 +#define DMA_MAP(osh, va, size, direction, p) \
1902 + osl_dma_map((osh), (va), (size), (direction))
1903 +#define DMA_UNMAP(osh, pa, size, direction, p) \
1904 + osl_dma_unmap((osh), (pa), (size), (direction))
1905 +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
1906 +extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
1907 +
1908 +/* register access macros */
1909 +#if defined(BCMJTAG)
1910 +#include <bcmjtag.h>
1911 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
1912 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
1913 +#endif
1914 +
1915 +/*
1916 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
1917 + * Macros expand to calls to functions defined in linux_osl.c .
1918 + */
1919 +#ifndef BINOSL
1920 +
1921 +/* string library, kernel mode */
1922 +#define printf(fmt, args...) printk(fmt, ## args)
1923 +#include <linux/kernel.h>
1924 +#include <linux/string.h>
1925 +
1926 +/* register access macros */
1927 +#if !defined(BCMJTAG)
1928 +#ifndef IL_BIGENDIAN
1929 +#define R_REG(r) ( \
1930 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
1931 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
1932 + readl((volatile uint32*)(r)) \
1933 +)
1934 +#define W_REG(r, v) do { \
1935 + switch (sizeof(*(r))) { \
1936 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
1937 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
1938 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
1939 + } \
1940 +} while (0)
1941 +#else /* IL_BIGENDIAN */
1942 +#define R_REG(r) ({ \
1943 + __typeof(*(r)) __osl_v; \
1944 + switch (sizeof(*(r))) { \
1945 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
1946 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
1947 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
1948 + } \
1949 + __osl_v; \
1950 +})
1951 +#define W_REG(r, v) do { \
1952 + switch (sizeof(*(r))) { \
1953 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
1954 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
1955 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
1956 + } \
1957 +} while (0)
1958 +#endif
1959 +#endif
1960 +
1961 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
1962 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
1963 +
1964 +/* bcopy, bcmp, and bzero */
1965 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
1966 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
1967 +#define bzero(b, len) memset((b), '\0', (len))
1968 +
1969 +/* uncached virtual address */
1970 +#ifdef mips
1971 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
1972 +#include <asm/addrspace.h>
1973 +#else
1974 +#define OSL_UNCACHED(va) (va)
1975 +#endif
1976 +
1977 +/* get processor cycle count */
1978 +#if defined(mips)
1979 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
1980 +#elif defined(__i386__)
1981 +#define OSL_GETCYCLES(x) rdtscl((x))
1982 +#else
1983 +#define OSL_GETCYCLES(x) ((x) = 0)
1984 +#endif
1985 +
1986 +/* dereference an address that may cause a bus exception */
1987 +#ifdef mips
1988 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
1989 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
1990 +#else
1991 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
1992 +#include <asm/paccess.h>
1993 +#endif
1994 +#else
1995 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
1996 +#endif
1997 +
1998 +/* map/unmap physical to virtual I/O */
1999 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
2000 +#define REG_UNMAP(va) iounmap((void *)(va))
2001 +
2002 +/* shared (dma-able) memory access macros */
2003 +#define R_SM(r) *(r)
2004 +#define W_SM(r, v) (*(r) = (v))
2005 +#define BZERO_SM(r, len) memset((r), '\0', (len))
2006 +
2007 +/* packet primitives */
2008 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
2009 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
2010 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
2011 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
2012 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
2013 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
2014 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
2015 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
2016 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
2017 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
2018 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
2019 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
2020 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
2021 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
2022 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
2023 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
2024 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
2025 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
2026 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
2027 +extern void osl_pktfree(void *skb);
2028 +
2029 +#else /* BINOSL */
2030 +
2031 +/* string library */
2032 +#ifndef LINUX_OSL
2033 +#undef printf
2034 +#define printf(fmt, args...) osl_printf((fmt), ## args)
2035 +#undef sprintf
2036 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
2037 +#undef strcmp
2038 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
2039 +#undef strncmp
2040 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
2041 +#undef strlen
2042 +#define strlen(s) osl_strlen((s))
2043 +#undef strcpy
2044 +#define strcpy(d, s) osl_strcpy((d), (s))
2045 +#undef strncpy
2046 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
2047 +#endif
2048 +extern int osl_printf(const char *format, ...);
2049 +extern int osl_sprintf(char *buf, const char *format, ...);
2050 +extern int osl_strcmp(const char *s1, const char *s2);
2051 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
2052 +extern int osl_strlen(const char *s);
2053 +extern char* osl_strcpy(char *d, const char *s);
2054 +extern char* osl_strncpy(char *d, const char *s, uint n);
2055 +
2056 +/* register access macros */
2057 +#if !defined(BCMJTAG)
2058 +#define R_REG(r) ( \
2059 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
2060 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
2061 + osl_readl((volatile uint32*)(r)) \
2062 +)
2063 +#define W_REG(r, v) do { \
2064 + switch (sizeof(*(r))) { \
2065 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
2066 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
2067 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
2068 + } \
2069 +} while (0)
2070 +#endif
2071 +
2072 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2073 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2074 +extern uint8 osl_readb(volatile uint8 *r);
2075 +extern uint16 osl_readw(volatile uint16 *r);
2076 +extern uint32 osl_readl(volatile uint32 *r);
2077 +extern void osl_writeb(uint8 v, volatile uint8 *r);
2078 +extern void osl_writew(uint16 v, volatile uint16 *r);
2079 +extern void osl_writel(uint32 v, volatile uint32 *r);
2080 +
2081 +/* bcopy, bcmp, and bzero */
2082 +extern void bcopy(const void *src, void *dst, int len);
2083 +extern int bcmp(const void *b1, const void *b2, int len);
2084 +extern void bzero(void *b, int len);
2085 +
2086 +/* uncached virtual address */
2087 +#define OSL_UNCACHED(va) osl_uncached((va))
2088 +extern void *osl_uncached(void *va);
2089 +
2090 +/* get processor cycle count */
2091 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
2092 +extern uint osl_getcycles(void);
2093 +
2094 +/* dereference an address that may target abort */
2095 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
2096 +extern int osl_busprobe(uint32 *val, uint32 addr);
2097 +
2098 +/* map/unmap physical to virtual */
2099 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
2100 +#define REG_UNMAP(va) osl_reg_unmap((va))
2101 +extern void *osl_reg_map(uint32 pa, uint size);
2102 +extern void osl_reg_unmap(void *va);
2103 +
2104 +/* shared (dma-able) memory access macros */
2105 +#define R_SM(r) *(r)
2106 +#define W_SM(r, v) (*(r) = (v))
2107 +#define BZERO_SM(r, len) bzero((r), (len))
2108 +
2109 +/* packet primitives */
2110 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
2111 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
2112 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
2113 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
2114 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
2115 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
2116 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
2117 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
2118 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
2119 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
2120 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
2121 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
2122 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
2123 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
2124 +#define PKTLINK(skb) osl_pktlink((skb))
2125 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
2126 +#define PKTPRIO(skb) osl_pktprio((skb))
2127 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
2128 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
2129 +extern void osl_pktfree(void *skb);
2130 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
2131 +extern uint osl_pktlen(osl_t *osh, void *skb);
2132 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
2133 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
2134 +extern void *osl_pktnext(osl_t *osh, void *skb);
2135 +extern void osl_pktsetnext(void *skb, void *x);
2136 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
2137 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
2138 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
2139 +extern void *osl_pktdup(osl_t *osh, void *skb);
2140 +extern void *osl_pktcookie(void *skb);
2141 +extern void osl_pktsetcookie(void *skb, void *x);
2142 +extern void *osl_pktlink(void *skb);
2143 +extern void osl_pktsetlink(void *skb, void *x);
2144 +extern uint osl_pktprio(void *skb);
2145 +extern void osl_pktsetprio(void *skb, uint x);
2146 +
2147 +#endif /* BINOSL */
2148 +
2149 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
2150 +extern int osl_error(int bcmerror);
2151 +
2152 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2153 +#define PKTBUFSZ 2048
2154 +
2155 +#endif /* _linux_osl_h_ */
2156 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/linuxver.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/linuxver.h
2157 --- linux-2.4.32/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
2158 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/linuxver.h 2005-12-16 23:39:10.748824500 +0100
2159 @@ -0,0 +1,411 @@
2160 +/*
2161 + * Linux-specific abstractions to gain some independence from linux kernel versions.
2162 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
2163 + *
2164 + * Copyright 2005, Broadcom Corporation
2165 + * All Rights Reserved.
2166 + *
2167 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2168 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2169 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2170 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2171 + *
2172 + * $Id$
2173 + */
2174 +
2175 +#ifndef _linuxver_h_
2176 +#define _linuxver_h_
2177 +
2178 +#include <linux/config.h>
2179 +#include <linux/version.h>
2180 +
2181 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
2182 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
2183 +#ifdef __UNDEF_NO_VERSION__
2184 +#undef __NO_VERSION__
2185 +#else
2186 +#define __NO_VERSION__
2187 +#endif
2188 +#endif
2189 +
2190 +#if defined(MODULE) && defined(MODVERSIONS)
2191 +#include <linux/modversions.h>
2192 +#endif
2193 +
2194 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
2195 +#include <linux/moduleparam.h>
2196 +#endif
2197 +
2198 +
2199 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
2200 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
2201 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
2202 +#endif
2203 +
2204 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
2205 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
2206 +#include <linux/malloc.h>
2207 +#else
2208 +#include <linux/slab.h>
2209 +#endif
2210 +
2211 +#include <linux/types.h>
2212 +#include <linux/init.h>
2213 +#include <linux/mm.h>
2214 +#include <linux/string.h>
2215 +#include <linux/pci.h>
2216 +#include <linux/interrupt.h>
2217 +#include <linux/netdevice.h>
2218 +#include <asm/io.h>
2219 +
2220 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
2221 +#include <linux/workqueue.h>
2222 +#else
2223 +#include <linux/tqueue.h>
2224 +#ifndef work_struct
2225 +#define work_struct tq_struct
2226 +#endif
2227 +#ifndef INIT_WORK
2228 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
2229 +#endif
2230 +#ifndef schedule_work
2231 +#define schedule_work(_work) schedule_task((_work))
2232 +#endif
2233 +#ifndef flush_scheduled_work
2234 +#define flush_scheduled_work() flush_scheduled_tasks()
2235 +#endif
2236 +#endif
2237 +
2238 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
2239 +/* Some distributions have their own 2.6.x compatibility layers */
2240 +#ifndef IRQ_NONE
2241 +typedef void irqreturn_t;
2242 +#define IRQ_NONE
2243 +#define IRQ_HANDLED
2244 +#define IRQ_RETVAL(x)
2245 +#endif
2246 +#else
2247 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
2248 +#endif
2249 +
2250 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2251 +
2252 +#include <pcmcia/version.h>
2253 +#include <pcmcia/cs_types.h>
2254 +#include <pcmcia/cs.h>
2255 +#include <pcmcia/cistpl.h>
2256 +#include <pcmcia/cisreg.h>
2257 +#include <pcmcia/ds.h>
2258 +
2259 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
2260 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
2261 + * does this, but it's not in 2.4 so we do our own for now. */
2262 +static inline void
2263 +cs_error(client_handle_t handle, int func, int ret)
2264 +{
2265 + error_info_t err = { func, ret };
2266 + CardServices(ReportError, handle, &err);
2267 +}
2268 +#endif
2269 +
2270 +#endif /* CONFIG_PCMCIA */
2271 +
2272 +#ifndef __exit
2273 +#define __exit
2274 +#endif
2275 +#ifndef __devexit
2276 +#define __devexit
2277 +#endif
2278 +#ifndef __devinit
2279 +#define __devinit __init
2280 +#endif
2281 +#ifndef __devinitdata
2282 +#define __devinitdata
2283 +#endif
2284 +#ifndef __devexit_p
2285 +#define __devexit_p(x) x
2286 +#endif
2287 +
2288 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
2289 +
2290 +#define pci_get_drvdata(dev) (dev)->sysdata
2291 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
2292 +
2293 +/*
2294 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
2295 + */
2296 +
2297 +struct pci_device_id {
2298 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
2299 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
2300 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
2301 + unsigned long driver_data; /* Data private to the driver */
2302 +};
2303 +
2304 +struct pci_driver {
2305 + struct list_head node;
2306 + char *name;
2307 + const struct pci_device_id *id_table; /* NULL if wants all devices */
2308 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
2309 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
2310 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
2311 + void (*resume)(struct pci_dev *dev); /* Device woken up */
2312 +};
2313 +
2314 +#define MODULE_DEVICE_TABLE(type, name)
2315 +#define PCI_ANY_ID (~0)
2316 +
2317 +/* compatpci.c */
2318 +#define pci_module_init pci_register_driver
2319 +extern int pci_register_driver(struct pci_driver *drv);
2320 +extern void pci_unregister_driver(struct pci_driver *drv);
2321 +
2322 +#endif /* PCI registration */
2323 +
2324 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
2325 +#ifdef MODULE
2326 +#define module_init(x) int init_module(void) { return x(); }
2327 +#define module_exit(x) void cleanup_module(void) { x(); }
2328 +#else
2329 +#define module_init(x) __initcall(x);
2330 +#define module_exit(x) __exitcall(x);
2331 +#endif
2332 +#endif
2333 +
2334 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
2335 +#define list_for_each(pos, head) \
2336 + for (pos = (head)->next; pos != (head); pos = pos->next)
2337 +#endif
2338 +
2339 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
2340 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
2341 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
2342 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
2343 +#endif
2344 +
2345 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
2346 +#define pci_enable_device(dev) do { } while (0)
2347 +#endif
2348 +
2349 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
2350 +#define net_device device
2351 +#endif
2352 +
2353 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
2354 +
2355 +/*
2356 + * DMA mapping
2357 + *
2358 + * See linux/Documentation/DMA-mapping.txt
2359 + */
2360 +
2361 +#ifndef PCI_DMA_TODEVICE
2362 +#define PCI_DMA_TODEVICE 1
2363 +#define PCI_DMA_FROMDEVICE 2
2364 +#endif
2365 +
2366 +typedef u32 dma_addr_t;
2367 +
2368 +/* Pure 2^n version of get_order */
2369 +static inline int get_order(unsigned long size)
2370 +{
2371 + int order;
2372 +
2373 + size = (size-1) >> (PAGE_SHIFT-1);
2374 + order = -1;
2375 + do {
2376 + size >>= 1;
2377 + order++;
2378 + } while (size);
2379 + return order;
2380 +}
2381 +
2382 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
2383 + dma_addr_t *dma_handle)
2384 +{
2385 + void *ret;
2386 + int gfp = GFP_ATOMIC | GFP_DMA;
2387 +
2388 + ret = (void *)__get_free_pages(gfp, get_order(size));
2389 +
2390 + if (ret != NULL) {
2391 + memset(ret, 0, size);
2392 + *dma_handle = virt_to_bus(ret);
2393 + }
2394 + return ret;
2395 +}
2396 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
2397 + void *vaddr, dma_addr_t dma_handle)
2398 +{
2399 + free_pages((unsigned long)vaddr, get_order(size));
2400 +}
2401 +#ifdef ILSIM
2402 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
2403 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
2404 +#else
2405 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
2406 +#define pci_unmap_single(cookie, address, size, dir)
2407 +#endif
2408 +
2409 +#endif /* DMA mapping */
2410 +
2411 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
2412 +
2413 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
2414 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
2415 +
2416 +/* pcmcia-cs provides its own netdevice compatibility layer */
2417 +#ifndef _COMPAT_NETDEVICE_H
2418 +
2419 +/*
2420 + * SoftNet
2421 + *
2422 + * For pre-softnet kernels we need to tell the upper layer not to
2423 + * re-enter start_xmit() while we are in there. However softnet
2424 + * guarantees not to enter while we are in there so there is no need
2425 + * to do the netif_stop_queue() dance unless the transmit queue really
2426 + * gets stuck. This should also improve performance according to tests
2427 + * done by Aman Singla.
2428 + */
2429 +
2430 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
2431 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
2432 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
2433 +
2434 +static inline void netif_start_queue(struct net_device *dev)
2435 +{
2436 + dev->tbusy = 0;
2437 + dev->interrupt = 0;
2438 + dev->start = 1;
2439 +}
2440 +
2441 +#define netif_queue_stopped(dev) (dev)->tbusy
2442 +#define netif_running(dev) (dev)->start
2443 +
2444 +#endif /* _COMPAT_NETDEVICE_H */
2445 +
2446 +#define netif_device_attach(dev) netif_start_queue(dev)
2447 +#define netif_device_detach(dev) netif_stop_queue(dev)
2448 +
2449 +/* 2.4.x renamed bottom halves to tasklets */
2450 +#define tasklet_struct tq_struct
2451 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
2452 +{
2453 + queue_task(tasklet, &tq_immediate);
2454 + mark_bh(IMMEDIATE_BH);
2455 +}
2456 +
2457 +static inline void tasklet_init(struct tasklet_struct *tasklet,
2458 + void (*func)(unsigned long),
2459 + unsigned long data)
2460 +{
2461 + tasklet->next = NULL;
2462 + tasklet->sync = 0;
2463 + tasklet->routine = (void (*)(void *))func;
2464 + tasklet->data = (void *)data;
2465 +}
2466 +#define tasklet_kill(tasklet) {do{} while(0);}
2467 +
2468 +/* 2.4.x introduced del_timer_sync() */
2469 +#define del_timer_sync(timer) del_timer(timer)
2470 +
2471 +#else
2472 +
2473 +#define netif_down(dev)
2474 +
2475 +#endif /* SoftNet */
2476 +
2477 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
2478 +
2479 +/*
2480 + * Emit code to initialise a tq_struct's routine and data pointers
2481 + */
2482 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
2483 + do { \
2484 + (_tq)->routine = _routine; \
2485 + (_tq)->data = _data; \
2486 + } while (0)
2487 +
2488 +/*
2489 + * Emit code to initialise all of a tq_struct
2490 + */
2491 +#define INIT_TQUEUE(_tq, _routine, _data) \
2492 + do { \
2493 + INIT_LIST_HEAD(&(_tq)->list); \
2494 + (_tq)->sync = 0; \
2495 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
2496 + } while (0)
2497 +
2498 +#endif
2499 +
2500 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
2501 +
2502 +/* Power management related routines */
2503 +
2504 +static inline int
2505 +pci_save_state(struct pci_dev *dev, u32 *buffer)
2506 +{
2507 + int i;
2508 + if (buffer) {
2509 + for (i = 0; i < 16; i++)
2510 + pci_read_config_dword(dev, i * 4,&buffer[i]);
2511 + }
2512 + return 0;
2513 +}
2514 +
2515 +static inline int
2516 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
2517 +{
2518 + int i;
2519 +
2520 + if (buffer) {
2521 + for (i = 0; i < 16; i++)
2522 + pci_write_config_dword(dev,i * 4, buffer[i]);
2523 + }
2524 + /*
2525 + * otherwise, write the context information we know from bootup.
2526 + * This works around a problem where warm-booting from Windows
2527 + * combined with a D3(hot)->D0 transition causes PCI config
2528 + * header data to be forgotten.
2529 + */
2530 + else {
2531 + for (i = 0; i < 6; i ++)
2532 + pci_write_config_dword(dev,
2533 + PCI_BASE_ADDRESS_0 + (i * 4),
2534 + pci_resource_start(dev, i));
2535 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
2536 + }
2537 + return 0;
2538 +}
2539 +
2540 +#endif /* PCI power management */
2541 +
2542 +/* Old cp0 access macros deprecated in 2.4.19 */
2543 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
2544 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
2545 +#endif
2546 +
2547 +/* Module refcount handled internally in 2.6.x */
2548 +#ifndef SET_MODULE_OWNER
2549 +#define SET_MODULE_OWNER(dev) do {} while (0)
2550 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
2551 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
2552 +#else
2553 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
2554 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
2555 +#endif
2556 +
2557 +#ifndef SET_NETDEV_DEV
2558 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
2559 +#endif
2560 +
2561 +#ifndef HAVE_FREE_NETDEV
2562 +#define free_netdev(dev) kfree(dev)
2563 +#endif
2564 +
2565 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
2566 +/* struct packet_type redefined in 2.6.x */
2567 +#define af_packet_priv data
2568 +#endif
2569 +
2570 +#endif /* _linuxver_h_ */
2571 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h
2572 --- linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
2573 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h 2005-12-16 23:39:10.748824500 +0100
2574 @@ -0,0 +1,552 @@
2575 +/*
2576 + * HND Run Time Environment for standalone MIPS programs.
2577 + *
2578 + * Copyright 2005, Broadcom Corporation
2579 + * All Rights Reserved.
2580 + *
2581 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2582 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2583 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2584 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2585 + *
2586 + * $Id$
2587 + */
2588 +
2589 +#ifndef _MISPINC_H
2590 +#define _MISPINC_H
2591 +
2592 +
2593 +/* MIPS defines */
2594 +
2595 +#ifdef _LANGUAGE_ASSEMBLY
2596 +
2597 +/*
2598 + * Symbolic register names for 32 bit ABI
2599 + */
2600 +#define zero $0 /* wired zero */
2601 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
2602 +#define v0 $2 /* return value */
2603 +#define v1 $3
2604 +#define a0 $4 /* argument registers */
2605 +#define a1 $5
2606 +#define a2 $6
2607 +#define a3 $7
2608 +#define t0 $8 /* caller saved */
2609 +#define t1 $9
2610 +#define t2 $10
2611 +#define t3 $11
2612 +#define t4 $12
2613 +#define t5 $13
2614 +#define t6 $14
2615 +#define t7 $15
2616 +#define s0 $16 /* callee saved */
2617 +#define s1 $17
2618 +#define s2 $18
2619 +#define s3 $19
2620 +#define s4 $20
2621 +#define s5 $21
2622 +#define s6 $22
2623 +#define s7 $23
2624 +#define t8 $24 /* caller saved */
2625 +#define t9 $25
2626 +#define jp $25 /* PIC jump register */
2627 +#define k0 $26 /* kernel scratch */
2628 +#define k1 $27
2629 +#define gp $28 /* global pointer */
2630 +#define sp $29 /* stack pointer */
2631 +#define fp $30 /* frame pointer */
2632 +#define s8 $30 /* same like fp! */
2633 +#define ra $31 /* return address */
2634 +
2635 +
2636 +/*
2637 + * CP0 Registers
2638 + */
2639 +
2640 +#define C0_INX $0
2641 +#define C0_RAND $1
2642 +#define C0_TLBLO0 $2
2643 +#define C0_TLBLO C0_TLBLO0
2644 +#define C0_TLBLO1 $3
2645 +#define C0_CTEXT $4
2646 +#define C0_PGMASK $5
2647 +#define C0_WIRED $6
2648 +#define C0_BADVADDR $8
2649 +#define C0_COUNT $9
2650 +#define C0_TLBHI $10
2651 +#define C0_COMPARE $11
2652 +#define C0_SR $12
2653 +#define C0_STATUS C0_SR
2654 +#define C0_CAUSE $13
2655 +#define C0_EPC $14
2656 +#define C0_PRID $15
2657 +#define C0_CONFIG $16
2658 +#define C0_LLADDR $17
2659 +#define C0_WATCHLO $18
2660 +#define C0_WATCHHI $19
2661 +#define C0_XCTEXT $20
2662 +#define C0_DIAGNOSTIC $22
2663 +#define C0_BROADCOM C0_DIAGNOSTIC
2664 +#define C0_PERFORMANCE $25
2665 +#define C0_ECC $26
2666 +#define C0_CACHEERR $27
2667 +#define C0_TAGLO $28
2668 +#define C0_TAGHI $29
2669 +#define C0_ERREPC $30
2670 +#define C0_DESAVE $31
2671 +
2672 +/*
2673 + * LEAF - declare leaf routine
2674 + */
2675 +#define LEAF(symbol) \
2676 + .globl symbol; \
2677 + .align 2; \
2678 + .type symbol,@function; \
2679 + .ent symbol,0; \
2680 +symbol: .frame sp,0,ra
2681 +
2682 +/*
2683 + * END - mark end of function
2684 + */
2685 +#define END(function) \
2686 + .end function; \
2687 + .size function,.-function
2688 +
2689 +#define _ULCAST_
2690 +
2691 +#else
2692 +
2693 +/*
2694 + * The following macros are especially useful for __asm__
2695 + * inline assembler.
2696 + */
2697 +#ifndef __STR
2698 +#define __STR(x) #x
2699 +#endif
2700 +#ifndef STR
2701 +#define STR(x) __STR(x)
2702 +#endif
2703 +
2704 +#define _ULCAST_ (unsigned long)
2705 +
2706 +
2707 +/*
2708 + * CP0 Registers
2709 + */
2710 +
2711 +#define C0_INX 0 /* CP0: TLB Index */
2712 +#define C0_RAND 1 /* CP0: TLB Random */
2713 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
2714 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
2715 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
2716 +#define C0_CTEXT 4 /* CP0: Context */
2717 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
2718 +#define C0_WIRED 6 /* CP0: TLB Wired */
2719 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
2720 +#define C0_COUNT 9 /* CP0: Count */
2721 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
2722 +#define C0_COMPARE 11 /* CP0: Compare */
2723 +#define C0_SR 12 /* CP0: Processor Status */
2724 +#define C0_STATUS C0_SR /* CP0: Processor Status */
2725 +#define C0_CAUSE 13 /* CP0: Exception Cause */
2726 +#define C0_EPC 14 /* CP0: Exception PC */
2727 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
2728 +#define C0_CONFIG 16 /* CP0: Config */
2729 +#define C0_LLADDR 17 /* CP0: LLAddr */
2730 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
2731 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
2732 +#define C0_XCTEXT 20 /* CP0: XContext */
2733 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
2734 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
2735 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
2736 +#define C0_ECC 26 /* CP0: ECC */
2737 +#define C0_CACHEERR 27 /* CP0: CacheErr */
2738 +#define C0_TAGLO 28 /* CP0: TagLo */
2739 +#define C0_TAGHI 29 /* CP0: TagHi */
2740 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
2741 +#define C0_DESAVE 31 /* CP0: DebugSave */
2742 +
2743 +#endif /* _LANGUAGE_ASSEMBLY */
2744 +
2745 +/*
2746 + * Memory segments (32bit kernel mode addresses)
2747 + */
2748 +#undef KUSEG
2749 +#undef KSEG0
2750 +#undef KSEG1
2751 +#undef KSEG2
2752 +#undef KSEG3
2753 +#define KUSEG 0x00000000
2754 +#define KSEG0 0x80000000
2755 +#define KSEG1 0xa0000000
2756 +#define KSEG2 0xc0000000
2757 +#define KSEG3 0xe0000000
2758 +#define PHYSADDR_MASK 0x1fffffff
2759 +
2760 +/*
2761 + * Map an address to a certain kernel segment
2762 + */
2763 +#undef PHYSADDR
2764 +#undef KSEG0ADDR
2765 +#undef KSEG1ADDR
2766 +#undef KSEG2ADDR
2767 +#undef KSEG3ADDR
2768 +
2769 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
2770 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
2771 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
2772 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
2773 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
2774 +
2775 +
2776 +#ifndef Index_Invalidate_I
2777 +/*
2778 + * Cache Operations
2779 + */
2780 +#define Index_Invalidate_I 0x00
2781 +#define Index_Writeback_Inv_D 0x01
2782 +#define Index_Invalidate_SI 0x02
2783 +#define Index_Writeback_Inv_SD 0x03
2784 +#define Index_Load_Tag_I 0x04
2785 +#define Index_Load_Tag_D 0x05
2786 +#define Index_Load_Tag_SI 0x06
2787 +#define Index_Load_Tag_SD 0x07
2788 +#define Index_Store_Tag_I 0x08
2789 +#define Index_Store_Tag_D 0x09
2790 +#define Index_Store_Tag_SI 0x0A
2791 +#define Index_Store_Tag_SD 0x0B
2792 +#define Create_Dirty_Excl_D 0x0d
2793 +#define Create_Dirty_Excl_SD 0x0f
2794 +#define Hit_Invalidate_I 0x10
2795 +#define Hit_Invalidate_D 0x11
2796 +#define Hit_Invalidate_SI 0x12
2797 +#define Hit_Invalidate_SD 0x13
2798 +#define Fill_I 0x14
2799 +#define Hit_Writeback_Inv_D 0x15
2800 + /* 0x16 is unused */
2801 +#define Hit_Writeback_Inv_SD 0x17
2802 +#define R5K_Page_Invalidate_S 0x17
2803 +#define Hit_Writeback_I 0x18
2804 +#define Hit_Writeback_D 0x19
2805 + /* 0x1a is unused */
2806 +#define Hit_Writeback_SD 0x1b
2807 + /* 0x1c is unused */
2808 + /* 0x1e is unused */
2809 +#define Hit_Set_Virtual_SI 0x1e
2810 +#define Hit_Set_Virtual_SD 0x1f
2811 +#endif
2812 +
2813 +
2814 +/*
2815 + * R4x00 interrupt enable / cause bits
2816 + */
2817 +#define IE_SW0 (_ULCAST_(1) << 8)
2818 +#define IE_SW1 (_ULCAST_(1) << 9)
2819 +#define IE_IRQ0 (_ULCAST_(1) << 10)
2820 +#define IE_IRQ1 (_ULCAST_(1) << 11)
2821 +#define IE_IRQ2 (_ULCAST_(1) << 12)
2822 +#define IE_IRQ3 (_ULCAST_(1) << 13)
2823 +#define IE_IRQ4 (_ULCAST_(1) << 14)
2824 +#define IE_IRQ5 (_ULCAST_(1) << 15)
2825 +
2826 +#ifndef ST0_UM
2827 +/*
2828 + * Bitfields in the mips32 cp0 status register
2829 + */
2830 +#define ST0_IE 0x00000001
2831 +#define ST0_EXL 0x00000002
2832 +#define ST0_ERL 0x00000004
2833 +#define ST0_UM 0x00000010
2834 +#define ST0_SWINT0 0x00000100
2835 +#define ST0_SWINT1 0x00000200
2836 +#define ST0_HWINT0 0x00000400
2837 +#define ST0_HWINT1 0x00000800
2838 +#define ST0_HWINT2 0x00001000
2839 +#define ST0_HWINT3 0x00002000
2840 +#define ST0_HWINT4 0x00004000
2841 +#define ST0_HWINT5 0x00008000
2842 +#define ST0_IM 0x0000ff00
2843 +#define ST0_NMI 0x00080000
2844 +#define ST0_SR 0x00100000
2845 +#define ST0_TS 0x00200000
2846 +#define ST0_BEV 0x00400000
2847 +#define ST0_RE 0x02000000
2848 +#define ST0_RP 0x08000000
2849 +#define ST0_CU 0xf0000000
2850 +#define ST0_CU0 0x10000000
2851 +#define ST0_CU1 0x20000000
2852 +#define ST0_CU2 0x40000000
2853 +#define ST0_CU3 0x80000000
2854 +#endif
2855 +
2856 +
2857 +/*
2858 + * Bitfields in the mips32 cp0 cause register
2859 + */
2860 +#define C_EXC 0x0000007c
2861 +#define C_EXC_SHIFT 2
2862 +#define C_INT 0x0000ff00
2863 +#define C_INT_SHIFT 8
2864 +#define C_SW0 (_ULCAST_(1) << 8)
2865 +#define C_SW1 (_ULCAST_(1) << 9)
2866 +#define C_IRQ0 (_ULCAST_(1) << 10)
2867 +#define C_IRQ1 (_ULCAST_(1) << 11)
2868 +#define C_IRQ2 (_ULCAST_(1) << 12)
2869 +#define C_IRQ3 (_ULCAST_(1) << 13)
2870 +#define C_IRQ4 (_ULCAST_(1) << 14)
2871 +#define C_IRQ5 (_ULCAST_(1) << 15)
2872 +#define C_WP 0x00400000
2873 +#define C_IV 0x00800000
2874 +#define C_CE 0x30000000
2875 +#define C_CE_SHIFT 28
2876 +#define C_BD 0x80000000
2877 +
2878 +/* Values in C_EXC */
2879 +#define EXC_INT 0
2880 +#define EXC_TLBM 1
2881 +#define EXC_TLBL 2
2882 +#define EXC_TLBS 3
2883 +#define EXC_AEL 4
2884 +#define EXC_AES 5
2885 +#define EXC_IBE 6
2886 +#define EXC_DBE 7
2887 +#define EXC_SYS 8
2888 +#define EXC_BPT 9
2889 +#define EXC_RI 10
2890 +#define EXC_CU 11
2891 +#define EXC_OV 12
2892 +#define EXC_TR 13
2893 +#define EXC_WATCH 23
2894 +#define EXC_MCHK 24
2895 +
2896 +
2897 +/*
2898 + * Bits in the cp0 config register.
2899 + */
2900 +#define CONF_CM_CACHABLE_NO_WA 0
2901 +#define CONF_CM_CACHABLE_WA 1
2902 +#define CONF_CM_UNCACHED 2
2903 +#define CONF_CM_CACHABLE_NONCOHERENT 3
2904 +#define CONF_CM_CACHABLE_CE 4
2905 +#define CONF_CM_CACHABLE_COW 5
2906 +#define CONF_CM_CACHABLE_CUW 6
2907 +#define CONF_CM_CACHABLE_ACCELERATED 7
2908 +#define CONF_CM_CMASK 7
2909 +#define CONF_CU (_ULCAST_(1) << 3)
2910 +#define CONF_DB (_ULCAST_(1) << 4)
2911 +#define CONF_IB (_ULCAST_(1) << 5)
2912 +#define CONF_SE (_ULCAST_(1) << 12)
2913 +#define CONF_SC (_ULCAST_(1) << 17)
2914 +#define CONF_AC (_ULCAST_(1) << 23)
2915 +#define CONF_HALT (_ULCAST_(1) << 25)
2916 +
2917 +
2918 +/*
2919 + * Bits in the cp0 config register select 1.
2920 + */
2921 +#define CONF1_FP 0x00000001 /* FPU present */
2922 +#define CONF1_EP 0x00000002 /* EJTAG present */
2923 +#define CONF1_CA 0x00000004 /* mips16 implemented */
2924 +#define CONF1_WR 0x00000008 /* Watch registers present */
2925 +#define CONF1_PC 0x00000010 /* Performance counters present */
2926 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
2927 +#define CONF1_DA_MASK 0x00000380
2928 +#define CONF1_DA_BASE 1
2929 +#define CONF1_DL_SHIFT 10 /* D$ line size */
2930 +#define CONF1_DL_MASK 0x00001c00
2931 +#define CONF1_DL_BASE 2
2932 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
2933 +#define CONF1_DS_MASK 0x0000e000
2934 +#define CONF1_DS_BASE 64
2935 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
2936 +#define CONF1_IA_MASK 0x00070000
2937 +#define CONF1_IA_BASE 1
2938 +#define CONF1_IL_SHIFT 19 /* I$ line size */
2939 +#define CONF1_IL_MASK 0x00380000
2940 +#define CONF1_IL_BASE 2
2941 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
2942 +#define CONF1_IS_MASK 0x01c00000
2943 +#define CONF1_IS_BASE 64
2944 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
2945 +#define CONF1_MS_SHIFT 25
2946 +
2947 +/* PRID register */
2948 +#define PRID_COPT_MASK 0xff000000
2949 +#define PRID_COMP_MASK 0x00ff0000
2950 +#define PRID_IMP_MASK 0x0000ff00
2951 +#define PRID_REV_MASK 0x000000ff
2952 +
2953 +#define PRID_COMP_LEGACY 0x000000
2954 +#define PRID_COMP_MIPS 0x010000
2955 +#define PRID_COMP_BROADCOM 0x020000
2956 +#define PRID_COMP_ALCHEMY 0x030000
2957 +#define PRID_COMP_SIBYTE 0x040000
2958 +#define PRID_IMP_BCM4710 0x4000
2959 +#define PRID_IMP_BCM3302 0x9000
2960 +#define PRID_IMP_BCM3303 0x9100
2961 +
2962 +#define PRID_IMP_UNKNOWN 0xff00
2963 +
2964 +#define BCM330X(id) \
2965 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
2966 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
2967 +
2968 +/* Bits in C0_BROADCOM */
2969 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
2970 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
2971 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
2972 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
2973 +
2974 +/* PreFetch Cache aka Read Ahead Cache */
2975 +
2976 +#define PFC_CR0 0xff400000 /* control reg 0 */
2977 +#define PFC_CR1 0xff400004 /* control reg 1 */
2978 +
2979 +/* PFC operations */
2980 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
2981 +#define PFC_D 0x00000002 /* Enable PFC use for data */
2982 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
2983 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
2984 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
2985 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
2986 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
2987 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
2988 +#define PFC_BRR 0x40000000 /* Bus error indication */
2989 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
2990 +
2991 +/* Handy defaults */
2992 +#define PFC_DISABLED 0
2993 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
2994 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
2995 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
2996 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
2997 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
2998 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
2999 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
3000 +
3001 +
3002 +/*
3003 + * These are the UART port assignments, expressed as offsets from the base
3004 + * register. These assignments should hold for any serial port based on
3005 + * a 8250, 16450, or 16550(A).
3006 + */
3007 +
3008 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
3009 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
3010 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
3011 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
3012 +#define UART_LCR 3 /* Out: Line Control Register */
3013 +#define UART_MCR 4 /* Out: Modem Control Register */
3014 +#define UART_LSR 5 /* In: Line Status Register */
3015 +#define UART_MSR 6 /* In: Modem Status Register */
3016 +#define UART_SCR 7 /* I/O: Scratch Register */
3017 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
3018 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
3019 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
3020 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
3021 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
3022 +
3023 +
3024 +#ifndef _LANGUAGE_ASSEMBLY
3025 +
3026 +/*
3027 + * Macros to access the system control coprocessor
3028 + */
3029 +
3030 +#define MFC0(source, sel) \
3031 +({ \
3032 + int __res; \
3033 + __asm__ __volatile__( \
3034 + ".set\tnoreorder\n\t" \
3035 + ".set\tnoat\n\t" \
3036 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
3037 + "move\t%0,$1\n\t" \
3038 + ".set\tat\n\t" \
3039 + ".set\treorder" \
3040 + :"=r" (__res) \
3041 + : \
3042 + :"$1"); \
3043 + __res; \
3044 +})
3045 +
3046 +#define MTC0(source, sel, value) \
3047 +do { \
3048 + __asm__ __volatile__( \
3049 + ".set\tnoreorder\n\t" \
3050 + ".set\tnoat\n\t" \
3051 + "move\t$1,%z0\n\t" \
3052 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
3053 + ".set\tat\n\t" \
3054 + ".set\treorder" \
3055 + : \
3056 + :"jr" (value) \
3057 + :"$1"); \
3058 +} while (0)
3059 +
3060 +#define get_c0_count() \
3061 +({ \
3062 + int __res; \
3063 + __asm__ __volatile__( \
3064 + ".set\tnoreorder\n\t" \
3065 + ".set\tnoat\n\t" \
3066 + "mfc0\t%0,$9\n\t" \
3067 + ".set\tat\n\t" \
3068 + ".set\treorder" \
3069 + :"=r" (__res)); \
3070 + __res; \
3071 +})
3072 +
3073 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
3074 +{
3075 + uint lsz, sets, ways;
3076 +
3077 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
3078 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
3079 + lsz = CONF1_IL_BASE << lsz;
3080 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
3081 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
3082 + *size = lsz * sets * ways;
3083 + *lsize = lsz;
3084 +}
3085 +
3086 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
3087 +{
3088 + uint lsz, sets, ways;
3089 +
3090 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
3091 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
3092 + lsz = CONF1_DL_BASE << lsz;
3093 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
3094 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
3095 + *size = lsz * sets * ways;
3096 + *lsize = lsz;
3097 +}
3098 +
3099 +#define cache_op(base, op) \
3100 + __asm__ __volatile__(" \
3101 + .set noreorder; \
3102 + .set mips3; \
3103 + cache %1, (%0); \
3104 + .set mips0; \
3105 + .set reorder" \
3106 + : \
3107 + : "r" (base), \
3108 + "i" (op));
3109 +
3110 +#define cache_unroll4(base, delta, op) \
3111 + __asm__ __volatile__(" \
3112 + .set noreorder; \
3113 + .set mips3; \
3114 + cache %1,0(%0); \
3115 + cache %1,delta(%0); \
3116 + cache %1,(2 * delta)(%0); \
3117 + cache %1,(3 * delta)(%0); \
3118 + .set mips0; \
3119 + .set reorder" \
3120 + : \
3121 + : "r" (base), \
3122 + "i" (op));
3123 +
3124 +#endif /* !_LANGUAGE_ASSEMBLY */
3125 +
3126 +#endif /* _MISPINC_H */
3127 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/osl.h
3128 --- linux-2.4.32/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
3129 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/osl.h 2005-12-16 23:39:10.748824500 +0100
3130 @@ -0,0 +1,42 @@
3131 +/*
3132 + * OS Abstraction Layer
3133 + *
3134 + * Copyright 2005, Broadcom Corporation
3135 + * All Rights Reserved.
3136 + *
3137 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3138 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3139 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3140 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3141 + * $Id$
3142 + */
3143 +
3144 +#ifndef _osl_h_
3145 +#define _osl_h_
3146 +
3147 +/* osl handle type forward declaration */
3148 +typedef struct os_handle osl_t;
3149 +
3150 +#if defined(linux)
3151 +#include <linux_osl.h>
3152 +#elif defined(NDIS)
3153 +#include <ndis_osl.h>
3154 +#elif defined(_CFE_)
3155 +#include <cfe_osl.h>
3156 +#elif defined(_HNDRTE_)
3157 +#include <hndrte_osl.h>
3158 +#elif defined(_MINOSL_)
3159 +#include <min_osl.h>
3160 +#elif PMON
3161 +#include <pmon_osl.h>
3162 +#elif defined(MACOSX)
3163 +#include <macosx_osl.h>
3164 +#else
3165 +#error "Unsupported OSL requested"
3166 +#endif
3167 +
3168 +/* handy */
3169 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
3170 +#define MAXPRIO 7 /* 0-7 */
3171 +
3172 +#endif /* _osl_h_ */
3173 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/pcicfg.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/pcicfg.h
3174 --- linux-2.4.32/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
3175 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/pcicfg.h 2005-12-16 23:39:10.752824750 +0100
3176 @@ -0,0 +1,451 @@
3177 +/*
3178 + * pcicfg.h: PCI configuration constants and structures.
3179 + *
3180 + * Copyright 2005, Broadcom Corporation
3181 + * All Rights Reserved.
3182 + *
3183 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3184 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3185 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3186 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3187 + *
3188 + * $Id$
3189 + */
3190 +
3191 +#ifndef _h_pci_
3192 +#define _h_pci_
3193 +
3194 +/* The following inside ifndef's so we don't collide with NTDDK.H */
3195 +#ifndef PCI_MAX_BUS
3196 +#define PCI_MAX_BUS 0x100
3197 +#endif
3198 +#ifndef PCI_MAX_DEVICES
3199 +#define PCI_MAX_DEVICES 0x20
3200 +#endif
3201 +#ifndef PCI_MAX_FUNCTION
3202 +#define PCI_MAX_FUNCTION 0x8
3203 +#endif
3204 +
3205 +#ifndef PCI_INVALID_VENDORID
3206 +#define PCI_INVALID_VENDORID 0xffff
3207 +#endif
3208 +#ifndef PCI_INVALID_DEVICEID
3209 +#define PCI_INVALID_DEVICEID 0xffff
3210 +#endif
3211 +
3212 +
3213 +/* Convert between bus-slot-function-register and config addresses */
3214 +
3215 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
3216 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
3217 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
3218 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
3219 +
3220 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
3221 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
3222 +#define PCICFG_FUN_MASK 7 /* Function mask */
3223 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
3224 +
3225 +#define PCI_CONFIG_ADDR(b, s, f, o) \
3226 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
3227 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
3228 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
3229 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
3230 +
3231 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
3232 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
3233 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
3234 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
3235 +
3236 +/* PCIE Config space accessing MACROS*/
3237 +
3238 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
3239 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
3240 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
3241 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
3242 +
3243 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
3244 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
3245 +#define PCIECFG_FUN_MASK 7 /* Function mask */
3246 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
3247 +
3248 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
3249 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
3250 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
3251 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
3252 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
3253 +
3254 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
3255 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
3256 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
3257 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
3258 +
3259 +
3260 +/* The actual config space */
3261 +
3262 +#define PCI_BAR_MAX 6
3263 +
3264 +#define PCI_ROM_BAR 8
3265 +
3266 +#define PCR_RSVDA_MAX 2
3267 +
3268 +/* pci config status reg has a bit to indicate that capability ptr is present*/
3269 +
3270 +#define PCI_CAPPTR_PRESENT 0x0010
3271 +
3272 +typedef struct _pci_config_regs {
3273 + unsigned short vendor;
3274 + unsigned short device;
3275 + unsigned short command;
3276 + unsigned short status;
3277 + unsigned char rev_id;
3278 + unsigned char prog_if;
3279 + unsigned char sub_class;
3280 + unsigned char base_class;
3281 + unsigned char cache_line_size;
3282 + unsigned char latency_timer;
3283 + unsigned char header_type;
3284 + unsigned char bist;
3285 + unsigned long base[PCI_BAR_MAX];
3286 + unsigned long cardbus_cis;
3287 + unsigned short subsys_vendor;
3288 + unsigned short subsys_id;
3289 + unsigned long baserom;
3290 + unsigned long rsvd_a[PCR_RSVDA_MAX];
3291 + unsigned char int_line;
3292 + unsigned char int_pin;
3293 + unsigned char min_gnt;
3294 + unsigned char max_lat;
3295 + unsigned char dev_dep[192];
3296 +} pci_config_regs;
3297 +
3298 +#define SZPCR (sizeof (pci_config_regs))
3299 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
3300 +
3301 +/* A structure for the config registers is nice, but in most
3302 + * systems the config space is not memory mapped, so we need
3303 + * filed offsetts. :-(
3304 + */
3305 +#define PCI_CFG_VID 0
3306 +#define PCI_CFG_DID 2
3307 +#define PCI_CFG_CMD 4
3308 +#define PCI_CFG_STAT 6
3309 +#define PCI_CFG_REV 8
3310 +#define PCI_CFG_PROGIF 9
3311 +#define PCI_CFG_SUBCL 0xa
3312 +#define PCI_CFG_BASECL 0xb
3313 +#define PCI_CFG_CLSZ 0xc
3314 +#define PCI_CFG_LATTIM 0xd
3315 +#define PCI_CFG_HDR 0xe
3316 +#define PCI_CFG_BIST 0xf
3317 +#define PCI_CFG_BAR0 0x10
3318 +#define PCI_CFG_BAR1 0x14
3319 +#define PCI_CFG_BAR2 0x18
3320 +#define PCI_CFG_BAR3 0x1c
3321 +#define PCI_CFG_BAR4 0x20
3322 +#define PCI_CFG_BAR5 0x24
3323 +#define PCI_CFG_CIS 0x28
3324 +#define PCI_CFG_SVID 0x2c
3325 +#define PCI_CFG_SSID 0x2e
3326 +#define PCI_CFG_ROMBAR 0x30
3327 +#define PCI_CFG_CAPPTR 0x34
3328 +#define PCI_CFG_INT 0x3c
3329 +#define PCI_CFG_PIN 0x3d
3330 +#define PCI_CFG_MINGNT 0x3e
3331 +#define PCI_CFG_MAXLAT 0x3f
3332 +
3333 +/* Classes and subclasses */
3334 +
3335 +typedef enum {
3336 + PCI_CLASS_OLD = 0,
3337 + PCI_CLASS_DASDI,
3338 + PCI_CLASS_NET,
3339 + PCI_CLASS_DISPLAY,
3340 + PCI_CLASS_MMEDIA,
3341 + PCI_CLASS_MEMORY,
3342 + PCI_CLASS_BRIDGE,
3343 + PCI_CLASS_COMM,
3344 + PCI_CLASS_BASE,
3345 + PCI_CLASS_INPUT,
3346 + PCI_CLASS_DOCK,
3347 + PCI_CLASS_CPU,
3348 + PCI_CLASS_SERIAL,
3349 + PCI_CLASS_INTELLIGENT = 0xe,
3350 + PCI_CLASS_SATELLITE,
3351 + PCI_CLASS_CRYPT,
3352 + PCI_CLASS_DSP,
3353 + PCI_CLASS_MAX
3354 +} pci_classes;
3355 +
3356 +typedef enum {
3357 + PCI_DASDI_SCSI,
3358 + PCI_DASDI_IDE,
3359 + PCI_DASDI_FLOPPY,
3360 + PCI_DASDI_IPI,
3361 + PCI_DASDI_RAID,
3362 + PCI_DASDI_OTHER = 0x80
3363 +} pci_dasdi_subclasses;
3364 +
3365 +typedef enum {
3366 + PCI_NET_ETHER,
3367 + PCI_NET_TOKEN,
3368 + PCI_NET_FDDI,
3369 + PCI_NET_ATM,
3370 + PCI_NET_OTHER = 0x80
3371 +} pci_net_subclasses;
3372 +
3373 +typedef enum {
3374 + PCI_DISPLAY_VGA,
3375 + PCI_DISPLAY_XGA,
3376 + PCI_DISPLAY_3D,
3377 + PCI_DISPLAY_OTHER = 0x80
3378 +} pci_display_subclasses;
3379 +
3380 +typedef enum {
3381 + PCI_MMEDIA_VIDEO,
3382 + PCI_MMEDIA_AUDIO,
3383 + PCI_MMEDIA_PHONE,
3384 + PCI_MEDIA_OTHER = 0x80
3385 +} pci_mmedia_subclasses;
3386 +
3387 +typedef enum {
3388 + PCI_MEMORY_RAM,
3389 + PCI_MEMORY_FLASH,
3390 + PCI_MEMORY_OTHER = 0x80
3391 +} pci_memory_subclasses;
3392 +
3393 +typedef enum {
3394 + PCI_BRIDGE_HOST,
3395 + PCI_BRIDGE_ISA,
3396 + PCI_BRIDGE_EISA,
3397 + PCI_BRIDGE_MC,
3398 + PCI_BRIDGE_PCI,
3399 + PCI_BRIDGE_PCMCIA,
3400 + PCI_BRIDGE_NUBUS,
3401 + PCI_BRIDGE_CARDBUS,
3402 + PCI_BRIDGE_RACEWAY,
3403 + PCI_BRIDGE_OTHER = 0x80
3404 +} pci_bridge_subclasses;
3405 +
3406 +typedef enum {
3407 + PCI_COMM_UART,
3408 + PCI_COMM_PARALLEL,
3409 + PCI_COMM_MULTIUART,
3410 + PCI_COMM_MODEM,
3411 + PCI_COMM_OTHER = 0x80
3412 +} pci_comm_subclasses;
3413 +
3414 +typedef enum {
3415 + PCI_BASE_PIC,
3416 + PCI_BASE_DMA,
3417 + PCI_BASE_TIMER,
3418 + PCI_BASE_RTC,
3419 + PCI_BASE_PCI_HOTPLUG,
3420 + PCI_BASE_OTHER = 0x80
3421 +} pci_base_subclasses;
3422 +
3423 +typedef enum {
3424 + PCI_INPUT_KBD,
3425 + PCI_INPUT_PEN,
3426 + PCI_INPUT_MOUSE,
3427 + PCI_INPUT_SCANNER,
3428 + PCI_INPUT_GAMEPORT,
3429 + PCI_INPUT_OTHER = 0x80
3430 +} pci_input_subclasses;
3431 +
3432 +typedef enum {
3433 + PCI_DOCK_GENERIC,
3434 + PCI_DOCK_OTHER = 0x80
3435 +} pci_dock_subclasses;
3436 +
3437 +typedef enum {
3438 + PCI_CPU_386,
3439 + PCI_CPU_486,
3440 + PCI_CPU_PENTIUM,
3441 + PCI_CPU_ALPHA = 0x10,
3442 + PCI_CPU_POWERPC = 0x20,
3443 + PCI_CPU_MIPS = 0x30,
3444 + PCI_CPU_COPROC = 0x40,
3445 + PCI_CPU_OTHER = 0x80
3446 +} pci_cpu_subclasses;
3447 +
3448 +typedef enum {
3449 + PCI_SERIAL_IEEE1394,
3450 + PCI_SERIAL_ACCESS,
3451 + PCI_SERIAL_SSA,
3452 + PCI_SERIAL_USB,
3453 + PCI_SERIAL_FIBER,
3454 + PCI_SERIAL_SMBUS,
3455 + PCI_SERIAL_OTHER = 0x80
3456 +} pci_serial_subclasses;
3457 +
3458 +typedef enum {
3459 + PCI_INTELLIGENT_I2O,
3460 +} pci_intelligent_subclasses;
3461 +
3462 +typedef enum {
3463 + PCI_SATELLITE_TV,
3464 + PCI_SATELLITE_AUDIO,
3465 + PCI_SATELLITE_VOICE,
3466 + PCI_SATELLITE_DATA,
3467 + PCI_SATELLITE_OTHER = 0x80
3468 +} pci_satellite_subclasses;
3469 +
3470 +typedef enum {
3471 + PCI_CRYPT_NETWORK,
3472 + PCI_CRYPT_ENTERTAINMENT,
3473 + PCI_CRYPT_OTHER = 0x80
3474 +} pci_crypt_subclasses;
3475 +
3476 +typedef enum {
3477 + PCI_DSP_DPIO,
3478 + PCI_DSP_OTHER = 0x80
3479 +} pci_dsp_subclasses;
3480 +
3481 +/* Header types */
3482 +typedef enum {
3483 + PCI_HEADER_NORMAL,
3484 + PCI_HEADER_BRIDGE,
3485 + PCI_HEADER_CARDBUS
3486 +} pci_header_types;
3487 +
3488 +
3489 +/* Overlay for a PCI-to-PCI bridge */
3490 +
3491 +#define PPB_RSVDA_MAX 2
3492 +#define PPB_RSVDD_MAX 8
3493 +
3494 +typedef struct _ppb_config_regs {
3495 + unsigned short vendor;
3496 + unsigned short device;
3497 + unsigned short command;
3498 + unsigned short status;
3499 + unsigned char rev_id;
3500 + unsigned char prog_if;
3501 + unsigned char sub_class;
3502 + unsigned char base_class;
3503 + unsigned char cache_line_size;
3504 + unsigned char latency_timer;
3505 + unsigned char header_type;
3506 + unsigned char bist;
3507 + unsigned long rsvd_a[PPB_RSVDA_MAX];
3508 + unsigned char prim_bus;
3509 + unsigned char sec_bus;
3510 + unsigned char sub_bus;
3511 + unsigned char sec_lat;
3512 + unsigned char io_base;
3513 + unsigned char io_lim;
3514 + unsigned short sec_status;
3515 + unsigned short mem_base;
3516 + unsigned short mem_lim;
3517 + unsigned short pf_mem_base;
3518 + unsigned short pf_mem_lim;
3519 + unsigned long pf_mem_base_hi;
3520 + unsigned long pf_mem_lim_hi;
3521 + unsigned short io_base_hi;
3522 + unsigned short io_lim_hi;
3523 + unsigned short subsys_vendor;
3524 + unsigned short subsys_id;
3525 + unsigned long rsvd_b;
3526 + unsigned char rsvd_c;
3527 + unsigned char int_pin;
3528 + unsigned short bridge_ctrl;
3529 + unsigned char chip_ctrl;
3530 + unsigned char diag_ctrl;
3531 + unsigned short arb_ctrl;
3532 + unsigned long rsvd_d[PPB_RSVDD_MAX];
3533 + unsigned char dev_dep[192];
3534 +} ppb_config_regs;
3535 +
3536 +
3537 +/* PCI CAPABILITY DEFINES */
3538 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
3539 +#define PCI_CAP_MSICAP_ID 0x05
3540 +#define PCI_CAP_PCIECAP_ID 0x10
3541 +
3542 +/* Data structure to define the Message Signalled Interrupt facility
3543 + * Valid for PCI and PCIE configurations */
3544 +typedef struct _pciconfig_cap_msi {
3545 + unsigned char capID;
3546 + unsigned char nextptr;
3547 + unsigned short msgctrl;
3548 + unsigned int msgaddr;
3549 +} pciconfig_cap_msi;
3550 +
3551 +/* Data structure to define the Power managment facility
3552 + * Valid for PCI and PCIE configurations */
3553 +typedef struct _pciconfig_cap_pwrmgmt {
3554 + unsigned char capID;
3555 + unsigned char nextptr;
3556 + unsigned short pme_cap;
3557 + unsigned short pme_sts_ctrl;
3558 + unsigned char pme_bridge_ext;
3559 + unsigned char data;
3560 +} pciconfig_cap_pwrmgmt;
3561 +
3562 +/* Data structure to define the PCIE capability */
3563 +typedef struct _pciconfig_cap_pcie {
3564 + unsigned char capID;
3565 + unsigned char nextptr;
3566 + unsigned short pcie_cap;
3567 + unsigned int dev_cap;
3568 + unsigned short dev_ctrl;
3569 + unsigned short dev_status;
3570 + unsigned int link_cap;
3571 + unsigned short link_ctrl;
3572 + unsigned short link_status;
3573 +} pciconfig_cap_pcie;
3574 +
3575 +/* PCIE Enhanced CAPABILITY DEFINES */
3576 +#define PCIE_EXTCFG_OFFSET 0x100
3577 +#define PCIE_ADVERRREP_CAPID 0x0001
3578 +#define PCIE_VC_CAPID 0x0002
3579 +#define PCIE_DEVSNUM_CAPID 0x0003
3580 +#define PCIE_PWRBUDGET_CAPID 0x0004
3581 +
3582 +/* Header to define the PCIE specific capabilities in the extended config space */
3583 +typedef struct _pcie_enhanced_caphdr {
3584 + unsigned short capID;
3585 + unsigned short cap_ver : 4;
3586 + unsigned short next_ptr : 12;
3587 +} pcie_enhanced_caphdr;
3588 +
3589 +
3590 +/* Everything below is BRCM HND proprietary */
3591 +
3592 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
3593 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
3594 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
3595 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
3596 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
3597 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
3598 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
3599 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
3600 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
3601 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
3602 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
3603 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
3604 +
3605 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
3606 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
3607 +
3608 +/* PCI_INT_STATUS */
3609 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
3610 +
3611 +/* PCI_INT_MASK */
3612 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
3613 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
3614 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
3615 +
3616 +/* PCI_SPROM_CONTROL */
3617 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
3618 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
3619 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
3620 +
3621 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
3622 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
3623 +
3624 +/* PCI_CFG_CMD_STAT */
3625 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
3626 +
3627 +#endif
3628 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbchipc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbchipc.h
3629 --- linux-2.4.32/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
3630 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbchipc.h 2005-12-16 23:39:10.932836000 +0100
3631 @@ -0,0 +1,440 @@
3632 +/*
3633 + * SiliconBackplane Chipcommon core hardware definitions.
3634 + *
3635 + * The chipcommon core provides chip identification, SB control,
3636 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
3637 + * gpio interface, extbus, and support for serial and parallel flashes.
3638 + *
3639 + * $Id$
3640 + * Copyright 2005, Broadcom Corporation
3641 + * All Rights Reserved.
3642 + *
3643 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3644 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3645 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3646 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3647 + *
3648 + */
3649 +
3650 +#ifndef _SBCHIPC_H
3651 +#define _SBCHIPC_H
3652 +
3653 +
3654 +#ifndef _LANGUAGE_ASSEMBLY
3655 +
3656 +/* cpp contortions to concatenate w/arg prescan */
3657 +#ifndef PAD
3658 +#define _PADLINE(line) pad ## line
3659 +#define _XSTR(line) _PADLINE(line)
3660 +#define PAD _XSTR(__LINE__)
3661 +#endif /* PAD */
3662 +
3663 +typedef volatile struct {
3664 + uint32 chipid; /* 0x0 */
3665 + uint32 capabilities;
3666 + uint32 corecontrol; /* corerev >= 1 */
3667 + uint32 bist;
3668 +
3669 + /* OTP */
3670 + uint32 otpstatus; /* 0x10, corerev >= 10 */
3671 + uint32 otpcontrol;
3672 + uint32 otpprog;
3673 + uint32 PAD;
3674 +
3675 + /* Interrupt control */
3676 + uint32 intstatus; /* 0x20 */
3677 + uint32 intmask;
3678 + uint32 chipcontrol; /* 0x28, rev >= 11 */
3679 + uint32 chipstatus; /* 0x2c, rev >= 11 */
3680 +
3681 + /* Jtag Master */
3682 + uint32 jtagcmd; /* 0x30, rev >= 10 */
3683 + uint32 jtagir;
3684 + uint32 jtagdr;
3685 + uint32 jtagctrl;
3686 +
3687 + /* serial flash interface registers */
3688 + uint32 flashcontrol; /* 0x40 */
3689 + uint32 flashaddress;
3690 + uint32 flashdata;
3691 + uint32 PAD[1];
3692 +
3693 + /* Silicon backplane configuration broadcast control */
3694 + uint32 broadcastaddress; /* 0x50 */
3695 + uint32 broadcastdata;
3696 + uint32 PAD[2];
3697 +
3698 + /* gpio - cleared only by power-on-reset */
3699 + uint32 gpioin; /* 0x60 */
3700 + uint32 gpioout;
3701 + uint32 gpioouten;
3702 + uint32 gpiocontrol;
3703 + uint32 gpiointpolarity;
3704 + uint32 gpiointmask;
3705 + uint32 PAD[2];
3706 +
3707 + /* Watchdog timer */
3708 + uint32 watchdog; /* 0x80 */
3709 + uint32 PAD[1];
3710 +
3711 + /*GPIO based LED powersave registers corerev >= 16*/
3712 + uint32 gpiotimerval; /*0x88 */
3713 + uint32 gpiotimeroutmask;
3714 +
3715 + /* clock control */
3716 + uint32 clockcontrol_n; /* 0x90 */
3717 + uint32 clockcontrol_sb; /* aka m0 */
3718 + uint32 clockcontrol_pci; /* aka m1 */
3719 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
3720 + uint32 clockcontrol_mips; /* aka m3 */
3721 + uint32 clkdiv; /* corerev >= 3 */
3722 + uint32 PAD[2];
3723 +
3724 + /* pll delay registers (corerev >= 4) */
3725 + uint32 pll_on_delay; /* 0xb0 */
3726 + uint32 fref_sel_delay;
3727 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
3728 + uint32 PAD[1];
3729 +
3730 + /* Instaclock registers (corerev >= 10) */
3731 + uint32 system_clk_ctl; /* 0xc0 */
3732 + uint32 clkstatestretch;
3733 + uint32 PAD[14];
3734 +
3735 + /* ExtBus control registers (corerev >= 3) */
3736 + uint32 pcmcia_config; /* 0x100 */
3737 + uint32 pcmcia_memwait;
3738 + uint32 pcmcia_attrwait;
3739 + uint32 pcmcia_iowait;
3740 + uint32 ide_config;
3741 + uint32 ide_memwait;
3742 + uint32 ide_attrwait;
3743 + uint32 ide_iowait;
3744 + uint32 prog_config;
3745 + uint32 prog_waitcount;
3746 + uint32 flash_config;
3747 + uint32 flash_waitcount;
3748 + uint32 PAD[116];
3749 +
3750 + /* uarts */
3751 + uint8 uart0data; /* 0x300 */
3752 + uint8 uart0imr;
3753 + uint8 uart0fcr;
3754 + uint8 uart0lcr;
3755 + uint8 uart0mcr;
3756 + uint8 uart0lsr;
3757 + uint8 uart0msr;
3758 + uint8 uart0scratch;
3759 + uint8 PAD[248]; /* corerev >= 1 */
3760 +
3761 + uint8 uart1data; /* 0x400 */
3762 + uint8 uart1imr;
3763 + uint8 uart1fcr;
3764 + uint8 uart1lcr;
3765 + uint8 uart1mcr;
3766 + uint8 uart1lsr;
3767 + uint8 uart1msr;
3768 + uint8 uart1scratch;
3769 +} chipcregs_t;
3770 +
3771 +#endif /* _LANGUAGE_ASSEMBLY */
3772 +
3773 +#define CC_CHIPID 0
3774 +#define CC_CAPABILITIES 4
3775 +#define CC_JTAGCMD 0x30
3776 +#define CC_JTAGIR 0x34
3777 +#define CC_JTAGDR 0x38
3778 +#define CC_JTAGCTRL 0x3c
3779 +#define CC_WATCHDOG 0x80
3780 +#define CC_CLKC_N 0x90
3781 +#define CC_CLKC_M0 0x94
3782 +#define CC_CLKC_M1 0x98
3783 +#define CC_CLKC_M2 0x9c
3784 +#define CC_CLKC_M3 0xa0
3785 +#define CC_CLKDIV 0xa4
3786 +#define CC_SYS_CLK_CTL 0xc0
3787 +#define CC_OTP 0x800
3788 +
3789 +/* chipid */
3790 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
3791 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
3792 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
3793 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
3794 +#define CID_PKG_SHIFT 20 /* Package Option shift */
3795 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
3796 +#define CID_CC_SHIFT 24
3797 +
3798 +/* capabilities */
3799 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
3800 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
3801 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
3802 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
3803 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
3804 +#define CAP_EXTBUS 0x00000040 /* External bus present */
3805 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
3806 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
3807 +#define CAP_PWR_CTL 0x00040000 /* Power control */
3808 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
3809 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
3810 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
3811 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
3812 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
3813 +
3814 +/* PLL type */
3815 +#define PLL_NONE 0x00000000
3816 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
3817 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
3818 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
3819 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
3820 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
3821 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
3822 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
3823 +
3824 +/* corecontrol */
3825 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
3826 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
3827 +
3828 +/* Fields in the otpstatus register */
3829 +#define OTPS_PROGFAIL 0x80000000
3830 +#define OTPS_PROTECT 0x00000007
3831 +#define OTPS_HW_PROTECT 0x00000001
3832 +#define OTPS_SW_PROTECT 0x00000002
3833 +#define OTPS_CID_PROTECT 0x00000004
3834 +
3835 +/* Fields in the otpcontrol register */
3836 +#define OTPC_RECWAIT 0xff000000
3837 +#define OTPC_PROGWAIT 0x00ffff00
3838 +#define OTPC_PRW_SHIFT 8
3839 +#define OTPC_MAXFAIL 0x00000038
3840 +#define OTPC_VSEL 0x00000006
3841 +#define OTPC_SELVL 0x00000001
3842 +
3843 +/* Fields in otpprog */
3844 +#define OTPP_COL_MASK 0x000000ff
3845 +#define OTPP_ROW_MASK 0x0000ff00
3846 +#define OTPP_ROW_SHIFT 8
3847 +#define OTPP_READERR 0x10000000
3848 +#define OTPP_VALUE 0x20000000
3849 +#define OTPP_VALUE_SHIFT 29
3850 +#define OTPP_READ 0x40000000
3851 +#define OTPP_START 0x80000000
3852 +#define OTPP_BUSY 0x80000000
3853 +
3854 +/* jtagcmd */
3855 +#define JCMD_START 0x80000000
3856 +#define JCMD_BUSY 0x80000000
3857 +#define JCMD_PAUSE 0x40000000
3858 +#define JCMD0_ACC_MASK 0x0000f000
3859 +#define JCMD0_ACC_IRDR 0x00000000
3860 +#define JCMD0_ACC_DR 0x00001000
3861 +#define JCMD0_ACC_IR 0x00002000
3862 +#define JCMD0_ACC_RESET 0x00003000
3863 +#define JCMD0_ACC_IRPDR 0x00004000
3864 +#define JCMD0_ACC_PDR 0x00005000
3865 +#define JCMD0_IRW_MASK 0x00000f00
3866 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
3867 +#define JCMD_ACC_IRDR 0x00000000
3868 +#define JCMD_ACC_DR 0x00010000
3869 +#define JCMD_ACC_IR 0x00020000
3870 +#define JCMD_ACC_RESET 0x00030000
3871 +#define JCMD_ACC_IRPDR 0x00040000
3872 +#define JCMD_ACC_PDR 0x00050000
3873 +#define JCMD_IRW_MASK 0x00001f00
3874 +#define JCMD_IRW_SHIFT 8
3875 +#define JCMD_DRW_MASK 0x0000003f
3876 +
3877 +/* jtagctrl */
3878 +#define JCTRL_FORCE_CLK 4 /* Force clock */
3879 +#define JCTRL_EXT_EN 2 /* Enable external targets */
3880 +#define JCTRL_EN 1 /* Enable Jtag master */
3881 +
3882 +/* Fields in clkdiv */
3883 +#define CLKD_SFLASH 0x0f000000
3884 +#define CLKD_SFLASH_SHIFT 24
3885 +#define CLKD_OTP 0x000f0000
3886 +#define CLKD_OTP_SHIFT 16
3887 +#define CLKD_JTAG 0x00000f00
3888 +#define CLKD_JTAG_SHIFT 8
3889 +#define CLKD_UART 0x000000ff
3890 +
3891 +/* intstatus/intmask */
3892 +#define CI_GPIO 0x00000001 /* gpio intr */
3893 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
3894 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
3895 +
3896 +/* slow_clk_ctl */
3897 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
3898 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
3899 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
3900 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
3901 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
3902 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
3903 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
3904 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
3905 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
3906 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
3907 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
3908 +#define SCC_CD_SHIFT 16
3909 +
3910 +/* system_clk_ctl */
3911 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
3912 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
3913 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
3914 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
3915 +#define SYCC_HR 0x00000010 /* Force HT */
3916 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
3917 +#define SYCC_CD_SHIFT 16
3918 +
3919 +/* gpiotimerval*/
3920 +#define GPIO_ONTIME_SHIFT 16
3921 +
3922 +/* clockcontrol_n */
3923 +#define CN_N1_MASK 0x3f /* n1 control */
3924 +#define CN_N2_MASK 0x3f00 /* n2 control */
3925 +#define CN_N2_SHIFT 8
3926 +#define CN_PLLC_MASK 0xf0000 /* pll control */
3927 +#define CN_PLLC_SHIFT 16
3928 +
3929 +/* clockcontrol_sb/pci/uart */
3930 +#define CC_M1_MASK 0x3f /* m1 control */
3931 +#define CC_M2_MASK 0x3f00 /* m2 control */
3932 +#define CC_M2_SHIFT 8
3933 +#define CC_M3_MASK 0x3f0000 /* m3 control */
3934 +#define CC_M3_SHIFT 16
3935 +#define CC_MC_MASK 0x1f000000 /* mux control */
3936 +#define CC_MC_SHIFT 24
3937 +
3938 +/* N3M Clock control magic field values */
3939 +#define CC_F6_2 0x02 /* A factor of 2 in */
3940 +#define CC_F6_3 0x03 /* 6-bit fields like */
3941 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
3942 +#define CC_F6_5 0x09
3943 +#define CC_F6_6 0x11
3944 +#define CC_F6_7 0x21
3945 +
3946 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
3947 +
3948 +#define CC_MC_BYPASS 0x08
3949 +#define CC_MC_M1 0x04
3950 +#define CC_MC_M1M2 0x02
3951 +#define CC_MC_M1M2M3 0x01
3952 +#define CC_MC_M1M3 0x11
3953 +
3954 +/* Type 2 Clock control magic field values */
3955 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
3956 +#define CC_T2M2_BIAS 3 /* m2 bias */
3957 +
3958 +#define CC_T2MC_M1BYP 1
3959 +#define CC_T2MC_M2BYP 2
3960 +#define CC_T2MC_M3BYP 4
3961 +
3962 +/* Type 6 Clock control magic field values */
3963 +#define CC_T6_MMASK 1 /* bits of interest in m */
3964 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
3965 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
3966 +#define SB2MIPS_T6(sb) (2 * (sb))
3967 +
3968 +/* Common clock base */
3969 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
3970 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
3971 +
3972 +/* Clock control values for 200Mhz in 5350 */
3973 +#define CLKC_5350_N 0x0311
3974 +#define CLKC_5350_M 0x04020009
3975 +
3976 +/* Flash types in the chipcommon capabilities register */
3977 +#define FLASH_NONE 0x000 /* No flash */
3978 +#define SFLASH_ST 0x100 /* ST serial flash */
3979 +#define SFLASH_AT 0x200 /* Atmel serial flash */
3980 +#define PFLASH 0x700 /* Parallel flash */
3981 +
3982 +/* Bits in the config registers */
3983 +#define CC_CFG_EN 0x0001 /* Enable */
3984 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
3985 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
3986 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
3987 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
3988 +#define CC_CFG_EM_IDE 0x000a /* IDE */
3989 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
3990 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
3991 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
3992 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
3993 +
3994 +/* Start/busy bit in flashcontrol */
3995 +#define SFLASH_START 0x80000000
3996 +#define SFLASH_BUSY SFLASH_START
3997 +
3998 +/* flashcontrol opcodes for ST flashes */
3999 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
4000 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
4001 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
4002 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
4003 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
4004 +#define SFLASH_ST_PP 0x0302 /* Page Program */
4005 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
4006 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
4007 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
4008 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
4009 +
4010 +/* Status register bits for ST flashes */
4011 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
4012 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
4013 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
4014 +#define SFLASH_ST_BP_SHIFT 2
4015 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
4016 +
4017 +/* flashcontrol opcodes for Atmel flashes */
4018 +#define SFLASH_AT_READ 0x07e8
4019 +#define SFLASH_AT_PAGE_READ 0x07d2
4020 +#define SFLASH_AT_BUF1_READ
4021 +#define SFLASH_AT_BUF2_READ
4022 +#define SFLASH_AT_STATUS 0x01d7
4023 +#define SFLASH_AT_BUF1_WRITE 0x0384
4024 +#define SFLASH_AT_BUF2_WRITE 0x0387
4025 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
4026 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
4027 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
4028 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
4029 +#define SFLASH_AT_PAGE_ERASE 0x0281
4030 +#define SFLASH_AT_BLOCK_ERASE 0x0250
4031 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
4032 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
4033 +#define SFLASH_AT_BUF1_LOAD 0x0253
4034 +#define SFLASH_AT_BUF2_LOAD 0x0255
4035 +#define SFLASH_AT_BUF1_COMPARE 0x0260
4036 +#define SFLASH_AT_BUF2_COMPARE 0x0261
4037 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
4038 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
4039 +
4040 +/* Status register bits for Atmel flashes */
4041 +#define SFLASH_AT_READY 0x80
4042 +#define SFLASH_AT_MISMATCH 0x40
4043 +#define SFLASH_AT_ID_MASK 0x38
4044 +#define SFLASH_AT_ID_SHIFT 3
4045 +
4046 +/* OTP regions */
4047 +#define OTP_HW_REGION OTPS_HW_PROTECT
4048 +#define OTP_SW_REGION OTPS_SW_PROTECT
4049 +#define OTP_CID_REGION OTPS_CID_PROTECT
4050 +
4051 +/* OTP regions (Byte offsets from otp size) */
4052 +#define OTP_SWLIM_OFF (-8)
4053 +#define OTP_CIDBASE_OFF 0
4054 +#define OTP_CIDLIM_OFF 8
4055 +
4056 +/* Predefined OTP words (Word offset from otp size) */
4057 +#define OTP_BOUNDARY_OFF (-4)
4058 +#define OTP_HWSIGN_OFF (-3)
4059 +#define OTP_SWSIGN_OFF (-2)
4060 +#define OTP_CIDSIGN_OFF (-1)
4061 +
4062 +#define OTP_CID_OFF 0
4063 +#define OTP_PKG_OFF 1
4064 +#define OTP_FID_OFF 2
4065 +#define OTP_RSV_OFF 3
4066 +#define OTP_LIM_OFF 4
4067 +
4068 +#define OTP_SIGNATURE 0x578a
4069 +#define OTP_MAGIC 0x4e56
4070 +
4071 +#endif /* _SBCHIPC_H */
4072 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbconfig.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbconfig.h
4073 --- linux-2.4.32/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
4074 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbconfig.h 2005-12-16 23:39:10.932836000 +0100
4075 @@ -0,0 +1,342 @@
4076 +/*
4077 + * Broadcom SiliconBackplane hardware register definitions.
4078 + *
4079 + * Copyright 2005, Broadcom Corporation
4080 + * All Rights Reserved.
4081 + *
4082 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4083 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4084 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4085 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4086 + * $Id$
4087 + */
4088 +