large target/linux cleanup
[openwrt/svn-archive/archive.git] / openwrt / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -Nur linux-2.4.32/arch/mips/bcm947xx/cfe_env.c linux-2.4.32-brcm/arch/mips/bcm947xx/cfe_env.c
2 --- linux-2.4.32/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/cfe_env.c 2005-12-19 01:56:35.104829500 +0100
4 @@ -0,0 +1,234 @@
5 +/*
6 + * NVRAM variable manipulation (Linux kernel half)
7 + *
8 + * Copyright 2001-2003, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + *
16 + * $Id$
17 + */
18 +
19 +#include <linux/config.h>
20 +#include <linux/init.h>
21 +#include <linux/module.h>
22 +#include <linux/kernel.h>
23 +#include <linux/string.h>
24 +#include <asm/io.h>
25 +#include <asm/uaccess.h>
26 +
27 +#include <typedefs.h>
28 +#include <osl.h>
29 +#include <bcmendian.h>
30 +#include <bcmutils.h>
31 +
32 +#define NVRAM_SIZE (0x1ff0)
33 +static char _nvdata[NVRAM_SIZE] __initdata;
34 +static char _valuestr[256] __initdata;
35 +
36 +/*
37 + * TLV types. These codes are used in the "type-length-value"
38 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
39 + *
40 + * The layout of the flash/nvram is as follows:
41 + *
42 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
43 + *
44 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
45 + * The "length" field marks the length of the data section, not
46 + * including the type and length fields.
47 + *
48 + * Environment variables are stored as follows:
49 + *
50 + * <type_env> <length> <flags> <name> = <value>
51 + *
52 + * If bit 0 (low bit) is set, the length is an 8-bit value.
53 + * If bit 0 (low bit) is clear, the length is a 16-bit value
54 + *
55 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
56 + * indicates the size of the length field.
57 + *
58 + * Flags are from the constants below:
59 + *
60 + */
61 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
62 +#define ENV_LENGTH_8BITS 0x01
63 +
64 +#define ENV_TYPE_USER 0x80
65 +
66 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
67 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
68 +
69 +/*
70 + * The actual TLV types we support
71 + */
72 +
73 +#define ENV_TLV_TYPE_END 0x00
74 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
75 +
76 +/*
77 + * Environment variable flags
78 + */
79 +
80 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
81 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
82 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
83 +
84 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
85 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
86 +
87 +
88 +/* *********************************************************************
89 + * _nvram_read(buffer,offset,length)
90 + *
91 + * Read data from the NVRAM device
92 + *
93 + * Input parameters:
94 + * buffer - destination buffer
95 + * offset - offset of data to read
96 + * length - number of bytes to read
97 + *
98 + * Return value:
99 + * number of bytes read, or <0 if error occured
100 + ********************************************************************* */
101 +static int
102 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
103 +{
104 + int i;
105 + if (offset > NVRAM_SIZE)
106 + return -1;
107 +
108 + for ( i = 0; i < length; i++) {
109 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
110 + }
111 + return length;
112 +}
113 +
114 +
115 +static char*
116 +_strnchr(const char *dest,int c,size_t cnt)
117 +{
118 + while (*dest && (cnt > 0)) {
119 + if (*dest == c) return (char *) dest;
120 + dest++;
121 + cnt--;
122 + }
123 + return NULL;
124 +}
125 +
126 +
127 +
128 +/*
129 + * Core support API: Externally visible.
130 + */
131 +
132 +/*
133 + * Get the value of an NVRAM variable
134 + * @param name name of variable to get
135 + * @return value of variable or NULL if undefined
136 + */
137 +
138 +char*
139 +cfe_env_get(unsigned char *nv_buf, char* name)
140 +{
141 + int size;
142 + unsigned char *buffer;
143 + unsigned char *ptr;
144 + unsigned char *envval;
145 + unsigned int reclen;
146 + unsigned int rectype;
147 + int offset;
148 + int flg;
149 +
150 + size = NVRAM_SIZE;
151 + buffer = &_nvdata[0];
152 +
153 + ptr = buffer;
154 + offset = 0;
155 +
156 + /* Read the record type and length */
157 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
158 + goto error;
159 + }
160 +
161 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
162 +
163 + /* Adjust pointer for TLV type */
164 + rectype = *(ptr);
165 + offset++;
166 + size--;
167 +
168 + /*
169 + * Read the length. It can be either 1 or 2 bytes
170 + * depending on the code
171 + */
172 + if (rectype & ENV_LENGTH_8BITS) {
173 + /* Read the record type and length - 8 bits */
174 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
175 + goto error;
176 + }
177 + reclen = *(ptr);
178 + size--;
179 + offset++;
180 + }
181 + else {
182 + /* Read the record type and length - 16 bits, MSB first */
183 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
184 + goto error;
185 + }
186 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
187 + size -= 2;
188 + offset += 2;
189 + }
190 +
191 + if (reclen > size)
192 + break; /* should not happen, bad NVRAM */
193 +
194 + switch (rectype) {
195 + case ENV_TLV_TYPE_ENV:
196 + /* Read the TLV data */
197 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
198 + goto error;
199 + flg = *ptr++;
200 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
201 + if (envval) {
202 + *envval++ = '\0';
203 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
204 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
205 +#if 0
206 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
207 +#endif
208 + if(!strcmp(ptr, name)){
209 + return _valuestr;
210 + }
211 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
212 + return _valuestr;
213 + }
214 + break;
215 +
216 + default:
217 + /* Unknown TLV type, skip it. */
218 + break;
219 + }
220 +
221 + /*
222 + * Advance to next TLV
223 + */
224 +
225 + size -= (int)reclen;
226 + offset += reclen;
227 +
228 + /* Read the next record type */
229 + ptr = buffer;
230 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
231 + goto error;
232 + }
233 +
234 +error:
235 + return NULL;
236 +
237 +}
238 +
239 diff -Nur linux-2.4.32/arch/mips/bcm947xx/compressed/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/compressed/Makefile
240 --- linux-2.4.32/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
241 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/compressed/Makefile 2005-12-16 23:39:10.668819500 +0100
242 @@ -0,0 +1,33 @@
243 +#
244 +# Makefile for Broadcom BCM947XX boards
245 +#
246 +# Copyright 2001-2003, Broadcom Corporation
247 +# All Rights Reserved.
248 +#
249 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
250 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
251 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
252 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
253 +#
254 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
255 +#
256 +
257 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
258 +SYSTEM ?= $(TOPDIR)/vmlinux
259 +
260 +all: vmlinuz
261 +
262 +# Don't build dependencies, this may die if $(CC) isn't gcc
263 +dep:
264 +
265 +# Create a gzipped version named vmlinuz for compatibility
266 +vmlinuz: piggy
267 + gzip -c9 $< > $@
268 +
269 +piggy: $(SYSTEM)
270 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
271 +
272 +mrproper: clean
273 +
274 +clean:
275 + rm -f vmlinuz piggy
276 diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/int-handler.S linux-2.4.32-brcm/arch/mips/bcm947xx/generic/int-handler.S
277 --- linux-2.4.32/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
278 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/int-handler.S 2005-12-16 23:39:10.668819500 +0100
279 @@ -0,0 +1,51 @@
280 +/*
281 + * Generic interrupt handler for Broadcom MIPS boards
282 + *
283 + * Copyright 2004, Broadcom Corporation
284 + * All Rights Reserved.
285 + *
286 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
287 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
288 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
289 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
290 + *
291 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
292 + */
293 +
294 +#include <linux/config.h>
295 +
296 +#include <asm/asm.h>
297 +#include <asm/mipsregs.h>
298 +#include <asm/regdef.h>
299 +#include <asm/stackframe.h>
300 +
301 +/*
302 + * MIPS IRQ Source
303 + * -------- ------
304 + * 0 Software (ignored)
305 + * 1 Software (ignored)
306 + * 2 Combined hardware interrupt (hw0)
307 + * 3 Hardware
308 + * 4 Hardware
309 + * 5 Hardware
310 + * 6 Hardware
311 + * 7 R4k timer
312 + */
313 +
314 + .text
315 + .set noreorder
316 + .set noat
317 + .align 5
318 + NESTED(brcmIRQ, PT_SIZE, sp)
319 + SAVE_ALL
320 + CLI
321 + .set at
322 + .set noreorder
323 +
324 + jal brcm_irq_dispatch
325 + move a0, sp
326 +
327 + j ret_from_irq
328 + nop
329 +
330 + END(brcmIRQ)
331 diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/irq.c linux-2.4.32-brcm/arch/mips/bcm947xx/generic/irq.c
332 --- linux-2.4.32/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
333 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/irq.c 2005-12-16 23:39:10.668819500 +0100
334 @@ -0,0 +1,130 @@
335 +/*
336 + * Generic interrupt control functions for Broadcom MIPS boards
337 + *
338 + * Copyright 2004, Broadcom Corporation
339 + * All Rights Reserved.
340 + *
341 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
342 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
343 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
344 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
345 + *
346 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
347 + */
348 +
349 +#include <linux/config.h>
350 +#include <linux/init.h>
351 +#include <linux/kernel.h>
352 +#include <linux/types.h>
353 +#include <linux/interrupt.h>
354 +#include <linux/irq.h>
355 +
356 +#include <asm/irq.h>
357 +#include <asm/mipsregs.h>
358 +#include <asm/gdb-stub.h>
359 +
360 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
361 +
362 +extern asmlinkage void brcmIRQ(void);
363 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
364 +
365 +void
366 +brcm_irq_dispatch(struct pt_regs *regs)
367 +{
368 + u32 cause;
369 +
370 + cause = read_c0_cause() &
371 + read_c0_status() &
372 + CAUSEF_IP;
373 +
374 +#ifdef CONFIG_KERNPROF
375 + change_c0_status(cause | 1, 1);
376 +#else
377 + clear_c0_status(cause);
378 +#endif
379 +
380 + if (cause & CAUSEF_IP7)
381 + do_IRQ(7, regs);
382 + if (cause & CAUSEF_IP2)
383 + do_IRQ(2, regs);
384 + if (cause & CAUSEF_IP3)
385 + do_IRQ(3, regs);
386 + if (cause & CAUSEF_IP4)
387 + do_IRQ(4, regs);
388 + if (cause & CAUSEF_IP5)
389 + do_IRQ(5, regs);
390 + if (cause & CAUSEF_IP6)
391 + do_IRQ(6, regs);
392 +}
393 +
394 +static void
395 +enable_brcm_irq(unsigned int irq)
396 +{
397 + if (irq < 8)
398 + set_c0_status(1 << (irq + 8));
399 + else
400 + set_c0_status(IE_IRQ0);
401 +}
402 +
403 +static void
404 +disable_brcm_irq(unsigned int irq)
405 +{
406 + if (irq < 8)
407 + clear_c0_status(1 << (irq + 8));
408 + else
409 + clear_c0_status(IE_IRQ0);
410 +}
411 +
412 +static void
413 +ack_brcm_irq(unsigned int irq)
414 +{
415 + /* Already done in brcm_irq_dispatch */
416 +}
417 +
418 +static unsigned int
419 +startup_brcm_irq(unsigned int irq)
420 +{
421 + enable_brcm_irq(irq);
422 +
423 + return 0; /* never anything pending */
424 +}
425 +
426 +static void
427 +end_brcm_irq(unsigned int irq)
428 +{
429 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
430 + enable_brcm_irq(irq);
431 +}
432 +
433 +static struct hw_interrupt_type brcm_irq_type = {
434 + typename: "MIPS",
435 + startup: startup_brcm_irq,
436 + shutdown: disable_brcm_irq,
437 + enable: enable_brcm_irq,
438 + disable: disable_brcm_irq,
439 + ack: ack_brcm_irq,
440 + end: end_brcm_irq,
441 + NULL
442 +};
443 +
444 +void __init
445 +init_IRQ(void)
446 +{
447 + int i;
448 +
449 + for (i = 0; i < NR_IRQS; i++) {
450 + irq_desc[i].status = IRQ_DISABLED;
451 + irq_desc[i].action = 0;
452 + irq_desc[i].depth = 1;
453 + irq_desc[i].handler = &brcm_irq_type;
454 + }
455 +
456 + set_except_vector(0, brcmIRQ);
457 + change_c0_status(ST0_IM, ALLINTS);
458 +
459 +#ifdef CONFIG_REMOTE_DEBUG
460 + printk("Breaking into debugger...\n");
461 + set_debug_traps();
462 + breakpoint();
463 +#endif
464 +}
465 diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/generic/Makefile
466 --- linux-2.4.32/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
467 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/Makefile 2005-12-16 23:39:10.668819500 +0100
468 @@ -0,0 +1,15 @@
469 +#
470 +# Makefile for the BCM947xx specific kernel interface routines
471 +# under Linux.
472 +#
473 +
474 +.S.s:
475 + $(CPP) $(AFLAGS) $< -o $*.s
476 +.S.o:
477 + $(CC) $(AFLAGS) -c $< -o $*.o
478 +
479 +O_TARGET := brcm.o
480 +
481 +obj-y := int-handler.o irq.o
482 +
483 +include $(TOPDIR)/Rules.make
484 diff -Nur linux-2.4.32/arch/mips/bcm947xx/gpio.c linux-2.4.32-brcm/arch/mips/bcm947xx/gpio.c
485 --- linux-2.4.32/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
486 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/gpio.c 2005-12-16 23:39:10.668819500 +0100
487 @@ -0,0 +1,158 @@
488 +/*
489 + * GPIO char driver
490 + *
491 + * Copyright 2005, Broadcom Corporation
492 + * All Rights Reserved.
493 + *
494 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
495 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
496 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
497 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
498 + *
499 + * $Id$
500 + */
501 +
502 +#include <linux/module.h>
503 +#include <linux/init.h>
504 +#include <linux/fs.h>
505 +#include <linux/miscdevice.h>
506 +#include <asm/uaccess.h>
507 +
508 +#include <typedefs.h>
509 +#include <bcmutils.h>
510 +#include <sbutils.h>
511 +#include <bcmdevs.h>
512 +
513 +static sb_t *gpio_sbh;
514 +static int gpio_major;
515 +static devfs_handle_t gpio_dir;
516 +static struct {
517 + char *name;
518 + devfs_handle_t handle;
519 +} gpio_file[] = {
520 + { "in", NULL },
521 + { "out", NULL },
522 + { "outen", NULL },
523 + { "control", NULL }
524 +};
525 +
526 +static int
527 +gpio_open(struct inode *inode, struct file * file)
528 +{
529 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
530 + return -ENODEV;
531 +
532 + MOD_INC_USE_COUNT;
533 + return 0;
534 +}
535 +
536 +static int
537 +gpio_release(struct inode *inode, struct file * file)
538 +{
539 + MOD_DEC_USE_COUNT;
540 + return 0;
541 +}
542 +
543 +static ssize_t
544 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
545 +{
546 + u32 val;
547 +
548 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
549 + case 0:
550 + val = sb_gpioin(gpio_sbh);
551 + break;
552 + case 1:
553 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
554 + break;
555 + case 2:
556 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
557 + break;
558 + case 3:
559 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
560 + break;
561 + default:
562 + return -ENODEV;
563 + }
564 +
565 + if (put_user(val, (u32 *) buf))
566 + return -EFAULT;
567 +
568 + return sizeof(val);
569 +}
570 +
571 +static ssize_t
572 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
573 +{
574 + u32 val;
575 +
576 + if (get_user(val, (u32 *) buf))
577 + return -EFAULT;
578 +
579 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
580 + case 0:
581 + return -EACCES;
582 + case 1:
583 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
584 + break;
585 + case 2:
586 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
587 + break;
588 + case 3:
589 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
590 + break;
591 + default:
592 + return -ENODEV;
593 + }
594 +
595 + return sizeof(val);
596 +}
597 +
598 +static struct file_operations gpio_fops = {
599 + owner: THIS_MODULE,
600 + open: gpio_open,
601 + release: gpio_release,
602 + read: gpio_read,
603 + write: gpio_write,
604 +};
605 +
606 +static int __init
607 +gpio_init(void)
608 +{
609 + int i;
610 +
611 + if (!(gpio_sbh = sb_kattach()))
612 + return -ENODEV;
613 +
614 + sb_gpiosetcore(gpio_sbh);
615 +
616 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
617 + return gpio_major;
618 +
619 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
620 +
621 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
622 + gpio_file[i].handle = devfs_register(gpio_dir,
623 + gpio_file[i].name,
624 + DEVFS_FL_DEFAULT, gpio_major, i,
625 + S_IFCHR | S_IRUGO | S_IWUGO,
626 + &gpio_fops, NULL);
627 + }
628 +
629 + return 0;
630 +}
631 +
632 +static void __exit
633 +gpio_exit(void)
634 +{
635 + int i;
636 +
637 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
638 + devfs_unregister(gpio_file[i].handle);
639 + devfs_unregister(gpio_dir);
640 + devfs_unregister_chrdev(gpio_major, "gpio");
641 + sb_detach(gpio_sbh);
642 +}
643 +
644 +module_init(gpio_init);
645 +module_exit(gpio_exit);
646 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmdevs.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmdevs.h
647 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
648 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmdevs.h 2005-12-16 23:39:10.672819750 +0100
649 @@ -0,0 +1,391 @@
650 +/*
651 + * Broadcom device-specific manifest constants.
652 + *
653 + * Copyright 2005, Broadcom Corporation
654 + * All Rights Reserved.
655 + *
656 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
657 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
658 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
659 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
660 + * $Id$
661 + */
662 +
663 +#ifndef _BCMDEVS_H
664 +#define _BCMDEVS_H
665 +
666 +
667 +/* Known PCI vendor Id's */
668 +#define VENDOR_EPIGRAM 0xfeda
669 +#define VENDOR_BROADCOM 0x14e4
670 +#define VENDOR_3COM 0x10b7
671 +#define VENDOR_NETGEAR 0x1385
672 +#define VENDOR_DIAMOND 0x1092
673 +#define VENDOR_DELL 0x1028
674 +#define VENDOR_HP 0x0e11
675 +#define VENDOR_APPLE 0x106b
676 +
677 +/* PCI Device Id's */
678 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
679 +#define BCM4211_DEVICE_ID 0x4211
680 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
681 +#define BCM4231_DEVICE_ID 0x4231
682 +
683 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
684 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
685 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
686 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
687 +
688 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
689 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
690 +
691 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
692 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
693 +
694 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
695 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
696 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
697 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
698 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
699 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
700 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
701 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
702 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
703 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
704 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
705 +
706 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
707 +
708 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
709 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
710 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
711 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
712 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
713 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
714 +
715 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
716 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
717 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
718 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
719 +
720 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
721 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
722 +
723 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
724 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
725 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
726 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
727 +
728 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
729 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
730 +#define BCM4306_D11G_ID2 0x4325
731 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
732 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
733 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
734 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
735 +
736 +#define BCM4309_PKG_ID 1 /* 4309 package id */
737 +
738 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
739 +#define BCM4303_PKG_ID 2 /* 4303 package id */
740 +
741 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
742 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
743 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
744 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
745 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
746 +
747 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
748 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
749 +
750 +
751 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
752 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
753 +
754 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
755 +
756 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
757 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
758 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
759 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
760 +
761 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
762 +
763 +/* Address map */
764 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
765 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
766 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
767 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
768 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
769 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
770 +
771 +/* Core register space */
772 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
773 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
774 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
775 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
776 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
777 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
778 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
779 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
780 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
781 +
782 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
783 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
784 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
785 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
786 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
787 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
788 +
789 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
790 +
791 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
792 +
793 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
794 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
795 +
796 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
797 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
798 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
799 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
800 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
801 +
802 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
803 +
804 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
805 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
806 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
807 +
808 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
809 +
810 +/* PCMCIA vendor Id's */
811 +
812 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
813 +
814 +/* SDIO vendor Id's */
815 +#define VENDOR_BROADCOM_SDIO 0x00BF
816 +
817 +
818 +/* boardflags */
819 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
820 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
821 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
822 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
823 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
824 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
825 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
826 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
827 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
828 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
829 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
830 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
831 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
832 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
833 +
834 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
835 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
836 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
837 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
838 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
839 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
840 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
841 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
842 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
843 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
844 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
845 +
846 +/* Bus types */
847 +#define SB_BUS 0 /* Silicon Backplane */
848 +#define PCI_BUS 1 /* PCI target */
849 +#define PCMCIA_BUS 2 /* PCMCIA target */
850 +#define SDIO_BUS 3 /* SDIO target */
851 +#define JTAG_BUS 4 /* JTAG */
852 +
853 +/* Allows optimization for single-bus support */
854 +#ifdef BCMBUSTYPE
855 +#define BUSTYPE(bus) (BCMBUSTYPE)
856 +#else
857 +#define BUSTYPE(bus) (bus)
858 +#endif
859 +
860 +/* power control defines */
861 +#define PLL_DELAY 150 /* us pll on delay */
862 +#define FREF_DELAY 200 /* us fref change delay */
863 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
864 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
865 +
866 +/* Reference Board Types */
867 +
868 +#define BU4710_BOARD 0x0400
869 +#define VSIM4710_BOARD 0x0401
870 +#define QT4710_BOARD 0x0402
871 +
872 +#define BU4610_BOARD 0x0403
873 +#define VSIM4610_BOARD 0x0404
874 +
875 +#define BU4307_BOARD 0x0405
876 +#define BCM94301CB_BOARD 0x0406
877 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
878 +#define BCM94301MP_BOARD 0x0407
879 +#define BCM94307MP_BOARD 0x0408
880 +#define BCMAP4307_BOARD 0x0409
881 +
882 +#define BU4309_BOARD 0x040a
883 +#define BCM94309CB_BOARD 0x040b
884 +#define BCM94309MP_BOARD 0x040c
885 +#define BCM4309AP_BOARD 0x040d
886 +
887 +#define BCM94302MP_BOARD 0x040e
888 +
889 +#define VSIM4310_BOARD 0x040f
890 +#define BU4711_BOARD 0x0410
891 +#define BCM94310U_BOARD 0x0411
892 +#define BCM94310AP_BOARD 0x0412
893 +#define BCM94310MP_BOARD 0x0414
894 +
895 +#define BU4306_BOARD 0x0416
896 +#define BCM94306CB_BOARD 0x0417
897 +#define BCM94306MP_BOARD 0x0418
898 +
899 +#define BCM94710D_BOARD 0x041a
900 +#define BCM94710R1_BOARD 0x041b
901 +#define BCM94710R4_BOARD 0x041c
902 +#define BCM94710AP_BOARD 0x041d
903 +
904 +
905 +#define BU2050_BOARD 0x041f
906 +
907 +
908 +#define BCM94309G_BOARD 0x0421
909 +
910 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
911 +
912 +#define BU4704_BOARD 0x0423
913 +#define BU4702_BOARD 0x0424
914 +
915 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
916 +
917 +#define BU4317_BOARD 0x0426
918 +
919 +
920 +#define BCM94702MN_BOARD 0x0428
921 +
922 +/* BCM4702 1U CompactPCI Board */
923 +#define BCM94702CPCI_BOARD 0x0429
924 +
925 +/* BCM4702 with BCM95380 VLAN Router */
926 +#define BCM95380RR_BOARD 0x042a
927 +
928 +/* cb4306 with SiGe PA */
929 +#define BCM94306CBSG_BOARD 0x042b
930 +
931 +/* mp4301 with 2050 radio */
932 +#define BCM94301MPL_BOARD 0x042c
933 +
934 +/* cb4306 with SiGe PA */
935 +#define PCSG94306_BOARD 0x042d
936 +
937 +/* bu4704 with sdram */
938 +#define BU4704SD_BOARD 0x042e
939 +
940 +/* Dual 11a/11g Router */
941 +#define BCM94704AGR_BOARD 0x042f
942 +
943 +/* 11a-only minipci */
944 +#define BCM94308MP_BOARD 0x0430
945 +
946 +
947 +
948 +/* BCM94317 boards */
949 +#define BCM94317CB_BOARD 0x0440
950 +#define BCM94317MP_BOARD 0x0441
951 +#define BCM94317PCMCIA_BOARD 0x0442
952 +#define BCM94317SDIO_BOARD 0x0443
953 +
954 +#define BU4712_BOARD 0x0444
955 +#define BU4712SD_BOARD 0x045d
956 +#define BU4712L_BOARD 0x045f
957 +
958 +/* BCM4712 boards */
959 +#define BCM94712AP_BOARD 0x0445
960 +#define BCM94712P_BOARD 0x0446
961 +
962 +/* BCM4318 boards */
963 +#define BU4318_BOARD 0x0447
964 +#define CB4318_BOARD 0x0448
965 +#define MPG4318_BOARD 0x0449
966 +#define MP4318_BOARD 0x044a
967 +#define SD4318_BOARD 0x044b
968 +
969 +/* BCM63XX boards */
970 +#define BCM96338_BOARD 0x6338
971 +#define BCM96345_BOARD 0x6345
972 +#define BCM96348_BOARD 0x6348
973 +
974 +/* Another mp4306 with SiGe */
975 +#define BCM94306P_BOARD 0x044c
976 +
977 +/* CF-like 4317 modules */
978 +#define BCM94317CF_BOARD 0x044d
979 +
980 +/* mp4303 */
981 +#define BCM94303MP_BOARD 0x044e
982 +
983 +/* mpsgh4306 */
984 +#define BCM94306MPSGH_BOARD 0x044f
985 +
986 +/* BRCM 4306 w/ Front End Modules */
987 +#define BCM94306MPM 0x0450
988 +#define BCM94306MPL 0x0453
989 +
990 +/* 4712agr */
991 +#define BCM94712AGR_BOARD 0x0451
992 +
993 +/* The real CF 4317 board */
994 +#define CFI4317_BOARD 0x0452
995 +
996 +/* pcmcia 4303 */
997 +#define PC4303_BOARD 0x0454
998 +
999 +/* 5350K */
1000 +#define BCM95350K_BOARD 0x0455
1001 +
1002 +/* 5350R */
1003 +#define BCM95350R_BOARD 0x0456
1004 +
1005 +/* 4306mplna */
1006 +#define BCM94306MPLNA_BOARD 0x0457
1007 +
1008 +/* 4320 boards */
1009 +#define BU4320_BOARD 0x0458
1010 +#define BU4320S_BOARD 0x0459
1011 +#define BCM94320PH_BOARD 0x045a
1012 +
1013 +/* 4306mph */
1014 +#define BCM94306MPH_BOARD 0x045b
1015 +
1016 +/* 4306pciv */
1017 +#define BCM94306PCIV_BOARD 0x045c
1018 +
1019 +#define BU4712SD_BOARD 0x045d
1020 +
1021 +#define BCM94320PFLSH_BOARD 0x045e
1022 +
1023 +#define BU4712L_BOARD 0x045f
1024 +#define BCM94712LGR_BOARD 0x0460
1025 +#define BCM94320R_BOARD 0x0461
1026 +
1027 +#define BU5352_BOARD 0x0462
1028 +
1029 +#define BCM94318MPGH_BOARD 0x0463
1030 +
1031 +
1032 +#define BCM95352GR_BOARD 0x0467
1033 +
1034 +/* bcm95351agr */
1035 +#define BCM95351AGR_BOARD 0x0470
1036 +
1037 +/* # of GPIO pins */
1038 +#define GPIO_NUMPINS 16
1039 +
1040 +#endif /* _BCMDEVS_H */
1041 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmendian.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmendian.h
1042 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
1043 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmendian.h 2005-12-16 23:39:10.672819750 +0100
1044 @@ -0,0 +1,152 @@
1045 +/*
1046 + * local version of endian.h - byte order defines
1047 + *
1048 + * Copyright 2005, Broadcom Corporation
1049 + * All Rights Reserved.
1050 + *
1051 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1052 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1053 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1054 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1055 + *
1056 + * $Id$
1057 +*/
1058 +
1059 +#ifndef _BCMENDIAN_H_
1060 +#define _BCMENDIAN_H_
1061 +
1062 +#include <typedefs.h>
1063 +
1064 +/* Byte swap a 16 bit value */
1065 +#define BCMSWAP16(val) \
1066 + ((uint16)( \
1067 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
1068 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
1069 +
1070 +/* Byte swap a 32 bit value */
1071 +#define BCMSWAP32(val) \
1072 + ((uint32)( \
1073 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
1074 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
1075 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
1076 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
1077 +
1078 +/* 2 Byte swap a 32 bit value */
1079 +#define BCMSWAP32BY16(val) \
1080 + ((uint32)( \
1081 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
1082 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
1083 +
1084 +
1085 +static INLINE uint16
1086 +bcmswap16(uint16 val)
1087 +{
1088 + return BCMSWAP16(val);
1089 +}
1090 +
1091 +static INLINE uint32
1092 +bcmswap32(uint32 val)
1093 +{
1094 + return BCMSWAP32(val);
1095 +}
1096 +
1097 +static INLINE uint32
1098 +bcmswap32by16(uint32 val)
1099 +{
1100 + return BCMSWAP32BY16(val);
1101 +}
1102 +
1103 +/* buf - start of buffer of shorts to swap */
1104 +/* len - byte length of buffer */
1105 +static INLINE void
1106 +bcmswap16_buf(uint16 *buf, uint len)
1107 +{
1108 + len = len/2;
1109 +
1110 + while(len--){
1111 + *buf = bcmswap16(*buf);
1112 + buf++;
1113 + }
1114 +}
1115 +
1116 +#ifndef hton16
1117 +#ifndef IL_BIGENDIAN
1118 +#define HTON16(i) BCMSWAP16(i)
1119 +#define hton16(i) bcmswap16(i)
1120 +#define hton32(i) bcmswap32(i)
1121 +#define ntoh16(i) bcmswap16(i)
1122 +#define ntoh32(i) bcmswap32(i)
1123 +#define ltoh16(i) (i)
1124 +#define ltoh32(i) (i)
1125 +#define htol16(i) (i)
1126 +#define htol32(i) (i)
1127 +#else
1128 +#define HTON16(i) (i)
1129 +#define hton16(i) (i)
1130 +#define hton32(i) (i)
1131 +#define ntoh16(i) (i)
1132 +#define ntoh32(i) (i)
1133 +#define ltoh16(i) bcmswap16(i)
1134 +#define ltoh32(i) bcmswap32(i)
1135 +#define htol16(i) bcmswap16(i)
1136 +#define htol32(i) bcmswap32(i)
1137 +#endif
1138 +#endif
1139 +
1140 +#ifndef IL_BIGENDIAN
1141 +#define ltoh16_buf(buf, i)
1142 +#define htol16_buf(buf, i)
1143 +#else
1144 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1145 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1146 +#endif
1147 +
1148 +/*
1149 +* load 16-bit value from unaligned little endian byte array.
1150 +*/
1151 +static INLINE uint16
1152 +ltoh16_ua(uint8 *bytes)
1153 +{
1154 + return (bytes[1]<<8)+bytes[0];
1155 +}
1156 +
1157 +/*
1158 +* load 32-bit value from unaligned little endian byte array.
1159 +*/
1160 +static INLINE uint32
1161 +ltoh32_ua(uint8 *bytes)
1162 +{
1163 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
1164 +}
1165 +
1166 +/*
1167 +* load 16-bit value from unaligned big(network) endian byte array.
1168 +*/
1169 +static INLINE uint16
1170 +ntoh16_ua(uint8 *bytes)
1171 +{
1172 + return (bytes[0]<<8)+bytes[1];
1173 +}
1174 +
1175 +/*
1176 +* load 32-bit value from unaligned big(network) endian byte array.
1177 +*/
1178 +static INLINE uint32
1179 +ntoh32_ua(uint8 *bytes)
1180 +{
1181 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
1182 +}
1183 +
1184 +#define ltoh_ua(ptr) ( \
1185 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1186 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
1187 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
1188 +)
1189 +
1190 +#define ntoh_ua(ptr) ( \
1191 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1192 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
1193 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
1194 +)
1195 +
1196 +#endif /* _BCMENDIAN_H_ */
1197 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenet47xx.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h
1198 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
1199 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-12-16 23:39:10.700821500 +0100
1200 @@ -0,0 +1,229 @@
1201 +/*
1202 + * Hardware-specific definitions for
1203 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
1204 + *
1205 + * Copyright 2005, Broadcom Corporation
1206 + * All Rights Reserved.
1207 + *
1208 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1209 + * the contents of this file may not be disclosed to third parties, copied
1210 + * or duplicated in any form, in whole or in part, without the prior
1211 + * written permission of Broadcom Corporation.
1212 + * $Id$
1213 + */
1214 +
1215 +#ifndef _bcmenet_47xx_h_
1216 +#define _bcmenet_47xx_h_
1217 +
1218 +#include <bcmenetmib.h>
1219 +#include <bcmenetrxh.h>
1220 +#include <bcmenetphy.h>
1221 +
1222 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
1223 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
1224 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
1225 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
1226 +
1227 +/* power management event wakeup pattern constants */
1228 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
1229 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
1230 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
1231 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
1232 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
1233 +
1234 +/* cpp contortions to concatenate w/arg prescan */
1235 +#ifndef PAD
1236 +#define _PADLINE(line) pad ## line
1237 +#define _XSTR(line) _PADLINE(line)
1238 +#define PAD _XSTR(__LINE__)
1239 +#endif /* PAD */
1240 +
1241 +/*
1242 + * Host Interface Registers
1243 + */
1244 +typedef volatile struct _bcmenettregs {
1245 + /* Device and Power Control */
1246 + uint32 devcontrol;
1247 + uint32 PAD[2];
1248 + uint32 biststatus;
1249 + uint32 wakeuplength;
1250 + uint32 PAD[3];
1251 +
1252 + /* Interrupt Control */
1253 + uint32 intstatus;
1254 + uint32 intmask;
1255 + uint32 gptimer;
1256 + uint32 PAD[23];
1257 +
1258 + /* Ethernet MAC Address Filtering Control */
1259 + uint32 PAD[2];
1260 + uint32 enetftaddr;
1261 + uint32 enetftdata;
1262 + uint32 PAD[2];
1263 +
1264 + /* Ethernet MAC Control */
1265 + uint32 emactxmaxburstlen;
1266 + uint32 emacrxmaxburstlen;
1267 + uint32 emaccontrol;
1268 + uint32 emacflowcontrol;
1269 +
1270 + uint32 PAD[20];
1271 +
1272 + /* DMA Lazy Interrupt Control */
1273 + uint32 intrecvlazy;
1274 + uint32 PAD[63];
1275 +
1276 + /* DMA engine */
1277 + dma32regp_t dmaregs;
1278 + dma32diag_t dmafifo;
1279 + uint32 PAD[116];
1280 +
1281 + /* EMAC Registers */
1282 + uint32 rxconfig;
1283 + uint32 rxmaxlength;
1284 + uint32 txmaxlength;
1285 + uint32 PAD;
1286 + uint32 mdiocontrol;
1287 + uint32 mdiodata;
1288 + uint32 emacintmask;
1289 + uint32 emacintstatus;
1290 + uint32 camdatalo;
1291 + uint32 camdatahi;
1292 + uint32 camcontrol;
1293 + uint32 enetcontrol;
1294 + uint32 txcontrol;
1295 + uint32 txwatermark;
1296 + uint32 mibcontrol;
1297 + uint32 PAD[49];
1298 +
1299 + /* EMAC MIB counters */
1300 + bcmenetmib_t mib;
1301 +
1302 + uint32 PAD[585];
1303 +
1304 + /* Sonics SiliconBackplane config registers */
1305 + sbconfig_t sbconfig;
1306 +} bcmenetregs_t;
1307 +
1308 +/* device control */
1309 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
1310 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
1311 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
1312 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
1313 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
1314 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
1315 +#define DC_PA_SHIFT 18
1316 +#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
1317 +#define DC_FS_SHIFT 23
1318 +#define DC_FS_4K 0 /* 4Kbytes */
1319 +#define DC_FS_512 1 /* 512bytes */
1320 +
1321 +/* wakeup length */
1322 +#define WL_P0_MASK 0x7f /* pattern 0 */
1323 +#define WL_D0 ((uint32)1 << 7)
1324 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
1325 +#define WL_P1_SHIFT 8
1326 +#define WL_D1 ((uint32)1 << 15)
1327 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
1328 +#define WL_P2_SHIFT 16
1329 +#define WL_D2 ((uint32)1 << 23)
1330 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
1331 +#define WL_P3_SHIFT 24
1332 +#define WL_D3 ((uint32)1 << 31)
1333 +
1334 +/* intstatus and intmask */
1335 +#define I_PME ((uint32)1 << 6) /* power management event */
1336 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
1337 +#define I_PC ((uint32)1 << 10) /* descriptor error */
1338 +#define I_PD ((uint32)1 << 11) /* data error */
1339 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
1340 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
1341 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
1342 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
1343 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
1344 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
1345 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
1346 +#define I_MW ((uint32)1 << 27) /* mii write */
1347 +#define I_MR ((uint32)1 << 28) /* mii read */
1348 +
1349 +/* emaccontrol */
1350 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
1351 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
1352 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
1353 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
1354 +#define EMC_LC_SHIFT 5
1355 +
1356 +/* emacflowcontrol */
1357 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
1358 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
1359 +
1360 +/* interrupt receive lazy */
1361 +#define IRL_TO_MASK 0x00ffffff /* timeout */
1362 +#define IRL_FC_MASK 0xff000000 /* frame count */
1363 +#define IRL_FC_SHIFT 24 /* frame count */
1364 +
1365 +/* emac receive config */
1366 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
1367 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
1368 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
1369 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
1370 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
1371 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
1372 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
1373 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
1374 +#define ERC_CA ((uint32)1 << 8) /* cam absent */
1375 +
1376 +/* emac mdio control */
1377 +#define MC_MF_MASK 0x7f /* mdc frequency */
1378 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
1379 +
1380 +/* emac mdio data */
1381 +#define MD_DATA_MASK 0xffff /* r/w data */
1382 +#define MD_TA_MASK 0x30000 /* turnaround value */
1383 +#define MD_TA_SHIFT 16
1384 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
1385 +#define MD_RA_MASK 0x7c0000 /* register address */
1386 +#define MD_RA_SHIFT 18
1387 +#define MD_PMD_MASK 0xf800000 /* physical media device */
1388 +#define MD_PMD_SHIFT 23
1389 +#define MD_OP_MASK 0x30000000 /* opcode */
1390 +#define MD_OP_SHIFT 28
1391 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
1392 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
1393 +#define MD_SB_MASK 0xc0000000 /* start bits */
1394 +#define MD_SB_SHIFT 30
1395 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
1396 +
1397 +/* emac intstatus and intmask */
1398 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
1399 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
1400 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
1401 +
1402 +/* emac cam data high */
1403 +#define CD_V ((uint32)1 << 16) /* valid bit */
1404 +
1405 +/* emac cam control */
1406 +#define CC_CE ((uint32)1 << 0) /* cam enable */
1407 +#define CC_MS ((uint32)1 << 1) /* mask select */
1408 +#define CC_RD ((uint32)1 << 2) /* read */
1409 +#define CC_WR ((uint32)1 << 3) /* write */
1410 +#define CC_INDEX_MASK 0x3f0000 /* index */
1411 +#define CC_INDEX_SHIFT 16
1412 +#define CC_CB ((uint32)1 << 31) /* cam busy */
1413 +
1414 +/* emac ethernet control */
1415 +#define EC_EE ((uint32)1 << 0) /* emac enable */
1416 +#define EC_ED ((uint32)1 << 1) /* emac disable */
1417 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
1418 +#define EC_EP ((uint32)1 << 3) /* external phy select */
1419 +
1420 +/* emac transmit control */
1421 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
1422 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
1423 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
1424 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
1425 +
1426 +/* emac mib control */
1427 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
1428 +
1429 +#endif /* _bcmenet_47xx_h_ */
1430 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenetmib.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetmib.h
1431 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
1432 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetmib.h 2005-12-16 23:39:10.700821500 +0100
1433 @@ -0,0 +1,81 @@
1434 +/*
1435 + * Hardware-specific MIB definition for
1436 + * Broadcom Home Networking Division
1437 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1438 + *
1439 + * Copyright 2005, Broadcom Corporation
1440 + * All Rights Reserved.
1441 + *
1442 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1443 + * the contents of this file may not be disclosed to third parties, copied
1444 + * or duplicated in any form, in whole or in part, without the prior
1445 + * written permission of Broadcom Corporation.
1446 + * $Id$
1447 + */
1448 +
1449 +#ifndef _bcmenetmib_h_
1450 +#define _bcmenetmib_h_
1451 +
1452 +/* cpp contortions to concatenate w/arg prescan */
1453 +#ifndef PAD
1454 +#define _PADLINE(line) pad ## line
1455 +#define _XSTR(line) _PADLINE(line)
1456 +#define PAD _XSTR(__LINE__)
1457 +#endif /* PAD */
1458 +
1459 +/*
1460 + * EMAC MIB Registers
1461 + */
1462 +typedef volatile struct {
1463 + uint32 tx_good_octets;
1464 + uint32 tx_good_pkts;
1465 + uint32 tx_octets;
1466 + uint32 tx_pkts;
1467 + uint32 tx_broadcast_pkts;
1468 + uint32 tx_multicast_pkts;
1469 + uint32 tx_len_64;
1470 + uint32 tx_len_65_to_127;
1471 + uint32 tx_len_128_to_255;
1472 + uint32 tx_len_256_to_511;
1473 + uint32 tx_len_512_to_1023;
1474 + uint32 tx_len_1024_to_max;
1475 + uint32 tx_jabber_pkts;
1476 + uint32 tx_oversize_pkts;
1477 + uint32 tx_fragment_pkts;
1478 + uint32 tx_underruns;
1479 + uint32 tx_total_cols;
1480 + uint32 tx_single_cols;
1481 + uint32 tx_multiple_cols;
1482 + uint32 tx_excessive_cols;
1483 + uint32 tx_late_cols;
1484 + uint32 tx_defered;
1485 + uint32 tx_carrier_lost;
1486 + uint32 tx_pause_pkts;
1487 + uint32 PAD[8];
1488 +
1489 + uint32 rx_good_octets;
1490 + uint32 rx_good_pkts;
1491 + uint32 rx_octets;
1492 + uint32 rx_pkts;
1493 + uint32 rx_broadcast_pkts;
1494 + uint32 rx_multicast_pkts;
1495 + uint32 rx_len_64;
1496 + uint32 rx_len_65_to_127;
1497 + uint32 rx_len_128_to_255;
1498 + uint32 rx_len_256_to_511;
1499 + uint32 rx_len_512_to_1023;
1500 + uint32 rx_len_1024_to_max;
1501 + uint32 rx_jabber_pkts;
1502 + uint32 rx_oversize_pkts;
1503 + uint32 rx_fragment_pkts;
1504 + uint32 rx_missed_pkts;
1505 + uint32 rx_crc_align_errs;
1506 + uint32 rx_undersize;
1507 + uint32 rx_crc_errs;
1508 + uint32 rx_align_errs;
1509 + uint32 rx_symbol_errs;
1510 + uint32 rx_pause_pkts;
1511 + uint32 rx_nonpause_pkts;
1512 +} bcmenetmib_t;
1513 +
1514 +#endif /* _bcmenetmib_h_ */
1515 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenetphy.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetphy.h
1516 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
1517 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetphy.h 2005-12-16 23:39:10.700821500 +0100
1518 @@ -0,0 +1,58 @@
1519 +/*
1520 + * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
1521 + *
1522 + * Copyright 2005, Broadcom Corporation
1523 + * All Rights Reserved.
1524 + *
1525 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1526 + * the contents of this file may not be disclosed to third parties, copied
1527 + * or duplicated in any form, in whole or in part, without the prior
1528 + * written permission of Broadcom Corporation.
1529 + * $Id$
1530 + */
1531 +
1532 +#ifndef _bcmenetphy_h_
1533 +#define _bcmenetphy_h_
1534 +
1535 +/* phy address */
1536 +#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
1537 +#define EPHY_MASK 0x1f
1538 +#define EPHY_NONE 31 /* nvram: no phy present at all */
1539 +#define EPHY_NOREG 30 /* nvram: no local phy regs */
1540 +
1541 +/* just a few phy registers */
1542 +#define CTL_RESET (1 << 15) /* reset */
1543 +#define CTL_LOOP (1 << 14) /* loopback */
1544 +#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
1545 +#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
1546 +#define CTL_RESTART (1 << 9) /* restart autonegotiation */
1547 +#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
1548 +
1549 +#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
1550 +#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
1551 +#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
1552 +#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
1553 +
1554 +/* link partner ability register */
1555 +#define LPA_SLCT 0x001f /* same as advertise selector */
1556 +#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
1557 +#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
1558 +#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
1559 +#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
1560 +#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
1561 +#define LPA_RESV 0x1c00 /* unused */
1562 +#define LPA_RFAULT 0x2000 /* link partner faulted */
1563 +#define LPA_LPACK 0x4000 /* link partner acked us */
1564 +#define LPA_NPAGE 0x8000 /* next page bit */
1565 +
1566 +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
1567 +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
1568 +
1569 +#define STAT_REMFAULT (1 << 4) /* remote fault */
1570 +#define STAT_LINK (1 << 2) /* link status */
1571 +#define STAT_JAB (1 << 1) /* jabber detected */
1572 +#define AUX_FORCED (1 << 2) /* forced 10/100 */
1573 +#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
1574 +#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
1575 +
1576 +#endif /* _bcmenetphy_h_ */
1577 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenetrxh.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h
1578 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
1579 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-12-16 23:39:10.700821500 +0100
1580 @@ -0,0 +1,43 @@
1581 +/*
1582 + * Hardware-specific Receive Data Header for the
1583 + * Broadcom Home Networking Division
1584 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1585 + *
1586 + * Copyright 2005, Broadcom Corporation
1587 + * All Rights Reserved.
1588 + *
1589 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1590 + * the contents of this file may not be disclosed to third parties, copied
1591 + * or duplicated in any form, in whole or in part, without the prior
1592 + * written permission of Broadcom Corporation.
1593 + * $Id$
1594 + */
1595 +
1596 +#ifndef _bcmenetrxh_h_
1597 +#define _bcmenetrxh_h_
1598 +
1599 +/*
1600 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
1601 + * with every frame consisting of
1602 + * 16bits of frame length, followed by
1603 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
1604 + */
1605 +typedef volatile struct {
1606 + uint16 len;
1607 + uint16 flags;
1608 + uint16 pad[12];
1609 +} bcmenetrxh_t;
1610 +
1611 +#define RXHDR_LEN 28
1612 +
1613 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
1614 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
1615 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
1616 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
1617 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
1618 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
1619 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
1620 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
1621 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
1622 +
1623 +#endif /* _bcmenetrxh_h_ */
1624 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmnvram.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmnvram.h
1625 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1626 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmnvram.h 2005-12-16 23:39:10.700821500 +0100
1627 @@ -0,0 +1,141 @@
1628 +/*
1629 + * NVRAM variable manipulation
1630 + *
1631 + * Copyright 2005, Broadcom Corporation
1632 + * All Rights Reserved.
1633 + *
1634 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1635 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1636 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1637 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1638 + *
1639 + * $Id$
1640 + */
1641 +
1642 +#ifndef _bcmnvram_h_
1643 +#define _bcmnvram_h_
1644 +
1645 +#ifndef _LANGUAGE_ASSEMBLY
1646 +
1647 +#include <typedefs.h>
1648 +
1649 +struct nvram_header {
1650 + uint32 magic;
1651 + uint32 len;
1652 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
1653 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
1654 + uint32 config_ncdl; /* ncdl values for memc */
1655 +};
1656 +
1657 +struct nvram_tuple {
1658 + char *name;
1659 + char *value;
1660 + struct nvram_tuple *next;
1661 +};
1662 +
1663 +/*
1664 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1665 + * platforms.
1666 + */
1667 +extern int BCMINIT(nvram_init)(void *sbh);
1668 +
1669 +/*
1670 + * Disable NVRAM access. May be unnecessary or undefined on certain
1671 + * platforms.
1672 + */
1673 +extern void BCMINIT(nvram_exit)(void *sbh);
1674 +
1675 +/*
1676 + * Get the value of an NVRAM variable. The pointer returned may be
1677 + * invalid after a set.
1678 + * @param name name of variable to get
1679 + * @return value of variable or NULL if undefined
1680 + */
1681 +extern char * BCMINIT(nvram_get)(const char *name);
1682 +
1683 +/*
1684 + * Read the reset GPIO value from the nvram and set the GPIO
1685 + * as input
1686 + */
1687 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
1688 +
1689 +/*
1690 + * Get the value of an NVRAM variable.
1691 + * @param name name of variable to get
1692 + * @return value of variable or NUL if undefined
1693 + */
1694 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1695 +
1696 +/*
1697 + * Match an NVRAM variable.
1698 + * @param name name of variable to match
1699 + * @param match value to compare against value of variable
1700 + * @return TRUE if variable is defined and its value is string equal
1701 + * to match or FALSE otherwise
1702 + */
1703 +static INLINE int
1704 +nvram_match(char *name, char *match) {
1705 + const char *value = BCMINIT(nvram_get)(name);
1706 + return (value && !strcmp(value, match));
1707 +}
1708 +
1709 +/*
1710 + * Inversely match an NVRAM variable.
1711 + * @param name name of variable to match
1712 + * @param match value to compare against value of variable
1713 + * @return TRUE if variable is defined and its value is not string
1714 + * equal to invmatch or FALSE otherwise
1715 + */
1716 +static INLINE int
1717 +nvram_invmatch(char *name, char *invmatch) {
1718 + const char *value = BCMINIT(nvram_get)(name);
1719 + return (value && strcmp(value, invmatch));
1720 +}
1721 +
1722 +/*
1723 + * Set the value of an NVRAM variable. The name and value strings are
1724 + * copied into private storage. Pointers to previously set values
1725 + * may become invalid. The new value may be immediately
1726 + * retrieved but will not be permanently stored until a commit.
1727 + * @param name name of variable to set
1728 + * @param value value of variable
1729 + * @return 0 on success and errno on failure
1730 + */
1731 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1732 +
1733 +/*
1734 + * Unset an NVRAM variable. Pointers to previously set values
1735 + * remain valid until a set.
1736 + * @param name name of variable to unset
1737 + * @return 0 on success and errno on failure
1738 + * NOTE: use nvram_commit to commit this change to flash.
1739 + */
1740 +extern int BCMINIT(nvram_unset)(const char *name);
1741 +
1742 +/*
1743 + * Commit NVRAM variables to permanent storage. All pointers to values
1744 + * may be invalid after a commit.
1745 + * NVRAM values are undefined after a commit.
1746 + * @return 0 on success and errno on failure
1747 + */
1748 +extern int BCMINIT(nvram_commit)(void);
1749 +
1750 +/*
1751 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1752 + * @param buf buffer to store variables
1753 + * @param count size of buffer in bytes
1754 + * @return 0 on success and errno on failure
1755 + */
1756 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1757 +
1758 +#endif /* _LANGUAGE_ASSEMBLY */
1759 +
1760 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1761 +#define NVRAM_VERSION 1
1762 +#define NVRAM_HEADER_SIZE 20
1763 +#define NVRAM_SPACE 0x8000
1764 +
1765 +#define NVRAM_MAX_VALUE_LEN 255
1766 +#define NVRAM_MAX_PARAM_LEN 64
1767 +
1768 +#endif /* _bcmnvram_h_ */
1769 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmparams.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmparams.h
1770 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
1771 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmparams.h 2005-12-16 23:39:10.700821500 +0100
1772 @@ -0,0 +1,25 @@
1773 +/*
1774 + * Misc system wide parameters.
1775 + *
1776 + * Copyright 2005, Broadcom Corporation
1777 + * All Rights Reserved.
1778 + *
1779 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1780 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1781 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1782 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1783 + * $Id$
1784 + */
1785 +
1786 +#ifndef _bcmparams_h_
1787 +#define _bcmparams_h_
1788 +
1789 +#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
1790 +
1791 +#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
1792 +
1793 +#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
1794 +
1795 +#define WL_MAXBSSCFG 16 /* maximum number of BSS Configs we can configure */
1796 +
1797 +#endif
1798 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmsrom.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmsrom.h
1799 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1800 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmsrom.h 2005-12-16 23:39:10.704821750 +0100
1801 @@ -0,0 +1,23 @@
1802 +/*
1803 + * Misc useful routines to access NIC local SROM/OTP .
1804 + *
1805 + * Copyright 2005, Broadcom Corporation
1806 + * All Rights Reserved.
1807 + *
1808 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1809 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1810 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1811 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1812 + *
1813 + * $Id$
1814 + */
1815 +
1816 +#ifndef _bcmsrom_h_
1817 +#define _bcmsrom_h_
1818 +
1819 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
1820 +
1821 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1822 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1823 +
1824 +#endif /* _bcmsrom_h_ */
1825 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmutils.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmutils.h
1826 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1827 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmutils.h 2005-12-16 23:39:10.704821750 +0100
1828 @@ -0,0 +1,313 @@
1829 +/*
1830 + * Misc useful os-independent macros and functions.
1831 + *
1832 + * Copyright 2005, Broadcom Corporation
1833 + * All Rights Reserved.
1834 + *
1835 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1836 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1837 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1838 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1839 + * $Id$
1840 + */
1841 +
1842 +#ifndef _bcmutils_h_
1843 +#define _bcmutils_h_
1844 +
1845 +/*** driver-only section ***/
1846 +#ifdef BCMDRIVER
1847 +#include <osl.h>
1848 +
1849 +#define _BCM_U 0x01 /* upper */
1850 +#define _BCM_L 0x02 /* lower */
1851 +#define _BCM_D 0x04 /* digit */
1852 +#define _BCM_C 0x08 /* cntrl */
1853 +#define _BCM_P 0x10 /* punct */
1854 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1855 +#define _BCM_X 0x40 /* hex digit */
1856 +#define _BCM_SP 0x80 /* hard space (0x20) */
1857 +
1858 +#define GPIO_PIN_NOTDEFINED 0x20
1859 +
1860 +extern unsigned char bcm_ctype[];
1861 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1862 +
1863 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1864 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1865 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1866 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1867 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1868 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1869 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1870 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1871 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1872 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1873 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1874 +
1875 +/*
1876 + * Spin at most 'us' microseconds while 'exp' is true.
1877 + * Caller should explicitly test 'exp' when this completes
1878 + * and take appropriate error action if 'exp' is still true.
1879 + */
1880 +#define SPINWAIT(exp, us) { \
1881 + uint countdown = (us) + 9; \
1882 + while ((exp) && (countdown >= 10)) {\
1883 + OSL_DELAY(10); \
1884 + countdown -= 10; \
1885 + } \
1886 +}
1887 +
1888 +/* generic osl packet queue */
1889 +struct pktq {
1890 + void *head; /* first packet to dequeue */
1891 + void *tail; /* last packet to dequeue */
1892 + uint len; /* number of queued packets */
1893 + uint maxlen; /* maximum number of queued packets */
1894 + bool priority; /* enqueue by packet priority */
1895 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1896 +};
1897 +#define DEFAULT_QLEN 128
1898 +
1899 +#define pktq_len(q) ((q)->len)
1900 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1901 +#define pktq_head(q) ((q)->head)
1902 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1903 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1904 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1905 +
1906 +/* externs */
1907 +/* packet */
1908 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
1909 +extern uint pkttotlen(osl_t *osh, void *);
1910 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1911 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1912 +extern void *pktdeq(struct pktq *q);
1913 +extern void *pktdeqtail(struct pktq *q);
1914 +/* string */
1915 +extern uint bcm_atoi(char *s);
1916 +extern uchar bcm_toupper(uchar c);
1917 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1918 +extern char *bcmstrstr(char *haystack, char *needle);
1919 +extern char *bcmstrcat(char *dest, const char *src);
1920 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1921 +/* ethernet address */
1922 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1923 +extern int bcm_ether_atoe(char *p, char *ea);
1924 +/* delay */
1925 +extern void bcm_mdelay(uint ms);
1926 +/* variable access */
1927 +extern char *getvar(char *vars, char *name);
1928 +extern int getintvar(char *vars, char *name);
1929 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1930 +#define bcmlog(fmt, a1, a2)
1931 +#define bcmdumplog(buf, size) *buf = '\0'
1932 +#define bcmdumplogent(buf, idx) -1
1933 +
1934 +#endif /* #ifdef BCMDRIVER */
1935 +
1936 +/*** driver/apps-shared section ***/
1937 +
1938 +#define BCME_STRLEN 64
1939 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
1940 +
1941 +
1942 +/*
1943 + * error codes could be added but the defined ones shouldn't be changed/deleted
1944 + * these error codes are exposed to the user code
1945 + * when ever a new error code is added to this list
1946 + * please update errorstring table with the related error string and
1947 + * update osl files with os specific errorcode map
1948 +*/
1949 +
1950 +#define BCME_ERROR -1 /* Error generic */
1951 +#define BCME_BADARG -2 /* Bad Argument */
1952 +#define BCME_BADOPTION -3 /* Bad option */
1953 +#define BCME_NOTUP -4 /* Not up */
1954 +#define BCME_NOTDOWN -5 /* Not down */
1955 +#define BCME_NOTAP -6 /* Not AP */
1956 +#define BCME_NOTSTA -7 /* Not STA */
1957 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
1958 +#define BCME_RADIOOFF -9 /* Radio Off */
1959 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
1960 +#define BCME_NOCLK -11 /* No Clock*/
1961 +#define BCME_BADRATESET -12 /* BAD RateSet*/
1962 +#define BCME_BADBAND -13 /* BAD Band */
1963 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
1964 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
1965 +#define BCME_BUSY -16 /* Busy*/
1966 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
1967 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
1968 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
1969 +#define BCME_BADCHAN -20 /* BAD Channel */
1970 +#define BCME_BADADDR -21 /* BAD Address*/
1971 +#define BCME_NORESOURCE -22 /* No resources*/
1972 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
1973 +#define BCME_BADLEN -24 /* Bad Length*/
1974 +#define BCME_NOTREADY -25 /* Not ready Yet*/
1975 +#define BCME_EPERM -26 /* Not Permitted */
1976 +#define BCME_NOMEM -27 /* No Memory */
1977 +#define BCME_ASSOCIATED -28 /* Associated */
1978 +#define BCME_RANGE -29 /* Range Error*/
1979 +#define BCME_NOTFOUND -30 /* Not found */
1980 +#define BCME_LAST BCME_NOTFOUND
1981 +
1982 +#ifndef ABS
1983 +#define ABS(a) (((a)<0)?-(a):(a))
1984 +#endif
1985 +
1986 +#ifndef MIN
1987 +#define MIN(a, b) (((a)<(b))?(a):(b))
1988 +#endif
1989 +
1990 +#ifndef MAX
1991 +#define MAX(a, b) (((a)>(b))?(a):(b))
1992 +#endif
1993 +
1994 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1995 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1996 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1997 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1998 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
1999 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
2000 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
2001 +
2002 +/* bit map related macros */
2003 +#ifndef setbit
2004 +#define NBBY 8 /* 8 bits per byte */
2005 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
2006 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
2007 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
2008 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
2009 +#endif
2010 +
2011 +#define NBITS(type) (sizeof(type) * 8)
2012 +#define NBITVAL(bits) (1 << (bits))
2013 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
2014 +
2015 +/* crc defines */
2016 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
2017 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
2018 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
2019 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
2020 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
2021 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
2022 +
2023 +/* bcm_format_flags() bit description structure */
2024 +typedef struct bcm_bit_desc {
2025 + uint32 bit;
2026 + char* name;
2027 +} bcm_bit_desc_t;
2028 +
2029 +/* tag_ID/length/value_buffer tuple */
2030 +typedef struct bcm_tlv {
2031 + uint8 id;
2032 + uint8 len;
2033 + uint8 data[1];
2034 +} bcm_tlv_t;
2035 +
2036 +/* Check that bcm_tlv_t fits into the given buflen */
2037 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
2038 +
2039 +/* buffer length for ethernet address from bcm_ether_ntoa() */
2040 +#define ETHER_ADDR_STR_LEN 18
2041 +
2042 +/* unaligned load and store macros */
2043 +#ifdef IL_BIGENDIAN
2044 +static INLINE uint32
2045 +load32_ua(uint8 *a)
2046 +{
2047 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
2048 +}
2049 +
2050 +static INLINE void
2051 +store32_ua(uint8 *a, uint32 v)
2052 +{
2053 + a[0] = (v >> 24) & 0xff;
2054 + a[1] = (v >> 16) & 0xff;
2055 + a[2] = (v >> 8) & 0xff;
2056 + a[3] = v & 0xff;
2057 +}
2058 +
2059 +static INLINE uint16
2060 +load16_ua(uint8 *a)
2061 +{
2062 + return ((a[0] << 8) | a[1]);
2063 +}
2064 +
2065 +static INLINE void
2066 +store16_ua(uint8 *a, uint16 v)
2067 +{
2068 + a[0] = (v >> 8) & 0xff;
2069 + a[1] = v & 0xff;
2070 +}
2071 +
2072 +#else
2073 +
2074 +static INLINE uint32
2075 +load32_ua(uint8 *a)
2076 +{
2077 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
2078 +}
2079 +
2080 +static INLINE void
2081 +store32_ua(uint8 *a, uint32 v)
2082 +{
2083 + a[3] = (v >> 24) & 0xff;
2084 + a[2] = (v >> 16) & 0xff;
2085 + a[1] = (v >> 8) & 0xff;
2086 + a[0] = v & 0xff;
2087 +}
2088 +
2089 +static INLINE uint16
2090 +load16_ua(uint8 *a)
2091 +{
2092 + return ((a[1] << 8) | a[0]);
2093 +}
2094 +
2095 +static INLINE void
2096 +store16_ua(uint8 *a, uint16 v)
2097 +{
2098 + a[1] = (v >> 8) & 0xff;
2099 + a[0] = v & 0xff;
2100 +}
2101 +
2102 +#endif
2103 +
2104 +/* externs */
2105 +/* crc */
2106 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
2107 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
2108 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
2109 +/* format/print */
2110 +/* IE parsing */
2111 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
2112 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
2113 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
2114 +
2115 +/* bcmerror*/
2116 +extern const char *bcmerrorstr(int bcmerror);
2117 +
2118 +/* multi-bool data type: set of bools, mbool is true if any is set */
2119 +typedef uint32 mbool;
2120 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
2121 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
2122 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
2123 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
2124 +
2125 +/* power conversion */
2126 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
2127 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
2128 +
2129 +/* generic datastruct to help dump routines */
2130 +struct fielddesc {
2131 + char *nameandfmt;
2132 + uint32 offset;
2133 + uint32 len;
2134 +};
2135 +
2136 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
2137 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
2138 +
2139 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
2140 +
2141 +#endif /* _bcmutils_h_ */
2142 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bitfuncs.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bitfuncs.h
2143 --- linux-2.4.32/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
2144 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bitfuncs.h 2005-12-16 23:39:10.704821750 +0100
2145 @@ -0,0 +1,85 @@
2146 +/*
2147 + * bit manipulation utility functions
2148 + *
2149 + * Copyright 2005, Broadcom Corporation
2150 + * All Rights Reserved.
2151 + *
2152 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2153 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2154 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2155 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2156 + * $Id$
2157 + */
2158 +
2159 +#ifndef _BITFUNCS_H
2160 +#define _BITFUNCS_H
2161 +
2162 +#include <typedefs.h>
2163 +
2164 +/* local prototypes */
2165 +static INLINE uint32 find_msbit(uint32 x);
2166 +
2167 +
2168 +/*
2169 + * find_msbit: returns index of most significant set bit in x, with index
2170 + * range defined as 0-31. NOTE: returns zero if input is zero.
2171 + */
2172 +
2173 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
2174 +
2175 +/*
2176 + * Implementation for Pentium processors and gcc. Note that this
2177 + * instruction is actually very slow on some processors (e.g., family 5,
2178 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
2179 + * implementation instead.
2180 + */
2181 +static INLINE uint32 find_msbit(uint32 x)
2182 +{
2183 + uint msbit;
2184 + __asm__("bsrl %1,%0"
2185 + :"=r" (msbit)
2186 + :"r" (x));
2187 + return msbit;
2188 +}
2189 +
2190 +#else
2191 +
2192 +/*
2193 + * Generic Implementation
2194 + */
2195 +
2196 +#define DB_POW_MASK16 0xffff0000
2197 +#define DB_POW_MASK8 0x0000ff00
2198 +#define DB_POW_MASK4 0x000000f0
2199 +#define DB_POW_MASK2 0x0000000c
2200 +#define DB_POW_MASK1 0x00000002
2201 +
2202 +static INLINE uint32 find_msbit(uint32 x)
2203 +{
2204 + uint32 temp_x = x;
2205 + uint msbit = 0;
2206 + if (temp_x & DB_POW_MASK16) {
2207 + temp_x >>= 16;
2208 + msbit = 16;
2209 + }
2210 + if (temp_x & DB_POW_MASK8) {
2211 + temp_x >>= 8;
2212 + msbit += 8;
2213 + }
2214 + if (temp_x & DB_POW_MASK4) {
2215 + temp_x >>= 4;
2216 + msbit += 4;
2217 + }
2218 + if (temp_x & DB_POW_MASK2) {
2219 + temp_x >>= 2;
2220 + msbit += 2;
2221 + }
2222 + if (temp_x & DB_POW_MASK1) {
2223 + msbit += 1;
2224 + }
2225 + return(msbit);
2226 +}
2227 +
2228 +#endif
2229 +
2230 +#endif /* _BITFUNCS_H */
2231 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/cfe_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/cfe_osl.h
2232 --- linux-2.4.32/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
2233 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/cfe_osl.h 2005-12-16 23:39:10.704821750 +0100
2234 @@ -0,0 +1,191 @@
2235 +/*
2236 + * CFE boot loader OS Abstraction Layer.
2237 + *
2238 + * Copyright 2005, Broadcom Corporation
2239 + * All Rights Reserved.
2240 + *
2241 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
2242 + * the contents of this file may not be disclosed to third parties, copied
2243 + * or duplicated in any form, in whole or in part, without the prior
2244 + * written permission of Broadcom Corporation.
2245 + *
2246 + * $Id$
2247 + */
2248 +
2249 +#ifndef _cfe_osl_h_
2250 +#define _cfe_osl_h_
2251 +
2252 +#include <lib_types.h>
2253 +#include <lib_string.h>
2254 +#include <lib_printf.h>
2255 +#include <lib_malloc.h>
2256 +#include <cpu_config.h>
2257 +#include <cfe_timer.h>
2258 +#include <cfe_iocb.h>
2259 +#include <cfe_devfuncs.h>
2260 +#include <addrspace.h>
2261 +
2262 +#include <typedefs.h>
2263 +
2264 +/* dump string */
2265 +extern int (*xprinthook)(const char *str);
2266 +#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
2267 +
2268 +/* assert and panic */
2269 +#define ASSERT(exp) do {} while (0)
2270 +
2271 +/* PCMCIA attribute space access macros */
2272 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2273 + bzero(buf, size)
2274 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2275 + do {} while (0)
2276 +
2277 +/* PCI configuration space access macros */
2278 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
2279 + (offset == 8 ? 0 : 0xffffffff)
2280 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
2281 + do {} while (0)
2282 +
2283 +/* PCI device bus # and slot # */
2284 +#define OSL_PCI_BUS(osh) (0)
2285 +#define OSL_PCI_SLOT(osh) (0)
2286 +
2287 +/* register access macros */
2288 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
2289 +#define rreg32(r) (*(volatile uint32*)(r))
2290 +#ifdef IL_BIGENDIAN
2291 +#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
2292 +#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
2293 +#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
2294 +#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
2295 +#else
2296 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
2297 +#define rreg16(r) (*(volatile uint16*)(r))
2298 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
2299 +#define rreg8(r) (*(volatile uint8*)(r))
2300 +#endif
2301 +#define R_REG(r) ({ \
2302 + __typeof(*(r)) __osl_v; \
2303 + switch (sizeof(*(r))) { \
2304 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
2305 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
2306 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
2307 + } \
2308 + __osl_v; \
2309 +})
2310 +#define W_REG(r, v) do { \
2311 + switch (sizeof(*(r))) { \
2312 + case sizeof(uint8): wreg8((r), (v)); break; \
2313 + case sizeof(uint16): wreg16((r), (v)); break; \
2314 + case sizeof(uint32): wreg32((r), (v)); break; \
2315 + } \
2316 +} while (0)
2317 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2318 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2319 +
2320 +/* bcopy, bcmp, and bzero */
2321 +#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
2322 +
2323 +#define osl_attach(pdev) ((osl_t*)pdev)
2324 +#define osl_detach(osh)
2325 +
2326 +/* general purpose memory allocation */
2327 +#define MALLOC(osh, size) KMALLOC((size),0)
2328 +#define MFREE(osh, addr, size) KFREE((addr))
2329 +#define MALLOCED(osh) (0)
2330 +#define MALLOC_DUMP(osh, buf, sz)
2331 +#define MALLOC_FAILED(osh) (0)
2332 +
2333 +/* uncached virtual address */
2334 +#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
2335 +
2336 +/* host/bus architecture-specific address byte swap */
2337 +#define BUS_SWAP32(v) (v)
2338 +
2339 +/* get processor cycle count */
2340 +#define OSL_GETCYCLES(x) ((x) = 0)
2341 +
2342 +/* microsecond delay */
2343 +#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
2344 +
2345 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
2346 +
2347 +/* map/unmap physical to virtual I/O */
2348 +#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
2349 +#define REG_UNMAP(va) do {} while (0)
2350 +
2351 +/* dereference an address that may cause a bus exception */
2352 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
2353 +extern int osl_busprobe(uint32 *val, uint32 addr);
2354 +
2355 +/* allocate/free shared (dma-able) consistent (uncached) memory */
2356 +#define DMA_CONSISTENT_ALIGN 4096
2357 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2358 + osl_dma_alloc_consistent((size), (pap))
2359 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2360 + osl_dma_free_consistent((void*)(va))
2361 +extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
2362 +extern void osl_dma_free_consistent(void *va);
2363 +
2364 +/* map/unmap direction */
2365 +#define DMA_TX 1
2366 +#define DMA_RX 2
2367 +
2368 +/* map/unmap shared (dma-able) memory */
2369 +#define DMA_MAP(osh, va, size, direction, lb) ({ \
2370 + cfe_flushcache(CFE_CACHE_FLUSH_D); \
2371 + PHYSADDR((ulong)(va)); \
2372 +})
2373 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2374 + do {} while (0)
2375 +
2376 +/* shared (dma-able) memory access macros */
2377 +#define R_SM(r) *(r)
2378 +#define W_SM(r, v) (*(r) = (v))
2379 +#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
2380 +
2381 +/* generic packet structure */
2382 +#define LBUFSZ 4096
2383 +#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
2384 +struct lbuf {
2385 + struct lbuf *next; /* pointer to next lbuf if in a chain */
2386 + struct lbuf *link; /* pointer to next lbuf if in a list */
2387 + uchar *head; /* start of buffer */
2388 + uchar *end; /* end of buffer */
2389 + uchar *data; /* start of data */
2390 + uchar *tail; /* end of data */
2391 + uint len; /* nbytes of data */
2392 + void *cookie; /* generic cookie */
2393 +};
2394 +
2395 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2396 +#define PKTBUFSZ 2048
2397 +
2398 +/* packet primitives */
2399 +#define PKTGET(osh, len, send) ((void*)osl_pktget((len)))
2400 +#define PKTFREE(osh, lb, send) osl_pktfree((struct lbuf*)(lb))
2401 +#define PKTDATA(osh, lb) (((struct lbuf*)(lb))->data)
2402 +#define PKTLEN(osh, lb) (((struct lbuf*)(lb))->len)
2403 +#define PKTHEADROOM(osh, lb) (PKTDATA(osh,lb)-(((struct lbuf*)(lb))->head))
2404 +#define PKTTAILROOM(osh, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
2405 +#define PKTNEXT(osh, lb) (((struct lbuf*)(lb))->next)
2406 +#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
2407 +#define PKTSETLEN(osh, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
2408 +#define PKTPUSH(osh, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
2409 +#define PKTPULL(osh, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
2410 +#define PKTDUP(osh, lb) osl_pktdup((struct lbuf*)(lb))
2411 +#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
2412 +#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
2413 +#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
2414 +#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
2415 +#define PKTPRIO(lb) (0)
2416 +#define PKTSETPRIO(lb, x) do {} while (0)
2417 +extern struct lbuf *osl_pktget(uint len);
2418 +extern void osl_pktfree(struct lbuf *lb);
2419 +extern void osl_pktsetlen(struct lbuf *lb, uint len);
2420 +extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
2421 +extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
2422 +extern struct lbuf *osl_pktdup(struct lbuf *lb);
2423 +extern int osl_error(int bcmerror);
2424 +
2425 +#endif /* _cfe_osl_h_ */
2426 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/epivers.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h
2427 --- linux-2.4.32/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
2428 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h 2005-12-16 23:39:10.704821750 +0100
2429 @@ -0,0 +1,69 @@
2430 +/*
2431 + * Copyright 2005, Broadcom Corporation
2432 + * All Rights Reserved.
2433 + *
2434 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2435 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2436 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2437 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2438 + *
2439 + * $Id$
2440 + *
2441 +*/
2442 +
2443 +#ifndef _epivers_h_
2444 +#define _epivers_h_
2445 +
2446 +#ifdef linux
2447 +#include <linux/config.h>
2448 +#endif
2449 +
2450 +/* Vendor Name, ASCII, 32 chars max */
2451 +#ifdef COMPANYNAME
2452 +#define HPNA_VENDOR COMPANYNAME
2453 +#else
2454 +#define HPNA_VENDOR "Broadcom Corporation"
2455 +#endif
2456 +
2457 +/* Driver Date, ASCII, 32 chars max */
2458 +#define HPNA_DRV_BUILD_DATE __DATE__
2459 +
2460 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2461 +#define HPNA_HW_MFG_DATE "Not Specified"
2462 +
2463 +/* See documentation for Device Type values, 32 values max */
2464 +#ifndef HPNA_DEV_TYPE
2465 +
2466 +#if defined(CONFIG_BRCM_VJ)
2467 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2468 +
2469 +#elif defined(CONFIG_BCRM_93725)
2470 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2471 +
2472 +#else
2473 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2474 +
2475 +#endif
2476 +
2477 +#endif /* !HPNA_DEV_TYPE */
2478 +
2479 +
2480 +#define EPI_MAJOR_VERSION 3
2481 +
2482 +#define EPI_MINOR_VERSION 130
2483 +
2484 +#define EPI_RC_NUMBER 20
2485 +
2486 +#define EPI_INCREMENTAL_NUMBER 0
2487 +
2488 +#define EPI_BUILD_NUMBER 0
2489 +
2490 +#define EPI_VERSION 3,130,20,0
2491 +
2492 +#define EPI_VERSION_NUM 0x03821400
2493 +
2494 +/* Driver Version String, ASCII, 32 chars max */
2495 +#define EPI_VERSION_STR "3.130.20.0"
2496 +#define EPI_ROUTER_VERSION_STR "3.131.20.0"
2497 +
2498 +#endif /* _epivers_h_ */
2499 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/epivers.h.in linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h.in
2500 --- linux-2.4.32/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
2501 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h.in 2005-12-16 23:39:10.704821750 +0100
2502 @@ -0,0 +1,69 @@
2503 +/*
2504 + * Copyright 2005, Broadcom Corporation
2505 + * All Rights Reserved.
2506 + *
2507 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2508 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2509 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2510 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2511 + *
2512 + * $Id$
2513 + *
2514 +*/
2515 +
2516 +#ifndef _epivers_h_
2517 +#define _epivers_h_
2518 +
2519 +#ifdef linux
2520 +#include <linux/config.h>
2521 +#endif
2522 +
2523 +/* Vendor Name, ASCII, 32 chars max */
2524 +#ifdef COMPANYNAME
2525 +#define HPNA_VENDOR COMPANYNAME
2526 +#else
2527 +#define HPNA_VENDOR "Broadcom Corporation"
2528 +#endif
2529 +
2530 +/* Driver Date, ASCII, 32 chars max */
2531 +#define HPNA_DRV_BUILD_DATE __DATE__
2532 +
2533 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2534 +#define HPNA_HW_MFG_DATE "Not Specified"
2535 +
2536 +/* See documentation for Device Type values, 32 values max */
2537 +#ifndef HPNA_DEV_TYPE
2538 +
2539 +#if defined(CONFIG_BRCM_VJ)
2540 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2541 +
2542 +#elif defined(CONFIG_BCRM_93725)
2543 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2544 +
2545 +#else
2546 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2547 +
2548 +#endif
2549 +
2550 +#endif /* !HPNA_DEV_TYPE */
2551 +
2552 +
2553 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
2554 +
2555 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
2556 +
2557 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
2558 +
2559 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
2560 +
2561 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
2562 +
2563 +#define EPI_VERSION @EPI_VERSION@
2564 +
2565 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
2566 +
2567 +/* Driver Version String, ASCII, 32 chars max */
2568 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
2569 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
2570 +
2571 +#endif /* _epivers_h_ */
2572 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/etsockio.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/etsockio.h
2573 --- linux-2.4.32/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
2574 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/etsockio.h 2005-12-16 23:39:10.704821750 +0100
2575 @@ -0,0 +1,59 @@
2576 +/*
2577 + * Driver-specific socket ioctls
2578 + * used by BSD, Linux, and PSOS
2579 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
2580 + *
2581 + * Copyright 2005, Broadcom Corporation
2582 + * All Rights Reserved.
2583 + *
2584 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2585 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2586 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2587 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2588 + *
2589 + * $Id$
2590 + */
2591 +
2592 +#ifndef _etsockio_h_
2593 +#define _etsockio_h_
2594 +
2595 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
2596 +
2597 +
2598 +#if defined(linux)
2599 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
2600 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
2601 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
2602 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
2603 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
2604 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
2605 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
2606 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
2607 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
2608 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
2609 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
2610 +#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
2611 +
2612 +#else /* !linux */
2613 +
2614 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
2615 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
2616 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
2617 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
2618 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
2619 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
2620 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
2621 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
2622 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
2623 +
2624 +#endif
2625 +
2626 +/* arg to SIOCTXGEN */
2627 +struct txg {
2628 + uint32 num; /* number of frames to send */
2629 + uint32 delay; /* delay in microseconds between sending each */
2630 + uint32 size; /* size of ether frame to send */
2631 + uchar buf[1514]; /* starting ether frame data */
2632 +};
2633 +
2634 +#endif
2635 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/flash.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/flash.h
2636 --- linux-2.4.32/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
2637 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/flash.h 2005-12-16 23:39:10.704821750 +0100
2638 @@ -0,0 +1,188 @@
2639 +/*
2640 + * flash.h: Common definitions for flash access.
2641 + *
2642 + * Copyright 2005, Broadcom Corporation
2643 + * All Rights Reserved.
2644 + *
2645 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2646 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2647 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2648 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2649 + *
2650 + * $Id$
2651 + */
2652 +
2653 +/* Types of flashes we know about */
2654 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
2655 +
2656 +/* Commands to write/erase the flases */
2657 +typedef struct _flash_cmds{
2658 + flash_type_t type;
2659 + bool need_unlock;
2660 + uint16 pre_erase;
2661 + uint16 erase_block;
2662 + uint16 erase_chip;
2663 + uint16 write_word;
2664 + uint16 write_buf;
2665 + uint16 clear_csr;
2666 + uint16 read_csr;
2667 + uint16 read_id;
2668 + uint16 confirm;
2669 + uint16 read_array;
2670 +} flash_cmds_t;
2671 +
2672 +#define UNLOCK_CMD_WORDS 2
2673 +
2674 +typedef struct _unlock_cmd {
2675 + uint addr[UNLOCK_CMD_WORDS];
2676 + uint16 cmd[UNLOCK_CMD_WORDS];
2677 +} unlock_cmd_t;
2678 +
2679 +/* Flash descriptors */
2680 +typedef struct _flash_desc {
2681 + uint16 mfgid; /* Manufacturer Id */
2682 + uint16 devid; /* Device Id */
2683 + uint size; /* Total size in bytes */
2684 + uint width; /* Device width in bytes */
2685 + flash_type_t type; /* Device type old, S, J */
2686 + uint bsize; /* Block size */
2687 + uint nb; /* Number of blocks */
2688 + uint ff; /* First full block */
2689 + uint lf; /* Last full block */
2690 + uint nsub; /* Number of subblocks */
2691 + uint *subblocks; /* Offsets for subblocks */
2692 + char *desc; /* Description */
2693 +} flash_desc_t;
2694 +
2695 +
2696 +#ifdef DECLARE_FLASHES
2697 +flash_cmds_t sflash_cmd_t =
2698 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2699 +
2700 +flash_cmds_t flash_cmds[] = {
2701 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
2702 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
2703 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
2704 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2705 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2706 + { 0 }
2707 +};
2708 +
2709 +unlock_cmd_t unlock_cmd_amd = {
2710 +#ifdef MIPSEB
2711 +/* addr: */ { 0x0aa8, 0x0556},
2712 +#else
2713 +/* addr: */ { 0x0aaa, 0x0554},
2714 +#endif
2715 +/* data: */ { 0xaa, 0x55}
2716 +};
2717 +
2718 +unlock_cmd_t unlock_cmd_sst = {
2719 +#ifdef MIPSEB
2720 +/* addr: */ { 0xaaa8, 0x5556},
2721 +#else
2722 +/* addr: */ { 0xaaaa, 0x5554},
2723 +#endif
2724 +/* data: */ { 0xaa, 0x55}
2725 +};
2726 +
2727 +#define AMD_CMD 0xaaa
2728 +#define SST_CMD 0xaaaa
2729 +
2730 +/* intel unlock block cmds */
2731 +#define INTEL_UNLOCK1 0x60
2732 +#define INTEL_UNLOCK2 0xD0
2733 +
2734 +/* Just eight blocks of 8KB byte each */
2735 +
2736 +uint blk8x8k[] = { 0x00000000,
2737 + 0x00002000,
2738 + 0x00004000,
2739 + 0x00006000,
2740 + 0x00008000,
2741 + 0x0000a000,
2742 + 0x0000c000,
2743 + 0x0000e000,
2744 + 0x00010000
2745 +};
2746 +
2747 +/* Funky AMD arrangement for 29xx800's */
2748 +uint amd800[] = { 0x00000000, /* 16KB */
2749 + 0x00004000, /* 32KB */
2750 + 0x0000c000, /* 8KB */
2751 + 0x0000e000, /* 8KB */
2752 + 0x00010000, /* 8KB */
2753 + 0x00012000, /* 8KB */
2754 + 0x00014000, /* 32KB */
2755 + 0x0001c000, /* 16KB */
2756 + 0x00020000
2757 +};
2758 +
2759 +/* AMD arrangement for 29xx160's */
2760 +uint amd4112[] = { 0x00000000, /* 32KB */
2761 + 0x00008000, /* 8KB */
2762 + 0x0000a000, /* 8KB */
2763 + 0x0000c000, /* 16KB */
2764 + 0x00010000
2765 +};
2766 +uint amd2114[] = { 0x00000000, /* 16KB */
2767 + 0x00004000, /* 8KB */
2768 + 0x00006000, /* 8KB */
2769 + 0x00008000, /* 32KB */
2770 + 0x00010000
2771 +};
2772 +
2773 +
2774 +flash_desc_t sflash_desc =
2775 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
2776 +
2777 +flash_desc_t flashes[] = {
2778 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
2779 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
2780 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
2781 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
2782 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
2783 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
2784 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
2785 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
2786 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
2787 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
2788 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
2789 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
2790 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
2791 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
2792 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
2793 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
2794 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
2795 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
2796 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
2797 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
2798 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
2799 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
2800 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
2801 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
2802 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
2803 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
2804 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
2805 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
2806 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
2807 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
2808 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2809 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2810 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
2811 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
2812 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
2813 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
2814 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2815 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2816 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
2817 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
2818 +};
2819 +
2820 +#else
2821 +
2822 +extern flash_cmds_t flash_cmds[];
2823 +extern unlock_cmd_t unlock_cmd;
2824 +extern flash_desc_t flashes[];
2825 +
2826 +#endif
2827 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/flashutl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/flashutl.h
2828 --- linux-2.4.32/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
2829 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/flashutl.h 2005-12-16 23:39:10.708822000 +0100
2830 @@ -0,0 +1,27 @@
2831 +/*
2832 + * BCM47XX FLASH driver interface
2833 + *
2834 + * Copyright 2005, Broadcom Corporation
2835 + * All Rights Reserved.
2836 + *
2837 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2838 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2839 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2840 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2841 + * $Id$
2842 + */
2843 +
2844 +#ifndef _flashutl_h_
2845 +#define _flashutl_h_
2846 +
2847 +
2848 +#ifndef _LANGUAGE_ASSEMBLY
2849 +
2850 +int sysFlashInit(char *flash_str);
2851 +int sysFlashRead(uint off, uchar *dst, uint bytes);
2852 +int sysFlashWrite(uint off, uchar *src, uint bytes);
2853 +void nvWrite(unsigned short *data, unsigned int len);
2854 +
2855 +#endif /* _LANGUAGE_ASSEMBLY */
2856 +
2857 +#endif /* _flashutl_h_ */
2858 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/hnddma.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/hnddma.h
2859 --- linux-2.4.32/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
2860 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/hnddma.h 2005-12-16 23:39:10.708822000 +0100
2861 @@ -0,0 +1,71 @@
2862 +/*
2863 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
2864 + * This supports the following chips: BCM42xx, 44xx, 47xx .
2865 + *
2866 + * Copyright 2005, Broadcom Corporation
2867 + * All Rights Reserved.
2868 + *
2869 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2870 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2871 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2872 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2873 + * $Id$
2874 + */
2875 +
2876 +#ifndef _hnddma_h_
2877 +#define _hnddma_h_
2878 +
2879 +/* export structure */
2880 +typedef volatile struct {
2881 + /* rx error counters */
2882 + uint rxgiants; /* rx giant frames */
2883 + uint rxnobuf; /* rx out of dma descriptors */
2884 + /* tx error counters */
2885 + uint txnobuf; /* tx out of dma descriptors */
2886 +} hnddma_t;
2887 +
2888 +#ifndef di_t
2889 +#define di_t void
2890 +#endif
2891 +
2892 +#ifndef osl_t
2893 +#define osl_t void
2894 +#endif
2895 +
2896 +/* externs */
2897 +extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
2898 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
2899 +extern void dma_detach(di_t *di);
2900 +extern void dma_txreset(di_t *di);
2901 +extern void dma_rxreset(di_t *di);
2902 +extern void dma_txinit(di_t *di);
2903 +extern bool dma_txenabled(di_t *di);
2904 +extern void dma_rxinit(di_t *di);
2905 +extern void dma_rxenable(di_t *di);
2906 +extern bool dma_rxenabled(di_t *di);
2907 +extern void dma_txsuspend(di_t *di);
2908 +extern void dma_txresume(di_t *di);
2909 +extern bool dma_txsuspended(di_t *di);
2910 +extern bool dma_txsuspendedidle(di_t *di);
2911 +extern bool dma_txstopped(di_t *di);
2912 +extern bool dma_rxstopped(di_t *di);
2913 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
2914 +extern void dma_fifoloopbackenable(di_t *di);
2915 +extern void *dma_rx(di_t *di);
2916 +extern void dma_rxfill(di_t *di);
2917 +extern void dma_txreclaim(di_t *di, bool forceall);
2918 +extern void dma_rxreclaim(di_t *di);
2919 +extern uintptr dma_getvar(di_t *di, char *name);
2920 +extern void *dma_getnexttxp(di_t *di, bool forceall);
2921 +extern void *dma_peeknexttxp(di_t *di);
2922 +extern void *dma_getnextrxp(di_t *di, bool forceall);
2923 +extern void dma_txblock(di_t *di);
2924 +extern void dma_txunblock(di_t *di);
2925 +extern uint dma_txactive(di_t *di);
2926 +extern void dma_txrotate(di_t *di);
2927 +
2928 +extern void dma_rxpiomode(dma32regs_t *);
2929 +extern void dma_txpioloopback(dma32regs_t *);
2930 +
2931 +
2932 +#endif /* _hnddma_h_ */
2933 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/hndmips.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/hndmips.h
2934 --- linux-2.4.32/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
2935 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/hndmips.h 2005-12-16 23:39:10.708822000 +0100
2936 @@ -0,0 +1,16 @@
2937 +/*
2938 + * Alternate include file for HND sbmips.h since CFE also ships with
2939 + * a sbmips.h.
2940 + *
2941 + * Copyright 2005, Broadcom Corporation
2942 + * All Rights Reserved.
2943 + *
2944 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2945 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2946 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2947 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2948 + *
2949 + * $Id$
2950 + */
2951 +
2952 +#include "sbmips.h"
2953 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/linux_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/linux_osl.h
2954 --- linux-2.4.32/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
2955 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/linux_osl.h 2005-12-16 23:39:10.708822000 +0100
2956 @@ -0,0 +1,371 @@
2957 +/*
2958 + * Linux OS Independent Layer
2959 + *
2960 + * Copyright 2005, Broadcom Corporation
2961 + * All Rights Reserved.
2962 + *
2963 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2964 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2965 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2966 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2967 + *
2968 + * $Id$
2969 + */
2970 +
2971 +#ifndef _linux_osl_h_
2972 +#define _linux_osl_h_
2973 +
2974 +#include <typedefs.h>
2975 +
2976 +/* use current 2.4.x calling conventions */
2977 +#include <linuxver.h>
2978 +
2979 +/* assert and panic */
2980 +#ifdef __GNUC__
2981 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
2982 +#if GCC_VERSION > 30100
2983 +#define ASSERT(exp) do {} while (0)
2984 +#else
2985 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
2986 +#define ASSERT(exp)
2987 +#endif
2988 +#endif
2989 +
2990 +/* microsecond delay */
2991 +#define OSL_DELAY(usec) osl_delay(usec)
2992 +extern void osl_delay(uint usec);
2993 +
2994 +/* PCMCIA attribute space access macros */
2995 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2996 +struct pcmcia_dev {
2997 + dev_link_t link; /* PCMCIA device pointer */
2998 + dev_node_t node; /* PCMCIA node structure */
2999 + void *base; /* Mapped attribute memory window */
3000 + size_t size; /* Size of window */
3001 + void *drv; /* Driver data */
3002 +};
3003 +#endif
3004 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3005 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
3006 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3007 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
3008 +extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
3009 +extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
3010 +
3011 +/* PCI configuration space access macros */
3012 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
3013 + osl_pci_read_config((osh), (offset), (size))
3014 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
3015 + osl_pci_write_config((osh), (offset), (size), (val))
3016 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
3017 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
3018 +
3019 +/* PCI device bus # and slot # */
3020 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
3021 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
3022 +extern uint osl_pci_bus(osl_t *osh);
3023 +extern uint osl_pci_slot(osl_t *osh);
3024 +
3025 +/* OSL initialization */
3026 +extern osl_t *osl_attach(void *pdev);
3027 +extern void osl_detach(osl_t *osh);
3028 +
3029 +/* host/bus architecture-specific byte swap */
3030 +#define BUS_SWAP32(v) (v)
3031 +
3032 +/* general purpose memory allocation */
3033 +
3034 +#if defined(BCMDBG_MEM)
3035 +
3036 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
3037 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
3038 +#define MALLOCED(osh) osl_malloced((osh))
3039 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
3040 +extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
3041 +extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
3042 +extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
3043 +
3044 +#else
3045 +
3046 +#define MALLOC(osh, size) osl_malloc((osh), (size))
3047 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
3048 +#define MALLOCED(osh) osl_malloced((osh))
3049 +
3050 +#endif /* BCMDBG_MEM */
3051 +
3052 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
3053 +
3054 +extern void *osl_malloc(osl_t *osh, uint size);
3055 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
3056 +extern uint osl_malloced(osl_t *osh);
3057 +extern uint osl_malloc_failed(osl_t *osh);
3058 +
3059 +/* allocate/free shared (dma-able) consistent memory */
3060 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
3061 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
3062 + osl_dma_alloc_consistent((osh), (size), (pap))
3063 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
3064 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
3065 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
3066 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
3067 +
3068 +/* map/unmap direction */
3069 +#define DMA_TX 1
3070 +#define DMA_RX 2
3071 +
3072 +/* map/unmap shared (dma-able) memory */
3073 +#define DMA_MAP(osh, va, size, direction, p) \
3074 + osl_dma_map((osh), (va), (size), (direction))
3075 +#define DMA_UNMAP(osh, pa, size, direction, p) \
3076 + osl_dma_unmap((osh), (pa), (size), (direction))
3077 +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
3078 +extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
3079 +
3080 +/* register access macros */
3081 +#if defined(BCMJTAG)
3082 +#include <bcmjtag.h>
3083 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
3084 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
3085 +#endif
3086 +
3087 +/*
3088 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
3089 + * Macros expand to calls to functions defined in linux_osl.c .
3090 + */
3091 +#ifndef BINOSL
3092 +
3093 +/* string library, kernel mode */
3094 +#define printf(fmt, args...) printk(fmt, ## args)
3095 +#include <linux/kernel.h>
3096 +#include <linux/string.h>
3097 +
3098 +/* register access macros */
3099 +#if !defined(BCMJTAG)
3100 +#ifndef IL_BIGENDIAN
3101 +#define R_REG(r) ( \
3102 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
3103 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
3104 + readl((volatile uint32*)(r)) \
3105 +)
3106 +#define W_REG(r, v) do { \
3107 + switch (sizeof(*(r))) { \
3108 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
3109 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
3110 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3111 + } \
3112 +} while (0)
3113 +#else /* IL_BIGENDIAN */
3114 +#define R_REG(r) ({ \
3115 + __typeof(*(r)) __osl_v; \
3116 + switch (sizeof(*(r))) { \
3117 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
3118 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
3119 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
3120 + } \
3121 + __osl_v; \
3122 +})
3123 +#define W_REG(r, v) do { \
3124 + switch (sizeof(*(r))) { \
3125 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
3126 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
3127 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3128 + } \
3129 +} while (0)
3130 +#endif
3131 +#endif
3132 +
3133 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3134 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3135 +
3136 +/* bcopy, bcmp, and bzero */
3137 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3138 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3139 +#define bzero(b, len) memset((b), '\0', (len))
3140 +
3141 +/* uncached virtual address */
3142 +#ifdef mips
3143 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
3144 +#include <asm/addrspace.h>
3145 +#else
3146 +#define OSL_UNCACHED(va) (va)
3147 +#endif
3148 +
3149 +/* get processor cycle count */
3150 +#if defined(mips)
3151 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
3152 +#elif defined(__i386__)
3153 +#define OSL_GETCYCLES(x) rdtscl((x))
3154 +#else
3155 +#define OSL_GETCYCLES(x) ((x) = 0)
3156 +#endif
3157 +
3158 +/* dereference an address that may cause a bus exception */
3159 +#ifdef mips
3160 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
3161 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
3162 +#else
3163 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
3164 +#include <asm/paccess.h>
3165 +#endif
3166 +#else
3167 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
3168 +#endif
3169 +
3170 +/* map/unmap physical to virtual I/O */
3171 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
3172 +#define REG_UNMAP(va) iounmap((void *)(va))
3173 +
3174 +/* shared (dma-able) memory access macros */
3175 +#define R_SM(r) *(r)
3176 +#define W_SM(r, v) (*(r) = (v))
3177 +#define BZERO_SM(r, len) memset((r), '\0', (len))
3178 +
3179 +/* packet primitives */
3180 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3181 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3182 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
3183 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
3184 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
3185 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
3186 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
3187 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
3188 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
3189 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
3190 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
3191 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
3192 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
3193 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
3194 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
3195 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
3196 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
3197 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
3198 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3199 +extern void osl_pktfree(void *skb);
3200 +
3201 +#else /* BINOSL */
3202 +
3203 +/* string library */
3204 +#ifndef LINUX_OSL
3205 +#undef printf
3206 +#define printf(fmt, args...) osl_printf((fmt), ## args)
3207 +#undef sprintf
3208 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
3209 +#undef strcmp
3210 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
3211 +#undef strncmp
3212 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
3213 +#undef strlen
3214 +#define strlen(s) osl_strlen((s))
3215 +#undef strcpy
3216 +#define strcpy(d, s) osl_strcpy((d), (s))
3217 +#undef strncpy
3218 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
3219 +#endif
3220 +extern int osl_printf(const char *format, ...);
3221 +extern int osl_sprintf(char *buf, const char *format, ...);
3222 +extern int osl_strcmp(const char *s1, const char *s2);
3223 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
3224 +extern int osl_strlen(const char *s);
3225 +extern char* osl_strcpy(char *d, const char *s);
3226 +extern char* osl_strncpy(char *d, const char *s, uint n);
3227 +
3228 +/* register access macros */
3229 +#if !defined(BCMJTAG)
3230 +#define R_REG(r) ( \
3231 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
3232 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
3233 + osl_readl((volatile uint32*)(r)) \
3234 +)
3235 +#define W_REG(r, v) do { \
3236 + switch (sizeof(*(r))) { \
3237 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
3238 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
3239 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
3240 + } \
3241 +} while (0)
3242 +#endif
3243 +
3244 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3245 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3246 +extern uint8 osl_readb(volatile uint8 *r);
3247 +extern uint16 osl_readw(volatile uint16 *r);
3248 +extern uint32 osl_readl(volatile uint32 *r);
3249 +extern void osl_writeb(uint8 v, volatile uint8 *r);
3250 +extern void osl_writew(uint16 v, volatile uint16 *r);
3251 +extern void osl_writel(uint32 v, volatile uint32 *r);
3252 +
3253 +/* bcopy, bcmp, and bzero */
3254 +extern void bcopy(const void *src, void *dst, int len);
3255 +extern int bcmp(const void *b1, const void *b2, int len);
3256 +extern void bzero(void *b, int len);
3257 +
3258 +/* uncached virtual address */
3259 +#define OSL_UNCACHED(va) osl_uncached((va))
3260 +extern void *osl_uncached(void *va);
3261 +
3262 +/* get processor cycle count */
3263 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
3264 +extern uint osl_getcycles(void);
3265 +
3266 +/* dereference an address that may target abort */
3267 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
3268 +extern int osl_busprobe(uint32 *val, uint32 addr);
3269 +
3270 +/* map/unmap physical to virtual */
3271 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
3272 +#define REG_UNMAP(va) osl_reg_unmap((va))
3273 +extern void *osl_reg_map(uint32 pa, uint size);
3274 +extern void osl_reg_unmap(void *va);
3275 +
3276 +/* shared (dma-able) memory access macros */
3277 +#define R_SM(r) *(r)
3278 +#define W_SM(r, v) (*(r) = (v))
3279 +#define BZERO_SM(r, len) bzero((r), (len))
3280 +
3281 +/* packet primitives */
3282 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3283 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3284 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
3285 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
3286 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
3287 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
3288 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
3289 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
3290 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
3291 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
3292 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
3293 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
3294 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
3295 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
3296 +#define PKTLINK(skb) osl_pktlink((skb))
3297 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
3298 +#define PKTPRIO(skb) osl_pktprio((skb))
3299 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
3300 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3301 +extern void osl_pktfree(void *skb);
3302 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
3303 +extern uint osl_pktlen(osl_t *osh, void *skb);
3304 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
3305 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
3306 +extern void *osl_pktnext(osl_t *osh, void *skb);
3307 +extern void osl_pktsetnext(void *skb, void *x);
3308 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
3309 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
3310 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
3311 +extern void *osl_pktdup(osl_t *osh, void *skb);
3312 +extern void *osl_pktcookie(void *skb);
3313 +extern void osl_pktsetcookie(void *skb, void *x);
3314 +extern void *osl_pktlink(void *skb);
3315 +extern void osl_pktsetlink(void *skb, void *x);
3316 +extern uint osl_pktprio(void *skb);
3317 +extern void osl_pktsetprio(void *skb, uint x);
3318 +
3319 +#endif /* BINOSL */
3320 +
3321 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3322 +extern int osl_error(int bcmerror);
3323 +
3324 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
3325 +#define PKTBUFSZ 2048
3326 +
3327 +#endif /* _linux_osl_h_ */
3328 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/linuxver.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/linuxver.h
3329 --- linux-2.4.32/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
3330 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/linuxver.h 2005-12-16 23:39:10.748824500 +0100
3331 @@ -0,0 +1,411 @@
3332 +/*
3333 + * Linux-specific abstractions to gain some independence from linux kernel versions.
3334 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
3335 + *
3336 + * Copyright 2005, Broadcom Corporation
3337 + * All Rights Reserved.
3338 + *
3339 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3340 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3341 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3342 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3343 + *
3344 + * $Id$
3345 + */
3346 +
3347 +#ifndef _linuxver_h_
3348 +#define _linuxver_h_
3349 +
3350 +#include <linux/config.h>
3351 +#include <linux/version.h>
3352 +
3353 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
3354 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
3355 +#ifdef __UNDEF_NO_VERSION__
3356 +#undef __NO_VERSION__
3357 +#else
3358 +#define __NO_VERSION__
3359 +#endif
3360 +#endif
3361 +
3362 +#if defined(MODULE) && defined(MODVERSIONS)
3363 +#include <linux/modversions.h>
3364 +#endif
3365 +
3366 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
3367 +#include <linux/moduleparam.h>
3368 +#endif
3369 +
3370 +
3371 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3372 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
3373 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
3374 +#endif
3375 +
3376 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
3377 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
3378 +#include <linux/malloc.h>
3379 +#else
3380 +#include <linux/slab.h>
3381 +#endif
3382 +
3383 +#include <linux/types.h>
3384 +#include <linux/init.h>
3385 +#include <linux/mm.h>
3386 +#include <linux/string.h>
3387 +#include <linux/pci.h>
3388 +#include <linux/interrupt.h>
3389 +#include <linux/netdevice.h>
3390 +#include <asm/io.h>
3391 +
3392 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
3393 +#include <linux/workqueue.h>
3394 +#else
3395 +#include <linux/tqueue.h>
3396 +#ifndef work_struct
3397 +#define work_struct tq_struct
3398 +#endif
3399 +#ifndef INIT_WORK
3400 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
3401 +#endif
3402 +#ifndef schedule_work
3403 +#define schedule_work(_work) schedule_task((_work))
3404 +#endif
3405 +#ifndef flush_scheduled_work
3406 +#define flush_scheduled_work() flush_scheduled_tasks()
3407 +#endif
3408 +#endif
3409 +
3410 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3411 +/* Some distributions have their own 2.6.x compatibility layers */
3412 +#ifndef IRQ_NONE
3413 +typedef void irqreturn_t;
3414 +#define IRQ_NONE
3415 +#define IRQ_HANDLED
3416 +#define IRQ_RETVAL(x)
3417 +#endif
3418 +#else
3419 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
3420 +#endif
3421 +
3422 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
3423 +
3424 +#include <pcmcia/version.h>
3425 +#include <pcmcia/cs_types.h>
3426 +#include <pcmcia/cs.h>
3427 +#include <pcmcia/cistpl.h>
3428 +#include <pcmcia/cisreg.h>
3429 +#include <pcmcia/ds.h>
3430 +
3431 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
3432 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
3433 + * does this, but it's not in 2.4 so we do our own for now. */
3434 +static inline void
3435 +cs_error(client_handle_t handle, int func, int ret)
3436 +{
3437 + error_info_t err = { func, ret };
3438 + CardServices(ReportError, handle, &err);
3439 +}
3440 +#endif
3441 +
3442 +#endif /* CONFIG_PCMCIA */
3443 +
3444 +#ifndef __exit
3445 +#define __exit
3446 +#endif
3447 +#ifndef __devexit
3448 +#define __devexit
3449 +#endif
3450 +#ifndef __devinit
3451 +#define __devinit __init
3452 +#endif
3453 +#ifndef __devinitdata
3454 +#define __devinitdata
3455 +#endif
3456 +#ifndef __devexit_p
3457 +#define __devexit_p(x) x
3458 +#endif
3459 +
3460 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
3461 +
3462 +#define pci_get_drvdata(dev) (dev)->sysdata
3463 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
3464 +
3465 +/*
3466 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
3467 + */
3468 +
3469 +struct pci_device_id {
3470 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
3471 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
3472 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
3473 + unsigned long driver_data; /* Data private to the driver */
3474 +};
3475 +
3476 +struct pci_driver {
3477 + struct list_head node;
3478 + char *name;
3479 + const struct pci_device_id *id_table; /* NULL if wants all devices */
3480 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
3481 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
3482 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
3483 + void (*resume)(struct pci_dev *dev); /* Device woken up */
3484 +};
3485 +
3486 +#define MODULE_DEVICE_TABLE(type, name)
3487 +#define PCI_ANY_ID (~0)
3488 +
3489 +/* compatpci.c */
3490 +#define pci_module_init pci_register_driver
3491 +extern int pci_register_driver(struct pci_driver *drv);
3492 +extern void pci_unregister_driver(struct pci_driver *drv);
3493 +
3494 +#endif /* PCI registration */
3495 +
3496 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
3497 +#ifdef MODULE
3498 +#define module_init(x) int init_module(void) { return x(); }
3499 +#define module_exit(x) void cleanup_module(void) { x(); }
3500 +#else
3501 +#define module_init(x) __initcall(x);
3502 +#define module_exit(x) __exitcall(x);
3503 +#endif
3504 +#endif
3505 +
3506 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
3507 +#define list_for_each(pos, head) \
3508 + for (pos = (head)->next; pos != (head); pos = pos->next)
3509 +#endif
3510 +
3511 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
3512 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
3513 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
3514 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
3515 +#endif
3516 +
3517 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
3518 +#define pci_enable_device(dev) do { } while (0)
3519 +#endif
3520 +
3521 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
3522 +#define net_device device
3523 +#endif
3524 +
3525 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
3526 +
3527 +/*
3528 + * DMA mapping
3529 + *
3530 + * See linux/Documentation/DMA-mapping.txt
3531 + */
3532 +
3533 +#ifndef PCI_DMA_TODEVICE
3534 +#define PCI_DMA_TODEVICE 1
3535 +#define PCI_DMA_FROMDEVICE 2
3536 +#endif
3537 +
3538 +typedef u32 dma_addr_t;
3539 +
3540 +/* Pure 2^n version of get_order */
3541 +static inline int get_order(unsigned long size)
3542 +{
3543 + int order;
3544 +
3545 + size = (size-1) >> (PAGE_SHIFT-1);
3546 + order = -1;
3547 + do {
3548 + size >>= 1;
3549 + order++;
3550 + } while (size);
3551 + return order;
3552 +}
3553 +
3554 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
3555 + dma_addr_t *dma_handle)
3556 +{
3557 + void *ret;
3558 + int gfp = GFP_ATOMIC | GFP_DMA;
3559 +
3560 + ret = (void *)__get_free_pages(gfp, get_order(size));
3561 +
3562 + if (ret != NULL) {
3563 + memset(ret, 0, size);
3564 + *dma_handle = virt_to_bus(ret);
3565 + }
3566 + return ret;
3567 +}
3568 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
3569 + void *vaddr, dma_addr_t dma_handle)
3570 +{
3571 + free_pages((unsigned long)vaddr, get_order(size));
3572 +}
3573 +#ifdef ILSIM
3574 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
3575 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
3576 +#else
3577 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
3578 +#define pci_unmap_single(cookie, address, size, dir)
3579 +#endif
3580 +
3581 +#endif /* DMA mapping */
3582 +
3583 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
3584 +
3585 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
3586 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
3587 +
3588 +/* pcmcia-cs provides its own netdevice compatibility layer */
3589 +#ifndef _COMPAT_NETDEVICE_H
3590 +
3591 +/*
3592 + * SoftNet
3593 + *
3594 + * For pre-softnet kernels we need to tell the upper layer not to
3595 + * re-enter start_xmit() while we are in there. However softnet
3596 + * guarantees not to enter while we are in there so there is no need
3597 + * to do the netif_stop_queue() dance unless the transmit queue really
3598 + * gets stuck. This should also improve performance according to tests
3599 + * done by Aman Singla.
3600 + */
3601 +
3602 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
3603 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
3604 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
3605 +
3606 +static inline void netif_start_queue(struct net_device *dev)
3607 +{
3608 + dev->tbusy = 0;
3609 + dev->interrupt = 0;
3610 + dev->start = 1;
3611 +}
3612 +
3613 +#define netif_queue_stopped(dev) (dev)->tbusy
3614 +#define netif_running(dev) (dev)->start
3615 +
3616 +#endif /* _COMPAT_NETDEVICE_H */
3617 +
3618 +#define netif_device_attach(dev) netif_start_queue(dev)
3619 +#define netif_device_detach(dev) netif_stop_queue(dev)
3620 +
3621 +/* 2.4.x renamed bottom halves to tasklets */
3622 +#define tasklet_struct tq_struct
3623 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
3624 +{
3625 + queue_task(tasklet, &tq_immediate);
3626 + mark_bh(IMMEDIATE_BH);
3627 +}
3628 +
3629 +static inline void tasklet_init(struct tasklet_struct *tasklet,
3630 + void (*func)(unsigned long),
3631 + unsigned long data)
3632 +{
3633 + tasklet->next = NULL;
3634 + tasklet->sync = 0;
3635 + tasklet->routine = (void (*)(void *))func;
3636 + tasklet->data = (void *)data;
3637 +}
3638 +#define tasklet_kill(tasklet) {do{} while(0);}
3639 +
3640 +/* 2.4.x introduced del_timer_sync() */
3641 +#define del_timer_sync(timer) del_timer(timer)
3642 +
3643 +#else
3644 +
3645 +#define netif_down(dev)
3646 +
3647 +#endif /* SoftNet */
3648 +
3649 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
3650 +
3651 +/*
3652 + * Emit code to initialise a tq_struct's routine and data pointers
3653 + */
3654 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
3655 + do { \
3656 + (_tq)->routine = _routine; \
3657 + (_tq)->data = _data; \
3658 + } while (0)
3659 +
3660 +/*
3661 + * Emit code to initialise all of a tq_struct
3662 + */
3663 +#define INIT_TQUEUE(_tq, _routine, _data) \
3664 + do { \
3665 + INIT_LIST_HEAD(&(_tq)->list); \
3666 + (_tq)->sync = 0; \
3667 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
3668 + } while (0)
3669 +
3670 +#endif
3671 +
3672 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
3673 +
3674 +/* Power management related routines */
3675 +
3676 +static inline int
3677 +pci_save_state(struct pci_dev *dev, u32 *buffer)
3678 +{
3679 + int i;
3680 + if (buffer) {
3681 + for (i = 0; i < 16; i++)
3682 + pci_read_config_dword(dev, i * 4,&buffer[i]);
3683 + }
3684 + return 0;
3685 +}
3686 +
3687 +static inline int
3688 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
3689 +{
3690 + int i;
3691 +
3692 + if (buffer) {
3693 + for (i = 0; i < 16; i++)
3694 + pci_write_config_dword(dev,i * 4, buffer[i]);
3695 + }
3696 + /*
3697 + * otherwise, write the context information we know from bootup.
3698 + * This works around a problem where warm-booting from Windows
3699 + * combined with a D3(hot)->D0 transition causes PCI config
3700 + * header data to be forgotten.
3701 + */
3702 + else {
3703 + for (i = 0; i < 6; i ++)
3704 + pci_write_config_dword(dev,
3705 + PCI_BASE_ADDRESS_0 + (i * 4),
3706 + pci_resource_start(dev, i));
3707 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3708 + }
3709 + return 0;
3710 +}
3711 +
3712 +#endif /* PCI power management */
3713 +
3714 +/* Old cp0 access macros deprecated in 2.4.19 */
3715 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
3716 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
3717 +#endif
3718 +
3719 +/* Module refcount handled internally in 2.6.x */
3720 +#ifndef SET_MODULE_OWNER
3721 +#define SET_MODULE_OWNER(dev) do {} while (0)
3722 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
3723 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
3724 +#else
3725 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
3726 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
3727 +#endif
3728 +
3729 +#ifndef SET_NETDEV_DEV
3730 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
3731 +#endif
3732 +
3733 +#ifndef HAVE_FREE_NETDEV
3734 +#define free_netdev(dev) kfree(dev)
3735 +#endif
3736 +
3737 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3738 +/* struct packet_type redefined in 2.6.x */
3739 +#define af_packet_priv data
3740 +#endif
3741 +
3742 +#endif /* _linuxver_h_ */
3743 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/min_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/min_osl.h
3744 --- linux-2.4.32/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
3745 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/min_osl.h 2005-12-16 23:39:10.748824500 +0100
3746 @@ -0,0 +1,126 @@
3747 +/*
3748 + * HND Minimal OS Abstraction Layer.
3749 + *
3750 + * Copyright 2005, Broadcom Corporation
3751 + * All Rights Reserved.
3752 + *
3753 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3754 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3755 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3756 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3757 + *
3758 + * $Id$
3759 + */
3760 +
3761 +#ifndef _min_osl_h_
3762 +#define _min_osl_h_
3763 +
3764 +#include <typedefs.h>
3765 +#include <sbconfig.h>
3766 +#include <mipsinc.h>
3767 +
3768 +/* Cache support */
3769 +extern void caches_on(void);
3770 +extern void blast_dcache(void);
3771 +extern void blast_icache(void);
3772 +
3773 +/* uart output */
3774 +extern void putc(int c);
3775 +
3776 +/* lib functions */
3777 +extern int printf(const char *fmt, ...);
3778 +extern int sprintf(char *buf, const char *fmt, ...);
3779 +extern int strcmp(const char *s1, const char *s2);
3780 +extern int strncmp(const char *s1, const char *s2, uint n);
3781 +extern char *strcpy(char *dest, const char *src);
3782 +extern char *strncpy(char *dest, const char *src, uint n);
3783 +extern uint strlen(const char *s);
3784 +extern char *strchr(const char *str,int c);
3785 +extern char *strrchr(const char *str, int c);
3786 +extern char *strcat(char *d, const char *s);
3787 +extern void *memset(void *dest, int c, uint n);
3788 +extern void *memcpy(void *dest, const void *src, uint n);
3789 +extern int memcmp(const void *s1, const void *s2, uint n);
3790 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3791 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3792 +#define bzero(b, len) memset((b), '\0', (len))
3793 +
3794 +/* assert & debugging */
3795 +#define ASSERT(exp) do {} while (0)
3796 +
3797 +/* PCMCIA attribute space access macros */
3798 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3799 + ASSERT(0)
3800 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3801 + ASSERT(0)
3802 +
3803 +/* PCI configuration space access macros */
3804 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
3805 + (offset == 8 ? 0 : 0xffffffff)
3806 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
3807 + do {} while (0)
3808 +
3809 +/* PCI device bus # and slot # */
3810 +#define OSL_PCI_BUS(osh) (0)
3811 +#define OSL_PCI_SLOT(osh) (0)
3812 +
3813 +/* register access macros */
3814 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
3815 +#define rreg32(r) (*(volatile uint32*)(r))
3816 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
3817 +#define rreg16(r) (*(volatile uint16*)(r))
3818 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
3819 +#define rreg8(r) (*(volatile uint8*)(r))
3820 +#define R_REG(r) ({ \
3821 + __typeof(*(r)) __osl_v; \
3822 + switch (sizeof(*(r))) { \
3823 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
3824 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
3825 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
3826 + } \
3827 + __osl_v; \
3828 +})
3829 +#define W_REG(r, v) do { \
3830 + switch (sizeof(*(r))) { \
3831 + case sizeof(uint8): wreg8((r), (v)); break; \
3832 + case sizeof(uint16): wreg16((r), (v)); break; \
3833 + case sizeof(uint32): wreg32((r), (v)); break; \
3834 + } \
3835 +} while (0)
3836 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3837 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3838 +
3839 +/* general purpose memory allocation */
3840 +#define MALLOC(osh, size) malloc(size)
3841 +#define MFREE(osh, addr, size) free(addr)
3842 +#define MALLOCED(osh) 0
3843 +#define MALLOC_FAILED(osh) 0
3844 +#define MALLOC_DUMP(osh, buf, sz)
3845 +extern int free(void *ptr);
3846 +extern void *malloc(uint size);
3847 +
3848 +/* uncached virtual address */
3849 +#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
3850 +
3851 +/* host/bus architecture-specific address byte swap */
3852 +#define BUS_SWAP32(v) (v)
3853 +
3854 +/* microsecond delay */
3855 +#define OSL_DELAY(usec) udelay(usec)
3856 +extern void udelay(uint32 usec);
3857 +
3858 +/* map/unmap physical to virtual I/O */
3859 +#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
3860 +#define REG_UNMAP(va) do {} while (0)
3861 +
3862 +/* dereference an address that may cause a bus exception */
3863 +#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
3864 +
3865 +/* Misc stubs */
3866 +#define osl_attach(pdev) ((osl_t*)pdev)
3867 +#define osl_detach(osh)
3868 +extern void *osl_init(void);
3869 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3870 +extern int osl_error(int);
3871 +
3872 +#endif /* _min_osl_h_ */
3873 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h
3874 --- linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
3875 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h 2005-12-16 23:39:10.748824500 +0100
3876 @@ -0,0 +1,552 @@
3877 +/*
3878 + * HND Run Time Environment for standalone MIPS programs.
3879 + *
3880 + * Copyright 2005, Broadcom Corporation
3881 + * All Rights Reserved.
3882 + *
3883 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3884 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3885 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3886 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3887 + *
3888 + * $Id$
3889 + */
3890 +
3891 +#ifndef _MISPINC_H
3892 +#define _MISPINC_H
3893 +
3894 +
3895 +/* MIPS defines */
3896 +
3897 +#ifdef _LANGUAGE_ASSEMBLY
3898 +
3899 +/*
3900 + * Symbolic register names for 32 bit ABI
3901 + */
3902 +#define zero $0 /* wired zero */
3903 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
3904 +#define v0 $2 /* return value */
3905 +#define v1 $3
3906 +#define a0 $4 /* argument registers */
3907 +#define a1 $5
3908 +#define a2 $6
3909 +#define a3 $7
3910 +#define t0 $8 /* caller saved */
3911 +#define t1 $9
3912 +#define t2 $10
3913 +#define t3 $11
3914 +#define t4 $12
3915 +#define t5 $13
3916 +#define t6 $14
3917 +#define t7 $15
3918 +#define s0 $16 /* callee saved */
3919 +#define s1 $17
3920 +#define s2 $18
3921 +#define s3 $19
3922 +#define s4 $20
3923 +#define s5 $21
3924 +#define s6 $22
3925 +#define s7 $23
3926 +#define t8 $24 /* caller saved */
3927 +#define t9 $25
3928 +#define jp $25 /* PIC jump register */
3929 +#define k0 $26 /* kernel scratch */
3930 +#define k1 $27
3931 +#define gp $28 /* global pointer */
3932 +#define sp $29 /* stack pointer */
3933 +#define fp $30 /* frame pointer */
3934 +#define s8 $30 /* same like fp! */
3935 +#define ra $31 /* return address */
3936 +
3937 +
3938 +/*
3939 + * CP0 Registers
3940 + */
3941 +
3942 +#define C0_INX $0
3943 +#define C0_RAND $1
3944 +#define C0_TLBLO0 $2
3945 +#define C0_TLBLO C0_TLBLO0
3946 +#define C0_TLBLO1 $3
3947 +#define C0_CTEXT $4
3948 +#define C0_PGMASK $5
3949 +#define C0_WIRED $6
3950 +#define C0_BADVADDR $8
3951 +#define C0_COUNT $9
3952 +#define C0_TLBHI $10
3953 +#define C0_COMPARE $11
3954 +#define C0_SR $12
3955 +#define C0_STATUS C0_SR
3956 +#define C0_CAUSE $13
3957 +#define C0_EPC $14
3958 +#define C0_PRID $15
3959 +#define C0_CONFIG $16
3960 +#define C0_LLADDR $17
3961 +#define C0_WATCHLO $18
3962 +#define C0_WATCHHI $19
3963 +#define C0_XCTEXT $20
3964 +#define C0_DIAGNOSTIC $22
3965 +#define C0_BROADCOM C0_DIAGNOSTIC
3966 +#define C0_PERFORMANCE $25
3967 +#define C0_ECC $26
3968 +#define C0_CACHEERR $27
3969 +#define C0_TAGLO $28
3970 +#define C0_TAGHI $29
3971 +#define C0_ERREPC $30
3972 +#define C0_DESAVE $31
3973 +
3974 +/*
3975 + * LEAF - declare leaf routine
3976 + */
3977 +#define LEAF(symbol) \
3978 + .globl symbol; \
3979 + .align 2; \
3980 + .type symbol,@function; \
3981 + .ent symbol,0; \
3982 +symbol: .frame sp,0,ra
3983 +
3984 +/*
3985 + * END - mark end of function
3986 + */
3987 +#define END(function) \
3988 + .end function; \
3989 + .size function,.-function
3990 +
3991 +#define _ULCAST_
3992 +
3993 +#else
3994 +
3995 +/*
3996 + * The following macros are especially useful for __asm__
3997 + * inline assembler.
3998 + */
3999 +#ifndef __STR
4000 +#define __STR(x) #x
4001 +#endif
4002 +#ifndef STR
4003 +#define STR(x) __STR(x)
4004 +#endif
4005 +
4006 +#define _ULCAST_ (unsigned long)
4007 +
4008 +
4009 +/*
4010 + * CP0 Registers
4011 + */
4012 +
4013 +#define C0_INX 0 /* CP0: TLB Index */
4014 +#define C0_RAND 1 /* CP0: TLB Random */
4015 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4016 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4017 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4018 +#define C0_CTEXT 4 /* CP0: Context */
4019 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4020 +#define C0_WIRED 6 /* CP0: TLB Wired */
4021 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4022 +#define C0_COUNT 9 /* CP0: Count */
4023 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4024 +#define C0_COMPARE 11 /* CP0: Compare */
4025 +#define C0_SR 12 /* CP0: Processor Status */
4026 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4027 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4028 +#define C0_EPC 14 /* CP0: Exception PC */
4029 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4030 +#define C0_CONFIG 16 /* CP0: Config */
4031 +#define C0_LLADDR 17 /* CP0: LLAddr */
4032 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4033 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4034 +#define C0_XCTEXT 20 /* CP0: XContext */
4035 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4036 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4037 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4038 +#define C0_ECC 26 /* CP0: ECC */
4039 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4040 +#define C0_TAGLO 28 /* CP0: TagLo */
4041 +#define C0_TAGHI 29 /* CP0: TagHi */
4042 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4043 +#define C0_DESAVE 31 /* CP0: DebugSave */
4044 +
4045 +#endif /* _LANGUAGE_ASSEMBLY */
4046 +
4047 +/*
4048 + * Memory segments (32bit kernel mode addresses)
4049 + */
4050 +#undef KUSEG
4051 +#undef KSEG0
4052 +#undef KSEG1
4053 +#undef KSEG2
4054 +#undef KSEG3
4055 +#define KUSEG 0x00000000
4056 +#define KSEG0 0x80000000
4057 +#define KSEG1 0xa0000000
4058 +#define KSEG2 0xc0000000
4059 +#define KSEG3 0xe0000000
4060 +#define PHYSADDR_MASK 0x1fffffff
4061 +
4062 +/*
4063 + * Map an address to a certain kernel segment
4064 + */
4065 +#undef PHYSADDR
4066 +#undef KSEG0ADDR
4067 +#undef KSEG1ADDR
4068 +#undef KSEG2ADDR
4069 +#undef KSEG3ADDR
4070 +
4071 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
4072 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
4073 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
4074 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
4075 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
4076 +
4077 +
4078 +#ifndef Index_Invalidate_I
4079 +/*
4080 + * Cache Operations
4081 + */
4082 +#define Index_Invalidate_I 0x00