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patch nvram library for new nas version (thx to Vincent Bernat)
[openwrt/svn-archive/archive.git] / openwrt / target / linux / brcm-2.6 / patches / 004-b44_bcm47xx_support.patch
1 diff -urN orig/linux-2.6.15/drivers/net/b44.c linux-2.6.15/drivers/net/b44.c
2 --- orig/linux-2.6.15/drivers/net/b44.c 2006-01-03 04:21:10.000000000 +0100
3 +++ linux-2.6.15/drivers/net/b44.c 2006-01-12 12:22:58.760883688 +0100
4 @@ -1,7 +1,9 @@
5 -/* b44.c: Broadcom 4400 device driver.
6 +/* b44.c: Broadcom 4400/47xx device driver.
7 *
8 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
9 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
10 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
11 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12 + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
13 *
14 * Distribute under GPL.
15 */
16 @@ -31,6 +33,28 @@
17 #define DRV_MODULE_VERSION "0.97"
18 #define DRV_MODULE_RELDATE "Nov 30, 2005"
19
20 +#ifdef CONFIG_BCM947XX
21 +extern char *nvram_get(char *name);
22 +static inline void e_aton(char *str, char *dest)
23 +{
24 + int i = 0;
25 +
26 + if (str == NULL) {
27 + memset(dest, 0, 6);
28 + return;
29 + }
30 +
31 + for (;;) {
32 + dest[i++] = (char) simple_strtoul(str, NULL, 16);
33 + str += 2;
34 + if (!*str++ || i == 6)
35 + break;
36 + }
37 +}
38 +
39 +static int b44_4713_instance;
40 +#endif
41 +
42 #define B44_DEF_MSG_ENABLE \
43 (NETIF_MSG_DRV | \
44 NETIF_MSG_PROBE | \
45 @@ -77,8 +101,8 @@
46 static char version[] __devinitdata =
47 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
48
49 -MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
50 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
51 +MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
52 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
53 MODULE_LICENSE("GPL");
54 MODULE_VERSION(DRV_MODULE_VERSION);
55
56 @@ -93,6 +117,10 @@
57 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
58 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
59 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
60 +#ifdef CONFIG_BCM947XX
61 + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
62 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
63 +#endif
64 { } /* terminate list with empty entry */
65 };
66
67 @@ -131,17 +159,6 @@
68 dma_desc_sync_size, dir);
69 }
70
71 -static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
72 -{
73 - return readl(bp->regs + reg);
74 -}
75 -
76 -static inline void bw32(const struct b44 *bp,
77 - unsigned long reg, unsigned long val)
78 -{
79 - writel(val, bp->regs + reg);
80 -}
81 -
82 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
83 u32 bit, unsigned long timeout, const int clear)
84 {
85 @@ -268,6 +285,10 @@
86 break;
87 };
88 #endif
89 +#ifdef CONFIG_BCM947XX
90 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
91 + return b44_4713_instance++;
92 +#endif
93 return 0;
94 }
95
96 @@ -313,14 +334,14 @@
97 bw32(bp, B44_IMASK, bp->imask);
98 }
99
100 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
101 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
102 {
103 int err;
104
105 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
106 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
107 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
108 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
109 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
110 (reg << MDIO_DATA_RA_SHIFT) |
111 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
112 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
113 @@ -329,18 +350,34 @@
114 return err;
115 }
116
117 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
118 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
119 {
120 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
121 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
122 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
123 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
124 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
125 (reg << MDIO_DATA_RA_SHIFT) |
126 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
127 (val & MDIO_DATA_DATA)));
128 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
129 }
130
131 +static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
132 +{
133 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
134 + return 0;
135 +
136 + return __b44_readphy(bp, bp->phy_addr, reg, val);
137 +}
138 +
139 +static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
140 +{
141 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
142 + return 0;
143 +
144 + return __b44_writephy(bp, bp->phy_addr, reg, val);
145 +}
146 +
147 /* miilib interface */
148 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
149 * due to code existing before miilib use was added to this driver.
150 @@ -369,6 +406,8 @@
151 u32 val;
152 int err;
153
154 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
155 + return 0;
156 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
157 if (err)
158 return err;
159 @@ -439,6 +478,30 @@
160 u32 val;
161 int err;
162
163 +#ifdef CONFIG_BCM947XX
164 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
165 + /*
166 + * workaround for bad hardware design in Linksys WAP54G v1.0
167 + * see https://dev.openwrt.org/ticket/146
168 + * check and reset bit "isolate"
169 + */
170 + if (!strcmp(nvram_get("boardnum"), "2\r")) {
171 + u32 val;
172 + if (__b44_readphy(bp, 0, MII_BMCR, &val) != 0) {
173 + printk(KERN_WARNING PFX "%s: PHY WAP54G: cannot access PHY.\n",
174 + bp->dev->name);
175 + } else if (val & BMCR_ISOLATE) {
176 + printk(KERN_INFO PFX "%s: PHY WAP54G: resetting isolate bit.\n",
177 + bp->dev->name);
178 + if (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)
179 + printk(KERN_WARNING PFX "PHY WAP54G: cannot reset isolate bit.\n");
180 + }
181 + }
182 + }
183 +#endif
184 +
185 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
186 + return 0;
187 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
188 goto out;
189 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
190 @@ -534,6 +597,19 @@
191 {
192 u32 bmsr, aux;
193
194 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
195 + bp->flags |= B44_FLAG_100_BASE_T;
196 + bp->flags |= B44_FLAG_FULL_DUPLEX;
197 + if (!netif_carrier_ok(bp->dev)) {
198 + u32 val = br32(bp, B44_TX_CTRL);
199 + val |= TX_CTRL_DUPLEX;
200 + bw32(bp, B44_TX_CTRL, val);
201 + netif_carrier_on(bp->dev);
202 + b44_link_report(bp);
203 + }
204 + return;
205 + }
206 +
207 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
208 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
209 (bmsr != 0xffff)) {
210 @@ -1281,9 +1357,10 @@
211 bw32(bp, B44_DMARX_CTRL, 0);
212 bp->rx_prod = bp->rx_cons = 0;
213 } else {
214 - ssb_pci_setup(bp, (bp->core_unit == 0 ?
215 - SBINTVEC_ENET0 :
216 - SBINTVEC_ENET1));
217 + if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
218 + ssb_pci_setup(bp, (bp->core_unit == 0 ?
219 + SBINTVEC_ENET0 :
220 + SBINTVEC_ENET1));
221 }
222
223 ssb_core_reset(bp);
224 @@ -1291,8 +1368,14 @@
225 b44_clear_stats(bp);
226
227 /* Make PHY accessible. */
228 - bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
229 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
230 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
231 + (((100000000 + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
232 + & MDIO_CTRL_MAXF_MASK)));
233 + else
234 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
235 (0x0d & MDIO_CTRL_MAXF_MASK)));
236 +
237 br32(bp, B44_MDIO_CTRL);
238
239 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
240 @@ -1834,18 +1917,297 @@
241 .get_perm_addr = ethtool_op_get_perm_addr,
242 };
243
244 +static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
245 +{
246 + struct b44 *bp = dev->priv;
247 + struct pci_dev *pci_dev = bp->pdev;
248 + u32 ethcmd;
249 +
250 + if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
251 + return -EFAULT;
252 +
253 + switch (ethcmd) {
254 + case ETHTOOL_GDRVINFO: {
255 + struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
256 + strcpy (info.driver, DRV_MODULE_NAME);
257 + strcpy (info.version, DRV_MODULE_VERSION);
258 + memset(&info.fw_version, 0, sizeof(info.fw_version));
259 + strcpy (info.bus_info, pci_name(pci_dev));
260 + info.eedump_len = 0;
261 + info.regdump_len = 0;
262 + if (copy_to_user (useraddr, &info, sizeof (info)))
263 + return -EFAULT;
264 + return 0;
265 + }
266 +
267 + case ETHTOOL_GSET: {
268 + struct ethtool_cmd cmd = { ETHTOOL_GSET };
269 +
270 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
271 + return -EAGAIN;
272 + cmd.supported = (SUPPORTED_Autoneg);
273 + cmd.supported |= (SUPPORTED_100baseT_Half |
274 + SUPPORTED_100baseT_Full |
275 + SUPPORTED_10baseT_Half |
276 + SUPPORTED_10baseT_Full |
277 + SUPPORTED_MII);
278 +
279 + cmd.advertising = 0;
280 + if (bp->flags & B44_FLAG_ADV_10HALF)
281 + cmd.advertising |= ADVERTISE_10HALF;
282 + if (bp->flags & B44_FLAG_ADV_10FULL)
283 + cmd.advertising |= ADVERTISE_10FULL;
284 + if (bp->flags & B44_FLAG_ADV_100HALF)
285 + cmd.advertising |= ADVERTISE_100HALF;
286 + if (bp->flags & B44_FLAG_ADV_100FULL)
287 + cmd.advertising |= ADVERTISE_100FULL;
288 + cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
289 + cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
290 + SPEED_100 : SPEED_10;
291 + cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
292 + DUPLEX_FULL : DUPLEX_HALF;
293 + cmd.port = 0;
294 + cmd.phy_address = bp->phy_addr;
295 + cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
296 + XCVR_INTERNAL : XCVR_EXTERNAL;
297 + cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
298 + AUTONEG_DISABLE : AUTONEG_ENABLE;
299 + cmd.maxtxpkt = 0;
300 + cmd.maxrxpkt = 0;
301 + if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
302 + return -EFAULT;
303 + return 0;
304 + }
305 + case ETHTOOL_SSET: {
306 + struct ethtool_cmd cmd;
307 +
308 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
309 + return -EAGAIN;
310 +
311 + if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
312 + return -EFAULT;
313 +
314 + /* We do not support gigabit. */
315 + if (cmd.autoneg == AUTONEG_ENABLE) {
316 + if (cmd.advertising &
317 + (ADVERTISED_1000baseT_Half |
318 + ADVERTISED_1000baseT_Full))
319 + return -EINVAL;
320 + } else if ((cmd.speed != SPEED_100 &&
321 + cmd.speed != SPEED_10) ||
322 + (cmd.duplex != DUPLEX_HALF &&
323 + cmd.duplex != DUPLEX_FULL)) {
324 + return -EINVAL;
325 + }
326 +
327 + spin_lock_irq(&bp->lock);
328 +
329 + if (cmd.autoneg == AUTONEG_ENABLE) {
330 + bp->flags &= ~B44_FLAG_FORCE_LINK;
331 + bp->flags &= ~(B44_FLAG_ADV_10HALF |
332 + B44_FLAG_ADV_10FULL |
333 + B44_FLAG_ADV_100HALF |
334 + B44_FLAG_ADV_100FULL);
335 + if (cmd.advertising & ADVERTISE_10HALF)
336 + bp->flags |= B44_FLAG_ADV_10HALF;
337 + if (cmd.advertising & ADVERTISE_10FULL)
338 + bp->flags |= B44_FLAG_ADV_10FULL;
339 + if (cmd.advertising & ADVERTISE_100HALF)
340 + bp->flags |= B44_FLAG_ADV_100HALF;
341 + if (cmd.advertising & ADVERTISE_100FULL)
342 + bp->flags |= B44_FLAG_ADV_100FULL;
343 + } else {
344 + bp->flags |= B44_FLAG_FORCE_LINK;
345 + if (cmd.speed == SPEED_100)
346 + bp->flags |= B44_FLAG_100_BASE_T;
347 + if (cmd.duplex == DUPLEX_FULL)
348 + bp->flags |= B44_FLAG_FULL_DUPLEX;
349 + }
350 +
351 + b44_setup_phy(bp);
352 +
353 + spin_unlock_irq(&bp->lock);
354 +
355 + return 0;
356 + }
357 +
358 + case ETHTOOL_GMSGLVL: {
359 + struct ethtool_value edata = { ETHTOOL_GMSGLVL };
360 + edata.data = bp->msg_enable;
361 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
362 + return -EFAULT;
363 + return 0;
364 + }
365 + case ETHTOOL_SMSGLVL: {
366 + struct ethtool_value edata;
367 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
368 + return -EFAULT;
369 + bp->msg_enable = edata.data;
370 + return 0;
371 + }
372 + case ETHTOOL_NWAY_RST: {
373 + u32 bmcr;
374 + int r;
375 +
376 + spin_lock_irq(&bp->lock);
377 + b44_readphy(bp, MII_BMCR, &bmcr);
378 + b44_readphy(bp, MII_BMCR, &bmcr);
379 + r = -EINVAL;
380 + if (bmcr & BMCR_ANENABLE) {
381 + b44_writephy(bp, MII_BMCR,
382 + bmcr | BMCR_ANRESTART);
383 + r = 0;
384 + }
385 + spin_unlock_irq(&bp->lock);
386 +
387 + return r;
388 + }
389 + case ETHTOOL_GLINK: {
390 + struct ethtool_value edata = { ETHTOOL_GLINK };
391 + edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
392 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
393 + return -EFAULT;
394 + return 0;
395 + }
396 + case ETHTOOL_GRINGPARAM: {
397 + struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
398 +
399 + ering.rx_max_pending = B44_RX_RING_SIZE - 1;
400 + ering.rx_pending = bp->rx_pending;
401 +
402 + /* XXX ethtool lacks a tx_max_pending, oops... */
403 +
404 + if (copy_to_user(useraddr, &ering, sizeof(ering)))
405 + return -EFAULT;
406 + return 0;
407 + }
408 + case ETHTOOL_SRINGPARAM: {
409 + struct ethtool_ringparam ering;
410 +
411 + if (copy_from_user(&ering, useraddr, sizeof(ering)))
412 + return -EFAULT;
413 +
414 + if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
415 + (ering.rx_mini_pending != 0) ||
416 + (ering.rx_jumbo_pending != 0) ||
417 + (ering.tx_pending > B44_TX_RING_SIZE - 1))
418 + return -EINVAL;
419 +
420 + spin_lock_irq(&bp->lock);
421 +
422 + bp->rx_pending = ering.rx_pending;
423 + bp->tx_pending = ering.tx_pending;
424 +
425 + b44_halt(bp);
426 + b44_init_rings(bp);
427 + b44_init_hw(bp);
428 + netif_wake_queue(bp->dev);
429 + spin_unlock_irq(&bp->lock);
430 +
431 + b44_enable_ints(bp);
432 +
433 + return 0;
434 + }
435 + case ETHTOOL_GPAUSEPARAM: {
436 + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
437 +
438 + epause.autoneg =
439 + (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
440 + epause.rx_pause =
441 + (bp->flags & B44_FLAG_RX_PAUSE) != 0;
442 + epause.tx_pause =
443 + (bp->flags & B44_FLAG_TX_PAUSE) != 0;
444 + if (copy_to_user(useraddr, &epause, sizeof(epause)))
445 + return -EFAULT;
446 + return 0;
447 + }
448 + case ETHTOOL_SPAUSEPARAM: {
449 + struct ethtool_pauseparam epause;
450 +
451 + if (copy_from_user(&epause, useraddr, sizeof(epause)))
452 + return -EFAULT;
453 +
454 + spin_lock_irq(&bp->lock);
455 + if (epause.autoneg)
456 + bp->flags |= B44_FLAG_PAUSE_AUTO;
457 + else
458 + bp->flags &= ~B44_FLAG_PAUSE_AUTO;
459 + if (epause.rx_pause)
460 + bp->flags |= B44_FLAG_RX_PAUSE;
461 + else
462 + bp->flags &= ~B44_FLAG_RX_PAUSE;
463 + if (epause.tx_pause)
464 + bp->flags |= B44_FLAG_TX_PAUSE;
465 + else
466 + bp->flags &= ~B44_FLAG_TX_PAUSE;
467 + if (bp->flags & B44_FLAG_PAUSE_AUTO) {
468 + b44_halt(bp);
469 + b44_init_rings(bp);
470 + b44_init_hw(bp);
471 + } else {
472 + __b44_set_flow_ctrl(bp, bp->flags);
473 + }
474 + spin_unlock_irq(&bp->lock);
475 +
476 + b44_enable_ints(bp);
477 +
478 + return 0;
479 + }
480 + };
481 +
482 + return -EOPNOTSUPP;
483 +}
484 +
485 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
486 {
487 struct mii_ioctl_data *data = if_mii(ifr);
488 struct b44 *bp = netdev_priv(dev);
489 int err = -EINVAL;
490
491 - if (!netif_running(dev))
492 + if (bp->pdev->device != PCI_DEVICE_ID_BCM4713) {
493 + if (!netif_running(dev))
494 + goto out;
495 +
496 + spin_lock_irq(&bp->lock);
497 + err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
498 + spin_unlock_irq(&bp->lock);
499 goto out;
500 + }
501
502 - spin_lock_irq(&bp->lock);
503 - err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
504 - spin_unlock_irq(&bp->lock);
505 + switch (cmd) {
506 + case SIOCETHTOOL:
507 + return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
508 +
509 + case SIOCGMIIPHY:
510 + data->phy_id = bp->phy_addr;
511 +
512 + /* fallthru */
513 + case SIOCGMIIREG: {
514 + u32 mii_regval;
515 + spin_lock_irq(&bp->lock);
516 + err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
517 + spin_unlock_irq(&bp->lock);
518 +
519 + data->val_out = mii_regval;
520 +
521 + return err;
522 + }
523 +
524 + case SIOCSMIIREG:
525 + if (!capable(CAP_NET_ADMIN))
526 + return -EPERM;
527 +
528 + spin_lock_irq(&bp->lock);
529 + err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
530 + spin_unlock_irq(&bp->lock);
531 +
532 + return err;
533 +
534 + default:
535 + break;
536 + };
537 + return -EOPNOTSUPP;
538 +
539 out:
540 return err;
541 }
542 @@ -1865,22 +2227,43 @@
543 static int __devinit b44_get_invariants(struct b44 *bp)
544 {
545 u8 eeprom[128];
546 - int err;
547 + u8 buf[32];
548 + int err = 0;
549
550 - err = b44_read_eeprom(bp, &eeprom[0]);
551 - if (err)
552 - goto out;
553 -
554 - bp->dev->dev_addr[0] = eeprom[79];
555 - bp->dev->dev_addr[1] = eeprom[78];
556 - bp->dev->dev_addr[2] = eeprom[81];
557 - bp->dev->dev_addr[3] = eeprom[80];
558 - bp->dev->dev_addr[4] = eeprom[83];
559 - bp->dev->dev_addr[5] = eeprom[82];
560 - memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
561 -
562 - bp->phy_addr = eeprom[90] & 0x1f;
563 +#ifdef CONFIG_BCM947XX
564 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
565 + /*
566 + * BCM47xx boards don't have a EEPROM. The MAC is stored in
567 + * a NVRAM area somewhere in the flash memory.
568 + */
569 + sprintf(buf, "et%dmacaddr", b44_4713_instance);
570 + e_aton(nvram_get(buf), bp->dev->dev_addr);
571
572 + /*
573 + * BCM47xx boards don't have a PHY. Usually there is a switch
574 + * chip with multiple PHYs connected to the PHY port.
575 + */
576 + bp->phy_addr = B44_PHY_ADDR_NO_PHY;
577 + bp->dma_offset = 0;
578 + } else
579 +#endif
580 + {
581 + err = b44_read_eeprom(bp, &eeprom[0]);
582 + if (err)
583 + goto out;
584 +
585 + bp->dev->dev_addr[0] = eeprom[79];
586 + bp->dev->dev_addr[1] = eeprom[78];
587 + bp->dev->dev_addr[2] = eeprom[81];
588 + bp->dev->dev_addr[3] = eeprom[80];
589 + bp->dev->dev_addr[4] = eeprom[83];
590 + bp->dev->dev_addr[5] = eeprom[82];
591 + memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
592 +
593 + bp->phy_addr = eeprom[90] & 0x1f;
594 + bp->dma_offset = SB_PCI_DMA;
595 + }
596 +
597 /* With this, plus the rx_header prepended to the data by the
598 * hardware, we'll land the ethernet header on a 2-byte boundary.
599 */
600 @@ -1889,11 +2272,7 @@
601 bp->imask = IMASK_DEF;
602
603 bp->core_unit = ssb_core_unit(bp);
604 - bp->dma_offset = SB_PCI_DMA;
605
606 - /* XXX - really required?
607 - bp->flags |= B44_FLAG_BUGGY_TXPTR;
608 - */
609 out:
610 return err;
611 }
612 @@ -2032,11 +2411,17 @@
613
614 pci_save_state(bp->pdev);
615
616 - printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
617 + printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
618 + (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
619 for (i = 0; i < 6; i++)
620 printk("%2.2x%c", dev->dev_addr[i],
621 i == 5 ? '\n' : ':');
622
623 + /* Initialize phy */
624 + spin_lock_irq(&bp->lock);
625 + b44_chip_reset(bp);
626 + spin_unlock_irq(&bp->lock);
627 +
628 return 0;
629
630 err_out_iounmap:
631 diff -urN orig/linux-2.6.15/drivers/net/b44.h linux-2.6.15/drivers/net/b44.h
632 --- orig/linux-2.6.15/drivers/net/b44.h 2006-01-03 04:21:10.000000000 +0100
633 +++ linux-2.6.15/drivers/net/b44.h 2006-01-12 12:16:02.403179680 +0100
634 @@ -292,6 +292,10 @@
635 #define SSB_PCI_MASK1 0xfc000000
636 #define SSB_PCI_MASK2 0xc0000000
637
638 +#define br32(bp, REG) readl((void *)bp->regs + (REG))
639 +#define bw32(bp, REG,VAL) writel((VAL), (void *)bp->regs + (REG))
640 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
641 +
642 /* 4400 PHY registers */
643 #define B44_MII_AUXCTRL 24 /* Auxiliary Control */
644 #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */
645 @@ -345,6 +349,8 @@
646 };
647
648 #define B44_MCAST_TABLE_SIZE 32
649 +#define B44_PHY_ADDR_NO_PHY 30
650 +#define B44_MDC_RATIO 5000000
651
652 #define B44_STAT_REG_DECLARE \
653 _B44(tx_good_octets) \
654 @@ -420,6 +426,7 @@
655
656 u32 dma_offset;
657 u32 flags;
658 +#define B44_FLAG_INIT_COMPLETE 0x00000001
659 #define B44_FLAG_BUGGY_TXPTR 0x00000002
660 #define B44_FLAG_REORDER_BUG 0x00000004
661 #define B44_FLAG_PAUSE_AUTO 0x00008000
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