add incomplete ar7 hardware support (disabled by default)
[openwrt/svn-archive/archive.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux-2.4.30/Makefile linux-2.4.30.current/Makefile
2 --- linux-2.4.30/Makefile 2005-06-11 20:24:07.000000000 +0200
3 +++ linux-2.4.30.current/Makefile 2005-06-12 20:14:28.000000000 +0200
4 @@ -91,7 +91,7 @@
5
6 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
7
8 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
9 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
10 -fno-strict-aliasing -fno-common
11 ifndef CONFIG_FRAME_POINTER
12 CFLAGS += -fomit-frame-pointer
13 diff -urN linux-2.4.30/arch/mips/Makefile linux-2.4.30.current/arch/mips/Makefile
14 --- linux-2.4.30/arch/mips/Makefile 2005-06-11 20:24:07.000000000 +0200
15 +++ linux-2.4.30.current/arch/mips/Makefile 2005-06-12 20:14:28.000000000 +0200
16 @@ -369,6 +369,16 @@
17 endif
18
19 #
20 +# Texas Instruments AR7
21 +#
22 +
23 +ifdef CONFIG_AR7
24 +LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
25 +SUBDIRS += arch/mips/ar7 arch/mips/ar7/avalanche
26 +LOADADDR += 0x94020000
27 +endif
28 +
29 +#
30 # DECstation family
31 #
32 ifdef CONFIG_DECSTATION
33 diff -urN linux-2.4.30/arch/mips/ar7/Makefile linux-2.4.30.current/arch/mips/ar7/Makefile
34 --- linux-2.4.30/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
35 +++ linux-2.4.30.current/arch/mips/ar7/Makefile 2005-06-12 20:14:28.000000000 +0200
36 @@ -0,0 +1,12 @@
37 +.S.s:
38 + $(CPP) $(AFLAGS) $< -o $*.s
39 +
40 +.S.o:
41 + $(CC) $(AFLAGS) -c $< -o $*.o
42 +
43 +O_TARGET := ar7.o
44 +
45 +obj-y := tnetd73xx_misc.o
46 +obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
47 +
48 +include $(TOPDIR)/Rules.make
49 diff -urN linux-2.4.30/arch/mips/ar7/avalanche/Makefile linux-2.4.30.current/arch/mips/ar7/avalanche/Makefile
50 --- linux-2.4.30/arch/mips/ar7/avalanche/Makefile 1970-01-01 01:00:00.000000000 +0100
51 +++ linux-2.4.30.current/arch/mips/ar7/avalanche/Makefile 2005-06-12 20:14:28.000000000 +0200
52 @@ -0,0 +1,13 @@
53 +.S.s:
54 + $(CPP) $(AFLAGS) $< -o $*.s
55 +
56 +.S.o:
57 + $(CC) $(AFLAGS) -c $< -o $*.o
58 +
59 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
60 +
61 +O_TARGET := avalanche.o
62 +
63 +obj-y += avalanche_paging.o avalanche_jump.o
64 +
65 +include $(TOPDIR)/Rules.make
66 diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S linux-2.4.30.current/arch/mips/ar7/avalanche/avalanche_jump.S
67 --- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 01:00:00.000000000 +0100
68 +++ linux-2.4.30.current/arch/mips/ar7/avalanche/avalanche_jump.S 2005-06-12 20:14:28.000000000 +0200
69 @@ -0,0 +1,69 @@
70 +#include <linux/config.h>
71 +#include <linux/threads.h>
72 +
73 +#include <asm/asm.h>
74 +#include <asm/cacheops.h>
75 +#include <asm/current.h>
76 +#include <asm/offset.h>
77 +#include <asm/processor.h>
78 +#include <asm/regdef.h>
79 +#include <asm/cachectl.h>
80 +#include <asm/mipsregs.h>
81 +#include <asm/stackframe.h>
82 +
83 +.text
84 +
85 +.set noreorder
86 +.set noat
87 +
88 +/* TLB Miss Vector */
89 +
90 +LEAF(jump_tlb_miss)
91 + .set mips2
92 + lui k0,0x9400
93 + ori k0,0
94 + jr k0
95 + nop
96 +END(jump_tlb_miss)
97 +
98 + /* Unused TLB Miss Vector */
99 +
100 +LEAF(jump_tlb_miss_unused)
101 + .set mips2
102 + lui k0,0x9400
103 + ori k0,0x80
104 + jr k0
105 + nop
106 +END(jump_tlb_miss_unused)
107 +
108 + /* Cache Error Vector */
109 +
110 +LEAF(jump_cache_error)
111 + .set mips2
112 + lui k0,0x9400
113 + ori k0,0x100
114 + jr k0
115 + nop
116 +END(jump_cache_error)
117 +
118 + /* General Exception */
119 +
120 +LEAF(jump_general_exception)
121 + .set mips2
122 + lui k0,0x9400
123 + ori k0,0x180
124 + jr k0
125 + nop
126 +END(jump_general_exception)
127 +
128 + /* Dedicated Interrupt */
129 +
130 +LEAF(jump_dedicated_interrupt)
131 + .set mips2
132 + lui k0,0x9400
133 + ori k0,0x200
134 + jr k0
135 + nop
136 +END(jump_dedicated_interrupt)
137 +
138 + .set at
139 diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c linux-2.4.30.current/arch/mips/ar7/avalanche/avalanche_paging.c
140 --- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c 1970-01-01 01:00:00.000000000 +0100
141 +++ linux-2.4.30.current/arch/mips/ar7/avalanche/avalanche_paging.c 2005-06-12 20:14:28.000000000 +0200
142 @@ -0,0 +1,314 @@
143 +/*
144 + * -*- linux-c -*-
145 + * This file is subject to the terms and conditions of the GNU General Public
146 + * License. See the file "COPYING" in the main directory of this archive
147 + * for more details.
148 + *
149 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
150 + * Copyright (C) 2002 Texas Instruments, Inc.
151 + *
152 + */
153 +
154 +/*
155 + * This file takes care of the "memory hole" issue that exists with the standard
156 + * linux kernel and the TI Avalanche ASIC. The Avalanche ASIC requires an offset
157 + * of 0x14000000 due to the ASIC's memory map constraints. This file corrects the
158 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
159 + *
160 + * -JAH
161 + */
162 +#include <linux/config.h>
163 +#include <linux/signal.h>
164 +#include <linux/sched.h>
165 +#include <linux/kernel.h>
166 +#include <linux/errno.h>
167 +#include <linux/string.h>
168 +#include <linux/types.h>
169 +#include <linux/ptrace.h>
170 +#include <linux/mman.h>
171 +#include <linux/mm.h>
172 +#include <linux/swap.h>
173 +#include <linux/smp.h>
174 +#include <linux/init.h>
175 +#ifdef CONFIG_BLK_DEV_INITRD
176 +#include <linux/blk.h>
177 +#endif /* CONFIG_BLK_DEV_INITRD */
178 +#include <linux/highmem.h>
179 +#include <linux/bootmem.h>
180 +
181 +#include <asm/processor.h>
182 +#include <asm/system.h>
183 +#include <asm/uaccess.h>
184 +#include <asm/pgtable.h>
185 +#include <asm/pgalloc.h>
186 +#include <asm/mmu_context.h>
187 +#include <asm/io.h>
188 +#include <asm/tlb.h>
189 +#include <asm/cpu.h>
190 +
191 +#define __MEMORY_START CONFIG_AR7_MEMORY
192 +
193 +#ifdef CONFIG_DISCONTIGMEM
194 +pg_data_t discontig_page_data[NR_NODES];
195 +bootmem_data_t discontig_node_bdata[NR_NODES];
196 +#endif
197 +
198 +static unsigned long totalram_pages;
199 +/* static unsigned long totalhigh_pages; */
200 +
201 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
202 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
203 +
204 +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
205 +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
206 +#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
207 +
208 +unsigned long bootmap_size;
209 +
210 +extern char *prom_getenv(char *envname);
211 +
212 +/*
213 + * We have upto 8 empty zeroed pages so we can map one of the right colour
214 + * when needed. This is necessary only on R4000 / R4400 SC and MC versions
215 + * where we have to avoid VCED / VECI exceptions for good performance at
216 + * any price. Since page is never written to after the initialization we
217 + * don't have to care about aliases on other CPUs.
218 + */
219 +
220 +static inline unsigned long setup_zero_pages(void)
221 +{
222 + unsigned long order, size;
223 + struct page *page;
224 + if(current_cpu_data.options & MIPS_CPU_VCE)
225 + order = 3;
226 + else
227 + order = 0;
228 +
229 + empty_zero_page = __get_free_pages(GFP_KERNEL, order);
230 +
231 + if (!empty_zero_page)
232 + panic("Oh boy, that early out of memory?");
233 +
234 + page = virt_to_page(empty_zero_page);
235 +
236 + while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
237 + set_bit(PG_reserved, &page->flags);
238 + set_page_count(page, 0);
239 + page++;
240 + }
241 +
242 + size = PAGE_SIZE << order;
243 + zero_page_mask = (size - 1) & PAGE_MASK;
244 + memset((void *)empty_zero_page, 0, size);
245 +
246 + return 1UL << order;
247 +}
248 +
249 +/*
250 + * paging_init() sets up the page tables
251 + *
252 + * This routines also unmaps the page at virtual kernel address 0, so
253 + * that we can trap those pesky NULL-reference errors in the kernel.
254 + */
255 +void __init paging_init(void)
256 +{
257 + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
258 + unsigned long low, start_pfn;
259 +
260 + /* Initialize the entire pgd. */
261 + pgd_init((unsigned long)swapper_pg_dir);
262 + pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
263 +
264 +
265 + start_pfn = START_PFN;
266 + // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
267 + low = MAX_LOW_PFN;
268 +
269 + /* Avalanche DMA-able memory 0x14000000+memsize */
270 +
271 + zones_size[ZONE_DMA] = low - start_pfn;
272 +
273 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
274 +
275 +#ifdef CONFIG_DISCONTIGMEM
276 + zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
277 + zones_size[ZONE_NORMAL] = 0;
278 + free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
279 +#endif /* CONFIG_DISCONTIGMEM */
280 +
281 +}
282 +
283 +extern char _ftext, _etext, _fdata, _edata, _end;
284 +extern char __init_begin, __init_end;
285 +
286 +void __init mem_init(void)
287 +{
288 + int codesize, reservedpages, datasize, initsize;
289 + int tmp;
290 +
291 + max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
292 + high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
293 +
294 + /* free up the memory associated with Adam2 -
295 + * that is the, after the first page that is
296 + * reserved all the way up to the start of the kernel
297 + */
298 + free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
299 + (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
300 +
301 + /* this will put all low memory onto the freelists */
302 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
303 +
304 + /* Setup zeroed pages */
305 + totalram_pages -= setup_zero_pages();
306 +
307 +
308 +#ifdef CONFIG_DISCONTIGMEM
309 + totalram_pages += free_all_bootmem_node(NODE_DATA(1));
310 +#endif
311 + reservedpages = 0;
312 + for (tmp = 0; tmp < num_physpages; tmp++)
313 + /*
314 + * Only count reserved RAM pages
315 + */
316 + if (PageReserved(mem_map+tmp))
317 + reservedpages++;
318 +
319 + codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
320 + datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
321 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
322 +
323 + printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
324 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
325 + max_mapnr << (PAGE_SHIFT-10),
326 + codesize >> 10,
327 + reservedpages << (PAGE_SHIFT-10),
328 + datasize >> 10,
329 + initsize >> 10);
330 +
331 +}
332 +
333 +/* fixes paging routines for avalanche (utilized in /arch/mips/kernel/setup.c) */
334 +
335 +void avalanche_bootmem_init(void)
336 +{
337 + unsigned long start_pfn, max_pfn;
338 + unsigned long max_low_pfn;
339 + unsigned int memsize,memory_end,memory_start;
340 + char *memsize_str;
341 +
342 + memsize_str = prom_getenv("memsize");
343 + if (!memsize_str) {
344 + memsize = 0x02000000;
345 + } else {
346 + memsize = simple_strtol(memsize_str, NULL, 0);
347 + }
348 +
349 +
350 + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
351 + memory_end = memory_start + memsize;
352 +
353 + /*
354 + * Find the highest memory page fram number we have available
355 + */
356 +
357 + max_pfn = PFN_DOWN(__pa(memory_end));
358 +
359 + /*
360 + * Determine the low and high memory ranges
361 + */
362 +
363 + max_low_pfn = max_pfn;
364 +
365 + /*
366 + * Partially used pages are not usable - thus we are
367 + * rounding upwards:
368 + */
369 +
370 + start_pfn = PFN_UP(__pa(&_end));
371 +
372 + /*
373 + * Find a proper area for the bootmem bitmap. After this
374 + * bootstrap step all allocations (until the page allocator is
375 + * intact) must be done via bootmem_alloc().
376 + */
377 +
378 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
379 + __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
380 +
381 +
382 + /*
383 + * Register fully available low RAM pages with the bootmem allocator.
384 + */
385 +
386 + {
387 + unsigned long curr_pfn, last_pfn, pages;
388 +
389 + /*
390 + * We are rounding up the start address of usable memory:
391 + */
392 + curr_pfn = PFN_UP(__MEMORY_START);
393 +
394 + /*
395 + * ... and at the end of the usable range downwards:
396 + */
397 + last_pfn = PFN_DOWN(__pa(memory_end));
398 +
399 + if (last_pfn > max_low_pfn)
400 + last_pfn = max_low_pfn;
401 +
402 + pages = last_pfn - curr_pfn;
403 +
404 +
405 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
406 + PFN_PHYS(pages));
407 + }
408 +
409 + /*
410 + * Reserve the kernel text and
411 + * Reserve the bootmem bitmap. We do this in two steps (first step
412 + * was init_bootmem()), because this catches the (definitely buggy)
413 + * case of us accidentally initializing the bootmem allocator with
414 + * an invalid RAM area.
415 + */
416 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
417 + (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
418 +
419 + /*
420 + * reserve physical page 0 - it's a special BIOS page on many boxes,
421 + * enabling clean reboots, SMP operation, laptop functions.
422 + */
423 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
424 +}
425 +
426 +extern char __init_begin, __init_end;
427 +
428 +void free_initmem(void)
429 +{
430 + unsigned long addr;
431 + // prom_free_prom_memory ();
432 +
433 + addr = (unsigned long) &__init_begin;
434 + while (addr < (unsigned long) &__init_end) {
435 + ClearPageReserved(virt_to_page(addr));
436 + set_page_count(virt_to_page(addr), 1);
437 + free_page(addr);
438 + totalram_pages++;
439 + addr += PAGE_SIZE;
440 + }
441 + printk("Freeing unused kernel memory: %dk freed\n",
442 + (&__init_end - &__init_begin) >> 10);
443 +}
444 +
445 +void si_meminfo(struct sysinfo *val)
446 +{
447 + val->totalram = totalram_pages;
448 + val->sharedram = 0;
449 + val->freeram = nr_free_pages();
450 + val->bufferram = atomic_read(&buffermem_pages);
451 + val->totalhigh = 0;
452 + val->freehigh = nr_free_highpages();
453 + val->mem_unit = PAGE_SIZE;
454 +
455 + return;
456 +}
457 diff -urN linux-2.4.30/arch/mips/ar7/cmdline.c linux-2.4.30.current/arch/mips/ar7/cmdline.c
458 --- linux-2.4.30/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
459 +++ linux-2.4.30.current/arch/mips/ar7/cmdline.c 2005-06-12 20:14:28.000000000 +0200
460 @@ -0,0 +1,64 @@
461 +/*
462 + * Carsten Langgaard, carstenl@mips.com
463 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
464 + *
465 + * This program is free software; you can distribute it and/or modify it
466 + * under the terms of the GNU General Public License (Version 2) as
467 + * published by the Free Software Foundation.
468 + *
469 + * This program is distributed in the hope it will be useful, but WITHOUT
470 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
471 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
472 + * for more details.
473 + *
474 + * You should have received a copy of the GNU General Public License along
475 + * with this program; if not, write to the Free Software Foundation, Inc.,
476 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
477 + *
478 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
479 + */
480 +#include <linux/init.h>
481 +#include <linux/string.h>
482 +
483 +#include <asm/bootinfo.h>
484 +
485 +extern int prom_argc;
486 +extern int *_prom_argv;
487 +
488 +/*
489 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
490 + * This macro take care of sign extension.
491 + */
492 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
493 +
494 +char arcs_cmdline[CL_SIZE];
495 +
496 +char * __init prom_getcmdline(void)
497 +{
498 + return &(arcs_cmdline[0]);
499 +}
500 +
501 +
502 +void __init prom_init_cmdline(void)
503 +{
504 + char *cp;
505 + int actr;
506 +
507 + actr = 1; /* Always ignore argv[0] */
508 +
509 + cp = &(arcs_cmdline[0]);
510 +#ifdef CONFIG_CMDLINE_BOOL
511 + strcpy(cp, CONFIG_CMDLINE);
512 + cp += strlen(CONFIG_CMDLINE);
513 + *cp++ = ' ';
514 +#endif
515 + while(actr < prom_argc) {
516 + strcpy(cp, prom_argv(actr));
517 + cp += strlen(prom_argv(actr));
518 + *cp++ = ' ';
519 + actr++;
520 + }
521 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
522 + --cp;
523 + *cp = '\0';
524 +}
525 diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.current/arch/mips/ar7/init.c
526 --- linux-2.4.30/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
527 +++ linux-2.4.30.current/arch/mips/ar7/init.c 2005-06-12 20:14:28.000000000 +0200
528 @@ -0,0 +1,127 @@
529 +/*
530 + * Carsten Langgaard, carstenl@mips.com
531 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
532 + *
533 + * This program is free software; you can distribute it and/or modify it
534 + * under the terms of the GNU General Public License (Version 2) as
535 + * published by the Free Software Foundation.
536 + *
537 + * This program is distributed in the hope it will be useful, but WITHOUT
538 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
539 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
540 + * for more details.
541 + *
542 + * You should have received a copy of the GNU General Public License along
543 + * with this program; if not, write to the Free Software Foundation, Inc.,
544 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
545 + *
546 + * PROM library initialisation code.
547 + */
548 +#include <linux/config.h>
549 +#include <linux/init.h>
550 +#include <linux/string.h>
551 +#include <linux/kernel.h>
552 +
553 +#include <asm/io.h>
554 +#include <asm/mips-boards/prom.h>
555 +#include <asm/mips-boards/generic.h>
556 +
557 +/* Environment variable */
558 +typedef struct {
559 + char *name;
560 + char *val;
561 +} t_env_var;
562 +
563 +int prom_argc;
564 +int *_prom_argv, *_prom_envp;
565 +
566 +/*
567 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
568 + * This macro take care of sign extension, if running in 64-bit mode.
569 + */
570 +#define prom_envp(index) ((char *)(((int *)(int)_prom_envp)[(index)]))
571 +
572 +int init_debug = 0;
573 +
574 +char *prom_getenv(char *envname)
575 +{
576 + /*
577 + * Return a pointer to the given environment variable.
578 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
579 + * in the PROM structures are only 32-bit, so we need some
580 + * workarounds, if we are running in 64-bit mode.
581 + */
582 + int i, index=0;
583 +
584 + i = strlen(envname);
585 +
586 + while (prom_envp(index)) {
587 + if(strncmp(envname, prom_envp(index), i) == 0) {
588 + return(prom_envp(index+1));
589 + }
590 + index += 2;
591 + }
592 +
593 + return NULL;
594 +}
595 +
596 +static inline unsigned char str2hexnum(unsigned char c)
597 +{
598 + if (c >= '0' && c <= '9')
599 + return c - '0';
600 + if (c >= 'a' && c <= 'f')
601 + return c - 'a' + 10;
602 + return 0; /* foo */
603 +}
604 +
605 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
606 +{
607 + int i;
608 +
609 + for (i = 0; i < 6; i++) {
610 + unsigned char num;
611 +
612 + if((*str == '.') || (*str == ':'))
613 + str++;
614 + num = str2hexnum(*str++) << 4;
615 + num |= (str2hexnum(*str++));
616 + ea[i] = num;
617 + }
618 +}
619 +
620 +int get_ethernet_addr(char *ethernet_addr)
621 +{
622 + char *ethaddr_str;
623 +
624 + ethaddr_str = prom_getenv("ethaddr");
625 + if (!ethaddr_str) {
626 + printk("ethaddr not set in boot prom\n");
627 + return -1;
628 + }
629 + str2eaddr(ethernet_addr, ethaddr_str);
630 +
631 + if (init_debug > 1) {
632 + int i;
633 + printk("get_ethernet_addr: ");
634 + for (i=0; i<5; i++)
635 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
636 + printk("%02x\n", *(ethernet_addr+i));
637 + }
638 +
639 + return 0;
640 +}
641 +
642 +int __init prom_init(int argc, char **argv, char **envp)
643 +{
644 + prom_argc = argc;
645 + _prom_argv = (int *)argv;
646 + _prom_envp = (int *)envp;
647 +
648 + set_io_port_base(0);
649 +
650 + prom_printf("\nLINUX started...\n");
651 + prom_init_cmdline();
652 + prom_meminit();
653 +
654 + return 0;
655 +}
656 diff -urN linux-2.4.30/arch/mips/ar7/irq.c linux-2.4.30.current/arch/mips/ar7/irq.c
657 --- linux-2.4.30/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
658 +++ linux-2.4.30.current/arch/mips/ar7/irq.c 2005-06-12 20:14:28.000000000 +0200
659 @@ -0,0 +1,669 @@
660 +/*
661 + * Nitin Dhingra, iamnd@ti.com
662 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
663 + *
664 + * ########################################################################
665 + *
666 + * This program is free software; you can distribute it and/or modify it
667 + * under the terms of the GNU General Public License (Version 2) as
668 + * published by the Free Software Foundation.
669 + *
670 + * This program is distributed in the hope it will be useful, but WITHOUT
671 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
672 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
673 + * for more details.
674 + *
675 + * You should have received a copy of the GNU General Public License along
676 + * with this program; if not, write to the Free Software Foundation, Inc.,
677 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
678 + *
679 + * ########################################################################
680 + *
681 + * Routines for generic manipulation of the interrupts found on the Texas
682 + * Instruments avalanche board
683 + *
684 + */
685 +
686 +#include <linux/config.h>
687 +#include <linux/init.h>
688 +#include <linux/sched.h>
689 +#include <linux/slab.h>
690 +#include <linux/interrupt.h>
691 +#include <linux/kernel_stat.h>
692 +#include <linux/proc_fs.h>
693 +#include <asm/irq.h>
694 +#include <asm/mips-boards/prom.h>
695 +#include <asm/ar7/ar7.h>
696 +#include <asm/ar7/avalanche_intc.h>
697 +#include <asm/gdb-stub.h>
698 +
699 +
700 +#define shutdown_avalanche_irq disable_avalanche_irq
701 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
702 +
703 +static unsigned int startup_avalanche_irq(unsigned int irq);
704 +static void end_avalanche_irq(unsigned int irq);
705 +void enable_avalanche_irq(unsigned int irq_nr);
706 +void disable_avalanche_irq(unsigned int irq_nr);
707 +
708 +static struct hw_interrupt_type avalanche_irq_type = {
709 + "TI AVALANCHE",
710 + startup_avalanche_irq,
711 + shutdown_avalanche_irq,
712 + enable_avalanche_irq,
713 + disable_avalanche_irq,
714 + mask_and_ack_avalanche_irq,
715 + end_avalanche_irq,
716 + NULL
717 +};
718 +
719 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
720 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
721 +
722 +
723 +unsigned long spurious_count = 0;
724 +
725 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
726 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
727 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
728 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
729 +
730 +extern asmlinkage void mipsIRQ(void);
731 +
732 +
733 +/*
734 + * The avalanche/MIPS interrupt line numbers are used to represent the
735 + * interrupts within the irqaction arrays. The index notation is
736 + * is as follows:
737 + *
738 + * 0-7 MIPS CPU Exceptions (HW/SW)
739 + * 8-47 Primary Interrupts (Avalanche)
740 + * 48-79 Secondary Interrupts (Avalanche)
741 + *
742 + */
743 +
744 +
745 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
746 +{
747 + NULL, NULL, NULL, NULL,
748 + NULL, NULL, NULL, NULL,
749 + NULL, NULL, NULL, NULL,
750 + NULL, NULL, NULL, NULL,
751 + NULL, NULL, NULL, NULL,
752 + NULL, NULL, NULL, NULL,
753 + NULL, NULL, NULL, NULL,
754 + NULL, NULL, NULL, NULL,
755 + NULL, NULL, NULL, NULL,
756 + NULL, NULL, NULL, NULL
757 +};
758 +
759 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
760 +{
761 + NULL, NULL, NULL, NULL,
762 + NULL, NULL, NULL, NULL,
763 + NULL, NULL, NULL, NULL,
764 + NULL, NULL, NULL, NULL,
765 + NULL, NULL, NULL, NULL,
766 + NULL, NULL, NULL, NULL,
767 + NULL, NULL, NULL, NULL,
768 + NULL, NULL, NULL, NULL
769 +};
770 +
771 +/*
772 + This remaps interrupts to exist on other channels than the default
773 + channels. essentially we can use the line # as the index for this
774 + array
775 + */
776 +
777 +
778 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
779 +unsigned long uni_secondary_interrupt = 0;
780 +
781 +static struct irqaction r4ktimer_action = {
782 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
783 +};
784 +
785 +static struct irqaction *irq_action[8] = {
786 + NULL, /* SW int 0 */
787 + NULL, /* SW int 1 */
788 + NULL, /* HW int 0 */
789 + NULL,
790 + NULL,
791 + NULL, /* HW int 3 */
792 + NULL, /* HW int 4 */
793 + &r4ktimer_action /* HW int 5 */
794 +};
795 +
796 +static void end_avalanche_irq(unsigned int irq)
797 +{
798 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
799 + enable_avalanche_irq(irq);
800 +}
801 +
802 +void disable_avalanche_irq(unsigned int irq_nr)
803 +{
804 + unsigned long flags;
805 + unsigned long chan_nr=0;
806 + unsigned long int_bit=0;
807 +
808 + if(irq_nr >= AVALANCHE_INT_END)
809 + {
810 + printk("whee, invalid irq_nr %d\n", irq_nr);
811 + panic("IRQ, you lose...");
812 + }
813 +
814 + save_and_cli(flags);
815 +
816 +
817 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
818 + {
819 + /* disable mips exception */
820 +
821 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
822 + change_c0_status(ST0_IM,int_bit);
823 + restore_flags(flags);
824 + return;
825 + }
826 +
827 + /* irq_nr represents the line number for the interrupt. We must
828 + * disable the channel number associated with that line number.
829 + */
830 +
831 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
832 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
833 + else
834 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
835 +
836 + /* disable the interrupt channel bit */
837 +
838 + /* primary interrupt #'s 0-31 */
839 +
840 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
841 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
842 +
843 + /* primary interrupt #'s 32-39 */
844 +
845 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
846 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
847 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
848 +
849 + else /* secondary interrupt #'s 0-31 */
850 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
851 +
852 + restore_flags(flags);
853 +}
854 +
855 +void enable_avalanche_irq(unsigned int irq_nr)
856 +{
857 + unsigned long flags;
858 + unsigned long chan_nr=0;
859 + unsigned long int_bit=0;
860 +
861 + if(irq_nr > AVALANCHE_INT_END) {
862 + printk("whee, invalid irq_nr %d\n", irq_nr);
863 + panic("IRQ, you lose...");
864 + }
865 +
866 + save_and_cli(flags);
867 +
868 +
869 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
870 + {
871 + /* Enable MIPS exceptions */
872 + int_bit = read_c0_status();
873 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
874 + restore_flags(flags);
875 + return;
876 + }
877 +
878 + /* irq_nr represents the line number for the interrupt. We must
879 + * disable the channel number associated with that line number.
880 + */
881 +
882 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
883 + chan_nr = AVINTNUM(irq_nr);
884 + else
885 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
886 +
887 + /* enable the interrupt channel bit */
888 +
889 + /* primary interrupt #'s 0-31 */
890 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
891 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
892 +
893 + /* primary interrupt #'s 32 throuth 39 */
894 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
895 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
896 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
897 +
898 + else /* secondary interrupt #'s 0-31 */
899 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
900 +
901 + restore_flags(flags);
902 +}
903 +
904 +static unsigned int startup_avalanche_irq(unsigned int irq)
905 +{
906 + enable_avalanche_irq(irq);
907 + return 0; /* never anything pending */
908 +}
909 +
910 +
911 +int get_irq_list(char *buf)
912 +{
913 + int i, len = 0;
914 + int num = 0;
915 + struct irqaction *action;
916 +
917 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
918 + {
919 + action = irq_action[i];
920 + if (!action)
921 + continue;
922 + len += sprintf(buf+len, "%2d: %8d %c %s",
923 + num, kstat.irqs[0][num],
924 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
925 + action->name);
926 + for (action=action->next; action; action = action->next) {
927 + len += sprintf(buf+len, ",%s %s",
928 + (action->flags & SA_INTERRUPT) ? " +" : "",
929 + action->name);
930 + }
931 + len += sprintf(buf+len, " [MIPS interrupt]\n");
932 + }
933 +
934 +
935 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
936 + {
937 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
938 + action = hw0_irq_action_primary[i];
939 + else
940 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
941 + if (!action)
942 + continue;
943 + len += sprintf(buf+len, "%2d: %8d %c %s",
944 + num, kstat.irqs[0][ LNXINTNUM(i) ],
945 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
946 + action->name);
947 +
948 + for (action=action->next; action; action = action->next)
949 + {
950 + len += sprintf(buf+len, ",%s %s",
951 + (action->flags & SA_INTERRUPT) ? " +" : "",
952 + action->name);
953 + }
954 +
955 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
956 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
957 + else
958 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
959 +
960 + }
961 +
962 + return len;
963 +}
964 +
965 +int request_irq(unsigned int irq,
966 + void (*handler)(int, void *, struct pt_regs *),
967 + unsigned long irqflags,
968 + const char * devname,
969 + void *dev_id)
970 +{
971 + struct irqaction *action;
972 +
973 + if (irq > AVALANCHE_INT_END)
974 + return -EINVAL;
975 + if (!handler)
976 + return -EINVAL;
977 +
978 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
979 + if(!action)
980 + return -ENOMEM;
981 +
982 + action->handler = handler;
983 + action->flags = irqflags;
984 + action->mask = 0;
985 + action->name = devname;
986 + irq_desc_ti[irq].action = action;
987 + action->dev_id = dev_id;
988 +
989 + action->next = 0;
990 +
991 + if(irq < MIPS_EXCEPTION_OFFSET)
992 + {
993 + irq_action[irq] = action;
994 + enable_avalanche_irq(irq);
995 + return 0;
996 + }
997 +
998 + if(irq < AVALANCHE_INT_END_PRIMARY)
999 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
1000 + else
1001 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
1002 +
1003 + enable_avalanche_irq(irq);
1004 +
1005 + return 0;
1006 +}
1007 +
1008 +void free_irq(unsigned int irq, void *dev_id)
1009 +{
1010 + struct irqaction *action;
1011 +
1012 + if (irq > AVALANCHE_INT_END) {
1013 + printk("Trying to free IRQ%d\n",irq);
1014 + return;
1015 + }
1016 +
1017 + if(irq < MIPS_EXCEPTION_OFFSET)
1018 + {
1019 + action = irq_action[irq];
1020 + irq_action[irq] = NULL;
1021 + irq_desc_ti[irq].action = NULL;
1022 + disable_avalanche_irq(irq);
1023 + kfree(action);
1024 + return;
1025 + }
1026 +
1027 + if(irq < AVALANCHE_INT_END_PRIMARY) {
1028 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
1029 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
1030 + irq_desc_ti[irq].action = NULL;
1031 + }
1032 + else {
1033 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
1034 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
1035 + irq_desc_ti[irq].action = NULL;
1036 + }
1037 +
1038 + disable_avalanche_irq(irq);
1039 + kfree(action);
1040 +}
1041 +
1042 +#ifdef CONFIG_KGDB
1043 +extern void breakpoint(void);
1044 +extern int remote_debug;
1045 +#endif
1046 +
1047 +//void init_IRQ(void) __init;
1048 +void __init init_IRQ(void)
1049 +{
1050 + int i;
1051 +
1052 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
1053 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
1054 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
1055 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
1056 +
1057 + /* Disable interrupts and clear pending
1058 + */
1059 +
1060 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
1061 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
1062 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
1063 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
1064 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
1065 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
1066 +
1067 +
1068 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
1069 + /* hack for speeding up the pacing. */
1070 + printk("the pacing pre-scalar has been set as 600.\n");
1071 + avalanche_hw0_ipaceregs->ipacep = 600;
1072 + /* Channel to line mapping, Line to Channel mapping */
1073 +
1074 + for(i = 0; i < 40; i++)
1075 + avalanche_int_set(i,i);
1076 +
1077 + /* Now safe to set the exception vector. */
1078 + set_except_vector(0, mipsIRQ);
1079 +
1080 + /* Setup the IRQ description array. These will be mapped
1081 + * as flat interrupts numbers. The mapping is as follows
1082 + *
1083 + * 0-7 MIPS CPU Exceptions (HW/SW)
1084 + * 8-46 Primary Interrupts (Avalanche)
1085 + * 47-78 Secondary Interrupts (Avalanche)
1086 + */
1087 +
1088 + for (i = 0; i <= AVALANCHE_INT_END; i++)
1089 + {
1090 + irq_desc_ti[i].status = IRQ_DISABLED;
1091 + irq_desc_ti[i].action = 0;
1092 + irq_desc_ti[i].depth = 1;
1093 + irq_desc_ti[i].handler = &avalanche_irq_type;
1094 + }
1095 +
1096 +#ifdef CONFIG_KGDB
1097 + if (remote_debug)
1098 + {
1099 + set_debug_traps();
1100 + breakpoint();
1101 + }
1102 +#endif
1103 +}
1104 +
1105 +
1106 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
1107 +{
1108 + struct irqaction *action;
1109 + int irq, cpu = smp_processor_id();
1110 + unsigned long int_line_number,status;
1111 + int i,secondary = 0;
1112 + int chan_nr=0;
1113 +
1114 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
1115 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
1116 +
1117 +
1118 + if(chan_nr < 32)
1119 + {
1120 + if( chan_nr != uni_secondary_interrupt)
1121 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
1122 +
1123 + }
1124 +
1125 + if((chan_nr < 40) && (chan_nr > 31))
1126 + {
1127 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1128 + }
1129 +
1130 +
1131 + /* If the Priority Interrupt Index Register returns 40 then no
1132 + * interrupts are pending
1133 + */
1134 +
1135 + if(chan_nr == 40)
1136 + return;
1137 +
1138 + if(chan_nr == uni_secondary_interrupt)
1139 + {
1140 + status = avalanche_hw0_ecregs->exsr;
1141 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
1142 + {
1143 + if (status & 1<<i)
1144 + {
1145 + /* clear secondary interrupt */
1146 + avalanche_hw0_ecregs->excr = 1 << i;
1147 + break;
1148 + }
1149 + }
1150 + irq = i;
1151 + secondary = 1;
1152 +
1153 + /* clear the universal secondary interrupt */
1154 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
1155 +
1156 + }
1157 + else
1158 + irq = chan_nr;
1159 +
1160 + /* Suraj Add code to clear secondary interrupt */
1161 +
1162 + if(secondary)
1163 + action = hw0_irq_action_secondary[irq];
1164 + else
1165 + action = hw0_irq_action_primary[irq];
1166 +
1167 + /* if action == NULL, then we don't have a handler for the irq */
1168 +
1169 + if ( action == NULL ) {
1170 + printk("No handler for hw0 irq: %i\n", irq);
1171 + return;
1172 + }
1173 +
1174 + irq_enter(cpu,irq);
1175 + if(secondary)
1176 + {
1177 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
1178 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
1179 + }
1180 + else
1181 + {
1182 + kstat.irqs[0][irq + 8]++;
1183 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
1184 + }
1185 +
1186 + irq_exit(cpu,irq);
1187 +
1188 + if(softirq_pending(cpu))
1189 + do_softirq();
1190 +
1191 + return;
1192 +}
1193 +
1194 +void avalanche_int_set(int channel, int line)
1195 +{
1196 + switch(channel)
1197 + {
1198 + case(0):
1199 + avalanche_hw0_chregs->cintnr0 = line;
1200 + break;
1201 + case(1):
1202 + avalanche_hw0_chregs->cintnr1 = line;
1203 + break;
1204 + case(2):
1205 + avalanche_hw0_chregs->cintnr2 = line;
1206 + break;
1207 + case(3):
1208 + avalanche_hw0_chregs->cintnr3 = line;
1209 + break;
1210 + case(4):
1211 + avalanche_hw0_chregs->cintnr4 = line;
1212 + break;
1213 + case(5):
1214 + avalanche_hw0_chregs->cintnr5 = line;
1215 + break;
1216 + case(6):
1217 + avalanche_hw0_chregs->cintnr6 = line;
1218 + break;
1219 + case(7):
1220 + avalanche_hw0_chregs->cintnr7 = line;
1221 + break;
1222 + case(8):
1223 + avalanche_hw0_chregs->cintnr8 = line;
1224 + break;
1225 + case(9):
1226 + avalanche_hw0_chregs->cintnr9 = line;
1227 + break;
1228 + case(10):
1229 + avalanche_hw0_chregs->cintnr10 = line;
1230 + break;
1231 + case(11):
1232 + avalanche_hw0_chregs->cintnr11 = line;
1233 + break;
1234 + case(12):
1235 + avalanche_hw0_chregs->cintnr12 = line;
1236 + break;
1237 + case(13):
1238 + avalanche_hw0_chregs->cintnr13 = line;
1239 + break;
1240 + case(14):
1241 + avalanche_hw0_chregs->cintnr14 = line;
1242 + break;
1243 + case(15):
1244 + avalanche_hw0_chregs->cintnr15 = line;
1245 + break;
1246 + case(16):
1247 + avalanche_hw0_chregs->cintnr16 = line;
1248 + break;
1249 + case(17):
1250 + avalanche_hw0_chregs->cintnr17 = line;
1251 + break;
1252 + case(18):
1253 + avalanche_hw0_chregs->cintnr18 = line;
1254 + break;
1255 + case(19):
1256 + avalanche_hw0_chregs->cintnr19 = line;
1257 + break;
1258 + case(20):
1259 + avalanche_hw0_chregs->cintnr20 = line;
1260 + break;
1261 + case(21):
1262 + avalanche_hw0_chregs->cintnr21 = line;
1263 + break;
1264 + case(22):
1265 + avalanche_hw0_chregs->cintnr22 = line;
1266 + break;
1267 + case(23):
1268 + avalanche_hw0_chregs->cintnr23 = line;
1269 + break;
1270 + case(24):
1271 + avalanche_hw0_chregs->cintnr24 = line;
1272 + break;
1273 + case(25):
1274 + avalanche_hw0_chregs->cintnr25 = line;
1275 + break;
1276 + case(26):
1277 + avalanche_hw0_chregs->cintnr26 = line;
1278 + break;
1279 + case(27):
1280 + avalanche_hw0_chregs->cintnr27 = line;
1281 + break;
1282 + case(28):
1283 + avalanche_hw0_chregs->cintnr28 = line;
1284 + break;
1285 + case(29):
1286 + avalanche_hw0_chregs->cintnr29 = line;
1287 + break;
1288 + case(30):
1289 + avalanche_hw0_chregs->cintnr30 = line;
1290 + break;
1291 + case(31):
1292 + avalanche_hw0_chregs->cintnr31 = line;
1293 + break;
1294 + case(32):
1295 + avalanche_hw0_chregs->cintnr32 = line;
1296 + break;
1297 + case(33):
1298 + avalanche_hw0_chregs->cintnr33 = line;
1299 + break;
1300 + case(34):
1301 + avalanche_hw0_chregs->cintnr34 = line;
1302 + break;
1303 + case(35):
1304 + avalanche_hw0_chregs->cintnr35 = line;
1305 + break;
1306 + case(36):
1307 + avalanche_hw0_chregs->cintnr36 = line;
1308 + break;
1309 + case(37):
1310 + avalanche_hw0_chregs->cintnr37 = line;
1311 + break;
1312 + case(38):
1313 + avalanche_hw0_chregs->cintnr38 = line;
1314 + break;
1315 + case(39):
1316 + avalanche_hw0_chregs->cintnr39 = line;
1317 + break;
1318 + default:
1319 + printk("Error: Unknown Avalanche interrupt channel\n");
1320 + }
1321 +
1322 + line_to_channel[line] = channel; /* Suraj check */
1323 +
1324 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
1325 + uni_secondary_interrupt = line;
1326 +
1327 +}
1328 +
1329 diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.current/arch/mips/ar7/memory.c
1330 --- linux-2.4.30/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
1331 +++ linux-2.4.30.current/arch/mips/ar7/memory.c 2005-06-12 20:14:28.000000000 +0200
1332 @@ -0,0 +1,130 @@
1333 +/*
1334 + * Carsten Langgaard, carstenl@mips.com
1335 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1336 + *
1337 + * ########################################################################
1338 + *
1339 + * This program is free software; you can distribute it and/or modify it
1340 + * under the terms of the GNU General Public License (Version 2) as
1341 + * published by the Free Software Foundation.
1342 + *
1343 + * This program is distributed in the hope it will be useful, but WITHOUT
1344 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1345 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1346 + * for more details.
1347 + *
1348 + * You should have received a copy of the GNU General Public License along
1349 + * with this program; if not, write to the Free Software Foundation, Inc.,
1350 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1351 + *
1352 + * ########################################################################
1353 + *
1354 + * PROM library functions for acquiring/using memory descriptors given to
1355 + * us from the YAMON.
1356 + *
1357 + */
1358 +#include <linux/config.h>
1359 +#include <linux/init.h>
1360 +#include <linux/mm.h>
1361 +#include <linux/bootmem.h>
1362 +
1363 +#include <asm/bootinfo.h>
1364 +#include <asm/page.h>
1365 +#include <asm/mips-boards/prom.h>
1366 +#include <asm/ar7/ar7.h>
1367 +
1368 +enum yamon_memtypes {
1369 + yamon_dontuse,
1370 + yamon_prom,
1371 + yamon_free,
1372 +};
1373 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1374 +
1375 +/* References to section boundaries */
1376 +extern char _end;
1377 +
1378 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1379 +
1380 +
1381 +struct prom_pmemblock * __init prom_getmdesc(void)
1382 +{
1383 + char *memsize_str;
1384 + unsigned int memsize;
1385 +
1386 + memsize_str = prom_getenv("memsize");
1387 + if (!memsize_str) {
1388 + memsize = 0x02000000;
1389 + } else {
1390 + memsize = simple_strtol(memsize_str, NULL, 0);
1391 + }
1392 +
1393 + memset(mdesc, 0, sizeof(mdesc));
1394 +
1395 + mdesc[0].type = yamon_dontuse;
1396 + mdesc[0].base = 0x00000000;
1397 + mdesc[0].size = AVALANCHE_SDRAM_BASE;
1398 +
1399 + mdesc[1].type = yamon_prom;
1400 + mdesc[1].base = AVALANCHE_SDRAM_BASE;
1401 + mdesc[1].size = 0x00020000;
1402 +
1403 + mdesc[2].type = yamon_free;
1404 + mdesc[2].base = AVALANCHE_SDRAM_BASE + 0x00020000;
1405 + mdesc[2].size = (memsize + AVALANCHE_SDRAM_BASE) - mdesc[2].base;
1406 +
1407 + return &mdesc[0];
1408 +}
1409 +
1410 +static int __init prom_memtype_classify (unsigned int type)
1411 +{
1412 + switch (type) {
1413 + case yamon_free:
1414 + return BOOT_MEM_RAM;
1415 + case yamon_prom:
1416 + return BOOT_MEM_ROM_DATA;
1417 + default:
1418 + return BOOT_MEM_RESERVED;
1419 + }
1420 +}
1421 +
1422 +void __init prom_meminit(void)
1423 +{
1424 + struct prom_pmemblock *p;
1425 +
1426 + p = prom_getmdesc();
1427 +
1428 + while (p->size) {
1429 + long type;
1430 + unsigned long base, size;
1431 +
1432 + type = prom_memtype_classify (p->type);
1433 + base = p->base;
1434 + size = p->size;
1435 +
1436 + add_memory_region(base, size, type);
1437 + p++;
1438 + }
1439 +}
1440 +
1441 +void __init prom_free_prom_memory (void)
1442 +{
1443 + int i;
1444 + unsigned long freed = 0;
1445 + unsigned long addr;
1446 +
1447 + for (i = 0; i < boot_mem_map.nr_map; i++) {
1448 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1449 + continue;
1450 +
1451 + addr = boot_mem_map.map[i].addr;
1452 + while (addr < boot_mem_map.map[i].addr
1453 + + boot_mem_map.map[i].size) {
1454 + ClearPageReserved(virt_to_page(__va(addr)));
1455 + set_page_count(virt_to_page(__va(addr)), 1);
1456 + free_page((unsigned long)__va(addr));
1457 + addr += PAGE_SIZE;
1458 + freed += PAGE_SIZE;
1459 + }
1460 + }
1461 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1462 +}
1463 diff -urN linux-2.4.30/arch/mips/ar7/mipsIRQ.S linux-2.4.30.current/arch/mips/ar7/mipsIRQ.S
1464 --- linux-2.4.30/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
1465 +++ linux-2.4.30.current/arch/mips/ar7/mipsIRQ.S 2005-06-12 20:14:28.000000000 +0200
1466 @@ -0,0 +1,120 @@
1467 +/*
1468 + * Carsten Langgaard, carstenl@mips.com
1469 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
1470 + *
1471 + * ########################################################################
1472 + *
1473 + * This program is free software; you can distribute it and/or modify it
1474 + * under the terms of the GNU General Public License (Version 2) as
1475 + * published by the Free Software Foundation.
1476 + *
1477 + * This program is distributed in the hope it will be useful, but WITHOUT
1478 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1479 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1480 + * for more details.
1481 + *
1482 + * You should have received a copy of the GNU General Public License along
1483 + * with this program; if not, write to the Free Software Foundation, Inc.,
1484 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1485 + *
1486 + * ########################################################################
1487 + *
1488 + * Interrupt exception dispatch code.
1489 + *
1490 + */
1491 +#include <linux/config.h>
1492 +
1493 +#include <asm/asm.h>
1494 +#include <asm/mipsregs.h>
1495 +#include <asm/regdef.h>
1496 +#include <asm/stackframe.h>
1497 +
1498 +/* A lot of complication here is taken away because:
1499 + *
1500 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1501 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
1502 + * common case is one pending IRQ so optimize in that direction.
1503 + *
1504 + * 2) We need not check against bits in the status register IRQ mask, that
1505 + * would make this routine slow as hell.
1506 + *
1507 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1508 + * between like BSD spl() brain-damage.
1509 + *
1510 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1511 + * IRQs which we don't use at all and all external interrupt sources are
1512 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1513 + *
1514 + * MIPS IRQ Source
1515 + * -------- ------
1516 + * 0 Software (ignored)
1517 + * 1 Software (ignored)
1518 + * 2 Combined hardware interrupt (hw0)
1519 + * 3 Hardware (ignored)
1520 + * 4 Hardware (ignored)
1521 + * 5 Hardware (ignored)
1522 + * 6 Hardware (ignored)
1523 + * 7 R4k timer (what we use)
1524 + *
1525 + * Note: On the SEAD board thing are a little bit different.
1526 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1527 + * wired to UART1.
1528 + *
1529 + * We handle the IRQ according to _our_ priority which is:
1530 + *
1531 + * Highest ---- R4k Timer
1532 + * Lowest ---- Combined hardware interrupt
1533 + *
1534 + * then we just return, if multiple IRQs are pending then we will just take
1535 + * another exception, big deal.
1536 + */
1537 +
1538 +.text
1539 +.set noreorder
1540 +.set noat
1541 + .align 5
1542 +NESTED(mipsIRQ, PT_SIZE, sp)
1543 + SAVE_ALL
1544 + CLI
1545 + .set at
1546 +
1547 + mfc0 s0, CP0_CAUSE # get irq bits
1548 +
1549 + /* First we check for r4k counter/timer IRQ. */
1550 + andi a0, s0, CAUSEF_IP7
1551 + beq a0, zero, 1f
1552 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
1553 +
1554 + /* Wheee, a timer interrupt. */
1555 + move a0, sp
1556 + jal ar7_timer_interrupt
1557 + nop
1558 +
1559 + j ret_from_irq
1560 + nop
1561 +
1562 + 1:
1563 + beq a0, zero, 1f # delay slot, check hw3 interrupt
1564 + nop
1565 +
1566 + /* Wheee, combined hardware level zero interrupt. */
1567 + jal avalanche_hw0_irqdispatch
1568 + move a0, sp # delay slot
1569 +
1570 + j ret_from_irq
1571 + nop # delay slot
1572 +
1573 + 1:
1574 + /*
1575 + * Here by mistake? This is possible, what can happen is that by the
1576 + * time we take the exception the IRQ pin goes low, so just leave if
1577 + * this is the case.
1578 + */
1579 + move a1,s0
1580 + PRINT("Got interrupt: c0_cause = %08x\n")
1581 + mfc0 a1, CP0_EPC
1582 + PRINT("c0_epc = %08x\n")
1583 +
1584 + j ret_from_irq
1585 + nop
1586 +END(mipsIRQ)
1587 diff -urN linux-2.4.30/arch/mips/ar7/printf.c linux-2.4.30.current/arch/mips/ar7/printf.c
1588 --- linux-2.4.30/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
1589 +++ linux-2.4.30.current/arch/mips/ar7/printf.c 2005-06-12 20:14:28.000000000 +0200
1590 @@ -0,0 +1,51 @@
1591 +/*
1592 + * Carsten Langgaard, carstenl@mips.com
1593 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1594 + *
1595 + * This program is free software; you can distribute it and/or modify it
1596 + * under the terms of the GNU General Public License (Version 2) as
1597 + * published by the Free Software Foundation.
1598 + *
1599 + * This program is distributed in the hope it will be useful, but WITHOUT
1600 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1601 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1602 + * for more details.
1603 + *
1604 + * You should have received a copy of the GNU General Public License along
1605 + * with this program; if not, write to the Free Software Foundation, Inc.,
1606 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1607 + *
1608 + * Putting things on the screen/serial line using Adam2 facilities.
1609 + */
1610 +
1611 +#include <linux/config.h>
1612 +#include <linux/init.h>
1613 +#include <linux/kernel.h>
1614 +#include <linux/serial_reg.h>
1615 +#include <linux/spinlock.h>
1616 +#include <asm/io.h>
1617 +#include <asm/serial.h>
1618 +#include <asm/addrspace.h>
1619 +#include <asm/ar7/ar7.h>
1620 +
1621 +static char ppbuf[1024];
1622 +
1623 +void (*prom_print_str)(unsigned int out, char *s, int len);
1624 +
1625 +void prom_printf(char *fmt, ...) __init;
1626 +void prom_printf(char *fmt, ...)
1627 +{
1628 + va_list args;
1629 + int len;
1630 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
1631 +
1632 + va_start(args, fmt);
1633 + vsprintf(ppbuf, fmt, args);
1634 + len = strlen(ppbuf);
1635 +
1636 + prom_print_str(1, ppbuf, len);
1637 +
1638 + va_end(args);
1639 + return;
1640 +
1641 +}
1642 diff -urN linux-2.4.30/arch/mips/ar7/reset.c linux-2.4.30.current/arch/mips/ar7/reset.c
1643 --- linux-2.4.30/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
1644 +++ linux-2.4.30.current/arch/mips/ar7/reset.c 2005-06-12 20:14:28.000000000 +0200
1645 @@ -0,0 +1,54 @@
1646 +/*
1647 + * Carsten Langgaard, carstenl@mips.com
1648 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1649 + *
1650 + * ########################################################################
1651 + *
1652 + * This program is free software; you can distribute it and/or modify it
1653 + * under the terms of the GNU General Public License (Version 2) as
1654 + * published by the Free Software Foundation.
1655 + *
1656 + * This program is distributed in the hope it will be useful, but WITHOUT
1657 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1658 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1659 + * for more details.
1660 + *
1661 + * You should have received a copy of the GNU General Public License along
1662 + * with this program; if not, write to the Free Software Foundation, Inc.,
1663 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1664 + *
1665 + * ########################################################################
1666 + *
1667 + * Reset the MIPS boards.
1668 + *
1669 + */
1670 +#include <linux/config.h>
1671 +
1672 +#include <asm/reboot.h>
1673 +#include <asm/mips-boards/generic.h>
1674 +
1675 +static void ar7_machine_restart(char *command);
1676 +static void ar7_machine_halt(void);
1677 +static void ar7_machine_power_off(void);
1678 +
1679 +static void ar7_machine_restart(char *command)
1680 +{
1681 +
1682 +}
1683 +
1684 +static void ar7_machine_halt(void)
1685 +{
1686 +
1687 +}
1688 +
1689 +static void ar7_machine_power_off(void)
1690 +{
1691 +
1692 +}
1693 +
1694 +void ar7_reboot_setup(void)
1695 +{
1696 + _machine_restart = ar7_machine_restart;
1697 + _machine_halt = ar7_machine_halt;
1698 + _machine_power_off = ar7_machine_power_off;
1699 +}
1700 diff -urN linux-2.4.30/arch/mips/ar7/setup.c linux-2.4.30.current/arch/mips/ar7/setup.c
1701 --- linux-2.4.30/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
1702 +++ linux-2.4.30.current/arch/mips/ar7/setup.c 2005-06-12 20:14:28.000000000 +0200
1703 @@ -0,0 +1,150 @@
1704 +/*
1705 + * Carsten Langgaard, carstenl@mips.com
1706 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
1707 + *
1708 + * This program is free software; you can distribute it and/or modify it
1709 + * under the terms of the GNU General Public License (Version 2) as
1710 + * published by the Free Software Foundation.
1711 + *
1712 + * This program is distributed in the hope it will be useful, but WITHOUT
1713 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1714 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1715 + * for more details.
1716 + *
1717 + * You should have received a copy of the GNU General Public License along
1718 + * with this program; if not, write to the Free Software Foundation, Inc.,
1719 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1720 + */
1721 +#include <linux/config.h>
1722 +#include <linux/init.h>
1723 +#include <linux/sched.h>
1724 +#include <linux/mc146818rtc.h>
1725 +#include <linux/ioport.h>
1726 +
1727 +#include <asm/cpu.h>
1728 +#include <asm/bootinfo.h>
1729 +#include <asm/irq.h>
1730 +#include <asm/mips-boards/generic.h>
1731 +#include <asm/mips-boards/prom.h>
1732 +
1733 +#include <asm/dma.h>
1734 +#include <asm/time.h>
1735 +#include <asm/traps.h>
1736 +
1737 +
1738 +#define _LINK_KSEG0_
1739 +#define LITTLE_ENDIAN
1740 +#include <asm/ar7/tnetd73xx.h>
1741 +#include <asm/ar7/tnetd73xx_misc.h>
1742 +
1743 +// Specific for ar7wrd
1744 +unsigned int tnetd73xx_vbus_freq;
1745 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
1746 +#define AFECLK_FREQ 35328000
1747 +#define REFCLK_FREQ 25000000
1748 +#define OSC3_FREQ 24000000
1749 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
1750 +
1751 +#if defined(CONFIG_AR7_MARVELL)
1752 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
1753 +#else
1754 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
1755 +#endif
1756 +
1757 +
1758 +#ifdef CONFIG_KGDB
1759 +extern void rs_kgdb_hook(int);
1760 +int remote_debug = 0;
1761 +#endif
1762 +
1763 +extern struct rtc_ops no_rtc_ops;
1764 +
1765 +extern void ar7_reboot_setup(void);
1766 +
1767 +extern void ar7_time_init(void);
1768 +extern void ar7_timer_setup(struct irqaction *irq);
1769 +
1770 +/* maybe some of this is not needed? */
1771 +static void ar7_platform_init(void)
1772 +{
1773 + //tnetd73xx_gpio_init();
1774 +
1775 + tnetd73xx_reset_ctrl(RESET_MODULE_UART0, OUT_OF_RESET);
1776 + //tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
1777 + //REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0);
1778 +
1779 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, IN_RESET);
1780 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, OUT_OF_RESET);
1781 +
1782 + tnetd73xx_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ);
1783 +
1784 + tnetd73xx_vbus_freq = tnetd73xx_clkc_get_freq(CLKC_SYS) / 2;
1785 +
1786 +#if defined(CONFIG_AR7WRD)
1787 + if(! (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE)) {
1788 + tnetd73xx_clkc_set_freq(CLKC_MIPS, CLK_MHZ(150));
1789 + }
1790 +#endif
1791 +
1792 +}
1793 +
1794 +const char *get_system_type(void)
1795 +{
1796 + return "Texas Instruments AR7";
1797 +}
1798 +
1799 +void __init ar7_setup(void)
1800 +{
1801 +#ifdef CONFIG_KGDB
1802 + int rs_putDebugChar(char);
1803 + char rs_getDebugChar(void);
1804 + extern int (*generic_putDebugChar)(char);
1805 + extern char (*generic_getDebugChar)(void);
1806 +#endif
1807 + char *argptr;
1808 +
1809 +#ifdef CONFIG_SERIAL_CONSOLE
1810 + argptr = prom_getcmdline();
1811 + if ((argptr = strstr(argptr, "console=")) == NULL) {
1812 + argptr = prom_getcmdline();
1813 + strcat(argptr, " console=ttyS0,38400");
1814 + }
1815 +#endif
1816 +
1817 +#ifdef CONFIG_KGDB
1818 + argptr = prom_getcmdline();
1819 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1820 + int line;
1821 + argptr += strlen("kgdb=ttyS");
1822 + if (*argptr != '0' && *argptr != '1')
1823 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
1824 + "falling back to /dev/ttyS1\n", *argptr);
1825 + line = *argptr == '0' ? 0 : 1;
1826 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1827 + line ? 1 : 0);
1828 +
1829 + rs_kgdb_hook(line);
1830 + generic_putDebugChar = rs_putDebugChar;
1831 + generic_getDebugChar = rs_getDebugChar;
1832 +
1833 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1834 + "please connect your debugger\n", line ? 1 : 0);
1835 +
1836 + remote_debug = 1;
1837 + /* Breakpoints are in init_IRQ() */
1838 + }
1839 +#endif
1840 +
1841 + argptr = prom_getcmdline();
1842 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
1843 + cpu_data[0].options &= ~MIPS_CPU_FPU;
1844 +
1845 + rtc_ops = &no_rtc_ops;
1846 +
1847 + ar7_platform_init();
1848 +
1849 + ar7_reboot_setup();
1850 +
1851 + board_time_init = ar7_time_init;
1852 + board_timer_setup = ar7_timer_setup;
1853 +}
1854 diff -urN linux-2.4.30/arch/mips/ar7/time.c linux-2.4.30.current/arch/mips/ar7/time.c
1855 --- linux-2.4.30/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
1856 +++ linux-2.4.30.current/arch/mips/ar7/time.c 2005-06-12 20:14:28.000000000 +0200
1857 @@ -0,0 +1,125 @@
1858 +/*
1859 + * Carsten Langgaard, carstenl@mips.com
1860 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1861 + *
1862 + * ########################################################################
1863 + *
1864 + * This program is free software; you can distribute it and/or modify it
1865 + * under the terms of the GNU General Public License (Version 2) as
1866 + * published by the Free Software Foundation.
1867 + *
1868 + * This program is distributed in the hope it will be useful, but WITHOUT
1869 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1870 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1871 + * for more details.
1872 + *
1873 + * You should have received a copy of the GNU General Public License along
1874 + * with this program; if not, write to the Free Software Foundation, Inc.,
1875 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1876 + *
1877 + * ########################################################################
1878 + *
1879 + * Setting up the clock on the MIPS boards.
1880 + *
1881 + */
1882 +
1883 +#include <linux/types.h>
1884 +#include <linux/config.h>
1885 +#include <linux/init.h>
1886 +#include <linux/kernel_stat.h>
1887 +#include <linux/sched.h>
1888 +#include <linux/spinlock.h>
1889 +
1890 +#include <asm/mipsregs.h>
1891 +#include <asm/ptrace.h>
1892 +#include <asm/hardirq.h>
1893 +#include <asm/div64.h>
1894 +
1895 +#include <linux/interrupt.h>
1896 +#include <linux/mc146818rtc.h>
1897 +#include <linux/timex.h>
1898 +
1899 +#include <asm/mips-boards/generic.h>
1900 +#include <asm/mips-boards/prom.h>
1901 +#include <asm/ar7/ar7.h>
1902 +
1903 +extern asmlinkage void mipsIRQ(void);
1904 +
1905 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
1906 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1907 +
1908 +#define MIPS_CPU_TIMER_IRQ 7
1909 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1910 +
1911 +static inline void ack_r4ktimer(unsigned long newval)
1912 +{
1913 + write_c0_compare(newval);
1914 +}
1915 +
1916 +void ar7_timer_interrupt(struct pt_regs *regs)
1917 +{
1918 + int cpu = smp_processor_id();
1919 +
1920 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
1921 +
1922 + if (r4k_offset == 0)
1923 + goto null;
1924 +
1925 + do {
1926 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
1927 + do_timer(regs);
1928 + r4k_cur += r4k_offset;
1929 + ack_r4ktimer(r4k_cur);
1930 +
1931 + } while (((unsigned long)read_c0_count()
1932 + - r4k_cur) < 0x7fffffff);
1933 +
1934 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
1935 +
1936 + if (softirq_pending(cpu))
1937 + do_softirq();
1938 +
1939 + return;
1940 +
1941 +null:
1942 + ack_r4ktimer(0);
1943 +}
1944 +
1945 +/*
1946 + * Figure out the r4k offset, the amount to increment the compare
1947 + * register for each time tick.
1948 + */
1949 +static unsigned long __init cal_r4koff(void)
1950 +{
1951 + return ((CONFIG_AR7_FREQUENCY*500000)/HZ);
1952 +}
1953 +
1954 +void __init ar7_time_init(void)
1955 +{
1956 + unsigned long flags;
1957 + unsigned int est_freq;
1958 +
1959 + set_except_vector(0, mipsIRQ);
1960 + write_c0_count(0);
1961 +
1962 + printk("calculating r4koff... ");
1963 + r4k_offset = cal_r4koff();
1964 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1965 +
1966 + est_freq = 2*r4k_offset*HZ;
1967 + est_freq += 5000; /* round */
1968 + est_freq -= est_freq%10000;
1969 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1970 + (est_freq%1000000)*100/1000000);
1971 +}
1972 +
1973 +void __init ar7_timer_setup(struct irqaction *irq)
1974 +{
1975 + /* we are using the cpu counter for timer interrupts */
1976 + irq->handler = no_action; /* we use our own handler */
1977 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1978 +
1979 + r4k_cur = (read_c0_count() + r4k_offset);
1980 + write_c0_compare(r4k_cur);
1981 + set_c0_status(ALLINTS);
1982 +}
1983 diff -urN linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c linux-2.4.30.current/arch/mips/ar7/tnetd73xx_misc.c
1984 --- linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
1985 +++ linux-2.4.30.current/arch/mips/ar7/tnetd73xx_misc.c 2005-06-12 20:14:28.000000000 +0200
1986 @@ -0,0 +1,924 @@
1987 +/******************************************************************************
1988 + * FILE PURPOSE: TNETD73xx Misc modules API Source
1989 + ******************************************************************************
1990 + * FILE NAME: tnetd73xx_misc.c
1991 + *
1992 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
1993 + * FSER Modules API
1994 + * As per TNETD73xx specifications
1995 + *
1996 + * REVISION HISTORY:
1997 + * 27 Nov 02 - Sharath Kumar PSP TII
1998 + * 14 Feb 03 - Anant Gole PSP TII
1999 + *
2000 + * (C) Copyright 2002, Texas Instruments, Inc
2001 + *******************************************************************************/
2002 +
2003 +#define LITTLE_ENDIAN
2004 +#define _LINK_KSEG0_
2005 +
2006 +#include <linux/types.h>
2007 +#include <asm/ar7/tnetd73xx.h>
2008 +#include <asm/ar7/tnetd73xx_misc.h>
2009 +
2010 +/* TNETD73XX Revision */
2011 +u32 tnetd73xx_get_revision(void)
2012 +{
2013 + /* Read Chip revision register - This register is from GPIO module */
2014 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2015 +}
2016 +
2017 +/*****************************************************************************
2018 + * Reset Control Module
2019 + *****************************************************************************/
2020 +
2021 +
2022 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2023 +{
2024 + u32 reset_status;
2025 +
2026 + /* read current reset register */
2027 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2028 +
2029 + if (reset_ctrl == OUT_OF_RESET)
2030 + {
2031 + /* bring module out of reset */
2032 + reset_status |= (1 << reset_module);
2033 + }
2034 + else
2035 + {
2036 + /* put module in reset */
2037 + reset_status &= (~(1 << reset_module));
2038 + }
2039 +
2040 + /* write to the reset register */
2041 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2042 +}
2043 +
2044 +
2045 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2046 +{
2047 + u32 reset_status;
2048 +
2049 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2050 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2051 +}
2052 +
2053 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2054 +{
2055 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2056 +}
2057 +
2058 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2059 +
2060 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2061 +{
2062 + u32 sys_reset_status;
2063 +
2064 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2065 +
2066 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2067 +}
2068 +
2069 +
2070 +/*****************************************************************************
2071 + * Power Control Module
2072 + *****************************************************************************/
2073 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2074 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2075 +
2076 +
2077 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2078 +{
2079 + u32 power_status;
2080 +
2081 + /* read current power down control register */
2082 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2083 +
2084 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2085 + {
2086 + /* power down the module */
2087 + power_status |= (1 << power_module);
2088 + }
2089 + else
2090 + {
2091 + /* power on the module */
2092 + power_status &= (~(1 << power_module));
2093 + }
2094 +
2095 + /* write to the reset register */
2096 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2097 +}
2098 +
2099 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2100 +{
2101 + u32 power_status;
2102 +
2103 + /* read current power down control register */
2104 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2105 +
2106 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2107 +}
2108 +
2109 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2110 +{
2111 + u32 power_status;
2112 +
2113 + /* read current power down control register */
2114 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2115 +
2116 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2117 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2118 +
2119 + /* write to power down control register */
2120 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2121 +}
2122 +
2123 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2124 +{
2125 + u32 power_status;
2126 +
2127 + /* read current power down control register */
2128 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2129 +
2130 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2131 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2132 +
2133 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2134 +}
2135 +
2136 +
2137 +/*****************************************************************************
2138 + * Wakeup Control
2139 + *****************************************************************************/
2140 +
2141 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2142 +
2143 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2144 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2145 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2146 +{
2147 + u32 wakeup_status;
2148 +
2149 + /* read the wakeup control register */
2150 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2151 +
2152 + /* enable/disable */
2153 + if (wakeup_ctrl == WAKEUP_ENABLED)
2154 + {
2155 + /* enable wakeup */
2156 + wakeup_status |= wakeup_int;
2157 + }
2158 + else
2159 + {
2160 + /* disable wakeup */
2161 + wakeup_status &= (~wakeup_int);
2162 + }
2163 +
2164 + /* set polarity */
2165 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2166 + {
2167 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2168 + }
2169 + else
2170 + {
2171 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2172 + }
2173 +
2174 + /* write the wakeup control register */
2175 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2176 +}
2177 +
2178 +
2179 +/*****************************************************************************
2180 + * FSER Control
2181 + *****************************************************************************/
2182 +
2183 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2184 +{
2185 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2186 +}
2187 +
2188 +/*****************************************************************************
2189 + * Clock Control
2190 + *****************************************************************************/
2191 +
2192 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2193 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2194 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2195 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2196 +
2197 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2198 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2199 +
2200 +#define CLKC_PRE_DIVIDER 0x0000001F
2201 +#define CLKC_POST_DIVIDER 0x001F0000
2202 +
2203 +#define CLKC_PLL_STATUS 0x1
2204 +#define CLKC_PLL_FACTOR 0x0000F000
2205 +
2206 +#define BOOTCR_PLL_BYPASS (1 << 5)
2207 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2208 +
2209 +#define MIPS_PLL_SELECT 0x00030000
2210 +#define SYSTEM_PLL_SELECT 0x0000C000
2211 +#define USB_PLL_SELECT 0x000C0000
2212 +#define ADSLSS_PLL_SELECT 0x00C00000
2213 +
2214 +#define MIPS_AFECLKI_SELECT 0x00000000
2215 +#define MIPS_REFCLKI_SELECT 0x00010000
2216 +#define MIPS_XTAL3IN_SELECT 0x00020000
2217 +
2218 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2219 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2220 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2221 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2222 +
2223 +#define USB_SYSPLL_SELECT 0x00000000
2224 +#define USB_REFCLKI_SELECT 0x00040000
2225 +#define USB_XTAL3IN_SELECT 0x00080000
2226 +#define USB_MIPSPLL_SELECT 0x000C0000
2227 +
2228 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2229 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2230 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2231 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2232 +
2233 +#define SYS_MAX CLK_MHZ(150)
2234 +#define SYS_MIN CLK_MHZ(1)
2235 +
2236 +#define MIPS_SYNC_MAX SYS_MAX
2237 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2238 +#define MIPS_MIN CLK_MHZ(1)
2239 +
2240 +#define USB_MAX CLK_MHZ(100)
2241 +#define USB_MIN CLK_MHZ(1)
2242 +
2243 +#define ADSL_MAX CLK_MHZ(180)
2244 +#define ADSL_MIN CLK_MHZ(1)
2245 +
2246 +#define PLL_MUL_MAXFACTOR 15
2247 +#define MAX_DIV_VALUE 32
2248 +#define MIN_DIV_VALUE 1
2249 +
2250 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2251 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2252 +
2253 +#define DIVIDER_LOCK_TIME 10100
2254 +#define PLL_LOCK_TIME 10100 * 75
2255 +
2256 +
2257 +
2258 + /****************************************************************************
2259 + * DATA PURPOSE: PRIVATE Variables
2260 + **************************************************************************/
2261 + static u32 *clk_src[4];
2262 + static u32 mips_pll_out;
2263 + static u32 sys_pll_out;
2264 + static u32 afeclk_inp;
2265 + static u32 refclk_inp;
2266 + static u32 xtal_inp;
2267 + static u32 present_min;
2268 + static u32 present_max;
2269 +
2270 + /* Forward References */
2271 + static u32 find_gcd(u32 min, u32 max);
2272 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2273 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2274 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2275 + static void find_approx(u32 *,u32 *,u32);
2276 +
2277 + /****************************************************************************
2278 + * FUNCTION: tnetd73xx_clkc_init
2279 + ****************************************************************************
2280 + * Description: The routine initializes the internal variables depending on
2281 + * on the sources selected for different clocks.
2282 + ***************************************************************************/
2283 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2284 +{
2285 +
2286 + u32 choice;
2287 +
2288 + afeclk_inp = afeclk;
2289 + refclk_inp = refclk;
2290 + xtal_inp = xtal3in;
2291 +
2292 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2293 + switch(choice)
2294 + {
2295 + case MIPS_AFECLKI_SELECT:
2296 + clk_src[CLKC_MIPS] = &afeclk_inp;
2297 + break;
2298 +
2299 + case MIPS_REFCLKI_SELECT:
2300 + clk_src[CLKC_MIPS] = &refclk_inp;
2301 + break;
2302 +
2303 + case MIPS_XTAL3IN_SELECT:
2304 + clk_src[CLKC_MIPS] = &xtal_inp;
2305 + break;
2306 +
2307 + default :
2308 + clk_src[CLKC_MIPS] = 0;
2309 +
2310 + }
2311 +
2312 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2313 + switch(choice)
2314 + {
2315 + case SYSTEM_AFECLKI_SELECT:
2316 + clk_src[CLKC_SYS] = &afeclk_inp;
2317 + break;
2318 +
2319 + case SYSTEM_REFCLKI_SELECT:
2320 + clk_src[CLKC_SYS] = &refclk_inp;
2321 + break;
2322 +
2323 + case SYSTEM_XTAL3IN_SELECT:
2324 + clk_src[CLKC_SYS] = &xtal_inp;
2325 + break;
2326 +
2327 + case SYSTEM_MIPSPLL_SELECT:
2328 + clk_src[CLKC_SYS] = &mips_pll_out;
2329 + break;
2330 +
2331 + default :
2332 + clk_src[CLKC_SYS] = 0;
2333 +
2334 + }
2335 +
2336 +
2337 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2338 + switch(choice)
2339 + {
2340 + case ADSLSS_AFECLKI_SELECT:
2341 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2342 + break;
2343 +
2344 + case ADSLSS_REFCLKI_SELECT:
2345 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2346 + break;
2347 +
2348 + case ADSLSS_XTAL3IN_SELECT:
2349 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2350 + break;
2351 +
2352 + case ADSLSS_MIPSPLL_SELECT:
2353 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2354 + break;
2355 +
2356 + default :
2357 + clk_src[CLKC_ADSLSS] = 0;
2358 +
2359 + }
2360 +
2361 +
2362 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2363 + switch(choice)
2364 + {
2365 + case USB_SYSPLL_SELECT:
2366 + clk_src[CLKC_USB] = &sys_pll_out ;
2367 + break;
2368 +
2369 + case USB_REFCLKI_SELECT:
2370 + clk_src[CLKC_USB] = &refclk_inp;
2371 + break;
2372 +
2373 + case USB_XTAL3IN_SELECT:
2374 + clk_src[CLKC_USB] = &xtal_inp;
2375 + break;
2376 +
2377 + case USB_MIPSPLL_SELECT:
2378 + clk_src[CLKC_USB] = &mips_pll_out;
2379 + break;
2380 +
2381 + default :
2382 + clk_src[CLKC_USB] = 0;
2383 +
2384 + }
2385 +}
2386 +
2387 +
2388 +
2389 +/****************************************************************************
2390 + * FUNCTION: tnetd73xx_clkc_set_freq
2391 + ****************************************************************************
2392 + * Description: The above routine is called to set the output_frequency of the
2393 + * selected clock(using clk_id) to the required value given
2394 + * by the variable output_freq.
2395 + ***************************************************************************/
2396 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2397 +(
2398 + TNETD73XX_CLKC_ID_T clk_id,
2399 + u32 output_freq
2400 + )
2401 +{
2402 + u32 base_freq;
2403 + u32 multiplier;
2404 + u32 divider;
2405 + u32 min_prediv;
2406 + u32 max_prediv;
2407 + u32 prediv;
2408 + u32 postdiv;
2409 + u32 temp;
2410 +
2411 + /* check if PLLs are bypassed*/
2412 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2413 + {
2414 + return TNETD73XX_ERR_ERROR;
2415 + }
2416 +
2417 + /*check if the requested output_frequency is in valid range*/
2418 + switch( clk_id )
2419 + {
2420 + case CLKC_SYS:
2421 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2422 + {
2423 + return TNETD73XX_ERR_ERROR;
2424 + }
2425 + present_min = SYS_MIN;
2426 + present_max = SYS_MAX;
2427 + break;
2428 +
2429 + case CLKC_MIPS:
2430 + if((output_freq < MIPS_MIN) ||
2431 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2432 + {
2433 + return TNETD73XX_ERR_ERROR;
2434 + }
2435 + present_min = MIPS_MIN;
2436 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2437 + break;
2438 +
2439 + case CLKC_USB:
2440 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2441 + {
2442 + return TNETD73XX_ERR_ERROR;
2443 + }
2444 + present_min = USB_MIN;
2445 + present_max = USB_MAX;
2446 + break;
2447 +
2448 + case CLKC_ADSLSS:
2449 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2450 + {
2451 + return TNETD73XX_ERR_ERROR;
2452 + }
2453 + present_min = ADSL_MIN;
2454 + present_max = ADSL_MAX;
2455 + break;
2456 + }
2457 +
2458 +
2459 + base_freq = get_base_frequency(clk_id);
2460 +
2461 +
2462 + /* check for minimum base frequency value */
2463 + if( base_freq < MIN_PLL_INP_FREQ)
2464 + {
2465 + return TNETD73XX_ERR_ERROR;
2466 + }
2467 +
2468 + get_val(output_freq, base_freq, &multiplier, &divider);
2469 +
2470 + /* check multiplier range */
2471 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2472 + {
2473 + return TNETD73XX_ERR_ERROR;
2474 + }
2475 +
2476 + /* check divider value */
2477 + if( divider == 0 )
2478 + {
2479 + return TNETD73XX_ERR_ERROR;
2480 + }
2481 +
2482 + /*compute minimum and maximum predivider values */
2483 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2484 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2485 +
2486 + /*adjust the value of divider so that it not less than minimum predivider value*/
2487 + if (divider < min_prediv)
2488 + {
2489 + temp = CEIL(min_prediv, divider);
2490 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2491 + {
2492 + return TNETD73XX_ERR_ERROR ;
2493 + }
2494 + else
2495 + {
2496 + multiplier = temp * multiplier;
2497 + divider = min_prediv;
2498 + }
2499 +
2500 + }
2501 +
2502 + /* compute predivider and postdivider values */
2503 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2504 + postdiv = CEIL(divider,prediv);
2505 +
2506 + /*return fail if postdivider value falls out of range */
2507 + if(postdiv > MAX_DIV_VALUE)
2508 + {
2509 + return TNETD73XX_ERR_ERROR;
2510 + }
2511 +
2512 +
2513 + /*write predivider and postdivider values*/
2514 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2515 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2516 +
2517 + /*wait for divider output to stabilise*/
2518 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2519 +
2520 + /*write to PLL clock register*/
2521 +
2522 + if(clk_id == CLKC_SYS)
2523 + {
2524 + /* but before writing put DRAM to hold mode */
2525 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2526 + }
2527 + /*Bring PLL into div mode */
2528 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2529 +
2530 + /*compute the word to be written to PLLCR
2531 + *corresponding to multiplier value
2532 + */
2533 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2534 +
2535 + /* wait till PLL enters div mode */
2536 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2537 + /*nothing*/;
2538 +
2539 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2540 +
2541 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2542 + /*nothing*/;
2543 +
2544 +
2545 + /*wait for External pll to lock*/
2546 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2547 +
2548 + if(clk_id == CLKC_SYS)
2549 + {
2550 + /* Bring DRAM out of hold */
2551 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2552 + }
2553 +
2554 + return TNETD73XX_ERR_OK ;
2555 +}
2556 +
2557 +/****************************************************************************
2558 + * FUNCTION: tnetd73xx_clkc_get_freq
2559 + ****************************************************************************
2560 + * Description: The above routine is called to get the output_frequency of the
2561 + * selected clock( clk_id)
2562 + ***************************************************************************/
2563 +u32 tnetd73xx_clkc_get_freq
2564 +(
2565 + TNETD73XX_CLKC_ID_T clk_id
2566 + )
2567 +{
2568 +
2569 + u32 clk_ctrl_register;
2570 + u32 clk_pll_setting;
2571 + u32 clk_predivider;
2572 + u32 clk_postdivider;
2573 + u16 pll_factor;
2574 + u32 base_freq;
2575 + u32 divider;
2576 +
2577 + base_freq = get_base_frequency(clk_id);
2578 +
2579 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2580 +
2581 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2582 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2583 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2584 +
2585 + divider = clk_predivider * clk_postdivider;
2586 +
2587 +
2588 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2589 + {
2590 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2591 + }
2592 +
2593 +
2594 + else
2595 + {
2596 + /* return the current clock speed based upon the PLL setting */
2597 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2598 +
2599 + /* Get the PLL multiplication factor */
2600 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2601 +
2602 + /* Check if we're in divide mode or multiply mode */
2603 + if((clk_pll_setting & 0x1) == 0)
2604 + {
2605 + /* We're in divide mode */
2606 + if(pll_factor < 0x10)
2607 + return (CEIL(base_freq >> 1, divider));
2608 + else
2609 + return (CEIL(base_freq >> 2, divider));
2610 + }
2611 +
2612 + else /* We're in PLL mode */
2613 + {
2614 + /* See if PLLNDIV & PLLDIV are set */
2615 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2616 + {
2617 + if(clk_pll_setting & 0x1000)
2618 + {
2619 + /* clk = base_freq * k/2 */
2620 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2621 + }
2622 + else
2623 + {
2624 + /* clk = base_freq * (k-1) / 4)*/
2625 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2626 + }
2627 + }
2628 + else
2629 + {
2630 + if(pll_factor < 0x10)
2631 + {
2632 + /* clk = base_freq * k */
2633 + return(CEIL(base_freq * pll_factor, divider));
2634 + }
2635 +
2636 + else
2637 + {
2638 + /* clk = base_freq */
2639 + return(CEIL(base_freq, divider));
2640 + }
2641 + }
2642 + }
2643 + return(0); /* Should never reach here */
2644 +
2645 + }
2646 +
2647 +}
2648 +
2649 +
2650 +/* local helper functions */
2651 +
2652 +/****************************************************************************
2653 + * FUNCTION: get_base_frequency
2654 + ****************************************************************************
2655 + * Description: The above routine is called to get base frequency of the clocks.
2656 + ***************************************************************************/
2657 +
2658 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
2659 +{
2660 + /* update the current MIPs PLL output value, if the required
2661 + * source is MIPS PLL
2662 + */
2663 + if ( clk_src[clk_id] == &mips_pll_out)
2664 + {
2665 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
2666 + }
2667 +
2668 +
2669 + /* update the current System PLL output value, if the required
2670 + * source is system PLL
2671 + */
2672 + if ( clk_src[clk_id] == &sys_pll_out)
2673 + {
2674 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
2675 + }
2676 +
2677 + return (*clk_src[clk_id]);
2678 +
2679 +}
2680 +
2681 +
2682 +
2683 +/****************************************************************************
2684 + * FUNCTION: find_gcd
2685 + ****************************************************************************
2686 + * Description: The above routine is called to find gcd of 2 numbers.
2687 + ***************************************************************************/
2688 +static u32 find_gcd
2689 +(
2690 + u32 min,
2691 + u32 max
2692 + )
2693 +{
2694 + if (max % min == 0)
2695 + {
2696 + return min;
2697 + }
2698 + else
2699 + {
2700 + return find_gcd(max % min, min);
2701 + }
2702 +}
2703 +
2704 +/****************************************************************************
2705 + * FUNCTION: compute_prediv
2706 + ****************************************************************************
2707 + * Description: The above routine is called to compute predivider value
2708 + ***************************************************************************/
2709 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
2710 +{
2711 + u16 prediv;
2712 +
2713 + /* return the divider itself it it falls within the range of predivider*/
2714 + if (min <= divider && divider <= max)
2715 + {
2716 + return divider;
2717 + }
2718 +
2719 + /* find a value for prediv such that it is a factor of divider */
2720 + for (prediv = max; prediv >= min ; prediv--)
2721 + {
2722 + if ( (divider % prediv) == 0 )
2723 + {
2724 + return prediv;
2725 + }
2726 + }
2727 +
2728 + /* No such factor exists, return min as prediv */
2729 + return min;
2730 +}
2731 +
2732 +/****************************************************************************
2733 + * FUNCTION: get_val
2734 + ****************************************************************************
2735 + * Description: This routine is called to get values of divider and multiplier.
2736 + ***************************************************************************/
2737 +
2738 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
2739 +{
2740 + u32 temp_mul;
2741 + u32 temp_div;
2742 + u32 gcd;
2743 + u32 min_freq;
2744 + u32 max_freq;
2745 +
2746 + /* find gcd of base_freq, output_freq */
2747 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2748 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2749 + gcd = find_gcd(min_freq , max_freq);
2750 +
2751 + if(gcd == 0)
2752 + return; /* ERROR */
2753 +
2754 + /* compute values of multiplier and divider */
2755 + temp_mul = output_freq / gcd;
2756 + temp_div = base_freq / gcd;
2757 +
2758 +
2759 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2760 + if( temp_mul > PLL_MUL_MAXFACTOR )
2761 + {
2762 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2763 + return;
2764 +
2765 + find_approx(&temp_mul,&temp_div,base_freq);
2766 + }
2767 +
2768 + *multiplier = temp_mul;
2769 + *divider = temp_div;
2770 +}
2771 +
2772 +/****************************************************************************
2773 + * FUNCTION: find_approx
2774 + ****************************************************************************
2775 + * Description: This function gets the approx value of num/denom.
2776 + ***************************************************************************/
2777 +
2778 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
2779 +{
2780 + u32 num1;
2781 + u32 denom1;
2782 + u32 num2;
2783 + u32 denom2;
2784 + int32_t closest;
2785 + int32_t prev_closest;
2786 + u32 temp_num;
2787 + u32 temp_denom;
2788 + u32 normalize;
2789 + u32 gcd;
2790 + u32 output_freq;
2791 +
2792 + num1 = *num;
2793 + denom1 = *denom;
2794 +
2795 + prev_closest = 0x7fffffff; /* maximum possible value */
2796 + num2 = num1;
2797 + denom2 = denom1;
2798 +
2799 + /* start with max */
2800 + for(temp_num = 15; temp_num >=1; temp_num--)
2801 + {
2802 +
2803 + temp_denom = CEIL(temp_num * denom1, num1);
2804 + output_freq = (temp_num * base_freq) / temp_denom;
2805 +
2806 + if(temp_denom < 1)
2807 + {
2808 + break;
2809 + }
2810 + else
2811 + {
2812 + normalize = CEIL(num1,temp_num);
2813 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
2814 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2815 + {
2816 + prev_closest = closest;
2817 + num2 = temp_num;
2818 + denom2 = temp_denom;
2819 + }
2820 +
2821 + }
2822 +
2823 + }
2824 +
2825 + gcd = find_gcd(num2,denom2);
2826 + num2 = num2 / gcd;
2827 + denom2 = denom2 /gcd;
2828 +
2829 + *num = num2;
2830 + *denom = denom2;
2831 +}
2832 +
2833 +
2834 +/*****************************************************************************
2835 + * GPIO Control
2836 + *****************************************************************************/
2837 +
2838 +/****************************************************************************
2839 + * FUNCTION: tnetd73xx_gpio_init
2840 + ***************************************************************************/
2841 +void tnetd73xx_gpio_init()
2842 +{
2843 + /* Bring module out of reset */
2844 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2845 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2846 +}
2847 +
2848 +/****************************************************************************
2849 + * FUNCTION: tnetd73xx_gpio_ctrl
2850 + ***************************************************************************/
2851 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2852 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2853 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2854 +{
2855 + u32 pin_status;
2856 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
2857 + if (pin_mode == GPIO_PIN)
2858 + {
2859 + pin_status |= (1 << gpio_pin);
2860 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2861 +
2862 + /* Set pin direction */
2863 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2864 + if (pin_direction == GPIO_INPUT_PIN)
2865 + {
2866 + pin_status |= (1 << gpio_pin);
2867 + }
2868 + else /* GPIO_OUTPUT_PIN */
2869 + {
2870 + pin_status &= (~(1 << gpio_pin));
2871 + }
2872 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2873 + }
2874 + else /* FUNCTIONAL PIN */
2875 + {
2876 + pin_status &= (~(1 << gpio_pin));
2877 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2878 + }
2879 +
2880 +}
2881 +
2882 +/****************************************************************************
2883 + * FUNCTION: tnetd73xx_gpio_out
2884 + ***************************************************************************/
2885 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2886 +{
2887 + u32 pin_value;
2888 +
2889 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2890 + if (value == 1)
2891 + {
2892 + pin_value |= (1 << gpio_pin);
2893 + }
2894 + else
2895 + {
2896 + pin_value &= (~(1 << gpio_pin));
2897 + }
2898 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2899 +}
2900 +
2901 +/****************************************************************************
2902 + * FUNCTION: tnetd73xx_gpio_in
2903 + ***************************************************************************/
2904 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2905 +{
2906 + u32 pin_value;
2907 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
2908 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
2909 +}
2910 +
2911 diff -urN linux-2.4.30/arch/mips/config-shared.in linux-2.4.30.current/arch/mips/config-shared.in
2912 --- linux-2.4.30/arch/mips/config-shared.in 2005-06-11 20:24:09.000000000 +0200
2913 +++ linux-2.4.30.current/arch/mips/config-shared.in 2005-06-12 20:14:28.000000000 +0200
2914 @@ -20,6 +20,15 @@
2915 mainmenu_option next_comment
2916 comment 'Machine selection'
2917 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2918 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2919 +if [ "$CONFIG_AR7" = "y" ]; then
2920 + choice 'Texas Instruments Reference Platform' \
2921 + "AR7DB CONFIG_AR7DB \
2922 + AR7RD CONFIG_AR7RD \
2923 + AR7WRD CONFIG_AR7WRD" AR7DB
2924 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_FREQUENCY 150
2925 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2926 +fi
2927 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2928 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2929 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2930 @@ -239,6 +248,11 @@
2931 define_bool CONFIG_NONCOHERENT_IO y
2932 define_bool CONFIG_PC_KEYB y
2933 fi
2934 +if [ "$CONFIG_AR7" = "y" ]; then
2935 + define_bool CONFIG_NONCOHERENT_IO y
2936 + define_bool CONFIG_SWAP_IO_SPACE y
2937 + define_bool CONFIG_AR7_PAGING y
2938 +fi
2939 if [ "$CONFIG_CASIO_E55" = "y" ]; then
2940 define_bool CONFIG_IRQ_CPU y
2941 define_bool CONFIG_NONCOHERENT_IO y
2942 @@ -736,6 +750,7 @@
2943 mainmenu_option next_comment
2944 comment 'General setup'
2945 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2946 + "$CONFIG_AR7" = "y" -o \
2947 "$CONFIG_CASIO_E55" = "y" -o \
2948 "$CONFIG_DDB5074" = "y" -o \
2949 "$CONFIG_DDB5476" = "y" -o \
2950 @@ -797,6 +812,7 @@
2951 bool 'Networking support' CONFIG_NET
2952
2953 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2954 + "$CONFIG_AR7" = "y" -o \
2955 "$CONFIG_CASIO_E55" = "y" -o \
2956 "$CONFIG_DECSTATION" = "y" -o \
2957 "$CONFIG_IBM_WORKPAD" = "y" -o \
2958 diff -urN linux-2.4.30/arch/mips/kernel/irq.c linux-2.4.30.current/arch/mips/kernel/irq.c
2959 --- linux-2.4.30/arch/mips/kernel/irq.c 2004-02-18 14:36:30.000000000 +0100
2960 +++ linux-2.4.30.current/arch/mips/kernel/irq.c 2005-06-12 20:21:34.000000000 +0200
2961 @@ -76,6 +76,7 @@
2962 * Generic, controller-independent functions:
2963 */
2964
2965 +#ifndef CONFIG_AR7
2966 int get_irq_list(char *buf)
2967 {
2968 int i, j;
2969 @@ -110,6 +111,7 @@
2970 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
2971 return p - buf;
2972 }
2973 +#endif
2974
2975 #ifdef CONFIG_SMP
2976 int global_irq_holder = NO_PROC_ID;
2977 @@ -525,6 +527,7 @@
2978 *
2979 */
2980
2981 +#ifndef CONFIG_AR7
2982 int request_irq(unsigned int irq,
2983 void (*handler)(int, void *, struct pt_regs *),
2984 unsigned long irqflags,
2985 @@ -569,6 +572,7 @@
2986 kfree(action);
2987 return retval;
2988 }
2989 +#endif
2990
2991 /**
2992 * free_irq - free an interrupt
2993 @@ -588,6 +592,7 @@
2994 * the machine.
2995 */
2996
2997 +#ifndef CONFIG_AR7
2998 void free_irq(unsigned int irq, void *dev_id)
2999 {
3000 irq_desc_t *desc;
3001 @@ -629,6 +634,7 @@
3002 return;
3003 }
3004 }
3005 +#endif
3006
3007 /*
3008 * IRQ autodetection code..
3009 diff -urN linux-2.4.30/arch/mips/kernel/setup.c linux-2.4.30.current/arch/mips/kernel/setup.c
3010 --- linux-2.4.30/arch/mips/kernel/setup.c 2005-06-11 20:24:07.000000000 +0200
3011 +++ linux-2.4.30.current/arch/mips/kernel/setup.c 2005-06-12 20:14:28.000000000 +0200
3012 @@ -109,6 +109,7 @@
3013 unsigned long isa_slot_offset;
3014 EXPORT_SYMBOL(isa_slot_offset);
3015
3016 +extern void avalanche_bootmem_init(void);
3017 extern void SetUpBootInfo(void);
3018 extern void load_mmu(void);
3019 extern asmlinkage void start_kernel(void);
3020 @@ -267,6 +268,9 @@
3021 #endif /* CONFIG_BLK_DEV_INITRD */
3022
3023 /* Find the highest page frame number we have available. */
3024 +#ifdef CONFIG_AR7_PAGING
3025 + avalanche_bootmem_init();
3026 +#else
3027 max_pfn = 0;
3028 first_usable_pfn = -1UL;
3029 for (i = 0; i < boot_mem_map.nr_map; i++) {
3030 @@ -376,7 +380,7 @@
3031
3032 /* Reserve the bootmap memory. */
3033 reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3034 -
3035 +#endif
3036 #ifdef CONFIG_BLK_DEV_INITRD
3037 /* Board specific code should have set up initrd_start and initrd_end */
3038 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
3039 @@ -494,6 +498,7 @@
3040 void hp_setup(void);
3041 void au1x00_setup(void);
3042 void frame_info_init(void);
3043 + void ar7_setup(void);
3044
3045 frame_info_init();
3046 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3047 @@ -691,6 +696,11 @@
3048 pmc_yosemite_setup();
3049 break;
3050 #endif
3051 +#ifdef CONFIG_AR7
3052 + case MACH_GROUP_UNKNOWN:
3053 + ar7_setup();
3054 + break;
3055 +#endif
3056 default:
3057 panic("Unsupported architecture");
3058 }
3059 diff -urN linux-2.4.30/arch/mips/kernel/traps.c linux-2.4.30.current/arch/mips/kernel/traps.c
3060 --- linux-2.4.30/arch/mips/kernel/traps.c 2005-06-11 20:24:07.000000000 +0200
3061 +++ linux-2.4.30.current/arch/mips/kernel/traps.c 2005-06-12 20:24:13.000000000 +0200
3062 @@ -40,6 +40,10 @@
3063 #include <asm/uaccess.h>
3064 #include <asm/mmu_context.h>
3065
3066 +#ifdef CONFIG_AR7
3067 +#include <asm/ar7/ar7.h>
3068 +#endif
3069 +
3070 extern asmlinkage void handle_mod(void);
3071 extern asmlinkage void handle_tlbl(void);
3072 extern asmlinkage void handle_tlbs(void);
3073 @@ -920,14 +924,37 @@
3074 void __init trap_init(void)
3075 {
3076 extern char except_vec1_generic;
3077 + extern char except_vec2_generic;
3078 extern char except_vec3_generic, except_vec3_r4000;
3079 extern char except_vec_ejtag_debug;
3080 extern char except_vec4;
3081 unsigned long i;
3082
3083 +#ifdef CONFIG_AR7
3084 + extern char jump_tlb_miss, jump_tlb_miss_unused;
3085 + extern char jump_cache_error,jump_general_exception;
3086 + extern char jump_dedicated_interrupt;
3087 + clear_c0_status(ST0_BEV);
3088 +#endif
3089 +
3090 /* Copy the generic exception handler code to it's final destination. */
3091 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3092
3093 +#ifdef CONFIG_AR7
3094 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
3095 + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3096 + flush_icache_range(KSEG0, KSEG0 + 0x200);
3097 +
3098 + /* jump table to exception routines */
3099 +
3100 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3101 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3102 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3103 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3104 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3105 + flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
3106 +#endif
3107 +
3108 /*
3109 * Setup default vectors
3110 */
3111 diff -urN linux-2.4.30/arch/mips/lib/promlib.c linux-2.4.30.current/arch/mips/lib/promlib.c
3112 --- linux-2.4.30/arch/mips/lib/promlib.c 2003-08-25 13:44:40.000000000 +0200
3113 +++ linux-2.4.30.current/arch/mips/lib/promlib.c 2005-06-12 20:14:28.000000000 +0200
3114 @@ -1,3 +1,4 @@
3115 +#ifndef CONFIG_AR7
3116 #include <stdarg.h>
3117 #include <linux/kernel.h>
3118
3119 @@ -22,3 +23,4 @@
3120 }
3121 va_end(args);
3122 }
3123 +#endif
3124 diff -urN linux-2.4.30/arch/mips/mm/init.c linux-2.4.30.current/arch/mips/mm/init.c
3125 --- linux-2.4.30/arch/mips/mm/init.c 2004-02-18 14:36:30.000000000 +0100
3126 +++ linux-2.4.30.current/arch/mips/mm/init.c 2005-06-12 20:14:28.000000000 +0200
3127 @@ -40,8 +40,10 @@
3128
3129 mmu_gather_t mmu_gathers[NR_CPUS];
3130 unsigned long highstart_pfn, highend_pfn;
3131 +#ifndef CONFIG_AR7_PAGING
3132 static unsigned long totalram_pages;
3133 static unsigned long totalhigh_pages;
3134 +#endif
3135
3136 void pgd_init(unsigned long page)
3137 {
3138 @@ -235,6 +237,7 @@
3139 #endif
3140 }
3141
3142 +#ifndef CONFIG_AR7_PAGING
3143 void __init paging_init(void)
3144 {
3145 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3146 @@ -272,6 +275,7 @@
3147
3148 free_area_init(zones_size);
3149 }
3150 +#endif
3151
3152 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3153 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
3154 @@ -298,6 +302,7 @@
3155 return 0;
3156 }
3157
3158 +#ifndef CONFIG_AR7_PAGING
3159 void __init mem_init(void)
3160 {
3161 unsigned long codesize, reservedpages, datasize, initsize;
3162 @@ -359,6 +364,7 @@
3163 initsize >> 10,
3164 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
3165 }
3166 +#endif
3167
3168 #ifdef CONFIG_BLK_DEV_INITRD
3169 void free_initrd_mem(unsigned long start, unsigned long end)
3170 @@ -376,6 +382,7 @@
3171 }
3172 #endif
3173
3174 +#ifndef CONFIG_AR7_PAGING
3175 extern char __init_begin, __init_end;
3176 extern void prom_free_prom_memory(void) __init;
3177
3178 @@ -383,7 +390,9 @@
3179 {
3180 unsigned long addr;
3181
3182 +#ifndef CONFIG_AR7
3183 prom_free_prom_memory ();
3184 +#endif
3185
3186 addr = (unsigned long) &__init_begin;
3187 while (addr < (unsigned long) &__init_end) {
3188 @@ -409,3 +418,4 @@
3189
3190 return;
3191 }
3192 +#endif
3193 diff -urN linux-2.4.30/arch/mips/mm/tlb-r4k.c linux-2.4.30.current/arch/mips/mm/tlb-r4k.c
3194 --- linux-2.4.30/arch/mips/mm/tlb-r4k.c 2005-06-11 20:24:07.000000000 +0200
3195 +++ linux-2.4.30.current/arch/mips/mm/tlb-r4k.c 2005-06-12 20:14:28.000000000 +0200
3196 @@ -20,6 +20,10 @@
3197 #include <asm/pgtable.h>
3198 #include <asm/system.h>
3199
3200 +#ifdef CONFIG_AR7
3201 +#include <asm/ar7/ar7.h>
3202 +#endif
3203 +
3204 extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
3205
3206 /* CP0 hazard avoidance. */
3207 diff -urN linux-2.4.30/drivers/char/serial.c linux-2.4.30.current/drivers/char/serial.c
3208 --- linux-2.4.30/drivers/char/serial.c 2005-06-11 20:24:07.000000000 +0200
3209 +++ linux-2.4.30.current/drivers/char/serial.c 2005-06-12 20:14:28.000000000 +0200
3210 @@ -419,7 +419,40 @@
3211 return 0;
3212 }
3213
3214 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3215 +#if defined(CONFIG_AR7)
3216 +
3217 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
3218 +{
3219 + return (inb(info->port + (offset * 4)) & 0xff);
3220 +}
3221 +
3222 +
3223 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
3224 +{
3225 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3226 + return (inb(info->port + (offset * 4)) & 0xff);
3227 +#else
3228 + return (inb_p(info->port + (offset * 4)) & 0xff);
3229 +#endif
3230 +}
3231 +
3232 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
3233 +{
3234 + outb(value, info->port + (offset * 4));
3235 +}
3236 +
3237 +
3238 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
3239 + int value)
3240 +{
3241 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3242 + outb(value, info->port + (offset * 4));
3243 +#else
3244 + outb_p(value, info->port + (offset * 4));
3245 +#endif
3246 +}
3247 +
3248 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3249
3250 #include <asm/mips-boards/atlas.h>
3251
3252 @@ -478,8 +511,10 @@
3253 * needed for certain old 386 machines, I've left these #define's
3254 * in....
3255 */
3256 +#ifdef CONFIG_AR7
3257 #define serial_inp(info, offset) serial_in(info, offset)
3258 #define serial_outp(info, offset, value) serial_out(info, offset, value)
3259 +#endif
3260
3261
3262 /*
3263 @@ -1728,7 +1763,15 @@
3264 /* Special case since 134 is really 134.5 */
3265 quot = (2*baud_base / 269);
3266 else if (baud)
3267 +#ifdef CONFIG_AR7
3268 + quot = get_avalanche_vbus_freq() / baud;
3269 +
3270 + if ((quot%16)>7)
3271 + quot += 8;
3272 + quot /=16;
3273 +#else
3274 quot = baud_base / baud;
3275 +#endif
3276 }
3277 /* If the quotient is zero refuse the change */
3278 if (!quot && old_termios) {
3279 @@ -5552,8 +5595,10 @@
3280 state->irq = irq_cannonicalize(state->irq);
3281 if (state->hub6)
3282 state->io_type = SERIAL_IO_HUB6;
3283 +#ifdef CONFIG_AR7
3284 if (state->port && check_region(state->port,8))
3285 continue;
3286 +#endif
3287 #ifdef CONFIG_MCA
3288 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
3289 continue;
3290 @@ -6009,7 +6054,15 @@
3291 info->io_type = state->io_type;
3292 info->iomem_base = state->iomem_base;
3293 info->iomem_reg_shift = state->iomem_reg_shift;
3294 +#ifdef CONFIG_AR7
3295 + quot = get_avalanche_vbus_freq() / baud;
3296 +
3297 + if ((quot%16)>7)
3298 + quot += 8;
3299 + quot /=16;
3300 +#else
3301 quot = state->baud_base / baud;
3302 +#endif
3303 cval = cflag & (CSIZE | CSTOPB);
3304 #if defined(__powerpc__) || defined(__alpha__)
3305 cval >>= 8;
3306 Binary files linux-2.4.30/include/asm-mips/.addrspace.h.swp and linux-2.4.30.current/include/asm-mips/.addrspace.h.swp differ
3307 diff -urN linux-2.4.30/include/asm-mips/ar7/ar7.h linux-2.4.30.current/include/asm-mips/ar7/ar7.h
3308 --- linux-2.4.30/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
3309 +++ linux-2.4.30.current/include/asm-mips/ar7/ar7.h 2005-06-12 20:59:09.000000000 +0200
3310 @@ -0,0 +1,138 @@
3311 +#ifndef _MIPS_AR7_H
3312 +#define _MIPS_AR7_H
3313 +
3314 +#include <linux/config.h>
3315 +#include <asm/addrspace.h>
3316 +
3317 +
3318 +#ifndef LITTLE_ENDIAN
3319 +#define LITTLE_ENDIAN
3320 +#endif
3321 +
3322 +#ifndef _LINK_KSEG0_
3323 +#define _LINK_KSEG0_
3324 +#endif
3325 +
3326 +#include <asm/ar7/tnetd73xx.h>
3327 +
3328 +#define AVALANCHE_UART0_INT 7
3329 +#define AVALANCHE_UART1_INT 8
3330 +
3331 +#define MIPS_EXCEPTION_OFFSET 8
3332 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3333 +
3334 +/*
3335 + * AR7 board SDRAM base address. This is used to setup the
3336 + * bootmem tables
3337 + */
3338 +
3339 +#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL
3340 +#define AVALANCHE_INTC_BASE TNETD73XX_INTC_BASE
3341 +
3342 +
3343 +/*
3344 + * AR7 board vectors
3345 + */
3346 +
3347 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3348 +#define AVALANCHE_VECS_KSEG0 (CPHYSADDR(AVALANCHE_SDRAM_BASE) | 0x80000000)
3349 +#undef KSEG0
3350 +#define KSEG0 AVALANCHE_VECS_KSEG0
3351 +
3352 +/*
3353 + * Yamon Prom print address.
3354 + */
3355 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
3356 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
3357 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
3358 +
3359 +/*
3360 + * AR7 Reset and PSU standby register.
3361 + */
3362 +#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
3363 +#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
3364 +#define AVALANCHE_GORESET 0x1
3365 +#define AVALANCHE_GOSTBY 0x1
3366 +#define AVALANCHE_SWRCR (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR)
3367 +
3368 +/*
3369 + * Avalanche UART register base.
3370 + */
3371 +
3372 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
3373 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
3374 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
3375 +
3376 +/*
3377 + * AVALANCHE DMA controller base
3378 + */
3379 +
3380 +#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
3381 +
3382 +
3383 +
3384 +/*
3385 + * GPIO register map
3386 + */
3387 +
3388 +/* to be obtained from avalanche_map.h */
3389 +#define AVALANCHE_GPIO_WRITE_REG (KSEG1ADDR(0xa8610904))
3390 +#define AVALANCHE_GPIO_DIRECTION_REG (KSEG1ADDR(0xa8610908))
3391 +#define AVALANCHE_GPIO_MODE_REG (KSEG1ADDR(0xa861090C))
3392 +#define AVALANCHE_GPIO_PIN_COUNT 32
3393 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0,0}
3394 +
3395 +
3396 +// Let us define board specific information here.
3397 +
3398 +#if defined(CONFIG_AR7DB)
3399 +
3400 +#define AFECLK_FREQ 35328000
3401 +#define REFCLK_FREQ 25000000
3402 +#define OSC3_FREQ 24000000
3403 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3404 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x55555555
3405 +
3406 +#endif
3407 +
3408 +
3409 +#if defined(CONFIG_AR7RD)
3410 +
3411 +#define AFECLK_FREQ 35328000
3412 +#define REFCLK_FREQ 25000000
3413 +#define OSC3_FREQ 24000000
3414 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3415 +
3416 +#if defined(CONFIG_AR7_MARVELL)
3417 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3418 +#else
3419 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
3420 +#endif
3421 +
3422 +#endif
3423 +
3424 +
3425 +#if defined(CONFIG_AR7WRD)
3426 +
3427 +#define AFECLK_FREQ 35328000
3428 +#define REFCLK_FREQ 25000000
3429 +#define OSC3_FREQ 24000000
3430 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3431 +
3432 +#if defined(CONFIG_AR7_MARVELL)
3433 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3434 +#else
3435 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2