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move generic kernel build parts out of board support patches
[openwrt/svn-archive/archive.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
2 --- linux.old/arch/mips/Makefile 2005-10-21 16:43:16.316951500 +0200
3 +++ linux.dev/arch/mips/Makefile 2005-11-10 01:10:45.775570250 +0100
4 @@ -369,6 +369,16 @@
5 endif
6
7 #
8 +# Texas Instruments AR7
9 +#
10 +
11 +ifdef CONFIG_AR7
12 +LIBS += arch/mips/ar7/ar7.o
13 +SUBDIRS += arch/mips/ar7
14 +LOADADDR += 0x94020000
15 +endif
16 +
17 +#
18 # DECstation family
19 #
20 ifdef CONFIG_DECSTATION
21 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
22 --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
23 +++ linux.dev/arch/mips/ar7/Makefile 2005-11-10 01:13:51.443173750 +0100
24 @@ -0,0 +1,14 @@
25 +.S.s:
26 + $(CPP) $(AFLAGS) $< -o $*.s
27 +
28 +.S.o:
29 + $(CC) $(AFLAGS) -c $< -o $*.o
30 +
31 +EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
32 +O_TARGET := ar7.o
33 +
34 +obj-y := tnetd73xx_misc.o misc.o
35 +export-objs := misc.o irq.o init.o
36 +obj-y += setup.o irq.o int-handler.o reset.o init.o psp_env.o memory.o promlib.o cmdline.o
37 +
38 +include $(TOPDIR)/Rules.make
39 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
40 --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
41 +++ linux.dev/arch/mips/ar7/cmdline.c 2005-11-10 01:14:16.372731750 +0100
42 @@ -0,0 +1,88 @@
43 +/*
44 + * Carsten Langgaard, carstenl@mips.com
45 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
46 + *
47 + * This program is free software; you can distribute it and/or modify it
48 + * under the terms of the GNU General Public License (Version 2) as
49 + * published by the Free Software Foundation.
50 + *
51 + * This program is distributed in the hope it will be useful, but WITHOUT
52 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
53 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
54 + * for more details.
55 + *
56 + * You should have received a copy of the GNU General Public License along
57 + * with this program; if not, write to the Free Software Foundation, Inc.,
58 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
59 + *
60 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
61 + */
62 +#include <linux/init.h>
63 +#include <linux/string.h>
64 +
65 +#include <asm/bootinfo.h>
66 +
67 +extern int prom_argc;
68 +extern int *_prom_argv;
69 +
70 +/*
71 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
72 + * This macro take care of sign extension.
73 + */
74 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
75 +
76 +char arcs_cmdline[CL_SIZE];
77 +#ifdef CONFIG_CMDLINE_BOOL
78 +char __initdata cfg_cmdline[] = CONFIG_CMDLINE;
79 +#endif
80 +
81 +char * __init prom_getcmdline(void)
82 +{
83 + return &(arcs_cmdline[0]);
84 +}
85 +
86 +
87 +void __init prom_init_cmdline(void)
88 +{
89 + char *cp, *end;
90 + int actr;
91 + char *env_cmdline = prom_getenv("kernel_args");
92 + size_t len;
93 +
94 + actr = 1; /* Always ignore argv[0] */
95 +
96 + cp = end = &(arcs_cmdline[0]);
97 + end += sizeof(arcs_cmdline);
98 +
99 + if (env_cmdline) {
100 + len = strlen(env_cmdline);
101 + if (len > end - cp - 1)
102 + len = end - cp - 1;
103 + strncpy(cp, env_cmdline, len);
104 + cp += len;
105 + *cp++ = ' ';
106 + }
107 +#ifdef CONFIG_CMDLINE_BOOL
108 + else {
109 + len = strlen(cfg_cmdline);
110 + if (len > end - cp - 1)
111 + len = end - cp - 1;
112 + strncpy(cp, cfg_cmdline, len);
113 + cp += len;
114 + *cp++ = ' ';
115 + }
116 +#endif
117 +
118 + while(actr < prom_argc) {
119 + len = strlen(prom_argv(actr));
120 + if (len > end - cp - 1)
121 + break;
122 + strncpy(cp, prom_argv(actr), len);
123 + cp += len;
124 + *cp++ = ' ';
125 + actr++;
126 + }
127 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
128 + --cp;
129 + *cp = '\0';
130 +}
131 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
132 --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
133 +++ linux.dev/arch/mips/ar7/init.c 2005-11-10 01:10:45.795571500 +0100
134 @@ -0,0 +1,199 @@
135 +/*
136 + * Carsten Langgaard, carstenl@mips.com
137 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
138 + *
139 + * This program is free software; you can distribute it and/or modify it
140 + * under the terms of the GNU General Public License (Version 2) as
141 + * published by the Free Software Foundation.
142 + *
143 + * This program is distributed in the hope it will be useful, but WITHOUT
144 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
145 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
146 + * for more details.
147 + *
148 + * You should have received a copy of the GNU General Public License along
149 + * with this program; if not, write to the Free Software Foundation, Inc.,
150 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
151 + *
152 + * PROM library initialisation code.
153 + */
154 +#include <linux/config.h>
155 +#include <linux/init.h>
156 +#include <linux/string.h>
157 +#include <linux/kernel.h>
158 +#include <linux/module.h>
159 +
160 +#include <asm/io.h>
161 +#include <asm/mips-boards/prom.h>
162 +#include <asm/mips-boards/generic.h>
163 +
164 +#include <asm/ar7/adam2_env.h>
165 +
166 +int prom_argc;
167 +int *_prom_argv, *_prom_envp;
168 +
169 +/* max # of Adam2 environment variables */
170 +#define MAX_ENV_ENTRY 80
171 +
172 +static t_env_var local_envp[MAX_ENV_ENTRY];
173 +static int env_type = 0;
174 +int init_debug = 0;
175 +
176 +unsigned int max_env_entry;
177 +
178 +extern char *prom_psp_getenv(char *envname);
179 +
180 +static inline char *prom_adam2_getenv(char *envname)
181 +{
182 + /*
183 + * Return a pointer to the given environment variable.
184 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
185 + * in the PROM structures are only 32-bit, so we need some
186 + * workarounds, if we are running in 64-bit mode.
187 + */
188 + int i;
189 + t_env_var *env = (t_env_var *) local_envp;
190 +
191 + if (strcmp("bootloader", envname) == 0)
192 + return "Adam2";
193 +
194 + i = strlen(envname);
195 + while (env->name) {
196 + if(strncmp(envname, env->name, i) == 0) {
197 + return(env->val);
198 + }
199 + env++;
200 + }
201 +
202 + return NULL;
203 +}
204 +
205 +/* XXX "bootloader" won't be returned.
206 + * Better make it an element of local_envp */
207 +static inline t_env_var *
208 +prom_adam2_iterenv(t_env_var *env) {
209 + if (!env)
210 + env = local_envp;
211 + else
212 + env++;
213 + if (env - local_envp > MAX_ENV_ENTRY || !env->name)
214 + return 0;
215 + return env;
216 +}
217 +
218 +char *prom_getenv(char *envname)
219 +{
220 + if (env_type == 1)
221 + return prom_psp_getenv(envname);
222 + else
223 + return prom_adam2_getenv(envname);
224 +}
225 +
226 +t_env_var *
227 +prom_iterenv(t_env_var *last)
228 +{
229 + if (env_type == 1)
230 + return 0; /* not yet implemented */
231 + return prom_adam2_iterenv(last);
232 +}
233 +
234 +static inline unsigned char str2hexnum(unsigned char c)
235 +{
236 + if (c >= '0' && c <= '9')
237 + return c - '0';
238 + if (c >= 'a' && c <= 'f')
239 + return c - 'a' + 10;
240 + return 0; /* foo */
241 +}
242 +
243 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
244 +{
245 + int i;
246 +
247 + for (i = 0; i < 6; i++) {
248 + unsigned char num;
249 +
250 + if((*str == '.') || (*str == ':'))
251 + str++;
252 + num = str2hexnum(*str++) << 4;
253 + num |= (str2hexnum(*str++));
254 + ea[i] = num;
255 + }
256 +}
257 +
258 +int get_ethernet_addr(char *ethernet_addr)
259 +{
260 + char *ethaddr_str;
261 +
262 + ethaddr_str = prom_getenv("ethaddr");
263 + if (!ethaddr_str) {
264 + printk("ethaddr not set in boot prom\n");
265 + return -1;
266 + }
267 + str2eaddr(ethernet_addr, ethaddr_str);
268 +
269 + if (init_debug > 1) {
270 + int i;
271 + printk("get_ethernet_addr: ");
272 + for (i=0; i<5; i++)
273 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
274 + printk("%02x\n", *(ethernet_addr+i));
275 + }
276 +
277 + return 0;
278 +}
279 +
280 +struct psbl_rec {
281 + unsigned int psbl_size;
282 + unsigned int env_base;
283 + unsigned int env_size;
284 + unsigned int ffs_base;
285 + unsigned int ffs_size;
286 +};
287 +
288 +static const char psp_env_version[] = "TIENV0.8";
289 +
290 +int __init prom_init(int argc, char **argv, char **envp)
291 +{
292 + int i;
293 +
294 + t_env_var *env = (t_env_var *) envp;
295 + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
296 + void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
297 +
298 + prom_argc = argc;
299 + _prom_argv = (int *)argv;
300 + _prom_envp = (int *)envp;
301 +
302 + if(strcmp(psp_env, psp_env_version) == 0) {
303 + /* PSPBOOT */
304 +
305 + env_type = 1;
306 + _prom_envp = psp_env;
307 + max_env_entry = (psbl->env_size / 16) - 1;
308 + } else {
309 + /* Copy what we need locally so we are not dependent on
310 + * bootloader RAM. In Adam2, the environment parameters
311 + * are in flash but the table that references them is in
312 + * RAM
313 + */
314 +
315 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
316 + if (env->name) {
317 + local_envp[i].name = env->name;
318 + local_envp[i].val = env->val;
319 + } else {
320 + local_envp[i].name = NULL;
321 + local_envp[i].val = NULL;
322 + }
323 + }
324 + }
325 +
326 + set_io_port_base(0);
327 +
328 + prom_printf("\nLINUX started...\n");
329 + prom_init_cmdline();
330 + prom_meminit();
331 +
332 + return 0;
333 +}
334 diff -urN linux.old/arch/mips/ar7/int-handler.S linux.dev/arch/mips/ar7/int-handler.S
335 --- linux.old/arch/mips/ar7/int-handler.S 1970-01-01 01:00:00.000000000 +0100
336 +++ linux.dev/arch/mips/ar7/int-handler.S 2005-11-10 01:12:43.938955000 +0100
337 @@ -0,0 +1,63 @@
338 +/*
339 + * Copyright 2004 PMC-Sierra Inc.
340 + * Author: Manish Lachwani (lachwani@pmc-sierra.com)
341 + * Adaption for AR7: Enrik Berkhan <enrik@akk.org>
342 + *
343 + * First-level interrupt dispatcher for the TI AR7
344 + *
345 + * This program is free software; you can redistribute it and/or modify it
346 + * under the terms of the GNU General Public License as published by the
347 + * Free Software Foundation; either version 2 of the License, or (at your
348 + * option) any later version.
349 + */
350 +#define __ASSEMBLY__
351 +#include <linux/config.h>
352 +#include <asm/asm.h>
353 +#include <asm/mipsregs.h>
354 +#include <asm/addrspace.h>
355 +#include <asm/regdef.h>
356 +#include <asm/stackframe.h>
357 +
358 +/*
359 + * First level interrupt dispatcher for TI AR7 based boards
360 + */
361 +
362 + .align 5
363 + NESTED(ar7IRQ, PT_SIZE, sp)
364 + SAVE_ALL
365 + CLI
366 + .set at
367 +
368 + mfc0 t0, CP0_CAUSE
369 + mfc0 t2, CP0_STATUS
370 +
371 + and t0, t2
372 +
373 + andi t1, t0, STATUSF_IP2 /* hw0 hardware interrupt */
374 + bnez t1, ll_hw0_irq
375 +
376 + andi t1, t0, STATUSF_IP7 /* R4k CPU timer */
377 + bnez t1, ll_timer_irq
378 +
379 + .set reorder
380 +
381 + /* wrong alarm or masked ... */
382 + j spurious_interrupt
383 + nop
384 + END(ar7IRQ)
385 +
386 + .align 5
387 +
388 +ll_hw0_irq:
389 + li a0, 2
390 + move a1, sp
391 + jal do_IRQ
392 + j ret_from_irq
393 +
394 +ll_timer_irq:
395 + li a0, 7
396 + move a1, sp
397 + jal do_IRQ
398 + j ret_from_irq
399 +
400 +
401 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
402 --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
403 +++ linux.dev/arch/mips/ar7/irq.c 2005-11-10 01:12:43.938955000 +0100
404 @@ -0,0 +1,427 @@
405 +/*
406 + * Nitin Dhingra, iamnd@ti.com
407 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
408 + *
409 + * ########################################################################
410 + *
411 + * This program is free software; you can distribute it and/or modify it
412 + * under the terms of the GNU General Public License (Version 2) as
413 + * published by the Free Software Foundation.
414 + *
415 + * This program is distributed in the hope it will be useful, but WITHOUT
416 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
417 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
418 + * for more details.
419 + *
420 + * You should have received a copy of the GNU General Public License along
421 + * with this program; if not, write to the Free Software Foundation, Inc.,
422 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
423 + *
424 + * ########################################################################
425 + *
426 + * Routines for generic manipulation of the interrupts found on the Texas
427 + * Instruments avalanche board
428 + *
429 + */
430 +
431 +#include <linux/init.h>
432 +#include <linux/interrupt.h>
433 +
434 +#include <asm/irq.h>
435 +#include <asm/mipsregs.h>
436 +#include <asm/ar7/ar7.h>
437 +#include <asm/ar7/avalanche_intc.h>
438 +
439 +#define shutdown_avalanche_irq disable_avalanche_irq
440 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
441 +
442 +static unsigned int startup_avalanche_irq(unsigned int irq);
443 +static void end_avalanche_irq(unsigned int irq);
444 +void enable_avalanche_irq(unsigned int irq_nr);
445 +void disable_avalanche_irq(unsigned int irq_nr);
446 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs);
447 +
448 +static struct hw_interrupt_type avalanche_irq_type = {
449 + "AR7",
450 + startup_avalanche_irq,
451 + shutdown_avalanche_irq,
452 + enable_avalanche_irq,
453 + disable_avalanche_irq,
454 + mask_and_ack_avalanche_irq,
455 + end_avalanche_irq,
456 + NULL
457 +};
458 +
459 +static int ar7_irq_base;
460 +
461 +static struct irqaction ar7_hw0_action = {
462 + ar7_hw0_interrupt, 0, 0, "AR7 on hw0", NULL, NULL
463 +};
464 +
465 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
466 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
467 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
468 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
469 +
470 +/*
471 + This remaps interrupts to exist on other channels than the default
472 + channels. essentially we can use the line # as the index for this
473 + array
474 + */
475 +
476 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
477 +unsigned long uni_secondary_interrupt = 0;
478 +
479 +static void end_avalanche_irq(unsigned int irq)
480 +{
481 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
482 + enable_avalanche_irq(irq);
483 +}
484 +
485 +void disable_avalanche_irq(unsigned int irq_nr)
486 +{
487 + unsigned long flags;
488 + unsigned long chan_nr=0;
489 +
490 + save_and_cli(flags);
491 +
492 + /* irq_nr represents the line number for the interrupt. We must
493 + * disable the channel number associated with that line number.
494 + */
495 +
496 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
497 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
498 + else
499 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
500 +
501 + /* disable the interrupt channel bit */
502 +
503 + /* primary interrupt #'s 0-31 */
504 +
505 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
506 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
507 +
508 + /* primary interrupt #'s 32-39 */
509 +
510 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
511 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
512 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
513 +
514 + else /* secondary interrupt #'s 0-31 */
515 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
516 +
517 + restore_flags(flags);
518 +}
519 +
520 +void enable_avalanche_irq(unsigned int irq_nr)
521 +{
522 + unsigned long flags;
523 + unsigned long chan_nr=0;
524 +
525 + save_and_cli(flags);
526 +
527 + /* irq_nr represents the line number for the interrupt. We must
528 + * disable the channel number associated with that line number.
529 + */
530 +
531 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
532 + chan_nr = AVINTNUM(irq_nr);
533 + else
534 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
535 +
536 + /* enable the interrupt channel bit */
537 +
538 + /* primary interrupt #'s 0-31 */
539 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
540 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
541 +
542 + /* primary interrupt #'s 32 throuth 39 */
543 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
544 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
545 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
546 +
547 + else /* secondary interrupt #'s 0-31 */
548 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
549 +
550 + restore_flags(flags);
551 +}
552 +
553 +static unsigned int startup_avalanche_irq(unsigned int irq)
554 +{
555 + enable_avalanche_irq(irq);
556 + return 0; /* never anything pending */
557 +}
558 +
559 +void __init ar7_irq_init(int base)
560 +{
561 + int i;
562 +
563 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
564 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
565 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
566 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
567 +
568 + /* Disable interrupts and clear pending
569 + */
570 +
571 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
572 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
573 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
574 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
575 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
576 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
577 +
578 +
579 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
580 + /* hack for speeding up the pacing. */
581 + printk("the pacing pre-scalar has been set as 600.\n");
582 + avalanche_hw0_ipaceregs->ipacep = 600;
583 + /* Channel to line mapping, Line to Channel mapping */
584 +
585 + for(i = 0; i < 40; i++)
586 + avalanche_int_set(i,i);
587 +
588 + ar7_irq_base = base;
589 + for (i = base; i <= base+40; i++)
590 + {
591 + irq_desc[i].status = IRQ_DISABLED;
592 + irq_desc[i].action = 0;
593 + irq_desc[i].depth = 1;
594 + irq_desc[i].handler = &avalanche_irq_type;
595 + }
596 +
597 + setup_irq(2, &ar7_hw0_action);
598 + set_c0_status(IE_IRQ0);
599 +
600 + return;
601 +}
602 +
603 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs)
604 +{
605 + int irq;
606 + unsigned long int_line_number, status;
607 + int i, chan_nr = 0;
608 +
609 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
610 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
611 +
612 + if(chan_nr < 32) /* primary 0-31 */
613 + {
614 + if( chan_nr != uni_secondary_interrupt)
615 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
616 +
617 + }
618 +
619 + if((chan_nr < 40) && (chan_nr > 31)) /* primary 32-39 */
620 + {
621 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-32));
622 + }
623 +
624 +
625 + /* If the Priority Interrupt Index Register returns 40 then no
626 + * interrupts are pending
627 + */
628 +
629 + if(chan_nr == 40)
630 + return;
631 +
632 + if(chan_nr == uni_secondary_interrupt) /* secondary 0-31 */
633 + {
634 + status = avalanche_hw0_ecregs->exsr;
635 + for(i=0; i < 32; i++)
636 + {
637 + if (status & 1<<i)
638 + {
639 + /* clear secondary interrupt */
640 + avalanche_hw0_ecregs->excr = 1 << i;
641 + break;
642 + }
643 + }
644 + irq = i+40;
645 +
646 + /* clear the universal secondary interrupt */
647 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
648 +
649 + }
650 + else
651 + irq = chan_nr;
652 +
653 + do_IRQ(irq + ar7_irq_base, regs);
654 + return;
655 +}
656 +
657 +void avalanche_int_set(int channel, int line)
658 +{
659 + switch(channel)
660 + {
661 + case(0):
662 + avalanche_hw0_chregs->cintnr0 = line;
663 + break;
664 + case(1):
665 + avalanche_hw0_chregs->cintnr1 = line;
666 + break;
667 + case(2):
668 + avalanche_hw0_chregs->cintnr2 = line;
669 + break;
670 + case(3):
671 + avalanche_hw0_chregs->cintnr3 = line;
672 + break;
673 + case(4):
674 + avalanche_hw0_chregs->cintnr4 = line;
675 + break;
676 + case(5):
677 + avalanche_hw0_chregs->cintnr5 = line;
678 + break;
679 + case(6):
680 + avalanche_hw0_chregs->cintnr6 = line;
681 + break;
682 + case(7):
683 + avalanche_hw0_chregs->cintnr7 = line;
684 + break;
685 + case(8):
686 + avalanche_hw0_chregs->cintnr8 = line;
687 + break;
688 + case(9):
689 + avalanche_hw0_chregs->cintnr9 = line;
690 + break;
691 + case(10):
692 + avalanche_hw0_chregs->cintnr10 = line;
693 + break;
694 + case(11):
695 + avalanche_hw0_chregs->cintnr11 = line;
696 + break;
697 + case(12):
698 + avalanche_hw0_chregs->cintnr12 = line;
699 + break;
700 + case(13):
701 + avalanche_hw0_chregs->cintnr13 = line;
702 + break;
703 + case(14):
704 + avalanche_hw0_chregs->cintnr14 = line;
705 + break;
706 + case(15):
707 + avalanche_hw0_chregs->cintnr15 = line;
708 + break;
709 + case(16):
710 + avalanche_hw0_chregs->cintnr16 = line;
711 + break;
712 + case(17):
713 + avalanche_hw0_chregs->cintnr17 = line;
714 + break;
715 + case(18):
716 + avalanche_hw0_chregs->cintnr18 = line;
717 + break;
718 + case(19):
719 + avalanche_hw0_chregs->cintnr19 = line;
720 + break;
721 + case(20):
722 + avalanche_hw0_chregs->cintnr20 = line;
723 + break;
724 + case(21):
725 + avalanche_hw0_chregs->cintnr21 = line;
726 + break;
727 + case(22):
728 + avalanche_hw0_chregs->cintnr22 = line;
729 + break;
730 + case(23):
731 + avalanche_hw0_chregs->cintnr23 = line;
732 + break;
733 + case(24):
734 + avalanche_hw0_chregs->cintnr24 = line;
735 + break;
736 + case(25):
737 + avalanche_hw0_chregs->cintnr25 = line;
738 + break;
739 + case(26):
740 + avalanche_hw0_chregs->cintnr26 = line;
741 + break;
742 + case(27):
743 + avalanche_hw0_chregs->cintnr27 = line;
744 + break;
745 + case(28):
746 + avalanche_hw0_chregs->cintnr28 = line;
747 + break;
748 + case(29):
749 + avalanche_hw0_chregs->cintnr29 = line;
750 + break;
751 + case(30):
752 + avalanche_hw0_chregs->cintnr30 = line;
753 + break;
754 + case(31):
755 + avalanche_hw0_chregs->cintnr31 = line;
756 + break;
757 + case(32):
758 + avalanche_hw0_chregs->cintnr32 = line;
759 + break;
760 + case(33):
761 + avalanche_hw0_chregs->cintnr33 = line;
762 + break;
763 + case(34):
764 + avalanche_hw0_chregs->cintnr34 = line;
765 + break;
766 + case(35):
767 + avalanche_hw0_chregs->cintnr35 = line;
768 + break;
769 + case(36):
770 + avalanche_hw0_chregs->cintnr36 = line;
771 + break;
772 + case(37):
773 + avalanche_hw0_chregs->cintnr37 = line;
774 + break;
775 + case(38):
776 + avalanche_hw0_chregs->cintnr38 = line;
777 + break;
778 + case(39):
779 + avalanche_hw0_chregs->cintnr39 = line;
780 + break;
781 + default:
782 + printk("Error: Unknown Avalanche interrupt channel\n");
783 + }
784 +
785 + line_to_channel[line] = channel; /* Suraj check */
786 +
787 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
788 + uni_secondary_interrupt = line;
789 +
790 +}
791 +
792 +
793 +#define AVALANCHE_MAX_PACING_BLK 3
794 +#define AVALANCHE_PACING_LOW_VAL 2
795 +#define AVALANCHE_PACING_HIGH_VAL 63
796 +
797 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
798 + unsigned int pace_value)
799 +{
800 + unsigned int blk_offset;
801 + unsigned long flags;
802 +
803 + if(irq_nr < MIPS_EXCEPTION_OFFSET &&
804 + irq_nr >= AVALANCHE_INT_END_PRIMARY)
805 + return (0);
806 +
807 + if(blk_num > AVALANCHE_MAX_PACING_BLK)
808 + return(-1);
809 +
810 + if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
811 + pace_value < AVALANCHE_PACING_LOW_VAL)
812 + return(-1);
813 +
814 + blk_offset = blk_num*8;
815 +
816 + save_and_cli(flags);
817 +
818 + /* disable the interrupt pacing, if enabled previously */
819 + avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
820 +
821 + /* clear the pacing map */
822 + avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
823 +
824 + /* setup the new values */
825 + avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
826 + avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
827 +
828 + restore_flags(flags);
829 +
830 + return(0);
831 +}
832 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
833 --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
834 +++ linux.dev/arch/mips/ar7/memory.c 2005-11-10 01:14:16.372731750 +0100
835 @@ -0,0 +1,103 @@
836 +/*
837 + * Carsten Langgaard, carstenl@mips.com
838 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
839 + *
840 + * ########################################################################
841 + *
842 + * This program is free software; you can distribute it and/or modify it
843 + * under the terms of the GNU General Public License (Version 2) as
844 + * published by the Free Software Foundation.
845 + *
846 + * This program is distributed in the hope it will be useful, but WITHOUT
847 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
848 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
849 + * for more details.
850 + *
851 + * You should have received a copy of the GNU General Public License along
852 + * with this program; if not, write to the Free Software Foundation, Inc.,
853 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
854 + *
855 + * ########################################################################
856 + *
857 + */
858 +
859 +#include <linux/config.h>
860 +#include <linux/init.h>
861 +#include <linux/mm.h>
862 +#include <linux/bootmem.h>
863 +
864 +#include <asm/bootinfo.h>
865 +#include <asm/page.h>
866 +#include <asm/mips-boards/prom.h>
867 +
868 +extern char _ftext;
869 +extern int preserve_adam2;
870 +
871 +void __init prom_meminit(void)
872 +{
873 + char *memsize_str;
874 + unsigned long memsize, adam2size;
875 +
876 + /* assume block before kernel is used by bootloader */
877 + adam2size = __pa(&_ftext) - PHYS_OFFSET;
878 +
879 + memsize_str = prom_getenv("memsize");
880 + if (!memsize_str) {
881 + memsize = 0x02000000;
882 + } else {
883 + memsize = simple_strtol(memsize_str, NULL, 0);
884 + }
885 +
886 +#if 0
887 + add_memory_region(0x00000000, PHYS_OFFSET, BOOT_MEM_RESERVED);
888 +#endif
889 + add_memory_region(PHYS_OFFSET, adam2size, BOOT_MEM_ROM_DATA);
890 + add_memory_region(PHYS_OFFSET+adam2size, memsize-adam2size,
891 + BOOT_MEM_RAM);
892 +}
893 +
894 +unsigned long __init prom_free_prom_memory (void)
895 +{
896 + int i;
897 + unsigned long freed = 0;
898 + unsigned long addr;
899 +
900 + if (preserve_adam2) {
901 + char *firstfree_str = prom_getenv("firstfreeaddress");
902 + unsigned long firstfree = 0;
903 +
904 + if (firstfree_str)
905 + firstfree = simple_strtol(firstfree_str, NULL, 0);
906 +
907 + if (firstfree && firstfree < (unsigned long)&_ftext) {
908 + printk("Preserving ADAM2 memory.\n");
909 + } else if (firstfree) {
910 + printk("Can't preserve ADAM2 memory, "
911 + "firstfreeaddress = %08lx.\n", firstfree);
912 + preserve_adam2 = 0;
913 + } else {
914 + printk("Can't preserve ADAM2 memory, "
915 + "firstfreeaddress unknown!\n");
916 + preserve_adam2 = 0;
917 + }
918 + }
919 +
920 + if (!preserve_adam2) {
921 + for (i = 0; i < boot_mem_map.nr_map; i++) {
922 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
923 + continue;
924 +
925 + addr = boot_mem_map.map[i].addr;
926 + while (addr < boot_mem_map.map[i].addr
927 + + boot_mem_map.map[i].size) {
928 + ClearPageReserved(virt_to_page(__va(addr)));
929 + set_page_count(virt_to_page(__va(addr)), 1);
930 + free_page((unsigned long)__va(addr));
931 + addr += PAGE_SIZE;
932 + freed += PAGE_SIZE;
933 + }
934 + }
935 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
936 + }
937 + return freed >> PAGE_SHIFT;
938 +}
939 diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
940 --- linux.old/arch/mips/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
941 +++ linux.dev/arch/mips/ar7/misc.c 2005-11-10 01:12:43.946955500 +0100
942 @@ -0,0 +1,322 @@
943 +#include <asm/ar7/sangam.h>
944 +#include <asm/ar7/avalanche_misc.h>
945 +#include <linux/module.h>
946 +#include <linux/spinlock.h>
947 +
948 +#define TRUE 1
949 +
950 +static unsigned int avalanche_vbus_freq;
951 +
952 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
953 +
954 +/*****************************************************************************
955 + * Reset Control Module.
956 + *****************************************************************************/
957 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
958 + AVALANCHE_RESET_CTRL_T reset_ctrl)
959 +{
960 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
961 +
962 + if(module_reset_bit >= 32 && module_reset_bit < 64)
963 + return;
964 +
965 + if(module_reset_bit >= 64)
966 + {
967 + if(p_remote_vlynq_dev_reset_ctrl) {
968 + p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl);
969 + return;
970 + }
971 + else
972 + return;
973 + }
974 +
975 + if(reset_ctrl == OUT_OF_RESET)
976 + *reset_reg |= 1 << module_reset_bit;
977 + else
978 + *reset_reg &= ~(1 << module_reset_bit);
979 + return;
980 +}
981 +
982 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
983 +{
984 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
985 +
986 + return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
987 +}
988 +
989 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
990 +{
991 + volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
992 + *sw_reset_reg = mode;
993 +}
994 +
995 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
996 +
997 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
998 +{
999 + volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
1000 +
1001 + return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
1002 +}
1003 +
1004 +
1005 +/*****************************************************************************
1006 + * Power Control Module
1007 + *****************************************************************************/
1008 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
1009 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
1010 +
1011 +
1012 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
1013 +{
1014 + volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1015 +
1016 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
1017 + /* power down the module */
1018 + *power_reg |= (1 << module_power_bit);
1019 + else
1020 + /* power on the module */
1021 + *power_reg &= (~(1 << module_power_bit));
1022 +}
1023 +
1024 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
1025 +{
1026 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1027 +
1028 + return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
1029 +}
1030 +
1031 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
1032 +{
1033 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1034 +
1035 + *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
1036 + *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
1037 +}
1038 +
1039 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
1040 +{
1041 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1042 +
1043 + return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
1044 + >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
1045 +}
1046 +
1047 +/*****************************************************************************
1048 + * GPIO Control
1049 + *****************************************************************************/
1050 +
1051 +/****************************************************************************
1052 + * FUNCTION: avalanche_gpio_init
1053 + ***************************************************************************/
1054 +void avalanche_gpio_init(void)
1055 +{
1056 + spinlock_t closeLock;
1057 + unsigned int closeFlag;
1058 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1059 + spin_lock_irqsave(&closeLock, closeFlag);
1060 + *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
1061 + spin_unlock_irqrestore(&closeLock, closeFlag);
1062 +}
1063 +
1064 +/****************************************************************************
1065 + * FUNCTION: avalanche_gpio_ctrl
1066 + ***************************************************************************/
1067 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
1068 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
1069 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
1070 +{
1071 + spinlock_t closeLock;
1072 + unsigned int closeFlag;
1073 + volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
1074 +
1075 + if(gpio_pin >= 32)
1076 + return(-1);
1077 +
1078 + spin_lock_irqsave(&closeLock, closeFlag);
1079 +
1080 + if(pin_mode == GPIO_PIN)
1081 + {
1082 + *gpio_ctrl |= (1 << gpio_pin);
1083 +
1084 + gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
1085 +
1086 + if(pin_direction == GPIO_INPUT_PIN)
1087 + *gpio_ctrl |= (1 << gpio_pin);
1088 + else
1089 + *gpio_ctrl &= ~(1 << gpio_pin);
1090 + }
1091 + else /* FUNCTIONAL PIN */
1092 + {
1093 + *gpio_ctrl &= ~(1 << gpio_pin);
1094 + }
1095 +
1096 + spin_unlock_irqrestore(&closeLock, closeFlag);
1097 +
1098 + return (0);
1099 +}
1100 +
1101 +/****************************************************************************
1102 + * FUNCTION: avalanche_gpio_out
1103 + ***************************************************************************/
1104 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
1105 +{
1106 + spinlock_t closeLock;
1107 + unsigned int closeFlag;
1108 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1109 +
1110 + if(gpio_pin >= 32)
1111 + return(-1);
1112 +
1113 + spin_lock_irqsave(&closeLock, closeFlag);
1114 + if(value == TRUE)
1115 + *gpio_out |= 1 << gpio_pin;
1116 + else
1117 + *gpio_out &= ~(1 << gpio_pin);
1118 + spin_unlock_irqrestore(&closeLock, closeFlag);
1119 +
1120 + return(0);
1121 +}
1122 +
1123 +/****************************************************************************
1124 + * FUNCTION: avalanche_gpio_in
1125 + ***************************************************************************/
1126 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
1127 +{
1128 + spinlock_t closeLock;
1129 + unsigned int closeFlag;
1130 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1131 + int ret_val = 0;
1132 +
1133 + if(gpio_pin >= 32)
1134 + return(-1);
1135 +
1136 + spin_lock_irqsave(&closeLock, closeFlag);
1137 + ret_val = ((*gpio_in) & (1 << gpio_pin));
1138 + spin_unlock_irqrestore(&closeLock, closeFlag);
1139 +
1140 + return (ret_val);
1141 +}
1142 +
1143 +/****************************************************************************
1144 + * FUNCTION: avalanche_gpio_out_val
1145 + ***************************************************************************/
1146 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
1147 + unsigned int reg_index)
1148 +{
1149 + spinlock_t closeLock;
1150 + unsigned int closeFlag;
1151 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1152 +
1153 + if(reg_index > 0)
1154 + return(-1);
1155 +
1156 + spin_lock_irqsave(&closeLock, closeFlag);
1157 + *gpio_out &= ~out_mask;
1158 + *gpio_out |= out_val;
1159 + spin_unlock_irqrestore(&closeLock, closeFlag);
1160 +
1161 + return(0);
1162 +}
1163 +
1164 +/****************************************************************************
1165 + * FUNCTION: avalanche_gpio_in_value
1166 + ***************************************************************************/
1167 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
1168 +{
1169 + spinlock_t closeLock;
1170 + unsigned int closeFlag;
1171 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1172 +
1173 + if(reg_index > 0)
1174 + return(-1);
1175 +
1176 + spin_lock_irqsave(&closeLock, closeFlag);
1177 + *in_val = *gpio_in;
1178 + spin_unlock_irqrestore(&closeLock, closeFlag);
1179 +
1180 + return (0);
1181 +}
1182 +
1183 +/***********************************************************************
1184 + *
1185 + * Wakeup Control Module for TNETV1050 Communication Processor
1186 + *
1187 + ***********************************************************************/
1188 +
1189 +#define AVALANCHE_WAKEUP_POLARITY_BIT 16
1190 +
1191 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
1192 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
1193 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
1194 +{
1195 + volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
1196 +
1197 + /* enable/disable */
1198 + if (wakeup_ctrl == WAKEUP_ENABLED)
1199 + /* enable wakeup */
1200 + *wakeup_status_reg |= wakeup_int;
1201 + else
1202 + /* disable wakeup */
1203 + *wakeup_status_reg &= (~wakeup_int);
1204 +
1205 + /* set polarity */
1206 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
1207 + *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1208 + else
1209 + *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1210 +}
1211 +
1212 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
1213 +{
1214 + avalanche_vbus_freq = new_vbus_freq;
1215 +}
1216 +
1217 +unsigned int avalanche_get_vbus_freq()
1218 +{
1219 + return(avalanche_vbus_freq);
1220 +}
1221 +
1222 +unsigned int avalanche_get_chip_version_info()
1223 +{
1224 + return(*(volatile unsigned int*)AVALANCHE_CVR);
1225 +}
1226 +
1227 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
1228 +
1229 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
1230 +{
1231 + if(p_set_mdix_on_chip_fn)
1232 + return (p_set_mdix_on_chip_fn(base_addr, operation));
1233 + else
1234 + return(-1);
1235 +}
1236 +
1237 +unsigned int avalanche_is_mdix_on_chip(void)
1238 +{
1239 + return(p_set_mdix_on_chip_fn ? 1:0);
1240 +}
1241 +
1242 +EXPORT_SYMBOL(avalanche_reset_ctrl);
1243 +EXPORT_SYMBOL(avalanche_get_reset_status);
1244 +EXPORT_SYMBOL(avalanche_sys_reset);
1245 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
1246 +EXPORT_SYMBOL(avalanche_power_ctrl);
1247 +EXPORT_SYMBOL(avalanche_get_power_status);
1248 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
1249 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
1250 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
1251 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
1252 +
1253 +EXPORT_SYMBOL(avalanche_gpio_init);
1254 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
1255 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
1256 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
1257 +EXPORT_SYMBOL(avalanche_gpio_out_value);
1258 +EXPORT_SYMBOL(avalanche_gpio_in_value);
1259 +
1260 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
1261 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
1262 +
1263 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
1264 +
1265 diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
1266 --- linux.old/arch/mips/ar7/platform.h 1970-01-01 01:00:00.000000000 +0100
1267 +++ linux.dev/arch/mips/ar7/platform.h 2005-11-10 01:10:45.799571750 +0100
1268 @@ -0,0 +1,65 @@
1269 +#ifndef _PLATFORM_H_
1270 +#define _PLATFORM_H_
1271 +
1272 +#include <linux/config.h>
1273 +
1274 +
1275 +/* Important: The definition of ENV_SPACE_SIZE should match with that in
1276 + * PSPBoot. (/psp_boot/inc/psbl/env.h)
1277 + */
1278 +#ifdef CONFIG_MIPS_AVALANCHE_TICFG
1279 +#define ENV_SPACE_SIZE (10 * 1024)
1280 +#endif
1281 +
1282 +#ifdef CONFIG_MIPS_TNETV1050SDB
1283 +#define TNETV1050SDB
1284 +#define DUAL_FLASH
1285 +#endif
1286 +
1287 +#ifdef CONFIG_MIPS_AR7DB
1288 +#define TNETD73XX_BOARD
1289 +#define AR7DB
1290 +#endif
1291 +
1292 +#ifdef CONFIG_MIPS_AR7RD
1293 +#define TNETD73XX_BOARD
1294 +#define AR7RD
1295 +#endif
1296 +
1297 +#ifdef CONFIG_AR7WRD
1298 +#define TNETD73XX_BOARD
1299 +#define AR7WRD
1300 +#endif
1301 +
1302 +#ifdef CONFIG_MIPS_AR7VWI
1303 +#define TNETD73XX_BOARD
1304 +#define AR7VWi
1305 +#endif
1306 +
1307 +/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
1308 +#ifdef CONFIG_MIPS_AR7VW
1309 +#define TNETD73XX_BOARD
1310 +#define AR7WRD
1311 +#endif
1312 +
1313 +#ifdef CONFIG_MIPS_AR7WI
1314 +#define TNETD73XX_BOARD
1315 +#define AR7Wi
1316 +#endif
1317 +
1318 +#ifdef CONFIG_MIPS_AR7V
1319 +#define TNETD73XX_BOARD
1320 +#define AR7V
1321 +#endif
1322 +
1323 +#ifdef CONFIG_MIPS_AR7V
1324 +#define TNETD73XX_BOARD
1325 +#define AR7V
1326 +#endif
1327 +
1328 +#ifdef CONFIG_MIPS_WA1130
1329 +#define AVALANCHE
1330 +#define WLAN
1331 +#endif
1332 +
1333 +#endif
1334 diff -urN linux.old/arch/mips/ar7/promlib.c linux.dev/arch/mips/ar7/promlib.c
1335 --- linux.old/arch/mips/ar7/promlib.c 1970-01-01 01:00:00.000000000 +0100
1336 +++ linux.dev/arch/mips/ar7/promlib.c 2005-11-10 01:14:16.372731750 +0100
1337 @@ -0,0 +1,48 @@
1338 +/*
1339 + * Carsten Langgaard, carstenl@mips.com
1340 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1341 + *
1342 + * This program is free software; you can distribute it and/or modify it
1343 + * under the terms of the GNU General Public License (Version 2) as
1344 + * published by the Free Software Foundation.
1345 + *
1346 + * This program is distributed in the hope it will be useful, but WITHOUT
1347 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1348 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1349 + * for more details.
1350 + *
1351 + * You should have received a copy of the GNU General Public License along
1352 + * with this program; if not, write to the Free Software Foundation, Inc.,
1353 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1354 + *
1355 + * Putting things on the screen/serial line using Adam2 facilities.
1356 + */
1357 +
1358 +#include <linux/types.h>
1359 +#include <asm/addrspace.h>
1360 +
1361 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
1362 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR \
1363 + (AVALANCHE_YAMON_FUNCTION_BASE + 1 * 0x4)
1364 +#define AVALANCHE_YAMON_PROM_EXIT \
1365 + (AVALANCHE_YAMON_FUNCTION_BASE + 8 * 0x4)
1366 +
1367 +void prom_putchar(char c)
1368 +{
1369 + static char buf[1];
1370 + void (*prom_print_str)(unsigned int dummy, char *s, int len) =
1371 + (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR);
1372 +
1373 + buf[0] = c;
1374 + prom_print_str(1, buf, 1);
1375 + return;
1376 +}
1377 +
1378 +void adam2_exit(int retval)
1379 +{
1380 + void (*yamon_exit)(int retval) =
1381 + (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_EXIT);
1382 +
1383 + yamon_exit(retval);
1384 + return;
1385 +}
1386 diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
1387 --- linux.old/arch/mips/ar7/psp_env.c 1970-01-01 01:00:00.000000000 +0100
1388 +++ linux.dev/arch/mips/ar7/psp_env.c 2005-11-10 01:10:45.799571750 +0100
1389 @@ -0,0 +1,350 @@
1390 +#include <linux/config.h>
1391 +#include <linux/init.h>
1392 +#include <linux/string.h>
1393 +#include <linux/kernel.h>
1394 +#include <linux/module.h>
1395 +#include <asm/io.h>
1396 +
1397 +#include "platform.h"
1398 +
1399 +#define ENV_CELL_SIZE 16
1400 +
1401 +/* control field decode */
1402 +#define ENV_GARBAGE_BIT 0x01 /* Env is garbage if this bit is off */
1403 +#define ENV_DYNAMIC_BIT 0x02 /* Env is dynamic if this bit is off */
1404 +
1405 +#define ENV_CTRL_MASK 0x03
1406 +#define ENV_PREFINED (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
1407 +#define ENV_DYNAMIC (ENV_GARBAGE_BIT)
1408 +
1409 +struct env_variable {
1410 + unsigned char varNum;
1411 + unsigned char ctrl;
1412 + unsigned short chksum;
1413 + unsigned char numCells;
1414 + unsigned char data[ENV_CELL_SIZE - 5]; /* The data section starts
1415 + * here, continues for
1416 + * numCells.
1417 + */
1418 +};
1419 +
1420 +extern unsigned int max_env_entry;
1421 +
1422 +/* Internal macros */
1423 +#define get_next_block(var) ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
1424 +
1425 +typedef enum ENV_VARS {
1426 + env_vars_start = 0,
1427 + CPUFREQ,
1428 + MEMSZ,
1429 + FLASHSZ,
1430 + MODETTY0,
1431 + MODETTY1,
1432 + PROMPT,
1433 + BOOTCFG,
1434 + HWA_0,
1435 +#if !defined (AVALANCHE) || defined(TNETC401B)
1436 + HWA_1,
1437 +#endif
1438 +#if !defined(TNETV1020_BOARD)
1439 + HWA_RNDIS,
1440 +#endif
1441 +#if defined (TNETD73XX_BOARD)
1442 + HWA_3,
1443 +#endif
1444 + IPA,
1445 + IPA_SVR,
1446 + BLINE_MAC0,
1447 +#if !defined (AVALANCHE) || defined(TNETC401B)
1448 + BLINE_MAC1,
1449 +#endif
1450 +#if !defined(TNETV1020_BOARD)
1451 + BLINE_RNDIS,
1452 +#endif
1453 +#if defined (TNETD73XX_BOARD)
1454 + BLINE_ATM,
1455 +#endif
1456 +#if !defined(TNETV1020_BOARD)
1457 + USB_PID,
1458 + USB_VID,
1459 + USB_EPPOLLI,
1460 +#endif
1461 + IPA_GATEWAY,
1462 + SUBNET_MASK,
1463 +#if defined (TNETV1050_BOARD)
1464 + BLINE_ESWITCH,
1465 +#endif
1466 +#if !defined(TNETV1020_BOARD)
1467 + USB_SERIAL,
1468 + HWA_HRNDIS, /* Host (PC) side RNDIS address */
1469 +#endif
1470 + REMOTE_USER,
1471 + REMOTE_PASS,
1472 + REMOTE_DIR,
1473 + SYSFREQ,
1474 + LINK_TIMEOUT,
1475 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1476 + MAC_PORT,
1477 +#endif
1478 + PATH,
1479 + HOSTNAME,
1480 +#ifdef WLAN
1481 + HW_REV_MAJOR,
1482 + HW_REV_MINOR,
1483 + HW_PATCH,
1484 + SW_PATCH,
1485 + SERIAL_NUMBER,
1486 +#endif
1487 + TFTPCFG,
1488 +#if defined (TNETV1050_BOARD)
1489 + HWA_ESWITCH,
1490 +#endif
1491 + /*
1492 + * Add new env variables here.
1493 + * NOTE: New environment variables should always be placed at the end, ie
1494 + * just before env_vars_end.
1495 + */
1496 +
1497 + env_vars_end
1498 +} ENV_VARS;
1499 +
1500 +
1501 +struct env_description {
1502 + ENV_VARS idx;
1503 + char *nm;
1504 + char *alias;
1505 +};
1506 +
1507 +#define ENVSTR(x) #x
1508 +#define _ENV_ENTRY(x) {.idx = x, .nm = ENVSTR(x), .alias = NULL}
1509 +
1510 +struct env_description env_ns[] = {
1511 + _ENV_ENTRY(env_vars_start), /* start. */
1512 + _ENV_ENTRY(CPUFREQ),
1513 + _ENV_ENTRY(MEMSZ),
1514 + _ENV_ENTRY(FLASHSZ),
1515 + _ENV_ENTRY(MODETTY0),
1516 + _ENV_ENTRY(MODETTY1),
1517 + _ENV_ENTRY(PROMPT),
1518 + _ENV_ENTRY(BOOTCFG),
1519 + _ENV_ENTRY(HWA_0),
1520 +#if !defined (AVALANCHE) || defined(TNETC401B)
1521 + _ENV_ENTRY(HWA_1),
1522 +#endif
1523 +#if !defined(TNETV1020_BOARD)
1524 + _ENV_ENTRY(HWA_RNDIS),
1525 +#endif
1526 +#if defined (TNETD73XX_BOARD)
1527 + _ENV_ENTRY(HWA_3),
1528 +#endif
1529 + _ENV_ENTRY(IPA),
1530 + _ENV_ENTRY(IPA_SVR),
1531 + _ENV_ENTRY(IPA_GATEWAY),
1532 + _ENV_ENTRY(SUBNET_MASK),
1533 + _ENV_ENTRY(BLINE_MAC0),
1534 +#if !defined (AVALANCHE) || defined(TNETC401B)
1535 + _ENV_ENTRY(BLINE_MAC1),
1536 +#endif
1537 +#if !defined(TNETV1020_BOARD)
1538 + _ENV_ENTRY(BLINE_RNDIS),
1539 +#endif
1540 +#if defined (TNETD73XX_BOARD)
1541 + _ENV_ENTRY(BLINE_ATM),
1542 +#endif
1543 +#if !defined(TNETV1020_BOARD)
1544 + _ENV_ENTRY(USB_PID),
1545 + _ENV_ENTRY(USB_VID),
1546 + _ENV_ENTRY(USB_EPPOLLI),
1547 +#endif
1548 +#if defined (TNETV1050_BOARD)
1549 + _ENV_ENTRY(BLINE_ESWITCH),
1550 +#endif
1551 +#if !defined(TNETV1020_BOARD)
1552 + _ENV_ENTRY(USB_SERIAL),
1553 + _ENV_ENTRY(HWA_HRNDIS),
1554 +#endif
1555 + _ENV_ENTRY(REMOTE_USER),
1556 + _ENV_ENTRY(REMOTE_PASS),
1557 + _ENV_ENTRY(REMOTE_DIR),
1558 + _ENV_ENTRY(SYSFREQ),
1559 + _ENV_ENTRY(LINK_TIMEOUT),
1560 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1561 + _ENV_ENTRY(MAC_PORT),
1562 +#endif
1563 + _ENV_ENTRY(PATH),
1564 + _ENV_ENTRY(HOSTNAME),
1565 +#ifdef WLAN
1566 + _ENV_ENTRY(HW_REV_MAJOR),
1567 + _ENV_ENTRY(HW_REV_MINOR),
1568 + _ENV_ENTRY(HW_PATCH),
1569 + _ENV_ENTRY(SW_PATCH),
1570 + _ENV_ENTRY(SERIAL_NUMBER),
1571 +#endif
1572 + _ENV_ENTRY(TFTPCFG),
1573 +#if defined (TNETV1050_BOARD)
1574 + _ENV_ENTRY(HWA_ESWITCH),
1575 +#endif
1576 + /*
1577 + * Add new entries below this.
1578 + */
1579 + /* Adam2 environment name alias. */
1580 + { .idx = IPA, .nm = "my_ipaddress" },
1581 + { .idx = CPUFREQ, .nm = "cpufrequency" },
1582 + { .idx = SYSFREQ, .nm = "sysfrequency" },
1583 + { .idx = HWA_0, .nm = "maca" },
1584 +#ifndef AVALANCHE
1585 + { .idx = HWA_1, .nm = "macb" },
1586 +#endif
1587 + { .idx = MODETTY0, .nm = "modetty0" },
1588 + { .idx = MODETTY1, .nm = "modetty1" },
1589 + { .idx = MEMSZ, .nm = "memsize" },
1590 +
1591 + _ENV_ENTRY(env_vars_end) /* delimiter. */
1592 +};
1593 +
1594 +static inline int var_to_idx(const char* var)
1595 +{
1596 + int ii;
1597 +
1598 + /* go over the list of pre-defined environment variables */
1599 + for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
1600 + /* check if the env variable is listed */
1601 + if (strcmp(env_ns[ii].nm, var) == 0) {
1602 + return env_ns[ii].idx;
1603 + }
1604 +
1605 + /* if an alias is present, check if the alias matches
1606 + * the description
1607 + */
1608 + if (env_ns[ii].alias != NULL) {
1609 + if (strcmp(env_ns[ii].alias, var) == 0) {
1610 + return env_ns[ii].idx;
1611 + }
1612 + }
1613 + }
1614 + return 0;
1615 +}
1616 +
1617 +extern int *_prom_envp;
1618 +
1619 +/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
1620 + * the next read some seconds later is ok. It looks like something is hidding or
1621 + * overlay the flash address at 0xb0000000. Is this possible?
1622 + *
1623 + * The readb() and while() usage below is a attempt of a workarround - with limited success.
1624 + */
1625 +
1626 +static inline struct env_variable* get_var_by_number(int index)
1627 +{
1628 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1629 + volatile unsigned char nr;
1630 + int i;
1631 +
1632 + env_var++; /* skip signature */
1633 +
1634 + i = 0;
1635 + nr = readb(&(env_var->varNum));
1636 +
1637 + while (i < max_env_entry && nr != 0xFF) {
1638 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
1639 + if (nr == index) {
1640 + return env_var;
1641 + }
1642 + }
1643 + i++;
1644 + env_var = get_next_block(env_var);
1645 + nr = readb(&(env_var->varNum));
1646 + }
1647 +
1648 + return NULL;
1649 +}
1650 +
1651 +static inline struct env_variable* get_var_by_name(char *var)
1652 +{
1653 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1654 + volatile unsigned char nr;
1655 + int i;
1656 +
1657 + env_var++; /* skip signature */
1658 +
1659 + nr = readb(&(env_var->varNum));
1660 + i = 0;
1661 +
1662 + while (i < max_env_entry && nr != 0xFF) {
1663 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1664 + if (strcmp(var, env_var->data) == 0)
1665 + return env_var;
1666 + }
1667 + i++;
1668 + env_var = get_next_block(env_var);
1669 + nr = readb(&(env_var->varNum));
1670 + }
1671 + return NULL;
1672 +}
1673 +
1674 +static inline struct env_variable* get_var(char *var)
1675 +{
1676 + int index = var_to_idx(var);
1677 +
1678 + if (index)
1679 + return get_var_by_number(index);
1680 + else
1681 + return get_var_by_name(var);
1682 +
1683 + return NULL;
1684 +}
1685 +
1686 +static inline char *get_value(struct env_variable* env_var)
1687 +{
1688 + unsigned char *name;
1689 + unsigned char *value;
1690 + unsigned short chksum;
1691 + int i;
1692 +
1693 + chksum = env_var->varNum + env_var->ctrl + env_var->numCells;
1694 +
1695 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1696 + name = env_var->data;
1697 + value = env_var->data + strlen(name) + 1;
1698 +
1699 + for(i = 0; i < strlen(name); i++)
1700 + chksum += name[i];
1701 + } else
1702 + value = env_var->data;
1703 +
1704 + for (i = 0; i < strlen(value); i++)
1705 + chksum += value[i];
1706 +
1707 + chksum += env_var->chksum;
1708 + chksum = ~(chksum);
1709 +
1710 + if(chksum != 0) {
1711 + return NULL;
1712 + }
1713 +
1714 + return value;
1715 +}
1716 +
1717 +struct psbl_rec {
1718 + unsigned int psbl_size;
1719 + unsigned int env_base;
1720 + unsigned int env_size;
1721 + unsigned int ffs_base;
1722 + unsigned int ffs_size;
1723 +};
1724 +
1725 +char *prom_psp_getenv(char *envname)
1726 +{
1727 + struct env_variable* env_var;
1728 + char *value;
1729 +
1730 + if (strcmp("bootloader", envname) == 0)
1731 + return "PSPBoot";
1732 +
1733 + if (!(env_var = get_var(envname)))
1734 + return NULL;
1735 +
1736 + value = get_value(env_var);
1737 +
1738 + return value;
1739 +}
1740 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
1741 --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
1742 +++ linux.dev/arch/mips/ar7/reset.c 2005-11-10 01:14:16.372731750 +0100
1743 @@ -0,0 +1,98 @@
1744 +/*
1745 + * Carsten Langgaard, carstenl@mips.com
1746 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1747 + *
1748 + * ########################################################################
1749 + *
1750 + * This program is free software; you can distribute it and/or modify it
1751 + * under the terms of the GNU General Public License (Version 2) as
1752 + * published by the Free Software Foundation.
1753 + *
1754 + * This program is distributed in the hope it will be useful, but WITHOUT
1755 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1756 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1757 + * for more details.
1758 + *
1759 + * You should have received a copy of the GNU General Public License along
1760 + * with this program; if not, write to the Free Software Foundation, Inc.,
1761 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1762 + *
1763 + * ########################################################################
1764 + *
1765 + * Reset the AR7 boards.
1766 + *
1767 + */
1768 +
1769 +#include <linux/init.h>
1770 +#include <linux/kernel.h>
1771 +#include <linux/string.h>
1772 +#include <linux/types.h>
1773 +
1774 +#include <asm/mipsregs.h>
1775 +#include <asm/reboot.h>
1776 +#include <asm/addrspace.h>
1777 +
1778 +int preserve_adam2 = 1;
1779 +
1780 +extern void adam2_exit(int retval);
1781 +
1782 +static void ar7_machine_restart(char *command);
1783 +static void ar7_machine_halt(void);
1784 +static void ar7_machine_power_off(void);
1785 +
1786 +static void ar7_machine_restart(char *command)
1787 +{
1788 + volatile uint32_t *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
1789 +
1790 + *softres_reg = 1;
1791 +}
1792 +
1793 +static void ar7_machine_halt(void)
1794 +{
1795 +
1796 + if (preserve_adam2) {
1797 + set_c0_status(ST0_BEV);
1798 + adam2_exit(0);
1799 + } else {
1800 + /* I'd like to have Alt-SysRq-b work in this state.
1801 + * What's missing here? The timer interrupt is still running.
1802 + * Why doesn't the UART work anymore? */
1803 + while(1) {
1804 + __asm__(".set\tmips3\n\t"
1805 + "wait\n\t"
1806 + ".set\tmips0");
1807 + }
1808 + }
1809 +}
1810 +
1811 +static void ar7_machine_power_off(void)
1812 +{
1813 + volatile uint32_t *power_reg = (void *)(KSEG1ADDR(0x08610A00));
1814 + uint32_t power_state = *power_reg;
1815 +
1816 + /* add something to turn LEDs off? */
1817 +
1818 + power_state &= ~(3 << 30);
1819 + power_state |= (3 << 30); /* power down */
1820 + *power_reg = power_state;
1821 +
1822 + printk("after power down?\n");
1823 +}
1824 +
1825 +void ar7_reboot_setup(void)
1826 +{
1827 + _machine_restart = ar7_machine_restart;
1828 + _machine_halt = ar7_machine_halt;
1829 + _machine_power_off = ar7_machine_power_off;
1830 +}
1831 +
1832 +static int __init ar7_do_preserve_adam2(char *s)
1833 +{
1834 + if (!strcmp(s, "no") || !strcmp(s, "0"))
1835 + preserve_adam2 = 0;
1836 + else
1837 + preserve_adam2 = 1;
1838 + return 1;
1839 +}
1840 +
1841 +__setup("adam2=", ar7_do_preserve_adam2);
1842 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
1843 --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
1844 +++ linux.dev/arch/mips/ar7/setup.c 2005-11-10 01:12:43.946955500 +0100
1845 @@ -0,0 +1,143 @@
1846 +/*
1847 + * Carsten Langgaard, carstenl@mips.com
1848 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
1849 + *
1850 + * This program is free software; you can distribute it and/or modify it
1851 + * under the terms of the GNU General Public License (Version 2) as
1852 + * published by the Free Software Foundation.
1853 + *
1854 + * This program is distributed in the hope it will be useful, but WITHOUT
1855 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1856 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1857 + * for more details.
1858 + *
1859 + * You should have received a copy of the GNU General Public License along
1860 + * with this program; if not, write to the Free Software Foundation, Inc.,
1861 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1862 + */
1863 +
1864 +#include <linux/config.h>
1865 +#include <linux/init.h>
1866 +#include <linux/string.h>
1867 +#include <linux/irq.h>
1868 +
1869 +#include <asm/processor.h>
1870 +#include <asm/irq.h>
1871 +#include <asm/irq_cpu.h>
1872 +#include <asm/time.h>
1873 +#include <asm/mipsregs.h>
1874 +#include <asm/mips-boards/prom.h>
1875 +
1876 +#ifdef CONFIG_KGDB
1877 +extern void rs_kgdb_hook(int);
1878 +extern void breakpoint(void);
1879 +int remote_debug = 0;
1880 +#endif
1881 +
1882 +extern void ar7_reboot_setup(void);
1883 +extern void ar7_irq_init(int);
1884 +extern asmlinkage void ar7IRQ(void);
1885 +
1886 +void ar7_time_init(void)
1887 +{
1888 + /* XXX runtime */
1889 + mips_hpt_frequency = CONFIG_AR7_CPU * 500000;
1890 +}
1891 +
1892 +void ar7_timer_setup(struct irqaction *irq)
1893 +{
1894 + setup_irq(7, irq);
1895 + set_c0_status(IE_IRQ5);
1896 +}
1897 +
1898 +void __init init_IRQ(void)
1899 +{
1900 + init_generic_irq();
1901 + mips_cpu_irq_init(0);
1902 + ar7_irq_init(8);
1903 +
1904 + /* Now safe to set the exception vector. */
1905 + set_except_vector(0, ar7IRQ);
1906 +
1907 +#ifdef CONFIG_KGDB
1908 + if (remote_debug)
1909 + {
1910 + set_debug_traps();
1911 + breakpoint();
1912 + }
1913 +#endif
1914 +}
1915 +
1916 +const char *get_system_type(void)
1917 +{
1918 + return "Texas Instruments AR7";
1919 +}
1920 +
1921 +void __init ar7_setup(void)
1922 +{
1923 +#ifdef CONFIG_KGDB
1924 + int rs_putDebugChar(char);
1925 + char rs_getDebugChar(void);
1926 + extern int (*generic_putDebugChar)(char);
1927 + extern char (*generic_getDebugChar)(void);
1928 +#endif
1929 + char *argptr;
1930 +#ifdef CONFIG_SERIAL_CONSOLE
1931 + argptr = prom_getcmdline();
1932 + if ((argptr = strstr(argptr, "console=")) == NULL) {
1933 + char console[20];
1934 + char *s;
1935 + int i = 0;
1936 +
1937 + s = prom_getenv("modetty0");
1938 + strcpy(console, "38400");
1939 +
1940 + if (s != NULL) {
1941 + while (s[i] >= '0' && s[i] <= '9')
1942 + i++;
1943 +
1944 + if (i > 0) {
1945 + strncpy(console, s, i);
1946 + console[i] = 0;
1947 + }
1948 + }
1949 +
1950 + argptr = prom_getcmdline();
1951 + strcat(argptr, " console=ttyS0,");
1952 + strcat(argptr, console);
1953 + }
1954 +#endif
1955 +
1956 +#ifdef CONFIG_KGDB
1957 + argptr = prom_getcmdline();
1958 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1959 + int line;
1960 + argptr += strlen("kgdb=ttyS");
1961 + if (*argptr != '0' && *argptr != '1')
1962 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
1963 + "falling back to /dev/ttyS1\n", *argptr);
1964 + line = *argptr == '0' ? 0 : 1;
1965 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1966 + line ? 1 : 0);
1967 +
1968 + rs_kgdb_hook(line);
1969 + generic_putDebugChar = rs_putDebugChar;
1970 + generic_getDebugChar = rs_getDebugChar;
1971 +
1972 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1973 + "please connect your debugger\n", line ? 1 : 0);
1974 +
1975 + remote_debug = 1;
1976 + /* Breakpoints are in init_IRQ() */
1977 + }
1978 +#endif
1979 +
1980 + argptr = prom_getcmdline();
1981 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
1982 + cpu_data[0].options &= ~MIPS_CPU_FPU;
1983 +
1984 + ar7_reboot_setup();
1985 +
1986 + board_time_init = ar7_time_init;
1987 + board_timer_setup = ar7_timer_setup;
1988 +}
1989 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
1990 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
1991 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-11-10 01:12:43.946955500 +0100
1992 @@ -0,0 +1,921 @@
1993 +/******************************************************************************
1994 + * FILE PURPOSE: TNETD73xx Misc modules API Source
1995 + ******************************************************************************
1996 + * FILE NAME: tnetd73xx_misc.c
1997 + *
1998 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
1999 + * FSER Modules API
2000 + * As per TNETD73xx specifications
2001 + *
2002 + * REVISION HISTORY:
2003 + * 27 Nov 02 - Sharath Kumar PSP TII
2004 + * 14 Feb 03 - Anant Gole PSP TII
2005 + *
2006 + * (C) Copyright 2002, Texas Instruments, Inc
2007 + *******************************************************************************/
2008 +
2009 +#include <linux/types.h>
2010 +#include <asm/ar7/tnetd73xx.h>
2011 +#include <asm/ar7/tnetd73xx_misc.h>
2012 +
2013 +/* TNETD73XX Revision */
2014 +u32 tnetd73xx_get_revision(void)
2015 +{
2016 + /* Read Chip revision register - This register is from GPIO module */
2017 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2018 +}
2019 +
2020 +/*****************************************************************************
2021 + * Reset Control Module
2022 + *****************************************************************************/
2023 +
2024 +
2025 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2026 +{
2027 + u32 reset_status;
2028 +
2029 + /* read current reset register */
2030 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2031 +
2032 + if (reset_ctrl == OUT_OF_RESET)
2033 + {
2034 + /* bring module out of reset */
2035 + reset_status |= (1 << reset_module);
2036 + }
2037 + else
2038 + {
2039 + /* put module in reset */
2040 + reset_status &= (~(1 << reset_module));
2041 + }
2042 +
2043 + /* write to the reset register */
2044 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2045 +}
2046 +
2047 +
2048 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2049 +{
2050 + u32 reset_status;
2051 +
2052 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2053 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2054 +}
2055 +
2056 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2057 +{
2058 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2059 +}
2060 +
2061 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2062 +
2063 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2064 +{
2065 + u32 sys_reset_status;
2066 +
2067 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2068 +
2069 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2070 +}
2071 +
2072 +
2073 +/*****************************************************************************
2074 + * Power Control Module
2075 + *****************************************************************************/
2076 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2077 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2078 +
2079 +
2080 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2081 +{
2082 + u32 power_status;
2083 +
2084 + /* read current power down control register */
2085 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2086 +
2087 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2088 + {
2089 + /* power down the module */
2090 + power_status |= (1 << power_module);
2091 + }
2092 + else
2093 + {
2094 + /* power on the module */
2095 + power_status &= (~(1 << power_module));
2096 + }
2097 +
2098 + /* write to the reset register */
2099 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2100 +}
2101 +
2102 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2103 +{
2104 + u32 power_status;
2105 +
2106 + /* read current power down control register */
2107 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2108 +
2109 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2110 +}
2111 +
2112 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2113 +{
2114 + u32 power_status;
2115 +
2116 + /* read current power down control register */
2117 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2118 +
2119 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2120 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2121 +
2122 + /* write to power down control register */
2123 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2124 +}
2125 +
2126 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2127 +{
2128 + u32 power_status;
2129 +
2130 + /* read current power down control register */
2131 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2132 +
2133 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2134 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2135 +
2136 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2137 +}
2138 +
2139 +
2140 +/*****************************************************************************
2141 + * Wakeup Control
2142 + *****************************************************************************/
2143 +
2144 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2145 +
2146 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2147 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2148 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2149 +{
2150 + u32 wakeup_status;
2151 +
2152 + /* read the wakeup control register */
2153 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2154 +
2155 + /* enable/disable */
2156 + if (wakeup_ctrl == WAKEUP_ENABLED)
2157 + {
2158 + /* enable wakeup */
2159 + wakeup_status |= wakeup_int;
2160 + }
2161 + else
2162 + {
2163 + /* disable wakeup */
2164 + wakeup_status &= (~wakeup_int);
2165 + }
2166 +
2167 + /* set polarity */
2168 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2169 + {
2170 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2171 + }
2172 + else
2173 + {
2174 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2175 + }
2176 +
2177 + /* write the wakeup control register */
2178 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2179 +}
2180 +
2181 +
2182 +/*****************************************************************************
2183 + * FSER Control
2184 + *****************************************************************************/
2185 +
2186 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2187 +{
2188 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2189 +}
2190 +
2191 +/*****************************************************************************
2192 + * Clock Control
2193 + *****************************************************************************/
2194 +
2195 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2196 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2197 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2198 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2199 +
2200 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2201 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2202 +
2203 +#define CLKC_PRE_DIVIDER 0x0000001F
2204 +#define CLKC_POST_DIVIDER 0x001F0000
2205 +
2206 +#define CLKC_PLL_STATUS 0x1
2207 +#define CLKC_PLL_FACTOR 0x0000F000
2208 +
2209 +#define BOOTCR_PLL_BYPASS (1 << 5)
2210 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2211 +
2212 +#define MIPS_PLL_SELECT 0x00030000
2213 +#define SYSTEM_PLL_SELECT 0x0000C000
2214 +#define USB_PLL_SELECT 0x000C0000
2215 +#define ADSLSS_PLL_SELECT 0x00C00000
2216 +
2217 +#define MIPS_AFECLKI_SELECT 0x00000000
2218 +#define MIPS_REFCLKI_SELECT 0x00010000
2219 +#define MIPS_XTAL3IN_SELECT 0x00020000
2220 +
2221 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2222 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2223 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2224 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2225 +
2226 +#define USB_SYSPLL_SELECT 0x00000000
2227 +#define USB_REFCLKI_SELECT 0x00040000
2228 +#define USB_XTAL3IN_SELECT 0x00080000
2229 +#define USB_MIPSPLL_SELECT 0x000C0000
2230 +
2231 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2232 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2233 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2234 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2235 +
2236 +#define SYS_MAX CLK_MHZ(150)
2237 +#define SYS_MIN CLK_MHZ(1)
2238 +
2239 +#define MIPS_SYNC_MAX SYS_MAX
2240 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2241 +#define MIPS_MIN CLK_MHZ(1)
2242 +
2243 +#define USB_MAX CLK_MHZ(100)
2244 +#define USB_MIN CLK_MHZ(1)
2245 +
2246 +#define ADSL_MAX CLK_MHZ(180)
2247 +#define ADSL_MIN CLK_MHZ(1)
2248 +
2249 +#define PLL_MUL_MAXFACTOR 15
2250 +#define MAX_DIV_VALUE 32
2251 +#define MIN_DIV_VALUE 1
2252 +
2253 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2254 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2255 +
2256 +#define DIVIDER_LOCK_TIME 10100
2257 +#define PLL_LOCK_TIME 10100 * 75
2258 +
2259 +
2260 +
2261 + /****************************************************************************
2262 + * DATA PURPOSE: PRIVATE Variables
2263 + **************************************************************************/
2264 + static u32 *clk_src[4];
2265 + static u32 mips_pll_out;
2266 + static u32 sys_pll_out;
2267 + static u32 afeclk_inp;
2268 + static u32 refclk_inp;
2269 + static u32 xtal_inp;
2270 + static u32 present_min;
2271 + static u32 present_max;
2272 +
2273 + /* Forward References */
2274 + static u32 find_gcd(u32 min, u32 max);
2275 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2276 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2277 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2278 + static void find_approx(u32 *,u32 *,u32);
2279 +
2280 + /****************************************************************************
2281 + * FUNCTION: tnetd73xx_clkc_init
2282 + ****************************************************************************
2283 + * Description: The routine initializes the internal variables depending on
2284 + * on the sources selected for different clocks.
2285 + ***************************************************************************/
2286 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2287 +{
2288 +
2289 + u32 choice;
2290 +
2291 + afeclk_inp = afeclk;
2292 + refclk_inp = refclk;
2293 + xtal_inp = xtal3in;
2294 +
2295 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2296 + switch(choice)
2297 + {
2298 + case MIPS_AFECLKI_SELECT:
2299 + clk_src[CLKC_MIPS] = &afeclk_inp;
2300 + break;
2301 +
2302 + case MIPS_REFCLKI_SELECT:
2303 + clk_src[CLKC_MIPS] = &refclk_inp;
2304 + break;
2305 +
2306 + case MIPS_XTAL3IN_SELECT:
2307 + clk_src[CLKC_MIPS] = &xtal_inp;
2308 + break;
2309 +
2310 + default :
2311 + clk_src[CLKC_MIPS] = 0;
2312 +
2313 + }
2314 +
2315 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2316 + switch(choice)
2317 + {
2318 + case SYSTEM_AFECLKI_SELECT:
2319 + clk_src[CLKC_SYS] = &afeclk_inp;
2320 + break;
2321 +
2322 + case SYSTEM_REFCLKI_SELECT:
2323 + clk_src[CLKC_SYS] = &refclk_inp;
2324 + break;
2325 +
2326 + case SYSTEM_XTAL3IN_SELECT:
2327 + clk_src[CLKC_SYS] = &xtal_inp;
2328 + break;
2329 +
2330 + case SYSTEM_MIPSPLL_SELECT:
2331 + clk_src[CLKC_SYS] = &mips_pll_out;
2332 + break;
2333 +
2334 + default :
2335 + clk_src[CLKC_SYS] = 0;
2336 +
2337 + }
2338 +
2339 +
2340 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2341 + switch(choice)
2342 + {
2343 + case ADSLSS_AFECLKI_SELECT:
2344 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2345 + break;
2346 +
2347 + case ADSLSS_REFCLKI_SELECT:
2348 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2349 + break;
2350 +
2351 + case ADSLSS_XTAL3IN_SELECT:
2352 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2353 + break;
2354 +
2355 + case ADSLSS_MIPSPLL_SELECT:
2356 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2357 + break;
2358 +
2359 + default :
2360 + clk_src[CLKC_ADSLSS] = 0;
2361 +
2362 + }
2363 +
2364 +
2365 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2366 + switch(choice)
2367 + {
2368 + case USB_SYSPLL_SELECT:
2369 + clk_src[CLKC_USB] = &sys_pll_out ;
2370 + break;
2371 +
2372 + case USB_REFCLKI_SELECT:
2373 + clk_src[CLKC_USB] = &refclk_inp;
2374 + break;
2375 +
2376 + case USB_XTAL3IN_SELECT:
2377 + clk_src[CLKC_USB] = &xtal_inp;
2378 + break;
2379 +
2380 + case USB_MIPSPLL_SELECT:
2381 + clk_src[CLKC_USB] = &mips_pll_out;
2382 + break;
2383 +
2384 + default :
2385 + clk_src[CLKC_USB] = 0;
2386 +
2387 + }
2388 +}
2389 +
2390 +
2391 +
2392 +/****************************************************************************
2393 + * FUNCTION: tnetd73xx_clkc_set_freq
2394 + ****************************************************************************
2395 + * Description: The above routine is called to set the output_frequency of the
2396 + * selected clock(using clk_id) to the required value given
2397 + * by the variable output_freq.
2398 + ***************************************************************************/
2399 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2400 +(
2401 + TNETD73XX_CLKC_ID_T clk_id,
2402 + u32 output_freq
2403 + )
2404 +{
2405 + u32 base_freq;
2406 + u32 multiplier;
2407 + u32 divider;
2408 + u32 min_prediv;
2409 + u32 max_prediv;
2410 + u32 prediv;
2411 + u32 postdiv;
2412 + u32 temp;
2413 +
2414 + /* check if PLLs are bypassed*/
2415 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2416 + {
2417 + return TNETD73XX_ERR_ERROR;
2418 + }
2419 +
2420 + /*check if the requested output_frequency is in valid range*/
2421 + switch( clk_id )
2422 + {
2423 + case CLKC_SYS:
2424 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2425 + {
2426 + return TNETD73XX_ERR_ERROR;
2427 + }
2428 + present_min = SYS_MIN;
2429 + present_max = SYS_MAX;
2430 + break;
2431 +
2432 + case CLKC_MIPS:
2433 + if((output_freq < MIPS_MIN) ||
2434 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2435 + {
2436 + return TNETD73XX_ERR_ERROR;
2437 + }
2438 + present_min = MIPS_MIN;
2439 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2440 + break;
2441 +
2442 + case CLKC_USB:
2443 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2444 + {
2445 + return TNETD73XX_ERR_ERROR;
2446 + }
2447 + present_min = USB_MIN;
2448 + present_max = USB_MAX;
2449 + break;
2450 +
2451 + case CLKC_ADSLSS:
2452 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2453 + {
2454 + return TNETD73XX_ERR_ERROR;
2455 + }
2456 + present_min = ADSL_MIN;
2457 + present_max = ADSL_MAX;
2458 + break;
2459 + }
2460 +
2461 +
2462 + base_freq = get_base_frequency(clk_id);
2463 +
2464 +
2465 + /* check for minimum base frequency value */
2466 + if( base_freq < MIN_PLL_INP_FREQ)
2467 + {
2468 + return TNETD73XX_ERR_ERROR;
2469 + }
2470 +
2471 + get_val(output_freq, base_freq, &multiplier, &divider);
2472 +
2473 + /* check multiplier range */
2474 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2475 + {
2476 + return TNETD73XX_ERR_ERROR;
2477 + }
2478 +
2479 + /* check divider value */
2480 + if( divider == 0 )
2481 + {
2482 + return TNETD73XX_ERR_ERROR;
2483 + }
2484 +
2485 + /*compute minimum and maximum predivider values */
2486 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2487 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2488 +
2489 + /*adjust the value of divider so that it not less than minimum predivider value*/
2490 + if (divider < min_prediv)
2491 + {
2492 + temp = CEIL(min_prediv, divider);
2493 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2494 + {
2495 + return TNETD73XX_ERR_ERROR ;
2496 + }
2497 + else
2498 + {
2499 + multiplier = temp * multiplier;
2500 + divider = min_prediv;
2501 + }
2502 +
2503 + }
2504 +
2505 + /* compute predivider and postdivider values */
2506 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2507 + postdiv = CEIL(divider,prediv);
2508 +
2509 + /*return fail if postdivider value falls out of range */
2510 + if(postdiv > MAX_DIV_VALUE)
2511 + {
2512 + return TNETD73XX_ERR_ERROR;
2513 + }
2514 +
2515 +
2516 + /*write predivider and postdivider values*/
2517 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2518 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2519 +
2520 + /*wait for divider output to stabilise*/
2521 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2522 +
2523 + /*write to PLL clock register*/
2524 +
2525 + if(clk_id == CLKC_SYS)
2526 + {
2527 + /* but before writing put DRAM to hold mode */
2528 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2529 + }
2530 + /*Bring PLL into div mode */
2531 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2532 +
2533 + /*compute the word to be written to PLLCR
2534 + *corresponding to multiplier value
2535 + */
2536 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2537 +
2538 + /* wait till PLL enters div mode */
2539 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2540 + /*nothing*/;
2541 +
2542 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2543 +
2544 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2545 + /*nothing*/;
2546 +
2547 +
2548 + /*wait for External pll to lock*/
2549 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2550 +
2551 + if(clk_id == CLKC_SYS)
2552 + {
2553 + /* Bring DRAM out of hold */
2554 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2555 + }
2556 +
2557 + return TNETD73XX_ERR_OK ;
2558 +}
2559 +
2560 +/****************************************************************************
2561 + * FUNCTION: tnetd73xx_clkc_get_freq
2562 + ****************************************************************************
2563 + * Description: The above routine is called to get the output_frequency of the
2564 + * selected clock( clk_id)
2565 + ***************************************************************************/
2566 +u32 tnetd73xx_clkc_get_freq
2567 +(
2568 + TNETD73XX_CLKC_ID_T clk_id
2569 + )
2570 +{
2571 +
2572 + u32 clk_ctrl_register;
2573 + u32 clk_pll_setting;
2574 + u32 clk_predivider;
2575 + u32 clk_postdivider;
2576 + u16 pll_factor;
2577 + u32 base_freq;
2578 + u32 divider;
2579 +
2580 + base_freq = get_base_frequency(clk_id);
2581 +
2582 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2583 +
2584 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2585 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2586 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2587 +
2588 + divider = clk_predivider * clk_postdivider;
2589 +
2590 +
2591 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2592 + {
2593 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2594 + }
2595 +
2596 +
2597 + else
2598 + {
2599 + /* return the current clock speed based upon the PLL setting */
2600 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2601 +
2602 + /* Get the PLL multiplication factor */
2603 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2604 +
2605 + /* Check if we're in divide mode or multiply mode */
2606 + if((clk_pll_setting & 0x1) == 0)
2607 + {
2608 + /* We're in divide mode */
2609 + if(pll_factor < 0x10)
2610 + return (CEIL(base_freq >> 1, divider));
2611 + else
2612 + return (CEIL(base_freq >> 2, divider));
2613 + }
2614 +
2615 + else /* We're in PLL mode */
2616 + {
2617 + /* See if PLLNDIV & PLLDIV are set */
2618 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2619 + {
2620 + if(clk_pll_setting & 0x1000)
2621 + {
2622 + /* clk = base_freq * k/2 */
2623 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2624 + }
2625 + else
2626 + {
2627 + /* clk = base_freq * (k-1) / 4)*/
2628 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2629 + }
2630 + }
2631 + else
2632 + {
2633 + if(pll_factor < 0x10)
2634 + {
2635 + /* clk = base_freq * k */
2636 + return(CEIL(base_freq * pll_factor, divider));
2637 + }
2638 +
2639 + else
2640 + {
2641 + /* clk = base_freq */
2642 + return(CEIL(base_freq, divider));
2643 + }
2644 + }
2645 + }
2646 + return(0); /* Should never reach here */
2647 +
2648 + }
2649 +
2650 +}
2651 +
2652 +
2653 +/* local helper functions */
2654 +
2655 +/****************************************************************************
2656 + * FUNCTION: get_base_frequency
2657 + ****************************************************************************
2658 + * Description: The above routine is called to get base frequency of the clocks.
2659 + ***************************************************************************/
2660 +
2661 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
2662 +{
2663 + /* update the current MIPs PLL output value, if the required
2664 + * source is MIPS PLL
2665 + */
2666 + if ( clk_src[clk_id] == &mips_pll_out)
2667 + {
2668 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
2669 + }
2670 +
2671 +
2672 + /* update the current System PLL output value, if the required
2673 + * source is system PLL
2674 + */
2675 + if ( clk_src[clk_id] == &sys_pll_out)
2676 + {
2677 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
2678 + }
2679 +
2680 + return (*clk_src[clk_id]);
2681 +
2682 +}
2683 +
2684 +
2685 +
2686 +/****************************************************************************
2687 + * FUNCTION: find_gcd
2688 + ****************************************************************************
2689 + * Description: The above routine is called to find gcd of 2 numbers.
2690 + ***************************************************************************/
2691 +static u32 find_gcd
2692 +(
2693 + u32 min,
2694 + u32 max
2695 + )
2696 +{
2697 + if (max % min == 0)
2698 + {
2699 + return min;
2700 + }
2701 + else
2702 + {
2703 + return find_gcd(max % min, min);
2704 + }
2705 +}
2706 +
2707 +/****************************************************************************
2708 + * FUNCTION: compute_prediv
2709 + ****************************************************************************
2710 + * Description: The above routine is called to compute predivider value
2711 + ***************************************************************************/
2712 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
2713 +{
2714 + u16 prediv;
2715 +
2716 + /* return the divider itself it it falls within the range of predivider*/
2717 + if (min <= divider && divider <= max)
2718 + {
2719 + return divider;
2720 + }
2721 +
2722 + /* find a value for prediv such that it is a factor of divider */
2723 + for (prediv = max; prediv >= min ; prediv--)
2724 + {
2725 + if ( (divider % prediv) == 0 )
2726 + {
2727 + return prediv;
2728 + }
2729 + }
2730 +
2731 + /* No such factor exists, return min as prediv */
2732 + return min;
2733 +}
2734 +
2735 +/****************************************************************************
2736 + * FUNCTION: get_val
2737 + ****************************************************************************
2738 + * Description: This routine is called to get values of divider and multiplier.
2739 + ***************************************************************************/
2740 +
2741 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
2742 +{
2743 + u32 temp_mul;
2744 + u32 temp_div;
2745 + u32 gcd;
2746 + u32 min_freq;
2747 + u32 max_freq;
2748 +
2749 + /* find gcd of base_freq, output_freq */
2750 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2751 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2752 + gcd = find_gcd(min_freq , max_freq);
2753 +
2754 + if(gcd == 0)
2755 + return; /* ERROR */
2756 +
2757 + /* compute values of multiplier and divider */
2758 + temp_mul = output_freq / gcd;
2759 + temp_div = base_freq / gcd;
2760 +
2761 +
2762 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2763 + if( temp_mul > PLL_MUL_MAXFACTOR )
2764 + {
2765 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2766 + return;
2767 +
2768 + find_approx(&temp_mul,&temp_div,base_freq);
2769 + }
2770 +
2771 + *multiplier = temp_mul;
2772 + *divider = temp_div;
2773 +}
2774 +
2775 +/****************************************************************************
2776 + * FUNCTION: find_approx
2777 + ****************************************************************************
2778 + * Description: This function gets the approx value of num/denom.
2779 + ***************************************************************************/
2780 +
2781 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
2782 +{
2783 + u32 num1;
2784 + u32 denom1;
2785 + u32 num2;
2786 + u32 denom2;
2787 + int32_t closest;
2788 + int32_t prev_closest;
2789 + u32 temp_num;
2790 + u32 temp_denom;
2791 + u32 normalize;
2792 + u32 gcd;
2793 + u32 output_freq;
2794 +
2795 + num1 = *num;
2796 + denom1 = *denom;
2797 +
2798 + prev_closest = 0x7fffffff; /* maximum possible value */
2799 + num2 = num1;
2800 + denom2 = denom1;
2801 +
2802 + /* start with max */
2803 + for(temp_num = 15; temp_num >=1; temp_num--)
2804 + {
2805 +
2806 + temp_denom = CEIL(temp_num * denom1, num1);
2807 + output_freq = (temp_num * base_freq) / temp_denom;
2808 +
2809 + if(temp_denom < 1)
2810 + {
2811 + break;
2812 + }
2813 + else
2814 + {
2815 + normalize = CEIL(num1,temp_num);
2816 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
2817 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2818 + {
2819 + prev_closest = closest;
2820 + num2 = temp_num;
2821 + denom2 = temp_denom;
2822 + }
2823 +
2824 + }
2825 +
2826 + }
2827 +
2828 + gcd = find_gcd(num2,denom2);
2829 + num2 = num2 / gcd;
2830 + denom2 = denom2 /gcd;
2831 +
2832 + *num = num2;
2833 + *denom = denom2;
2834 +}
2835 +
2836 +
2837 +/*****************************************************************************
2838 + * GPIO Control
2839 + *****************************************************************************/
2840 +
2841 +/****************************************************************************
2842 + * FUNCTION: tnetd73xx_gpio_init
2843 + ***************************************************************************/
2844 +void tnetd73xx_gpio_init()
2845 +{
2846 + /* Bring module out of reset */
2847 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2848 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2849 +}
2850 +
2851 +/****************************************************************************
2852 + * FUNCTION: tnetd73xx_gpio_ctrl
2853 + ***************************************************************************/
2854 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2855 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2856 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2857 +{
2858 + u32 pin_status;
2859 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
2860 + if (pin_mode == GPIO_PIN)
2861 + {
2862 + pin_status |= (1 << gpio_pin);
2863 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2864 +
2865 + /* Set pin direction */
2866 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2867 + if (pin_direction == GPIO_INPUT_PIN)
2868 + {
2869 + pin_status |= (1 << gpio_pin);
2870 + }
2871 + else /* GPIO_OUTPUT_PIN */
2872 + {
2873 + pin_status &= (~(1 << gpio_pin));
2874 + }
2875 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2876 + }
2877 + else /* FUNCTIONAL PIN */
2878 + {
2879 + pin_status &= (~(1 << gpio_pin));
2880 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2881 + }
2882 +
2883 +}
2884 +
2885 +/****************************************************************************
2886 + * FUNCTION: tnetd73xx_gpio_out
2887 + ***************************************************************************/
2888 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2889 +{
2890 + u32 pin_value;
2891 +
2892 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2893 + if (value == 1)
2894 + {
2895 + pin_value |= (1 << gpio_pin);
2896 + }
2897 + else
2898 + {
2899 + pin_value &= (~(1 << gpio_pin));
2900 + }
2901 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2902 +}
2903 +
2904 +/****************************************************************************
2905 + * FUNCTION: tnetd73xx_gpio_in
2906 + ***************************************************************************/
2907 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2908 +{
2909 + u32 pin_value;
2910 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
2911 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
2912 +}
2913 +
2914 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
2915 --- linux.old/arch/mips/config-shared.in 2005-10-21 16:43:18.917114000 +0200
2916 +++ linux.dev/arch/mips/config-shared.in 2005-11-10 01:12:43.950955750 +0100
2917 @@ -20,6 +20,16 @@
2918 mainmenu_option next_comment
2919 comment 'Machine selection'
2920 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2921 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2922 +if [ "$CONFIG_AR7" = "y" ]; then
2923 + choice 'Texas Instruments Reference Platform' \
2924 + "AR7DB CONFIG_AR7DB \
2925 + AR7RD CONFIG_AR7RD \
2926 + AR7WRD CONFIG_AR7WRD" AR7DB
2927 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
2928 + int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
2929 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2930 +fi
2931 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2932 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2933 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2934 @@ -239,6 +249,11 @@
2935 define_bool CONFIG_NONCOHERENT_IO y
2936 define_bool CONFIG_PC_KEYB y
2937 fi
2938 +if [ "$CONFIG_AR7" = "y" ]; then
2939 + define_bool CONFIG_IRQ_CPU y
2940 + define_bool CONFIG_NONCOHERENT_IO y
2941 + define_bool CONFIG_SWAP_IO_SPACE y
2942 +fi
2943 if [ "$CONFIG_CASIO_E55" = "y" ]; then
2944 define_bool CONFIG_IRQ_CPU y
2945 define_bool CONFIG_NONCOHERENT_IO y
2946 @@ -736,6 +751,7 @@
2947 mainmenu_option next_comment
2948 comment 'General setup'
2949 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2950 + "$CONFIG_AR7" = "y" -o \
2951 "$CONFIG_CASIO_E55" = "y" -o \
2952 "$CONFIG_DDB5074" = "y" -o \
2953 "$CONFIG_DDB5476" = "y" -o \
2954 @@ -797,6 +813,7 @@
2955 bool 'Networking support' CONFIG_NET
2956
2957 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2958 + "$CONFIG_AR7" = "y" -o \
2959 "$CONFIG_CASIO_E55" = "y" -o \
2960 "$CONFIG_DECSTATION" = "y" -o \
2961 "$CONFIG_IBM_WORKPAD" = "y" -o \
2962 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
2963 --- linux.old/arch/mips/kernel/head.S 2005-10-21 16:43:16.396956500 +0200
2964 +++ linux.dev/arch/mips/kernel/head.S 2005-11-10 01:10:45.807572250 +0100
2965 @@ -75,11 +75,11 @@
2966 * size!
2967 */
2968 NESTED(except_vec4, 0, sp)
2969 - .set push
2970 - .set noreorder
2971 -1: j 1b /* Dummy, will be replaced */
2972 - nop
2973 - .set pop
2974 + .set mips2
2975 + lui k0, 0x9400
2976 + ori k0, 0x200
2977 + jr k0
2978 + nop
2979 END(except_vec4)
2980
2981 /*
2982 diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
2983 --- linux.old/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
2984 +++ linux.dev/arch/mips/kernel/mips_ksyms.c 2005-11-10 01:10:45.811572500 +0100
2985 @@ -40,6 +40,12 @@
2986 extern long __strnlen_user_nocheck_asm(const char *s);
2987 extern long __strnlen_user_asm(const char *s);
2988
2989 +#ifdef CONFIG_AR7
2990 +#include <asm/ar7/adam2_env.h>
2991 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
2992 +#endif
2993 +
2994 +
2995 EXPORT_SYMBOL(mips_machtype);
2996 #ifdef CONFIG_EISA
2997 EXPORT_SYMBOL(EISA_bus);
2998 @@ -103,3 +109,10 @@
2999 #endif
3000
3001 EXPORT_SYMBOL(get_wchan);
3002 +
3003 +#ifdef CONFIG_AR7
3004 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3005 +EXPORT_SYMBOL_NOVERS(prom_getenv);
3006 +EXPORT_SYMBOL_NOVERS(prom_iterenv);
3007 +#endif
3008 +
3009 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3010 --- linux.old/arch/mips/kernel/setup.c 2005-10-21 16:43:16.396956500 +0200
3011 +++ linux.dev/arch/mips/kernel/setup.c 2005-11-10 01:14:16.376732000 +0100
3012 @@ -38,6 +38,7 @@
3013 #include <asm/io.h>
3014 #include <asm/ptrace.h>
3015 #include <asm/system.h>
3016 +#include <asm/addrspace.h>
3017
3018 struct cpuinfo_mips cpu_data[NR_CPUS];
3019 EXPORT_SYMBOL(cpu_data);
3020 @@ -88,7 +89,7 @@
3021 struct boot_mem_map boot_mem_map;
3022
3023 unsigned char aux_device_present;
3024 -extern char _ftext, _etext, _fdata, _edata, _end;
3025 +extern char _ftext, _etext, _fdata, _edata, _fbss, _end;
3026
3027 static char command_line[CL_SIZE];
3028 char saved_command_line[CL_SIZE];
3029 @@ -116,6 +117,7 @@
3030
3031 static struct resource code_resource = { "Kernel code" };
3032 static struct resource data_resource = { "Kernel data" };
3033 +static struct resource bss_resource = { "Kernel bss" };
3034
3035 asmlinkage void __init
3036 init_arch(int argc, char **argv, char **envp, int *prom_vec)
3037 @@ -272,7 +274,7 @@
3038 for (i = 0; i < boot_mem_map.nr_map; i++) {
3039 unsigned long start, end;
3040
3041 - if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3042 + if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3043 continue;
3044
3045 start = PFN_UP(boot_mem_map.map[i].addr);
3046 @@ -320,7 +322,8 @@
3047 #endif
3048
3049 /* Initialize the boot-time allocator with low memory only. */
3050 - bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
3051 + bootmap_size = init_bootmem_node(NODE_DATA(0), first_usable_pfn,
3052 + PFN_UP(PHYS_OFFSET), max_low_pfn);
3053
3054 /*
3055 * Register fully available low RAM pages with the bootmem allocator.
3056 @@ -371,11 +374,12 @@
3057 continue;
3058
3059 /* Register lowmem ranges */
3060 - free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
3061 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
3062 + size<<PAGE_SHIFT);
3063 }
3064
3065 /* Reserve the bootmap memory. */
3066 - reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3067 + reserve_bootmem_node(NODE_DATA(0), PFN_PHYS(first_usable_pfn), bootmap_size);
3068
3069 #ifdef CONFIG_BLK_DEV_INITRD
3070 /* Board specific code should have set up initrd_start and initrd_end */
3071 @@ -409,6 +413,8 @@
3072 code_resource.end = virt_to_bus(&_etext) - 1;
3073 data_resource.start = virt_to_bus(&_fdata);
3074 data_resource.end = virt_to_bus(&_edata) - 1;
3075 + bss_resource.start = virt_to_bus(&_fbss);
3076 + bss_resource.end = virt_to_bus(&_end) - 1;
3077
3078 /*
3079 * Request address space for all standard RAM.
3080 @@ -448,6 +454,7 @@
3081 */
3082 request_resource(res, &code_resource);
3083 request_resource(res, &data_resource);
3084 + request_resource(res, &bss_resource);
3085 }
3086 }
3087
3088 @@ -494,6 +501,7 @@
3089 void hp_setup(void);
3090 void au1x00_setup(void);
3091 void frame_info_init(void);
3092 + void ar7_setup(void);
3093
3094 frame_info_init();
3095 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3096 @@ -691,6 +699,11 @@
3097 pmc_yosemite_setup();
3098 break;
3099 #endif
3100 +#ifdef CONFIG_AR7
3101 + case MACH_GROUP_UNKNOWN:
3102 + ar7_setup();
3103 + break;
3104 +#endif
3105 default:
3106 panic("Unsupported architecture");
3107 }
3108 diff -urN linux.old/arch/mips/kernel/time.c linux.dev/arch/mips/kernel/time.c
3109 --- linux.old/arch/mips/kernel/time.c 2005-01-19 15:09:29.000000000 +0100
3110 +++ linux.dev/arch/mips/kernel/time.c 2005-11-10 01:12:43.950955750 +0100
3111 @@ -143,7 +143,6 @@
3112 expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
3113 write_c0_count(expirelo - cycles_per_jiffy);
3114 write_c0_compare(expirelo);
3115 - write_c0_count(count);
3116 }
3117
3118 int (*mips_timer_state)(void);
3119 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3120 --- linux.old/arch/mips/kernel/traps.c 2005-10-21 16:43:16.400956750 +0200
3121 +++ linux.dev/arch/mips/kernel/traps.c 2005-11-10 01:13:28.301727500 +0100
3122 @@ -869,9 +869,24 @@
3123
3124 exception_handlers[n] = handler;
3125 if (n == 0 && cpu_has_divec) {
3126 + printk(KERN_DEBUG "%s: using long jump via k0 to reach %08x\n",
3127 + __FUNCTION__, handler);
3128 + /* where does the 8 byte limit mentioned in head.S come from??? */
3129 + if (handler > 0x0fffffff) { /* maximum for single J instruction */
3130 + /* lui k0, 0x0000 */
3131 + *(volatile u32 *)(KSEG0+0x200) = 0x3c1a0000 | (handler >> 16);
3132 + /* ori k0, 0x0000 */
3133 + *(volatile u32 *)(KSEG0+0x204) = 0x375a0000 | (handler & 0xffff);
3134 + /* jr k0 */
3135 + *(volatile u32 *)(KSEG0+0x208) = 0x03400008;
3136 + /* nop */
3137 + *(volatile u32 *)(KSEG0+0x20C) = 0x00000000;
3138 + flush_icache_range(KSEG0+0x200, KSEG0+0x210);
3139 + } else {
3140 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3141 (0x03ffffff & (handler >> 2));
3142 - flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3143 + flush_icache_range(KSEG0+0x200, KSEG0+0x204);
3144 + }
3145 }
3146 return (void *)old_handler;
3147 }
3148 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3149 --- linux.old/arch/mips/mm/init.c 2004-02-18 14:36:30.000000000 +0100
3150 +++ linux.dev/arch/mips/mm/init.c 2005-11-10 01:14:16.376732000 +0100
3151 @@ -235,10 +235,13 @@
3152 #endif
3153 }
3154
3155 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
3156 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
3157 +
3158 void __init paging_init(void)
3159 {
3160 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3161 - unsigned long max_dma, high, low;
3162 + unsigned long max_dma, high, low, start;
3163
3164 pagetable_init();
3165
3166 @@ -247,7 +250,8 @@
3167 #endif
3168
3169 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
3170 - low = max_low_pfn;
3171 + start = START_PFN;
3172 + low = MAX_LOW_PFN - start;
3173 high = highend_pfn;
3174
3175 #ifdef CONFIG_ISA
3176 @@ -270,7 +274,8 @@
3177 zones_size[ZONE_HIGHMEM] = high - low;
3178 #endif
3179
3180 - free_area_init(zones_size);
3181 + free_area_init_node(0, NODE_DATA(0), 0, zones_size,
3182 + start << PAGE_SHIFT, 0);
3183 }
3184
3185 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3186 @@ -283,7 +288,7 @@
3187 for (i = 0; i < boot_mem_map.nr_map; i++) {
3188 unsigned long addr, end;
3189
3190 - if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3191 + if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3192 /* not usable memory */
3193 continue;
3194
3195 @@ -313,16 +318,17 @@
3196 max_mapnr = num_physpages = highend_pfn;
3197 num_mappedpages = max_low_pfn;
3198 #else
3199 - max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
3200 + max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
3201 #endif
3202 - high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
3203 -
3204 - totalram_pages += free_all_bootmem();
3205 +
3206 + high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
3207 +
3208 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
3209 totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */
3210
3211 reservedpages = ram = 0;
3212 - for (tmp = 0; tmp < max_low_pfn; tmp++)
3213 - if (page_is_ram(tmp)) {
3214 + for (tmp = 0; tmp < max_mapnr; tmp++)
3215 + if (page_is_ram(START_PFN + tmp)) {
3216 ram++;
3217 if (PageReserved(mem_map+tmp))
3218 reservedpages++;
3219 @@ -377,13 +383,13 @@
3220 #endif
3221
3222 extern char __init_begin, __init_end;
3223 -extern void prom_free_prom_memory(void) __init;
3224 +extern unsigned long prom_free_prom_memory(void) __init;
3225
3226 void free_initmem(void)
3227 {
3228 unsigned long addr;
3229
3230 - prom_free_prom_memory ();
3231 + totalram_pages += prom_free_prom_memory ();
3232
3233 addr = (unsigned long) &__init_begin;
3234 while (addr < (unsigned long) &__init_end) {
3235 diff -urN linux.old/drivers/char/Config.in linux.dev/drivers/char/Config.in
3236 --- linux.old/drivers/char/Config.in 2005-10-21 16:43:16.440959250 +0200
3237 +++ linux.dev/drivers/char/Config.in 2005-11-10 01:10:45.843574500 +0100
3238 @@ -188,6 +188,14 @@
3239 tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3240 fi
3241
3242 +if [ "$CONFIG_AR7" = "y" ]; then
3243 + bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3244 + dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3245 +
3246 + define_int CONFIG_AR7_VLYNQ_PORTS 2
3247 + tristate 'ADAM2 environment support (read-only)' CONFIG_AR7_ADAM2
3248 +fi
3249 +
3250 source drivers/i2c/Config.in
3251
3252 mainmenu_option next_comment
3253 diff -urN linux.old/drivers/char/Config.in.orig linux.dev/drivers/char/Config.in.orig
3254 --- linux.old/drivers/char/Config.in.orig 1970-01-01 01:00:00.000000000 +0100
3255 +++ linux.dev/drivers/char/Config.in.orig 2005-11-10 01:10:45.863575750 +0100
3256 @@ -0,0 +1,414 @@
3257 +#
3258 +# Character device configuration
3259 +#
3260 +mainmenu_option next_comment
3261 +comment 'Character devices'
3262 +
3263 +bool 'Virtual terminal' CONFIG_VT
3264 +if [ "$CONFIG_VT" = "y" ]; then
3265 + bool ' Support for console on virtual terminal' CONFIG_VT_CONSOLE
3266 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3267 + bool ' Support for Lasi/Dino PS2 port' CONFIG_GSC_PS2
3268 + fi
3269 +fi
3270 +tristate 'Standard/generic (8250/16550 and compatible UARTs) serial support' CONFIG_SERIAL
3271 +if [ "$CONFIG_SERIAL" = "y" ]; then
3272 + bool ' Support for console on serial port' CONFIG_SERIAL_CONSOLE
3273 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3274 + bool ' serial port on GSC support' CONFIG_SERIAL_GSC
3275 + fi
3276 + if [ "$CONFIG_IA64" = "y" ]; then
3277 + bool ' Support for serial port described by EFI HCDP table' CONFIG_SERIAL_HCDP
3278 + fi
3279 + if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
3280 + tristate ' Atomwide serial port support' CONFIG_ATOMWIDE_SERIAL
3281 + tristate ' Dual serial port support' CONFIG_DUALSP_SERIAL
3282 + fi
3283 +fi
3284 +dep_mbool 'Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED $CONFIG_SERIAL
3285 +if [ "$CONFIG_SERIAL_EXTENDED" = "y" ]; then
3286 + bool ' Support more than 4 serial ports' CONFIG_SERIAL_MANY_PORTS
3287 + bool ' Support for sharing serial interrupts' CONFIG_SERIAL_SHARE_IRQ
3288 + bool ' Autodetect IRQ on standard ports (unsafe)' CONFIG_SERIAL_DETECT_IRQ
3289 + bool ' Support special multiport boards' CONFIG_SERIAL_MULTIPORT
3290 + bool ' Support the Bell Technologies HUB6 card' CONFIG_HUB6
3291 +fi
3292 +bool 'Non-standard serial port support' CONFIG_SERIAL_NONSTANDARD
3293 +if [ "$CONFIG_SERIAL_NONSTANDARD" = "y" ]; then
3294 + tristate ' Computone IntelliPort Plus serial support' CONFIG_COMPUTONE
3295 + tristate ' Comtrol Rocketport support' CONFIG_ROCKETPORT
3296 + tristate ' Cyclades async mux support' CONFIG_CYCLADES
3297 + if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_CYCLADES" != "n" ]; then
3298 + bool ' Cyclades-Z interrupt mode operation (EXPERIMENTAL)' CONFIG_CYZ_INTR
3299 + fi
3300 + if [ "$CONFIG_X86_64" != "y" ]; then
3301 + tristate ' Digiboard Intelligent Async Support' CONFIG_DIGIEPCA
3302 + if [ "$CONFIG_DIGIEPCA" = "n" ]; then
3303 + tristate ' Digiboard PC/Xx Support' CONFIG_DIGI
3304 + fi
3305 + fi
3306 + dep_tristate ' Hayes ESP serial port support' CONFIG_ESPSERIAL $CONFIG_ISA
3307 + tristate ' Moxa Intellio support' CONFIG_MOXA_INTELLIO
3308 + tristate ' Moxa SmartIO support' CONFIG_MOXA_SMARTIO
3309 + if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
3310 + dep_tristate ' Multi-Tech multiport card support (EXPERIMENTAL)' CONFIG_ISI m
3311 + fi
3312 + tristate ' Microgate SyncLink card support' CONFIG_SYNCLINK
3313 + tristate ' SyncLink Multiport support' CONFIG_SYNCLINKMP
3314 + tristate ' HDLC line discipline support' CONFIG_N_HDLC
3315 + tristate ' SDL RISCom/8 card support' CONFIG_RISCOM8
3316 + if [ "$CONFIG_X86_64" != "y" ]; then
3317 + tristate ' Specialix IO8+ card support' CONFIG_SPECIALIX
3318 + if [ "$CONFIG_SPECIALIX" != "n" ]; then
3319 + bool ' Specialix DTR/RTS pin is RTS' CONFIG_SPECIALIX_RTSCTS
3320 + fi
3321 + tristate ' Specialix SX (and SI) card support' CONFIG_SX
3322 + tristate ' Specialix RIO system support' CONFIG_RIO
3323 + if [ "$CONFIG_RIO" != "n" ]; then
3324 + bool ' Support really old RIO/PCI cards' CONFIG_RIO_OLDPCI
3325 + fi
3326 + fi
3327 + bool ' Stallion multiport serial support' CONFIG_STALDRV
3328 + if [ "$CONFIG_STALDRV" = "y" ]; then
3329 + tristate ' Stallion EasyIO or EC8/32 support' CONFIG_STALLION
3330 + tristate ' Stallion EC8/64, ONboard, Brumby support' CONFIG_ISTALLION
3331 + fi
3332 + if [ "$CONFIG_PARISC" = "y" ]; then
3333 + if [ "$CONFIG_PDC_CONSOLE" != "y" ]; then
3334 + bool ' Serial MUX support' CONFIG_SERIAL_MUX CONFIG_SERIAL_NONSTANDARD
3335 + fi
3336 + if [ "$CONFIG_SERIAL_MUX" != "y" ]; then
3337 + bool ' PDC software console support' CONFIG_PDC_CONSOLE CONFIG_SERIAL_NONSTANDARD
3338 + fi
3339 + fi
3340 + if [ "$CONFIG_MIPS" = "y" ]; then
3341 + bool ' TX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
3342 + dep_bool ' Console on TX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
3343 + bool ' TMPTX39XX/49XX serial port support' CONFIG_SERIAL_TXX9
3344 + dep_bool ' Console on TMPTX39XX/49XX serial port' CONFIG_SERIAL_TXX9_CONSOLE $CONFIG_SERIAL_TXX9
3345 + if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3346 + bool ' Enable Au1x00 UART Support' CONFIG_AU1X00_UART
3347 + if [ "$CONFIG_AU1X00_UART" = "y" ]; then
3348 + bool ' Enable Au1x00 serial console' CONFIG_AU1X00_SERIAL_CONSOLE
3349 + fi
3350 + dep_tristate ' Au1x00 USB TTY Device support' CONFIG_AU1X00_USB_TTY $CONFIG_SOC_AU1X00
3351 + if [ "$CONFIG_AU1000_USB_TTY" != "y" ]; then
3352 + dep_tristate ' Au1x00 USB Raw Device support' CONFIG_AU1X00_USB_RAW $CONFIG_SOC_AU1X00
3353 + fi
3354 + if [ "$CONFIG_AU1X00_USB_TTY" != "n" -o \
3355 + "$CONFIG_AU1X00_USB_RAW" != "n" ]; then
3356 + define_bool CONFIG_AU1X00_USB_DEVICE y
3357 + fi
3358 + fi
3359 + bool ' TXx927 SIO support' CONFIG_TXX927_SERIAL
3360 + if [ "$CONFIG_TXX927_SERIAL" = "y" ]; then
3361 + bool ' TXx927 SIO Console support' CONFIG_TXX927_SERIAL_CONSOLE
3362 + fi
3363 + if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]; then
3364 + bool ' Support for BCM1xxx onchip DUART' CONFIG_SIBYTE_SB1250_DUART
3365 + if [ "$CONFIG_SIBYTE_SB1250_DUART" = "y" ]; then
3366 + bool ' Console on BCM1xxx DUART' CONFIG_SIBYTE_SB1250_DUART_CONSOLE
3367 + if [ "$CONFIG_SIBYTE_SB1250_DUART_CONSOLE" = "y" ]; then
3368 + define_bool CONFIG_SERIAL_CONSOLE y
3369 + fi
3370 + fi
3371 + fi
3372 + fi
3373 + if [ "$CONFIG_DECSTATION" = "y" ]; then
3374 + bool ' DECstation serial support' CONFIG_SERIAL_DEC
3375 + dep_bool ' Support for console on a DECstation serial port' CONFIG_SERIAL_DEC_CONSOLE $CONFIG_SERIAL_DEC
3376 + dep_bool ' DZ11 serial support' CONFIG_DZ $CONFIG_SERIAL_DEC $CONFIG_MIPS32
3377 + dep_bool ' Z85C30 serial support' CONFIG_ZS $CONFIG_SERIAL_DEC $CONFIG_TC
3378 + fi
3379 + if [ "$CONFIG_SGI_IP22" = "y" ]; then
3380 + bool ' SGI Zilog85C30 serial support' CONFIG_IP22_SERIAL
3381 + fi
3382 + if [ "$CONFIG_IA64" = "y" ]; then
3383 + bool ' SGI SN2 l1 serial port support' CONFIG_SGI_L1_SERIAL
3384 + if [ "$CONFIG_SGI_L1_SERIAL" = "y" ]; then
3385 + bool ' SGI SN2 l1 Console support' CONFIG_SGI_L1_SERIAL_CONSOLE
3386 + fi
3387 + if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ]; then
3388 + bool ' SGI SN2 IOC4 serial port support' CONFIG_SGI_IOC4_SERIAL
3389 + fi
3390 + fi
3391 +fi
3392 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
3393 + tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
3394 +fi
3395 +if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
3396 + bool 'DC21285 serial port support' CONFIG_SERIAL_21285
3397 + if [ "$CONFIG_SERIAL_21285" = "y" ]; then
3398 + if [ "$CONFIG_OBSOLETE" = "y" ]; then
3399 + bool ' Use /dev/ttyS0 device (OBSOLETE)' CONFIG_SERIAL_21285_OLD
3400 + fi
3401 + bool ' Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE
3402 + fi
3403 + if [ "$CONFIG_PARISC" = "y" ]; then
3404 + bool ' PDC software console support' CONFIG_PDC_CONSOLE
3405 + fi
3406 +fi
3407 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
3408 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3409 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3410 + define_bool CONFIG_IT8172_CIR y
3411 + else
3412 + bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
3413 + fi
3414 + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
3415 + bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
3416 +fi
3417 +if [ "$CONFIG_MIPS_IVR" = "y" ]; then
3418 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3419 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3420 + define_bool CONFIG_IT8172_CIR y