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[openwrt/svn-archive/archive.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux.old/Makefile linux.dev/Makefile
2 --- linux.old/Makefile 2005-10-21 16:43:16.316951500 +0200
3 +++ linux.dev/Makefile 2005-11-10 01:10:45.771570000 +0100
4 @@ -91,7 +91,7 @@
5
6 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
7
8 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
9 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
10 -fno-strict-aliasing -fno-common
11 ifndef CONFIG_FRAME_POINTER
12 CFLAGS += -fomit-frame-pointer
13 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
14 --- linux.old/arch/mips/Makefile 2005-10-21 16:43:16.316951500 +0200
15 +++ linux.dev/arch/mips/Makefile 2005-11-10 01:10:45.775570250 +0100
16 @@ -369,6 +369,16 @@
17 endif
18
19 #
20 +# Texas Instruments AR7
21 +#
22 +
23 +ifdef CONFIG_AR7
24 +LIBS += arch/mips/ar7/ar7.o
25 +SUBDIRS += arch/mips/ar7
26 +LOADADDR += 0x94020000
27 +endif
28 +
29 +#
30 # DECstation family
31 #
32 ifdef CONFIG_DECSTATION
33 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
34 --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
35 +++ linux.dev/arch/mips/ar7/Makefile 2005-11-10 01:13:51.443173750 +0100
36 @@ -0,0 +1,14 @@
37 +.S.s:
38 + $(CPP) $(AFLAGS) $< -o $*.s
39 +
40 +.S.o:
41 + $(CC) $(AFLAGS) -c $< -o $*.o
42 +
43 +EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
44 +O_TARGET := ar7.o
45 +
46 +obj-y := tnetd73xx_misc.o misc.o
47 +export-objs := misc.o irq.o init.o
48 +obj-y += setup.o irq.o int-handler.o reset.o init.o psp_env.o memory.o promlib.o cmdline.o
49 +
50 +include $(TOPDIR)/Rules.make
51 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
52 --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
53 +++ linux.dev/arch/mips/ar7/cmdline.c 2005-11-10 01:14:16.372731750 +0100
54 @@ -0,0 +1,88 @@
55 +/*
56 + * Carsten Langgaard, carstenl@mips.com
57 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
58 + *
59 + * This program is free software; you can distribute it and/or modify it
60 + * under the terms of the GNU General Public License (Version 2) as
61 + * published by the Free Software Foundation.
62 + *
63 + * This program is distributed in the hope it will be useful, but WITHOUT
64 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
65 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
66 + * for more details.
67 + *
68 + * You should have received a copy of the GNU General Public License along
69 + * with this program; if not, write to the Free Software Foundation, Inc.,
70 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
71 + *
72 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
73 + */
74 +#include <linux/init.h>
75 +#include <linux/string.h>
76 +
77 +#include <asm/bootinfo.h>
78 +
79 +extern int prom_argc;
80 +extern int *_prom_argv;
81 +
82 +/*
83 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
84 + * This macro take care of sign extension.
85 + */
86 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
87 +
88 +char arcs_cmdline[CL_SIZE];
89 +#ifdef CONFIG_CMDLINE_BOOL
90 +char __initdata cfg_cmdline[] = CONFIG_CMDLINE;
91 +#endif
92 +
93 +char * __init prom_getcmdline(void)
94 +{
95 + return &(arcs_cmdline[0]);
96 +}
97 +
98 +
99 +void __init prom_init_cmdline(void)
100 +{
101 + char *cp, *end;
102 + int actr;
103 + char *env_cmdline = prom_getenv("kernel_args");
104 + size_t len;
105 +
106 + actr = 1; /* Always ignore argv[0] */
107 +
108 + cp = end = &(arcs_cmdline[0]);
109 + end += sizeof(arcs_cmdline);
110 +
111 + if (env_cmdline) {
112 + len = strlen(env_cmdline);
113 + if (len > end - cp - 1)
114 + len = end - cp - 1;
115 + strncpy(cp, env_cmdline, len);
116 + cp += len;
117 + *cp++ = ' ';
118 + }
119 +#ifdef CONFIG_CMDLINE_BOOL
120 + else {
121 + len = strlen(cfg_cmdline);
122 + if (len > end - cp - 1)
123 + len = end - cp - 1;
124 + strncpy(cp, cfg_cmdline, len);
125 + cp += len;
126 + *cp++ = ' ';
127 + }
128 +#endif
129 +
130 + while(actr < prom_argc) {
131 + len = strlen(prom_argv(actr));
132 + if (len > end - cp - 1)
133 + break;
134 + strncpy(cp, prom_argv(actr), len);
135 + cp += len;
136 + *cp++ = ' ';
137 + actr++;
138 + }
139 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
140 + --cp;
141 + *cp = '\0';
142 +}
143 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
144 --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
145 +++ linux.dev/arch/mips/ar7/init.c 2005-11-10 01:10:45.795571500 +0100
146 @@ -0,0 +1,199 @@
147 +/*
148 + * Carsten Langgaard, carstenl@mips.com
149 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
150 + *
151 + * This program is free software; you can distribute it and/or modify it
152 + * under the terms of the GNU General Public License (Version 2) as
153 + * published by the Free Software Foundation.
154 + *
155 + * This program is distributed in the hope it will be useful, but WITHOUT
156 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
157 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
158 + * for more details.
159 + *
160 + * You should have received a copy of the GNU General Public License along
161 + * with this program; if not, write to the Free Software Foundation, Inc.,
162 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
163 + *
164 + * PROM library initialisation code.
165 + */
166 +#include <linux/config.h>
167 +#include <linux/init.h>
168 +#include <linux/string.h>
169 +#include <linux/kernel.h>
170 +#include <linux/module.h>
171 +
172 +#include <asm/io.h>
173 +#include <asm/mips-boards/prom.h>
174 +#include <asm/mips-boards/generic.h>
175 +
176 +#include <asm/ar7/adam2_env.h>
177 +
178 +int prom_argc;
179 +int *_prom_argv, *_prom_envp;
180 +
181 +/* max # of Adam2 environment variables */
182 +#define MAX_ENV_ENTRY 80
183 +
184 +static t_env_var local_envp[MAX_ENV_ENTRY];
185 +static int env_type = 0;
186 +int init_debug = 0;
187 +
188 +unsigned int max_env_entry;
189 +
190 +extern char *prom_psp_getenv(char *envname);
191 +
192 +static inline char *prom_adam2_getenv(char *envname)
193 +{
194 + /*
195 + * Return a pointer to the given environment variable.
196 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
197 + * in the PROM structures are only 32-bit, so we need some
198 + * workarounds, if we are running in 64-bit mode.
199 + */
200 + int i;
201 + t_env_var *env = (t_env_var *) local_envp;
202 +
203 + if (strcmp("bootloader", envname) == 0)
204 + return "Adam2";
205 +
206 + i = strlen(envname);
207 + while (env->name) {
208 + if(strncmp(envname, env->name, i) == 0) {
209 + return(env->val);
210 + }
211 + env++;
212 + }
213 +
214 + return NULL;
215 +}
216 +
217 +/* XXX "bootloader" won't be returned.
218 + * Better make it an element of local_envp */
219 +static inline t_env_var *
220 +prom_adam2_iterenv(t_env_var *env) {
221 + if (!env)
222 + env = local_envp;
223 + else
224 + env++;
225 + if (env - local_envp > MAX_ENV_ENTRY || !env->name)
226 + return 0;
227 + return env;
228 +}
229 +
230 +char *prom_getenv(char *envname)
231 +{
232 + if (env_type == 1)
233 + return prom_psp_getenv(envname);
234 + else
235 + return prom_adam2_getenv(envname);
236 +}
237 +
238 +t_env_var *
239 +prom_iterenv(t_env_var *last)
240 +{
241 + if (env_type == 1)
242 + return 0; /* not yet implemented */
243 + return prom_adam2_iterenv(last);
244 +}
245 +
246 +static inline unsigned char str2hexnum(unsigned char c)
247 +{
248 + if (c >= '0' && c <= '9')
249 + return c - '0';
250 + if (c >= 'a' && c <= 'f')
251 + return c - 'a' + 10;
252 + return 0; /* foo */
253 +}
254 +
255 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
256 +{
257 + int i;
258 +
259 + for (i = 0; i < 6; i++) {
260 + unsigned char num;
261 +
262 + if((*str == '.') || (*str == ':'))
263 + str++;
264 + num = str2hexnum(*str++) << 4;
265 + num |= (str2hexnum(*str++));
266 + ea[i] = num;
267 + }
268 +}
269 +
270 +int get_ethernet_addr(char *ethernet_addr)
271 +{
272 + char *ethaddr_str;
273 +
274 + ethaddr_str = prom_getenv("ethaddr");
275 + if (!ethaddr_str) {
276 + printk("ethaddr not set in boot prom\n");
277 + return -1;
278 + }
279 + str2eaddr(ethernet_addr, ethaddr_str);
280 +
281 + if (init_debug > 1) {
282 + int i;
283 + printk("get_ethernet_addr: ");
284 + for (i=0; i<5; i++)
285 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
286 + printk("%02x\n", *(ethernet_addr+i));
287 + }
288 +
289 + return 0;
290 +}
291 +
292 +struct psbl_rec {
293 + unsigned int psbl_size;
294 + unsigned int env_base;
295 + unsigned int env_size;
296 + unsigned int ffs_base;
297 + unsigned int ffs_size;
298 +};
299 +
300 +static const char psp_env_version[] = "TIENV0.8";
301 +
302 +int __init prom_init(int argc, char **argv, char **envp)
303 +{
304 + int i;
305 +
306 + t_env_var *env = (t_env_var *) envp;
307 + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
308 + void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
309 +
310 + prom_argc = argc;
311 + _prom_argv = (int *)argv;
312 + _prom_envp = (int *)envp;
313 +
314 + if(strcmp(psp_env, psp_env_version) == 0) {
315 + /* PSPBOOT */
316 +
317 + env_type = 1;
318 + _prom_envp = psp_env;
319 + max_env_entry = (psbl->env_size / 16) - 1;
320 + } else {
321 + /* Copy what we need locally so we are not dependent on
322 + * bootloader RAM. In Adam2, the environment parameters
323 + * are in flash but the table that references them is in
324 + * RAM
325 + */
326 +
327 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
328 + if (env->name) {
329 + local_envp[i].name = env->name;
330 + local_envp[i].val = env->val;
331 + } else {
332 + local_envp[i].name = NULL;
333 + local_envp[i].val = NULL;
334 + }
335 + }
336 + }
337 +
338 + set_io_port_base(0);
339 +
340 + prom_printf("\nLINUX started...\n");
341 + prom_init_cmdline();
342 + prom_meminit();
343 +
344 + return 0;
345 +}
346 diff -urN linux.old/arch/mips/ar7/int-handler.S linux.dev/arch/mips/ar7/int-handler.S
347 --- linux.old/arch/mips/ar7/int-handler.S 1970-01-01 01:00:00.000000000 +0100
348 +++ linux.dev/arch/mips/ar7/int-handler.S 2005-11-10 01:12:43.938955000 +0100
349 @@ -0,0 +1,63 @@
350 +/*
351 + * Copyright 2004 PMC-Sierra Inc.
352 + * Author: Manish Lachwani (lachwani@pmc-sierra.com)
353 + * Adaption for AR7: Enrik Berkhan <enrik@akk.org>
354 + *
355 + * First-level interrupt dispatcher for the TI AR7
356 + *
357 + * This program is free software; you can redistribute it and/or modify it
358 + * under the terms of the GNU General Public License as published by the
359 + * Free Software Foundation; either version 2 of the License, or (at your
360 + * option) any later version.
361 + */
362 +#define __ASSEMBLY__
363 +#include <linux/config.h>
364 +#include <asm/asm.h>
365 +#include <asm/mipsregs.h>
366 +#include <asm/addrspace.h>
367 +#include <asm/regdef.h>
368 +#include <asm/stackframe.h>
369 +
370 +/*
371 + * First level interrupt dispatcher for TI AR7 based boards
372 + */
373 +
374 + .align 5
375 + NESTED(ar7IRQ, PT_SIZE, sp)
376 + SAVE_ALL
377 + CLI
378 + .set at
379 +
380 + mfc0 t0, CP0_CAUSE
381 + mfc0 t2, CP0_STATUS
382 +
383 + and t0, t2
384 +
385 + andi t1, t0, STATUSF_IP2 /* hw0 hardware interrupt */
386 + bnez t1, ll_hw0_irq
387 +
388 + andi t1, t0, STATUSF_IP7 /* R4k CPU timer */
389 + bnez t1, ll_timer_irq
390 +
391 + .set reorder
392 +
393 + /* wrong alarm or masked ... */
394 + j spurious_interrupt
395 + nop
396 + END(ar7IRQ)
397 +
398 + .align 5
399 +
400 +ll_hw0_irq:
401 + li a0, 2
402 + move a1, sp
403 + jal do_IRQ
404 + j ret_from_irq
405 +
406 +ll_timer_irq:
407 + li a0, 7
408 + move a1, sp
409 + jal do_IRQ
410 + j ret_from_irq
411 +
412 +
413 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
414 --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
415 +++ linux.dev/arch/mips/ar7/irq.c 2005-11-10 01:12:43.938955000 +0100
416 @@ -0,0 +1,427 @@
417 +/*
418 + * Nitin Dhingra, iamnd@ti.com
419 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
420 + *
421 + * ########################################################################
422 + *
423 + * This program is free software; you can distribute it and/or modify it
424 + * under the terms of the GNU General Public License (Version 2) as
425 + * published by the Free Software Foundation.
426 + *
427 + * This program is distributed in the hope it will be useful, but WITHOUT
428 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
429 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
430 + * for more details.
431 + *
432 + * You should have received a copy of the GNU General Public License along
433 + * with this program; if not, write to the Free Software Foundation, Inc.,
434 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
435 + *
436 + * ########################################################################
437 + *
438 + * Routines for generic manipulation of the interrupts found on the Texas
439 + * Instruments avalanche board
440 + *
441 + */
442 +
443 +#include <linux/init.h>
444 +#include <linux/interrupt.h>
445 +
446 +#include <asm/irq.h>
447 +#include <asm/mipsregs.h>
448 +#include <asm/ar7/ar7.h>
449 +#include <asm/ar7/avalanche_intc.h>
450 +
451 +#define shutdown_avalanche_irq disable_avalanche_irq
452 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
453 +
454 +static unsigned int startup_avalanche_irq(unsigned int irq);
455 +static void end_avalanche_irq(unsigned int irq);
456 +void enable_avalanche_irq(unsigned int irq_nr);
457 +void disable_avalanche_irq(unsigned int irq_nr);
458 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs);
459 +
460 +static struct hw_interrupt_type avalanche_irq_type = {
461 + "AR7",
462 + startup_avalanche_irq,
463 + shutdown_avalanche_irq,
464 + enable_avalanche_irq,
465 + disable_avalanche_irq,
466 + mask_and_ack_avalanche_irq,
467 + end_avalanche_irq,
468 + NULL
469 +};
470 +
471 +static int ar7_irq_base;
472 +
473 +static struct irqaction ar7_hw0_action = {
474 + ar7_hw0_interrupt, 0, 0, "AR7 on hw0", NULL, NULL
475 +};
476 +
477 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
478 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
479 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
480 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
481 +
482 +/*
483 + This remaps interrupts to exist on other channels than the default
484 + channels. essentially we can use the line # as the index for this
485 + array
486 + */
487 +
488 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
489 +unsigned long uni_secondary_interrupt = 0;
490 +
491 +static void end_avalanche_irq(unsigned int irq)
492 +{
493 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
494 + enable_avalanche_irq(irq);
495 +}
496 +
497 +void disable_avalanche_irq(unsigned int irq_nr)
498 +{
499 + unsigned long flags;
500 + unsigned long chan_nr=0;
501 +
502 + save_and_cli(flags);
503 +
504 + /* irq_nr represents the line number for the interrupt. We must
505 + * disable the channel number associated with that line number.
506 + */
507 +
508 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
509 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
510 + else
511 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
512 +
513 + /* disable the interrupt channel bit */
514 +
515 + /* primary interrupt #'s 0-31 */
516 +
517 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
518 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
519 +
520 + /* primary interrupt #'s 32-39 */
521 +
522 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
523 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
524 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
525 +
526 + else /* secondary interrupt #'s 0-31 */
527 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
528 +
529 + restore_flags(flags);
530 +}
531 +
532 +void enable_avalanche_irq(unsigned int irq_nr)
533 +{
534 + unsigned long flags;
535 + unsigned long chan_nr=0;
536 +
537 + save_and_cli(flags);
538 +
539 + /* irq_nr represents the line number for the interrupt. We must
540 + * disable the channel number associated with that line number.
541 + */
542 +
543 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
544 + chan_nr = AVINTNUM(irq_nr);
545 + else
546 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
547 +
548 + /* enable the interrupt channel bit */
549 +
550 + /* primary interrupt #'s 0-31 */
551 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
552 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
553 +
554 + /* primary interrupt #'s 32 throuth 39 */
555 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
556 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
557 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
558 +
559 + else /* secondary interrupt #'s 0-31 */
560 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
561 +
562 + restore_flags(flags);
563 +}
564 +
565 +static unsigned int startup_avalanche_irq(unsigned int irq)
566 +{
567 + enable_avalanche_irq(irq);
568 + return 0; /* never anything pending */
569 +}
570 +
571 +void __init ar7_irq_init(int base)
572 +{
573 + int i;
574 +
575 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
576 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
577 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
578 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
579 +
580 + /* Disable interrupts and clear pending
581 + */
582 +
583 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
584 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
585 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
586 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
587 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
588 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
589 +
590 +
591 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
592 + /* hack for speeding up the pacing. */
593 + printk("the pacing pre-scalar has been set as 600.\n");
594 + avalanche_hw0_ipaceregs->ipacep = 600;
595 + /* Channel to line mapping, Line to Channel mapping */
596 +
597 + for(i = 0; i < 40; i++)
598 + avalanche_int_set(i,i);
599 +
600 + ar7_irq_base = base;
601 + for (i = base; i <= base+40; i++)
602 + {
603 + irq_desc[i].status = IRQ_DISABLED;
604 + irq_desc[i].action = 0;
605 + irq_desc[i].depth = 1;
606 + irq_desc[i].handler = &avalanche_irq_type;
607 + }
608 +
609 + setup_irq(2, &ar7_hw0_action);
610 + set_c0_status(IE_IRQ0);
611 +
612 + return;
613 +}
614 +
615 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs)
616 +{
617 + int irq;
618 + unsigned long int_line_number, status;
619 + int i, chan_nr = 0;
620 +
621 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
622 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
623 +
624 + if(chan_nr < 32) /* primary 0-31 */
625 + {
626 + if( chan_nr != uni_secondary_interrupt)
627 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
628 +
629 + }
630 +
631 + if((chan_nr < 40) && (chan_nr > 31)) /* primary 32-39 */
632 + {
633 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-32));
634 + }
635 +
636 +
637 + /* If the Priority Interrupt Index Register returns 40 then no
638 + * interrupts are pending
639 + */
640 +
641 + if(chan_nr == 40)
642 + return;
643 +
644 + if(chan_nr == uni_secondary_interrupt) /* secondary 0-31 */
645 + {
646 + status = avalanche_hw0_ecregs->exsr;
647 + for(i=0; i < 32; i++)
648 + {
649 + if (status & 1<<i)
650 + {
651 + /* clear secondary interrupt */
652 + avalanche_hw0_ecregs->excr = 1 << i;
653 + break;
654 + }
655 + }
656 + irq = i+40;
657 +
658 + /* clear the universal secondary interrupt */
659 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
660 +
661 + }
662 + else
663 + irq = chan_nr;
664 +
665 + do_IRQ(irq + ar7_irq_base, regs);
666 + return;
667 +}
668 +
669 +void avalanche_int_set(int channel, int line)
670 +{
671 + switch(channel)
672 + {
673 + case(0):
674 + avalanche_hw0_chregs->cintnr0 = line;
675 + break;
676 + case(1):
677 + avalanche_hw0_chregs->cintnr1 = line;
678 + break;
679 + case(2):
680 + avalanche_hw0_chregs->cintnr2 = line;
681 + break;
682 + case(3):
683 + avalanche_hw0_chregs->cintnr3 = line;
684 + break;
685 + case(4):
686 + avalanche_hw0_chregs->cintnr4 = line;
687 + break;
688 + case(5):
689 + avalanche_hw0_chregs->cintnr5 = line;
690 + break;
691 + case(6):
692 + avalanche_hw0_chregs->cintnr6 = line;
693 + break;
694 + case(7):
695 + avalanche_hw0_chregs->cintnr7 = line;
696 + break;
697 + case(8):
698 + avalanche_hw0_chregs->cintnr8 = line;
699 + break;
700 + case(9):
701 + avalanche_hw0_chregs->cintnr9 = line;
702 + break;
703 + case(10):
704 + avalanche_hw0_chregs->cintnr10 = line;
705 + break;
706 + case(11):
707 + avalanche_hw0_chregs->cintnr11 = line;
708 + break;
709 + case(12):
710 + avalanche_hw0_chregs->cintnr12 = line;
711 + break;
712 + case(13):
713 + avalanche_hw0_chregs->cintnr13 = line;
714 + break;
715 + case(14):
716 + avalanche_hw0_chregs->cintnr14 = line;
717 + break;
718 + case(15):
719 + avalanche_hw0_chregs->cintnr15 = line;
720 + break;
721 + case(16):
722 + avalanche_hw0_chregs->cintnr16 = line;
723 + break;
724 + case(17):
725 + avalanche_hw0_chregs->cintnr17 = line;
726 + break;
727 + case(18):
728 + avalanche_hw0_chregs->cintnr18 = line;
729 + break;
730 + case(19):
731 + avalanche_hw0_chregs->cintnr19 = line;
732 + break;
733 + case(20):
734 + avalanche_hw0_chregs->cintnr20 = line;
735 + break;
736 + case(21):
737 + avalanche_hw0_chregs->cintnr21 = line;
738 + break;
739 + case(22):
740 + avalanche_hw0_chregs->cintnr22 = line;
741 + break;
742 + case(23):
743 + avalanche_hw0_chregs->cintnr23 = line;
744 + break;
745 + case(24):
746 + avalanche_hw0_chregs->cintnr24 = line;
747 + break;
748 + case(25):
749 + avalanche_hw0_chregs->cintnr25 = line;
750 + break;
751 + case(26):
752 + avalanche_hw0_chregs->cintnr26 = line;
753 + break;
754 + case(27):
755 + avalanche_hw0_chregs->cintnr27 = line;
756 + break;
757 + case(28):
758 + avalanche_hw0_chregs->cintnr28 = line;
759 + break;
760 + case(29):
761 + avalanche_hw0_chregs->cintnr29 = line;
762 + break;
763 + case(30):
764 + avalanche_hw0_chregs->cintnr30 = line;
765 + break;
766 + case(31):
767 + avalanche_hw0_chregs->cintnr31 = line;
768 + break;
769 + case(32):
770 + avalanche_hw0_chregs->cintnr32 = line;
771 + break;
772 + case(33):
773 + avalanche_hw0_chregs->cintnr33 = line;
774 + break;
775 + case(34):
776 + avalanche_hw0_chregs->cintnr34 = line;
777 + break;
778 + case(35):
779 + avalanche_hw0_chregs->cintnr35 = line;
780 + break;
781 + case(36):
782 + avalanche_hw0_chregs->cintnr36 = line;
783 + break;
784 + case(37):
785 + avalanche_hw0_chregs->cintnr37 = line;
786 + break;
787 + case(38):
788 + avalanche_hw0_chregs->cintnr38 = line;
789 + break;
790 + case(39):
791 + avalanche_hw0_chregs->cintnr39 = line;
792 + break;
793 + default:
794 + printk("Error: Unknown Avalanche interrupt channel\n");
795 + }
796 +
797 + line_to_channel[line] = channel; /* Suraj check */
798 +
799 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
800 + uni_secondary_interrupt = line;
801 +
802 +}
803 +
804 +
805 +#define AVALANCHE_MAX_PACING_BLK 3
806 +#define AVALANCHE_PACING_LOW_VAL 2
807 +#define AVALANCHE_PACING_HIGH_VAL 63
808 +
809 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
810 + unsigned int pace_value)
811 +{
812 + unsigned int blk_offset;
813 + unsigned long flags;
814 +
815 + if(irq_nr < MIPS_EXCEPTION_OFFSET &&
816 + irq_nr >= AVALANCHE_INT_END_PRIMARY)
817 + return (0);
818 +
819 + if(blk_num > AVALANCHE_MAX_PACING_BLK)
820 + return(-1);
821 +
822 + if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
823 + pace_value < AVALANCHE_PACING_LOW_VAL)
824 + return(-1);
825 +
826 + blk_offset = blk_num*8;
827 +
828 + save_and_cli(flags);
829 +
830 + /* disable the interrupt pacing, if enabled previously */
831 + avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
832 +
833 + /* clear the pacing map */
834 + avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
835 +
836 + /* setup the new values */
837 + avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
838 + avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
839 +
840 + restore_flags(flags);
841 +
842 + return(0);
843 +}
844 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
845 --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
846 +++ linux.dev/arch/mips/ar7/memory.c 2005-11-10 01:14:16.372731750 +0100
847 @@ -0,0 +1,103 @@
848 +/*
849 + * Carsten Langgaard, carstenl@mips.com
850 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
851 + *
852 + * ########################################################################
853 + *
854 + * This program is free software; you can distribute it and/or modify it
855 + * under the terms of the GNU General Public License (Version 2) as
856 + * published by the Free Software Foundation.
857 + *
858 + * This program is distributed in the hope it will be useful, but WITHOUT
859 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
860 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
861 + * for more details.
862 + *
863 + * You should have received a copy of the GNU General Public License along
864 + * with this program; if not, write to the Free Software Foundation, Inc.,
865 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
866 + *
867 + * ########################################################################
868 + *
869 + */
870 +
871 +#include <linux/config.h>
872 +#include <linux/init.h>
873 +#include <linux/mm.h>
874 +#include <linux/bootmem.h>
875 +
876 +#include <asm/bootinfo.h>
877 +#include <asm/page.h>
878 +#include <asm/mips-boards/prom.h>
879 +
880 +extern char _ftext;
881 +extern int preserve_adam2;
882 +
883 +void __init prom_meminit(void)
884 +{
885 + char *memsize_str;
886 + unsigned long memsize, adam2size;
887 +
888 + /* assume block before kernel is used by bootloader */
889 + adam2size = __pa(&_ftext) - PHYS_OFFSET;
890 +
891 + memsize_str = prom_getenv("memsize");
892 + if (!memsize_str) {
893 + memsize = 0x02000000;
894 + } else {
895 + memsize = simple_strtol(memsize_str, NULL, 0);
896 + }
897 +
898 +#if 0
899 + add_memory_region(0x00000000, PHYS_OFFSET, BOOT_MEM_RESERVED);
900 +#endif
901 + add_memory_region(PHYS_OFFSET, adam2size, BOOT_MEM_ROM_DATA);
902 + add_memory_region(PHYS_OFFSET+adam2size, memsize-adam2size,
903 + BOOT_MEM_RAM);
904 +}
905 +
906 +unsigned long __init prom_free_prom_memory (void)
907 +{
908 + int i;
909 + unsigned long freed = 0;
910 + unsigned long addr;
911 +
912 + if (preserve_adam2) {
913 + char *firstfree_str = prom_getenv("firstfreeaddress");
914 + unsigned long firstfree = 0;
915 +
916 + if (firstfree_str)
917 + firstfree = simple_strtol(firstfree_str, NULL, 0);
918 +
919 + if (firstfree && firstfree < (unsigned long)&_ftext) {
920 + printk("Preserving ADAM2 memory.\n");
921 + } else if (firstfree) {
922 + printk("Can't preserve ADAM2 memory, "
923 + "firstfreeaddress = %08lx.\n", firstfree);
924 + preserve_adam2 = 0;
925 + } else {
926 + printk("Can't preserve ADAM2 memory, "
927 + "firstfreeaddress unknown!\n");
928 + preserve_adam2 = 0;
929 + }
930 + }
931 +
932 + if (!preserve_adam2) {
933 + for (i = 0; i < boot_mem_map.nr_map; i++) {
934 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
935 + continue;
936 +
937 + addr = boot_mem_map.map[i].addr;
938 + while (addr < boot_mem_map.map[i].addr
939 + + boot_mem_map.map[i].size) {
940 + ClearPageReserved(virt_to_page(__va(addr)));
941 + set_page_count(virt_to_page(__va(addr)), 1);
942 + free_page((unsigned long)__va(addr));
943 + addr += PAGE_SIZE;
944 + freed += PAGE_SIZE;
945 + }
946 + }
947 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
948 + }
949 + return freed >> PAGE_SHIFT;
950 +}
951 diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
952 --- linux.old/arch/mips/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
953 +++ linux.dev/arch/mips/ar7/misc.c 2005-11-10 01:12:43.946955500 +0100
954 @@ -0,0 +1,322 @@
955 +#include <asm/ar7/sangam.h>
956 +#include <asm/ar7/avalanche_misc.h>
957 +#include <linux/module.h>
958 +#include <linux/spinlock.h>
959 +
960 +#define TRUE 1
961 +
962 +static unsigned int avalanche_vbus_freq;
963 +
964 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
965 +
966 +/*****************************************************************************
967 + * Reset Control Module.
968 + *****************************************************************************/
969 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
970 + AVALANCHE_RESET_CTRL_T reset_ctrl)
971 +{
972 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
973 +
974 + if(module_reset_bit >= 32 && module_reset_bit < 64)
975 + return;
976 +
977 + if(module_reset_bit >= 64)
978 + {
979 + if(p_remote_vlynq_dev_reset_ctrl) {
980 + p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl);
981 + return;
982 + }
983 + else
984 + return;
985 + }
986 +
987 + if(reset_ctrl == OUT_OF_RESET)
988 + *reset_reg |= 1 << module_reset_bit;
989 + else
990 + *reset_reg &= ~(1 << module_reset_bit);
991 + return;
992 +}
993 +
994 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
995 +{
996 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
997 +
998 + return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
999 +}
1000 +
1001 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
1002 +{
1003 + volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
1004 + *sw_reset_reg = mode;
1005 +}
1006 +
1007 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
1008 +
1009 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
1010 +{
1011 + volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
1012 +
1013 + return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
1014 +}
1015 +
1016 +
1017 +/*****************************************************************************
1018 + * Power Control Module
1019 + *****************************************************************************/
1020 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
1021 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
1022 +
1023 +
1024 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
1025 +{
1026 + volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1027 +
1028 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
1029 + /* power down the module */
1030 + *power_reg |= (1 << module_power_bit);
1031 + else
1032 + /* power on the module */
1033 + *power_reg &= (~(1 << module_power_bit));
1034 +}
1035 +
1036 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
1037 +{
1038 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1039 +
1040 + return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
1041 +}
1042 +
1043 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
1044 +{
1045 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1046 +
1047 + *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
1048 + *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
1049 +}
1050 +
1051 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
1052 +{
1053 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1054 +
1055 + return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
1056 + >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
1057 +}
1058 +
1059 +/*****************************************************************************
1060 + * GPIO Control
1061 + *****************************************************************************/
1062 +
1063 +/****************************************************************************
1064 + * FUNCTION: avalanche_gpio_init
1065 + ***************************************************************************/
1066 +void avalanche_gpio_init(void)
1067 +{
1068 + spinlock_t closeLock;
1069 + unsigned int closeFlag;
1070 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1071 + spin_lock_irqsave(&closeLock, closeFlag);
1072 + *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
1073 + spin_unlock_irqrestore(&closeLock, closeFlag);
1074 +}
1075 +
1076 +/****************************************************************************
1077 + * FUNCTION: avalanche_gpio_ctrl
1078 + ***************************************************************************/
1079 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
1080 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
1081 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
1082 +{
1083 + spinlock_t closeLock;
1084 + unsigned int closeFlag;
1085 + volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
1086 +
1087 + if(gpio_pin >= 32)
1088 + return(-1);
1089 +
1090 + spin_lock_irqsave(&closeLock, closeFlag);
1091 +
1092 + if(pin_mode == GPIO_PIN)
1093 + {
1094 + *gpio_ctrl |= (1 << gpio_pin);
1095 +
1096 + gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
1097 +
1098 + if(pin_direction == GPIO_INPUT_PIN)
1099 + *gpio_ctrl |= (1 << gpio_pin);
1100 + else
1101 + *gpio_ctrl &= ~(1 << gpio_pin);
1102 + }
1103 + else /* FUNCTIONAL PIN */
1104 + {
1105 + *gpio_ctrl &= ~(1 << gpio_pin);
1106 + }
1107 +
1108 + spin_unlock_irqrestore(&closeLock, closeFlag);
1109 +
1110 + return (0);
1111 +}
1112 +
1113 +/****************************************************************************
1114 + * FUNCTION: avalanche_gpio_out
1115 + ***************************************************************************/
1116 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
1117 +{
1118 + spinlock_t closeLock;
1119 + unsigned int closeFlag;
1120 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1121 +
1122 + if(gpio_pin >= 32)
1123 + return(-1);
1124 +
1125 + spin_lock_irqsave(&closeLock, closeFlag);
1126 + if(value == TRUE)
1127 + *gpio_out |= 1 << gpio_pin;
1128 + else
1129 + *gpio_out &= ~(1 << gpio_pin);
1130 + spin_unlock_irqrestore(&closeLock, closeFlag);
1131 +
1132 + return(0);
1133 +}
1134 +
1135 +/****************************************************************************
1136 + * FUNCTION: avalanche_gpio_in
1137 + ***************************************************************************/
1138 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
1139 +{
1140 + spinlock_t closeLock;
1141 + unsigned int closeFlag;
1142 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1143 + int ret_val = 0;
1144 +
1145 + if(gpio_pin >= 32)
1146 + return(-1);
1147 +
1148 + spin_lock_irqsave(&closeLock, closeFlag);
1149 + ret_val = ((*gpio_in) & (1 << gpio_pin));
1150 + spin_unlock_irqrestore(&closeLock, closeFlag);
1151 +
1152 + return (ret_val);
1153 +}
1154 +
1155 +/****************************************************************************
1156 + * FUNCTION: avalanche_gpio_out_val
1157 + ***************************************************************************/
1158 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
1159 + unsigned int reg_index)
1160 +{
1161 + spinlock_t closeLock;
1162 + unsigned int closeFlag;
1163 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1164 +
1165 + if(reg_index > 0)
1166 + return(-1);
1167 +
1168 + spin_lock_irqsave(&closeLock, closeFlag);
1169 + *gpio_out &= ~out_mask;
1170 + *gpio_out |= out_val;
1171 + spin_unlock_irqrestore(&closeLock, closeFlag);
1172 +
1173 + return(0);
1174 +}
1175 +
1176 +/****************************************************************************
1177 + * FUNCTION: avalanche_gpio_in_value
1178 + ***************************************************************************/
1179 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
1180 +{
1181 + spinlock_t closeLock;
1182 + unsigned int closeFlag;
1183 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1184 +
1185 + if(reg_index > 0)
1186 + return(-1);
1187 +
1188 + spin_lock_irqsave(&closeLock, closeFlag);
1189 + *in_val = *gpio_in;
1190 + spin_unlock_irqrestore(&closeLock, closeFlag);
1191 +
1192 + return (0);
1193 +}
1194 +
1195 +/***********************************************************************
1196 + *
1197 + * Wakeup Control Module for TNETV1050 Communication Processor
1198 + *
1199 + ***********************************************************************/
1200 +
1201 +#define AVALANCHE_WAKEUP_POLARITY_BIT 16
1202 +
1203 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
1204 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
1205 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
1206 +{
1207 + volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
1208 +
1209 + /* enable/disable */
1210 + if (wakeup_ctrl == WAKEUP_ENABLED)
1211 + /* enable wakeup */
1212 + *wakeup_status_reg |= wakeup_int;
1213 + else
1214 + /* disable wakeup */
1215 + *wakeup_status_reg &= (~wakeup_int);
1216 +
1217 + /* set polarity */
1218 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
1219 + *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1220 + else
1221 + *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1222 +}
1223 +
1224 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
1225 +{
1226 + avalanche_vbus_freq = new_vbus_freq;
1227 +}
1228 +
1229 +unsigned int avalanche_get_vbus_freq()
1230 +{
1231 + return(avalanche_vbus_freq);
1232 +}
1233 +
1234 +unsigned int avalanche_get_chip_version_info()
1235 +{
1236 + return(*(volatile unsigned int*)AVALANCHE_CVR);
1237 +}
1238 +
1239 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
1240 +
1241 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
1242 +{
1243 + if(p_set_mdix_on_chip_fn)
1244 + return (p_set_mdix_on_chip_fn(base_addr, operation));
1245 + else
1246 + return(-1);
1247 +}
1248 +
1249 +unsigned int avalanche_is_mdix_on_chip(void)
1250 +{
1251 + return(p_set_mdix_on_chip_fn ? 1:0);
1252 +}
1253 +
1254 +EXPORT_SYMBOL(avalanche_reset_ctrl);
1255 +EXPORT_SYMBOL(avalanche_get_reset_status);
1256 +EXPORT_SYMBOL(avalanche_sys_reset);
1257 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
1258 +EXPORT_SYMBOL(avalanche_power_ctrl);
1259 +EXPORT_SYMBOL(avalanche_get_power_status);
1260 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
1261 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
1262 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
1263 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
1264 +
1265 +EXPORT_SYMBOL(avalanche_gpio_init);
1266 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
1267 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
1268 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
1269 +EXPORT_SYMBOL(avalanche_gpio_out_value);
1270 +EXPORT_SYMBOL(avalanche_gpio_in_value);
1271 +
1272 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
1273 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
1274 +
1275 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
1276 +
1277 diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
1278 --- linux.old/arch/mips/ar7/platform.h 1970-01-01 01:00:00.000000000 +0100
1279 +++ linux.dev/arch/mips/ar7/platform.h 2005-11-10 01:10:45.799571750 +0100
1280 @@ -0,0 +1,65 @@
1281 +#ifndef _PLATFORM_H_
1282 +#define _PLATFORM_H_
1283 +
1284 +#include <linux/config.h>
1285 +
1286 +
1287 +/* Important: The definition of ENV_SPACE_SIZE should match with that in
1288 + * PSPBoot. (/psp_boot/inc/psbl/env.h)
1289 + */
1290 +#ifdef CONFIG_MIPS_AVALANCHE_TICFG
1291 +#define ENV_SPACE_SIZE (10 * 1024)
1292 +#endif
1293 +
1294 +#ifdef CONFIG_MIPS_TNETV1050SDB
1295 +#define TNETV1050SDB
1296 +#define DUAL_FLASH
1297 +#endif
1298 +
1299 +#ifdef CONFIG_MIPS_AR7DB
1300 +#define TNETD73XX_BOARD
1301 +#define AR7DB
1302 +#endif
1303 +
1304 +#ifdef CONFIG_MIPS_AR7RD
1305 +#define TNETD73XX_BOARD
1306 +#define AR7RD
1307 +#endif
1308 +
1309 +#ifdef CONFIG_AR7WRD
1310 +#define TNETD73XX_BOARD
1311 +#define AR7WRD
1312 +#endif
1313 +
1314 +#ifdef CONFIG_MIPS_AR7VWI
1315 +#define TNETD73XX_BOARD
1316 +#define AR7VWi
1317 +#endif
1318 +
1319 +/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
1320 +#ifdef CONFIG_MIPS_AR7VW
1321 +#define TNETD73XX_BOARD
1322 +#define AR7WRD
1323 +#endif
1324 +
1325 +#ifdef CONFIG_MIPS_AR7WI
1326 +#define TNETD73XX_BOARD
1327 +#define AR7Wi
1328 +#endif
1329 +
1330 +#ifdef CONFIG_MIPS_AR7V
1331 +#define TNETD73XX_BOARD
1332 +#define AR7V
1333 +#endif
1334 +
1335 +#ifdef CONFIG_MIPS_AR7V
1336 +#define TNETD73XX_BOARD
1337 +#define AR7V
1338 +#endif
1339 +
1340 +#ifdef CONFIG_MIPS_WA1130
1341 +#define AVALANCHE
1342 +#define WLAN
1343 +#endif
1344 +
1345 +#endif
1346 diff -urN linux.old/arch/mips/ar7/promlib.c linux.dev/arch/mips/ar7/promlib.c
1347 --- linux.old/arch/mips/ar7/promlib.c 1970-01-01 01:00:00.000000000 +0100
1348 +++ linux.dev/arch/mips/ar7/promlib.c 2005-11-10 01:14:16.372731750 +0100
1349 @@ -0,0 +1,48 @@
1350 +/*
1351 + * Carsten Langgaard, carstenl@mips.com
1352 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1353 + *
1354 + * This program is free software; you can distribute it and/or modify it
1355 + * under the terms of the GNU General Public License (Version 2) as
1356 + * published by the Free Software Foundation.
1357 + *
1358 + * This program is distributed in the hope it will be useful, but WITHOUT
1359 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1360 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1361 + * for more details.
1362 + *
1363 + * You should have received a copy of the GNU General Public License along
1364 + * with this program; if not, write to the Free Software Foundation, Inc.,
1365 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1366 + *
1367 + * Putting things on the screen/serial line using Adam2 facilities.
1368 + */
1369 +
1370 +#include <linux/types.h>
1371 +#include <asm/addrspace.h>
1372 +
1373 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
1374 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR \
1375 + (AVALANCHE_YAMON_FUNCTION_BASE + 1 * 0x4)
1376 +#define AVALANCHE_YAMON_PROM_EXIT \
1377 + (AVALANCHE_YAMON_FUNCTION_BASE + 8 * 0x4)
1378 +
1379 +void prom_putchar(char c)
1380 +{
1381 + static char buf[1];
1382 + void (*prom_print_str)(unsigned int dummy, char *s, int len) =
1383 + (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR);
1384 +
1385 + buf[0] = c;
1386 + prom_print_str(1, buf, 1);
1387 + return;
1388 +}
1389 +
1390 +void adam2_exit(int retval)
1391 +{
1392 + void (*yamon_exit)(int retval) =
1393 + (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_EXIT);
1394 +
1395 + yamon_exit(retval);
1396 + return;
1397 +}
1398 diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
1399 --- linux.old/arch/mips/ar7/psp_env.c 1970-01-01 01:00:00.000000000 +0100
1400 +++ linux.dev/arch/mips/ar7/psp_env.c 2005-11-10 01:10:45.799571750 +0100
1401 @@ -0,0 +1,350 @@
1402 +#include <linux/config.h>
1403 +#include <linux/init.h>
1404 +#include <linux/string.h>
1405 +#include <linux/kernel.h>
1406 +#include <linux/module.h>
1407 +#include <asm/io.h>
1408 +
1409 +#include "platform.h"
1410 +
1411 +#define ENV_CELL_SIZE 16
1412 +
1413 +/* control field decode */
1414 +#define ENV_GARBAGE_BIT 0x01 /* Env is garbage if this bit is off */
1415 +#define ENV_DYNAMIC_BIT 0x02 /* Env is dynamic if this bit is off */
1416 +
1417 +#define ENV_CTRL_MASK 0x03
1418 +#define ENV_PREFINED (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
1419 +#define ENV_DYNAMIC (ENV_GARBAGE_BIT)
1420 +
1421 +struct env_variable {
1422 + unsigned char varNum;
1423 + unsigned char ctrl;
1424 + unsigned short chksum;
1425 + unsigned char numCells;
1426 + unsigned char data[ENV_CELL_SIZE - 5]; /* The data section starts
1427 + * here, continues for
1428 + * numCells.
1429 + */
1430 +};
1431 +
1432 +extern unsigned int max_env_entry;
1433 +
1434 +/* Internal macros */
1435 +#define get_next_block(var) ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
1436 +
1437 +typedef enum ENV_VARS {
1438 + env_vars_start = 0,
1439 + CPUFREQ,
1440 + MEMSZ,
1441 + FLASHSZ,
1442 + MODETTY0,
1443 + MODETTY1,
1444 + PROMPT,
1445 + BOOTCFG,
1446 + HWA_0,
1447 +#if !defined (AVALANCHE) || defined(TNETC401B)
1448 + HWA_1,
1449 +#endif
1450 +#if !defined(TNETV1020_BOARD)
1451 + HWA_RNDIS,
1452 +#endif
1453 +#if defined (TNETD73XX_BOARD)
1454 + HWA_3,
1455 +#endif
1456 + IPA,
1457 + IPA_SVR,
1458 + BLINE_MAC0,
1459 +#if !defined (AVALANCHE) || defined(TNETC401B)
1460 + BLINE_MAC1,
1461 +#endif
1462 +#if !defined(TNETV1020_BOARD)
1463 + BLINE_RNDIS,
1464 +#endif
1465 +#if defined (TNETD73XX_BOARD)
1466 + BLINE_ATM,
1467 +#endif
1468 +#if !defined(TNETV1020_BOARD)
1469 + USB_PID,
1470 + USB_VID,
1471 + USB_EPPOLLI,
1472 +#endif
1473 + IPA_GATEWAY,
1474 + SUBNET_MASK,
1475 +#if defined (TNETV1050_BOARD)
1476 + BLINE_ESWITCH,
1477 +#endif
1478 +#if !defined(TNETV1020_BOARD)
1479 + USB_SERIAL,
1480 + HWA_HRNDIS, /* Host (PC) side RNDIS address */
1481 +#endif
1482 + REMOTE_USER,
1483 + REMOTE_PASS,
1484 + REMOTE_DIR,
1485 + SYSFREQ,
1486 + LINK_TIMEOUT,
1487 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1488 + MAC_PORT,
1489 +#endif
1490 + PATH,
1491 + HOSTNAME,
1492 +#ifdef WLAN
1493 + HW_REV_MAJOR,
1494 + HW_REV_MINOR,
1495 + HW_PATCH,
1496 + SW_PATCH,
1497 + SERIAL_NUMBER,
1498 +#endif
1499 + TFTPCFG,
1500 +#if defined (TNETV1050_BOARD)
1501 + HWA_ESWITCH,
1502 +#endif
1503 + /*
1504 + * Add new env variables here.
1505 + * NOTE: New environment variables should always be placed at the end, ie
1506 + * just before env_vars_end.
1507 + */
1508 +
1509 + env_vars_end
1510 +} ENV_VARS;
1511 +
1512 +
1513 +struct env_description {
1514 + ENV_VARS idx;
1515 + char *nm;
1516 + char *alias;
1517 +};
1518 +
1519 +#define ENVSTR(x) #x
1520 +#define _ENV_ENTRY(x) {.idx = x, .nm = ENVSTR(x), .alias = NULL}
1521 +
1522 +struct env_description env_ns[] = {
1523 + _ENV_ENTRY(env_vars_start), /* start. */
1524 + _ENV_ENTRY(CPUFREQ),
1525 + _ENV_ENTRY(MEMSZ),
1526 + _ENV_ENTRY(FLASHSZ),
1527 + _ENV_ENTRY(MODETTY0),
1528 + _ENV_ENTRY(MODETTY1),
1529 + _ENV_ENTRY(PROMPT),
1530 + _ENV_ENTRY(BOOTCFG),
1531 + _ENV_ENTRY(HWA_0),
1532 +#if !defined (AVALANCHE) || defined(TNETC401B)
1533 + _ENV_ENTRY(HWA_1),
1534 +#endif
1535 +#if !defined(TNETV1020_BOARD)
1536 + _ENV_ENTRY(HWA_RNDIS),
1537 +#endif
1538 +#if defined (TNETD73XX_BOARD)
1539 + _ENV_ENTRY(HWA_3),
1540 +#endif
1541 + _ENV_ENTRY(IPA),
1542 + _ENV_ENTRY(IPA_SVR),
1543 + _ENV_ENTRY(IPA_GATEWAY),
1544 + _ENV_ENTRY(SUBNET_MASK),
1545 + _ENV_ENTRY(BLINE_MAC0),
1546 +#if !defined (AVALANCHE) || defined(TNETC401B)
1547 + _ENV_ENTRY(BLINE_MAC1),
1548 +#endif
1549 +#if !defined(TNETV1020_BOARD)
1550 + _ENV_ENTRY(BLINE_RNDIS),
1551 +#endif
1552 +#if defined (TNETD73XX_BOARD)
1553 + _ENV_ENTRY(BLINE_ATM),
1554 +#endif
1555 +#if !defined(TNETV1020_BOARD)
1556 + _ENV_ENTRY(USB_PID),
1557 + _ENV_ENTRY(USB_VID),
1558 + _ENV_ENTRY(USB_EPPOLLI),
1559 +#endif
1560 +#if defined (TNETV1050_BOARD)
1561 + _ENV_ENTRY(BLINE_ESWITCH),
1562 +#endif
1563 +#if !defined(TNETV1020_BOARD)
1564 + _ENV_ENTRY(USB_SERIAL),
1565 + _ENV_ENTRY(HWA_HRNDIS),
1566 +#endif
1567 + _ENV_ENTRY(REMOTE_USER),
1568 + _ENV_ENTRY(REMOTE_PASS),
1569 + _ENV_ENTRY(REMOTE_DIR),
1570 + _ENV_ENTRY(SYSFREQ),
1571 + _ENV_ENTRY(LINK_TIMEOUT),
1572 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1573 + _ENV_ENTRY(MAC_PORT),
1574 +#endif
1575 + _ENV_ENTRY(PATH),
1576 + _ENV_ENTRY(HOSTNAME),
1577 +#ifdef WLAN
1578 + _ENV_ENTRY(HW_REV_MAJOR),
1579 + _ENV_ENTRY(HW_REV_MINOR),
1580 + _ENV_ENTRY(HW_PATCH),
1581 + _ENV_ENTRY(SW_PATCH),
1582 + _ENV_ENTRY(SERIAL_NUMBER),
1583 +#endif
1584 + _ENV_ENTRY(TFTPCFG),
1585 +#if defined (TNETV1050_BOARD)
1586 + _ENV_ENTRY(HWA_ESWITCH),
1587 +#endif
1588 + /*
1589 + * Add new entries below this.
1590 + */
1591 + /* Adam2 environment name alias. */
1592 + { .idx = IPA, .nm = "my_ipaddress" },
1593 + { .idx = CPUFREQ, .nm = "cpufrequency" },
1594 + { .idx = SYSFREQ, .nm = "sysfrequency" },
1595 + { .idx = HWA_0, .nm = "maca" },
1596 +#ifndef AVALANCHE
1597 + { .idx = HWA_1, .nm = "macb" },
1598 +#endif
1599 + { .idx = MODETTY0, .nm = "modetty0" },
1600 + { .idx = MODETTY1, .nm = "modetty1" },
1601 + { .idx = MEMSZ, .nm = "memsize" },
1602 +
1603 + _ENV_ENTRY(env_vars_end) /* delimiter. */
1604 +};
1605 +
1606 +static inline int var_to_idx(const char* var)
1607 +{
1608 + int ii;
1609 +
1610 + /* go over the list of pre-defined environment variables */
1611 + for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
1612 + /* check if the env variable is listed */
1613 + if (strcmp(env_ns[ii].nm, var) == 0) {
1614 + return env_ns[ii].idx;
1615 + }
1616 +
1617 + /* if an alias is present, check if the alias matches
1618 + * the description
1619 + */
1620 + if (env_ns[ii].alias != NULL) {
1621 + if (strcmp(env_ns[ii].alias, var) == 0) {
1622 + return env_ns[ii].idx;
1623 + }
1624 + }
1625 + }
1626 + return 0;
1627 +}
1628 +
1629 +extern int *_prom_envp;
1630 +
1631 +/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
1632 + * the next read some seconds later is ok. It looks like something is hidding or
1633 + * overlay the flash address at 0xb0000000. Is this possible?
1634 + *
1635 + * The readb() and while() usage below is a attempt of a workarround - with limited success.
1636 + */
1637 +
1638 +static inline struct env_variable* get_var_by_number(int index)
1639 +{
1640 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1641 + volatile unsigned char nr;
1642 + int i;
1643 +
1644 + env_var++; /* skip signature */
1645 +
1646 + i = 0;
1647 + nr = readb(&(env_var->varNum));
1648 +
1649 + while (i < max_env_entry && nr != 0xFF) {
1650 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
1651 + if (nr == index) {
1652 + return env_var;
1653 + }
1654 + }
1655 + i++;
1656 + env_var = get_next_block(env_var);
1657 + nr = readb(&(env_var->varNum));
1658 + }
1659 +
1660 + return NULL;
1661 +}
1662 +
1663 +static inline struct env_variable* get_var_by_name(char *var)
1664 +{
1665 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1666 + volatile unsigned char nr;
1667 + int i;
1668 +
1669 + env_var++; /* skip signature */
1670 +
1671 + nr = readb(&(env_var->varNum));
1672 + i = 0;
1673 +
1674 + while (i < max_env_entry && nr != 0xFF) {
1675 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1676 + if (strcmp(var, env_var->data) == 0)
1677 + return env_var;
1678 + }
1679 + i++;
1680 + env_var = get_next_block(env_var);
1681 + nr = readb(&(env_var->varNum));
1682 + }
1683 + return NULL;
1684 +}
1685 +
1686 +static inline struct env_variable* get_var(char *var)
1687 +{
1688 + int index = var_to_idx(var);
1689 +
1690 + if (index)
1691 + return get_var_by_number(index);
1692 + else
1693 + return get_var_by_name(var);
1694 +
1695 + return NULL;
1696 +}
1697 +
1698 +static inline char *get_value(struct env_variable* env_var)
1699 +{
1700 + unsigned char *name;
1701 + unsigned char *value;
1702 + unsigned short chksum;
1703 + int i;
1704 +
1705 + chksum = env_var->varNum + env_var->ctrl + env_var->numCells;
1706 +
1707 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1708 + name = env_var->data;
1709 + value = env_var->data + strlen(name) + 1;
1710 +
1711 + for(i = 0; i < strlen(name); i++)
1712 + chksum += name[i];
1713 + } else
1714 + value = env_var->data;
1715 +
1716 + for (i = 0; i < strlen(value); i++)
1717 + chksum += value[i];
1718 +
1719 + chksum += env_var->chksum;
1720 + chksum = ~(chksum);
1721 +
1722 + if(chksum != 0) {
1723 + return NULL;
1724 + }
1725 +
1726 + return value;
1727 +}
1728 +
1729 +struct psbl_rec {
1730 + unsigned int psbl_size;
1731 + unsigned int env_base;
1732 + unsigned int env_size;
1733 + unsigned int ffs_base;
1734 + unsigned int ffs_size;
1735 +};
1736 +
1737 +char *prom_psp_getenv(char *envname)
1738 +{
1739 + struct env_variable* env_var;
1740 + char *value;
1741 +
1742 + if (strcmp("bootloader", envname) == 0)
1743 + return "PSPBoot";
1744 +
1745 + if (!(env_var = get_var(envname)))
1746 + return NULL;
1747 +
1748 + value = get_value(env_var);
1749 +
1750 + return value;
1751 +}
1752 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
1753 --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
1754 +++ linux.dev/arch/mips/ar7/reset.c 2005-11-10 01:14:16.372731750 +0100
1755 @@ -0,0 +1,98 @@
1756 +/*
1757 + * Carsten Langgaard, carstenl@mips.com
1758 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1759 + *
1760 + * ########################################################################
1761 + *
1762 + * This program is free software; you can distribute it and/or modify it
1763 + * under the terms of the GNU General Public License (Version 2) as
1764 + * published by the Free Software Foundation.
1765 + *
1766 + * This program is distributed in the hope it will be useful, but WITHOUT
1767 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1768 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1769 + * for more details.
1770 + *
1771 + * You should have received a copy of the GNU General Public License along
1772 + * with this program; if not, write to the Free Software Foundation, Inc.,
1773 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1774 + *
1775 + * ########################################################################
1776 + *
1777 + * Reset the AR7 boards.
1778 + *
1779 + */
1780 +
1781 +#include <linux/init.h>
1782 +#include <linux/kernel.h>
1783 +#include <linux/string.h>
1784 +#include <linux/types.h>
1785 +
1786 +#include <asm/mipsregs.h>
1787 +#include <asm/reboot.h>
1788 +#include <asm/addrspace.h>
1789 +
1790 +int preserve_adam2 = 1;
1791 +
1792 +extern void adam2_exit(int retval);
1793 +
1794 +static void ar7_machine_restart(char *command);
1795 +static void ar7_machine_halt(void);
1796 +static void ar7_machine_power_off(void);
1797 +
1798 +static void ar7_machine_restart(char *command)
1799 +{
1800 + volatile uint32_t *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
1801 +
1802 + *softres_reg = 1;
1803 +}
1804 +
1805 +static void ar7_machine_halt(void)
1806 +{
1807 +
1808 + if (preserve_adam2) {
1809 + set_c0_status(ST0_BEV);
1810 + adam2_exit(0);
1811 + } else {
1812 + /* I'd like to have Alt-SysRq-b work in this state.
1813 + * What's missing here? The timer interrupt is still running.
1814 + * Why doesn't the UART work anymore? */
1815 + while(1) {
1816 + __asm__(".set\tmips3\n\t"
1817 + "wait\n\t"
1818 + ".set\tmips0");
1819 + }
1820 + }
1821 +}
1822 +
1823 +static void ar7_machine_power_off(void)
1824 +{
1825 + volatile uint32_t *power_reg = (void *)(KSEG1ADDR(0x08610A00));
1826 + uint32_t power_state = *power_reg;
1827 +
1828 + /* add something to turn LEDs off? */
1829 +
1830 + power_state &= ~(3 << 30);
1831 + power_state |= (3 << 30); /* power down */
1832 + *power_reg = power_state;
1833 +
1834 + printk("after power down?\n");
1835 +}
1836 +
1837 +void ar7_reboot_setup(void)
1838 +{
1839 + _machine_restart = ar7_machine_restart;
1840 + _machine_halt = ar7_machine_halt;
1841 + _machine_power_off = ar7_machine_power_off;
1842 +}
1843 +
1844 +static int __init ar7_do_preserve_adam2(char *s)
1845 +{
1846 + if (!strcmp(s, "no") || !strcmp(s, "0"))
1847 + preserve_adam2 = 0;
1848 + else
1849 + preserve_adam2 = 1;
1850 + return 1;
1851 +}
1852 +
1853 +__setup("adam2=", ar7_do_preserve_adam2);
1854 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
1855 --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
1856 +++ linux.dev/arch/mips/ar7/setup.c 2005-11-10 01:12:43.946955500 +0100
1857 @@ -0,0 +1,143 @@
1858 +/*
1859 + * Carsten Langgaard, carstenl@mips.com
1860 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
1861 + *
1862 + * This program is free software; you can distribute it and/or modify it
1863 + * under the terms of the GNU General Public License (Version 2) as
1864 + * published by the Free Software Foundation.
1865 + *
1866 + * This program is distributed in the hope it will be useful, but WITHOUT
1867 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1868 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1869 + * for more details.
1870 + *
1871 + * You should have received a copy of the GNU General Public License along
1872 + * with this program; if not, write to the Free Software Foundation, Inc.,
1873 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1874 + */
1875 +
1876 +#include <linux/config.h>
1877 +#include <linux/init.h>
1878 +#include <linux/string.h>
1879 +#include <linux/irq.h>
1880 +
1881 +#include <asm/processor.h>
1882 +#include <asm/irq.h>
1883 +#include <asm/irq_cpu.h>
1884 +#include <asm/time.h>
1885 +#include <asm/mipsregs.h>
1886 +#include <asm/mips-boards/prom.h>
1887 +
1888 +#ifdef CONFIG_KGDB
1889 +extern void rs_kgdb_hook(int);
1890 +extern void breakpoint(void);
1891 +int remote_debug = 0;
1892 +#endif
1893 +
1894 +extern void ar7_reboot_setup(void);
1895 +extern void ar7_irq_init(int);
1896 +extern asmlinkage void ar7IRQ(void);
1897 +
1898 +void ar7_time_init(void)
1899 +{
1900 + /* XXX runtime */
1901 + mips_hpt_frequency = CONFIG_AR7_CPU * 500000;
1902 +}
1903 +
1904 +void ar7_timer_setup(struct irqaction *irq)
1905 +{
1906 + setup_irq(7, irq);
1907 + set_c0_status(IE_IRQ5);
1908 +}
1909 +
1910 +void __init init_IRQ(void)
1911 +{
1912 + init_generic_irq();
1913 + mips_cpu_irq_init(0);
1914 + ar7_irq_init(8);
1915 +
1916 + /* Now safe to set the exception vector. */
1917 + set_except_vector(0, ar7IRQ);
1918 +
1919 +#ifdef CONFIG_KGDB
1920 + if (remote_debug)
1921 + {
1922 + set_debug_traps();
1923 + breakpoint();
1924 + }
1925 +#endif
1926 +}
1927 +
1928 +const char *get_system_type(void)
1929 +{
1930 + return "Texas Instruments AR7";
1931 +}
1932 +
1933 +void __init ar7_setup(void)
1934 +{
1935 +#ifdef CONFIG_KGDB
1936 + int rs_putDebugChar(char);
1937 + char rs_getDebugChar(void);
1938 + extern int (*generic_putDebugChar)(char);
1939 + extern char (*generic_getDebugChar)(void);
1940 +#endif
1941 + char *argptr;
1942 +#ifdef CONFIG_SERIAL_CONSOLE
1943 + argptr = prom_getcmdline();
1944 + if ((argptr = strstr(argptr, "console=")) == NULL) {
1945 + char console[20];
1946 + char *s;
1947 + int i = 0;
1948 +
1949 + s = prom_getenv("modetty0");
1950 + strcpy(console, "38400");
1951 +
1952 + if (s != NULL) {
1953 + while (s[i] >= '0' && s[i] <= '9')
1954 + i++;
1955 +
1956 + if (i > 0) {
1957 + strncpy(console, s, i);
1958 + console[i] = 0;
1959 + }
1960 + }
1961 +
1962 + argptr = prom_getcmdline();
1963 + strcat(argptr, " console=ttyS0,");
1964 + strcat(argptr, console);
1965 + }
1966 +#endif
1967 +
1968 +#ifdef CONFIG_KGDB
1969 + argptr = prom_getcmdline();
1970 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1971 + int line;
1972 + argptr += strlen("kgdb=ttyS");
1973 + if (*argptr != '0' && *argptr != '1')
1974 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
1975 + "falling back to /dev/ttyS1\n", *argptr);
1976 + line = *argptr == '0' ? 0 : 1;
1977 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1978 + line ? 1 : 0);
1979 +
1980 + rs_kgdb_hook(line);
1981 + generic_putDebugChar = rs_putDebugChar;
1982 + generic_getDebugChar = rs_getDebugChar;
1983 +
1984 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1985 + "please connect your debugger\n", line ? 1 : 0);
1986 +
1987 + remote_debug = 1;
1988 + /* Breakpoints are in init_IRQ() */
1989 + }
1990 +#endif
1991 +
1992 + argptr = prom_getcmdline();
1993 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
1994 + cpu_data[0].options &= ~MIPS_CPU_FPU;
1995 +
1996 + ar7_reboot_setup();
1997 +
1998 + board_time_init = ar7_time_init;
1999 + board_timer_setup = ar7_timer_setup;
2000 +}
2001 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
2002 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
2003 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-11-10 01:12:43.946955500 +0100
2004 @@ -0,0 +1,921 @@
2005 +/******************************************************************************
2006 + * FILE PURPOSE: TNETD73xx Misc modules API Source
2007 + ******************************************************************************
2008 + * FILE NAME: tnetd73xx_misc.c
2009 + *
2010 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
2011 + * FSER Modules API
2012 + * As per TNETD73xx specifications
2013 + *
2014 + * REVISION HISTORY:
2015 + * 27 Nov 02 - Sharath Kumar PSP TII
2016 + * 14 Feb 03 - Anant Gole PSP TII
2017 + *
2018 + * (C) Copyright 2002, Texas Instruments, Inc
2019 + *******************************************************************************/
2020 +
2021 +#include <linux/types.h>
2022 +#include <asm/ar7/tnetd73xx.h>
2023 +#include <asm/ar7/tnetd73xx_misc.h>
2024 +
2025 +/* TNETD73XX Revision */
2026 +u32 tnetd73xx_get_revision(void)
2027 +{
2028 + /* Read Chip revision register - This register is from GPIO module */
2029 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2030 +}
2031 +
2032 +/*****************************************************************************
2033 + * Reset Control Module
2034 + *****************************************************************************/
2035 +
2036 +
2037 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2038 +{
2039 + u32 reset_status;
2040 +
2041 + /* read current reset register */
2042 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2043 +
2044 + if (reset_ctrl == OUT_OF_RESET)
2045 + {
2046 + /* bring module out of reset */
2047 + reset_status |= (1 << reset_module);
2048 + }
2049 + else
2050 + {
2051 + /* put module in reset */
2052 + reset_status &= (~(1 << reset_module));
2053 + }
2054 +
2055 + /* write to the reset register */
2056 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2057 +}
2058 +
2059 +
2060 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2061 +{
2062 + u32 reset_status;
2063 +
2064 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2065 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2066 +}
2067 +
2068 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2069 +{
2070 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2071 +}
2072 +
2073 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2074 +
2075 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2076 +{
2077 + u32 sys_reset_status;
2078 +
2079 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2080 +
2081 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2082 +}
2083 +
2084 +
2085 +/*****************************************************************************
2086 + * Power Control Module
2087 + *****************************************************************************/
2088 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2089 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2090 +
2091 +
2092 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2093 +{
2094 + u32 power_status;
2095 +
2096 + /* read current power down control register */
2097 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2098 +
2099 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2100 + {
2101 + /* power down the module */
2102 + power_status |= (1 << power_module);
2103 + }
2104 + else
2105 + {
2106 + /* power on the module */
2107 + power_status &= (~(1 << power_module));
2108 + }
2109 +
2110 + /* write to the reset register */
2111 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2112 +}
2113 +
2114 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2115 +{
2116 + u32 power_status;
2117 +
2118 + /* read current power down control register */
2119 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2120 +
2121 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2122 +}
2123 +
2124 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2125 +{
2126 + u32 power_status;
2127 +
2128 + /* read current power down control register */
2129 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2130 +
2131 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2132 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2133 +
2134 + /* write to power down control register */
2135 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2136 +}
2137 +
2138 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2139 +{
2140 + u32 power_status;
2141 +
2142 + /* read current power down control register */
2143 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2144 +
2145 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2146 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2147 +
2148 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2149 +}
2150 +
2151 +
2152 +/*****************************************************************************
2153 + * Wakeup Control
2154 + *****************************************************************************/
2155 +
2156 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2157 +
2158 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2159 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2160 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2161 +{
2162 + u32 wakeup_status;
2163 +
2164 + /* read the wakeup control register */
2165 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2166 +
2167 + /* enable/disable */
2168 + if (wakeup_ctrl == WAKEUP_ENABLED)
2169 + {
2170 + /* enable wakeup */
2171 + wakeup_status |= wakeup_int;
2172 + }
2173 + else
2174 + {
2175 + /* disable wakeup */
2176 + wakeup_status &= (~wakeup_int);
2177 + }
2178 +
2179 + /* set polarity */
2180 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2181 + {
2182 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2183 + }
2184 + else
2185 + {
2186 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2187 + }
2188 +
2189 + /* write the wakeup control register */
2190 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2191 +}
2192 +
2193 +
2194 +/*****************************************************************************
2195 + * FSER Control
2196 + *****************************************************************************/
2197 +
2198 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2199 +{
2200 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2201 +}
2202 +
2203 +/*****************************************************************************
2204 + * Clock Control
2205 + *****************************************************************************/
2206 +
2207 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2208 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2209 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2210 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2211 +
2212 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2213 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2214 +
2215 +#define CLKC_PRE_DIVIDER 0x0000001F
2216 +#define CLKC_POST_DIVIDER 0x001F0000
2217 +
2218 +#define CLKC_PLL_STATUS 0x1
2219 +#define CLKC_PLL_FACTOR 0x0000F000
2220 +
2221 +#define BOOTCR_PLL_BYPASS (1 << 5)
2222 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2223 +
2224 +#define MIPS_PLL_SELECT 0x00030000
2225 +#define SYSTEM_PLL_SELECT 0x0000C000
2226 +#define USB_PLL_SELECT 0x000C0000
2227 +#define ADSLSS_PLL_SELECT 0x00C00000
2228 +
2229 +#define MIPS_AFECLKI_SELECT 0x00000000
2230 +#define MIPS_REFCLKI_SELECT 0x00010000
2231 +#define MIPS_XTAL3IN_SELECT 0x00020000
2232 +
2233 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2234 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2235 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2236 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2237 +
2238 +#define USB_SYSPLL_SELECT 0x00000000
2239 +#define USB_REFCLKI_SELECT 0x00040000
2240 +#define USB_XTAL3IN_SELECT 0x00080000
2241 +#define USB_MIPSPLL_SELECT 0x000C0000
2242 +
2243 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2244 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2245 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2246 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2247 +
2248 +#define SYS_MAX CLK_MHZ(150)
2249 +#define SYS_MIN CLK_MHZ(1)
2250 +
2251 +#define MIPS_SYNC_MAX SYS_MAX
2252 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2253 +#define MIPS_MIN CLK_MHZ(1)
2254 +
2255 +#define USB_MAX CLK_MHZ(100)
2256 +#define USB_MIN CLK_MHZ(1)
2257 +
2258 +#define ADSL_MAX CLK_MHZ(180)
2259 +#define ADSL_MIN CLK_MHZ(1)
2260 +
2261 +#define PLL_MUL_MAXFACTOR 15
2262 +#define MAX_DIV_VALUE 32
2263 +#define MIN_DIV_VALUE 1
2264 +
2265 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2266 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2267 +
2268 +#define DIVIDER_LOCK_TIME 10100
2269 +#define PLL_LOCK_TIME 10100 * 75
2270 +
2271 +
2272 +
2273 + /****************************************************************************
2274 + * DATA PURPOSE: PRIVATE Variables
2275 + **************************************************************************/
2276 + static u32 *clk_src[4];
2277 + static u32 mips_pll_out;
2278 + static u32 sys_pll_out;
2279 + static u32 afeclk_inp;
2280 + static u32 refclk_inp;
2281 + static u32 xtal_inp;
2282 + static u32 present_min;
2283 + static u32 present_max;
2284 +
2285 + /* Forward References */
2286 + static u32 find_gcd(u32 min, u32 max);
2287 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2288 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2289 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2290 + static void find_approx(u32 *,u32 *,u32);
2291 +
2292 + /****************************************************************************
2293 + * FUNCTION: tnetd73xx_clkc_init
2294 + ****************************************************************************
2295 + * Description: The routine initializes the internal variables depending on
2296 + * on the sources selected for different clocks.
2297 + ***************************************************************************/
2298 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2299 +{
2300 +
2301 + u32 choice;
2302 +
2303 + afeclk_inp = afeclk;
2304 + refclk_inp = refclk;
2305 + xtal_inp = xtal3in;
2306 +
2307 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2308 + switch(choice)
2309 + {
2310 + case MIPS_AFECLKI_SELECT:
2311 + clk_src[CLKC_MIPS] = &afeclk_inp;
2312 + break;
2313 +
2314 + case MIPS_REFCLKI_SELECT:
2315 + clk_src[CLKC_MIPS] = &refclk_inp;
2316 + break;
2317 +
2318 + case MIPS_XTAL3IN_SELECT:
2319 + clk_src[CLKC_MIPS] = &xtal_inp;
2320 + break;
2321 +
2322 + default :
2323 + clk_src[CLKC_MIPS] = 0;
2324 +
2325 + }
2326 +
2327 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2328 + switch(choice)
2329 + {
2330 + case SYSTEM_AFECLKI_SELECT:
2331 + clk_src[CLKC_SYS] = &afeclk_inp;
2332 + break;
2333 +
2334 + case SYSTEM_REFCLKI_SELECT:
2335 + clk_src[CLKC_SYS] = &refclk_inp;
2336 + break;
2337 +
2338 + case SYSTEM_XTAL3IN_SELECT:
2339 + clk_src[CLKC_SYS] = &xtal_inp;
2340 + break;
2341 +
2342 + case SYSTEM_MIPSPLL_SELECT:
2343 + clk_src[CLKC_SYS] = &mips_pll_out;
2344 + break;
2345 +
2346 + default :
2347 + clk_src[CLKC_SYS] = 0;
2348 +
2349 + }
2350 +
2351 +
2352 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2353 + switch(choice)
2354 + {
2355 + case ADSLSS_AFECLKI_SELECT:
2356 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2357 + break;
2358 +
2359 + case ADSLSS_REFCLKI_SELECT:
2360 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2361 + break;
2362 +
2363 + case ADSLSS_XTAL3IN_SELECT:
2364 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2365 + break;
2366 +
2367 + case ADSLSS_MIPSPLL_SELECT:
2368 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2369 + break;
2370 +
2371 + default :
2372 + clk_src[CLKC_ADSLSS] = 0;
2373 +
2374 + }
2375 +
2376 +
2377 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2378 + switch(choice)
2379 + {
2380 + case USB_SYSPLL_SELECT:
2381 + clk_src[CLKC_USB] = &sys_pll_out ;
2382 + break;
2383 +
2384 + case USB_REFCLKI_SELECT:
2385 + clk_src[CLKC_USB] = &refclk_inp;
2386 + break;
2387 +
2388 + case USB_XTAL3IN_SELECT:
2389 + clk_src[CLKC_USB] = &xtal_inp;
2390 + break;
2391 +
2392 + case USB_MIPSPLL_SELECT:
2393 + clk_src[CLKC_USB] = &mips_pll_out;
2394 + break;
2395 +
2396 + default :
2397 + clk_src[CLKC_USB] = 0;
2398 +
2399 + }
2400 +}
2401 +
2402 +
2403 +
2404 +/****************************************************************************
2405 + * FUNCTION: tnetd73xx_clkc_set_freq
2406 + ****************************************************************************
2407 + * Description: The above routine is called to set the output_frequency of the
2408 + * selected clock(using clk_id) to the required value given
2409 + * by the variable output_freq.
2410 + ***************************************************************************/
2411 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2412 +(
2413 + TNETD73XX_CLKC_ID_T clk_id,
2414 + u32 output_freq
2415 + )
2416 +{
2417 + u32 base_freq;
2418 + u32 multiplier;
2419 + u32 divider;
2420 + u32 min_prediv;
2421 + u32 max_prediv;
2422 + u32 prediv;
2423 + u32 postdiv;
2424 + u32 temp;
2425 +
2426 + /* check if PLLs are bypassed*/
2427 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2428 + {
2429 + return TNETD73XX_ERR_ERROR;
2430 + }
2431 +
2432 + /*check if the requested output_frequency is in valid range*/
2433 + switch( clk_id )
2434 + {
2435 + case CLKC_SYS:
2436 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2437 + {
2438 + return TNETD73XX_ERR_ERROR;
2439 + }
2440 + present_min = SYS_MIN;
2441 + present_max = SYS_MAX;
2442 + break;
2443 +
2444 + case CLKC_MIPS:
2445 + if((output_freq < MIPS_MIN) ||
2446 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2447 + {
2448 + return TNETD73XX_ERR_ERROR;
2449 + }
2450 + present_min = MIPS_MIN;
2451 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2452 + break;
2453 +
2454 + case CLKC_USB:
2455 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2456 + {
2457 + return TNETD73XX_ERR_ERROR;
2458 + }
2459 + present_min = USB_MIN;
2460 + present_max = USB_MAX;
2461 + break;
2462 +
2463 + case CLKC_ADSLSS:
2464 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2465 + {
2466 + return TNETD73XX_ERR_ERROR;
2467 + }
2468 + present_min = ADSL_MIN;
2469 + present_max = ADSL_MAX;
2470 + break;
2471 + }
2472 +
2473 +
2474 + base_freq = get_base_frequency(clk_id);
2475 +
2476 +
2477 + /* check for minimum base frequency value */
2478 + if( base_freq < MIN_PLL_INP_FREQ)
2479 + {
2480 + return TNETD73XX_ERR_ERROR;
2481 + }
2482 +
2483 + get_val(output_freq, base_freq, &multiplier, &divider);
2484 +
2485 + /* check multiplier range */
2486 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2487 + {
2488 + return TNETD73XX_ERR_ERROR;
2489 + }
2490 +
2491 + /* check divider value */
2492 + if( divider == 0 )
2493 + {
2494 + return TNETD73XX_ERR_ERROR;
2495 + }
2496 +
2497 + /*compute minimum and maximum predivider values */
2498 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2499 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2500 +
2501 + /*adjust the value of divider so that it not less than minimum predivider value*/
2502 + if (divider < min_prediv)
2503 + {
2504 + temp = CEIL(min_prediv, divider);
2505 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2506 + {
2507 + return TNETD73XX_ERR_ERROR ;
2508 + }
2509 + else
2510 + {
2511 + multiplier = temp * multiplier;
2512 + divider = min_prediv;
2513 + }
2514 +
2515 + }
2516 +
2517 + /* compute predivider and postdivider values */
2518 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2519 + postdiv = CEIL(divider,prediv);
2520 +
2521 + /*return fail if postdivider value falls out of range */
2522 + if(postdiv > MAX_DIV_VALUE)
2523 + {
2524 + return TNETD73XX_ERR_ERROR;
2525 + }
2526 +
2527 +
2528 + /*write predivider and postdivider values*/
2529 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2530 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2531 +
2532 + /*wait for divider output to stabilise*/
2533 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2534 +
2535 + /*write to PLL clock register*/
2536 +
2537 + if(clk_id == CLKC_SYS)
2538 + {
2539 + /* but before writing put DRAM to hold mode */
2540 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2541 + }
2542 + /*Bring PLL into div mode */
2543 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2544 +
2545 + /*compute the word to be written to PLLCR
2546 + *corresponding to multiplier value
2547 + */
2548 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2549 +
2550 + /* wait till PLL enters div mode */
2551 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2552 + /*nothing*/;
2553 +
2554 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2555 +
2556 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2557 + /*nothing*/;
2558 +
2559 +
2560 + /*wait for External pll to lock*/
2561 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2562 +
2563 + if(clk_id == CLKC_SYS)
2564 + {
2565 + /* Bring DRAM out of hold */
2566 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2567 + }
2568 +
2569 + return TNETD73XX_ERR_OK ;
2570 +}
2571 +
2572 +/****************************************************************************
2573 + * FUNCTION: tnetd73xx_clkc_get_freq
2574 + ****************************************************************************
2575 + * Description: The above routine is called to get the output_frequency of the
2576 + * selected clock( clk_id)
2577 + ***************************************************************************/
2578 +u32 tnetd73xx_clkc_get_freq
2579 +(
2580 + TNETD73XX_CLKC_ID_T clk_id
2581 + )
2582 +{
2583 +
2584 + u32 clk_ctrl_register;
2585 + u32 clk_pll_setting;
2586 + u32 clk_predivider;
2587 + u32 clk_postdivider;
2588 + u16 pll_factor;
2589 + u32 base_freq;
2590 + u32 divider;
2591 +
2592 + base_freq = get_base_frequency(clk_id);
2593 +
2594 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2595 +
2596 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2597 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2598 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2599 +
2600 + divider = clk_predivider * clk_postdivider;
2601 +
2602 +
2603 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2604 + {
2605 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2606 + }
2607 +
2608 +
2609 + else
2610 + {
2611 + /* return the current clock speed based upon the PLL setting */
2612 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2613 +
2614 + /* Get the PLL multiplication factor */
2615 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2616 +
2617 + /* Check if we're in divide mode or multiply mode */
2618 + if((clk_pll_setting & 0x1) == 0)
2619 + {
2620 + /* We're in divide mode */
2621 + if(pll_factor < 0x10)
2622 + return (CEIL(base_freq >> 1, divider));
2623 + else
2624 + return (CEIL(base_freq >> 2, divider));
2625 + }
2626 +
2627 + else /* We're in PLL mode */
2628 + {
2629 + /* See if PLLNDIV & PLLDIV are set */
2630 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2631 + {
2632 + if(clk_pll_setting & 0x1000)
2633 + {
2634 + /* clk = base_freq * k/2 */
2635 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2636 + }
2637 + else
2638 + {
2639 + /* clk = base_freq * (k-1) / 4)*/
2640 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2641 + }
2642 + }
2643 + else
2644 + {
2645 + if(pll_factor < 0x10)
2646 + {
2647 + /* clk = base_freq * k */
2648 + return(CEIL(base_freq * pll_factor, divider));
2649 + }
2650 +
2651 + else
2652 + {
2653 + /* clk = base_freq */
2654 + return(CEIL(base_freq, divider));
2655 + }
2656 + }
2657 + }
2658 + return(0); /* Should never reach here */
2659 +
2660 + }
2661 +
2662 +}
2663 +
2664 +
2665 +/* local helper functions */
2666 +
2667 +/****************************************************************************
2668 + * FUNCTION: get_base_frequency
2669 + ****************************************************************************
2670 + * Description: The above routine is called to get base frequency of the clocks.
2671 + ***************************************************************************/
2672 +
2673 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
2674 +{
2675 + /* update the current MIPs PLL output value, if the required
2676 + * source is MIPS PLL
2677 + */
2678 + if ( clk_src[clk_id] == &mips_pll_out)
2679 + {
2680 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
2681 + }
2682 +
2683 +
2684 + /* update the current System PLL output value, if the required
2685 + * source is system PLL
2686 + */
2687 + if ( clk_src[clk_id] == &sys_pll_out)
2688 + {
2689 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
2690 + }
2691 +
2692 + return (*clk_src[clk_id]);
2693 +
2694 +}
2695 +
2696 +
2697 +
2698 +/****************************************************************************
2699 + * FUNCTION: find_gcd
2700 + ****************************************************************************
2701 + * Description: The above routine is called to find gcd of 2 numbers.
2702 + ***************************************************************************/
2703 +static u32 find_gcd
2704 +(
2705 + u32 min,
2706 + u32 max
2707 + )
2708 +{
2709 + if (max % min == 0)
2710 + {
2711 + return min;
2712 + }
2713 + else
2714 + {
2715 + return find_gcd(max % min, min);
2716 + }
2717 +}
2718 +
2719 +/****************************************************************************
2720 + * FUNCTION: compute_prediv
2721 + ****************************************************************************
2722 + * Description: The above routine is called to compute predivider value
2723 + ***************************************************************************/
2724 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
2725 +{
2726 + u16 prediv;
2727 +
2728 + /* return the divider itself it it falls within the range of predivider*/
2729 + if (min <= divider && divider <= max)
2730 + {
2731 + return divider;
2732 + }
2733 +
2734 + /* find a value for prediv such that it is a factor of divider */
2735 + for (prediv = max; prediv >= min ; prediv--)
2736 + {
2737 + if ( (divider % prediv) == 0 )
2738 + {
2739 + return prediv;
2740 + }
2741 + }
2742 +
2743 + /* No such factor exists, return min as prediv */
2744 + return min;
2745 +}
2746 +
2747 +/****************************************************************************
2748 + * FUNCTION: get_val
2749 + ****************************************************************************
2750 + * Description: This routine is called to get values of divider and multiplier.
2751 + ***************************************************************************/
2752 +
2753 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
2754 +{
2755 + u32 temp_mul;
2756 + u32 temp_div;
2757 + u32 gcd;
2758 + u32 min_freq;
2759 + u32 max_freq;
2760 +
2761 + /* find gcd of base_freq, output_freq */
2762 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2763 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2764 + gcd = find_gcd(min_freq , max_freq);
2765 +
2766 + if(gcd == 0)
2767 + return; /* ERROR */
2768 +
2769 + /* compute values of multiplier and divider */
2770 + temp_mul = output_freq / gcd;
2771 + temp_div = base_freq / gcd;
2772 +
2773 +
2774 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2775 + if( temp_mul > PLL_MUL_MAXFACTOR )
2776 + {
2777 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2778 + return;
2779 +
2780 + find_approx(&temp_mul,&temp_div,base_freq);
2781 + }
2782 +
2783 + *multiplier = temp_mul;
2784 + *divider = temp_div;
2785 +}
2786 +
2787 +/****************************************************************************
2788 + * FUNCTION: find_approx
2789 + ****************************************************************************
2790 + * Description: This function gets the approx value of num/denom.
2791 + ***************************************************************************/
2792 +
2793 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
2794 +{
2795 + u32 num1;
2796 + u32 denom1;
2797 + u32 num2;
2798 + u32 denom2;
2799 + int32_t closest;
2800 + int32_t prev_closest;
2801 + u32 temp_num;
2802 + u32 temp_denom;
2803 + u32 normalize;
2804 + u32 gcd;
2805 + u32 output_freq;
2806 +
2807 + num1 = *num;
2808 + denom1 = *denom;
2809 +
2810 + prev_closest = 0x7fffffff; /* maximum possible value */
2811 + num2 = num1;
2812 + denom2 = denom1;
2813 +
2814 + /* start with max */
2815 + for(temp_num = 15; temp_num >=1; temp_num--)
2816 + {
2817 +
2818 + temp_denom = CEIL(temp_num * denom1, num1);
2819 + output_freq = (temp_num * base_freq) / temp_denom;
2820 +
2821 + if(temp_denom < 1)
2822 + {
2823 + break;
2824 + }
2825 + else
2826 + {
2827 + normalize = CEIL(num1,temp_num);
2828 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
2829 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2830 + {
2831 + prev_closest = closest;
2832 + num2 = temp_num;
2833 + denom2 = temp_denom;
2834 + }
2835 +
2836 + }
2837 +
2838 + }
2839 +
2840 + gcd = find_gcd(num2,denom2);
2841 + num2 = num2 / gcd;
2842 + denom2 = denom2 /gcd;
2843 +
2844 + *num = num2;
2845 + *denom = denom2;
2846 +}
2847 +
2848 +
2849 +/*****************************************************************************
2850 + * GPIO Control
2851 + *****************************************************************************/
2852 +
2853 +/****************************************************************************
2854 + * FUNCTION: tnetd73xx_gpio_init
2855 + ***************************************************************************/
2856 +void tnetd73xx_gpio_init()
2857 +{
2858 + /* Bring module out of reset */
2859 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2860 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2861 +}
2862 +
2863 +/****************************************************************************
2864 + * FUNCTION: tnetd73xx_gpio_ctrl
2865 + ***************************************************************************/
2866 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2867 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2868 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2869 +{
2870 + u32 pin_status;
2871 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
2872 + if (pin_mode == GPIO_PIN)
2873 + {
2874 + pin_status |= (1 << gpio_pin);
2875 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2876 +
2877 + /* Set pin direction */
2878 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2879 + if (pin_direction == GPIO_INPUT_PIN)
2880 + {
2881 + pin_status |= (1 << gpio_pin);
2882 + }
2883 + else /* GPIO_OUTPUT_PIN */
2884 + {
2885 + pin_status &= (~(1 << gpio_pin));
2886 + }
2887 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2888 + }
2889 + else /* FUNCTIONAL PIN */
2890 + {
2891 + pin_status &= (~(1 << gpio_pin));
2892 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2893 + }
2894 +
2895 +}
2896 +
2897 +/****************************************************************************
2898 + * FUNCTION: tnetd73xx_gpio_out
2899 + ***************************************************************************/
2900 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2901 +{
2902 + u32 pin_value;
2903 +
2904 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2905 + if (value == 1)
2906 + {
2907 + pin_value |= (1 << gpio_pin);
2908 + }
2909 + else
2910 + {
2911 + pin_value &= (~(1 << gpio_pin));
2912 + }
2913 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2914 +}
2915 +
2916 +/****************************************************************************
2917 + * FUNCTION: tnetd73xx_gpio_in
2918 + ***************************************************************************/
2919 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2920 +{
2921 + u32 pin_value;
2922 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
2923 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
2924 +}
2925 +
2926 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
2927 --- linux.old/arch/mips/config-shared.in 2005-10-21 16:43:18.917114000 +0200
2928 +++ linux.dev/arch/mips/config-shared.in 2005-11-10 01:12:43.950955750 +0100
2929 @@ -20,6 +20,16 @@
2930 mainmenu_option next_comment
2931 comment 'Machine selection'
2932 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2933 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2934 +if [ "$CONFIG_AR7" = "y" ]; then
2935 + choice 'Texas Instruments Reference Platform' \
2936 + "AR7DB CONFIG_AR7DB \
2937 + AR7RD CONFIG_AR7RD \
2938 + AR7WRD CONFIG_AR7WRD" AR7DB
2939 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
2940 + int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
2941 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2942 +fi
2943 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2944 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2945 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2946 @@ -239,6 +249,11 @@
2947 define_bool CONFIG_NONCOHERENT_IO y
2948 define_bool CONFIG_PC_KEYB y
2949 fi
2950 +if [ "$CONFIG_AR7" = "y" ]; then
2951 + define_bool CONFIG_IRQ_CPU y
2952 + define_bool CONFIG_NONCOHERENT_IO y
2953 + define_bool CONFIG_SWAP_IO_SPACE y
2954 +fi
2955 if [ "$CONFIG_CASIO_E55" = "y" ]; then
2956 define_bool CONFIG_IRQ_CPU y
2957 define_bool CONFIG_NONCOHERENT_IO y
2958 @@ -736,6 +751,7 @@
2959 mainmenu_option next_comment
2960 comment 'General setup'
2961 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2962 + "$CONFIG_AR7" = "y" -o \
2963 "$CONFIG_CASIO_E55" = "y" -o \
2964 "$CONFIG_DDB5074" = "y" -o \
2965 "$CONFIG_DDB5476" = "y" -o \
2966 @@ -797,6 +813,7 @@
2967 bool 'Networking support' CONFIG_NET
2968
2969 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2970 + "$CONFIG_AR7" = "y" -o \
2971 "$CONFIG_CASIO_E55" = "y" -o \
2972 "$CONFIG_DECSTATION" = "y" -o \
2973 "$CONFIG_IBM_WORKPAD" = "y" -o \
2974 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
2975 --- linux.old/arch/mips/kernel/head.S 2005-10-21 16:43:16.396956500 +0200
2976 +++ linux.dev/arch/mips/kernel/head.S 2005-11-10 01:10:45.807572250 +0100
2977 @@ -75,11 +75,11 @@
2978 * size!
2979 */
2980 NESTED(except_vec4, 0, sp)
2981 - .set push
2982 - .set noreorder
2983 -1: j 1b /* Dummy, will be replaced */
2984 - nop
2985 - .set pop
2986 + .set mips2
2987 + lui k0, 0x9400
2988 + ori k0, 0x200
2989 + jr k0
2990 + nop
2991 END(except_vec4)
2992
2993 /*
2994 diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
2995 --- linux.old/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
2996 +++ linux.dev/arch/mips/kernel/mips_ksyms.c 2005-11-10 01:10:45.811572500 +0100
2997 @@ -40,6 +40,12 @@
2998 extern long __strnlen_user_nocheck_asm(const char *s);
2999 extern long __strnlen_user_asm(const char *s);
3000
3001 +#ifdef CONFIG_AR7
3002 +#include <asm/ar7/adam2_env.h>
3003 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
3004 +#endif
3005 +
3006 +
3007 EXPORT_SYMBOL(mips_machtype);
3008 #ifdef CONFIG_EISA
3009 EXPORT_SYMBOL(EISA_bus);
3010 @@ -103,3 +109,10 @@
3011 #endif
3012
3013 EXPORT_SYMBOL(get_wchan);
3014 +
3015 +#ifdef CONFIG_AR7
3016 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3017 +EXPORT_SYMBOL_NOVERS(prom_getenv);
3018 +EXPORT_SYMBOL_NOVERS(prom_iterenv);
3019 +#endif
3020 +
3021 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3022 --- linux.old/arch/mips/kernel/setup.c 2005-10-21 16:43:16.396956500 +0200
3023 +++ linux.dev/arch/mips/kernel/setup.c 2005-11-10 01:14:16.376732000 +0100
3024 @@ -38,6 +38,7 @@
3025 #include <asm/io.h>
3026 #include <asm/ptrace.h>
3027 #include <asm/system.h>
3028 +#include <asm/addrspace.h>
3029
3030 struct cpuinfo_mips cpu_data[NR_CPUS];
3031 EXPORT_SYMBOL(cpu_data);
3032 @@ -88,7 +89,7 @@
3033 struct boot_mem_map boot_mem_map;
3034
3035 unsigned char aux_device_present;
3036 -extern char _ftext, _etext, _fdata, _edata, _end;
3037 +extern char _ftext, _etext, _fdata, _edata, _fbss, _end;
3038
3039 static char command_line[CL_SIZE];
3040 char saved_command_line[CL_SIZE];
3041 @@ -116,6 +117,7 @@
3042
3043 static struct resource code_resource = { "Kernel code" };
3044 static struct resource data_resource = { "Kernel data" };
3045 +static struct resource bss_resource = { "Kernel bss" };
3046
3047 asmlinkage void __init
3048 init_arch(int argc, char **argv, char **envp, int *prom_vec)
3049 @@ -272,7 +274,7 @@
3050 for (i = 0; i < boot_mem_map.nr_map; i++) {
3051 unsigned long start, end;
3052
3053 - if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3054 + if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3055 continue;
3056
3057 start = PFN_UP(boot_mem_map.map[i].addr);
3058 @@ -320,7 +322,8 @@
3059 #endif
3060
3061 /* Initialize the boot-time allocator with low memory only. */
3062 - bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
3063 + bootmap_size = init_bootmem_node(NODE_DATA(0), first_usable_pfn,
3064 + PFN_UP(PHYS_OFFSET), max_low_pfn);
3065
3066 /*
3067 * Register fully available low RAM pages with the bootmem allocator.
3068 @@ -371,11 +374,12 @@
3069 continue;
3070
3071 /* Register lowmem ranges */
3072 - free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
3073 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
3074 + size<<PAGE_SHIFT);
3075 }
3076
3077 /* Reserve the bootmap memory. */
3078 - reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3079 + reserve_bootmem_node(NODE_DATA(0), PFN_PHYS(first_usable_pfn), bootmap_size);
3080
3081 #ifdef CONFIG_BLK_DEV_INITRD
3082 /* Board specific code should have set up initrd_start and initrd_end */
3083 @@ -409,6 +413,8 @@
3084 code_resource.end = virt_to_bus(&_etext) - 1;
3085 data_resource.start = virt_to_bus(&_fdata);
3086 data_resource.end = virt_to_bus(&_edata) - 1;
3087 + bss_resource.start = virt_to_bus(&_fbss);
3088 + bss_resource.end = virt_to_bus(&_end) - 1;
3089
3090 /*
3091 * Request address space for all standard RAM.
3092 @@ -448,6 +454,7 @@
3093 */
3094 request_resource(res, &code_resource);
3095 request_resource(res, &data_resource);
3096 + request_resource(res, &bss_resource);
3097 }
3098 }
3099
3100 @@ -494,6 +501,7 @@
3101 void hp_setup(void);
3102 void au1x00_setup(void);
3103 void frame_info_init(void);
3104 + void ar7_setup(void);
3105
3106 frame_info_init();
3107 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3108 @@ -691,6 +699,11 @@
3109 pmc_yosemite_setup();
3110 break;
3111 #endif
3112 +#ifdef CONFIG_AR7
3113 + case MACH_GROUP_UNKNOWN:
3114 + ar7_setup();
3115 + break;
3116 +#endif
3117 default:
3118 panic("Unsupported architecture");
3119 }
3120 diff -urN linux.old/arch/mips/kernel/time.c linux.dev/arch/mips/kernel/time.c
3121 --- linux.old/arch/mips/kernel/time.c 2005-01-19 15:09:29.000000000 +0100
3122 +++ linux.dev/arch/mips/kernel/time.c 2005-11-10 01:12:43.950955750 +0100
3123 @@ -143,7 +143,6 @@
3124 expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
3125 write_c0_count(expirelo - cycles_per_jiffy);
3126 write_c0_compare(expirelo);
3127 - write_c0_count(count);
3128 }
3129
3130 int (*mips_timer_state)(void);
3131 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3132 --- linux.old/arch/mips/kernel/traps.c 2005-10-21 16:43:16.400956750 +0200
3133 +++ linux.dev/arch/mips/kernel/traps.c 2005-11-10 01:13:28.301727500 +0100
3134 @@ -869,9 +869,24 @@
3135
3136 exception_handlers[n] = handler;
3137 if (n == 0 && cpu_has_divec) {
3138 + printk(KERN_DEBUG "%s: using long jump via k0 to reach %08x\n",
3139 + __FUNCTION__, handler);
3140 + /* where does the 8 byte limit mentioned in head.S come from??? */
3141 + if (handler > 0x0fffffff) { /* maximum for single J instruction */
3142 + /* lui k0, 0x0000 */
3143 + *(volatile u32 *)(KSEG0+0x200) = 0x3c1a0000 | (handler >> 16);
3144 + /* ori k0, 0x0000 */
3145 + *(volatile u32 *)(KSEG0+0x204) = 0x375a0000 | (handler & 0xffff);
3146 + /* jr k0 */
3147 + *(volatile u32 *)(KSEG0+0x208) = 0x03400008;
3148 + /* nop */
3149 + *(volatile u32 *)(KSEG0+0x20C) = 0x00000000;
3150 + flush_icache_range(KSEG0+0x200, KSEG0+0x210);
3151 + } else {
3152 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3153 (0x03ffffff & (handler >> 2));
3154 - flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3155 + flush_icache_range(KSEG0+0x200, KSEG0+0x204);
3156 + }
3157 }
3158 return (void *)old_handler;
3159 }
3160 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3161 --- linux.old/arch/mips/mm/init.c 2004-02-18 14:36:30.000000000 +0100
3162 +++ linux.dev/arch/mips/mm/init.c 2005-11-10 01:14:16.376732000 +0100
3163 @@ -235,10 +235,13 @@
3164 #endif
3165 }
3166
3167 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
3168 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
3169 +
3170 void __init paging_init(void)
3171 {
3172 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3173 - unsigned long max_dma, high, low;
3174 + unsigned long max_dma, high, low, start;
3175
3176 pagetable_init();
3177
3178 @@ -247,7 +250,8 @@
3179 #endif
3180
3181 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
3182 - low = max_low_pfn;
3183 + start = START_PFN;
3184 + low = MAX_LOW_PFN - start;
3185 high = highend_pfn;
3186
3187 #ifdef CONFIG_ISA
3188 @@ -270,7 +274,8 @@
3189 zones_size[ZONE_HIGHMEM] = high - low;
3190 #endif
3191
3192 - free_area_init(zones_size);
3193 + free_area_init_node(0, NODE_DATA(0), 0, zones_size,
3194 + start << PAGE_SHIFT, 0);
3195 }
3196
3197 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3198 @@ -283,7 +288,7 @@
3199 for (i = 0; i < boot_mem_map.nr_map; i++) {
3200 unsigned long addr, end;
3201
3202 - if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3203 + if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3204 /* not usable memory */
3205 continue;
3206
3207 @@ -313,16 +318,17 @@
3208 max_mapnr = num_physpages = highend_pfn;
3209 num_mappedpages = max_low_pfn;
3210 #else
3211 - max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
3212 + max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
3213 #endif
3214 - high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
3215 -
3216 - totalram_pages += free_all_bootmem();
3217 +
3218 + high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
3219 +
3220 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
3221 totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */
3222
3223 reservedpages = ram = 0;
3224 - for (tmp = 0; tmp < max_low_pfn; tmp++)
3225 - if (page_is_ram(tmp)) {
3226 + for (tmp = 0; tmp < max_mapnr; tmp++)
3227 + if (page_is_ram(START_PFN + tmp)) {
3228 ram++;
3229 if (PageReserved(mem_map+tmp))
3230 reservedpages++;
3231 @@ -377,13 +383,13 @@
3232 #endif
3233
3234 extern char __init_begin, __init_end;
3235 -extern void prom_free_prom_memory(void) __init;
3236 +extern unsigned long prom_free_prom_memory(void) __init;
3237
3238 void free_initmem(void)
3239 {
3240 unsigned long addr;
3241
3242 - prom_free_prom_memory ();
3243 + totalram_pages += prom_free_prom_memory ();
3244
3245 addr = (unsigned long) &__init_begin;
3246 while (addr < (unsigned long) &__init_end) {
3247 diff -urN linux.old/drivers/char/Config.in linux.dev/drivers/char/Config.in
3248 --- linux.old/drivers/char/Config.in 2005-10-21 16:43:16.440959250 +0200
3249 +++ linux.dev/drivers/char/Config.in 2005-11-10 01:10:45.843574500 +0100
3250 @@ -188,6 +188,14 @@
3251 tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3252 fi
3253
3254 +if [ "$CONFIG_AR7" = "y" ]; then
3255 + bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3256 + dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3257 +
3258 + define_int CONFIG_AR7_VLYNQ_PORTS 2
3259 + tristate 'ADAM2 environment support (read-only)' CONFIG_AR7_ADAM2
3260 +fi
3261 +
3262 source drivers/i2c/Config.in
3263
3264 mainmenu_option next_comment
3265 diff -urN linux.old/drivers/char/Config.in.orig linux.dev/drivers/char/Config.in.orig
3266 --- linux.old/drivers/char/Config.in.orig 1970-01-01 01:00:00.000000000 +0100
3267 +++ linux.dev/drivers/char/Config.in.orig 2005-11-10 01:10:45.863575750 +0100
3268 @@ -0,0 +1,414 @@
3269 +#
3270 +# Character device configuration
3271 +#
3272 +mainmenu_option next_comment
3273 +comment 'Character devices'
3274 +
3275 +bool 'Virtual terminal' CONFIG_VT
3276 +if [ "$CONFIG_VT" = "y" ]; then
3277 + bool ' Support for console on virtual terminal' CONFIG_VT_CONSOLE
3278 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3279 + bool ' Support for Lasi/Dino PS2 port' CONFIG_GSC_PS2
3280 + fi
3281 +fi
3282 +tristate 'Standard/generic (8250/16550 and compatible UARTs) serial support' CONFIG_SERIAL
3283 +if [ "$CONFIG_SERIAL" = "y" ]; then
3284 + bool ' Support for console on serial port' CONFIG_SERIAL_CONSOLE
3285 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3286 + bool ' serial port on GSC support' CONFIG_SERIAL_GSC
3287 + fi
3288 + if [ "$CONFIG_IA64" = "y" ]; then
3289 + bool ' Support for serial port described by EFI HCDP table' CONFIG_SERIAL_HCDP
3290 + fi
3291 + if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
3292 + tristate ' Atomwide serial port support' CONFIG_ATOMWIDE_SERIAL
3293 + tristate ' Dual serial port support' CONFIG_DUALSP_SERIAL
3294 + fi
3295 +fi
3296 +dep_mbool 'Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED $CONFIG_SERIAL
3297 +if [ "$CONFIG_SERIAL_EXTENDED" = "y" ]; then
3298 + bool ' Support more than 4 serial ports' CONFIG_SERIAL_MANY_PORTS
3299 + bool ' Support for sharing serial interrupts' CONFIG_SERIAL_SHARE_IRQ
3300 + bool ' Autodetect IRQ on standard ports (unsafe)' CONFIG_SERIAL_DETECT_IRQ
3301 + bool ' Support special multiport boards' CONFIG_SERIAL_MULTIPORT
3302 + bool ' Support the Bell Technologies HUB6 card' CONFIG_HUB6
3303 +fi
3304 +bool 'Non-standard serial port support' CONFIG_SERIAL_NONSTANDARD
3305 +if [ "$CONFIG_SERIAL_NONSTANDARD" = "y" ]; then
3306 + tristate ' Computone IntelliPort Plus serial support' CONFIG_COMPUTONE
3307 + tristate ' Comtrol Rocketport support' CONFIG_ROCKETPORT
3308 + tristate ' Cyclades async mux support' CONFIG_CYCLADES
3309 + if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_CYCLADES" != "n" ]; then
3310 + bool ' Cyclades-Z interrupt mode operation (EXPERIMENTAL)' CONFIG_CYZ_INTR
3311 + fi
3312 + if [ "$CONFIG_X86_64" != "y" ]; then
3313 + tristate ' Digiboard Intelligent Async Support' CONFIG_DIGIEPCA
3314 + if [ "$CONFIG_DIGIEPCA" = "n" ]; then
3315 + tristate ' Digiboard PC/Xx Support' CONFIG_DIGI
3316 + fi
3317 + fi
3318 + dep_tristate ' Hayes ESP serial port support' CONFIG_ESPSERIAL $CONFIG_ISA
3319 + tristate ' Moxa Intellio support' CONFIG_MOXA_INTELLIO
3320 + tristate ' Moxa SmartIO support' CONFIG_MOXA_SMARTIO
3321 + if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
3322 + dep_tristate ' Multi-Tech multiport card support (EXPERIMENTAL)' CONFIG_ISI m
3323 + fi
3324 + tristate ' Microgate SyncLink card support' CONFIG_SYNCLINK
3325 + tristate ' SyncLink Multiport support' CONFIG_SYNCLINKMP
3326 + tristate ' HDLC line discipline support' CONFIG_N_HDLC
3327 + tristate ' SDL RISCom/8 card support' CONFIG_RISCOM8
3328 + if [ "$CONFIG_X86_64" != "y" ]; then
3329 + tristate ' Specialix IO8+ card support' CONFIG_SPECIALIX
3330 + if [ "$CONFIG_SPECIALIX" != "n" ]; then
3331 + bool ' Specialix DTR/RTS pin is RTS' CONFIG_SPECIALIX_RTSCTS
3332 + fi
3333 + tristate ' Specialix SX (and SI) card support' CONFIG_SX
3334 + tristate ' Specialix RIO system support' CONFIG_RIO
3335 + if [ "$CONFIG_RIO" != "n" ]; then
3336 + bool ' Support really old RIO/PCI cards' CONFIG_RIO_OLDPCI
3337 + fi
3338 + fi
3339 + bool ' Stallion multiport serial support' CONFIG_STALDRV
3340 + if [ "$CONFIG_STALDRV" = "y" ]; then
3341 + tristate ' Stallion EasyIO or EC8/32 support' CONFIG_STALLION
3342 + tristate ' Stallion EC8/64, ONboard, Brumby support' CONFIG_ISTALLION
3343 + fi
3344 + if [ "$CONFIG_PARISC" = "y" ]; then
3345 + if [ "$CONFIG_PDC_CONSOLE" != "y" ]; then
3346 + bool ' Serial MUX support' CONFIG_SERIAL_MUX CONFIG_SERIAL_NONSTANDARD
3347 + fi
3348 + if [ "$CONFIG_SERIAL_MUX" != "y" ]; then
3349 + bool ' PDC software console support' CONFIG_PDC_CONSOLE CONFIG_SERIAL_NONSTANDARD
3350 + fi
3351 + fi
3352 + if [ "$CONFIG_MIPS" = "y" ]; then
3353 + bool ' TX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
3354 + dep_bool ' Console on TX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
3355 + bool ' TMPTX39XX/49XX serial port support' CONFIG_SERIAL_TXX9
3356 + dep_bool ' Console on TMPTX39XX/49XX serial port' CONFIG_SERIAL_TXX9_CONSOLE $CONFIG_SERIAL_TXX9
3357 + if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3358 + bool ' Enable Au1x00 UART Support' CONFIG_AU1X00_UART
3359 + if [ "$CONFIG_AU1X00_UART" = "y" ]; then
3360 + bool ' Enable Au1x00 serial console' CONFIG_AU1X00_SERIAL_CONSOLE
3361 + fi
3362 + dep_tristate ' Au1x00 USB TTY Device support' CONFIG_AU1X00_USB_TTY $CONFIG_SOC_AU1X00
3363 + if [ "$CONFIG_AU1000_USB_TTY" != "y" ]; then
3364 + dep_tristate ' Au1x00 USB Raw Device support' CONFIG_AU1X00_USB_RAW $CONFIG_SOC_AU1X00
3365 + fi
3366 + if [ "$CONFIG_AU1X00_USB_TTY" != "n" -o \
3367 + "$CONFIG_AU1X00_USB_RAW" != "n" ]; then
3368 + define_bool CONFIG_AU1X00_USB_DEVICE y
3369 + fi
3370 + fi
3371 + bool ' TXx927 SIO support' CONFIG_TXX927_SERIAL
3372 + if [ "$CONFIG_TXX927_SERIAL" = "y" ]; then
3373 + bool ' TXx927 SIO Console support' CONFIG_TXX927_SERIAL_CONSOLE
3374 + fi
3375 + if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]; then
3376 + bool ' Support for BCM1xxx onchip DUART' CONFIG_SIBYTE_SB1250_DUART
3377 + if [ "$CONFIG_SIBYTE_SB1250_DUART" = "y" ]; then
3378 + bool ' Console on BCM1xxx DUART' CONFIG_SIBYTE_SB1250_DUART_CONSOLE
3379 + if [ "$CONFIG_SIBYTE_SB1250_DUART_CONSOLE" = "y" ]; then
3380 + define_bool CONFIG_SERIAL_CONSOLE y
3381 + fi
3382 + fi
3383 + fi
3384 + fi
3385 + if [ "$CONFIG_DECSTATION" = "y" ]; then
3386 + bool ' DECstation serial support' CONFIG_SERIAL_DEC
3387 + dep_bool ' Support for console on a DECstation serial port' CONFIG_SERIAL_DEC_CONSOLE $CONFIG_SERIAL_DEC
3388 + dep_bool ' DZ11 serial support' CONFIG_DZ $CONFIG_SERIAL_DEC $CONFIG_MIPS32
3389 + dep_bool ' Z85C30 serial support' CONFIG_ZS $CONFIG_SERIAL_DEC $CONFIG_TC
3390 + fi
3391 + if [ "$CONFIG_SGI_IP22" = "y" ]; then
3392 + bool ' SGI Zilog85C30 serial support' CONFIG_IP22_SERIAL
3393 + fi
3394 + if [ "$CONFIG_IA64" = "y" ]; then
3395 + bool ' SGI SN2 l1 serial port support' CONFIG_SGI_L1_SERIAL
3396 + if [ "$CONFIG_SGI_L1_SERIAL" = "y" ]; then
3397 + bool ' SGI SN2 l1 Console support' CONFIG_SGI_L1_SERIAL_CONSOLE
3398 + fi
3399 + if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ]; then
3400 + bool ' SGI SN2 IOC4 serial port support' CONFIG_SGI_IOC4_SERIAL
3401 + fi
3402 + fi
3403 +fi
3404 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
3405 + tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
3406 +fi
3407 +if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
3408 + bool 'DC21285 serial port support' CONFIG_SERIAL_21285
3409 + if [ "$CONFIG_SERIAL_21285" = "y" ]; then
3410 + if [ "$CONFIG_OBSOLETE" = "y" ]; then
3411 + bool ' Use /dev/ttyS0 device (OBSOLETE)' CONFIG_SERIAL_21285_OLD
3412 + fi
3413 + bool ' Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE
3414 + fi
3415 + if [ "$CONFIG_PARISC" = "y" ]; then
3416 + bool ' PDC software console support' CONFIG_PDC_CONSOLE
3417 + fi
3418 +fi
3419 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
3420 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3421 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3422 + define_bool CONFIG_IT8172_CIR y
3423 + else
3424 + bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
3425 + fi
3426 + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
3427 + bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
3428 +fi
3429 +if [ "$CONFIG_MIPS_IVR" = "y" ]; then
3430 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3431 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3432 + define_bool CONFIG_IT8172_CIR y
3433 + fi
3434 + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
3435 +fi
3436 +if [ "$CONFIG_CPU_VR41XX" = "y" ]; then
3437 + bool 'NEC VR4100 series Keyboard Interface Unit Support ' CONFIG_VR41XX_KIU
3438 +fi
3439 +bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
3440 +if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
3441 + int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 256
3442 +fi
3443 +if [ "$CONFIG_PARPORT" != "n" ]; then
3444 + dep_tristate 'Parallel printer support' CONFIG_PRINTER $CONFIG_PARPORT
3445 + if [ "$CONFIG_PRINTER" != "n" ]; then
3446 + bool ' Support for console on line printer' CONFIG_LP_CONSOLE
3447 + fi
3448 + dep_tristate 'Support for user-space parallel port device drivers' CONFIG_PPDEV $CONFIG_PARPORT
3449 + dep_tristate 'Texas Instruments parallel link cable support' CONFIG_TIPAR $CONFIG_PARPORT
3450 +fi
3451 +
3452 +if [ "$CONFIG_PPC64" = "y" ] ; then
3453 + bool 'pSeries Hypervisor Virtual Console support' CONFIG_HVC_CONSOLE
3454 +fi
3455 +if [ "$CONFIG_ALL_PPC" = "y" ]; then
3456 + tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3457 +fi
3458 +
3459 +if [ "$CONFIG_AR7" = "y" ]; then
3460 + bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3461 + dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3462 +
3463 + define_int CONFIG_AR7_VLYNQ_PORTS 2
3464 +fi
3465 +
3466 +source drivers/i2c/Config.in
3467 +
3468 +mainmenu_option next_comment
3469 +comment 'Mice'
3470 +tristate 'Bus Mouse Support' CONFIG_BUSMOUSE
3471 +if [ "$CONFIG_BUSMOUSE" != "n" ]; then
3472 + dep_tristate ' ATIXL busmouse support' CONFIG_ATIXL_BUSMOUSE $CONFIG_BUSMOUSE
3473 + dep_tristate ' Logitech busmouse support' CONFIG_LOGIBUSMOUSE $CONFIG_BUSMOUSE
3474 + dep_tristate ' Microsoft busmouse support' CONFIG_MS_BUSMOUSE $CONFIG_BUSMOUSE
3475 + if [ "$CONFIG_ADB" = "y" -a "$CONFIG_ADB_KEYBOARD" = "y" ]; then
3476 + dep_tristate ' Apple Desktop Bus mouse support (old driver)' CONFIG_ADBMOUSE $CONFIG_BUSMOUSE
3477 + fi
3478 +# if [ "$CONFIG_DECSTATION" = "y" ]; then
3479 +# dep_bool ' MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE $CONFIG_ACCESSBUS
3480 +# fi
3481 +fi
3482 +
3483 +tristate 'Mouse Support (not serial and bus mice)' CONFIG_MOUSE
3484 +if [ "$CONFIG_MOUSE" != "n" ]; then
3485 + bool ' PS/2 mouse (aka "auxiliary device") support' CONFIG_PSMOUSE
3486 + tristate ' C&T 82C710 mouse port support (as on TI Travelmate)' CONFIG_82C710_MOUSE
3487 + tristate ' PC110 digitizer pad support' CONFIG_PC110_PAD
3488 + tristate ' MK712 touch screen support' CONFIG_MK712_MOUSE
3489 +fi
3490 +endmenu
3491 +
3492 +source drivers/char/joystick/Config.in
3493 +
3494 +tristate 'QIC-02 tape support' CONFIG_QIC02_TAPE
3495 +if [ "$CONFIG_QIC02_TAPE" != "n" ]; then
3496 + bool ' Do you want runtime configuration for QIC-02' CONFIG_QIC02_DYNCONF
3497 + if [ "$CONFIG_QIC02_DYNCONF" != "y" ]; then
3498 + comment ' Edit configuration parameters in ./include/linux/tpqic02.h!'
3499 + else
3500 + comment ' Setting runtime QIC-02 configuration is done with qic02conf'
3501 + comment ' from the tpqic02-support package. It is available at'
3502 + comment ' metalab.unc.edu or ftp://titus.cfw.com/pub/Linux/util/'
3503 + fi
3504 +fi
3505 +
3506 +tristate 'IPMI top-level message handler' CONFIG_IPMI_HANDLER
3507 +dep_mbool ' Generate a panic event to all BMCs on a panic' CONFIG_IPMI_PANIC_EVENT $CONFIG_IPMI_HANDLER
3508 +dep_tristate ' Device interface for IPMI' CONFIG_IPMI_DEVICE_INTERFACE $CONFIG_IPMI_HANDLER
3509 +dep_tristate ' IPMI KCS handler' CONFIG_IPMI_KCS $CONFIG_IPMI_HANDLER
3510 +dep_tristate ' IPMI Watchdog Timer' CONFIG_IPMI_WATCHDOG $CONFIG_IPMI_HANDLER
3511 +
3512 +mainmenu_option next_comment
3513 +comment 'Watchdog Cards'
3514 +bool 'Watchdog Timer Support' CONFIG_WATCHDOG
3515 +if [ "$CONFIG_WATCHDOG" != "n" ]; then
3516 + bool ' Disable watchdog shutdown on close' CONFIG_WATCHDOG_NOWAYOUT
3517 + tristate ' Acquire SBC Watchdog Timer' CONFIG_ACQUIRE_WDT
3518 + tristate ' Advantech SBC Watchdog Timer' CONFIG_ADVANTECH_WDT
3519 + tristate ' ALi M7101 PMU on ALi 1535D+ Watchdog Timer' CONFIG_ALIM1535_WDT
3520 + tristate ' ALi M7101 PMU Watchdog Timer' CONFIG_ALIM7101_WDT
3521 + tristate ' AMD "Elan" SC520 Watchdog Timer' CONFIG_SC520_WDT
3522 + tristate ' Berkshire Products PC Watchdog' CONFIG_PCWATCHDOG
3523 + if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
3524 + tristate ' DC21285 watchdog' CONFIG_21285_WATCHDOG
3525 + if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
3526 + tristate ' NetWinder WB83C977 watchdog' CONFIG_977_WATCHDOG
3527 + fi
3528 + fi
3529 + tristate ' Eurotech CPU-1220/1410 Watchdog Timer' CONFIG_EUROTECH_WDT
3530 + tristate ' IB700 SBC Watchdog Timer' CONFIG_IB700_WDT
3531 + tristate ' ICP ELectronics Wafer 5823 Watchdog' CONFIG_WAFER_WDT
3532 + tristate ' Intel i810 TCO timer / Watchdog' CONFIG_I810_TCO
3533 + tristate ' Mixcom Watchdog' CONFIG_MIXCOMWD
3534 + tristate ' SBC-60XX Watchdog Timer' CONFIG_60XX_WDT
3535 + dep_tristate ' SC1200 Watchdog Timer (EXPERIMENTAL)' CONFIG_SC1200_WDT $CONFIG_EXPERIMENTAL
3536 + tristate ' NatSemi SCx200 Watchdog' CONFIG_SCx200_WDT
3537 + tristate ' Software Watchdog' CONFIG_SOFT_WATCHDOG
3538 + tristate ' W83877F (EMACS) Watchdog Timer' CONFIG_W83877F_WDT
3539 + tristate ' WDT Watchdog timer' CONFIG_WDT
3540 + tristate ' WDT PCI Watchdog timer' CONFIG_WDTPCI
3541 + if [ "$CONFIG_WDT" != "n" ]; then
3542 + bool ' WDT501 features' CONFIG_WDT_501
3543 + if [ "$CONFIG_WDT_501" = "y" ]; then
3544 + bool ' Fan Tachometer' CONFIG_WDT_501_FAN
3545 + fi
3546 + fi
3547 + tristate ' ZF MachZ Watchdog' CONFIG_MACHZ_WDT
3548 + if [ "$CONFIG_SGI_IP22" = "y" ]; then
3549 + dep_tristate ' Indy/I2 Hardware Watchdog' CONFIG_INDYDOG $CONFIG_SGI_IP22
3550 + fi
3551 + if [ "$CONFIG_8xx" = "y" ]; then
3552 + tristate ' MPC8xx Watchdog Timer' CONFIG_8xx_WDT
3553 + fi
3554 +fi
3555 +endmenu
3556 +
3557 +if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
3558 + tristate 'NetWinder thermometer support' CONFIG_DS1620
3559 + tristate 'NetWinder Button' CONFIG_NWBUTTON
3560 + if [ "$CONFIG_NWBUTTON" != "n" ]; then
3561 + bool ' Reboot Using Button' CONFIG_NWBUTTON_REBOOT
3562 + fi
3563 + tristate 'NetWinder flash support' CONFIG_NWFLASH
3564 +fi
3565 +tristate 'NatSemi SCx200 Support' CONFIG_SCx200
3566 +dep_tristate ' NatSemi SCx200 GPIO Support' CONFIG_SCx200_GPIO $CONFIG_SCx200
3567 +
3568 +if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ] ; then
3569 + bool 'SGI SN2 fetchop support' CONFIG_FETCHOP
3570 +fi
3571 +
3572 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_X86_64" = "y" ]; then
3573 + dep_tristate 'AMD 768/8111 Random Number Generator support' CONFIG_AMD_RNG $CONFIG_PCI
3574 +fi
3575 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
3576 + dep_tristate 'Intel i8x0 Random Number Generator support' CONFIG_INTEL_RNG $CONFIG_PCI
3577 +fi
3578 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" -o \
3579 + "$CONFIG_X86_64" = "y" ]; then
3580 + dep_tristate 'Intel/AMD/VIA HW Random Number Generator support' CONFIG_HW_RANDOM $CONFIG_PCI
3581 +fi
3582 +dep_tristate 'AMD 76x native power management (Experimental)' CONFIG_AMD_PM768 $CONFIG_PCI
3583 +tristate '/dev/nvram support' CONFIG_NVRAM
3584 +tristate 'Enhanced Real Time Clock Support' CONFIG_RTC
3585 +if [ "$CONFIG_IA64" = "y" ]; then
3586 + bool 'EFI Real Time Clock Services' CONFIG_EFI_RTC
3587 +fi
3588 +if [ "$CONFIG_OBSOLETE" = "y" -a "$CONFIG_ALPHA_BOOK1" = "y" ]; then
3589 + bool 'Tadpole ANA H8 Support (OBSOLETE)' CONFIG_H8
3590 +fi
3591 +if [ "$CONFIG_SGI_IP22" = "y" ]; then
3592 + tristate 'Dallas DS1286 RTC support' CONFIG_DS1286
3593 +fi
3594 +if [ "$CONFIG_SGI_IP27" = "y" ]; then
3595 + tristate 'SGI M48T35 RTC support' CONFIG_SGI_IP27_RTC
3596 +fi
3597 +if [ "$CONFIG_TOSHIBA_RBTX4927" = "y" -o "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
3598 + tristate 'Dallas DS1742 RTC support' CONFIG_DS1742
3599 +fi
3600 +
3601 +tristate 'Double Talk PC internal speech card support' CONFIG_DTLK
3602 +tristate 'Siemens R3964 line discipline' CONFIG_R3964
3603 +tristate 'Applicom intelligent fieldbus card support' CONFIG_APPLICOM
3604 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_X86" = "y" -a "$CONFIG_X86_64" != "y" ]; then
3605 + dep_tristate 'Sony Vaio Programmable I/O Control Device support (EXPERIMENTAL)' CONFIG_SONYPI $CONFIG_PCI
3606 +fi
3607 +
3608 +mainmenu_option next_comment
3609 +comment 'Ftape, the floppy tape device driver'
3610 +tristate 'Ftape (QIC-80/Travan) support' CONFIG_FTAPE
3611 +if [ "$CONFIG_FTAPE" != "n" ]; then
3612 + source drivers/char/ftape/Config.in
3613 +fi
3614 +
3615 +endmenu
3616 +
3617 +if [ "$CONFIG_GART_IOMMU" = "y" ]; then
3618 + bool '/dev/agpgart (AGP Support)' CONFIG_AGP
3619 + define_bool CONFIG_AGP_AMD_K8 y
3620 +else
3621 + tristate '/dev/agpgart (AGP Support)' CONFIG_AGP
3622 +fi
3623 +if [ "$CONFIG_AGP" != "n" ]; then
3624 + bool ' Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support' CONFIG_AGP_INTEL
3625 + bool ' Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
3626 + bool ' VIA chipset support' CONFIG_AGP_VIA
3627 + bool ' AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD
3628 + if [ "$CONFIG_GART_IOMMU" != "y" ]; then
3629 + bool ' AMD Opteron/Athlon64 on-CPU GART support' CONFIG_AGP_AMD_K8
3630 + fi
3631 + bool ' Generic SiS support' CONFIG_AGP_SIS
3632 + bool ' ALI chipset support' CONFIG_AGP_ALI
3633 + bool ' Serverworks LE/HE support' CONFIG_AGP_SWORKS
3634 + if [ "$CONFIG_X86" = "y" ]; then
3635 + bool ' NVIDIA chipset support' CONFIG_AGP_NVIDIA
3636 + fi
3637 + if [ "$CONFIG_IA64" = "y" ]; then
3638 + bool ' Intel 460GX support' CONFIG_AGP_I460
3639 + bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
3640 + fi
3641 + bool ' ATI IGP chipset support' CONFIG_AGP_ATI
3642 +fi
3643 +
3644 +mainmenu_option next_comment
3645 +comment 'Direct Rendering Manager (XFree86 DRI support)'
3646 +bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM
3647 +if [ "$CONFIG_DRM" = "y" ]; then
3648 + bool ' Build drivers for old (XFree 4.0) DRM' CONFIG_DRM_OLD
3649 + if [ "$CONFIG_DRM_OLD" = "y" ]; then
3650 + comment 'DRM 4.0 drivers'
3651 + source drivers/char/drm-4.0/Config.in
3652 + else
3653 + comment 'DRM 4.1 drivers'
3654 + define_bool CONFIG_DRM_NEW y
3655 + source drivers/char/drm/Config.in
3656 + fi
3657 +fi
3658 +
3659 +if [ "$CONFIG_X86" = "y" ]; then
3660 + tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
3661 +fi
3662 +
3663 +endmenu
3664 +
3665 +if [ "$CONFIG_HOTPLUG" = "y" -a "$CONFIG_PCMCIA" != "n" ]; then
3666 + source drivers/char/pcmcia/Config.in
3667 +fi
3668 +if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3669 + tristate ' Alchemy Au1x00 GPIO device support' CONFIG_AU1X00_GPIO
3670 + tristate ' Au1000/ADS7846 touchscreen support' CONFIG_TS_AU1X00_ADS7846
3671 + #tristate ' Alchemy Au1550 PSC SPI support' CONFIG_AU1550_PSC_SPI
3672 +fi
3673 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
3674 + tristate ' ITE GPIO' CONFIG_ITE_GPIO
3675 +fi
3676 +
3677 +if [ "$CONFIG_X86" = "y" ]; then
3678 + tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
3679 + dep_tristate 'HP OB600 C/CT Pop-up mouse support' CONFIG_OBMOUSE $CONFIG_INPUT_MOUSEDEV
3680 +fi
3681 +
3682 +endmenu
3683 diff -urN linux.old/drivers/char/Makefile linux.dev/drivers/char/Makefile
3684 --- linux.old/drivers/char/Makefile 2005-10-21 16:43:16.460960500 +0200
3685 +++ linux.dev/drivers/char/Makefile 2005-11-10 01:10:45.871576250 +0100
3686 @@ -240,6 +240,13 @@
3687 obj-y += joystick/js.o
3688 endif
3689
3690 +#
3691 +# Texas Intruments VLYNQ driver
3692 +#
3693 +
3694 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
3695 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
3696 +
3697 obj-$(CONFIG_FETCHOP) += fetchop.o
3698 obj-$(CONFIG_BUSMOUSE) += busmouse.o
3699 obj-$(CONFIG_DTLK) += dtlk.o
3700 @@ -340,6 +347,11 @@
3701 obj-y += ipmi/ipmi.o
3702 endif
3703
3704 +subdir-$(CONFIG_AR7_ADAM2) += ticfg
3705 +ifeq ($(CONFIG_AR7_ADAM2),y)
3706 + obj-y += ticfg/ticfg.o
3707 +endif
3708 +
3709 include $(TOPDIR)/Rules.make
3710
3711 fastdep:
3712 diff -urN linux.old/drivers/char/Makefile.orig linux.dev/drivers/char/Makefile.orig
3713 --- linux.old/drivers/char/Makefile.orig 1970-01-01 01:00:00.000000000 +0100
3714 +++ linux.dev/drivers/char/Makefile.orig 2005-11-10 01:10:45.871576250 +0100
3715 @@ -0,0 +1,374 @@
3716 +#
3717 +# Makefile for the kernel character device drivers.
3718 +#
3719 +# Note! Dependencies are done automagically by 'make dep', which also
3720 +# removes any old dependencies. DON'T put your own dependencies here
3721 +# unless it's something special (ie not a .c file).
3722 +#
3723 +# Note 2! The CFLAGS definitions are now inherited from the
3724 +# parent makes..
3725 +#
3726 +
3727 +#
3728 +# This file contains the font map for the default (hardware) font
3729 +#
3730 +FONTMAPFILE = cp437.uni
3731 +
3732 +O_TARGET := char.o
3733 +
3734 +obj-y += mem.o tty_io.o n_tty.o tty_ioctl.o raw.o pty.o misc.o random.o
3735 +
3736 +# All of the (potential) objects that export symbols.
3737 +# This list comes from 'grep -l EXPORT_SYMBOL *.[hc]'.
3738 +
3739 +export-objs := busmouse.o console.o keyboard.o sysrq.o \
3740 + misc.o pty.o random.o selection.o serial.o \
3741 + sonypi.o tty_io.o tty_ioctl.o generic_serial.o \
3742 + au1000_gpio.o vac-serial.o hp_psaux.o nvram.o \
3743 + scx200.o fetchop.o
3744 +
3745 +mod-subdirs := joystick ftape drm drm-4.0 pcmcia
3746 +
3747 +list-multi :=
3748 +
3749 +KEYMAP =defkeymap.o
3750 +KEYBD =pc_keyb.o
3751 +CONSOLE =console.o
3752 +SERIAL =serial.o
3753 +
3754 +ifeq ($(ARCH),s390)
3755 + KEYMAP =
3756 + KEYBD =
3757 + CONSOLE =
3758 + SERIAL =
3759 +endif
3760 +
3761 +ifeq ($(ARCH),mips)
3762 + ifneq ($(CONFIG_PC_KEYB),y)
3763 + KEYBD =
3764 + endif
3765 + ifeq ($(CONFIG_VR41XX_KIU),y)
3766 + ifeq ($(CONFIG_IBM_WORKPAD),y)
3767 + KEYMAP = ibm_workpad_keymap.o
3768 + endif
3769 + ifeq ($(CONFIG_VICTOR_MPC30X),y)
3770 + KEYMAP = victor_mpc30x_keymap.o
3771 + endif
3772 + KEYBD = vr41xx_keyb.o
3773 + endif
3774 +endif
3775 +
3776 +ifeq ($(ARCH),s390x)
3777 + KEYMAP =
3778 + KEYBD =
3779 + CONSOLE =
3780 + SERIAL =
3781 +endif
3782 +
3783 +ifeq ($(ARCH),m68k)
3784 + ifdef CONFIG_AMIGA
3785 + KEYBD = amikeyb.o
3786 + else
3787 + ifndef CONFIG_MAC
3788 + KEYBD =
3789 + endif
3790 + endif
3791 + SERIAL =
3792 +endif
3793 +
3794 +ifeq ($(ARCH),parisc)
3795 + ifdef CONFIG_GSC_PS2
3796 + KEYBD = hp_psaux.o hp_keyb.o
3797 + else
3798 + KEYBD =
3799 + endif
3800 + ifdef CONFIG_SERIAL_MUX
3801 + CONSOLE += mux.o
3802 + endif
3803 + ifdef CONFIG_PDC_CONSOLE
3804 + CONSOLE += pdc_console.o
3805 + endif
3806 +endif
3807 +
3808 +ifdef CONFIG_Q40
3809 + KEYBD += q40_keyb.o
3810 + SERIAL = serial.o
3811 +endif
3812 +
3813 +ifdef CONFIG_APOLLO
3814 + KEYBD += dn_keyb.o
3815 +endif
3816 +
3817 +ifeq ($(ARCH),parisc)
3818 + ifdef CONFIG_GSC_PS2
3819 + KEYBD = hp_psaux.o hp_keyb.o
3820 + else
3821 + KEYBD =
3822 + endif
3823 + ifdef CONFIG_PDC_CONSOLE
3824 + CONSOLE += pdc_console.o
3825 + endif
3826 +endif
3827 +
3828 +ifeq ($(ARCH),arm)
3829 + ifneq ($(CONFIG_PC_KEYMAP),y)
3830 + KEYMAP =
3831 + endif
3832 + ifneq ($(CONFIG_PC_KEYB),y)
3833 + KEYBD =
3834 + endif
3835 +endif
3836 +
3837 +ifeq ($(ARCH),sh)
3838 + KEYMAP =
3839 + KEYBD =
3840 + CONSOLE =
3841 + ifeq ($(CONFIG_SH_HP600),y)
3842 + KEYMAP = defkeymap.o
3843 + KEYBD = scan_keyb.o hp600_keyb.o
3844 + CONSOLE = console.o
3845 + endif
3846 + ifeq ($(CONFIG_SH_DMIDA),y)
3847 + # DMIDA does not connect the HD64465 PS/2 keyboard port
3848 + # but we allow for USB keyboards to be plugged in.
3849 + KEYMAP = defkeymap.o
3850 + KEYBD = # hd64465_keyb.o pc_keyb.o
3851 + CONSOLE = console.o
3852 + endif
3853 + ifeq ($(CONFIG_SH_EC3104),y)
3854 + KEYMAP = defkeymap.o
3855 + KEYBD = ec3104_keyb.o
3856 + CONSOLE = console.o
3857 + endif
3858 + ifeq ($(CONFIG_SH_DREAMCAST),y)
3859 + KEYMAP = defkeymap.o
3860 + KEYBD =
3861 + CONSOLE = console.o
3862 + endif
3863 +endif
3864 +
3865 +ifeq ($(CONFIG_DECSTATION),y)
3866 + KEYMAP =
3867 + KEYBD =
3868 +endif
3869 +
3870 +ifeq ($(CONFIG_BAGET_MIPS),y)
3871 + KEYBD =
3872 + SERIAL = vac-serial.o
3873 +endif
3874 +
3875 +ifeq ($(CONFIG_NINO),y)
3876 + SERIAL =
3877 +endif
3878 +
3879 +ifneq ($(CONFIG_SUN_SERIAL),)
3880 + SERIAL =
3881 +endif
3882 +
3883 +ifeq ($(CONFIG_QTRONIX_KEYBOARD),y)
3884 + KEYBD = qtronix.o
3885 + KEYMAP = qtronixmap.o
3886 +endif
3887 +
3888 +ifeq ($(CONFIG_DUMMY_KEYB),y)
3889 + KEYBD = dummy_keyb.o
3890 +endif
3891 +
3892 +obj-$(CONFIG_VT) += vt.o vc_screen.o consolemap.o consolemap_deftbl.o $(CONSOLE) selection.o
3893 +obj-$(CONFIG_SERIAL) += $(SERIAL)
3894 +obj-$(CONFIG_PARPORT_SERIAL) += parport_serial.o
3895 +obj-$(CONFIG_SERIAL_HCDP) += hcdp_serial.o
3896 +obj-$(CONFIG_SERIAL_21285) += serial_21285.o
3897 +obj-$(CONFIG_SERIAL_SA1100) += serial_sa1100.o
3898 +obj-$(CONFIG_SERIAL_AMBA) += serial_amba.o
3899 +obj-$(CONFIG_TS_AU1X00_ADS7846) += au1000_ts.o
3900 +obj-$(CONFIG_SERIAL_DEC) += decserial.o
3901 +
3902 +ifndef CONFIG_SUN_KEYBOARD
3903 + obj-$(CONFIG_VT) += keyboard.o $(KEYMAP) $(KEYBD)
3904 +else
3905 + obj-$(CONFIG_PCI) += keyboard.o $(KEYMAP)
3906 +endif
3907 +
3908 +obj-$(CONFIG_HIL) += hp_keyb.o
3909 +obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
3910 +obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
3911 +obj-$(CONFIG_ROCKETPORT) += rocket.o
3912 +obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
3913 +obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
3914 +obj-$(CONFIG_DIGI) += pcxx.o
3915 +obj-$(CONFIG_DIGIEPCA) += epca.o
3916 +obj-$(CONFIG_CYCLADES) += cyclades.o
3917 +obj-$(CONFIG_STALLION) += stallion.o
3918 +obj-$(CONFIG_ISTALLION) += istallion.o
3919 +obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
3920 +obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o
3921 +obj-$(CONFIG_RISCOM8) += riscom8.o
3922 +obj-$(CONFIG_ISI) += isicom.o
3923 +obj-$(CONFIG_ESPSERIAL) += esp.o
3924 +obj-$(CONFIG_SYNCLINK) += synclink.o
3925 +obj-$(CONFIG_SYNCLINKMP) += synclinkmp.o
3926 +obj-$(CONFIG_N_HDLC) += n_hdlc.o
3927 +obj-$(CONFIG_SPECIALIX) += specialix.o
3928 +obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
3929 +obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
3930 +obj-$(CONFIG_SX) += sx.o generic_serial.o
3931 +obj-$(CONFIG_RIO) += rio/rio.o generic_serial.o
3932 +obj-$(CONFIG_SH_SCI) += sh-sci.o generic_serial.o
3933 +obj-$(CONFIG_SERIAL167) += serial167.o
3934 +obj-$(CONFIG_MVME147_SCC) += generic_serial.o vme_scc.o
3935 +obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o
3936 +obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o
3937 +obj-$(CONFIG_HVC_CONSOLE) += hvc_console.o
3938 +obj-$(CONFIG_SERIAL_TX3912) += generic_serial.o serial_tx3912.o
3939 +obj-$(CONFIG_TXX927_SERIAL) += serial_txx927.o
3940 +obj-$(CONFIG_SERIAL_TXX9) += generic_serial.o serial_txx9.o
3941 +obj-$(CONFIG_IP22_SERIAL) += sgiserial.o
3942 +obj-$(CONFIG_AU1X00_UART) += au1x00-serial.o
3943 +obj-$(CONFIG_SGI_L1_SERIAL) += sn_serial.o
3944 +
3945 +subdir-$(CONFIG_RIO) += rio
3946 +subdir-$(CONFIG_INPUT) += joystick
3947 +
3948 +obj-$(CONFIG_ATIXL_BUSMOUSE) += atixlmouse.o
3949 +obj-$(CONFIG_LOGIBUSMOUSE) += logibusmouse.o
3950 +obj-$(CONFIG_PRINTER) += lp.o
3951 +obj-$(CONFIG_TIPAR) += tipar.o
3952 +obj-$(CONFIG_OBMOUSE) += obmouse.o
3953 +
3954 +ifeq ($(CONFIG_INPUT),y)
3955 +obj-y += joystick/js.o
3956 +endif
3957 +
3958 +#
3959 +# Texas Intruments VLYNQ driver
3960 +#
3961 +
3962 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
3963 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
3964 +
3965 +obj-$(CONFIG_FETCHOP) += fetchop.o
3966 +obj-$(CONFIG_BUSMOUSE) += busmouse.o
3967 +obj-$(CONFIG_DTLK) += dtlk.o
3968 +obj-$(CONFIG_R3964) += n_r3964.o
3969 +obj-$(CONFIG_APPLICOM) += applicom.o
3970 +obj-$(CONFIG_SONYPI) += sonypi.o
3971 +obj-$(CONFIG_MS_BUSMOUSE) += msbusmouse.o
3972 +obj-$(CONFIG_82C710_MOUSE) += qpmouse.o
3973 +obj-$(CONFIG_AMIGAMOUSE) += amigamouse.o
3974 +obj-$(CONFIG_ATARIMOUSE) += atarimouse.o
3975 +obj-$(CONFIG_ADBMOUSE) += adbmouse.o
3976 +obj-$(CONFIG_PC110_PAD) += pc110pad.o
3977 +obj-$(CONFIG_MK712_MOUSE) += mk712.o
3978 +obj-$(CONFIG_RTC) += rtc.o
3979 +obj-$(CONFIG_GEN_RTC) += genrtc.o
3980 +obj-$(CONFIG_EFI_RTC) += efirtc.o
3981 +obj-$(CONFIG_MIPS_RTC) += mips_rtc.o
3982 +obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
3983 +ifeq ($(CONFIG_PPC),)
3984 + obj-$(CONFIG_NVRAM) += nvram.o
3985 +endif
3986 +obj-$(CONFIG_TOSHIBA) += toshiba.o
3987 +obj-$(CONFIG_I8K) += i8k.o
3988 +obj-$(CONFIG_DS1286) += ds1286.o
3989 +obj-$(CONFIG_DS1620) += ds1620.o
3990 +obj-$(CONFIG_DS1742) += ds1742.o
3991 +obj-$(CONFIG_INTEL_RNG) += i810_rng.o
3992 +obj-$(CONFIG_AMD_RNG) += amd768_rng.o
3993 +obj-$(CONFIG_HW_RANDOM) += hw_random.o
3994 +obj-$(CONFIG_AMD_PM768) += amd76x_pm.o
3995 +obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o
3996 +
3997 +obj-$(CONFI