split kernel patches into board dependend and generic
[openwrt/svn-archive/archive.git] / openwrt / target / linux / linux-2.4 / patches / brcm / 001-bcm47xx.patch
1 diff -Nur linux-2.4.30/arch/mips/bcm947xx/compressed/Makefile linux-2.4.30-brcm/arch/mips/bcm947xx/compressed/Makefile
2 --- linux-2.4.30/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/compressed/Makefile 2005-05-26 03:29:22.000000000 +0200
4 @@ -0,0 +1,33 @@
5 +#
6 +# Makefile for Broadcom BCM947XX boards
7 +#
8 +# Copyright 2001-2003, Broadcom Corporation
9 +# All Rights Reserved.
10 +#
11 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 +#
16 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
17 +#
18 +
19 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
20 +SYSTEM ?= $(TOPDIR)/vmlinux
21 +
22 +all: vmlinuz
23 +
24 +# Don't build dependencies, this may die if $(CC) isn't gcc
25 +dep:
26 +
27 +# Create a gzipped version named vmlinuz for compatibility
28 +vmlinuz: piggy
29 + gzip -c9 $< > $@
30 +
31 +piggy: $(SYSTEM)
32 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
33 +
34 +mrproper: clean
35 +
36 +clean:
37 + rm -f vmlinuz piggy
38 diff -Nur linux-2.4.30/arch/mips/bcm947xx/generic/int-handler.S linux-2.4.30-brcm/arch/mips/bcm947xx/generic/int-handler.S
39 --- linux-2.4.30/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
40 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/generic/int-handler.S 2005-05-22 22:55:51.000000000 +0200
41 @@ -0,0 +1,51 @@
42 +/*
43 + * Generic interrupt handler for Broadcom MIPS boards
44 + *
45 + * Copyright 2004, Broadcom Corporation
46 + * All Rights Reserved.
47 + *
48 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
49 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
50 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
51 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
52 + *
53 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
54 + */
55 +
56 +#include <linux/config.h>
57 +
58 +#include <asm/asm.h>
59 +#include <asm/mipsregs.h>
60 +#include <asm/regdef.h>
61 +#include <asm/stackframe.h>
62 +
63 +/*
64 + * MIPS IRQ Source
65 + * -------- ------
66 + * 0 Software (ignored)
67 + * 1 Software (ignored)
68 + * 2 Combined hardware interrupt (hw0)
69 + * 3 Hardware
70 + * 4 Hardware
71 + * 5 Hardware
72 + * 6 Hardware
73 + * 7 R4k timer
74 + */
75 +
76 + .text
77 + .set noreorder
78 + .set noat
79 + .align 5
80 + NESTED(brcmIRQ, PT_SIZE, sp)
81 + SAVE_ALL
82 + CLI
83 + .set at
84 + .set noreorder
85 +
86 + jal brcm_irq_dispatch
87 + move a0, sp
88 +
89 + j ret_from_irq
90 + nop
91 +
92 + END(brcmIRQ)
93 diff -Nur linux-2.4.30/arch/mips/bcm947xx/generic/irq.c linux-2.4.30-brcm/arch/mips/bcm947xx/generic/irq.c
94 --- linux-2.4.30/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
95 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/generic/irq.c 2005-05-22 22:55:51.000000000 +0200
96 @@ -0,0 +1,130 @@
97 +/*
98 + * Generic interrupt control functions for Broadcom MIPS boards
99 + *
100 + * Copyright 2004, Broadcom Corporation
101 + * All Rights Reserved.
102 + *
103 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
104 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
105 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
106 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
107 + *
108 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
109 + */
110 +
111 +#include <linux/config.h>
112 +#include <linux/init.h>
113 +#include <linux/kernel.h>
114 +#include <linux/types.h>
115 +#include <linux/interrupt.h>
116 +#include <linux/irq.h>
117 +
118 +#include <asm/irq.h>
119 +#include <asm/mipsregs.h>
120 +#include <asm/gdb-stub.h>
121 +
122 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
123 +
124 +extern asmlinkage void brcmIRQ(void);
125 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
126 +
127 +void
128 +brcm_irq_dispatch(struct pt_regs *regs)
129 +{
130 + u32 cause;
131 +
132 + cause = read_c0_cause() &
133 + read_c0_status() &
134 + CAUSEF_IP;
135 +
136 +#ifdef CONFIG_KERNPROF
137 + change_c0_status(cause | 1, 1);
138 +#else
139 + clear_c0_status(cause);
140 +#endif
141 +
142 + if (cause & CAUSEF_IP7)
143 + do_IRQ(7, regs);
144 + if (cause & CAUSEF_IP2)
145 + do_IRQ(2, regs);
146 + if (cause & CAUSEF_IP3)
147 + do_IRQ(3, regs);
148 + if (cause & CAUSEF_IP4)
149 + do_IRQ(4, regs);
150 + if (cause & CAUSEF_IP5)
151 + do_IRQ(5, regs);
152 + if (cause & CAUSEF_IP6)
153 + do_IRQ(6, regs);
154 +}
155 +
156 +static void
157 +enable_brcm_irq(unsigned int irq)
158 +{
159 + if (irq < 8)
160 + set_c0_status(1 << (irq + 8));
161 + else
162 + set_c0_status(IE_IRQ0);
163 +}
164 +
165 +static void
166 +disable_brcm_irq(unsigned int irq)
167 +{
168 + if (irq < 8)
169 + clear_c0_status(1 << (irq + 8));
170 + else
171 + clear_c0_status(IE_IRQ0);
172 +}
173 +
174 +static void
175 +ack_brcm_irq(unsigned int irq)
176 +{
177 + /* Already done in brcm_irq_dispatch */
178 +}
179 +
180 +static unsigned int
181 +startup_brcm_irq(unsigned int irq)
182 +{
183 + enable_brcm_irq(irq);
184 +
185 + return 0; /* never anything pending */
186 +}
187 +
188 +static void
189 +end_brcm_irq(unsigned int irq)
190 +{
191 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
192 + enable_brcm_irq(irq);
193 +}
194 +
195 +static struct hw_interrupt_type brcm_irq_type = {
196 + typename: "MIPS",
197 + startup: startup_brcm_irq,
198 + shutdown: disable_brcm_irq,
199 + enable: enable_brcm_irq,
200 + disable: disable_brcm_irq,
201 + ack: ack_brcm_irq,
202 + end: end_brcm_irq,
203 + NULL
204 +};
205 +
206 +void __init
207 +init_IRQ(void)
208 +{
209 + int i;
210 +
211 + for (i = 0; i < NR_IRQS; i++) {
212 + irq_desc[i].status = IRQ_DISABLED;
213 + irq_desc[i].action = 0;
214 + irq_desc[i].depth = 1;
215 + irq_desc[i].handler = &brcm_irq_type;
216 + }
217 +
218 + set_except_vector(0, brcmIRQ);
219 + change_c0_status(ST0_IM, ALLINTS);
220 +
221 +#ifdef CONFIG_REMOTE_DEBUG
222 + printk("Breaking into debugger...\n");
223 + set_debug_traps();
224 + breakpoint();
225 +#endif
226 +}
227 diff -Nur linux-2.4.30/arch/mips/bcm947xx/generic/Makefile linux-2.4.30-brcm/arch/mips/bcm947xx/generic/Makefile
228 --- linux-2.4.30/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
229 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/generic/Makefile 2005-05-25 18:53:41.000000000 +0200
230 @@ -0,0 +1,15 @@
231 +#
232 +# Makefile for the BCM947xx specific kernel interface routines
233 +# under Linux.
234 +#
235 +
236 +.S.s:
237 + $(CPP) $(AFLAGS) $< -o $*.s
238 +.S.o:
239 + $(CC) $(AFLAGS) -c $< -o $*.o
240 +
241 +O_TARGET := brcm.o
242 +
243 +obj-y := int-handler.o irq.o
244 +
245 +include $(TOPDIR)/Rules.make
246 diff -Nur linux-2.4.30/arch/mips/bcm947xx/gpio.c linux-2.4.30-brcm/arch/mips/bcm947xx/gpio.c
247 --- linux-2.4.30/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
248 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/gpio.c 2005-05-22 22:55:51.000000000 +0200
249 @@ -0,0 +1,158 @@
250 +/*
251 + * GPIO char driver
252 + *
253 + * Copyright 2004, Broadcom Corporation
254 + * All Rights Reserved.
255 + *
256 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
257 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
258 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
259 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
260 + *
261 + * $Id: gpio.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
262 + */
263 +
264 +#include <linux/module.h>
265 +#include <linux/init.h>
266 +#include <linux/fs.h>
267 +#include <linux/miscdevice.h>
268 +#include <asm/uaccess.h>
269 +
270 +#include <typedefs.h>
271 +#include <bcmutils.h>
272 +#include <sbutils.h>
273 +#include <bcmdevs.h>
274 +
275 +static void *gpio_sbh;
276 +static int gpio_major;
277 +static devfs_handle_t gpio_dir;
278 +static struct {
279 + char *name;
280 + devfs_handle_t handle;
281 +} gpio_file[] = {
282 + { "in", NULL },
283 + { "out", NULL },
284 + { "outen", NULL },
285 + { "control", NULL }
286 +};
287 +
288 +static int
289 +gpio_open(struct inode *inode, struct file * file)
290 +{
291 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
292 + return -ENODEV;
293 +
294 + MOD_INC_USE_COUNT;
295 + return 0;
296 +}
297 +
298 +static int
299 +gpio_release(struct inode *inode, struct file * file)
300 +{
301 + MOD_DEC_USE_COUNT;
302 + return 0;
303 +}
304 +
305 +static ssize_t
306 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
307 +{
308 + u32 val;
309 +
310 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
311 + case 0:
312 + val = sb_gpioin(gpio_sbh);
313 + break;
314 + case 1:
315 + val = sb_gpioout(gpio_sbh, 0, 0);
316 + break;
317 + case 2:
318 + val = sb_gpioouten(gpio_sbh, 0, 0);
319 + break;
320 + case 3:
321 + val = sb_gpiocontrol(gpio_sbh, 0, 0);
322 + break;
323 + default:
324 + return -ENODEV;
325 + }
326 +
327 + if (put_user(val, (u32 *) buf))
328 + return -EFAULT;
329 +
330 + return sizeof(val);
331 +}
332 +
333 +static ssize_t
334 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
335 +{
336 + u32 val;
337 +
338 + if (get_user(val, (u32 *) buf))
339 + return -EFAULT;
340 +
341 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
342 + case 0:
343 + return -EACCES;
344 + case 1:
345 + sb_gpioout(gpio_sbh, ~0, val);
346 + break;
347 + case 2:
348 + sb_gpioouten(gpio_sbh, ~0, val);
349 + break;
350 + case 3:
351 + sb_gpiocontrol(gpio_sbh, ~0, val);
352 + break;
353 + default:
354 + return -ENODEV;
355 + }
356 +
357 + return sizeof(val);
358 +}
359 +
360 +static struct file_operations gpio_fops = {
361 + owner: THIS_MODULE,
362 + open: gpio_open,
363 + release: gpio_release,
364 + read: gpio_read,
365 + write: gpio_write,
366 +};
367 +
368 +static int __init
369 +gpio_init(void)
370 +{
371 + int i;
372 +
373 + if (!(gpio_sbh = sb_kattach()))
374 + return -ENODEV;
375 +
376 + sb_gpiosetcore(gpio_sbh);
377 +
378 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
379 + return gpio_major;
380 +
381 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
382 +
383 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
384 + gpio_file[i].handle = devfs_register(gpio_dir,
385 + gpio_file[i].name,
386 + DEVFS_FL_DEFAULT, gpio_major, i,
387 + S_IFCHR | S_IRUGO | S_IWUGO,
388 + &gpio_fops, NULL);
389 + }
390 +
391 + return 0;
392 +}
393 +
394 +static void __exit
395 +gpio_exit(void)
396 +{
397 + int i;
398 +
399 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
400 + devfs_unregister(gpio_file[i].handle);
401 + devfs_unregister(gpio_dir);
402 + devfs_unregister_chrdev(gpio_major, "gpio");
403 + sb_detach(gpio_sbh);
404 +}
405 +
406 +module_init(gpio_init);
407 +module_exit(gpio_exit);
408 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmdevs.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmdevs.h
409 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
410 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmdevs.h 2005-05-25 20:30:26.000000000 +0200
411 @@ -0,0 +1,369 @@
412 +/*
413 + * Broadcom device-specific manifest constants.
414 + *
415 + * Copyright 2005, Broadcom Corporation
416 + * All Rights Reserved.
417 + *
418 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
419 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
420 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
421 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
422 + * $Id$
423 + */
424 +
425 +#ifndef _BCMDEVS_H
426 +#define _BCMDEVS_H
427 +
428 +
429 +/* Known PCI vendor Id's */
430 +#define VENDOR_EPIGRAM 0xfeda
431 +#define VENDOR_BROADCOM 0x14e4
432 +#define VENDOR_3COM 0x10b7
433 +#define VENDOR_NETGEAR 0x1385
434 +#define VENDOR_DIAMOND 0x1092
435 +#define VENDOR_DELL 0x1028
436 +#define VENDOR_HP 0x0e11
437 +#define VENDOR_APPLE 0x106b
438 +
439 +/* PCI Device Id's */
440 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
441 +#define BCM4211_DEVICE_ID 0x4211
442 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
443 +#define BCM4231_DEVICE_ID 0x4231
444 +
445 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
446 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
447 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
448 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
449 +
450 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
451 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
452 +
453 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
454 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
455 +
456 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
457 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
458 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
459 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
460 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
461 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
462 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
463 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
464 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
465 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
466 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
467 +
468 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
469 +
470 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
471 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
472 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
473 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
474 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
475 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
476 +
477 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
478 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
479 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
480 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
481 +
482 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
483 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
484 +
485 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
486 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
487 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
488 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
489 +
490 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
491 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
492 +#define BCM4306_D11G_ID2 0x4325
493 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
494 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
495 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
496 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
497 +
498 +#define BCM4309_PKG_ID 1 /* 4309 package id */
499 +
500 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
501 +#define BCM4303_PKG_ID 2 /* 4303 package id */
502 +
503 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
504 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
505 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
506 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
507 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
508 +
509 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
510 +
511 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
512 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
513 +
514 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
515 +
516 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
517 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
518 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
519 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
520 +
521 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
522 +
523 +/* Address map */
524 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
525 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
526 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
527 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
528 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
529 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
530 +
531 +/* Core register space */
532 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
533 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
534 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
535 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
536 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
537 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
538 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
539 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
540 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
541 +
542 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
543 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
544 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
545 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
546 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
547 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
548 +
549 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
550 +
551 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
552 +
553 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
554 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
555 +
556 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
557 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
558 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
559 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
560 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
561 +
562 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
563 +
564 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
565 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
566 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
567 +
568 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
569 +
570 +/* PCMCIA vendor Id's */
571 +
572 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
573 +
574 +/* SDIO vendor Id's */
575 +#define VENDOR_BROADCOM_SDIO 0x00BF
576 +
577 +
578 +/* boardflags */
579 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
580 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
581 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
582 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
583 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
584 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
585 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
586 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
587 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
588 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
589 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
590 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
591 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
592 +
593 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
594 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
595 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
596 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
597 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
598 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
599 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
600 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
601 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
602 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
603 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
604 +
605 +/* Bus types */
606 +#define SB_BUS 0 /* Silicon Backplane */
607 +#define PCI_BUS 1 /* PCI target */
608 +#define PCMCIA_BUS 2 /* PCMCIA target */
609 +#define SDIO_BUS 3 /* SDIO target */
610 +#define JTAG_BUS 4 /* JTAG */
611 +
612 +/* Allows optimization for single-bus support */
613 +#ifdef BCMBUSTYPE
614 +#define BUSTYPE(bus) (BCMBUSTYPE)
615 +#else
616 +#define BUSTYPE(bus) (bus)
617 +#endif
618 +
619 +/* power control defines */
620 +#define PLL_DELAY 150 /* 150us pll on delay */
621 +#define FREF_DELAY 200 /* 200us fref change delay */
622 +#define MIN_SLOW_CLK 32 /* 32us Slow clock period */
623 +
624 +/* Reference Board Types */
625 +
626 +#define BU4710_BOARD 0x0400
627 +#define VSIM4710_BOARD 0x0401
628 +#define QT4710_BOARD 0x0402
629 +
630 +#define BU4610_BOARD 0x0403
631 +#define VSIM4610_BOARD 0x0404
632 +
633 +#define BU4307_BOARD 0x0405
634 +#define BCM94301CB_BOARD 0x0406
635 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
636 +#define BCM94301MP_BOARD 0x0407
637 +#define BCM94307MP_BOARD 0x0408
638 +#define BCMAP4307_BOARD 0x0409
639 +
640 +#define BU4309_BOARD 0x040a
641 +#define BCM94309CB_BOARD 0x040b
642 +#define BCM94309MP_BOARD 0x040c
643 +#define BCM4309AP_BOARD 0x040d
644 +
645 +#define BCM94302MP_BOARD 0x040e
646 +
647 +#define VSIM4310_BOARD 0x040f
648 +#define BU4711_BOARD 0x0410
649 +#define BCM94310U_BOARD 0x0411
650 +#define BCM94310AP_BOARD 0x0412
651 +#define BCM94310MP_BOARD 0x0414
652 +
653 +#define BU4306_BOARD 0x0416
654 +#define BCM94306CB_BOARD 0x0417
655 +#define BCM94306MP_BOARD 0x0418
656 +
657 +#define BCM94710D_BOARD 0x041a
658 +#define BCM94710R1_BOARD 0x041b
659 +#define BCM94710R4_BOARD 0x041c
660 +#define BCM94710AP_BOARD 0x041d
661 +
662 +
663 +#define BU2050_BOARD 0x041f
664 +
665 +
666 +#define BCM94309G_BOARD 0x0421
667 +
668 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
669 +
670 +#define BU4704_BOARD 0x0423
671 +#define BU4702_BOARD 0x0424
672 +
673 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
674 +
675 +#define BU4317_BOARD 0x0426
676 +
677 +
678 +#define BCM94702MN_BOARD 0x0428
679 +
680 +/* BCM4702 1U CompactPCI Board */
681 +#define BCM94702CPCI_BOARD 0x0429
682 +
683 +/* BCM4702 with BCM95380 VLAN Router */
684 +#define BCM95380RR_BOARD 0x042a
685 +
686 +/* cb4306 with SiGe PA */
687 +#define BCM94306CBSG_BOARD 0x042b
688 +
689 +/* mp4301 with 2050 radio */
690 +#define BCM94301MPL_BOARD 0x042c
691 +
692 +/* cb4306 with SiGe PA */
693 +#define PCSG94306_BOARD 0x042d
694 +
695 +/* bu4704 with sdram */
696 +#define BU4704SD_BOARD 0x042e
697 +
698 +/* Dual 11a/11g Router */
699 +#define BCM94704AGR_BOARD 0x042f
700 +
701 +/* 11a-only minipci */
702 +#define BCM94308MP_BOARD 0x0430
703 +
704 +
705 +
706 +/* BCM94317 boards */
707 +#define BCM94317CB_BOARD 0x0440
708 +#define BCM94317MP_BOARD 0x0441
709 +#define BCM94317PCMCIA_BOARD 0x0442
710 +#define BCM94317SDIO_BOARD 0x0443
711 +
712 +#define BU4712_BOARD 0x0444
713 +#define BU4712SD_BOARD 0x045d
714 +#define BU4712L_BOARD 0x045f
715 +
716 +/* BCM4712 boards */
717 +#define BCM94712AP_BOARD 0x0445
718 +#define BCM94712P_BOARD 0x0446
719 +
720 +/* BCM4318 boards */
721 +#define BU4318_BOARD 0x0447
722 +#define CB4318_BOARD 0x0448
723 +#define MPG4318_BOARD 0x0449
724 +#define MP4318_BOARD 0x044a
725 +#define SD4318_BOARD 0x044b
726 +
727 +/* Another mp4306 with SiGe */
728 +#define BCM94306P_BOARD 0x044c
729 +
730 +/* CF-like 4317 modules */
731 +#define BCM94317CF_BOARD 0x044d
732 +
733 +/* mp4303 */
734 +#define BCM94303MP_BOARD 0x044e
735 +
736 +/* mpsgh4306 */
737 +#define BCM94306MPSGH_BOARD 0x044f
738 +
739 +/* BRCM 4306 w/ Front End Modules */
740 +#define BCM94306MPM 0x0450
741 +#define BCM94306MPL 0x0453
742 +
743 +/* 4712agr */
744 +#define BCM94712AGR_BOARD 0x0451
745 +
746 +/* The real CF 4317 board */
747 +#define CFI4317_BOARD 0x0452
748 +
749 +/* pcmcia 4303 */
750 +#define PC4303_BOARD 0x0454
751 +
752 +/* 5350K */
753 +#define BCM95350K_BOARD 0x0455
754 +
755 +/* 5350R */
756 +#define BCM95350R_BOARD 0x0456
757 +
758 +/* 4306mplna */
759 +#define BCM94306MPLNA_BOARD 0x0457
760 +
761 +
762 +/* 4306mph */
763 +#define BCM94306MPH_BOARD 0x045b
764 +
765 +/* 4306pciv */
766 +#define BCM94306PCIV_BOARD 0x045c
767 +
768 +#define BU4712SD_BOARD 0x045d
769 +
770 +
771 +#define BU4712L_BOARD 0x045f
772 +#define BCM94712LGR_BOARD 0x0460
773 +
774 +#define BU5352_BOARD 0x0462
775 +#define BCM95352GR_BOARD 0x0467
776 +
777 +/* # of GPIO pins */
778 +#define GPIO_NUMPINS 16
779 +
780 +#endif /* _BCMDEVS_H */
781 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmendian.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmendian.h
782 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
783 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmendian.h 2005-02-02 23:16:39.000000000 +0100
784 @@ -0,0 +1,168 @@
785 +/*
786 + * local version of endian.h - byte order defines
787 + *
788 + * Copyright 2005, Broadcom Corporation
789 + * All Rights Reserved.
790 + *
791 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
792 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
793 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
794 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
795 + *
796 + * $Id$
797 +*/
798 +
799 +#ifndef _BCMENDIAN_H_
800 +#define _BCMENDIAN_H_
801 +
802 +#include <typedefs.h>
803 +
804 +/* Byte swap a 16 bit value */
805 +#define BCMSWAP16(val) \
806 + ((uint16)( \
807 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
808 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
809 +
810 +/* Byte swap a 32 bit value */
811 +#define BCMSWAP32(val) \
812 + ((uint32)( \
813 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
814 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
815 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
816 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
817 +
818 +static INLINE uint16
819 +bcmswap16(uint16 val)
820 +{
821 + return BCMSWAP16(val);
822 +}
823 +
824 +static INLINE uint32
825 +bcmswap32(uint32 val)
826 +{
827 + return BCMSWAP32(val);
828 +}
829 +
830 +/* buf - start of buffer of shorts to swap */
831 +/* len - byte length of buffer */
832 +static INLINE void
833 +bcmswap16_buf(uint16 *buf, uint len)
834 +{
835 + len = len/2;
836 +
837 + while(len--){
838 + *buf = bcmswap16(*buf);
839 + buf++;
840 + }
841 +}
842 +
843 +#ifndef hton16
844 +#ifndef IL_BIGENDIAN
845 +#define HTON16(i) BCMSWAP16(i)
846 +#define hton16(i) bcmswap16(i)
847 +#define hton32(i) bcmswap32(i)
848 +#define ntoh16(i) bcmswap16(i)
849 +#define ntoh32(i) bcmswap32(i)
850 +#define ltoh16(i) (i)
851 +#define ltoh32(i) (i)
852 +#define htol16(i) (i)
853 +#define htol32(i) (i)
854 +#else
855 +#define HTON16(i) (i)
856 +#define hton16(i) (i)
857 +#define hton32(i) (i)
858 +#define ntoh16(i) (i)
859 +#define ntoh32(i) (i)
860 +#define ltoh16(i) bcmswap16(i)
861 +#define ltoh32(i) bcmswap32(i)
862 +#define htol16(i) bcmswap16(i)
863 +#define htol32(i) bcmswap32(i)
864 +#endif
865 +#endif
866 +
867 +#ifndef IL_BIGENDIAN
868 +#define ltoh16_buf(buf, i)
869 +#define htol16_buf(buf, i)
870 +#else
871 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
872 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
873 +#endif
874 +
875 +/*
876 +* load 16-bit value from unaligned little endian byte array.
877 +*/
878 +static INLINE uint16
879 +ltoh16_ua(uint8 *bytes)
880 +{
881 + return (bytes[1]<<8)+bytes[0];
882 +}
883 +
884 +/*
885 +* load 32-bit value from unaligned little endian byte array.
886 +*/
887 +static INLINE uint32
888 +ltoh32_ua(uint8 *bytes)
889 +{
890 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
891 +}
892 +
893 +/*
894 +* load 16-bit value from unaligned big(network) endian byte array.
895 +*/
896 +static INLINE uint16
897 +ntoh16_ua(uint8 *bytes)
898 +{
899 + return (bytes[0]<<8)+bytes[1];
900 +}
901 +
902 +/*
903 +* load 32-bit value from unaligned big(network) endian byte array.
904 +*/
905 +static INLINE uint32
906 +ntoh32_ua(uint8 *bytes)
907 +{
908 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
909 +}
910 +
911 +/* get_ua adapted from Linux asm-mips/unaligned.h */
912 +#ifdef IL_BIGENDIAN
913 +#define get_ua(ptr) \
914 +({ \
915 + __typeof__(*(ptr)) __val; \
916 + \
917 + switch (sizeof(*(ptr))) { \
918 + case 1: \
919 + __val = *(uint8 *)ptr; \
920 + break; \
921 + case 2: \
922 + __val = ntoh16_ua((uint8 *)ptr); \
923 + break; \
924 + case 4: \
925 + __val = ntoh32_ua((uint8 *)ptr); \
926 + break; \
927 + } \
928 + \
929 + __val; \
930 +})
931 +#else
932 +#define get_ua(ptr) \
933 +({ \
934 + __typeof__(*(ptr)) __val; \
935 + \
936 + switch (sizeof(*(ptr))) { \
937 + case 1: \
938 + __val = *(uint8 *)ptr; \
939 + break; \
940 + case 2: \
941 + __val = ltoh16_ua((uint8 *)ptr); \
942 + break; \
943 + case 4: \
944 + __val = ltoh32_ua((uint8 *)ptr); \
945 + break; \
946 + } \
947 + \
948 + __val; \
949 +})
950 +#endif
951 +
952 +#endif /* _BCMENDIAN_H_ */
953 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmenet47xx.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h
954 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
955 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-02-02 23:16:39.000000000 +0100
956 @@ -0,0 +1,229 @@
957 +/*
958 + * Hardware-specific definitions for
959 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
960 + *
961 + * Copyright 2005, Broadcom Corporation
962 + * All Rights Reserved.
963 + *
964 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
965 + * the contents of this file may not be disclosed to third parties, copied
966 + * or duplicated in any form, in whole or in part, without the prior
967 + * written permission of Broadcom Corporation.
968 + * $Id$
969 + */
970 +
971 +#ifndef _bcmenet_47xx_h_
972 +#define _bcmenet_47xx_h_
973 +
974 +#include <bcmenetmib.h>
975 +#include <bcmenetrxh.h>
976 +#include <bcmenetphy.h>
977 +
978 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
979 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
980 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
981 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
982 +
983 +/* power management event wakeup pattern constants */
984 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
985 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
986 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
987 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
988 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
989 +
990 +/* cpp contortions to concatenate w/arg prescan */
991 +#ifndef PAD
992 +#define _PADLINE(line) pad ## line
993 +#define _XSTR(line) _PADLINE(line)
994 +#define PAD _XSTR(__LINE__)
995 +#endif /* PAD */
996 +
997 +/*
998 + * Host Interface Registers
999 + */
1000 +typedef volatile struct _bcmenettregs {
1001 + /* Device and Power Control */
1002 + uint32 devcontrol;
1003 + uint32 PAD[2];
1004 + uint32 biststatus;
1005 + uint32 wakeuplength;
1006 + uint32 PAD[3];
1007 +
1008 + /* Interrupt Control */
1009 + uint32 intstatus;
1010 + uint32 intmask;
1011 + uint32 gptimer;
1012 + uint32 PAD[23];
1013 +
1014 + /* Ethernet MAC Address Filtering Control */
1015 + uint32 PAD[2];
1016 + uint32 enetftaddr;
1017 + uint32 enetftdata;
1018 + uint32 PAD[2];
1019 +
1020 + /* Ethernet MAC Control */
1021 + uint32 emactxmaxburstlen;
1022 + uint32 emacrxmaxburstlen;
1023 + uint32 emaccontrol;
1024 + uint32 emacflowcontrol;
1025 +
1026 + uint32 PAD[20];
1027 +
1028 + /* DMA Lazy Interrupt Control */
1029 + uint32 intrecvlazy;
1030 + uint32 PAD[63];
1031 +
1032 + /* DMA engine */
1033 + dmaregs_t dmaregs;
1034 + dmafifo_t dmafifo;
1035 + uint32 PAD[116];
1036 +
1037 + /* EMAC Registers */
1038 + uint32 rxconfig;
1039 + uint32 rxmaxlength;
1040 + uint32 txmaxlength;
1041 + uint32 PAD;
1042 + uint32 mdiocontrol;
1043 + uint32 mdiodata;
1044 + uint32 emacintmask;
1045 + uint32 emacintstatus;
1046 + uint32 camdatalo;
1047 + uint32 camdatahi;
1048 + uint32 camcontrol;
1049 + uint32 enetcontrol;
1050 + uint32 txcontrol;
1051 + uint32 txwatermark;
1052 + uint32 mibcontrol;
1053 + uint32 PAD[49];
1054 +
1055 + /* EMAC MIB counters */
1056 + bcmenetmib_t mib;
1057 +
1058 + uint32 PAD[585];
1059 +
1060 + /* Sonics SiliconBackplane config registers */
1061 + sbconfig_t sbconfig;
1062 +} bcmenetregs_t;
1063 +
1064 +/* device control */
1065 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
1066 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
1067 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
1068 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
1069 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
1070 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
1071 +#define DC_PA_SHIFT 18
1072 +#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
1073 +#define DC_FS_SHIFT 23
1074 +#define DC_FS_4K 0 /* 4Kbytes */
1075 +#define DC_FS_512 1 /* 512bytes */
1076 +
1077 +/* wakeup length */
1078 +#define WL_P0_MASK 0x7f /* pattern 0 */
1079 +#define WL_D0 ((uint32)1 << 7)
1080 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
1081 +#define WL_P1_SHIFT 8
1082 +#define WL_D1 ((uint32)1 << 15)
1083 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
1084 +#define WL_P2_SHIFT 16
1085 +#define WL_D2 ((uint32)1 << 23)
1086 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
1087 +#define WL_P3_SHIFT 24
1088 +#define WL_D3 ((uint32)1 << 31)
1089 +
1090 +/* intstatus and intmask */
1091 +#define I_PME ((uint32)1 << 6) /* power management event */
1092 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
1093 +#define I_PC ((uint32)1 << 10) /* descriptor error */
1094 +#define I_PD ((uint32)1 << 11) /* data error */
1095 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
1096 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
1097 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
1098 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
1099 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
1100 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
1101 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
1102 +#define I_MW ((uint32)1 << 27) /* mii write */
1103 +#define I_MR ((uint32)1 << 28) /* mii read */
1104 +
1105 +/* emaccontrol */
1106 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
1107 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
1108 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
1109 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
1110 +#define EMC_LC_SHIFT 5
1111 +
1112 +/* emacflowcontrol */
1113 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
1114 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
1115 +
1116 +/* interrupt receive lazy */
1117 +#define IRL_TO_MASK 0x00ffffff /* timeout */
1118 +#define IRL_FC_MASK 0xff000000 /* frame count */
1119 +#define IRL_FC_SHIFT 24 /* frame count */
1120 +
1121 +/* emac receive config */
1122 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
1123 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
1124 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
1125 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
1126 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
1127 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
1128 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
1129 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
1130 +#define ERC_CA ((uint32)1 << 8) /* cam absent */
1131 +
1132 +/* emac mdio control */
1133 +#define MC_MF_MASK 0x7f /* mdc frequency */
1134 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
1135 +
1136 +/* emac mdio data */
1137 +#define MD_DATA_MASK 0xffff /* r/w data */
1138 +#define MD_TA_MASK 0x30000 /* turnaround value */
1139 +#define MD_TA_SHIFT 16
1140 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
1141 +#define MD_RA_MASK 0x7c0000 /* register address */
1142 +#define MD_RA_SHIFT 18
1143 +#define MD_PMD_MASK 0xf800000 /* physical media device */
1144 +#define MD_PMD_SHIFT 23
1145 +#define MD_OP_MASK 0x30000000 /* opcode */
1146 +#define MD_OP_SHIFT 28
1147 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
1148 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
1149 +#define MD_SB_MASK 0xc0000000 /* start bits */
1150 +#define MD_SB_SHIFT 30
1151 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
1152 +
1153 +/* emac intstatus and intmask */
1154 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
1155 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
1156 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
1157 +
1158 +/* emac cam data high */
1159 +#define CD_V ((uint32)1 << 16) /* valid bit */
1160 +
1161 +/* emac cam control */
1162 +#define CC_CE ((uint32)1 << 0) /* cam enable */
1163 +#define CC_MS ((uint32)1 << 1) /* mask select */
1164 +#define CC_RD ((uint32)1 << 2) /* read */
1165 +#define CC_WR ((uint32)1 << 3) /* write */
1166 +#define CC_INDEX_MASK 0x3f0000 /* index */
1167 +#define CC_INDEX_SHIFT 16
1168 +#define CC_CB ((uint32)1 << 31) /* cam busy */
1169 +
1170 +/* emac ethernet control */
1171 +#define EC_EE ((uint32)1 << 0) /* emac enable */
1172 +#define EC_ED ((uint32)1 << 1) /* emac disable */
1173 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
1174 +#define EC_EP ((uint32)1 << 3) /* external phy select */
1175 +
1176 +/* emac transmit control */
1177 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
1178 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
1179 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
1180 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
1181 +
1182 +/* emac mib control */
1183 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
1184 +
1185 +#endif /* _bcmenet_47xx_h_ */
1186 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmenetmib.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetmib.h
1187 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
1188 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetmib.h 2005-02-02 23:16:39.000000000 +0100
1189 @@ -0,0 +1,81 @@
1190 +/*
1191 + * Hardware-specific MIB definition for
1192 + * Broadcom Home Networking Division
1193 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1194 + *
1195 + * Copyright 2005, Broadcom Corporation
1196 + * All Rights Reserved.
1197 + *
1198 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1199 + * the contents of this file may not be disclosed to third parties, copied
1200 + * or duplicated in any form, in whole or in part, without the prior
1201 + * written permission of Broadcom Corporation.
1202 + * $Id$
1203 + */
1204 +
1205 +#ifndef _bcmenetmib_h_
1206 +#define _bcmenetmib_h_
1207 +
1208 +/* cpp contortions to concatenate w/arg prescan */
1209 +#ifndef PAD
1210 +#define _PADLINE(line) pad ## line
1211 +#define _XSTR(line) _PADLINE(line)
1212 +#define PAD _XSTR(__LINE__)
1213 +#endif /* PAD */
1214 +
1215 +/*
1216 + * EMAC MIB Registers
1217 + */
1218 +typedef volatile struct {
1219 + uint32 tx_good_octets;
1220 + uint32 tx_good_pkts;
1221 + uint32 tx_octets;
1222 + uint32 tx_pkts;
1223 + uint32 tx_broadcast_pkts;
1224 + uint32 tx_multicast_pkts;
1225 + uint32 tx_len_64;
1226 + uint32 tx_len_65_to_127;
1227 + uint32 tx_len_128_to_255;
1228 + uint32 tx_len_256_to_511;
1229 + uint32 tx_len_512_to_1023;
1230 + uint32 tx_len_1024_to_max;
1231 + uint32 tx_jabber_pkts;
1232 + uint32 tx_oversize_pkts;
1233 + uint32 tx_fragment_pkts;
1234 + uint32 tx_underruns;
1235 + uint32 tx_total_cols;
1236 + uint32 tx_single_cols;
1237 + uint32 tx_multiple_cols;
1238 + uint32 tx_excessive_cols;
1239 + uint32 tx_late_cols;
1240 + uint32 tx_defered;
1241 + uint32 tx_carrier_lost;
1242 + uint32 tx_pause_pkts;
1243 + uint32 PAD[8];
1244 +
1245 + uint32 rx_good_octets;
1246 + uint32 rx_good_pkts;
1247 + uint32 rx_octets;
1248 + uint32 rx_pkts;
1249 + uint32 rx_broadcast_pkts;
1250 + uint32 rx_multicast_pkts;
1251 + uint32 rx_len_64;
1252 + uint32 rx_len_65_to_127;
1253 + uint32 rx_len_128_to_255;
1254 + uint32 rx_len_256_to_511;
1255 + uint32 rx_len_512_to_1023;
1256 + uint32 rx_len_1024_to_max;
1257 + uint32 rx_jabber_pkts;
1258 + uint32 rx_oversize_pkts;
1259 + uint32 rx_fragment_pkts;
1260 + uint32 rx_missed_pkts;
1261 + uint32 rx_crc_align_errs;
1262 + uint32 rx_undersize;
1263 + uint32 rx_crc_errs;
1264 + uint32 rx_align_errs;
1265 + uint32 rx_symbol_errs;
1266 + uint32 rx_pause_pkts;
1267 + uint32 rx_nonpause_pkts;
1268 +} bcmenetmib_t;
1269 +
1270 +#endif /* _bcmenetmib_h_ */
1271 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmenetphy.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetphy.h
1272 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
1273 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetphy.h 2005-02-02 23:16:39.000000000 +0100
1274 @@ -0,0 +1,58 @@
1275 +/*
1276 + * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
1277 + *
1278 + * Copyright 2005, Broadcom Corporation
1279 + * All Rights Reserved.
1280 + *
1281 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1282 + * the contents of this file may not be disclosed to third parties, copied
1283 + * or duplicated in any form, in whole or in part, without the prior
1284 + * written permission of Broadcom Corporation.
1285 + * $Id$
1286 + */
1287 +
1288 +#ifndef _bcmenetphy_h_
1289 +#define _bcmenetphy_h_
1290 +
1291 +/* phy address */
1292 +#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
1293 +#define EPHY_MASK 0x1f
1294 +#define EPHY_NONE 31 /* nvram: no phy present at all */
1295 +#define EPHY_NOREG 30 /* nvram: no local phy regs */
1296 +
1297 +/* just a few phy registers */
1298 +#define CTL_RESET (1 << 15) /* reset */
1299 +#define CTL_LOOP (1 << 14) /* loopback */
1300 +#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
1301 +#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
1302 +#define CTL_RESTART (1 << 9) /* restart autonegotiation */
1303 +#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
1304 +
1305 +#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
1306 +#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
1307 +#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
1308 +#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
1309 +
1310 +/* link partner ability register */
1311 +#define LPA_SLCT 0x001f /* same as advertise selector */
1312 +#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
1313 +#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
1314 +#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
1315 +#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
1316 +#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
1317 +#define LPA_RESV 0x1c00 /* unused */
1318 +#define LPA_RFAULT 0x2000 /* link partner faulted */
1319 +#define LPA_LPACK 0x4000 /* link partner acked us */
1320 +#define LPA_NPAGE 0x8000 /* next page bit */
1321 +
1322 +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
1323 +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
1324 +
1325 +#define STAT_REMFAULT (1 << 4) /* remote fault */
1326 +#define STAT_LINK (1 << 2) /* link status */
1327 +#define STAT_JAB (1 << 1) /* jabber detected */
1328 +#define AUX_FORCED (1 << 2) /* forced 10/100 */
1329 +#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
1330 +#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
1331 +
1332 +#endif /* _bcmenetphy_h_ */
1333 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmenetrxh.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h
1334 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
1335 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-02-02 23:16:39.000000000 +0100
1336 @@ -0,0 +1,43 @@
1337 +/*
1338 + * Hardware-specific Receive Data Header for the
1339 + * Broadcom Home Networking Division
1340 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1341 + *
1342 + * Copyright 2005, Broadcom Corporation
1343 + * All Rights Reserved.
1344 + *
1345 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1346 + * the contents of this file may not be disclosed to third parties, copied
1347 + * or duplicated in any form, in whole or in part, without the prior
1348 + * written permission of Broadcom Corporation.
1349 + * $Id$
1350 + */
1351 +
1352 +#ifndef _bcmenetrxh_h_
1353 +#define _bcmenetrxh_h_
1354 +
1355 +/*
1356 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
1357 + * with every frame consisting of
1358 + * 16bits of frame length, followed by
1359 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
1360 + */
1361 +typedef volatile struct {
1362 + uint16 len;
1363 + uint16 flags;
1364 + uint16 pad[12];
1365 +} bcmenetrxh_t;
1366 +
1367 +#define RXHDR_LEN 28
1368 +
1369 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
1370 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
1371 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
1372 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
1373 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
1374 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
1375 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
1376 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
1377 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
1378 +
1379 +#endif /* _bcmenetrxh_h_ */
1380 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmnvram.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmnvram.h
1381 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1382 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmnvram.h 2005-02-02 23:16:39.000000000 +0100
1383 @@ -0,0 +1,132 @@
1384 +/*
1385 + * NVRAM variable manipulation
1386 + *
1387 + * Copyright 2005, Broadcom Corporation
1388 + * All Rights Reserved.
1389 + *
1390 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1391 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1392 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1393 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1394 + *
1395 + * $Id$
1396 + */
1397 +
1398 +#ifndef _bcmnvram_h_
1399 +#define _bcmnvram_h_
1400 +
1401 +#ifndef _LANGUAGE_ASSEMBLY
1402 +
1403 +#include <typedefs.h>
1404 +
1405 +struct nvram_header {
1406 + uint32 magic;
1407 + uint32 len;
1408 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:27 init, mem. test 28, 29-31 reserved */
1409 + uint32 config_refresh; /* 0:15 config, 16:31 refresh */
1410 + uint32 config_ncdl; /* ncdl values for memc */
1411 +};
1412 +
1413 +struct nvram_tuple {
1414 + char *name;
1415 + char *value;
1416 + struct nvram_tuple *next;
1417 +};
1418 +
1419 +/*
1420 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1421 + * platforms.
1422 + */
1423 +extern int BCMINIT(nvram_init)(void *sbh);
1424 +
1425 +/*
1426 + * Disable NVRAM access. May be unnecessary or undefined on certain
1427 + * platforms.
1428 + */
1429 +extern void BCMINIT(nvram_exit)(void);
1430 +
1431 +/*
1432 + * Get the value of an NVRAM variable. The pointer returned may be
1433 + * invalid after a set.
1434 + * @param name name of variable to get
1435 + * @return value of variable or NULL if undefined
1436 + */
1437 +extern char * BCMINIT(nvram_get)(const char *name);
1438 +
1439 +/*
1440 + * Get the value of an NVRAM variable.
1441 + * @param name name of variable to get
1442 + * @return value of variable or NUL if undefined
1443 + */
1444 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1445 +
1446 +/*
1447 + * Match an NVRAM variable.
1448 + * @param name name of variable to match
1449 + * @param match value to compare against value of variable
1450 + * @return TRUE if variable is defined and its value is string equal
1451 + * to match or FALSE otherwise
1452 + */
1453 +static INLINE int
1454 +nvram_match(char *name, char *match) {
1455 + const char *value = BCMINIT(nvram_get)(name);
1456 + return (value && !strcmp(value, match));
1457 +}
1458 +
1459 +/*
1460 + * Inversely match an NVRAM variable.
1461 + * @param name name of variable to match
1462 + * @param match value to compare against value of variable
1463 + * @return TRUE if variable is defined and its value is not string
1464 + * equal to invmatch or FALSE otherwise
1465 + */
1466 +static INLINE int
1467 +nvram_invmatch(char *name, char *invmatch) {
1468 + const char *value = BCMINIT(nvram_get)(name);
1469 + return (value && strcmp(value, invmatch));
1470 +}
1471 +
1472 +/*
1473 + * Set the value of an NVRAM variable. The name and value strings are
1474 + * copied into private storage. Pointers to previously set values
1475 + * may become invalid. The new value may be immediately
1476 + * retrieved but will not be permanently stored until a commit.
1477 + * @param name name of variable to set
1478 + * @param value value of variable
1479 + * @return 0 on success and errno on failure
1480 + */
1481 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1482 +
1483 +/*
1484 + * Unset an NVRAM variable. Pointers to previously set values
1485 + * remain valid until a set.
1486 + * @param name name of variable to unset
1487 + * @return 0 on success and errno on failure
1488 + * NOTE: use nvram_commit to commit this change to flash.
1489 + */
1490 +extern int BCMINIT(nvram_unset)(const char *name);
1491 +
1492 +/*
1493 + * Commit NVRAM variables to permanent storage. All pointers to values
1494 + * may be invalid after a commit.
1495 + * NVRAM values are undefined after a commit.
1496 + * @return 0 on success and errno on failure
1497 + */
1498 +extern int BCMINIT(nvram_commit)(void);
1499 +
1500 +/*
1501 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1502 + * @param buf buffer to store variables
1503 + * @param count size of buffer in bytes
1504 + * @return 0 on success and errno on failure
1505 + */
1506 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1507 +
1508 +#endif /* _LANGUAGE_ASSEMBLY */
1509 +
1510 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1511 +#define NVRAM_VERSION 1
1512 +#define NVRAM_HEADER_SIZE 20
1513 +#define NVRAM_SPACE 0x8000
1514 +
1515 +#endif /* _bcmnvram_h_ */
1516 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmparams.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmparams.h
1517 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
1518 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmparams.h 2005-02-02 23:16:39.000000000 +0100
1519 @@ -0,0 +1,23 @@
1520 +/*
1521 + * Misc system wide parameters.
1522 + *
1523 + * Copyright 2005, Broadcom Corporation
1524 + * All Rights Reserved.
1525 + *
1526 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1527 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1528 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1529 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1530 + * $Id$
1531 + */
1532 +
1533 +#ifndef _bcmparams_h_
1534 +#define _bcmparams_h_
1535 +
1536 +#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
1537 +
1538 +#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
1539 +
1540 +#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
1541 +
1542 +#endif
1543 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmsrom.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmsrom.h
1544 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1545 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmsrom.h 2005-02-02 23:16:39.000000000 +0100
1546 @@ -0,0 +1,22 @@
1547 +/*
1548 + * Misc useful routines to access NIC local SROM/OTP .
1549 + *
1550 + * Copyright 2005, Broadcom Corporation
1551 + * All Rights Reserved.
1552 + *
1553 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1554 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1555 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1556 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1557 + *
1558 + * $Id$
1559 + */
1560 +
1561 +#ifndef _bcmsrom_h_
1562 +#define _bcmsrom_h_
1563 +
1564 +extern int srom_var_init(void *sbh, uint bus, void *curmap, void *osh, char **vars, int *count);
1565 +extern int srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
1566 +extern int srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
1567 +
1568 +#endif /* _bcmsrom_h_ */
1569 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bcmutils.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmutils.h
1570 --- linux-2.4.30/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1571 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bcmutils.h 2005-02-02 23:16:39.000000000 +0100
1572 @@ -0,0 +1,239 @@
1573 +/*
1574 + * Misc useful os-independent macros and functions.
1575 + *
1576 + * Copyright 2005, Broadcom Corporation
1577 + * All Rights Reserved.
1578 + *
1579 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1580 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1581 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1582 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1583 + * $Id$
1584 + */
1585 +
1586 +#ifndef _bcmutils_h_
1587 +#define _bcmutils_h_
1588 +
1589 +/*** driver-only section ***/
1590 +#ifdef BCMDRIVER
1591 +#include <osl.h>
1592 +
1593 +#define _BCM_U 0x01 /* upper */
1594 +#define _BCM_L 0x02 /* lower */
1595 +#define _BCM_D 0x04 /* digit */
1596 +#define _BCM_C 0x08 /* cntrl */
1597 +#define _BCM_P 0x10 /* punct */
1598 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1599 +#define _BCM_X 0x40 /* hex digit */
1600 +#define _BCM_SP 0x80 /* hard space (0x20) */
1601 +
1602 +extern unsigned char bcm_ctype[];
1603 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1604 +
1605 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1606 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1607 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1608 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1609 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1610 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1611 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1612 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1613 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1614 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1615 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1616 +
1617 +/*
1618 + * Spin at most 'us' microseconds while 'exp' is true.
1619 + * Caller should explicitly test 'exp' when this completes
1620 + * and take appropriate error action if 'exp' is still true.
1621 + */
1622 +#define SPINWAIT(exp, us) { \
1623 + uint countdown = (us) + 9; \
1624 + while ((exp) && (countdown >= 10)) {\
1625 + OSL_DELAY(10); \
1626 + countdown -= 10; \
1627 + } \
1628 +}
1629 +
1630 +/* generic osl packet queue */
1631 +struct pktq {
1632 + void *head; /* first packet to dequeue */
1633 + void *tail; /* last packet to dequeue */
1634 + uint len; /* number of queued packets */
1635 + uint maxlen; /* maximum number of queued packets */
1636 + bool priority; /* enqueue by packet priority */
1637 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1638 +};
1639 +#define DEFAULT_QLEN 128
1640 +
1641 +#define pktq_len(q) ((q)->len)
1642 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1643 +#define pktq_head(q) ((q)->head)
1644 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1645 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1646 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1647 +
1648 +/* externs */
1649 +/* packet */
1650 +extern uint pktcopy(void *drv, void *p, uint offset, int len, uchar *buf);
1651 +extern uint pkttotlen(void *drv, void *);
1652 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1653 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1654 +extern void *pktdeq(struct pktq *q);
1655 +extern void *pktdeqtail(struct pktq *q);
1656 +/* string */
1657 +extern uint bcm_atoi(char *s);
1658 +extern uchar bcm_toupper(uchar c);
1659 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1660 +extern char *bcmstrstr(char *haystack, char *needle);
1661 +extern char *bcmstrcat(char *dest, const char *src);
1662 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1663 +/* ethernet address */
1664 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1665 +extern int bcm_ether_atoe(char *p, char *ea);
1666 +/* delay */
1667 +extern void bcm_mdelay(uint ms);
1668 +/* variable access */
1669 +extern char *getvar(char *vars, char *name);
1670 +extern int getintvar(char *vars, char *name);
1671 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1672 +#define bcmlog(fmt, a1, a2)
1673 +#define bcmdumplog(buf, size) *buf = '\0'
1674 +#define bcmdumplogent(buf, idx) -1
1675 +#endif /* #ifdef BCMDRIVER */
1676 +
1677 +/*** driver/apps-shared section ***/
1678 +#ifndef MIN
1679 +#define MIN(a, b) (((a)<(b))?(a):(b))
1680 +#endif
1681 +
1682 +#ifndef MAX
1683 +#define MAX(a, b) (((a)>(b))?(a):(b))
1684 +#endif
1685 +
1686 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1687 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1688 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1689 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1690 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1691 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1692 +
1693 +/* bit map related macros */
1694 +#ifndef setbit
1695 +#define NBBY 8 /* 8 bits per byte */
1696 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1697 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1698 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1699 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1700 +#endif
1701 +
1702 +#define NBITS(type) (sizeof (type) * 8)
1703 +
1704 +/* crc defines */
1705 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1706 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1707 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1708 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1709 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1710 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1711 +
1712 +/* bcm_format_flags() bit description structure */
1713 +typedef struct bcm_bit_desc {
1714 + uint32 bit;
1715 + char* name;
1716 +} bcm_bit_desc_t;
1717 +
1718 +/* tag_ID/length/value_buffer tuple */
1719 +typedef struct bcm_tlv {
1720 + uint8 id;
1721 + uint8 len;
1722 + uint8 data[1];
1723 +} bcm_tlv_t;
1724 +
1725 +/* Check that bcm_tlv_t fits into the given buflen */
1726 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (buflen) >= 2 + (elt)->len)
1727 +
1728 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1729 +#define ETHER_ADDR_STR_LEN 18
1730 +
1731 +/* unaligned load and store macros */
1732 +#ifdef IL_BIGENDIAN
1733 +static INLINE uint32
1734 +load32_ua(uint8 *a)
1735 +{
1736 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1737 +}
1738 +
1739 +static INLINE void
1740 +store32_ua(uint8 *a, uint32 v)
1741 +{
1742 + a[0] = (v >> 24) & 0xff;
1743 + a[1] = (v >> 16) & 0xff;
1744 + a[2] = (v >> 8) & 0xff;
1745 + a[3] = v & 0xff;
1746 +}
1747 +
1748 +static INLINE uint16
1749 +load16_ua(uint8 *a)
1750 +{
1751 + return ((a[0] << 8) | a[1]);
1752 +}
1753 +
1754 +static INLINE void
1755 +store16_ua(uint8 *a, uint16 v)
1756 +{
1757 + a[0] = (v >> 8) & 0xff;
1758 + a[1] = v & 0xff;
1759 +}
1760 +
1761 +#else
1762 +
1763 +static INLINE uint32
1764 +load32_ua(uint8 *a)
1765 +{
1766 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
1767 +}
1768 +
1769 +static INLINE void
1770 +store32_ua(uint8 *a, uint32 v)
1771 +{
1772 + a[3] = (v >> 24) & 0xff;
1773 + a[2] = (v >> 16) & 0xff;
1774 + a[1] = (v >> 8) & 0xff;
1775 + a[0] = v & 0xff;
1776 +}
1777 +
1778 +static INLINE uint16
1779 +load16_ua(uint8 *a)
1780 +{
1781 + return ((a[1] << 8) | a[0]);
1782 +}
1783 +
1784 +static INLINE void
1785 +store16_ua(uint8 *a, uint16 v)
1786 +{
1787 + a[1] = (v >> 8) & 0xff;
1788 + a[0] = v & 0xff;
1789 +}
1790 +
1791 +#endif
1792 +
1793 +/* externs */
1794 +/* crc */
1795 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
1796 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
1797 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
1798 +/* format/print */
1799 +/* IE parsing */
1800 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
1801 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
1802 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
1803 +
1804 +/* multi-bool data type: set of bools, mbool is true if any is set */
1805 +typedef uint32 mbool;
1806 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
1807 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
1808 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
1809 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
1810 +
1811 +#endif /* _bcmutils_h_ */
1812 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/bitfuncs.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/bitfuncs.h
1813 --- linux-2.4.30/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
1814 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/bitfuncs.h 2005-02-02 23:16:39.000000000 +0100
1815 @@ -0,0 +1,85 @@
1816 +/*
1817 + * bit manipulation utility functions
1818 + *
1819 + * Copyright 2005, Broadcom Corporation
1820 + * All Rights Reserved.
1821 + *
1822 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1823 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1824 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1825 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1826 + * $Id$
1827 + */
1828 +
1829 +#ifndef _BITFUNCS_H
1830 +#define _BITFUNCS_H
1831 +
1832 +#include <typedefs.h>
1833 +
1834 +/* local prototypes */
1835 +static INLINE uint32 find_msbit(uint32 x);
1836 +
1837 +
1838 +/*
1839 + * find_msbit: returns index of most significant set bit in x, with index
1840 + * range defined as 0-31. NOTE: returns zero if input is zero.
1841 + */
1842 +
1843 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
1844 +
1845 +/*
1846 + * Implementation for Pentium processors and gcc. Note that this
1847 + * instruction is actually very slow on some processors (e.g., family 5,
1848 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
1849 + * implementation instead.
1850 + */
1851 +static INLINE uint32 find_msbit(uint32 x)
1852 +{
1853 + uint msbit;
1854 + __asm__("bsrl %1,%0"
1855 + :"=r" (msbit)
1856 + :"r" (x));
1857 + return msbit;
1858 +}
1859 +
1860 +#else
1861 +
1862 +/*
1863 + * Generic Implementation
1864 + */
1865 +
1866 +#define DB_POW_MASK16 0xffff0000
1867 +#define DB_POW_MASK8 0x0000ff00
1868 +#define DB_POW_MASK4 0x000000f0
1869 +#define DB_POW_MASK2 0x0000000c
1870 +#define DB_POW_MASK1 0x00000002
1871 +
1872 +static INLINE uint32 find_msbit(uint32 x)
1873 +{
1874 + uint32 temp_x = x;
1875 + uint msbit = 0;
1876 + if (temp_x & DB_POW_MASK16) {
1877 + temp_x >>= 16;
1878 + msbit = 16;
1879 + }
1880 + if (temp_x & DB_POW_MASK8) {
1881 + temp_x >>= 8;
1882 + msbit += 8;
1883 + }
1884 + if (temp_x & DB_POW_MASK4) {
1885 + temp_x >>= 4;
1886 + msbit += 4;
1887 + }
1888 + if (temp_x & DB_POW_MASK2) {
1889 + temp_x >>= 2;
1890 + msbit += 2;
1891 + }
1892 + if (temp_x & DB_POW_MASK1) {
1893 + msbit += 1;
1894 + }
1895 + return(msbit);
1896 +}
1897 +
1898 +#endif
1899 +
1900 +#endif /* _BITFUNCS_H */
1901 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/cfe_osl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/cfe_osl.h
1902 --- linux-2.4.30/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
1903 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/cfe_osl.h 2005-02-02 23:16:39.000000000 +0100
1904 @@ -0,0 +1,184 @@
1905 +/*
1906 + * CFE boot loader OS Abstraction Layer.
1907 + *
1908 + * Copyright 2005, Broadcom Corporation
1909 + * All Rights Reserved.
1910 + *
1911 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1912 + * the contents of this file may not be disclosed to third parties, copied
1913 + * or duplicated in any form, in whole or in part, without the prior
1914 + * written permission of Broadcom Corporation.
1915 + *
1916 + * $Id$
1917 + */
1918 +
1919 +#ifndef _cfe_osl_h_
1920 +#define _cfe_osl_h_
1921 +
1922 +#include <lib_types.h>
1923 +#include <lib_string.h>
1924 +#include <lib_printf.h>
1925 +#include <lib_malloc.h>
1926 +#include <cpu_config.h>
1927 +#include <cfe_timer.h>
1928 +#include <cfe_iocb.h>
1929 +#include <cfe_devfuncs.h>
1930 +#include <addrspace.h>
1931 +
1932 +#include <typedefs.h>
1933 +
1934 +/* dump string */
1935 +extern int (*xprinthook)(const char *str);
1936 +#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
1937 +
1938 +/* assert and panic */
1939 +#define ASSERT(exp) do {} while (0)
1940 +
1941 +/* PCMCIA attribute space access macros */
1942 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
1943 + bzero(buf, size)
1944 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
1945 + do {} while (0)
1946 +
1947 +/* PCI configuration space access macros */
1948 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
1949 + (offset == 8 ? 0 : 0xffffffff)
1950 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
1951 + do {} while (0)
1952 +
1953 +/* register access macros */
1954 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
1955 +#define rreg32(r) (*(volatile uint32*)(r))
1956 +#ifdef IL_BIGENDIAN
1957 +#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
1958 +#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
1959 +#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
1960 +#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
1961 +#else
1962 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
1963 +#define rreg16(r) (*(volatile uint16*)(r))
1964 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
1965 +#define rreg8(r) (*(volatile uint8*)(r))
1966 +#endif
1967 +#define R_REG(r) ({ \
1968 + __typeof(*(r)) __osl_v; \
1969 + switch (sizeof(*(r))) { \
1970 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
1971 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
1972 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
1973 + } \
1974 + __osl_v; \
1975 +})
1976 +#define W_REG(r, v) do { \
1977 + switch (sizeof(*(r))) { \
1978 + case sizeof(uint8): wreg8((r), (v)); break; \
1979 + case sizeof(uint16): wreg16((r), (v)); break; \
1980 + case sizeof(uint32): wreg32((r), (v)); break; \
1981 + } \
1982 +} while (0)
1983 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
1984 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
1985 +
1986 +/* bcopy, bcmp, and bzero */
1987 +#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
1988 +
1989 +#define osl_attach(pdev) (pdev)
1990 +#define osl_detach(osh)
1991 +
1992 +/* general purpose memory allocation */
1993 +#define MALLOC(osh, size) KMALLOC((size),0)
1994 +#define MFREE(osh, addr, size) KFREE((addr))
1995 +#define MALLOCED(osh) (0)
1996 +#define MALLOC_DUMP(osh, buf, sz)
1997 +#define MALLOC_FAILED(osh) (0)
1998 +
1999 +/* uncached virtual address */
2000 +#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
2001 +
2002 +/* host/bus architecture-specific address byte swap */
2003 +#define BUS_SWAP32(v) (v)
2004 +
2005 +/* get processor cycle count */
2006 +#define OSL_GETCYCLES(x) ((x) = 0)
2007 +
2008 +/* microsecond delay */
2009 +#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
2010 +
2011 +/* map/unmap physical to virtual I/O */
2012 +#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
2013 +#define REG_UNMAP(va) do {} while (0)
2014 +
2015 +/* dereference an address that may cause a bus exception */
2016 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
2017 +extern int osl_busprobe(uint32 *val, uint32 addr);
2018 +
2019 +/* allocate/free shared (dma-able) consistent (uncached) memory */
2020 +#define DMA_CONSISTENT_ALIGN 4096
2021 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2022 + osl_dma_alloc_consistent((size), (pap))
2023 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2024 + osl_dma_free_consistent((void*)(va))
2025 +extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
2026 +extern void osl_dma_free_consistent(void *va);
2027 +
2028 +/* map/unmap direction */
2029 +#define DMA_TX 1
2030 +#define DMA_RX 2
2031 +
2032 +/* map/unmap shared (dma-able) memory */
2033 +#define DMA_MAP(osh, va, size, direction, lb) ({ \
2034 + cfe_flushcache(CFE_CACHE_FLUSH_D); \
2035 + PHYSADDR((ulong)(va)); \
2036 +})
2037 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2038 + do {} while (0)
2039 +
2040 +/* shared (dma-able) memory access macros */
2041 +#define R_SM(r) *(r)
2042 +#define W_SM(r, v) (*(r) = (v))
2043 +#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
2044 +
2045 +/* generic packet structure */
2046 +#define LBUFSZ 4096
2047 +#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
2048 +struct lbuf {
2049 + struct lbuf *next; /* pointer to next lbuf if in a chain */
2050 + struct lbuf *link; /* pointer to next lbuf if in a list */
2051 + uchar *head; /* start of buffer */
2052 + uchar *end; /* end of buffer */
2053 + uchar *data; /* start of data */
2054 + uchar *tail; /* end of data */
2055 + uint len; /* nbytes of data */
2056 + void *cookie; /* generic cookie */
2057 +};
2058 +
2059 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2060 +#define PKTBUFSZ 2048
2061 +
2062 +/* packet primitives */
2063 +#define PKTGET(drv, len, send) ((void*)osl_pktget((len)))
2064 +#define PKTFREE(drv, lb, send) osl_pktfree((struct lbuf*)(lb))
2065 +#define PKTDATA(drv, lb) (((struct lbuf*)(lb))->data)
2066 +#define PKTLEN(drv, lb) (((struct lbuf*)(lb))->len)
2067 +#define PKTHEADROOM(drv, lb) (PKTDATA(drv,lb)-(((struct lbuf*)(lb))->head))
2068 +#define PKTTAILROOM(drv, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
2069 +#define PKTNEXT(drv, lb) (((struct lbuf*)(lb))->next)
2070 +#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
2071 +#define PKTSETLEN(drv, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
2072 +#define PKTPUSH(drv, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
2073 +#define PKTPULL(drv, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
2074 +#define PKTDUP(drv, lb) osl_pktdup((struct lbuf*)(lb))
2075 +#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
2076 +#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
2077 +#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
2078 +#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
2079 +#define PKTPRIO(lb) (0)
2080 +#define PKTSETPRIO(lb, x) do {} while (0)
2081 +extern struct lbuf *osl_pktget(uint len);
2082 +extern void osl_pktfree(struct lbuf *lb);
2083 +extern void osl_pktsetlen(struct lbuf *lb, uint len);
2084 +extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
2085 +extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
2086 +extern struct lbuf *osl_pktdup(struct lbuf *lb);
2087 +
2088 +#endif /* _cfe_osl_h_ */
2089 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/epivers.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/epivers.h
2090 --- linux-2.4.30/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
2091 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/epivers.h 2005-02-02 23:16:39.000000000 +0100
2092 @@ -0,0 +1,69 @@
2093 +/*
2094 + * Copyright 2005, Broadcom Corporation
2095 + * All Rights Reserved.
2096 + *
2097 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2098 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2099 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2100 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2101 + *
2102 + * $Id$
2103 + *
2104 +*/
2105 +
2106 +#ifndef _epivers_h_
2107 +#define _epivers_h_
2108 +
2109 +#ifdef linux
2110 +#include <linux/config.h>
2111 +#endif
2112 +
2113 +/* Vendor Name, ASCII, 32 chars max */
2114 +#ifdef COMPANYNAME
2115 +#define HPNA_VENDOR COMPANYNAME
2116 +#else
2117 +#define HPNA_VENDOR "Broadcom Corporation"
2118 +#endif
2119 +
2120 +/* Driver Date, ASCII, 32 chars max */
2121 +#define HPNA_DRV_BUILD_DATE __DATE__
2122 +
2123 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2124 +#define HPNA_HW_MFG_DATE "Not Specified"
2125 +
2126 +/* See documentation for Device Type values, 32 values max */
2127 +#ifndef HPNA_DEV_TYPE
2128 +
2129 +#if defined(CONFIG_BRCM_VJ)
2130 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2131 +
2132 +#elif defined(CONFIG_BCRM_93725)
2133 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2134 +
2135 +#else
2136 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2137 +
2138 +#endif
2139 +
2140 +#endif /* !HPNA_DEV_TYPE */
2141 +
2142 +
2143 +#define EPI_MAJOR_VERSION 3
2144 +
2145 +#define EPI_MINOR_VERSION 90
2146 +
2147 +#define EPI_RC_NUMBER 23
2148 +
2149 +#define EPI_INCREMENTAL_NUMBER 0
2150 +
2151 +#define EPI_BUILD_NUMBER 0
2152 +
2153 +#define EPI_VERSION 3,90,23,0
2154 +
2155 +#define EPI_VERSION_NUM 0x035a1700
2156 +
2157 +/* Driver Version String, ASCII, 32 chars max */
2158 +#define EPI_VERSION_STR "3.90.23.0"
2159 +#define EPI_ROUTER_VERSION_STR "3.91.23.0"
2160 +
2161 +#endif /* _epivers_h_ */
2162 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/epivers.h.in linux-2.4.30-brcm/arch/mips/bcm947xx/include/epivers.h.in
2163 --- linux-2.4.30/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
2164 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/epivers.h.in 2005-02-02 23:16:39.000000000 +0100
2165 @@ -0,0 +1,69 @@
2166 +/*
2167 + * Copyright 2005, Broadcom Corporation
2168 + * All Rights Reserved.
2169 + *
2170 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2171 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2172 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2173 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2174 + *
2175 + * $Id$
2176 + *
2177 +*/
2178 +
2179 +#ifndef _epivers_h_
2180 +#define _epivers_h_
2181 +
2182 +#ifdef linux
2183 +#include <linux/config.h>
2184 +#endif
2185 +
2186 +/* Vendor Name, ASCII, 32 chars max */
2187 +#ifdef COMPANYNAME
2188 +#define HPNA_VENDOR COMPANYNAME
2189 +#else
2190 +#define HPNA_VENDOR "Broadcom Corporation"
2191 +#endif
2192 +
2193 +/* Driver Date, ASCII, 32 chars max */
2194 +#define HPNA_DRV_BUILD_DATE __DATE__
2195 +
2196 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2197 +#define HPNA_HW_MFG_DATE "Not Specified"
2198 +
2199 +/* See documentation for Device Type values, 32 values max */
2200 +#ifndef HPNA_DEV_TYPE
2201 +
2202 +#if defined(CONFIG_BRCM_VJ)
2203 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2204 +
2205 +#elif defined(CONFIG_BCRM_93725)
2206 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2207 +
2208 +#else
2209 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2210 +
2211 +#endif
2212 +
2213 +#endif /* !HPNA_DEV_TYPE */
2214 +
2215 +
2216 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
2217 +
2218 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
2219 +
2220 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
2221 +
2222 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
2223 +
2224 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
2225 +
2226 +#define EPI_VERSION @EPI_VERSION@
2227 +
2228 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
2229 +
2230 +/* Driver Version String, ASCII, 32 chars max */
2231 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
2232 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
2233 +
2234 +#endif /* _epivers_h_ */
2235 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/etsockio.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/etsockio.h
2236 --- linux-2.4.30/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
2237 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/etsockio.h 2005-02-02 23:16:39.000000000 +0100
2238 @@ -0,0 +1,59 @@
2239 +/*
2240 + * Driver-specific socket ioctls
2241 + * used by BSD, Linux, and PSOS
2242 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
2243 + *
2244 + * Copyright 2005, Broadcom Corporation
2245 + * All Rights Reserved.
2246 + *
2247 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2248 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2249 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2250 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2251 + *
2252 + * $Id$
2253 + */
2254 +
2255 +#ifndef _etsockio_h_
2256 +#define _etsockio_h_
2257 +
2258 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
2259 +
2260 +
2261 +#if defined(linux)
2262 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
2263 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
2264 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
2265 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
2266 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
2267 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
2268 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
2269 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
2270 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
2271 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
2272 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
2273 +#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
2274 +
2275 +#else /* !linux */
2276 +
2277 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
2278 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
2279 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
2280 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
2281 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
2282 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
2283 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
2284 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
2285 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
2286 +
2287 +#endif
2288 +
2289 +/* arg to SIOCTXGEN */
2290 +struct txg {
2291 + uint32 num; /* number of frames to send */
2292 + uint32 delay; /* delay in microseconds between sending each */
2293 + uint32 size; /* size of ether frame to send */
2294 + uchar buf[1514]; /* starting ether frame data */
2295 +};
2296 +
2297 +#endif
2298 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/flash.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/flash.h
2299 --- linux-2.4.30/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
2300 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/flash.h 2005-02-02 23:16:39.000000000 +0100
2301 @@ -0,0 +1,188 @@
2302 +/*
2303 + * flash.h: Common definitions for flash access.
2304 + *
2305 + * Copyright 2005, Broadcom Corporation
2306 + * All Rights Reserved.
2307 + *
2308 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2309 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2310 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2311 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2312 + *
2313 + * $Id$
2314 + */
2315 +
2316 +/* Types of flashes we know about */
2317 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
2318 +
2319 +/* Commands to write/erase the flases */
2320 +typedef struct _flash_cmds{
2321 + flash_type_t type;
2322 + bool need_unlock;
2323 + uint16 pre_erase;
2324 + uint16 erase_block;
2325 + uint16 erase_chip;
2326 + uint16 write_word;
2327 + uint16 write_buf;
2328 + uint16 clear_csr;
2329 + uint16 read_csr;
2330 + uint16 read_id;
2331 + uint16 confirm;
2332 + uint16 read_array;
2333 +} flash_cmds_t;
2334 +
2335 +#define UNLOCK_CMD_WORDS 2
2336 +
2337 +typedef struct _unlock_cmd {
2338 + uint addr[UNLOCK_CMD_WORDS];
2339 + uint16 cmd[UNLOCK_CMD_WORDS];
2340 +} unlock_cmd_t;
2341 +
2342 +/* Flash descriptors */
2343 +typedef struct _flash_desc {
2344 + uint16 mfgid; /* Manufacturer Id */
2345 + uint16 devid; /* Device Id */
2346 + uint size; /* Total size in bytes */
2347 + uint width; /* Device width in bytes */
2348 + flash_type_t type; /* Device type old, S, J */
2349 + uint bsize; /* Block size */
2350 + uint nb; /* Number of blocks */
2351 + uint ff; /* First full block */
2352 + uint lf; /* Last full block */
2353 + uint nsub; /* Number of subblocks */
2354 + uint *subblocks; /* Offsets for subblocks */
2355 + char *desc; /* Description */
2356 +} flash_desc_t;
2357 +
2358 +
2359 +#ifdef DECLARE_FLASHES
2360 +flash_cmds_t sflash_cmd_t =
2361 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2362 +
2363 +flash_cmds_t flash_cmds[] = {
2364 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
2365 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
2366 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
2367 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2368 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2369 + { 0 }
2370 +};
2371 +
2372 +unlock_cmd_t unlock_cmd_amd = {
2373 +#ifdef MIPSEB
2374 +/* addr: */ { 0x0aa8, 0x0556},
2375 +#else
2376 +/* addr: */ { 0x0aaa, 0x0554},
2377 +#endif
2378 +/* data: */ { 0xaa, 0x55}
2379 +};
2380 +
2381 +unlock_cmd_t unlock_cmd_sst = {
2382 +#ifdef MIPSEB
2383 +/* addr: */ { 0xaaa8, 0x5556},
2384 +#else
2385 +/* addr: */ { 0xaaaa, 0x5554},
2386 +#endif
2387 +/* data: */ { 0xaa, 0x55}
2388 +};
2389 +
2390 +#define AMD_CMD 0xaaa
2391 +#define SST_CMD 0xaaaa
2392 +
2393 +/* intel unlock block cmds */
2394 +#define INTEL_UNLOCK1 0x60
2395 +#define INTEL_UNLOCK2 0xD0
2396 +
2397 +/* Just eight blocks of 8KB byte each */
2398 +
2399 +uint blk8x8k[] = { 0x00000000,
2400 + 0x00002000,
2401 + 0x00004000,
2402 + 0x00006000,
2403 + 0x00008000,
2404 + 0x0000a000,
2405 + 0x0000c000,
2406 + 0x0000e000,
2407 + 0x00010000
2408 +};
2409 +
2410 +/* Funky AMD arrangement for 29xx800's */
2411 +uint amd800[] = { 0x00000000, /* 16KB */
2412 + 0x00004000, /* 32KB */
2413 + 0x0000c000, /* 8KB */
2414 + 0x0000e000, /* 8KB */
2415 + 0x00010000, /* 8KB */
2416 + 0x00012000, /* 8KB */
2417 + 0x00014000, /* 32KB */
2418 + 0x0001c000, /* 16KB */
2419 + 0x00020000
2420 +};
2421 +
2422 +/* AMD arrangement for 29xx160's */
2423 +uint amd4112[] = { 0x00000000, /* 32KB */
2424 + 0x00008000, /* 8KB */
2425 + 0x0000a000, /* 8KB */
2426 + 0x0000c000, /* 16KB */
2427 + 0x00010000
2428 +};
2429 +uint amd2114[] = { 0x00000000, /* 16KB */
2430 + 0x00004000, /* 8KB */
2431 + 0x00006000, /* 8KB */
2432 + 0x00008000, /* 32KB */
2433 + 0x00010000
2434 +};
2435 +
2436 +
2437 +flash_desc_t sflash_desc =
2438 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
2439 +
2440 +flash_desc_t flashes[] = {
2441 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
2442 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
2443 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
2444 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
2445 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
2446 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
2447 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
2448 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
2449 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
2450 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
2451 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
2452 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
2453 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
2454 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
2455 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
2456 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
2457 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
2458 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
2459 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
2460 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
2461 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
2462 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
2463 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
2464 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
2465 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
2466 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
2467 + { 0x0001, 0x2201, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
2468 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
2469 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
2470 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
2471 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2472 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2473 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
2474 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
2475 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
2476 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
2477 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2478 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2479 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
2480 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
2481 +};
2482 +
2483 +#else
2484 +
2485 +extern flash_cmds_t flash_cmds[];
2486 +extern unlock_cmd_t unlock_cmd;
2487 +extern flash_desc_t flashes[];
2488 +
2489 +#endif
2490 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/flashutl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/flashutl.h
2491 --- linux-2.4.30/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
2492 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/flashutl.h 2005-02-02 23:16:39.000000000 +0100
2493 @@ -0,0 +1,27 @@
2494 +/*
2495 + * BCM47XX FLASH driver interface
2496 + *
2497 + * Copyright 2005, Broadcom Corporation
2498 + * All Rights Reserved.
2499 + *
2500 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2501 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2502 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2503 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2504 + * $Id$
2505 + */
2506 +
2507 +#ifndef _flashutl_h_
2508 +#define _flashutl_h_
2509 +
2510 +
2511 +#ifndef _LANGUAGE_ASSEMBLY
2512 +
2513 +int sysFlashInit(char *flash_str);
2514 +int sysFlashRead(uint off, uchar *dst, uint bytes);
2515 +int sysFlashWrite(uint off, uchar *src, uint bytes);
2516 +void nvWrite(unsigned short *data, unsigned int len);
2517 +
2518 +#endif /* _LANGUAGE_ASSEMBLY */
2519 +
2520 +#endif /* _flashutl_h_ */
2521 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/hnddma.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/hnddma.h
2522 --- linux-2.4.30/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
2523 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/hnddma.h 2005-02-02 23:16:39.000000000 +0100
2524 @@ -0,0 +1,184 @@
2525 +/*
2526 + * Generic Broadcom Home Networking Division (HND) DMA engine definitions.
2527 + * This supports the following chips: BCM42xx, 44xx, 47xx .
2528 + *
2529 + * Copyright 2005, Broadcom Corporation
2530 + * All Rights Reserved.
2531 + *
2532 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2533 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2534 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2535 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2536 + * $Id$
2537 + */
2538 +
2539 +#ifndef _hnddma_h_
2540 +#define _hnddma_h_
2541 +
2542 +/*
2543 + * Each DMA processor consists of a transmit channel and a receive channel.
2544 + */
2545 +typedef volatile struct {
2546 + /* transmit channel */
2547 + uint32 xmtcontrol; /* enable, et al */
2548 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
2549 + uint32 xmtptr; /* last descriptor posted to chip */
2550 + uint32 xmtstatus; /* current active descriptor, et al */
2551 +
2552 + /* receive channel */
2553 + uint32 rcvcontrol; /* enable, et al */
2554 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
2555 + uint32 rcvptr; /* last descriptor posted to chip */
2556 + uint32 rcvstatus; /* current active descriptor, et al */
2557 +} dmaregs_t;
2558 +
2559 +typedef volatile struct {
2560 + /* diag access */
2561 + uint32 fifoaddr; /* diag address */
2562 + uint32 fifodatalow; /* low 32bits of data */
2563 + uint32 fifodatahigh; /* high 32bits of data */
2564 + uint32 pad; /* reserved */
2565 +} dmafifo_t;
2566 +
2567 +/* transmit channel control */
2568 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
2569 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
2570 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
2571 +#define XC_FL ((uint32)1 << 4) /* flush request */
2572 +
2573 +/* transmit descriptor table pointer */
2574 +#define XP_LD_MASK 0xfff /* last valid descriptor */
2575 +
2576 +/* transmit channel status */
2577 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
2578 +#define XS_XS_MASK 0xf000 /* transmit state */
2579 +#define XS_XS_SHIFT 12
2580 +#define XS_XS_DISABLED 0x0000 /* disabled */
2581 +#define XS_XS_ACTIVE 0x1000 /* active */
2582 +#define XS_XS_IDLE 0x2000 /* idle wait */
2583 +#define XS_XS_STOPPED 0x3000 /* stopped */
2584 +#define XS_XS_SUSP 0x4000 /* suspend pending */
2585 +#define XS_XE_MASK 0xf0000 /* transmit errors */
2586 +#define XS_XE_SHIFT 16
2587 +#define XS_XE_NOERR 0x00000 /* no error */
2588 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
2589 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
2590 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
2591 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
2592 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
2593 +#define XS_AD_SHIFT 20
2594 +
2595 +/* receive channel control */
2596 +#define RC_RE ((uint32)1 << 0) /* receive enable */
2597 +#define RC_RO_MASK 0xfe /* receive frame offset */
2598 +#define RC_RO_SHIFT 1
2599 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
2600 +
2601 +/* receive descriptor table pointer */
2602 +#define RP_LD_MASK 0xfff /* last valid descriptor */
2603 +
2604 +/* receive channel status */
2605 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
2606 +#define RS_RS_MASK 0xf000 /* receive state */
2607 +#define RS_RS_SHIFT 12
2608 +#define RS_RS_DISABLED 0x0000 /* disabled */
2609 +#define RS_RS_ACTIVE 0x1000 /* active */
2610 +#define RS_RS_IDLE 0x2000 /* idle wait */
2611 +#define RS_RS_STOPPED 0x3000 /* reserved */
2612 +#define RS_RE_MASK 0xf0000 /* receive errors */
2613 +#define RS_RE_SHIFT 16
2614 +#define RS_RE_NOERR 0x00000 /* no error */
2615 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
2616 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
2617 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
2618 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
2619 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
2620 +#define RS_AD_SHIFT 20
2621 +
2622 +/* fifoaddr */
2623 +#define FA_OFF_MASK 0xffff /* offset */
2624 +#define FA_SEL_MASK 0xf0000 /* select */
2625 +#define FA_SEL_SHIFT 16
2626 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
2627 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
2628 +#define FA_SEL_RDD 0x40000 /* receive dma data */
2629 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
2630 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
2631 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
2632 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
2633 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
2634 +
2635 +/*
2636 + * DMA Descriptor
2637 + * Descriptors are only read by the hardware, never written back.
2638 + */
2639 +typedef volatile struct {
2640 + uint32 ctrl; /* misc control bits & bufcount */
2641 + uint32 addr; /* data buffer address */
2642 +} dmadd_t;
2643 +
2644 +/*
2645 + * Each descriptor ring must be 4096byte aligned
2646 + * and fit within a single 4096byte page.
2647 + */
2648 +#define DMAMAXRINGSZ 4096
2649 +#define DMARINGALIGN 4096
2650 +
2651 +/* control flags */
2652 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
2653 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
2654 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
2655 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
2656 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
2657 +
2658 +/* control flags in the range [27:20] are core-specific and not defined here */
2659 +#define CTRL_CORE_MASK 0x0ff00000
2660 +
2661 +/* export structure */
2662 +typedef volatile struct {
2663 + /* rx error counters */
2664 + uint rxgiants; /* rx giant frames */
2665 + uint rxnobuf; /* rx out of dma descriptors */
2666 + /* tx error counters */
2667 + uint txnobuf; /* tx out of dma descriptors */
2668 +} hnddma_t;
2669 +
2670 +#ifndef di_t
2671 +#define di_t void
2672 +#endif
2673 +
2674 +/* externs */
2675 +extern void * dma_attach(void *drv, void *dev, char *name, dmaregs_t *dmaregs,
2676 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset,
2677 + uint ddoffset, uint dataoffset, uint *msg_level);
2678 +extern void dma_detach(di_t *di);
2679 +extern void dma_txreset(di_t *di);
2680 +extern void dma_rxreset(di_t *di);
2681 +extern void dma_txinit(di_t *di);
2682 +extern bool dma_txenabled(di_t *di);
2683 +extern void dma_rxinit(di_t *di);
2684 +extern void dma_rxenable(di_t *di);
2685 +extern bool dma_rxenabled(di_t *di);
2686 +extern void dma_txsuspend(di_t *di);
2687 +extern void dma_txresume(di_t *di);
2688 +extern bool dma_txsuspended(di_t *di);
2689 +extern bool dma_txstopped(di_t *di);
2690 +extern bool dma_rxstopped(di_t *di);
2691 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
2692 +extern int dma_tx(di_t *di, void *p, uint32 coreflags);
2693 +extern void dma_fifoloopbackenable(di_t *di);
2694 +extern void *dma_rx(di_t *di);
2695 +extern void dma_rxfill(di_t *di);
2696 +extern void dma_txreclaim(di_t *di, bool forceall);
2697 +extern void dma_rxreclaim(di_t *di);
2698 +extern uintptr dma_getvar(di_t *di, char *name);
2699 +extern void *dma_getnexttxp(di_t *di, bool forceall);
2700 +extern void *dma_peeknexttxp(di_t *di);
2701 +extern void *dma_getnextrxp(di_t *di, bool forceall);
2702 +extern void dma_txblock(di_t *di);
2703 +extern void dma_txunblock(di_t *di);
2704 +extern uint dma_txactive(di_t *di);
2705 +extern void dma_txrotate(di_t *di);
2706 +
2707 +
2708 +#endif /* _hnddma_h_ */
2709 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/hndmips.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/hndmips.h
2710 --- linux-2.4.30/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
2711 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/hndmips.h 2005-02-02 23:16:39.000000000 +0100
2712 @@ -0,0 +1,16 @@
2713 +/*
2714 + * Alternate include file for HND sbmips.h since CFE also ships with
2715 + * a sbmips.h.
2716 + *
2717 + * Copyright 2005, Broadcom Corporation
2718 + * All Rights Reserved.
2719 + *
2720 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2721 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2722 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2723 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2724 + *
2725 + * $Id$
2726 + */
2727 +
2728 +#include "sbmips.h"
2729 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/linux_osl.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/linux_osl.h
2730 --- linux-2.4.30/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
2731 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/linux_osl.h 2005-02-02 23:16:39.000000000 +0100
2732 @@ -0,0 +1,341 @@
2733 +/*
2734 + * Linux OS Independent Layer
2735 + *
2736 + * Copyright 2005, Broadcom Corporation
2737 + * All Rights Reserved.
2738 + *
2739 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2740 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2741 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2742 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2743 + *
2744 + * $Id$
2745 + */
2746 +
2747 +#ifndef _linux_osl_h_
2748 +#define _linux_osl_h_
2749 +
2750 +#include <typedefs.h>
2751 +
2752 +/* use current 2.4.x calling conventions */
2753 +#include <linuxver.h>
2754 +
2755 +/* assert and panic */
2756 +#define ASSERT(exp) do {} while (0)
2757 +
2758 +/* PCMCIA attribute space access macros */
2759 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2760 +struct pcmcia_dev {
2761 + dev_link_t link; /* PCMCIA device pointer */
2762 + dev_node_t node; /* PCMCIA node structure */
2763 + void *base; /* Mapped attribute memory window */
2764 + size_t size; /* Size of window */
2765 + void *drv; /* Driver data */
2766 +};
2767 +#endif
2768 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2769 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
2770 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2771 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
2772 +extern void osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size);
2773 +extern void osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size);
2774 +
2775 +/* PCI configuration space access macros */
2776 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
2777 + osl_pci_read_config((osh), (offset), (size))
2778 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
2779 + osl_pci_write_config((osh), (offset), (size), (val))
2780 +extern uint32 osl_pci_read_config(void *osh, uint size, uint offset);
2781 +extern void osl_pci_write_config(void *osh, uint offset, uint size, uint val);
2782 +
2783 +/* OSL initialization */
2784 +extern void *osl_attach(void *pdev);
2785 +extern void osl_detach(void *osh);
2786 +
2787 +/* host/bus architecture-specific byte swap */
2788 +#define BUS_SWAP32(v) (v)
2789 +
2790 +/* general purpose memory allocation */
2791 +
2792 +#if defined(BCMDBG_MEM)
2793 +
2794 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
2795 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
2796 +#define MALLOCED(osh) osl_malloced((osh))
2797 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
2798 +extern void *osl_debug_malloc(void *osh, uint size, int line, char* file);
2799 +extern void osl_debug_mfree(void *osh, void *addr, uint size, int line, char* file);
2800 +extern char *osl_debug_memdump(void *osh, char *buf, uint sz);
2801 +
2802 +#else
2803 +
2804 +#define MALLOC(osh, size) osl_malloc((osh), (size))
2805 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
2806 +#define MALLOCED(osh) osl_malloced((osh))
2807 +
2808 +#endif /* BCMDBG_MEM */
2809 +
2810 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
2811 +
2812 +extern void *osl_malloc(void *osh, uint size);
2813 +extern void osl_mfree(void *osh, void *addr, uint size);
2814 +extern uint osl_malloced(void *osh);
2815 +extern uint osl_malloc_failed(void *osh);
2816 +
2817 +/* allocate/free shared (dma-able) consistent memory */
2818 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
2819 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2820 + osl_dma_alloc_consistent((osh), (size), (pap))
2821 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2822 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
2823 +extern void *osl_dma_alloc_consistent(void *osh, uint size, ulong *pap);
2824 +extern void osl_dma_free_consistent(void *osh, void *va, uint size, ulong pa);
2825 +
2826 +/* map/unmap direction */
2827 +#define DMA_TX 1
2828 +#define DMA_RX 2
2829 +
2830 +/* map/unmap shared (dma-able) memory */
2831 +#define DMA_MAP(osh, va, size, direction, p) \
2832 + osl_dma_map((osh), (va), (size), (direction))
2833 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2834 + osl_dma_unmap((osh), (pa), (size), (direction))
2835 +extern uint osl_dma_map(void *osh, void *va, uint size, int direction);
2836 +extern void osl_dma_unmap(void *osh, uint pa, uint size, int direction);
2837 +
2838 +/* register access macros */
2839 +#if defined(BCMJTAG)
2840 +struct bcmjtag_info;
2841 +extern uint32 bcmjtag_read(struct bcmjtag_info *ejh, uint32 addr, uint size);
2842 +extern void bcmjtag_write(struct bcmjtag_info *ejh, uint32 addr, uint32 val, uint size);
2843 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
2844 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
2845 +#endif
2846 +
2847 +/*
2848 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
2849 + * Macros expand to calls to functions defined in linux_osl.c .
2850 + */
2851 +#ifndef BINOSL
2852 +
2853 +/* string library, kernel mode */
2854 +#define printf(fmt, args...) printk(fmt, ## args)
2855 +#include <linux/kernel.h>
2856 +#include <linux/string.h>
2857 +
2858 +/* register access macros */
2859 +#if !defined(BCMJTAG)
2860 +#define R_REG(r) ( \
2861 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
2862 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
2863 + readl((volatile uint32*)(r)) \
2864 +)
2865 +#define W_REG(r, v) do { \
2866 + switch (sizeof(*(r))) { \
2867 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
2868 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
2869 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
2870 + } \
2871 +} while (0)
2872 +#endif
2873 +
2874 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2875 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2876 +
2877 +/* bcopy, bcmp, and bzero */
2878 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
2879 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
2880 +#define bzero(b, len) memset((b), '\0', (len))
2881 +
2882 +/* uncached virtual address */
2883 +#ifdef mips
2884 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
2885 +#include <asm/addrspace.h>
2886 +#else
2887 +#define OSL_UNCACHED(va) (va)
2888 +#endif
2889 +
2890 +/* get processor cycle count */
2891 +#if defined(mips)
2892 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
2893 +#elif defined(__i386__)
2894 +#define OSL_GETCYCLES(x) rdtscl((x))
2895 +#else
2896 +#define OSL_GETCYCLES(x) ((x) = 0)
2897 +#endif
2898 +
2899 +/* dereference an address that may cause a bus exception */
2900 +#ifdef mips
2901 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
2902 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
2903 +#else
2904 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
2905 +#include <asm/paccess.h>
2906 +#endif
2907 +#else
2908 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
2909 +#endif
2910 +
2911 +/* map/unmap physical to virtual I/O */
2912 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
2913 +#define REG_UNMAP(va) iounmap((void *)(va))
2914 +
2915 +/* microsecond delay */
2916 +#define OSL_DELAY(usec) udelay(usec)
2917 +#include <linux/delay.h>
2918 +
2919 +/* shared (dma-able) memory access macros */
2920 +#define R_SM(r) *(r)
2921 +#define W_SM(r, v) (*(r) = (v))
2922 +#define BZERO_SM(r, len) memset((r), '\0', (len))
2923 +
2924 +/* packet primitives */
2925 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
2926 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
2927 +#define PKTDATA(drv, skb) (((struct sk_buff*)(skb))->data)
2928 +#define PKTLEN(drv, skb) (((struct sk_buff*)(skb))->len)
2929 +#define PKTHEADROOM(drv, skb) (PKTDATA(drv,skb)-(((struct sk_buff*)(skb))->head))
2930 +#define PKTTAILROOM(drv, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
2931 +#define PKTNEXT(drv, skb) (((struct sk_buff*)(skb))->next)
2932 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
2933 +#define PKTSETLEN(drv, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
2934 +#define PKTPUSH(drv, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
2935 +#define PKTPULL(drv, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
2936 +#define PKTDUP(drv, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
2937 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
2938 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
2939 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
2940 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
2941 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
2942 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
2943 +extern void *osl_pktget(void *drv, uint len, bool send);
2944 +extern void osl_pktfree(void *skb);
2945 +
2946 +#else /* BINOSL */
2947 +
2948 +/* string library */
2949 +#ifndef LINUX_OSL
2950 +#undef printf
2951 +#define printf(fmt, args...) osl_printf((fmt), ## args)
2952 +#undef sprintf
2953 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
2954 +#undef strcmp
2955 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
2956 +#undef strncmp
2957 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
2958 +#undef strlen
2959 +#define strlen(s) osl_strlen((s))
2960 +#undef strcpy
2961 +#define strcpy(d, s) osl_strcpy((d), (s))
2962 +#undef strncpy
2963 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
2964 +#endif
2965 +extern int osl_printf(const char *format, ...);
2966 +extern int osl_sprintf(char *buf, const char *format, ...);
2967 +extern int osl_strcmp(const char *s1, const char *s2);
2968 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
2969 +extern int osl_strlen(char *s);
2970 +extern char* osl_strcpy(char *d, const char *s);
2971 +extern char* osl_strncpy(char *d, const char *s, uint n);
2972 +
2973 +/* register access macros */
2974 +#if !defined(BCMJTAG)
2975 +#define R_REG(r) ( \
2976 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
2977 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
2978 + osl_readl((volatile uint32*)(r)) \
2979 +)
2980 +#define W_REG(r, v) do { \
2981 + switch (sizeof(*(r))) { \
2982 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
2983 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
2984 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
2985 + } \
2986 +} while (0)
2987 +#endif
2988 +
2989 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2990 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2991 +extern uint8 osl_readb(volatile uint8 *r);
2992 +extern uint16 osl_readw(volatile uint16 *r);
2993 +extern uint32 osl_readl(volatile uint32 *r);
2994 +extern void osl_writeb(uint8 v, volatile uint8 *r);
2995 +extern void osl_writew(uint16 v, volatile uint16 *r);
2996 +extern void osl_writel(uint32 v, volatile uint32 *r);
2997 +
2998 +/* bcopy, bcmp, and bzero */
2999 +extern void bcopy(const void *src, void *dst, int len);
3000 +extern int bcmp(const void *b1, const void *b2, int len);
3001 +extern void bzero(void *b, int len);
3002 +
3003 +/* uncached virtual address */
3004 +#define OSL_UNCACHED(va) osl_uncached((va))
3005 +extern void *osl_uncached(void *va);
3006 +
3007 +/* get processor cycle count */
3008 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
3009 +extern uint osl_getcycles(void);
3010 +
3011 +/* dereference an address that may target abort */
3012 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
3013 +extern int osl_busprobe(uint32 *val, uint32 addr);
3014 +
3015 +/* map/unmap physical to virtual */
3016 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
3017 +#define REG_UNMAP(va) osl_reg_unmap((va))
3018 +extern void *osl_reg_map(uint32 pa, uint size);
3019 +extern void osl_reg_unmap(void *va);
3020 +
3021 +/* microsecond delay */
3022 +#define OSL_DELAY(usec) osl_delay((usec))
3023 +extern void osl_delay(uint usec);
3024 +
3025 +/* shared (dma-able) memory access macros */
3026 +#define R_SM(r) *(r)
3027 +#define W_SM(r, v) (*(r) = (v))
3028 +#define BZERO_SM(r, len) bzero((r), (len))
3029 +
3030 +/* packet primitives */
3031 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
3032 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
3033 +#define PKTDATA(drv, skb) osl_pktdata((drv), (skb))
3034 +#define PKTLEN(drv, skb) osl_pktlen((drv), (skb))
3035 +#define PKTHEADROOM(drv, skb) osl_pktheadroom((drv), (skb))
3036 +#define PKTTAILROOM(drv, skb) osl_pkttailroom((drv), (skb))
3037 +#define PKTNEXT(drv, skb) osl_pktnext((drv), (skb))
3038 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
3039 +#define PKTSETLEN(drv, skb, len) osl_pktsetlen((drv), (skb), (len))
3040 +#define PKTPUSH(drv, skb, bytes) osl_pktpush((drv), (skb), (bytes))
3041 +#define PKTPULL(drv, skb, bytes) osl_pktpull((drv), (skb), (bytes))
3042 +#define PKTDUP(drv, skb) osl_pktdup((drv), (skb))
3043 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
3044 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
3045 +#define PKTLINK(skb) osl_pktlink((skb))
3046 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
3047 +#define PKTPRIO(skb) osl_pktprio((skb))
3048 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
3049 +extern void *osl_pktget(void *drv, uint len, bool send);
3050 +extern void osl_pktfree(void *skb);
3051 +extern uchar *osl_pktdata(void *drv, void *skb);
3052 +extern uint osl_pktlen(void *drv, void *skb);
3053 +extern uint osl_pktheadroom(void *drv, void *skb);
3054 +extern uint osl_pkttailroom(void *drv, void *skb);
3055 +extern void *osl_pktnext(void *drv, void *skb);
3056 +extern void osl_pktsetnext(void *skb, void *x);
3057 +extern void osl_pktsetlen(void *drv, void *skb, uint len);
3058 +extern uchar *osl_pktpush(void *drv, void *skb, int bytes);
3059 +extern uchar *osl_pktpull(void *drv, void *skb, int bytes);
3060 +extern void *osl_pktdup(void *drv, void *skb);
3061 +extern void *osl_pktcookie(void *skb);
3062 +extern void osl_pktsetcookie(void *skb, void *x);
3063 +extern void *osl_pktlink(void *skb);
3064 +extern void osl_pktsetlink(void *skb, void *x);
3065 +extern uint osl_pktprio(void *skb);
3066 +extern void osl_pktsetprio(void *skb, uint x);
3067 +
3068 +#endif /* BINOSL */
3069 +
3070 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
3071 +#define PKTBUFSZ 2048
3072 +
3073 +#endif /* _linux_osl_h_ */
3074 diff -Nur linux-2.4.30/arch/mips/bcm947xx/include/linuxver.h linux-2.4.30-brcm/arch/mips/bcm947xx/include/linuxver.h
3075 --- linux-2.4.30/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
3076 +++ linux-2.4.30-brcm/arch/mips/bcm947xx/include/linuxver.h 2005-02-02 23:16:39.000000000 +0100
3077 @@ -0,0 +1,399 @@
3078 +/*
3079 + * Linux-specific abstractions to gain some independence from linux kernel versions.
3080 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
3081 + *
3082 + * Copyright 2005, Broadcom Corporation
3083 + * All Rights Reserved.
3084 + *
3085 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3086 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3087 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3088 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3089 + *
3090 + * $Id$
3091 + */
3092 +
3093 +#ifndef _linuxver_h_
3094 +#define _linuxver_h_
3095 +
3096 +#include <linux/config.h>
3097 +#include <linux/version.h>
3098 +
3099 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
3100 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
3101 +#ifdef __UNDEF_NO_VERSION__
3102 +#undef __NO_VERSION__
3103 +#else
3104 +#define __NO_VERSION__
3105 +#endif
3106 +#endif
3107 +
3108 +#if defined(MODULE) && defined(MODVERSIONS)
3109 +#include <linux/modversions.h>
3110 +#endif
3111 +
3112 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
3113 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
3114 +#include <linux/malloc.h>
3115 +#else
3116 +#include <linux/slab.h>
3117 +#endif
3118 +
3119 +#include <linux/types.h>
3120 +#include <linux/init.h>
3121 +#include <linux/mm.h>
3122 +#include <linux/string.h>
3123 +#include <linux/pci.h>
3124 +#include <linux/interrupt.h>
3125 +#include <linux/netdevice.h>
3126 +#include <asm/io.h>
3127 +
3128 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
3129 +#include <linux/workqueue.h>
3130 +#else
3131 +#include <linux/tqueue.h>
3132 +#ifndef work_struct
3133 +#define work_struct tq_struct
3134 +#endif
3135 +#ifndef INIT_WORK
3136 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
3137 +#endif
3138 +#ifndef schedule_work
3139 +#define schedule_work(_work) schedule_task((_work))
3140 +#endif
3141 +#ifndef flush_scheduled_work
3142 +#define flush_scheduled_work() flush_scheduled_tasks()
3143 +#endif
3144 +#endif
3145 +
3146 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3147 +/* Some distributions have their own 2.6.x compatibility layers */
3148 +#ifndef IRQ_NONE
3149 +typedef void irqreturn_t;
3150 +#define IRQ_NONE
3151 +#define IRQ_HANDLED
3152 +#define IRQ_RETVAL(x)
3153 +#endif
3154 +#endif
3155 +
3156 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
3157 +
3158 +#include <pcmcia/version.h>
3159 +#include <pcmcia/cs_types.h>
3160 +#include <pcmcia/cs.h>
3161 +#include <pcmcia/cistpl.h>
3162 +#include <pcmcia/cisreg.h>
3163 +#include <pcmcia/ds.h>
3164 +
3165 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
3166 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
3167 + * does this, but it's not in 2.4 so we do our own for now. */
3168 +static inline void
3169 +cs_error(client_handle_t handle, int func, int ret)
3170 +{
3171 + error_info_t err = { func, ret };
3172 + CardServices(ReportError, handle, &err);
3173 +}
3174 +#endif
3175 +
3176 +#endif /* CONFIG_PCMCIA */
3177 +
3178 +#ifndef __exit
3179 +#define __exit
3180 +#endif
3181 +#ifndef __devexit
3182 +#define __devexit
3183 +#endif
3184 +#ifndef __devinit
3185 +#define __devinit __init
3186 +#endif
3187 +#ifndef __devinitdata
3188 +#define __devinitdata
3189 +#endif
3190 +#ifndef __devexit_p
3191 +#define __devexit_p(x) x
3192 +#endif
3193 +
3194 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
3195 +
3196 +#define pci_get_drvdata(dev) (dev)->sysdata
3197 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
3198 +
3199 +/*
3200 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
3201 + */
3202 +
3203 +struct pci_device_id {
3204 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
3205 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
3206 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
3207 + unsigned long driver_data; /* Data private to the driver */
3208 +};
3209 +
3210 +struct pci_driver {
3211 + struct list_head node;
3212 + char *name;
3213 + const struct pci_device_id *id_table; /* NULL if wants all devices */
3214 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
3215 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
3216 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
3217 + void (*resume)(struct pci_dev *dev); /* Device woken up */
3218 +};
3219 +
3220 +#define MODULE_DEVICE_TABLE(type, name)
3221 +#define PCI_ANY_ID (~0)
3222 +
3223 +/* compatpci.c */
3224 +#define pci_module_init pci_register_driver
3225 +extern int pci_register_driver(struct pci_driver *drv);
3226 +extern void pci_unregister_driver(struct pci_driver *drv);
3227 +
3228 +#endif /* PCI registration */
3229 +
3230 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
3231 +#ifdef MODULE
3232 +#define module_init(x) int init_module(void) { return x(); }
3233 +#define module_exit(x) void cleanup_module(void) { x(); }
3234 +#else
3235 +#define module_init(x) __initcall(x);
3236 +#define module_exit(x) __exitcall(x);
3237 +#endif
3238 +#endif
3239 +
3240 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
3241 +#define list_for_each(pos, head) \
3242 + for (pos = (head)->next; pos != (head); pos = pos->next)
3243 +#endif
3244 +
3245 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
3246 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
3247 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
3248 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
3249 +#endif
3250 +
3251 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
3252 +#define pci_enable_device(dev) do { } while (0)
3253 +#endif
3254 +
3255 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
3256 +#define net_device device
3257 +#endif
3258 +
3259 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
3260 +
3261 +/*
3262 + * DMA mapping
3263 + *
3264 + * See linux/Documentation/DMA-mapping.txt
3265 + */
3266 +
3267 +#ifndef PCI_DMA_TODEVICE
3268 +#define PCI_DMA_TODEVICE 1
3269 +#define PCI_DMA_FROMDEVICE 2
3270 +#endif
3271 +
3272 +typedef u32 dma_addr_t;
3273 +
3274 +/* Pure 2^n version of get_order */
3275 +static inline int get_order(unsigned long size)
3276 +{
3277 + int order;
3278 +
3279 + size = (size-1) >> (PAGE_SHIFT-1);
3280 + order = -1;
3281 + do {
3282 + size >>= 1;
3283 + order++;
3284 + } while (size);
3285 + return order;
3286 +}
3287 +
3288 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
3289 + dma_addr_t *dma_handle)
3290 +{
3291 + void *ret;
3292 + int gfp = GFP_ATOMIC | GFP_DMA;
3293 +
3294 + ret = (void *)__get_free_pages(gfp, get_order(size));
3295 +
3296 + if (ret != NULL) {
3297 + memset(ret, 0, size);
3298 + *dma_handle = virt_to_bus(ret);
3299 + }
3300 + return ret;
3301 +}
3302 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
3303 + void *vaddr, dma_addr_t dma_handle)
3304 +{
3305 + free_pages((unsigned long)vaddr, get_order(size));
3306 +}
3307 +#ifdef ILSIM
3308 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
3309 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
3310 +#else
3311 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
3312 +#define pci_unmap_single(cookie, address, size, dir)
3313 +#endif
3314 +
3315 +#endif /* DMA mapping */
3316 +
3317 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
3318 +
3319 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
3320 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
3321 +
3322 +/* pcmcia-cs provides its own netdevice compatibility layer */
3323 +#ifndef _COMPAT_NETDEVICE_H
3324 +
3325 +/*
3326 + * SoftNet
3327 + *
3328 + * For pre-softnet kernels we need to tell the upper layer not to
3329 + * re-enter start_xmit() while we are in there. However softnet
3330 + * guarantees not to enter while we are in there so there is no need
3331 + * to do the netif_stop_queue() dance unless the transmit queue really
3332 + * gets stuck. This should also improve performance according to tests
3333 + * done by Aman Singla.
3334 + */
3335 +
3336 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
3337 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
3338 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
3339 +
3340 +static inline void netif_start_queue(struct net_device *dev)
3341 +{
3342 + dev->tbusy = 0;
3343 + dev->interrupt = 0;
3344 + dev->start = 1;
3345 +}
3346 +
3347 +#define netif_queue_stopped(dev) (dev)->tbusy
3348 +#define netif_running(dev) (dev)->start
3349 +
3350 +#endif /* _COMPAT_NETDEVICE_H */
3351 +
3352 +#define netif_device_attach(dev) netif_start_queue(dev)
3353 +#define netif_device_detach(dev) netif_stop_queue(dev)
3354 +
3355 +/* 2.4.x renamed bottom halves to tasklets */
3356 +#define tasklet_struct tq_struct
3357 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
3358 +{
3359 + queue_task(tasklet, &tq_immediate);
3360 + mark_bh(IMMEDIATE_BH);
3361 +}
3362 +
3363 +static inline void tasklet_init(struct tasklet_struct *tasklet,
3364 + void (*func)(unsigned long),
3365 + unsigned long data)
3366 +{
3367 + tasklet->next = NULL;
3368 + tasklet->sync = 0;
3369 + tasklet->routine = (void (*)(void *))func;
3370 + tasklet->data = (void *)data;
3371 +}
3372 +#define tasklet_kill(tasklet) {do{} while(0);}
3373 +
3374 +/* 2.4.x introduced del_timer_sync() */
3375 +#define del_timer_sync(timer) del_timer(timer)
3376 +
3377 +#else
3378 +
3379 +#define netif_down(dev)
3380 +
3381 +#endif /* SoftNet */
3382 +
3383 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
3384 +
3385 +/*
3386 + * Emit code to initialise a tq_struct's routine and data pointers
3387 + */
3388 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
3389 + do { \
3390 + (_tq)->routine = _routine; \
3391 + (_tq)->data = _data; \
3392 + } while (0)
3393 +
3394 +/*
3395 + * Emit code to initialise all of a tq_struct
3396 + */
3397 +#define INIT_TQUEUE(_tq, _routine, _data) \
3398 + do { \
3399 + INIT_LIST_HEAD(&(_tq)->list); \
3400 + (_tq)->sync = 0; \
3401 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
3402 + } while (0)
3403 +
3404 +#endif