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[openwrt/svn-archive/archive.git] / openwrt / target / linux / linux-2.4 / patches / brcm / 001-bcm47xx.patch
1 diff -urN linux.old/Makefile linux.dev/Makefile
2 --- linux.old/Makefile 2005-08-26 13:41:41.689634168 +0200
3 +++ linux.dev/Makefile 2005-08-26 13:44:34.233403528 +0200
4 @@ -17,9 +17,9 @@
5 FINDHPATH = $(HPATH)/asm $(HPATH)/linux $(HPATH)/scsi $(HPATH)/net $(HPATH)/math-emu
6
7 HOSTCC = gcc
8 -HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
9 +HOSTCFLAGS = -Wall -Wstrict-prototypes -Os -fomit-frame-pointer
10
11 -CROSS_COMPILE =
12 +CROSS_COMPILE=
13
14 #
15 # Include the make variables (CC, etc...)
16 @@ -91,8 +91,10 @@
17
18 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
19
20 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
21 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
22 -fno-strict-aliasing -fno-common
23 +
24 +
25 ifndef CONFIG_FRAME_POINTER
26 CFLAGS += -fomit-frame-pointer
27 endif
28 @@ -354,7 +356,7 @@
29 @rm -f .ver1
30
31 include/linux/version.h: ./Makefile
32 - @expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
33 + @-expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
34 (echo KERNELRELEASE \"$(KERNELRELEASE)\" exceeds $(uts_len) characters >&2; false)
35 @echo \#define UTS_RELEASE \"$(KERNELRELEASE)\" > .ver
36 @echo \#define LINUX_VERSION_CODE `expr $(VERSION) \\* 65536 + $(PATCHLEVEL) \\* 256 + $(SUBLEVEL)` >> .ver
37 diff -urN linux.old/Rules.make linux.dev/Rules.make
38 --- linux.old/Rules.make 2005-11-07 23:12:50.538884250 +0100
39 +++ linux.dev/Rules.make 2005-11-07 21:57:07.837585250 +0100
40 @@ -176,7 +176,14 @@
41 _modinst__: dummy
42 ifneq "$(strip $(ALL_MOBJS))" ""
43 mkdir -p $(MODLIB)/kernel/$(MOD_DESTDIR)
44 - cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
45 + #@cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
46 + for f in $(ALL_MOBJS) ; do \
47 + $(OBJCOPY) -R __ksymtab -R .comment -R .note -x \
48 + `$(NM) $$f | cut -f3- -d' ' | sed -n \
49 + -e 's/__module_parm_\(.*\)/-K \1/p' \
50 + -e 's/__ks..tab_\(.*\)/-K \1/p'` \
51 + $$f $(MODLIB)/kernel/$(MOD_DESTDIR)$(MOD_TARGET)$$f; \
52 + done
53 endif
54
55 .PHONY: modules_install
56 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
57 --- linux.old/arch/mips/Makefile 2005-11-07 23:12:50.582887000 +0100
58 +++ linux.dev/arch/mips/Makefile 2005-11-07 21:57:08.537629000 +0100
59 @@ -46,10 +46,10 @@
60 GCCFLAGS := -I $(TOPDIR)/include/asm/gcc
61 GCCFLAGS += -G 0 -mno-abicalls -fno-pic -pipe
62 GCCFLAGS += $(call check_gcc, -finline-limit=100000,)
63 -LINKFLAGS += -G 0 -static -n
64 -MODFLAGS += -mlong-calls
65 +LINKFLAGS += -G 0 -static -n -nostdlib
66 +MODFLAGS += -mlong-calls -fno-common
67
68 -ifdef CONFIG_DEBUG_INFO
69 +ifdef CONFIG_REMOTE_DEBUG
70 GCCFLAGS += -g
71 ifdef CONFIG_SB1XXX_CORELIS
72 GCCFLAGS += -mno-sched-prolog -fno-omit-frame-pointer
73 @@ -71,13 +71,13 @@
74 set_gccflags = $(shell \
75 while :; do \
76 cpu=$(1); isa=-$(2); \
77 - for gcc_opt in -march= -mcpu=; do \
78 + for gcc_opt in -march= -mtune=; do \
79 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
80 -xc /dev/null > /dev/null 2>&1 && \
81 break 2; \
82 done; \
83 cpu=$(3); isa=-$(4); \
84 - for gcc_opt in -march= -mcpu=; do \
85 + for gcc_opt in -march= -mtune=; do \
86 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
87 -xc /dev/null > /dev/null 2>&1 && \
88 break 2; \
89 @@ -92,7 +92,7 @@
90 fi; \
91 gas_abi=-Wa,-32; gas_cpu=$$cpu; gas_isa=-Wa,$$isa; \
92 while :; do \
93 - for gas_opt in -Wa,-march= -Wa,-mcpu=; do \
94 + for gas_opt in -Wa,-march= -Wa,-mtune=; do \
95 $(CC) $$gas_abi $$gas_opt$$cpu $$gas_isa -Wa,-Z -c \
96 -o /dev/null -xassembler /dev/null > /dev/null 2>&1 && \
97 break 2; \
98 @@ -174,6 +174,7 @@
99 endif
100
101 AFLAGS += $(GCCFLAGS)
102 +ASFLAGS += $(GCCFLAGS)
103 CFLAGS += $(GCCFLAGS)
104
105 LD += -m $(ld-emul)
106 @@ -727,6 +728,19 @@
107 endif
108
109 #
110 +# Broadcom BCM947XX variants
111 +#
112 +ifdef CONFIG_BCM947XX
113 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
114 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
115 +LOADADDR := 0x80001000
116 +
117 +zImage: vmlinux
118 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
119 +export LOADADDR
120 +endif
121 +
122 +#
123 # Choosing incompatible machines durings configuration will result in
124 # error messages during linking. Select a default linkscript if
125 # none has been choosen above.
126 @@ -779,6 +793,7 @@
127 $(MAKE) -C arch/$(ARCH)/tools clean
128 $(MAKE) -C arch/mips/baget clean
129 $(MAKE) -C arch/mips/lasat clean
130 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
131
132 archmrproper:
133 @$(MAKEBOOT) mrproper
134 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
135 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
136 +++ linux.dev/arch/mips/bcm947xx/Makefile 2005-11-08 00:55:04.392074500 +0100
137 @@ -0,0 +1,15 @@
138 +#
139 +# Makefile for the BCM947xx specific kernel interface routines
140 +# under Linux.
141 +#
142 +
143 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
144 +
145 +O_TARGET := bcm947xx.o
146 +
147 +export-objs := nvram_linux.o setup.o
148 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
149 +obj-y += nvram.o nvram_linux.o sflash.o
150 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
151 +
152 +include $(TOPDIR)/Rules.make
153 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
154 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
155 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2005-11-07 21:57:07.841585500 +0100
156 @@ -0,0 +1,33 @@
157 +#
158 +# Makefile for Broadcom BCM947XX boards
159 +#
160 +# Copyright 2001-2003, Broadcom Corporation
161 +# All Rights Reserved.
162 +#
163 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
164 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
165 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
166 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
167 +#
168 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
169 +#
170 +
171 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
172 +SYSTEM ?= $(TOPDIR)/vmlinux
173 +
174 +all: vmlinuz
175 +
176 +# Don't build dependencies, this may die if $(CC) isn't gcc
177 +dep:
178 +
179 +# Create a gzipped version named vmlinuz for compatibility
180 +vmlinuz: piggy
181 + gzip -c9 $< > $@
182 +
183 +piggy: $(SYSTEM)
184 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
185 +
186 +mrproper: clean
187 +
188 +clean:
189 + rm -f vmlinuz piggy
190 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
191 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
192 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2005-11-07 21:57:07.841585500 +0100
193 @@ -0,0 +1,15 @@
194 +#
195 +# Makefile for the BCM947xx specific kernel interface routines
196 +# under Linux.
197 +#
198 +
199 +.S.s:
200 + $(CPP) $(AFLAGS) $< -o $*.s
201 +.S.o:
202 + $(CC) $(AFLAGS) -c $< -o $*.o
203 +
204 +O_TARGET := brcm.o
205 +
206 +obj-y := int-handler.o irq.o
207 +
208 +include $(TOPDIR)/Rules.make
209 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
210 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
211 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2005-11-07 21:57:07.841585500 +0100
212 @@ -0,0 +1,51 @@
213 +/*
214 + * Generic interrupt handler for Broadcom MIPS boards
215 + *
216 + * Copyright 2004, Broadcom Corporation
217 + * All Rights Reserved.
218 + *
219 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
220 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
221 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
222 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
223 + *
224 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
225 + */
226 +
227 +#include <linux/config.h>
228 +
229 +#include <asm/asm.h>
230 +#include <asm/mipsregs.h>
231 +#include <asm/regdef.h>
232 +#include <asm/stackframe.h>
233 +
234 +/*
235 + * MIPS IRQ Source
236 + * -------- ------
237 + * 0 Software (ignored)
238 + * 1 Software (ignored)
239 + * 2 Combined hardware interrupt (hw0)
240 + * 3 Hardware
241 + * 4 Hardware
242 + * 5 Hardware
243 + * 6 Hardware
244 + * 7 R4k timer
245 + */
246 +
247 + .text
248 + .set noreorder
249 + .set noat
250 + .align 5
251 + NESTED(brcmIRQ, PT_SIZE, sp)
252 + SAVE_ALL
253 + CLI
254 + .set at
255 + .set noreorder
256 +
257 + jal brcm_irq_dispatch
258 + move a0, sp
259 +
260 + j ret_from_irq
261 + nop
262 +
263 + END(brcmIRQ)
264 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
265 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
266 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2005-11-07 21:57:07.841585500 +0100
267 @@ -0,0 +1,130 @@
268 +/*
269 + * Generic interrupt control functions for Broadcom MIPS boards
270 + *
271 + * Copyright 2004, Broadcom Corporation
272 + * All Rights Reserved.
273 + *
274 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
275 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
276 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
277 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
278 + *
279 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
280 + */
281 +
282 +#include <linux/config.h>
283 +#include <linux/init.h>
284 +#include <linux/kernel.h>
285 +#include <linux/types.h>
286 +#include <linux/interrupt.h>
287 +#include <linux/irq.h>
288 +
289 +#include <asm/irq.h>
290 +#include <asm/mipsregs.h>
291 +#include <asm/gdb-stub.h>
292 +
293 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
294 +
295 +extern asmlinkage void brcmIRQ(void);
296 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
297 +
298 +void
299 +brcm_irq_dispatch(struct pt_regs *regs)
300 +{
301 + u32 cause;
302 +
303 + cause = read_c0_cause() &
304 + read_c0_status() &
305 + CAUSEF_IP;
306 +
307 +#ifdef CONFIG_KERNPROF
308 + change_c0_status(cause | 1, 1);
309 +#else
310 + clear_c0_status(cause);
311 +#endif
312 +
313 + if (cause & CAUSEF_IP7)
314 + do_IRQ(7, regs);
315 + if (cause & CAUSEF_IP2)
316 + do_IRQ(2, regs);
317 + if (cause & CAUSEF_IP3)
318 + do_IRQ(3, regs);
319 + if (cause & CAUSEF_IP4)
320 + do_IRQ(4, regs);
321 + if (cause & CAUSEF_IP5)
322 + do_IRQ(5, regs);
323 + if (cause & CAUSEF_IP6)
324 + do_IRQ(6, regs);
325 +}
326 +
327 +static void
328 +enable_brcm_irq(unsigned int irq)
329 +{
330 + if (irq < 8)
331 + set_c0_status(1 << (irq + 8));
332 + else
333 + set_c0_status(IE_IRQ0);
334 +}
335 +
336 +static void
337 +disable_brcm_irq(unsigned int irq)
338 +{
339 + if (irq < 8)
340 + clear_c0_status(1 << (irq + 8));
341 + else
342 + clear_c0_status(IE_IRQ0);
343 +}
344 +
345 +static void
346 +ack_brcm_irq(unsigned int irq)
347 +{
348 + /* Already done in brcm_irq_dispatch */
349 +}
350 +
351 +static unsigned int
352 +startup_brcm_irq(unsigned int irq)
353 +{
354 + enable_brcm_irq(irq);
355 +
356 + return 0; /* never anything pending */
357 +}
358 +
359 +static void
360 +end_brcm_irq(unsigned int irq)
361 +{
362 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
363 + enable_brcm_irq(irq);
364 +}
365 +
366 +static struct hw_interrupt_type brcm_irq_type = {
367 + typename: "MIPS",
368 + startup: startup_brcm_irq,
369 + shutdown: disable_brcm_irq,
370 + enable: enable_brcm_irq,
371 + disable: disable_brcm_irq,
372 + ack: ack_brcm_irq,
373 + end: end_brcm_irq,
374 + NULL
375 +};
376 +
377 +void __init
378 +init_IRQ(void)
379 +{
380 + int i;
381 +
382 + for (i = 0; i < NR_IRQS; i++) {
383 + irq_desc[i].status = IRQ_DISABLED;
384 + irq_desc[i].action = 0;
385 + irq_desc[i].depth = 1;
386 + irq_desc[i].handler = &brcm_irq_type;
387 + }
388 +
389 + set_except_vector(0, brcmIRQ);
390 + change_c0_status(ST0_IM, ALLINTS);
391 +
392 +#ifdef CONFIG_REMOTE_DEBUG
393 + printk("Breaking into debugger...\n");
394 + set_debug_traps();
395 + breakpoint();
396 +#endif
397 +}
398 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
399 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
400 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2005-11-07 23:58:34.968754500 +0100
401 @@ -0,0 +1,158 @@
402 +/*
403 + * GPIO char driver
404 + *
405 + * Copyright 2005, Broadcom Corporation
406 + * All Rights Reserved.
407 + *
408 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
409 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
410 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
411 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
412 + *
413 + * $Id$
414 + */
415 +
416 +#include <linux/module.h>
417 +#include <linux/init.h>
418 +#include <linux/fs.h>
419 +#include <linux/miscdevice.h>
420 +#include <asm/uaccess.h>
421 +
422 +#include <typedefs.h>
423 +#include <bcmutils.h>
424 +#include <sbutils.h>
425 +#include <bcmdevs.h>
426 +
427 +static sb_t *gpio_sbh;
428 +static int gpio_major;
429 +static devfs_handle_t gpio_dir;
430 +static struct {
431 + char *name;
432 + devfs_handle_t handle;
433 +} gpio_file[] = {
434 + { "in", NULL },
435 + { "out", NULL },
436 + { "outen", NULL },
437 + { "control", NULL }
438 +};
439 +
440 +static int
441 +gpio_open(struct inode *inode, struct file * file)
442 +{
443 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
444 + return -ENODEV;
445 +
446 + MOD_INC_USE_COUNT;
447 + return 0;
448 +}
449 +
450 +static int
451 +gpio_release(struct inode *inode, struct file * file)
452 +{
453 + MOD_DEC_USE_COUNT;
454 + return 0;
455 +}
456 +
457 +static ssize_t
458 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
459 +{
460 + u32 val;
461 +
462 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
463 + case 0:
464 + val = sb_gpioin(gpio_sbh);
465 + break;
466 + case 1:
467 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
468 + break;
469 + case 2:
470 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
471 + break;
472 + case 3:
473 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
474 + break;
475 + default:
476 + return -ENODEV;
477 + }
478 +
479 + if (put_user(val, (u32 *) buf))
480 + return -EFAULT;
481 +
482 + return sizeof(val);
483 +}
484 +
485 +static ssize_t
486 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
487 +{
488 + u32 val;
489 +
490 + if (get_user(val, (u32 *) buf))
491 + return -EFAULT;
492 +
493 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
494 + case 0:
495 + return -EACCES;
496 + case 1:
497 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
498 + break;
499 + case 2:
500 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
501 + break;
502 + case 3:
503 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
504 + break;
505 + default:
506 + return -ENODEV;
507 + }
508 +
509 + return sizeof(val);
510 +}
511 +
512 +static struct file_operations gpio_fops = {
513 + owner: THIS_MODULE,
514 + open: gpio_open,
515 + release: gpio_release,
516 + read: gpio_read,
517 + write: gpio_write,
518 +};
519 +
520 +static int __init
521 +gpio_init(void)
522 +{
523 + int i;
524 +
525 + if (!(gpio_sbh = sb_kattach()))
526 + return -ENODEV;
527 +
528 + sb_gpiosetcore(gpio_sbh);
529 +
530 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
531 + return gpio_major;
532 +
533 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
534 +
535 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
536 + gpio_file[i].handle = devfs_register(gpio_dir,
537 + gpio_file[i].name,
538 + DEVFS_FL_DEFAULT, gpio_major, i,
539 + S_IFCHR | S_IRUGO | S_IWUGO,
540 + &gpio_fops, NULL);
541 + }
542 +
543 + return 0;
544 +}
545 +
546 +static void __exit
547 +gpio_exit(void)
548 +{
549 + int i;
550 +
551 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
552 + devfs_unregister(gpio_file[i].handle);
553 + devfs_unregister(gpio_dir);
554 + devfs_unregister_chrdev(gpio_major, "gpio");
555 + sb_detach(gpio_sbh);
556 +}
557 +
558 +module_init(gpio_init);
559 +module_exit(gpio_exit);
560 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
561 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
562 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-11-07 22:51:38.772725750 +0100
563 @@ -0,0 +1,391 @@
564 +/*
565 + * Broadcom device-specific manifest constants.
566 + *
567 + * Copyright 2005, Broadcom Corporation
568 + * All Rights Reserved.
569 + *
570 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
571 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
572 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
573 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
574 + * $Id$
575 + */
576 +
577 +#ifndef _BCMDEVS_H
578 +#define _BCMDEVS_H
579 +
580 +
581 +/* Known PCI vendor Id's */
582 +#define VENDOR_EPIGRAM 0xfeda
583 +#define VENDOR_BROADCOM 0x14e4
584 +#define VENDOR_3COM 0x10b7
585 +#define VENDOR_NETGEAR 0x1385
586 +#define VENDOR_DIAMOND 0x1092
587 +#define VENDOR_DELL 0x1028
588 +#define VENDOR_HP 0x0e11
589 +#define VENDOR_APPLE 0x106b
590 +
591 +/* PCI Device Id's */
592 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
593 +#define BCM4211_DEVICE_ID 0x4211
594 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
595 +#define BCM4231_DEVICE_ID 0x4231
596 +
597 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
598 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
599 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
600 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
601 +
602 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
603 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
604 +
605 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
606 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
607 +
608 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
609 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
610 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
611 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
612 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
613 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
614 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
615 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
616 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
617 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
618 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
619 +
620 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
621 +
622 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
623 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
624 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
625 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
626 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
627 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
628 +
629 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
630 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
631 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
632 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
633 +
634 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
635 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
636 +
637 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
638 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
639 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
640 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
641 +
642 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
643 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
644 +#define BCM4306_D11G_ID2 0x4325
645 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
646 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
647 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
648 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
649 +
650 +#define BCM4309_PKG_ID 1 /* 4309 package id */
651 +
652 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
653 +#define BCM4303_PKG_ID 2 /* 4303 package id */
654 +
655 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
656 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
657 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
658 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
659 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
660 +
661 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
662 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
663 +
664 +
665 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
666 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
667 +
668 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
669 +
670 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
671 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
672 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
673 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
674 +
675 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
676 +
677 +/* Address map */
678 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
679 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
680 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
681 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
682 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
683 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
684 +
685 +/* Core register space */
686 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
687 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
688 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
689 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
690 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
691 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
692 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
693 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
694 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
695 +
696 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
697 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
698 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
699 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
700 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
701 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
702 +
703 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
704 +
705 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
706 +
707 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
708 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
709 +
710 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
711 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
712 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
713 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
714 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
715 +
716 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
717 +
718 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
719 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
720 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
721 +
722 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
723 +
724 +/* PCMCIA vendor Id's */
725 +
726 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
727 +
728 +/* SDIO vendor Id's */
729 +#define VENDOR_BROADCOM_SDIO 0x00BF
730 +
731 +
732 +/* boardflags */
733 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
734 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
735 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
736 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
737 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
738 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
739 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
740 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
741 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
742 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
743 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
744 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
745 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
746 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
747 +
748 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
749 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
750 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
751 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
752 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
753 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
754 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
755 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
756 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
757 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
758 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
759 +
760 +/* Bus types */
761 +#define SB_BUS 0 /* Silicon Backplane */
762 +#define PCI_BUS 1 /* PCI target */
763 +#define PCMCIA_BUS 2 /* PCMCIA target */
764 +#define SDIO_BUS 3 /* SDIO target */
765 +#define JTAG_BUS 4 /* JTAG */
766 +
767 +/* Allows optimization for single-bus support */
768 +#ifdef BCMBUSTYPE
769 +#define BUSTYPE(bus) (BCMBUSTYPE)
770 +#else
771 +#define BUSTYPE(bus) (bus)
772 +#endif
773 +
774 +/* power control defines */
775 +#define PLL_DELAY 150 /* us pll on delay */
776 +#define FREF_DELAY 200 /* us fref change delay */
777 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
778 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
779 +
780 +/* Reference Board Types */
781 +
782 +#define BU4710_BOARD 0x0400
783 +#define VSIM4710_BOARD 0x0401
784 +#define QT4710_BOARD 0x0402
785 +
786 +#define BU4610_BOARD 0x0403
787 +#define VSIM4610_BOARD 0x0404
788 +
789 +#define BU4307_BOARD 0x0405
790 +#define BCM94301CB_BOARD 0x0406
791 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
792 +#define BCM94301MP_BOARD 0x0407
793 +#define BCM94307MP_BOARD 0x0408
794 +#define BCMAP4307_BOARD 0x0409
795 +
796 +#define BU4309_BOARD 0x040a
797 +#define BCM94309CB_BOARD 0x040b
798 +#define BCM94309MP_BOARD 0x040c
799 +#define BCM4309AP_BOARD 0x040d
800 +
801 +#define BCM94302MP_BOARD 0x040e
802 +
803 +#define VSIM4310_BOARD 0x040f
804 +#define BU4711_BOARD 0x0410
805 +#define BCM94310U_BOARD 0x0411
806 +#define BCM94310AP_BOARD 0x0412
807 +#define BCM94310MP_BOARD 0x0414
808 +
809 +#define BU4306_BOARD 0x0416
810 +#define BCM94306CB_BOARD 0x0417
811 +#define BCM94306MP_BOARD 0x0418
812 +
813 +#define BCM94710D_BOARD 0x041a
814 +#define BCM94710R1_BOARD 0x041b
815 +#define BCM94710R4_BOARD 0x041c
816 +#define BCM94710AP_BOARD 0x041d
817 +
818 +
819 +#define BU2050_BOARD 0x041f
820 +
821 +
822 +#define BCM94309G_BOARD 0x0421
823 +
824 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
825 +
826 +#define BU4704_BOARD 0x0423
827 +#define BU4702_BOARD 0x0424
828 +
829 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
830 +
831 +#define BU4317_BOARD 0x0426
832 +
833 +
834 +#define BCM94702MN_BOARD 0x0428
835 +
836 +/* BCM4702 1U CompactPCI Board */
837 +#define BCM94702CPCI_BOARD 0x0429
838 +
839 +/* BCM4702 with BCM95380 VLAN Router */
840 +#define BCM95380RR_BOARD 0x042a
841 +
842 +/* cb4306 with SiGe PA */
843 +#define BCM94306CBSG_BOARD 0x042b
844 +
845 +/* mp4301 with 2050 radio */
846 +#define BCM94301MPL_BOARD 0x042c
847 +
848 +/* cb4306 with SiGe PA */
849 +#define PCSG94306_BOARD 0x042d
850 +
851 +/* bu4704 with sdram */
852 +#define BU4704SD_BOARD 0x042e
853 +
854 +/* Dual 11a/11g Router */
855 +#define BCM94704AGR_BOARD 0x042f
856 +
857 +/* 11a-only minipci */
858 +#define BCM94308MP_BOARD 0x0430
859 +
860 +
861 +
862 +/* BCM94317 boards */
863 +#define BCM94317CB_BOARD 0x0440
864 +#define BCM94317MP_BOARD 0x0441
865 +#define BCM94317PCMCIA_BOARD 0x0442
866 +#define BCM94317SDIO_BOARD 0x0443
867 +
868 +#define BU4712_BOARD 0x0444
869 +#define BU4712SD_BOARD 0x045d
870 +#define BU4712L_BOARD 0x045f
871 +
872 +/* BCM4712 boards */
873 +#define BCM94712AP_BOARD 0x0445
874 +#define BCM94712P_BOARD 0x0446
875 +
876 +/* BCM4318 boards */
877 +#define BU4318_BOARD 0x0447
878 +#define CB4318_BOARD 0x0448
879 +#define MPG4318_BOARD 0x0449
880 +#define MP4318_BOARD 0x044a
881 +#define SD4318_BOARD 0x044b
882 +
883 +/* BCM63XX boards */
884 +#define BCM96338_BOARD 0x6338
885 +#define BCM96345_BOARD 0x6345
886 +#define BCM96348_BOARD 0x6348
887 +
888 +/* Another mp4306 with SiGe */
889 +#define BCM94306P_BOARD 0x044c
890 +
891 +/* CF-like 4317 modules */
892 +#define BCM94317CF_BOARD 0x044d
893 +
894 +/* mp4303 */
895 +#define BCM94303MP_BOARD 0x044e
896 +
897 +/* mpsgh4306 */
898 +#define BCM94306MPSGH_BOARD 0x044f
899 +
900 +/* BRCM 4306 w/ Front End Modules */
901 +#define BCM94306MPM 0x0450
902 +#define BCM94306MPL 0x0453
903 +
904 +/* 4712agr */
905 +#define BCM94712AGR_BOARD 0x0451
906 +
907 +/* The real CF 4317 board */
908 +#define CFI4317_BOARD 0x0452
909 +
910 +/* pcmcia 4303 */
911 +#define PC4303_BOARD 0x0454
912 +
913 +/* 5350K */
914 +#define BCM95350K_BOARD 0x0455
915 +
916 +/* 5350R */
917 +#define BCM95350R_BOARD 0x0456
918 +
919 +/* 4306mplna */
920 +#define BCM94306MPLNA_BOARD 0x0457
921 +
922 +/* 4320 boards */
923 +#define BU4320_BOARD 0x0458
924 +#define BU4320S_BOARD 0x0459
925 +#define BCM94320PH_BOARD 0x045a
926 +
927 +/* 4306mph */
928 +#define BCM94306MPH_BOARD 0x045b
929 +
930 +/* 4306pciv */
931 +#define BCM94306PCIV_BOARD 0x045c
932 +
933 +#define BU4712SD_BOARD 0x045d
934 +
935 +#define BCM94320PFLSH_BOARD 0x045e
936 +
937 +#define BU4712L_BOARD 0x045f
938 +#define BCM94712LGR_BOARD 0x0460
939 +#define BCM94320R_BOARD 0x0461
940 +
941 +#define BU5352_BOARD 0x0462
942 +
943 +#define BCM94318MPGH_BOARD 0x0463
944 +
945 +
946 +#define BCM95352GR_BOARD 0x0467
947 +
948 +/* bcm95351agr */
949 +#define BCM95351AGR_BOARD 0x0470
950 +
951 +/* # of GPIO pins */
952 +#define GPIO_NUMPINS 16
953 +
954 +#endif /* _BCMDEVS_H */
955 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
956 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
957 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-11-07 22:51:38.772725750 +0100
958 @@ -0,0 +1,152 @@
959 +/*
960 + * local version of endian.h - byte order defines
961 + *
962 + * Copyright 2005, Broadcom Corporation
963 + * All Rights Reserved.
964 + *
965 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
966 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
967 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
968 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
969 + *
970 + * $Id$
971 +*/
972 +
973 +#ifndef _BCMENDIAN_H_
974 +#define _BCMENDIAN_H_
975 +
976 +#include <typedefs.h>
977 +
978 +/* Byte swap a 16 bit value */
979 +#define BCMSWAP16(val) \
980 + ((uint16)( \
981 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
982 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
983 +
984 +/* Byte swap a 32 bit value */
985 +#define BCMSWAP32(val) \
986 + ((uint32)( \
987 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
988 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
989 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
990 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
991 +
992 +/* 2 Byte swap a 32 bit value */
993 +#define BCMSWAP32BY16(val) \
994 + ((uint32)( \
995 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
996 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
997 +
998 +
999 +static INLINE uint16
1000 +bcmswap16(uint16 val)
1001 +{
1002 + return BCMSWAP16(val);
1003 +}
1004 +
1005 +static INLINE uint32
1006 +bcmswap32(uint32 val)
1007 +{
1008 + return BCMSWAP32(val);
1009 +}
1010 +
1011 +static INLINE uint32
1012 +bcmswap32by16(uint32 val)
1013 +{
1014 + return BCMSWAP32BY16(val);
1015 +}
1016 +
1017 +/* buf - start of buffer of shorts to swap */
1018 +/* len - byte length of buffer */
1019 +static INLINE void
1020 +bcmswap16_buf(uint16 *buf, uint len)
1021 +{
1022 + len = len/2;
1023 +
1024 + while(len--){
1025 + *buf = bcmswap16(*buf);
1026 + buf++;
1027 + }
1028 +}
1029 +
1030 +#ifndef hton16
1031 +#ifndef IL_BIGENDIAN
1032 +#define HTON16(i) BCMSWAP16(i)
1033 +#define hton16(i) bcmswap16(i)
1034 +#define hton32(i) bcmswap32(i)
1035 +#define ntoh16(i) bcmswap16(i)
1036 +#define ntoh32(i) bcmswap32(i)
1037 +#define ltoh16(i) (i)
1038 +#define ltoh32(i) (i)
1039 +#define htol16(i) (i)
1040 +#define htol32(i) (i)
1041 +#else
1042 +#define HTON16(i) (i)
1043 +#define hton16(i) (i)
1044 +#define hton32(i) (i)
1045 +#define ntoh16(i) (i)
1046 +#define ntoh32(i) (i)
1047 +#define ltoh16(i) bcmswap16(i)
1048 +#define ltoh32(i) bcmswap32(i)
1049 +#define htol16(i) bcmswap16(i)
1050 +#define htol32(i) bcmswap32(i)
1051 +#endif
1052 +#endif
1053 +
1054 +#ifndef IL_BIGENDIAN
1055 +#define ltoh16_buf(buf, i)
1056 +#define htol16_buf(buf, i)
1057 +#else
1058 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1059 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1060 +#endif
1061 +
1062 +/*
1063 +* load 16-bit value from unaligned little endian byte array.
1064 +*/
1065 +static INLINE uint16
1066 +ltoh16_ua(uint8 *bytes)
1067 +{
1068 + return (bytes[1]<<8)+bytes[0];
1069 +}
1070 +
1071 +/*
1072 +* load 32-bit value from unaligned little endian byte array.
1073 +*/
1074 +static INLINE uint32
1075 +ltoh32_ua(uint8 *bytes)
1076 +{
1077 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
1078 +}
1079 +
1080 +/*
1081 +* load 16-bit value from unaligned big(network) endian byte array.
1082 +*/
1083 +static INLINE uint16
1084 +ntoh16_ua(uint8 *bytes)
1085 +{
1086 + return (bytes[0]<<8)+bytes[1];
1087 +}
1088 +
1089 +/*
1090 +* load 32-bit value from unaligned big(network) endian byte array.
1091 +*/
1092 +static INLINE uint32
1093 +ntoh32_ua(uint8 *bytes)
1094 +{
1095 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
1096 +}
1097 +
1098 +#define ltoh_ua(ptr) ( \
1099 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1100 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
1101 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
1102 +)
1103 +
1104 +#define ntoh_ua(ptr) ( \
1105 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1106 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
1107 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
1108 +)
1109 +
1110 +#endif /* _BCMENDIAN_H_ */
1111 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h
1112 --- linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
1113 +++ linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-11-07 22:51:38.772725750 +0100
1114 @@ -0,0 +1,229 @@
1115 +/*
1116 + * Hardware-specific definitions for
1117 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
1118 + *
1119 + * Copyright 2005, Broadcom Corporation
1120 + * All Rights Reserved.
1121 + *
1122 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1123 + * the contents of this file may not be disclosed to third parties, copied
1124 + * or duplicated in any form, in whole or in part, without the prior
1125 + * written permission of Broadcom Corporation.
1126 + * $Id$
1127 + */
1128 +
1129 +#ifndef _bcmenet_47xx_h_
1130 +#define _bcmenet_47xx_h_
1131 +
1132 +#include <bcmenetmib.h>
1133 +#include <bcmenetrxh.h>
1134 +#include <bcmenetphy.h>
1135 +
1136 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
1137 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
1138 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
1139 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
1140 +
1141 +/* power management event wakeup pattern constants */
1142 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
1143 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
1144 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
1145 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
1146 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
1147 +
1148 +/* cpp contortions to concatenate w/arg prescan */
1149 +#ifndef PAD
1150 +#define _PADLINE(line) pad ## line
1151 +#define _XSTR(line) _PADLINE(line)
1152 +#define PAD _XSTR(__LINE__)
1153 +#endif /* PAD */
1154 +
1155 +/*
1156 + * Host Interface Registers
1157 + */
1158 +typedef volatile struct _bcmenettregs {
1159 + /* Device and Power Control */
1160 + uint32 devcontrol;
1161 + uint32 PAD[2];
1162 + uint32 biststatus;
1163 + uint32 wakeuplength;
1164 + uint32 PAD[3];
1165 +
1166 + /* Interrupt Control */
1167 + uint32 intstatus;
1168 + uint32 intmask;
1169 + uint32 gptimer;
1170 + uint32 PAD[23];
1171 +
1172 + /* Ethernet MAC Address Filtering Control */
1173 + uint32 PAD[2];
1174 + uint32 enetftaddr;
1175 + uint32 enetftdata;
1176 + uint32 PAD[2];
1177 +
1178 + /* Ethernet MAC Control */
1179 + uint32 emactxmaxburstlen;
1180 + uint32 emacrxmaxburstlen;
1181 + uint32 emaccontrol;
1182 + uint32 emacflowcontrol;
1183 +
1184 + uint32 PAD[20];
1185 +
1186 + /* DMA Lazy Interrupt Control */
1187 + uint32 intrecvlazy;
1188 + uint32 PAD[63];
1189 +
1190 + /* DMA engine */
1191 + dma32regp_t dmaregs;
1192 + dma32diag_t dmafifo;
1193 + uint32 PAD[116];
1194 +
1195 + /* EMAC Registers */
1196 + uint32 rxconfig;
1197 + uint32 rxmaxlength;
1198 + uint32 txmaxlength;
1199 + uint32 PAD;
1200 + uint32 mdiocontrol;
1201 + uint32 mdiodata;
1202 + uint32 emacintmask;
1203 + uint32 emacintstatus;
1204 + uint32 camdatalo;
1205 + uint32 camdatahi;
1206 + uint32 camcontrol;
1207 + uint32 enetcontrol;
1208 + uint32 txcontrol;
1209 + uint32 txwatermark;
1210 + uint32 mibcontrol;
1211 + uint32 PAD[49];
1212 +
1213 + /* EMAC MIB counters */
1214 + bcmenetmib_t mib;
1215 +
1216 + uint32 PAD[585];
1217 +
1218 + /* Sonics SiliconBackplane config registers */
1219 + sbconfig_t sbconfig;
1220 +} bcmenetregs_t;
1221 +
1222 +/* device control */
1223 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
1224 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
1225 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
1226 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
1227 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
1228 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
1229 +#define DC_PA_SHIFT 18
1230 +#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
1231 +#define DC_FS_SHIFT 23
1232 +#define DC_FS_4K 0 /* 4Kbytes */
1233 +#define DC_FS_512 1 /* 512bytes */
1234 +
1235 +/* wakeup length */
1236 +#define WL_P0_MASK 0x7f /* pattern 0 */
1237 +#define WL_D0 ((uint32)1 << 7)
1238 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
1239 +#define WL_P1_SHIFT 8
1240 +#define WL_D1 ((uint32)1 << 15)
1241 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
1242 +#define WL_P2_SHIFT 16
1243 +#define WL_D2 ((uint32)1 << 23)
1244 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
1245 +#define WL_P3_SHIFT 24
1246 +#define WL_D3 ((uint32)1 << 31)
1247 +
1248 +/* intstatus and intmask */
1249 +#define I_PME ((uint32)1 << 6) /* power management event */
1250 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
1251 +#define I_PC ((uint32)1 << 10) /* descriptor error */
1252 +#define I_PD ((uint32)1 << 11) /* data error */
1253 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
1254 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
1255 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
1256 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
1257 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
1258 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
1259 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
1260 +#define I_MW ((uint32)1 << 27) /* mii write */
1261 +#define I_MR ((uint32)1 << 28) /* mii read */
1262 +
1263 +/* emaccontrol */
1264 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
1265 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
1266 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
1267 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
1268 +#define EMC_LC_SHIFT 5
1269 +
1270 +/* emacflowcontrol */
1271 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
1272 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
1273 +
1274 +/* interrupt receive lazy */
1275 +#define IRL_TO_MASK 0x00ffffff /* timeout */
1276 +#define IRL_FC_MASK 0xff000000 /* frame count */
1277 +#define IRL_FC_SHIFT 24 /* frame count */
1278 +
1279 +/* emac receive config */
1280 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
1281 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
1282 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
1283 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
1284 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
1285 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
1286 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
1287 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
1288 +#define ERC_CA ((uint32)1 << 8) /* cam absent */
1289 +
1290 +/* emac mdio control */
1291 +#define MC_MF_MASK 0x7f /* mdc frequency */
1292 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
1293 +
1294 +/* emac mdio data */
1295 +#define MD_DATA_MASK 0xffff /* r/w data */
1296 +#define MD_TA_MASK 0x30000 /* turnaround value */
1297 +#define MD_TA_SHIFT 16
1298 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
1299 +#define MD_RA_MASK 0x7c0000 /* register address */
1300 +#define MD_RA_SHIFT 18
1301 +#define MD_PMD_MASK 0xf800000 /* physical media device */
1302 +#define MD_PMD_SHIFT 23
1303 +#define MD_OP_MASK 0x30000000 /* opcode */
1304 +#define MD_OP_SHIFT 28
1305 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
1306 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
1307 +#define MD_SB_MASK 0xc0000000 /* start bits */
1308 +#define MD_SB_SHIFT 30
1309 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
1310 +
1311 +/* emac intstatus and intmask */
1312 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
1313 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
1314 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
1315 +
1316 +/* emac cam data high */
1317 +#define CD_V ((uint32)1 << 16) /* valid bit */
1318 +
1319 +/* emac cam control */
1320 +#define CC_CE ((uint32)1 << 0) /* cam enable */
1321 +#define CC_MS ((uint32)1 << 1) /* mask select */
1322 +#define CC_RD ((uint32)1 << 2) /* read */
1323 +#define CC_WR ((uint32)1 << 3) /* write */
1324 +#define CC_INDEX_MASK 0x3f0000 /* index */
1325 +#define CC_INDEX_SHIFT 16
1326 +#define CC_CB ((uint32)1 << 31) /* cam busy */
1327 +
1328 +/* emac ethernet control */
1329 +#define EC_EE ((uint32)1 << 0) /* emac enable */
1330 +#define EC_ED ((uint32)1 << 1) /* emac disable */
1331 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
1332 +#define EC_EP ((uint32)1 << 3) /* external phy select */
1333 +
1334 +/* emac transmit control */
1335 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
1336 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
1337 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
1338 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
1339 +
1340 +/* emac mib control */
1341 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
1342 +
1343 +#endif /* _bcmenet_47xx_h_ */
1344 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetmib.h linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h
1345 --- linux.old/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
1346 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h 2005-11-07 21:57:07.845585750 +0100
1347 @@ -0,0 +1,81 @@
1348 +/*
1349 + * Hardware-specific MIB definition for
1350 + * Broadcom Home Networking Division
1351 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1352 + *
1353 + * Copyright 2005, Broadcom Corporation
1354 + * All Rights Reserved.
1355 + *
1356 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1357 + * the contents of this file may not be disclosed to third parties, copied
1358 + * or duplicated in any form, in whole or in part, without the prior
1359 + * written permission of Broadcom Corporation.
1360 + * $Id$
1361 + */
1362 +
1363 +#ifndef _bcmenetmib_h_
1364 +#define _bcmenetmib_h_
1365 +
1366 +/* cpp contortions to concatenate w/arg prescan */
1367 +#ifndef PAD
1368 +#define _PADLINE(line) pad ## line
1369 +#define _XSTR(line) _PADLINE(line)
1370 +#define PAD _XSTR(__LINE__)
1371 +#endif /* PAD */
1372 +
1373 +/*
1374 + * EMAC MIB Registers
1375 + */
1376 +typedef volatile struct {
1377 + uint32 tx_good_octets;
1378 + uint32 tx_good_pkts;
1379 + uint32 tx_octets;
1380 + uint32 tx_pkts;
1381 + uint32 tx_broadcast_pkts;
1382 + uint32 tx_multicast_pkts;
1383 + uint32 tx_len_64;
1384 + uint32 tx_len_65_to_127;
1385 + uint32 tx_len_128_to_255;
1386 + uint32 tx_len_256_to_511;
1387 + uint32 tx_len_512_to_1023;
1388 + uint32 tx_len_1024_to_max;
1389 + uint32 tx_jabber_pkts;
1390 + uint32 tx_oversize_pkts;
1391 + uint32 tx_fragment_pkts;
1392 + uint32 tx_underruns;
1393 + uint32 tx_total_cols;
1394 + uint32 tx_single_cols;
1395 + uint32 tx_multiple_cols;
1396 + uint32 tx_excessive_cols;
1397 + uint32 tx_late_cols;
1398 + uint32 tx_defered;
1399 + uint32 tx_carrier_lost;
1400 + uint32 tx_pause_pkts;
1401 + uint32 PAD[8];
1402 +
1403 + uint32 rx_good_octets;
1404 + uint32 rx_good_pkts;
1405 + uint32 rx_octets;
1406 + uint32 rx_pkts;
1407 + uint32 rx_broadcast_pkts;
1408 + uint32 rx_multicast_pkts;
1409 + uint32 rx_len_64;
1410 + uint32 rx_len_65_to_127;
1411 + uint32 rx_len_128_to_255;
1412 + uint32 rx_len_256_to_511;
1413 + uint32 rx_len_512_to_1023;
1414 + uint32 rx_len_1024_to_max;
1415 + uint32 rx_jabber_pkts;
1416 + uint32 rx_oversize_pkts;
1417 + uint32 rx_fragment_pkts;
1418 + uint32 rx_missed_pkts;
1419 + uint32 rx_crc_align_errs;
1420 + uint32 rx_undersize;
1421 + uint32 rx_crc_errs;
1422 + uint32 rx_align_errs;
1423 + uint32 rx_symbol_errs;
1424 + uint32 rx_pause_pkts;
1425 + uint32 rx_nonpause_pkts;
1426 +} bcmenetmib_t;
1427 +
1428 +#endif /* _bcmenetmib_h_ */
1429 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetphy.h linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h
1430 --- linux.old/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
1431 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h 2005-11-07 21:57:07.845585750 +0100
1432 @@ -0,0 +1,58 @@
1433 +/*
1434 + * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
1435 + *
1436 + * Copyright 2005, Broadcom Corporation
1437 + * All Rights Reserved.
1438 + *
1439 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1440 + * the contents of this file may not be disclosed to third parties, copied
1441 + * or duplicated in any form, in whole or in part, without the prior
1442 + * written permission of Broadcom Corporation.
1443 + * $Id$
1444 + */
1445 +
1446 +#ifndef _bcmenetphy_h_
1447 +#define _bcmenetphy_h_
1448 +
1449 +/* phy address */
1450 +#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
1451 +#define EPHY_MASK 0x1f
1452 +#define EPHY_NONE 31 /* nvram: no phy present at all */
1453 +#define EPHY_NOREG 30 /* nvram: no local phy regs */
1454 +
1455 +/* just a few phy registers */
1456 +#define CTL_RESET (1 << 15) /* reset */
1457 +#define CTL_LOOP (1 << 14) /* loopback */
1458 +#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
1459 +#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
1460 +#define CTL_RESTART (1 << 9) /* restart autonegotiation */
1461 +#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
1462 +
1463 +#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
1464 +#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
1465 +#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
1466 +#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
1467 +
1468 +/* link partner ability register */
1469 +#define LPA_SLCT 0x001f /* same as advertise selector */
1470 +#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
1471 +#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
1472 +#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
1473 +#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
1474 +#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
1475 +#define LPA_RESV 0x1c00 /* unused */
1476 +#define LPA_RFAULT 0x2000 /* link partner faulted */
1477 +#define LPA_LPACK 0x4000 /* link partner acked us */
1478 +#define LPA_NPAGE 0x8000 /* next page bit */
1479 +
1480 +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
1481 +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
1482 +
1483 +#define STAT_REMFAULT (1 << 4) /* remote fault */
1484 +#define STAT_LINK (1 << 2) /* link status */
1485 +#define STAT_JAB (1 << 1) /* jabber detected */
1486 +#define AUX_FORCED (1 << 2) /* forced 10/100 */
1487 +#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
1488 +#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
1489 +
1490 +#endif /* _bcmenetphy_h_ */
1491 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h
1492 --- linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
1493 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-11-07 21:57:07.845585750 +0100
1494 @@ -0,0 +1,43 @@
1495 +/*
1496 + * Hardware-specific Receive Data Header for the
1497 + * Broadcom Home Networking Division
1498 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1499 + *
1500 + * Copyright 2005, Broadcom Corporation
1501 + * All Rights Reserved.
1502 + *
1503 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1504 + * the contents of this file may not be disclosed to third parties, copied
1505 + * or duplicated in any form, in whole or in part, without the prior
1506 + * written permission of Broadcom Corporation.
1507 + * $Id$
1508 + */
1509 +
1510 +#ifndef _bcmenetrxh_h_
1511 +#define _bcmenetrxh_h_
1512 +
1513 +/*
1514 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
1515 + * with every frame consisting of
1516 + * 16bits of frame length, followed by
1517 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
1518 + */
1519 +typedef volatile struct {
1520 + uint16 len;
1521 + uint16 flags;
1522 + uint16 pad[12];
1523 +} bcmenetrxh_t;
1524 +
1525 +#define RXHDR_LEN 28
1526 +
1527 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
1528 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
1529 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
1530 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
1531 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
1532 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
1533 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
1534 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
1535 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
1536 +
1537 +#endif /* _bcmenetrxh_h_ */
1538 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
1539 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1540 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-11-07 22:51:38.772725750 +0100
1541 @@ -0,0 +1,141 @@
1542 +/*
1543 + * NVRAM variable manipulation
1544 + *
1545 + * Copyright 2005, Broadcom Corporation
1546 + * All Rights Reserved.
1547 + *
1548 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1549 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1550 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1551 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1552 + *
1553 + * $Id$
1554 + */
1555 +
1556 +#ifndef _bcmnvram_h_
1557 +#define _bcmnvram_h_
1558 +
1559 +#ifndef _LANGUAGE_ASSEMBLY
1560 +
1561 +#include <typedefs.h>
1562 +
1563 +struct nvram_header {
1564 + uint32 magic;
1565 + uint32 len;
1566 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
1567 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
1568 + uint32 config_ncdl; /* ncdl values for memc */
1569 +};
1570 +
1571 +struct nvram_tuple {
1572 + char *name;
1573 + char *value;
1574 + struct nvram_tuple *next;
1575 +};
1576 +
1577 +/*
1578 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1579 + * platforms.
1580 + */
1581 +extern int BCMINIT(nvram_init)(void *sbh);
1582 +
1583 +/*
1584 + * Disable NVRAM access. May be unnecessary or undefined on certain
1585 + * platforms.
1586 + */
1587 +extern void BCMINIT(nvram_exit)(void *sbh);
1588 +
1589 +/*
1590 + * Get the value of an NVRAM variable. The pointer returned may be
1591 + * invalid after a set.
1592 + * @param name name of variable to get
1593 + * @return value of variable or NULL if undefined
1594 + */
1595 +extern char * BCMINIT(nvram_get)(const char *name);
1596 +
1597 +/*
1598 + * Read the reset GPIO value from the nvram and set the GPIO
1599 + * as input
1600 + */
1601 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
1602 +
1603 +/*
1604 + * Get the value of an NVRAM variable.
1605 + * @param name name of variable to get
1606 + * @return value of variable or NUL if undefined
1607 + */
1608 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1609 +
1610 +/*
1611 + * Match an NVRAM variable.
1612 + * @param name name of variable to match
1613 + * @param match value to compare against value of variable
1614 + * @return TRUE if variable is defined and its value is string equal
1615 + * to match or FALSE otherwise
1616 + */
1617 +static INLINE int
1618 +nvram_match(char *name, char *match) {
1619 + const char *value = BCMINIT(nvram_get)(name);
1620 + return (value && !strcmp(value, match));
1621 +}
1622 +
1623 +/*
1624 + * Inversely match an NVRAM variable.
1625 + * @param name name of variable to match
1626 + * @param match value to compare against value of variable
1627 + * @return TRUE if variable is defined and its value is not string
1628 + * equal to invmatch or FALSE otherwise
1629 + */
1630 +static INLINE int
1631 +nvram_invmatch(char *name, char *invmatch) {
1632 + const char *value = BCMINIT(nvram_get)(name);
1633 + return (value && strcmp(value, invmatch));
1634 +}
1635 +
1636 +/*
1637 + * Set the value of an NVRAM variable. The name and value strings are
1638 + * copied into private storage. Pointers to previously set values
1639 + * may become invalid. The new value may be immediately
1640 + * retrieved but will not be permanently stored until a commit.
1641 + * @param name name of variable to set
1642 + * @param value value of variable
1643 + * @return 0 on success and errno on failure
1644 + */
1645 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1646 +
1647 +/*
1648 + * Unset an NVRAM variable. Pointers to previously set values
1649 + * remain valid until a set.
1650 + * @param name name of variable to unset
1651 + * @return 0 on success and errno on failure
1652 + * NOTE: use nvram_commit to commit this change to flash.
1653 + */
1654 +extern int BCMINIT(nvram_unset)(const char *name);
1655 +
1656 +/*
1657 + * Commit NVRAM variables to permanent storage. All pointers to values
1658 + * may be invalid after a commit.
1659 + * NVRAM values are undefined after a commit.
1660 + * @return 0 on success and errno on failure
1661 + */
1662 +extern int BCMINIT(nvram_commit)(void);
1663 +
1664 +/*
1665 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1666 + * @param buf buffer to store variables
1667 + * @param count size of buffer in bytes
1668 + * @return 0 on success and errno on failure
1669 + */
1670 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1671 +
1672 +#endif /* _LANGUAGE_ASSEMBLY */
1673 +
1674 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1675 +#define NVRAM_VERSION 1
1676 +#define NVRAM_HEADER_SIZE 20
1677 +#define NVRAM_SPACE 0x8000
1678 +
1679 +#define NVRAM_MAX_VALUE_LEN 255
1680 +#define NVRAM_MAX_PARAM_LEN 64
1681 +
1682 +#endif /* _bcmnvram_h_ */
1683 diff -urN linux.old/arch/mips/bcm947xx/include/bcmparams.h linux.dev/arch/mips/bcm947xx/include/bcmparams.h
1684 --- linux.old/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
1685 +++ linux.dev/arch/mips/bcm947xx/include/bcmparams.h 2005-11-07 22:51:38.776726000 +0100
1686 @@ -0,0 +1,25 @@
1687 +/*
1688 + * Misc system wide parameters.
1689 + *
1690 + * Copyright 2005, Broadcom Corporation
1691 + * All Rights Reserved.
1692 + *
1693 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1694 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1695 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1696 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1697 + * $Id$
1698 + */
1699 +
1700 +#ifndef _bcmparams_h_
1701 +#define _bcmparams_h_
1702 +
1703 +#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
1704 +
1705 +#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
1706 +
1707 +#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
1708 +
1709 +#define WL_MAXBSSCFG 16 /* maximum number of BSS Configs we can configure */
1710 +
1711 +#endif
1712 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
1713 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1714 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-11-07 22:51:38.776726000 +0100
1715 @@ -0,0 +1,23 @@
1716 +/*
1717 + * Misc useful routines to access NIC local SROM/OTP .
1718 + *
1719 + * Copyright 2005, Broadcom Corporation
1720 + * All Rights Reserved.
1721 + *
1722 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1723 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1724 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1725 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1726 + *
1727 + * $Id$
1728 + */
1729 +
1730 +#ifndef _bcmsrom_h_
1731 +#define _bcmsrom_h_
1732 +
1733 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
1734 +
1735 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1736 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1737 +
1738 +#endif /* _bcmsrom_h_ */
1739 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
1740 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1741 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-11-07 22:51:38.776726000 +0100
1742 @@ -0,0 +1,313 @@
1743 +/*
1744 + * Misc useful os-independent macros and functions.
1745 + *
1746 + * Copyright 2005, Broadcom Corporation
1747 + * All Rights Reserved.
1748 + *
1749 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1750 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1751 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1752 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1753 + * $Id$
1754 + */
1755 +
1756 +#ifndef _bcmutils_h_
1757 +#define _bcmutils_h_
1758 +
1759 +/*** driver-only section ***/
1760 +#ifdef BCMDRIVER
1761 +#include <osl.h>
1762 +
1763 +#define _BCM_U 0x01 /* upper */
1764 +#define _BCM_L 0x02 /* lower */
1765 +#define _BCM_D 0x04 /* digit */
1766 +#define _BCM_C 0x08 /* cntrl */
1767 +#define _BCM_P 0x10 /* punct */
1768 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1769 +#define _BCM_X 0x40 /* hex digit */
1770 +#define _BCM_SP 0x80 /* hard space (0x20) */
1771 +
1772 +#define GPIO_PIN_NOTDEFINED 0x20
1773 +
1774 +extern unsigned char bcm_ctype[];
1775 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1776 +
1777 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1778 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1779 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1780 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1781 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1782 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1783 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1784 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1785 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1786 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1787 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1788 +
1789 +/*
1790 + * Spin at most 'us' microseconds while 'exp' is true.
1791 + * Caller should explicitly test 'exp' when this completes
1792 + * and take appropriate error action if 'exp' is still true.
1793 + */
1794 +#define SPINWAIT(exp, us) { \
1795 + uint countdown = (us) + 9; \
1796 + while ((exp) && (countdown >= 10)) {\
1797 + OSL_DELAY(10); \
1798 + countdown -= 10; \
1799 + } \
1800 +}
1801 +
1802 +/* generic osl packet queue */
1803 +struct pktq {
1804 + void *head; /* first packet to dequeue */
1805 + void *tail; /* last packet to dequeue */
1806 + uint len; /* number of queued packets */
1807 + uint maxlen; /* maximum number of queued packets */
1808 + bool priority; /* enqueue by packet priority */
1809 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1810 +};
1811 +#define DEFAULT_QLEN 128
1812 +
1813 +#define pktq_len(q) ((q)->len)
1814 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1815 +#define pktq_head(q) ((q)->head)
1816 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1817 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1818 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1819 +
1820 +/* externs */
1821 +/* packet */
1822 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
1823 +extern uint pkttotlen(osl_t *osh, void *);
1824 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1825 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1826 +extern void *pktdeq(struct pktq *q);
1827 +extern void *pktdeqtail(struct pktq *q);
1828 +/* string */
1829 +extern uint bcm_atoi(char *s);
1830 +extern uchar bcm_toupper(uchar c);
1831 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1832 +extern char *bcmstrstr(char *haystack, char *needle);
1833 +extern char *bcmstrcat(char *dest, const char *src);
1834 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1835 +/* ethernet address */
1836 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1837 +extern int bcm_ether_atoe(char *p, char *ea);
1838 +/* delay */
1839 +extern void bcm_mdelay(uint ms);
1840 +/* variable access */
1841 +extern char *getvar(char *vars, char *name);
1842 +extern int getintvar(char *vars, char *name);
1843 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1844 +#define bcmlog(fmt, a1, a2)
1845 +#define bcmdumplog(buf, size) *buf = '\0'
1846 +#define bcmdumplogent(buf, idx) -1
1847 +
1848 +#endif /* #ifdef BCMDRIVER */
1849 +
1850 +/*** driver/apps-shared section ***/
1851 +
1852 +#define BCME_STRLEN 64
1853 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
1854 +
1855 +
1856 +/*
1857 + * error codes could be added but the defined ones shouldn't be changed/deleted
1858 + * these error codes are exposed to the user code
1859 + * when ever a new error code is added to this list
1860 + * please update errorstring table with the related error string and
1861 + * update osl files with os specific errorcode map
1862 +*/
1863 +
1864 +#define BCME_ERROR -1 /* Error generic */
1865 +#define BCME_BADARG -2 /* Bad Argument */
1866 +#define BCME_BADOPTION -3 /* Bad option */
1867 +#define BCME_NOTUP -4 /* Not up */
1868 +#define BCME_NOTDOWN -5 /* Not down */
1869 +#define BCME_NOTAP -6 /* Not AP */
1870 +#define BCME_NOTSTA -7 /* Not STA */
1871 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
1872 +#define BCME_RADIOOFF -9 /* Radio Off */
1873 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
1874 +#define BCME_NOCLK -11 /* No Clock*/
1875 +#define BCME_BADRATESET -12 /* BAD RateSet*/
1876 +#define BCME_BADBAND -13 /* BAD Band */
1877 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
1878 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
1879 +#define BCME_BUSY -16 /* Busy*/
1880 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
1881 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
1882 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
1883 +#define BCME_BADCHAN -20 /* BAD Channel */
1884 +#define BCME_BADADDR -21 /* BAD Address*/
1885 +#define BCME_NORESOURCE -22 /* No resources*/
1886 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
1887 +#define BCME_BADLEN -24 /* Bad Length*/
1888 +#define BCME_NOTREADY -25 /* Not ready Yet*/
1889 +#define BCME_EPERM -26 /* Not Permitted */
1890 +#define BCME_NOMEM -27 /* No Memory */
1891 +#define BCME_ASSOCIATED -28 /* Associated */
1892 +#define BCME_RANGE -29 /* Range Error*/
1893 +#define BCME_NOTFOUND -30 /* Not found */
1894 +#define BCME_LAST BCME_NOTFOUND
1895 +
1896 +#ifndef ABS
1897 +#define ABS(a) (((a)<0)?-(a):(a))
1898 +#endif
1899 +
1900 +#ifndef MIN
1901 +#define MIN(a, b) (((a)<(b))?(a):(b))
1902 +#endif
1903 +
1904 +#ifndef MAX
1905 +#define MAX(a, b) (((a)>(b))?(a):(b))
1906 +#endif
1907 +
1908 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1909 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1910 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1911 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1912 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
1913 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1914 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1915 +
1916 +/* bit map related macros */
1917 +#ifndef setbit
1918 +#define NBBY 8 /* 8 bits per byte */
1919 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1920 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1921 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1922 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1923 +#endif
1924 +
1925 +#define NBITS(type) (sizeof(type) * 8)
1926 +#define NBITVAL(bits) (1 << (bits))
1927 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
1928 +
1929 +/* crc defines */
1930 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1931 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1932 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1933 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1934 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1935 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1936 +
1937 +/* bcm_format_flags() bit description structure */
1938 +typedef struct bcm_bit_desc {
1939 + uint32 bit;
1940 + char* name;
1941 +} bcm_bit_desc_t;
1942 +
1943 +/* tag_ID/length/value_buffer tuple */
1944 +typedef struct bcm_tlv {
1945 + uint8 id;
1946 + uint8 len;
1947 + uint8 data[1];
1948 +} bcm_tlv_t;
1949 +
1950 +/* Check that bcm_tlv_t fits into the given buflen */
1951 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
1952 +
1953 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1954 +#define ETHER_ADDR_STR_LEN 18
1955 +
1956 +/* unaligned load and store macros */
1957 +#ifdef IL_BIGENDIAN
1958 +static INLINE uint32
1959 +load32_ua(uint8 *a)
1960 +{
1961 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1962 +}
1963 +
1964 +static INLINE void
1965 +store32_ua(uint8 *a, uint32 v)
1966 +{
1967 + a[0] = (v >> 24) & 0xff;
1968 + a[1] = (v >> 16) & 0xff;
1969 + a[2] = (v >> 8) & 0xff;
1970 + a[3] = v & 0xff;
1971 +}
1972 +
1973 +static INLINE uint16
1974 +load16_ua(uint8 *a)
1975 +{
1976 + return ((a[0] << 8) | a[1]);
1977 +}
1978 +
1979 +static INLINE void
1980 +store16_ua(uint8 *a, uint16 v)
1981 +{
1982 + a[0] = (v >> 8) & 0xff;
1983 + a[1] = v & 0xff;
1984 +}
1985 +
1986 +#else
1987 +
1988 +static INLINE uint32
1989 +load32_ua(uint8 *a)
1990 +{
1991 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
1992 +}
1993 +
1994 +static INLINE void
1995 +store32_ua(uint8 *a, uint32 v)
1996 +{
1997 + a[3] = (v >> 24) & 0xff;
1998 + a[2] = (v >> 16) & 0xff;
1999 + a[1] = (v >> 8) & 0xff;
2000 + a[0] = v & 0xff;
2001 +}
2002 +
2003 +static INLINE uint16
2004 +load16_ua(uint8 *a)
2005 +{
2006 + return ((a[1] << 8) | a[0]);
2007 +}
2008 +
2009 +static INLINE void
2010 +store16_ua(uint8 *a, uint16 v)
2011 +{
2012 + a[1] = (v >> 8) & 0xff;
2013 + a[0] = v & 0xff;
2014 +}
2015 +
2016 +#endif
2017 +
2018 +/* externs */
2019 +/* crc */
2020 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
2021 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
2022 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
2023 +/* format/print */
2024 +/* IE parsing */
2025 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
2026 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
2027 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
2028 +
2029 +/* bcmerror*/
2030 +extern const char *bcmerrorstr(int bcmerror);
2031 +
2032 +/* multi-bool data type: set of bools, mbool is true if any is set */
2033 +typedef uint32 mbool;
2034 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
2035 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
2036 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
2037 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
2038 +
2039 +/* power conversion */
2040 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
2041 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
2042 +
2043 +/* generic datastruct to help dump routines */
2044 +struct fielddesc {
2045 + char *nameandfmt;
2046 + uint32 offset;
2047 + uint32 len;
2048 +};
2049 +
2050 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
2051 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
2052 +
2053 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
2054 +
2055 +#endif /* _bcmutils_h_ */
2056 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
2057 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
2058 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-11-07 21:57:07.849586000 +0100
2059 @@ -0,0 +1,85 @@
2060 +/*
2061 + * bit manipulation utility functions
2062 + *
2063 + * Copyright 2005, Broadcom Corporation
2064 + * All Rights Reserved.
2065 + *
2066 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2067 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2068 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2069 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2070 + * $Id$
2071 + */
2072 +
2073 +#ifndef _BITFUNCS_H
2074 +#define _BITFUNCS_H
2075 +
2076 +#include <typedefs.h>
2077 +
2078 +/* local prototypes */
2079 +static INLINE uint32 find_msbit(uint32 x);
2080 +
2081 +
2082 +/*
2083 + * find_msbit: returns index of most significant set bit in x, with index
2084 + * range defined as 0-31. NOTE: returns zero if input is zero.
2085 + */
2086 +
2087 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
2088 +
2089 +/*
2090 + * Implementation for Pentium processors and gcc. Note that this
2091 + * instruction is actually very slow on some processors (e.g., family 5,
2092 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
2093 + * implementation instead.
2094 + */
2095 +static INLINE uint32 find_msbit(uint32 x)
2096 +{
2097 + uint msbit;
2098 + __asm__("bsrl %1,%0"
2099 + :"=r" (msbit)
2100 + :"r" (x));
2101 + return msbit;
2102 +}
2103 +
2104 +#else
2105 +
2106 +/*
2107 + * Generic Implementation
2108 + */
2109 +
2110 +#define DB_POW_MASK16 0xffff0000
2111 +#define DB_POW_MASK8 0x0000ff00
2112 +#define DB_POW_MASK4 0x000000f0
2113 +#define DB_POW_MASK2 0x0000000c
2114 +#define DB_POW_MASK1 0x00000002
2115 +
2116 +static INLINE uint32 find_msbit(uint32 x)
2117 +{
2118 + uint32 temp_x = x;
2119 + uint msbit = 0;
2120 + if (temp_x & DB_POW_MASK16) {
2121 + temp_x >>= 16;
2122 + msbit = 16;
2123 + }
2124 + if (temp_x & DB_POW_MASK8) {
2125 + temp_x >>= 8;
2126 + msbit += 8;
2127 + }
2128 + if (temp_x & DB_POW_MASK4) {
2129 + temp_x >>= 4;
2130 + msbit += 4;
2131 + }
2132 + if (temp_x & DB_POW_MASK2) {
2133 + temp_x >>= 2;
2134 + msbit += 2;
2135 + }
2136 + if (temp_x & DB_POW_MASK1) {
2137 + msbit += 1;
2138 + }
2139 + return(msbit);
2140 +}
2141 +
2142 +#endif
2143 +
2144 +#endif /* _BITFUNCS_H */
2145 diff -urN linux.old/arch/mips/bcm947xx/include/cfe_osl.h linux.dev/arch/mips/bcm947xx/include/cfe_osl.h
2146 --- linux.old/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
2147 +++ linux.dev/arch/mips/bcm947xx/include/cfe_osl.h 2005-11-07 22:51:38.776726000 +0100
2148 @@ -0,0 +1,191 @@
2149 +/*
2150 + * CFE boot loader OS Abstraction Layer.
2151 + *
2152 + * Copyright 2005, Broadcom Corporation
2153 + * All Rights Reserved.
2154 + *
2155 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
2156 + * the contents of this file may not be disclosed to third parties, copied
2157 + * or duplicated in any form, in whole or in part, without the prior
2158 + * written permission of Broadcom Corporation.
2159 + *
2160 + * $Id$
2161 + */
2162 +
2163 +#ifndef _cfe_osl_h_
2164 +#define _cfe_osl_h_
2165 +
2166 +#include <lib_types.h>
2167 +#include <lib_string.h>
2168 +#include <lib_printf.h>
2169 +#include <lib_malloc.h>
2170 +#include <cpu_config.h>
2171 +#include <cfe_timer.h>
2172 +#include <cfe_iocb.h>
2173 +#include <cfe_devfuncs.h>
2174 +#include <addrspace.h>
2175 +
2176 +#include <typedefs.h>
2177 +
2178 +/* dump string */
2179 +extern int (*xprinthook)(const char *str);
2180 +#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
2181 +
2182 +/* assert and panic */
2183 +#define ASSERT(exp) do {} while (0)
2184 +
2185 +/* PCMCIA attribute space access macros */
2186 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2187 + bzero(buf, size)
2188 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2189 + do {} while (0)
2190 +
2191 +/* PCI configuration space access macros */
2192 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
2193 + (offset == 8 ? 0 : 0xffffffff)
2194 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
2195 + do {} while (0)
2196 +
2197 +/* PCI device bus # and slot # */
2198 +#define OSL_PCI_BUS(osh) (0)
2199 +#define OSL_PCI_SLOT(osh) (0)
2200 +
2201 +/* register access macros */
2202 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
2203 +#define rreg32(r) (*(volatile uint32*)(r))
2204 +#ifdef IL_BIGENDIAN
2205 +#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
2206 +#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
2207 +#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
2208 +#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
2209 +#else
2210 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
2211 +#define rreg16(r) (*(volatile uint16*)(r))
2212 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
2213 +#define rreg8(r) (*(volatile uint8*)(r))
2214 +#endif
2215 +#define R_REG(r) ({ \
2216 + __typeof(*(r)) __osl_v; \
2217 + switch (sizeof(*(r))) { \
2218 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
2219 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
2220 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
2221 + } \
2222 + __osl_v; \
2223 +})
2224 +#define W_REG(r, v) do { \
2225 + switch (sizeof(*(r))) { \
2226 + case sizeof(uint8): wreg8((r), (v)); break; \
2227 + case sizeof(uint16): wreg16((r), (v)); break; \
2228 + case sizeof(uint32): wreg32((r), (v)); break; \
2229 + } \
2230 +} while (0)
2231 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2232 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2233 +
2234 +/* bcopy, bcmp, and bzero */
2235 +#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
2236 +
2237 +#define osl_attach(pdev) ((osl_t*)pdev)
2238 +#define osl_detach(osh)
2239 +
2240 +/* general purpose memory allocation */
2241 +#define MALLOC(osh, size) KMALLOC((size),0)
2242 +#define MFREE(osh, addr, size) KFREE((addr))
2243 +#define MALLOCED(osh) (0)
2244 +#define MALLOC_DUMP(osh, buf, sz)
2245 +#define MALLOC_FAILED(osh) (0)
2246 +
2247 +/* uncached virtual address */
2248 +#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
2249 +
2250 +/* host/bus architecture-specific address byte swap */
2251 +#define BUS_SWAP32(v) (v)
2252 +
2253 +/* get processor cycle count */
2254 +#define OSL_GETCYCLES(x) ((x) = 0)
2255 +
2256 +/* microsecond delay */
2257 +#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
2258 +
2259 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
2260 +
2261 +/* map/unmap physical to virtual I/O */
2262 +#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
2263 +#define REG_UNMAP(va) do {} while (0)
2264 +
2265 +/* dereference an address that may cause a bus exception */
2266 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
2267 +extern int osl_busprobe(uint32 *val, uint32 addr);
2268 +
2269 +/* allocate/free shared (dma-able) consistent (uncached) memory */
2270 +#define DMA_CONSISTENT_ALIGN 4096
2271 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2272 + osl_dma_alloc_consistent((size), (pap))
2273 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2274 + osl_dma_free_consistent((void*)(va))
2275 +extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
2276 +extern void osl_dma_free_consistent(void *va);
2277 +
2278 +/* map/unmap direction */
2279 +#define DMA_TX 1
2280 +#define DMA_RX 2
2281 +
2282 +/* map/unmap shared (dma-able) memory */
2283 +#define DMA_MAP(osh, va, size, direction, lb) ({ \
2284 + cfe_flushcache(CFE_CACHE_FLUSH_D); \
2285 + PHYSADDR((ulong)(va)); \
2286 +})
2287 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2288 + do {} while (0)
2289 +
2290 +/* shared (dma-able) memory access macros */
2291 +#define R_SM(r) *(r)
2292 +#define W_SM(r, v) (*(r) = (v))
2293 +#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
2294 +
2295 +/* generic packet structure */
2296 +#define LBUFSZ 4096
2297 +#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
2298 +struct lbuf {
2299 + struct lbuf *next; /* pointer to next lbuf if in a chain */
2300 + struct lbuf *link; /* pointer to next lbuf if in a list */
2301 + uchar *head; /* start of buffer */
2302 + uchar *end; /* end of buffer */
2303 + uchar *data; /* start of data */
2304 + uchar *tail; /* end of data */
2305 + uint len; /* nbytes of data */
2306 + void *cookie; /* generic cookie */
2307 +};
2308 +
2309 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2310 +#define PKTBUFSZ 2048
2311 +
2312 +/* packet primitives */
2313 +#define PKTGET(osh, len, send) ((void*)osl_pktget((len)))
2314 +#define PKTFREE(osh, lb, send) osl_pktfree((struct lbuf*)(lb))
2315 +#define PKTDATA(osh, lb) (((struct lbuf*)(lb))->data)
2316 +#define PKTLEN(osh, lb) (((struct lbuf*)(lb))->len)
2317 +#define PKTHEADROOM(osh, lb) (PKTDATA(osh,lb)-(((struct lbuf*)(lb))->head))
2318 +#define PKTTAILROOM(osh, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
2319 +#define PKTNEXT(osh, lb) (((struct lbuf*)(lb))->next)
2320 +#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
2321 +#define PKTSETLEN(osh, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
2322 +#define PKTPUSH(osh, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
2323 +#define PKTPULL(osh, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
2324 +#define PKTDUP(osh, lb) osl_pktdup((struct lbuf*)(lb))
2325 +#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
2326 +#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
2327 +#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
2328 +#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
2329 +#define PKTPRIO(lb) (0)
2330 +#define PKTSETPRIO(lb, x) do {} while (0)
2331 +extern struct lbuf *osl_pktget(uint len);
2332 +extern void osl_pktfree(struct lbuf *lb);
2333 +extern void osl_pktsetlen(struct lbuf *lb, uint len);
2334 +extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
2335 +extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
2336 +extern struct lbuf *osl_pktdup(struct lbuf *lb);
2337 +extern int osl_error(int bcmerror);
2338 +
2339 +#endif /* _cfe_osl_h_ */
2340 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h linux.dev/arch/mips/bcm947xx/include/epivers.h
2341 --- linux.old/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
2342 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h 2005-11-07 22:51:38.776726000 +0100
2343 @@ -0,0 +1,69 @@
2344 +/*
2345 + * Copyright 2005, Broadcom Corporation
2346 + * All Rights Reserved.
2347 + *
2348 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2349 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2350 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2351 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2352 + *
2353 + * $Id$
2354 + *
2355 +*/
2356 +
2357 +#ifndef _epivers_h_
2358 +#define _epivers_h_
2359 +
2360 +#ifdef linux
2361 +#include <linux/config.h>
2362 +#endif
2363 +
2364 +/* Vendor Name, ASCII, 32 chars max */
2365 +#ifdef COMPANYNAME
2366 +#define HPNA_VENDOR COMPANYNAME
2367 +#else
2368 +#define HPNA_VENDOR "Broadcom Corporation"
2369 +#endif
2370 +
2371 +/* Driver Date, ASCII, 32 chars max */
2372 +#define HPNA_DRV_BUILD_DATE __DATE__
2373 +
2374 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2375 +#define HPNA_HW_MFG_DATE "Not Specified"
2376 +
2377 +/* See documentation for Device Type values, 32 values max */
2378 +#ifndef HPNA_DEV_TYPE
2379 +
2380 +#if defined(CONFIG_BRCM_VJ)
2381 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2382 +
2383 +#elif defined(CONFIG_BCRM_93725)
2384 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2385 +
2386 +#else
2387 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2388 +
2389 +#endif
2390 +
2391 +#endif /* !HPNA_DEV_TYPE */
2392 +
2393 +
2394 +#define EPI_MAJOR_VERSION 3
2395 +
2396 +#define EPI_MINOR_VERSION 130
2397 +
2398 +#define EPI_RC_NUMBER 20
2399 +
2400 +#define EPI_INCREMENTAL_NUMBER 0
2401 +
2402 +#define EPI_BUILD_NUMBER 0
2403 +
2404 +#define EPI_VERSION 3,130,20,0
2405 +
2406 +#define EPI_VERSION_NUM 0x03821400
2407 +
2408 +/* Driver Version String, ASCII, 32 chars max */
2409 +#define EPI_VERSION_STR "3.130.20.0"
2410 +#define EPI_ROUTER_VERSION_STR "3.131.20.0"
2411 +
2412 +#endif /* _epivers_h_ */
2413 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h.in linux.dev/arch/mips/bcm947xx/include/epivers.h.in
2414 --- linux.old/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
2415 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h.in 2005-11-07 21:57:07.849586000 +0100
2416 @@ -0,0 +1,69 @@
2417 +/*
2418 + * Copyright 2005, Broadcom Corporation
2419 + * All Rights Reserved.
2420 + *
2421 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2422 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2423 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2424 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2425 + *
2426 + * $Id$
2427 + *
2428 +*/
2429 +
2430 +#ifndef _epivers_h_
2431 +#define _epivers_h_
2432 +
2433 +#ifdef linux
2434 +#include <linux/config.h>
2435 +#endif
2436 +
2437 +/* Vendor Name, ASCII, 32 chars max */
2438 +#ifdef COMPANYNAME
2439 +#define HPNA_VENDOR COMPANYNAME
2440 +#else
2441 +#define HPNA_VENDOR "Broadcom Corporation"
2442 +#endif
2443 +
2444 +/* Driver Date, ASCII, 32 chars max */
2445 +#define HPNA_DRV_BUILD_DATE __DATE__
2446 +
2447 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2448 +#define HPNA_HW_MFG_DATE "Not Specified"
2449 +
2450 +/* See documentation for Device Type values, 32 values max */
2451 +#ifndef HPNA_DEV_TYPE
2452 +
2453 +#if defined(CONFIG_BRCM_VJ)
2454 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2455 +
2456 +#elif defined(CONFIG_BCRM_93725)
2457 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2458 +
2459 +#else
2460 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2461 +
2462 +#endif
2463 +
2464 +#endif /* !HPNA_DEV_TYPE */
2465 +
2466 +
2467 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
2468 +
2469 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
2470 +
2471 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
2472 +
2473 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
2474 +
2475 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
2476 +
2477 +#define EPI_VERSION @EPI_VERSION@
2478 +
2479 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
2480 +
2481 +/* Driver Version String, ASCII, 32 chars max */
2482 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
2483 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
2484 +
2485 +#endif /* _epivers_h_ */
2486 diff -urN linux.old/arch/mips/bcm947xx/include/etsockio.h linux.dev/arch/mips/bcm947xx/include/etsockio.h
2487 --- linux.old/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
2488 +++ linux.dev/arch/mips/bcm947xx/include/etsockio.h 2005-11-07 21:57:07.861586750 +0100
2489 @@ -0,0 +1,59 @@
2490 +/*
2491 + * Driver-specific socket ioctls
2492 + * used by BSD, Linux, and PSOS
2493 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
2494 + *
2495 + * Copyright 2005, Broadcom Corporation
2496 + * All Rights Reserved.
2497 + *
2498 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2499 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2500 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2501 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2502 + *
2503 + * $Id$
2504 + */
2505 +
2506 +#ifndef _etsockio_h_
2507 +#define _etsockio_h_
2508 +
2509 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
2510 +
2511 +
2512 +#if defined(linux)
2513 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
2514 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
2515 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
2516 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
2517 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
2518 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
2519 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
2520 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
2521 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
2522 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
2523 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
2524 +#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
2525 +
2526 +#else /* !linux */
2527 +
2528 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
2529 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
2530 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
2531 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
2532 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
2533 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
2534 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
2535 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
2536 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
2537 +
2538 +#endif
2539 +
2540 +/* arg to SIOCTXGEN */
2541 +struct txg {
2542 + uint32 num; /* number of frames to send */
2543 + uint32 delay; /* delay in microseconds between sending each */
2544 + uint32 size; /* size of ether frame to send */
2545 + uchar buf[1514]; /* starting ether frame data */
2546 +};
2547 +
2548 +#endif
2549 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
2550 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
2551 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-11-07 21:57:07.861586750 +0100
2552 @@ -0,0 +1,188 @@
2553 +/*
2554 + * flash.h: Common definitions for flash access.
2555 + *
2556 + * Copyright 2005, Broadcom Corporation
2557 + * All Rights Reserved.
2558 + *
2559 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2560 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2561 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2562 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2563 + *
2564 + * $Id$
2565 + */
2566 +
2567 +/* Types of flashes we know about */
2568 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
2569 +
2570 +/* Commands to write/erase the flases */
2571 +typedef struct _flash_cmds{
2572 + flash_type_t type;
2573 + bool need_unlock;
2574 + uint16 pre_erase;
2575 + uint16 erase_block;
2576 + uint16 erase_chip;
2577 + uint16 write_word;
2578 + uint16 write_buf;
2579 + uint16 clear_csr;
2580 + uint16 read_csr;
2581 + uint16 read_id;
2582 + uint16 confirm;
2583 + uint16 read_array;
2584 +} flash_cmds_t;
2585 +
2586 +#define UNLOCK_CMD_WORDS 2
2587 +
2588 +typedef struct _unlock_cmd {
2589 + uint addr[UNLOCK_CMD_WORDS];
2590 + uint16 cmd[UNLOCK_CMD_WORDS];
2591 +} unlock_cmd_t;
2592 +
2593 +/* Flash descriptors */
2594 +typedef struct _flash_desc {
2595 + uint16 mfgid; /* Manufacturer Id */
2596 + uint16 devid; /* Device Id */
2597 + uint size; /* Total size in bytes */
2598 + uint width; /* Device width in bytes */
2599 + flash_type_t type; /* Device type old, S, J */
2600 + uint bsize; /* Block size */
2601 + uint nb; /* Number of blocks */
2602 + uint ff; /* First full block */
2603 + uint lf; /* Last full block */
2604 + uint nsub; /* Number of subblocks */
2605 + uint *subblocks; /* Offsets for subblocks */
2606 + char *desc; /* Description */
2607 +} flash_desc_t;
2608 +
2609 +
2610 +#ifdef DECLARE_FLASHES
2611 +flash_cmds_t sflash_cmd_t =
2612 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2613 +
2614 +flash_cmds_t flash_cmds[] = {
2615 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
2616 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
2617 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
2618 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2619 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2620 + { 0 }
2621 +};
2622 +
2623 +unlock_cmd_t unlock_cmd_amd = {
2624 +#ifdef MIPSEB
2625 +/* addr: */ { 0x0aa8, 0x0556},
2626 +#else
2627 +/* addr: */ { 0x0aaa, 0x0554},
2628 +#endif
2629 +/* data: */ { 0xaa, 0x55}
2630 +};
2631 +
2632 +unlock_cmd_t unlock_cmd_sst = {
2633 +#ifdef MIPSEB
2634 +/* addr: */ { 0xaaa8, 0x5556},
2635 +#else
2636 +/* addr: */ { 0xaaaa, 0x5554},
2637 +#endif
2638 +/* data: */ { 0xaa, 0x55}
2639 +};
2640 +
2641 +#define AMD_CMD 0xaaa
2642 +#define SST_CMD 0xaaaa
2643 +
2644 +/* intel unlock block cmds */
2645 +#define INTEL_UNLOCK1 0x60
2646 +#define INTEL_UNLOCK2 0xD0
2647 +
2648 +/* Just eight blocks of 8KB byte each */
2649 +
2650 +uint blk8x8k[] = { 0x00000000,
2651 + 0x00002000,
2652 + 0x00004000,
2653 + 0x00006000,
2654 + 0x00008000,
2655 + 0x0000a000,
2656 + 0x0000c000,
2657 + 0x0000e000,
2658 + 0x00010000
2659 +};
2660 +
2661 +/* Funky AMD arrangement for 29xx800's */
2662 +uint amd800[] = { 0x00000000, /* 16KB */
2663 + 0x00004000, /* 32KB */
2664 + 0x0000c000, /* 8KB */
2665 + 0x0000e000, /* 8KB */
2666 + 0x00010000, /* 8KB */
2667 + 0x00012000, /* 8KB */
2668 + 0x00014000, /* 32KB */
2669 + 0x0001c000, /* 16KB */
2670 + 0x00020000
2671 +};
2672 +
2673 +/* AMD arrangement for 29xx160's */
2674 +uint amd4112[] = { 0x00000000, /* 32KB */
2675 + 0x00008000, /* 8KB */
2676 + 0x0000a000, /* 8KB */
2677 + 0x0000c000, /* 16KB */
2678 + 0x00010000
2679 +};
2680 +uint amd2114[] = { 0x00000000, /* 16KB */
2681 + 0x00004000, /* 8KB */
2682 + 0x00006000, /* 8KB */
2683 + 0x00008000, /* 32KB */
2684 + 0x00010000
2685 +};
2686 +
2687 +
2688 +flash_desc_t sflash_desc =
2689 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
2690 +
2691 +flash_desc_t flashes[] = {
2692 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
2693 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
2694 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
2695 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
2696 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
2697 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
2698 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
2699 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
2700 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
2701 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
2702 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
2703 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
2704 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
2705 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
2706 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
2707 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
2708 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
2709 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
2710 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
2711 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
2712 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
2713 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
2714 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
2715 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
2716 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
2717 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
2718 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
2719 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
2720 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
2721 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
2722 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2723 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2724 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
2725 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
2726 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
2727 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
2728 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2729 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2730 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
2731 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
2732 +};
2733 +
2734 +#else
2735 +
2736 +extern flash_cmds_t flash_cmds[];
2737 +extern unlock_cmd_t unlock_cmd;
2738 +extern flash_desc_t flashes[];
2739 +
2740 +#endif
2741 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
2742 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
2743 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-11-07 21:57:07.861586750 +0100
2744 @@ -0,0 +1,27 @@
2745 +/*
2746 + * BCM47XX FLASH driver interface
2747 + *
2748 + * Copyright 2005, Broadcom Corporation
2749 + * All Rights Reserved.
2750 + *
2751 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2752 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2753 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2754 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2755 + * $Id$
2756 + */
2757 +
2758 +#ifndef _flashutl_h_
2759 +#define _flashutl_h_
2760 +
2761 +
2762 +#ifndef _LANGUAGE_ASSEMBLY
2763 +
2764 +int sysFlashInit(char *flash_str);
2765 +int sysFlashRead(uint off, uchar *dst, uint bytes);
2766 +int sysFlashWrite(uint off, uchar *src, uint bytes);
2767 +void nvWrite(unsigned short *data, unsigned int len);
2768 +
2769 +#endif /* _LANGUAGE_ASSEMBLY */
2770 +
2771 +#endif /* _flashutl_h_ */
2772 diff -urN linux.old/arch/mips/bcm947xx/include/hnddma.h linux.dev/arch/mips/bcm947xx/include/hnddma.h
2773 --- linux.old/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
2774 +++ linux.dev/arch/mips/bcm947xx/include/hnddma.h 2005-11-07 22:51:38.776726000 +0100
2775 @@ -0,0 +1,71 @@
2776 +/*
2777 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
2778 + * This supports the following chips: BCM42xx, 44xx, 47xx .
2779 + *
2780 + * Copyright 2005, Broadcom Corporation
2781 + * All Rights Reserved.
2782 + *
2783 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2784 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2785 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2786 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2787 + * $Id$
2788 + */
2789 +
2790 +#ifndef _hnddma_h_
2791 +#define _hnddma_h_
2792 +
2793 +/* export structure */
2794 +typedef volatile struct {
2795 + /* rx error counters */
2796 + uint rxgiants; /* rx giant frames */
2797 + uint rxnobuf; /* rx out of dma descriptors */
2798 + /* tx error counters */
2799 + uint txnobuf; /* tx out of dma descriptors */
2800 +} hnddma_t;
2801 +
2802 +#ifndef di_t
2803 +#define di_t void
2804 +#endif
2805 +
2806 +#ifndef osl_t
2807 +#define osl_t void
2808 +#endif
2809 +
2810 +/* externs */
2811 +extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
2812 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
2813 +extern void dma_detach(di_t *di);
2814 +extern void dma_txreset(di_t *di);
2815 +extern void dma_rxreset(di_t *di);
2816 +extern void dma_txinit(di_t *di);
2817 +extern bool dma_txenabled(di_t *di);
2818 +extern void dma_rxinit(di_t *di);
2819 +extern void dma_rxenable(di_t *di);
2820 +extern bool dma_rxenabled(di_t *di);
2821 +extern void dma_txsuspend(di_t *di);
2822 +extern void dma_txresume(di_t *di);
2823 +extern bool dma_txsuspended(di_t *di);
2824 +extern bool dma_txsuspendedidle(di_t *di);
2825 +extern bool dma_txstopped(di_t *di);
2826 +extern bool dma_rxstopped(di_t *di);
2827 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
2828 +extern void dma_fifoloopbackenable(di_t *di);
2829 +extern void *dma_rx(di_t *di);
2830 +extern void dma_rxfill(di_t *di);
2831 +extern void dma_txreclaim(di_t *di, bool forceall);
2832 +extern void dma_rxreclaim(di_t *di);
2833 +extern uintptr dma_getvar(di_t *di, char *name);
2834 +extern void *dma_getnexttxp(di_t *di, bool forceall);
2835 +extern void *dma_peeknexttxp(di_t *di);
2836 +extern void *dma_getnextrxp(di_t *di, bool forceall);
2837 +extern void dma_txblock(di_t *di);
2838 +extern void dma_txunblock(di_t *di);
2839 +extern uint dma_txactive(di_t *di);
2840 +extern void dma_txrotate(di_t *di);
2841 +
2842 +extern void dma_rxpiomode(dma32regs_t *);
2843 +extern void dma_txpioloopback(dma32regs_t *);
2844 +
2845 +
2846 +#endif /* _hnddma_h_ */
2847 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
2848 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
2849 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-11-07 21:57:07.861586750 +0100
2850 @@ -0,0 +1,16 @@
2851 +/*
2852 + * Alternate include file for HND sbmips.h since CFE also ships with
2853 + * a sbmips.h.
2854 + *
2855 + * Copyright 2005, Broadcom Corporation
2856 + * All Rights Reserved.
2857 + *
2858 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2859 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2860 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2861 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2862 + *
2863 + * $Id$
2864 + */
2865 +
2866 +#include "sbmips.h"
2867 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
2868 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
2869 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-11-07 22:51:38.776726000 +0100
2870 @@ -0,0 +1,371 @@
2871 +/*
2872 + * Linux OS Independent Layer
2873 + *
2874 + * Copyright 2005, Broadcom Corporation
2875 + * All Rights Reserved.
2876 + *
2877 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2878 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2879 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2880 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2881 + *
2882 + * $Id$
2883 + */
2884 +
2885 +#ifndef _linux_osl_h_
2886 +#define _linux_osl_h_
2887 +
2888 +#include <typedefs.h>
2889 +
2890 +/* use current 2.4.x calling conventions */
2891 +#include <linuxver.h>
2892 +
2893 +/* assert and panic */
2894 +#ifdef __GNUC__
2895 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
2896 +#if GCC_VERSION > 30100
2897 +#define ASSERT(exp) do {} while (0)
2898 +#else
2899 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
2900 +#define ASSERT(exp)
2901 +#endif
2902 +#endif
2903 +
2904 +/* microsecond delay */
2905 +#define OSL_DELAY(usec) osl_delay(usec)
2906 +extern void osl_delay(uint usec);
2907 +
2908 +/* PCMCIA attribute space access macros */
2909 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2910 +struct pcmcia_dev {
2911 + dev_link_t link; /* PCMCIA device pointer */
2912 + dev_node_t node; /* PCMCIA node structure */
2913 + void *base; /* Mapped attribute memory window */
2914 + size_t size; /* Size of window */
2915 + void *drv; /* Driver data */
2916 +};
2917 +#endif
2918 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2919 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
2920 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2921 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
2922 +extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
2923 +extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
2924 +
2925 +/* PCI configuration space access macros */
2926 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
2927 + osl_pci_read_config((osh), (offset), (size))
2928 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
2929 + osl_pci_write_config((osh), (offset), (size), (val))
2930 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
2931 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
2932 +
2933 +/* PCI device bus # and slot # */
2934 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
2935 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
2936 +extern uint osl_pci_bus(osl_t *osh);
2937 +extern uint osl_pci_slot(osl_t *osh);
2938 +
2939 +/* OSL initialization */
2940 +extern osl_t *osl_attach(void *pdev);
2941 +extern void osl_detach(osl_t *osh);
2942 +
2943 +/* host/bus architecture-specific byte swap */
2944 +#define BUS_SWAP32(v) (v)
2945 +
2946 +/* general purpose memory allocation */
2947 +
2948 +#if defined(BCMDBG_MEM)
2949 +
2950 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
2951 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
2952 +#define MALLOCED(osh) osl_malloced((osh))
2953 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
2954 +extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
2955 +extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
2956 +extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
2957 +
2958 +#else
2959 +
2960 +#define MALLOC(osh, size) osl_malloc((osh), (size))
2961 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
2962 +#define MALLOCED(osh) osl_malloced((osh))
2963 +
2964 +#endif /* BCMDBG_MEM */
2965 +
2966 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
2967 +
2968 +extern void *osl_malloc(osl_t *osh, uint size);
2969 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
2970 +extern uint osl_malloced(osl_t *osh);
2971 +extern uint osl_malloc_failed(osl_t *osh);
2972 +
2973 +/* allocate/free shared (dma-able) consistent memory */
2974 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
2975 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2976 + osl_dma_alloc_consistent((osh), (size), (pap))
2977 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2978 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
2979 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
2980 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
2981 +
2982 +/* map/unmap direction */
2983 +#define DMA_TX 1
2984 +#define DMA_RX 2
2985 +
2986 +/* map/unmap shared (dma-able) memory */
2987 +#define DMA_MAP(osh, va, size, direction, p) \
2988 + osl_dma_map((osh), (va), (size), (direction))
2989 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2990 + osl_dma_unmap((osh), (pa), (size), (direction))
2991 +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
2992 +extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
2993 +
2994 +/* register access macros */
2995 +#if defined(BCMJTAG)
2996 +#include <bcmjtag.h>
2997 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
2998 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
2999 +#endif
3000 +
3001 +/*
3002 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
3003 + * Macros expand to calls to functions defined in linux_osl.c .
3004 + */
3005 +#ifndef BINOSL
3006 +
3007 +/* string library, kernel mode */
3008 +#define printf(fmt, args...) printk(fmt, ## args)
3009 +#include <linux/kernel.h>
3010 +#include <linux/string.h>
3011 +
3012 +/* register access macros */
3013 +#if !defined(BCMJTAG)
3014 +#ifndef IL_BIGENDIAN
3015 +#define R_REG(r) ( \
3016 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
3017 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
3018 + readl((volatile uint32*)(r)) \
3019 +)
3020 +#define W_REG(r, v) do { \
3021 + switch (sizeof(*(r))) { \
3022 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
3023 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
3024 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3025 + } \
3026 +} while (0)
3027 +#else /* IL_BIGENDIAN */
3028 +#define R_REG(r) ({ \
3029 + __typeof(*(r)) __osl_v; \
3030 + switch (sizeof(*(r))) { \
3031 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
3032 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
3033 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
3034 + } \
3035 + __osl_v; \
3036 +})
3037 +#define W_REG(r, v) do { \
3038 + switch (sizeof(*(r))) { \
3039 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
3040 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
3041 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3042 + } \
3043 +} while (0)
3044 +#endif
3045 +#endif
3046 +
3047 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3048 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3049 +
3050 +/* bcopy, bcmp, and bzero */
3051 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3052 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3053 +#define bzero(b, len) memset((b), '\0', (len))
3054 +
3055 +/* uncached virtual address */
3056 +#ifdef mips
3057 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
3058 +#include <asm/addrspace.h>
3059 +#else
3060 +#define OSL_UNCACHED(va) (va)
3061 +#endif
3062 +
3063 +/* get processor cycle count */
3064 +#if defined(mips)
3065 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
3066 +#elif defined(__i386__)
3067 +#define OSL_GETCYCLES(x) rdtscl((x))
3068 +#else
3069 +#define OSL_GETCYCLES(x) ((x) = 0)
3070 +#endif
3071 +
3072 +/* dereference an address that may cause a bus exception */
3073 +#ifdef mips
3074 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
3075 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
3076 +#else
3077 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
3078 +#include <asm/paccess.h>
3079 +#endif
3080 +#else
3081 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
3082 +#endif
3083 +
3084 +/* map/unmap physical to virtual I/O */
3085 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
3086 +#define REG_UNMAP(va) iounmap((void *)(va))
3087 +
3088 +/* shared (dma-able) memory access macros */
3089 +#define R_SM(r) *(r)
3090 +#define W_SM(r, v) (*(r) = (v))
3091 +#define BZERO_SM(r, len) memset((r), '\0', (len))
3092 +
3093 +/* packet primitives */
3094 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3095 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3096 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
3097 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
3098 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
3099 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
3100 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
3101 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
3102 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
3103 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
3104 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
3105 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
3106 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
3107 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
3108 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
3109 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
3110 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
3111 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
3112 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3113 +extern void osl_pktfree(void *skb);
3114 +
3115 +#else /* BINOSL */
3116 +
3117 +/* string library */
3118 +#ifndef LINUX_OSL
3119 +#undef printf
3120 +#define printf(fmt, args...) osl_printf((fmt), ## args)
3121 +#undef sprintf
3122 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
3123 +#undef strcmp
3124 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
3125 +#undef strncmp
3126 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
3127 +#undef strlen
3128 +#define strlen(s) osl_strlen((s))
3129 +#undef strcpy
3130 +#define strcpy(d, s) osl_strcpy((d), (s))
3131 +#undef strncpy
3132 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
3133 +#endif
3134 +extern int osl_printf(const char *format, ...);
3135 +extern int osl_sprintf(char *buf, const char *format, ...);
3136 +extern int osl_strcmp(const char *s1, const char *s2);
3137 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
3138 +extern int osl_strlen(const char *s);
3139 +extern char* osl_strcpy(char *d, const char *s);
3140 +extern char* osl_strncpy(char *d, const char *s, uint n);
3141 +
3142 +/* register access macros */
3143 +#if !defined(BCMJTAG)
3144 +#define R_REG(r) ( \
3145 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
3146 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
3147 + osl_readl((volatile uint32*)(r)) \
3148 +)
3149 +#define W_REG(r, v) do { \
3150 + switch (sizeof(*(r))) { \
3151 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
3152 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
3153 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
3154 + } \
3155 +} while (0)
3156 +#endif
3157 +
3158 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3159 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3160 +extern uint8 osl_readb(volatile uint8 *r);
3161 +extern uint16 osl_readw(volatile uint16 *r);
3162 +extern uint32 osl_readl(volatile uint32 *r);
3163 +extern void osl_writeb(uint8 v, volatile uint8 *r);
3164 +extern void osl_writew(uint16 v, volatile uint16 *r);
3165 +extern void osl_writel(uint32 v, volatile uint32 *r);
3166 +
3167 +/* bcopy, bcmp, and bzero */
3168 +extern void bcopy(const void *src, void *dst, int len);
3169 +extern int bcmp(const void *b1, const void *b2, int len);
3170 +extern void bzero(void *b, int len);
3171 +
3172 +/* uncached virtual address */
3173 +#define OSL_UNCACHED(va) osl_uncached((va))
3174 +extern void *osl_uncached(void *va);
3175 +
3176 +/* get processor cycle count */
3177 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
3178 +extern uint osl_getcycles(void);
3179 +
3180 +/* dereference an address that may target abort */
3181 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
3182 +extern int osl_busprobe(uint32 *val, uint32 addr);
3183 +
3184 +/* map/unmap physical to virtual */
3185 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
3186 +#define REG_UNMAP(va) osl_reg_unmap((va))
3187 +extern void *osl_reg_map(uint32 pa, uint size);
3188 +extern void osl_reg_unmap(void *va);
3189 +
3190 +/* shared (dma-able) memory access macros */
3191 +#define R_SM(r) *(r)
3192 +#define W_SM(r, v) (*(r) = (v))
3193 +#define BZERO_SM(r, len) bzero((r), (len))
3194 +
3195 +/* packet primitives */
3196 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3197 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3198 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
3199 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
3200 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
3201 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
3202 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
3203 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
3204 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
3205 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
3206 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
3207 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
3208 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
3209 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
3210 +#define PKTLINK(skb) osl_pktlink((skb))
3211 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
3212 +#define PKTPRIO(skb) osl_pktprio((skb))
3213 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
3214 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3215 +extern void osl_pktfree(void *skb);
3216 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
3217 +extern uint osl_pktlen(osl_t *osh, void *skb);
3218 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
3219 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
3220 +extern void *osl_pktnext(osl_t *osh, void *skb);
3221 +extern void osl_pktsetnext(void *skb, void *x);
3222 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
3223 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
3224 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
3225 +extern void *osl_pktdup(osl_t *osh, void *skb);
3226 +extern void *osl_pktcookie(void *skb);
3227 +extern void osl_pktsetcookie(void *skb, void *x);
3228 +extern void *osl_pktlink(void *skb);
3229 +extern void osl_pktsetlink(void *skb, void *x);
3230 +extern uint osl_pktprio(void *skb);
3231 +extern void osl_pktsetprio(void *skb, uint x);
3232 +
3233 +#endif /* BINOSL */
3234 +
3235 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3236 +extern int osl_error(int bcmerror);
3237 +
3238 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
3239 +#define PKTBUFSZ 2048
3240 +
3241 +#endif /* _linux_osl_h_ */
3242 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
3243 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
3244 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-11-07 22:51:38.780726250 +0100
3245 @@ -0,0 +1,411 @@
3246 +/*
3247 + * Linux-specific abstractions to gain some independence from linux kernel versions.
3248 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
3249 + *
3250 + * Copyright 2005, Broadcom Corporation
3251 + * All Rights Reserved.
3252 + *
3253 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3254 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3255 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3256 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3257 + *
3258 + * $Id$
3259 + */
3260 +
3261 +#ifndef _linuxver_h_
3262 +#define _linuxver_h_
3263 +
3264 +#include <linux/config.h>
3265 +#include <linux/version.h>
3266 +
3267 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
3268 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
3269 +#ifdef __UNDEF_NO_VERSION__
3270 +#undef __NO_VERSION__
3271 +#else
3272 +#define __NO_VERSION__
3273 +#endif
3274 +#endif
3275 +
3276 +#if defined(MODULE) && defined(MODVERSIONS)
3277 +#include <linux/modversions.h>
3278 +#endif
3279 +
3280 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
3281 +#include <linux/moduleparam.h>
3282 +#endif
3283 +
3284 +
3285 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3286 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
3287 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
3288 +#endif
3289 +
3290 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
3291 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
3292 +#include <linux/malloc.h>
3293 +#else
3294 +#include <linux/slab.h>
3295 +#endif
3296 +
3297 +#include <linux/types.h>
3298 +#include <linux/init.h>
3299 +#include <linux/mm.h>
3300 +#include <linux/string.h>
3301 +#include <linux/pci.h>
3302 +#include <linux/interrupt.h>
3303 +#include <linux/netdevice.h>
3304 +#include <asm/io.h>
3305 +
3306 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
3307 +#include <linux/workqueue.h>
3308 +#else
3309 +#include <linux/tqueue.h>
3310 +#ifndef work_struct
3311 +#define work_struct tq_struct
3312 +#endif
3313 +#ifndef INIT_WORK
3314 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
3315 +#endif
3316 +#ifndef schedule_work
3317 +#define schedule_work(_work) schedule_task((_work))
3318 +#endif
3319 +#ifndef flush_scheduled_work
3320 +#define flush_scheduled_work() flush_scheduled_tasks()
3321 +#endif
3322 +#endif
3323 +
3324 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3325 +/* Some distributions have their own 2.6.x compatibility layers */
3326 +#ifndef IRQ_NONE
3327 +typedef void irqreturn_t;
3328 +#define IRQ_NONE
3329 +#define IRQ_HANDLED
3330 +#define IRQ_RETVAL(x)
3331 +#endif
3332 +#else
3333 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
3334 +#endif
3335 +
3336 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
3337 +
3338 +#include <pcmcia/version.h>
3339 +#include <pcmcia/cs_types.h>
3340 +#include <pcmcia/cs.h>
3341 +#include <pcmcia/cistpl.h>
3342 +#include <pcmcia/cisreg.h>
3343 +#include <pcmcia/ds.h>
3344 +
3345 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
3346 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
3347 + * does this, but it's not in 2.4 so we do our own for now. */
3348 +static inline void
3349 +cs_error(client_handle_t handle, int func, int ret)
3350 +{
3351 + error_info_t err = { func, ret };
3352 + CardServices(ReportError, handle, &err);
3353 +}
3354 +#endif
3355 +
3356 +#endif /* CONFIG_PCMCIA */
3357 +
3358 +#ifndef __exit
3359 +#define __exit
3360 +#endif
3361 +#ifndef __devexit
3362 +#define __devexit
3363 +#endif
3364 +#ifndef __devinit
3365 +#define __devinit __init
3366 +#endif
3367 +#ifndef __devinitdata
3368 +#define __devinitdata
3369 +#endif
3370 +#ifndef __devexit_p
3371 +#define __devexit_p(x) x
3372 +#endif
3373 +
3374 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
3375 +
3376 +#define pci_get_drvdata(dev) (dev)->sysdata
3377 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
3378 +
3379 +/*
3380 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
3381 + */
3382 +
3383 +struct pci_device_id {
3384 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
3385 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
3386 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
3387 + unsigned long driver_data; /* Data private to the driver */
3388 +};
3389 +
3390 +struct pci_driver {
3391 + struct list_head node;
3392 + char *name;
3393 + const struct pci_device_id *id_table; /* NULL if wants all devices */
3394 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
3395 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
3396 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
3397 + void (*resume)(struct pci_dev *dev); /* Device woken up */
3398 +};
3399 +
3400 +#define MODULE_DEVICE_TABLE(type, name)
3401 +#define PCI_ANY_ID (~0)
3402 +
3403 +/* compatpci.c */
3404 +#define pci_module_init pci_register_driver
3405 +extern int pci_register_driver(struct pci_driver *drv);
3406 +extern void pci_unregister_driver(struct pci_driver *drv);
3407 +
3408 +#endif /* PCI registration */
3409 +
3410 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
3411 +#ifdef MODULE
3412 +#define module_init(x) int init_module(void) { return x(); }
3413 +#define module_exit(x) void cleanup_module(void) { x(); }
3414 +#else
3415 +#define module_init(x) __initcall(x);
3416 +#define module_exit(x) __exitcall(x);
3417 +#endif
3418 +#endif
3419 +
3420 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
3421 +#define list_for_each(pos, head) \
3422 + for (pos = (head)->next; pos != (head); pos = pos->next)
3423 +#endif
3424 +
3425 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
3426 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
3427 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
3428 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
3429 +#endif
3430 +
3431 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
3432 +#define pci_enable_device(dev) do { } while (0)
3433 +#endif
3434 +
3435 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
3436 +#define net_device device
3437 +#endif
3438 +
3439 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
3440 +
3441 +/*
3442 + * DMA mapping
3443 + *
3444 + * See linux/Documentation/DMA-mapping.txt
3445 + */
3446 +
3447 +#ifndef PCI_DMA_TODEVICE
3448 +#define PCI_DMA_TODEVICE 1
3449 +#define PCI_DMA_FROMDEVICE 2
3450 +#endif
3451 +
3452 +typedef u32 dma_addr_t;
3453 +
3454 +/* Pure 2^n version of get_order */
3455 +static inline int get_order(unsigned long size)
3456 +{
3457 + int order;
3458 +
3459 + size = (size-1) >> (PAGE_SHIFT-1);
3460 + order = -1;
3461 + do {
3462 + size >>= 1;
3463 + order++;
3464 + } while (size);
3465 + return order;
3466 +}
3467 +
3468 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
3469 + dma_addr_t *dma_handle)
3470 +{
3471 + void *ret;
3472 + int gfp = GFP_ATOMIC | GFP_DMA;
3473 +
3474 + ret = (void *)__get_free_pages(gfp, get_order(size));
3475 +
3476 + if (ret != NULL) {
3477 + memset(ret, 0, size);
3478 + *dma_handle = virt_to_bus(ret);
3479 + }
3480 + return ret;
3481 +}
3482 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
3483 + void *vaddr, dma_addr_t dma_handle)
3484 +{
3485 + free_pages((unsigned long)vaddr, get_order(size));
3486 +}
3487 +#ifdef ILSIM
3488 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
3489 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
3490 +#else
3491 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
3492 +#define pci_unmap_single(cookie, address, size, dir)
3493 +#endif
3494 +
3495 +#endif /* DMA mapping */
3496 +
3497 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
3498 +
3499 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
3500 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
3501 +
3502 +/* pcmcia-cs provides its own netdevice compatibility layer */
3503 +#ifndef _COMPAT_NETDEVICE_H
3504 +
3505 +/*
3506 + * SoftNet
3507 + *
3508 + * For pre-softnet kernels we need to tell the upper layer not to
3509 + * re-enter start_xmit() while we are in there. However softnet
3510 + * guarantees not to enter while we are in there so there is no need
3511 + * to do the netif_stop_queue() dance unless the transmit queue really
3512 + * gets stuck. This should also improve performance according to tests
3513 + * done by Aman Singla.
3514 + */
3515 +
3516 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
3517 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
3518 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
3519 +
3520 +static inline void netif_start_queue(struct net_device *dev)
3521 +{
3522 + dev->tbusy = 0;
3523 + dev->interrupt = 0;
3524 + dev->start = 1;
3525 +}
3526 +
3527 +#define netif_queue_stopped(dev) (dev)->tbusy
3528 +#define netif_running(dev) (dev)->start
3529 +
3530 +#endif /* _COMPAT_NETDEVICE_H */
3531 +
3532 +#define netif_device_attach(dev) netif_start_queue(dev)
3533 +#define netif_device_detach(dev) netif_stop_queue(dev)
3534 +
3535 +/* 2.4.x renamed bottom halves to tasklets */
3536 +#define tasklet_struct tq_struct
3537 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
3538 +{
3539 + queue_task(tasklet, &tq_immediate);
3540 + mark_bh(IMMEDIATE_BH);
3541 +}
3542 +
3543 +static inline void tasklet_init(struct tasklet_struct *tasklet,
3544 + void (*func)(unsigned long),
3545 + unsigned long data)
3546 +{
3547 + tasklet->next = NULL;
3548 + tasklet->sync = 0;
3549 + tasklet->routine = (void (*)(void *))func;
3550 + tasklet->data = (void *)data;
3551 +}
3552 +#define tasklet_kill(tasklet) {do{} while(0);}
3553 +
3554 +/* 2.4.x introduced del_timer_sync() */
3555 +#define del_timer_sync(timer) del_timer(timer)
3556 +
3557 +#else
3558 +
3559 +#define netif_down(dev)
3560 +
3561 +#endif /* SoftNet */
3562 +
3563 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
3564 +
3565 +/*
3566 + * Emit code to initialise a tq_struct's routine and data pointers
3567 + */
3568 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
3569 + do { \
3570 + (_tq)->routine = _routine; \
3571 + (_tq)->data = _data; \
3572 + } while (0)
3573 +
3574 +/*
3575 + * Emit code to initialise all of a tq_struct
3576 + */
3577 +#define INIT_TQUEUE(_tq, _routine, _data) \
3578 + do { \
3579 + INIT_LIST_HEAD(&(_tq)->list); \
3580 + (_tq)->sync = 0; \
3581 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
3582 + } while (0)
3583 +
3584 +#endif
3585 +
3586 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
3587 +
3588 +/* Power management related routines */
3589 +
3590 +static inline int
3591 +pci_save_state(struct pci_dev *dev, u32 *buffer)
3592 +{
3593 + int i;
3594 + if (buffer) {
3595 + for (i = 0; i < 16; i++)
3596 + pci_read_config_dword(dev, i * 4,&buffer[i]);
3597 + }
3598 + return 0;
3599 +}
3600 +
3601 +static inline int
3602 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
3603 +{
3604 + int i;
3605 +
3606 + if (buffer) {
3607 + for (i = 0; i < 16; i++)
3608 + pci_write_config_dword(dev,i * 4, buffer[i]);
3609 + }
3610 + /*
3611 + * otherwise, write the context information we know from bootup.
3612 + * This works around a problem where warm-booting from Windows
3613 + * combined with a D3(hot)->D0 transition causes PCI config
3614 + * header data to be forgotten.
3615 + */
3616 + else {
3617 + for (i = 0; i < 6; i ++)
3618 + pci_write_config_dword(dev,
3619 + PCI_BASE_ADDRESS_0 + (i * 4),
3620 + pci_resource_start(dev, i));
3621 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3622 + }
3623 + return 0;
3624 +}
3625 +
3626 +#endif /* PCI power management */
3627 +
3628 +/* Old cp0 access macros deprecated in 2.4.19 */
3629 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
3630 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
3631 +#endif
3632 +
3633 +/* Module refcount handled internally in 2.6.x */
3634 +#ifndef SET_MODULE_OWNER
3635 +#define SET_MODULE_OWNER(dev) do {} while (0)
3636 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
3637 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
3638 +#else
3639 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
3640 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
3641 +#endif
3642 +
3643 +#ifndef SET_NETDEV_DEV
3644 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
3645 +#endif
3646 +
3647 +#ifndef HAVE_FREE_NETDEV
3648 +#define free_netdev(dev) kfree(dev)
3649 +#endif
3650 +
3651 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3652 +/* struct packet_type redefined in 2.6.x */
3653 +#define af_packet_priv data
3654 +#endif
3655 +
3656 +#endif /* _linuxver_h_ */
3657 diff -urN linux.old/arch/mips/bcm947xx/include/min_osl.h linux.dev/arch/mips/bcm947xx/include/min_osl.h
3658 --- linux.old/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
3659 +++ linux.dev/arch/mips/bcm947xx/include/min_osl.h 2005-11-07 22:51:38.780726250 +0100
3660 @@ -0,0 +1,126 @@
3661 +/*
3662 + * HND Minimal OS Abstraction Layer.
3663 + *
3664 + * Copyright 2005, Broadcom Corporation
3665 + * All Rights Reserved.
3666 + *
3667 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3668 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3669 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3670 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3671 + *
3672 + * $Id$
3673 + */
3674 +
3675 +#ifndef _min_osl_h_
3676 +#define _min_osl_h_
3677 +
3678 +#include <typedefs.h>
3679 +#include <sbconfig.h>
3680 +#include <mipsinc.h>
3681 +
3682 +/* Cache support */
3683 +extern void caches_on(void);
3684 +extern void blast_dcache(void);
3685 +extern void blast_icache(void);
3686 +
3687 +/* uart output */
3688 +extern void putc(int c);
3689 +
3690 +/* lib functions */
3691 +extern int printf(const char *fmt, ...);
3692 +extern int sprintf(char *buf, const char *fmt, ...);
3693 +extern int strcmp(const char *s1, const char *s2);
3694 +extern int strncmp(const char *s1, const char *s2, uint n);
3695 +extern char *strcpy(char *dest, const char *src);
3696 +extern char *strncpy(char *dest, const char *src, uint n);
3697 +extern uint strlen(const char *s);
3698 +extern char *strchr(const char *str,int c);
3699 +extern char *strrchr(const char *str, int c);
3700 +extern char *strcat(char *d, const char *s);
3701 +extern void *memset(void *dest, int c, uint n);
3702 +extern void *memcpy(void *dest, const void *src, uint n);
3703 +extern int memcmp(const void *s1, const void *s2, uint n);
3704 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3705 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3706 +#define bzero(b, len) memset((b), '\0', (len))
3707 +
3708 +/* assert & debugging */
3709 +#define ASSERT(exp) do {} while (0)
3710 +
3711 +/* PCMCIA attribute space access macros */
3712 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3713 + ASSERT(0)
3714 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3715 + ASSERT(0)
3716 +
3717 +/* PCI configuration space access macros */
3718 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
3719 + (offset == 8 ? 0 : 0xffffffff)
3720 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
3721 + do {} while (0)
3722 +
3723 +/* PCI device bus # and slot # */
3724 +#define OSL_PCI_BUS(osh) (0)
3725 +#define OSL_PCI_SLOT(osh) (0)
3726 +
3727 +/* register access macros */
3728 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
3729 +#define rreg32(r) (*(volatile uint32*)(r))
3730 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
3731 +#define rreg16(r) (*(volatile uint16*)(r))
3732 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
3733 +#define rreg8(r) (*(volatile uint8*)(r))
3734 +#define R_REG(r) ({ \
3735 + __typeof(*(r)) __osl_v; \
3736 + switch (sizeof(*(r))) { \
3737 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
3738 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
3739 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
3740 + } \
3741 + __osl_v; \
3742 +})
3743 +#define W_REG(r, v) do { \
3744 + switch (sizeof(*(r))) { \
3745 + case sizeof(uint8): wreg8((r), (v)); break; \
3746 + case sizeof(uint16): wreg16((r), (v)); break; \
3747 + case sizeof(uint32): wreg32((r), (v)); break; \
3748 + } \
3749 +} while (0)
3750 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3751 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3752 +
3753 +/* general purpose memory allocation */
3754 +#define MALLOC(osh, size) malloc(size)
3755 +#define MFREE(osh, addr, size) free(addr)
3756 +#define MALLOCED(osh) 0
3757 +#define MALLOC_FAILED(osh) 0
3758 +#define MALLOC_DUMP(osh, buf, sz)
3759 +extern int free(void *ptr);
3760 +extern void *malloc(uint size);
3761 +
3762 +/* uncached virtual address */
3763 +#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
3764 +
3765 +/* host/bus architecture-specific address byte swap */
3766 +#define BUS_SWAP32(v) (v)
3767 +
3768 +/* microsecond delay */
3769 +#define OSL_DELAY(usec) udelay(usec)
3770 +extern void udelay(uint32 usec);
3771 +
3772 +/* map/unmap physical to virtual I/O */
3773 +#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
3774 +#define REG_UNMAP(va) do {} while (0)
3775 +
3776 +/* dereference an address that may cause a bus exception */
3777 +#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
3778 +
3779 +/* Misc stubs */
3780 +#define osl_attach(pdev) ((osl_t*)pdev)
3781 +#define osl_detach(osh)
3782 +extern void *osl_init(void);
3783 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3784 +extern int osl_error(int);
3785 +
3786 +#endif /* _min_osl_h_ */
3787 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
3788 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
3789 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-11-07 22:51:38.780726250 +0100
3790 @@ -0,0 +1,552 @@
3791 +/*
3792 + * HND Run Time Environment for standalone MIPS programs.
3793 + *
3794 + * Copyright 2005, Broadcom Corporation
3795 + * All Rights Reserved.
3796 + *
3797 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3798 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3799 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3800 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3801 + *
3802 + * $Id$
3803 + */
3804 +
3805 +#ifndef _MISPINC_H
3806 +#define _MISPINC_H
3807 +
3808 +
3809 +/* MIPS defines */
3810 +
3811 +#ifdef _LANGUAGE_ASSEMBLY
3812 +
3813 +/*
3814 + * Symbolic register names for 32 bit ABI
3815 + */
3816 +#define zero $0 /* wired zero */
3817 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
3818 +#define v0 $2 /* return value */
3819 +#define v1 $3
3820 +#define a0 $4 /* argument registers */
3821 +#define a1 $5
3822 +#define a2 $6
3823 +#define a3 $7
3824 +#define t0 $8 /* caller saved */
3825 +#define t1 $9
3826 +#define t2 $10
3827 +#define t3 $11
3828 +#define t4 $12
3829 +#define t5 $13
3830 +#define t6 $14
3831 +#define t7 $15
3832 +#define s0 $16 /* callee saved */
3833 +#define s1 $17
3834 +#define s2 $18
3835 +#define s3 $19
3836 +#define s4 $20
3837 +#define s5 $21
3838 +#define s6 $22
3839 +#define s7 $23
3840 +#define t8 $24 /* caller saved */
3841 +#define t9 $25
3842 +#define jp $25 /* PIC jump register */
3843 +#define k0 $26 /* kernel scratch */
3844 +#define k1 $27
3845 +#define gp $28 /* global pointer */
3846 +#define sp $29 /* stack pointer */
3847 +#define fp $30 /* frame pointer */
3848 +#define s8 $30 /* same like fp! */
3849 +#define ra $31 /* return address */
3850 +
3851 +
3852 +/*
3853 + * CP0 Registers
3854 + */
3855 +
3856 +#define C0_INX $0
3857 +#define C0_RAND $1
3858 +#define C0_TLBLO0 $2
3859 +#define C0_TLBLO C0_TLBLO0
3860 +#define C0_TLBLO1 $3
3861 +#define C0_CTEXT $4
3862 +#define C0_PGMASK $5
3863 +#define C0_WIRED $6
3864 +#define C0_BADVADDR $8
3865 +#define C0_COUNT $9
3866 +#define C0_TLBHI $10
3867 +#define C0_COMPARE $11
3868 +#define C0_SR $12
3869 +#define C0_STATUS C0_SR
3870 +#define C0_CAUSE $13
3871 +#define C0_EPC $14
3872 +#define C0_PRID $15
3873 +#define C0_CONFIG $16
3874 +#define C0_LLADDR $17
3875 +#define C0_WATCHLO $18
3876 +#define C0_WATCHHI $19
3877 +#define C0_XCTEXT $20
3878 +#define C0_DIAGNOSTIC $22
3879 +#define C0_BROADCOM C0_DIAGNOSTIC
3880 +#define C0_PERFORMANCE $25
3881 +#define C0_ECC $26
3882 +#define C0_CACHEERR $27
3883 +#define C0_TAGLO $28
3884 +#define C0_TAGHI $29
3885 +#define C0_ERREPC $30
3886 +#define C0_DESAVE $31
3887 +
3888 +/*
3889 + * LEAF - declare leaf routine
3890 + */
3891 +#define LEAF(symbol) \
3892 + .globl symbol; \
3893 + .align 2; \
3894 + .type symbol,@function; \
3895 + .ent symbol,0; \
3896 +symbol: .frame sp,0,ra
3897 +
3898 +/*
3899 + * END - mark end of function
3900 + */
3901 +#define END(function) \
3902 + .end function; \
3903 + .size function,.-function
3904 +
3905 +#define _ULCAST_
3906 +
3907 +#else
3908 +
3909 +/*
3910 + * The following macros are especially useful for __asm__
3911 + * inline assembler.
3912 + */
3913 +#ifndef __STR
3914 +#define __STR(x) #x
3915 +#endif
3916 +#ifndef STR
3917 +#define STR(x) __STR(x)
3918 +#endif
3919 +
3920 +#define _ULCAST_ (unsigned long)
3921 +
3922 +
3923 +/*
3924 + * CP0 Registers
3925 + */
3926 +
3927 +#define C0_INX 0 /* CP0: TLB Index */
3928 +#define C0_RAND 1 /* CP0: TLB Random */
3929 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
3930 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
3931 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
3932 +#define C0_CTEXT 4 /* CP0: Context */
3933 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
3934 +#define C0_WIRED 6 /* CP0: TLB Wired */
3935 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
3936 +#define C0_COUNT 9 /* CP0: Count */
3937 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
3938 +#define C0_COMPARE 11 /* CP0: Compare */
3939 +#define C0_SR 12 /* CP0: Processor Status */
3940 +#define C0_STATUS C0_SR /* CP0: Processor Status */
3941 +#define C0_CAUSE 13 /* CP0: Exception Cause */
3942 +#define C0_EPC 14 /* CP0: Exception PC */
3943 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
3944 +#define C0_CONFIG 16 /* CP0: Config */
3945 +#define C0_LLADDR 17 /* CP0: LLAddr */
3946 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
3947 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
3948 +#define C0_XCTEXT 20 /* CP0: XContext */
3949 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
3950 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
3951 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
3952 +#define C0_ECC 26 /* CP0: ECC */
3953 +#define C0_CACHEERR 27 /* CP0: CacheErr */
3954 +#define C0_TAGLO 28 /* CP0: TagLo */
3955 +#define C0_TAGHI 29 /* CP0: TagHi */
3956 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
3957 +#define C0_DESAVE 31 /* CP0: DebugSave */
3958 +
3959 +#endif /* _LANGUAGE_ASSEMBLY */
3960 +
3961 +/*
3962 + * Memory segments (32bit kernel mode addresses)
3963 + */
3964 +#undef KUSEG
3965 +#undef KSEG0
3966 +#undef KSEG1
3967 +#undef KSEG2
3968 +#undef KSEG3
3969 +#define KUSEG 0x00000000
3970 +#define KSEG0 0x80000000
3971 +#define KSEG1 0xa0000000
3972 +#define KSEG2 0xc0000000
3973 +#define KSEG3 0xe0000000
3974 +#define PHYSADDR_MASK 0x1fffffff
3975 +
3976 +/*
3977 + * Map an address to a certain kernel segment
3978 + */
3979 +#undef PHYSADDR
3980 +#undef KSEG0ADDR
3981 +#undef KSEG1ADDR
3982 +#undef KSEG2ADDR
3983 +#undef KSEG3ADDR
3984 +
3985 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
3986 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
3987 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
3988 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
3989 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
3990 +
3991 +
3992 +#ifndef Index_Invalidate_I
3993 +/*
3994 + * Cache Operations
3995 + */
3996 +#define Index_Invalidate_I 0x00
3997 +#define Index_Writeback_Inv_D 0x01
3998 +#define Index_Invalidate_SI 0x02
3999 +#define Index_Writeback_Inv_SD 0x03
4000 +#define Index_Load_Tag_I 0x04
4001 +#define Index_Load_Tag_D 0x05
4002 +#define Index_Load_Tag_SI 0x06
4003 +#define Index_Load_Tag_SD 0x07
4004 +#define Index_Store_Tag_I 0x08
4005 +#define Index_Store_Tag_D 0x09
4006 +#define Index_Store_Tag_SI 0x0A
4007 +#define Index_Store_Tag_SD 0x0B
4008 +#define Create_Dirty_Excl_D 0x0d
4009 +#define Create_Dirty_Excl_SD 0x0f
4010 +#define Hit_Invalidate_I 0x10
4011 +#define Hit_Invalidate_D 0x11
4012 +#define Hit_Invalidate_SI 0x12
4013 +#define Hit_Invalidate_SD 0x13
4014 +#define Fill_I 0x14
4015 +#define Hit_Writeback_Inv_D 0x15
4016 + /* 0x16 is unused */
4017 +#define Hit_Writeback_Inv_SD 0x17
4018 +#define R5K_Page_Invalidate_S 0x17
4019 +#define Hit_Writeback_I 0x18
4020 +#define Hit_Writeback_D 0x19
4021 + /* 0x1a is unused */
4022 +#define Hit_Writeback_SD 0x1b
4023 + /* 0x1c is unused */
4024 + /* 0x1e is unused */
4025 +#define Hit_Set_Virtual_SI 0x1e
4026 +#define Hit_Set_Virtual_SD 0x1f
4027 +#endif
4028 +
4029 +
4030 +/*
4031 + * R4x00 interrupt enable / cause bits
4032 + */
4033 +#define IE_SW0 (_ULCAST_(1) << 8)
4034 +#define IE_SW1 (_ULCAST_(1) << 9)
4035 +#define IE_IRQ0 (_ULCAST_(1) << 10)
4036 +#define IE_IRQ1 (_ULCAST_(1) << 11)
4037 +#define IE_IRQ2 (_ULCAST_(1) << 12)
4038 +#define IE_IRQ3 (_ULCAST_(1) << 13)
4039 +#define IE_IRQ4 (_ULCAST_(1) << 14)
4040 +#define IE_IRQ5 (_ULCAST_(1) << 15)
4041 +
4042 +#ifndef ST0_UM
4043 +/*
4044 + * Bitfields in the mips32 cp0 status register
4045 + */
4046 +#define ST0_IE 0x00000001
4047 +#define ST0_EXL 0x00000002
4048 +#define ST0_ERL 0x00000004
4049 +#define ST0_UM 0x00000010
4050 +#define ST0_SWINT0 0x00000100
4051 +#define ST0_SWINT1 0x00000200
4052 +#define ST0_HWINT0 0x00000400
4053 +#define ST0_HWINT1 0x00000800
4054 +#define ST0_HWINT2 0x00001000
4055 +#define ST0_HWINT3 0x00002000
4056 +#define ST0_HWINT4 0x00004000
4057 +#define ST0_HWINT5 0x00008000
4058 +#define ST0_IM 0x0000ff00
4059 +#define ST0_NMI 0x00080000
4060 +#define ST0_SR 0x00100000
4061 +#define ST0_TS 0x00200000
4062 +#define ST0_BEV 0x00400000
4063 +#define ST0_RE 0x02000000
4064 +#define ST0_RP 0x08000000
4065 +#define ST0_CU 0xf0000000
4066 +#define ST0_CU0 0x10000000
4067 +#define ST0_CU1 0x20000000
4068 +#define ST0_CU2 0x40000000
4069 +#define ST0_CU3 0x80000000
4070 +#endif
4071 +
4072 +
4073 +/*
4074 + * Bitfields in the mips32 cp0 cause register
4075 + */
4076 +#define C_EXC 0x0000007c
4077 +#define C_EXC_SHIFT 2
4078 +#define C_INT 0x0000ff00
4079 +#define C_INT_SHIFT 8
4080 +#define C_SW0 (_ULCAST_(1) << 8)
4081 +#define C_SW1 (_ULCAST_(1) << 9)
4082 +#define C_IRQ0 (_ULCAST_(1) << 10)
4083 +#define C_IRQ1 (_ULCAST_(1) << 11)
4084 +#define C_IRQ2 (_ULCAST_(1) << 12)
4085 +#define C_IRQ3 (_ULCAST_(1) << 13)
4086 +#define C_IRQ4 (_ULCAST_(1) << 14)
4087 +#define C_IRQ5 (_ULCAST_(1) << 15)
4088 +#define C_WP 0x00400000
4089 +#define C_IV 0x00800000
4090 +#define C_CE 0x30000000
4091 +#define C_CE_SHIFT 28
4092 +#define C_BD 0x80000000
4093 +
4094 +/* Values in C_EXC */
4095 +#define EXC_INT 0
4096 +#define EXC_TLBM 1
4097 +#define EXC_TLBL 2
4098 +#define EXC_TLBS 3
4099 +#define EXC_AEL 4
4100 +#define EXC_AES 5
4101 +#define EXC_IBE 6
4102 +#define EXC_DBE 7
4103 +#define EXC_SYS 8
4104 +#define EXC_BPT 9
4105 +#define EXC_RI 10
4106 +#define EXC_CU 11
4107 +#define EXC_OV 12
4108 +#define EXC_TR 13
4109 +#define EXC_WATCH 23
4110 +#define EXC_MCHK 24
4111 +
4112 +
4113 +/*
4114 + * Bits in the cp0 config register.
4115 + */
4116 +#define CONF_CM_CACHABLE_NO_WA 0
4117 +#define CONF_CM_CACHABLE_WA 1
4118 +#define CONF_CM_UNCACHED 2
4119 +#define CONF_CM_CACHABLE_NONCOHERENT 3
4120 +#define CONF_CM_CACHABLE_CE 4
4121 +#define CONF_CM_CACHABLE_COW 5
4122 +#define CONF_CM_CACHABLE_CUW 6
4123 +#define CONF_CM_CACHABLE_ACCELERATED 7
4124 +#define CONF_CM_CMASK 7
4125 +#define CONF_CU (_ULCAST_(1) << 3)
4126 +#define CONF_DB (_ULCAST_(1) << 4)
4127 +#define CONF_IB (_ULCAST_(1) << 5)
4128 +#define CONF_SE (_ULCAST_(1) << 12)
4129 +#define CONF_SC (_ULCAST_(1) << 17)
4130 +#define CONF_AC (_ULCAST_(1) << 23)
4131 +#define CONF_HALT (_ULCAST_(1) << 25)
4132 +
4133 +
4134 +/*
4135 + * Bits in the cp0 config register select 1.
4136 + */
4137 +#define CONF1_FP 0x00000001 /* FPU present */
4138 +#define CONF1_EP 0x00000002 /* EJTAG present */
4139 +#define CONF1_CA 0x00000004 /* mips16 implemented */
4140 +#define CONF1_WR 0x00000008 /* Watch registers present */
4141 +#define CONF1_PC 0x00000010 /* Performance counters present */
4142 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
4143 +#define CONF1_DA_MASK 0x00000380
4144 +#define CONF1_DA_BASE 1
4145 +#define CONF1_DL_SHIFT 10 /* D$ line size */
4146 +#define CONF1_DL_MASK 0x00001c00
4147 +#define CONF1_DL_BASE 2
4148 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
4149 +#define CONF1_DS_MASK 0x0000e000
4150 +#define CONF1_DS_BASE 64
4151 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
4152 +#define CONF1_IA_MASK 0x00070000
4153 +#define CONF1_IA_BASE 1
4154 +#define CONF1_IL_SHIFT 19 /* I$ line size */
4155 +#define CONF1_IL_MASK 0x00380000
4156 +#define CONF1_IL_BASE 2
4157 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
4158 +#define CONF1_IS_MASK 0x01c00000
4159 +#define CONF1_IS_BASE 64
4160 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
4161 +#define CONF1_MS_SHIFT 25
4162 +
4163 +/* PRID register */
4164 +#define PRID_COPT_MASK 0xff000000
4165 +#define PRID_COMP_MASK 0x00ff0000
4166 +#define PRID_IMP_MASK 0x0000ff00
4167 +#define PRID_REV_MASK 0x000000ff
4168 +
4169 +#define PRID_COMP_LEGACY 0x000000
4170 +#define PRID_COMP_MIPS 0x010000
4171 +#define PRID_COMP_BROADCOM 0x020000
4172 +#define PRID_COMP_ALCHEMY 0x030000
4173 +#define PRID_COMP_SIBYTE 0x040000
4174 +#define PRID_IMP_BCM4710 0x4000
4175 +#define PRID_IMP_BCM3302 0x9000
4176 +#define PRID_IMP_BCM3303 0x9100
4177 +
4178 +#define PRID_IMP_UNKNOWN 0xff00
4179 +
4180 +#define BCM330X(id) \
4181 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
4182 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
4183 +
4184 +/* Bits in C0_BROADCOM */
4185 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
4186 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
4187 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
4188 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
4189 +
4190 +/* PreFetch Cache aka Read Ahead Cache */
4191 +
4192 +#define PFC_CR0 0xff400000 /* control reg 0 */
4193 +#define PFC_CR1 0xff400004 /* control reg 1 */
4194 +
4195 +/* PFC operations */
4196 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
4197 +#define PFC_D 0x00000002 /* Enable PFC use for data */
4198 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
4199 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
4200 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
4201 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
4202 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
4203 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
4204 +#define PFC_BRR 0x40000000 /* Bus error indication */
4205 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
4206 +
4207 +/* Handy defaults */
4208 +#define PFC_DISABLED 0
4209 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
4210 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
4211 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
4212 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
4213 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
4214 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
4215 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
4216 +
4217 +
4218 +/*
4219 + * These are the UART port assignments, expressed as offsets from the base
4220 + * register. These assignments should hold for any serial port based on
4221 + * a 8250, 16450, or 16550(A).
4222 + */
4223 +
4224 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
4225 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
4226 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
4227 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
4228 +#define UART_LCR 3 /* Out: Line Control Register */
4229 +#define UART_MCR 4 /* Out: Modem Control Register */
4230 +#define UART_LSR 5 /* In: Line Status Register */
4231 +#define UART_MSR 6 /* In: Modem Status Register */
4232 +#define UART_SCR 7 /* I/O: Scratch Register */
4233 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
4234 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
4235 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
4236 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
4237 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
4238 +
4239 +
4240 +#ifndef _LANGUAGE_ASSEMBLY
4241 +
4242 +/*
4243 + * Macros to access the system control coprocessor
4244 + */
4245 +
4246 +#define MFC0(source, sel) \
4247 +({ \
4248 + int __res; \
4249 + __asm__ __volatile__( \
4250 + ".set\tnoreorder\n\t" \
4251 + ".set\tnoat\n\t" \
4252 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
4253 + "move\t%0,$1\n\t" \
4254 + ".set\tat\n\t" \
4255 + ".set\treorder" \
4256 + :"=r" (__res) \
4257 + : \
4258 + :"$1"); \
4259 + __res; \
4260 +})
4261 +
4262 +#define MTC0(source, sel, value) \
4263 +do { \
4264 + __asm__ __volatile__( \
4265 + ".set\tnoreorder\n\t" \
4266 + ".set\tnoat\n\t" \
4267 + "move\t$1,%z0\n\t" \
4268 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
4269 + ".set\tat\n\t" \
4270 + ".set\treorder" \
4271 + : \
4272 + :"jr" (value) \
4273 + :"$1"); \
4274 +} while (0)
4275 +
4276 +#define get_c0_count() \
4277 +({ \
4278 + int __res; \
4279 + __asm__ __volatile__( \
4280 + ".set\tnoreorder\n\t" \
4281 + ".set\tnoat\n\t" \
4282 + "mfc0\t%0,$9\n\t" \
4283 + ".set\tat\n\t" \
4284 + ".set\treorder" \
4285 + :"=r" (__res)); \
4286 + __res; \
4287 +})
4288 +
4289 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
4290 +{
4291 + uint lsz, sets, ways;
4292 +
4293 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
4294 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
4295 + lsz = CONF1_IL_BASE << lsz;
4296 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
4297 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
4298 + *size = lsz * sets * ways;
4299 + *lsize = lsz;
4300 +}
4301 +
4302 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
4303 +{
4304 + uint lsz, sets, ways;
4305 +
4306 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
4307 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
4308 + lsz = CONF1_DL_BASE << lsz;
4309 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
4310 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
4311 + *size = lsz * sets * ways;
4312 + *lsize = lsz;
4313 +}
4314 +
4315 +#define cache_op(base, op) \
4316 + __asm__ __volatile__(" \
4317 + .set noreorder; \
4318 + .set mips3; \
4319 + cache %1, (%0); \
4320 + .set mips0; \
4321 + .set reorder" \
4322 + : \
4323 + : "r" (base), \
4324 + "i" (op));
4325 +
4326 +#define cache_unroll4(base, delta, op) \
4327 + __asm__ __volatile__(" \
4328 + .set noreorder; \
4329 + .set mips3; \
4330 + cache %1,0(%0); \
4331 + cache %1,delta(%0); \
4332 + cache %1,(2 * delta)(%0); \
4333 + cache %1,(3 * delta)(%0); \
4334 + .set mips0; \
4335 + .set reorder" \
4336 + : \
4337 + : "r" (base), \
4338 + "i" (op));
4339 +
4340 +#endif /* !_LANGUAGE_ASSEMBLY */
4341 +
4342 +#endif /* _MISPINC_H */
4343 diff -urN linux.old/arch/mips/bcm947xx/include/nvports.h linux.dev/arch/mips/bcm947xx/include/nvports.h
4344 --- linux.old/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
4345 +++ linux.dev/arch/mips/bcm947xx/include/nvports.h 2005-11-07 21:57:07.865587000 +0100
4346 @@ -0,0 +1,55 @@
4347 +/*
4348 + * BCM53xx RoboSwitch utility functions
4349 + *
4350 + * Copyright (C) 2002 Broadcom Corporation
4351 + * $Id$
4352 + */
4353 +
4354 +#ifndef _nvports_h_
4355 +#define _nvports_h_
4356 +
4357 +#define uint32 unsigned long
4358 +#define uint16 unsigned short
4359 +#define uint unsigned int
4360 +#define uint8 unsigned char
4361 +#define uint64 unsigned long long
4362 +
4363 +enum FORCE_PORT {
4364 + FORCE_OFF,
4365 + FORCE_10H,
4366 + FORCE_10F,
4367 + FORCE_100H,
4368 + FORCE_100F,
4369 + FORCE_DOWN,
4370 + POWER_OFF
4371 +};
4372 +
4373 +typedef struct _PORT_ATTRIBS
4374 +{
4375 + uint autoneg;
4376 + uint force;
4377 + uint native;
4378 +} PORT_ATTRIBS;
4379 +
4380 +extern uint
4381 +nvExistsPortAttrib(char *attrib, uint portno);
4382 +
4383 +extern int
4384 +nvExistsAnyForcePortAttrib(uint portno);
4385 +
4386 +extern void
4387 +nvSetPortAttrib(char *attrib, uint portno);
4388 +
4389 +extern void
4390 +nvUnsetPortAttrib(char *attrib, uint portno);
4391 +
4392 +extern void
4393 +nvUnsetAllForcePortAttrib(uint portno);
4394 +
4395 +extern PORT_ATTRIBS
4396 +nvGetSwitchPortAttribs(uint portno);
4397 +
4398 +#endif /* _nvports_h_ */
4399 +
4400 +
4401 +
4402 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
4403 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
4404 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-11-07 22:51:38.780726250 +0100
4405 @@ -0,0 +1,42 @@
4406 +/*
4407 + * OS Abstraction Layer
4408 + *
4409 + * Copyright 2005, Broadcom Corporation
4410 + * All Rights Reserved.
4411 + *
4412 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4413 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4414 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4415 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4416 + * $Id$
4417 + */
4418 +
4419 +#ifndef _osl_h_
4420 +#define _osl_h_
4421 +
4422 +/* osl handle type forward declaration */
4423 +typedef struct os_handle osl_t;
4424 +
4425 +#if defined(linux)
4426 +#include <linux_osl.h>
4427 +#elif defined(NDIS)
4428 +#include <ndis_osl.h>
4429 +#elif defined(_CFE_)
4430 +#include <cfe_osl.h>
4431 +#elif defined(_HNDRTE_)
4432 +#include <hndrte_osl.h>
4433 +#elif defined(_MINOSL_)
4434 +#include <min_osl.h>
4435 +#elif PMON
4436 +#include <pmon_osl.h>
4437 +#elif defined(MACOSX)
4438 +#include <macosx_osl.h>
4439 +#else
4440 +#error "Unsupported OSL requested"
4441 +#endif
4442 +
4443 +/* handy */
4444 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
4445 +#define MAXPRIO 7 /* 0-7 */
4446 +
4447 +#endif /* _osl_h_ */
4448 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
4449 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
4450 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-11-07 22:51:38.780726250 +0100
4451 @@ -0,0 +1,451 @@
4452 +/*
4453 + * pcicfg.h: PCI configuration constants and structures.
4454 + *
4455 + * Copyright 2005, Broadcom Corporation
4456 + * All Rights Reserved.
4457 + *
4458 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4459 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4460 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4461 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4462 + *
4463 + * $Id$
4464 + */
4465 +
4466 +#ifndef _h_pci_
4467 +#define _h_pci_
4468 +
4469 +/* The following inside ifndef's so we don't collide with NTDDK.H */
4470 +#ifndef PCI_MAX_BUS
4471 +#define PCI_MAX_BUS 0x100
4472 +#endif
4473 +#ifndef PCI_MAX_DEVICES
4474 +#define PCI_MAX_DEVICES 0x20
4475 +#endif
4476 +#ifndef PCI_MAX_FUNCTION
4477 +#define PCI_MAX_FUNCTION 0x8
4478 +#endif
4479 +
4480 +#ifndef PCI_INVALID_VENDORID
4481 +#define PCI_INVALID_VENDORID 0xffff
4482 +#endif
4483 +#ifndef PCI_INVALID_DEVICEID
4484 +#define PCI_INVALID_DEVICEID 0xffff
4485 +#endif
4486 +
4487 +
4488 +/* Convert between bus-slot-function-register and config addresses */
4489 +
4490 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
4491 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
4492 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
4493 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
4494 +
4495 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
4496 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
4497 +#define PCICFG_FUN_MASK 7 /* Function mask */
4498 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
4499 +
4500 +#define PCI_CONFIG_ADDR(b, s, f, o) \
4501 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
4502 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
4503 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
4504 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
4505 +
4506 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
4507 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
4508 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
4509 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
4510 +
4511 +/* PCIE Config space accessing MACROS*/
4512 +
4513 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
4514 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
4515 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
4516 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
4517 +
4518 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
4519 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
4520 +#define PCIECFG_FUN_MASK 7 /* Function mask */
4521 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
4522 +
4523 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
4524 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
4525 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
4526 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
4527 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
4528 +
4529 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
4530 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
4531 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
4532 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
4533 +
4534 +
4535 +/* The actual config space */
4536 +
4537 +#define PCI_BAR_MAX 6
4538 +
4539 +#define PCI_ROM_BAR 8
4540 +
4541 +#define PCR_RSVDA_MAX 2
4542 +
4543 +/* pci config status reg has a bit to indicate that capability ptr is present*/
4544 +
4545 +#define PCI_CAPPTR_PRESENT 0x0010
4546 +
4547 +typedef struct _pci_config_regs {
4548 + unsigned short vendor;
4549 + unsigned short device;
4550 + unsigned short command;
4551 + unsigned short status;
4552 + unsigned char rev_id;
4553 + unsigned char prog_if;
4554 + unsigned char sub_class;
4555 + unsigned char base_class;
4556 + unsigned char cache_line_size;
4557 + unsigned char latency_timer;
4558 + unsigned char header_type;
4559 + unsigned char bist;
4560 + unsigned long base[PCI_BAR_MAX];
4561 + unsigned long cardbus_cis;
4562 + unsigned short subsys_vendor;
4563 + unsigned short subsys_id;
4564 + unsigned long baserom;
4565 + unsigned long rsvd_a[PCR_RSVDA_MAX];
4566 + unsigned char int_line;
4567 + unsigned char int_pin;
4568 + unsigned char min_gnt;
4569 + unsigned char max_lat;
4570 + unsigned char dev_dep[192];
4571 +} pci_config_regs;
4572 +
4573 +#define SZPCR (sizeof (pci_config_regs))
4574 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
4575 +
4576 +/* A structure for the config registers is nice, but in most
4577 + * systems the config space is not memory mapped, so we need
4578 + * filed offsetts. :-(
4579 + */
4580 +#define PCI_CFG_VID 0
4581 +#define PCI_CFG_DID 2
4582 +#define PCI_CFG_CMD 4
4583 +#define PCI_CFG_STAT 6
4584 +#define PCI_CFG_REV 8
4585 +#define PCI_CFG_PROGIF 9
4586 +#define PCI_CFG_SUBCL 0xa
4587 +#define PCI_CFG_BASECL 0xb
4588 +#define PCI_CFG_CLSZ 0xc
4589 +#define PCI_CFG_LATTIM 0xd
4590 +#define PCI_CFG_HDR 0xe
4591 +#define PCI_CFG_BIST 0xf
4592 +#define PCI_CFG_BAR0 0x10
4593 +#define PCI_CFG_BAR1 0x14
4594 +#define PCI_CFG_BAR2 0x18
4595 +#define PCI_CFG_BAR3 0x1c
4596 +#define PCI_CFG_BAR4 0x20
4597 +#define PCI_CFG_BAR5 0x24
4598 +#define PCI_CFG_CIS 0x28
4599 +#define PCI_CFG_SVID 0x2c
4600 +#define PCI_CFG_SSID 0x2e
4601 +#define PCI_CFG_ROMBAR 0x30
4602 +#define PCI_CFG_CAPPTR 0x34
4603 +#define PCI_CFG_INT 0x3c
4604 +#define PCI_CFG_PIN 0x3d
4605 +#define PCI_CFG_MINGNT 0x3e
4606 +#define PCI_CFG_MAXLAT 0x3f
4607 +
4608 +/* Classes and subclasses */
4609 +
4610 +typedef enum {
4611 + PCI_CLASS_OLD = 0,
4612 + PCI_CLASS_DASDI,
4613 + PCI_CLASS_NET,
4614 + PCI_CLASS_DISPLAY,
4615 + PCI_CLASS_MMEDIA,
4616 + PCI_CLASS_MEMORY,
4617 + PCI_CLASS_BRIDGE,
4618 + PCI_CLASS_COMM,
4619 + PCI_CLASS_BASE,
4620 + PCI_CLASS_INPUT,
4621 + PCI_CLASS_DOCK,
4622 + PCI_CLASS_CPU,
4623 + PCI_CLASS_SERIAL,
4624 + PCI_CLASS_INTELLIGENT = 0xe,
4625 + PCI_CLASS_SATELLITE,
4626 + PCI_CLASS_CRYPT,
4627 + PCI_CLASS_DSP,
4628 + PCI_CLASS_MAX
4629 +} pci_classes;
4630 +
4631 +typedef enum {
4632 + PCI_DASDI_SCSI,
4633 + PCI_DASDI_IDE,
4634 + PCI_DASDI_FLOPPY,
4635 + PCI_DASDI_IPI,
4636 + PCI_DASDI_RAID,
4637 + PCI_DASDI_OTHER = 0x80
4638 +} pci_dasdi_subclasses;
4639 +
4640 +typedef enum {
4641 + PCI_NET_ETHER,
4642 + PCI_NET_TOKEN,
4643 + PCI_NET_FDDI,
4644 + PCI_NET_ATM,
4645 + PCI_NET_OTHER = 0x80
4646 +} pci_net_subclasses;
4647 +
4648 +typedef enum {
4649 + PCI_DISPLAY_VGA,
4650 + PCI_DISPLAY_XGA,
4651 + PCI_DISPLAY_3D,
4652 + PCI_DISPLAY_OTHER = 0x80
4653 +} pci_display_subclasses;
4654 +
4655 +typedef enum {
4656 + PCI_MMEDIA_VIDEO,
4657 + PCI_MMEDIA_AUDIO,
4658 + PCI_MMEDIA_PHONE,
4659 + PCI_MEDIA_OTHER = 0x80
4660 +} pci_mmedia_subclasses;
4661 +
4662 +typedef enum {
4663 + PCI_MEMORY_RAM,
4664 + PCI_MEMORY_FLASH,
4665 + PCI_MEMORY_OTHER = 0x80
4666 +} pci_memory_subclasses;
4667 +
4668 +typedef enum {
4669 + PCI_BRIDGE_HOST,
4670 + PCI_BRIDGE_ISA,
4671 + PCI_BRIDGE_EISA,
4672 + PCI_BRIDGE_MC,
4673 + PCI_BRIDGE_PCI,
4674 + PCI_BRIDGE_PCMCIA,
4675 + PCI_BRIDGE_NUBUS,
4676 + PCI_BRIDGE_CARDBUS,
4677 + PCI_BRIDGE_RACEWAY,
4678 + PCI_BRIDGE_OTHER = 0x80
4679 +} pci_bridge_subclasses;
4680 +
4681 +typedef enum {
4682 + PCI_COMM_UART,
4683 + PCI_COMM_PARALLEL,
4684 + PCI_COMM_MULTIUART,
4685 + PCI_COMM_MODEM,
4686 + PCI_COMM_OTHER = 0x80
4687 +} pci_comm_subclasses;
4688 +
4689 +typedef enum {
4690 + PCI_BASE_PIC,
4691 + PCI_BASE_DMA,
4692 + PCI_BASE_TIMER,
4693 + PCI_BASE_RTC,
4694 + PCI_BASE_PCI_HOTPLUG,
4695 + PCI_BASE_OTHER = 0x80
4696 +} pci_base_subclasses;
4697 +
4698 +typedef enum {
4699 + PCI_INPUT_KBD,
4700 + PCI_INPUT_PEN,
4701 + PCI_INPUT_MOUSE,
4702 + PCI_INPUT_SCANNER,
4703 + PCI_INPUT_GAMEPORT,
4704 + PCI_INPUT_OTHER = 0x80
4705 +} pci_input_subclasses;
4706 +
4707 +typedef enum {
4708 + PCI_DOCK_GENERIC,
4709 + PCI_DOCK_OTHER = 0x80
4710 +} pci_dock_subclasses;
4711 +
4712 +typedef enum {
4713 + PCI_CPU_386,
4714 + PCI_CPU_486,
4715 + PCI_CPU_PENTIUM,
4716 + PCI_CPU_ALPHA = 0x10,
4717 + PCI_CPU_POWERPC = 0x20,
4718 + PCI_CPU_MIPS = 0x30,
4719 + PCI_CPU_COPROC = 0x40,
4720 + PCI_CPU_OTHER = 0x80
4721 +} pci_cpu_subclasses;
4722 +
4723 +typedef enum {
4724 + PCI_SERIAL_IEEE1394,
4725 + PCI_SERIAL_ACCESS,
4726 + PCI_SERIAL_SSA,
4727 + PCI_SERIAL_USB,
4728 + PCI_SERIAL_FIBER,
4729 + PCI_SERIAL_SMBUS,
4730 + PCI_SERIAL_OTHER = 0x80
4731 +} pci_serial_subclasses;
4732 +
4733 +typedef enum {
4734 + PCI_INTELLIGENT_I2O,
4735 +} pci_intelligent_subclasses;
4736 +
4737 +typedef enum {
4738 + PCI_SATELLITE_TV,
4739 + PCI_SATELLITE_AUDIO,
4740 + PCI_SATELLITE_VOICE,
4741 + PCI_SATELLITE_DATA,
4742 + PCI_SATELLITE_OTHER = 0x80
4743 +} pci_satellite_subclasses;
4744 +
4745 +typedef enum {
4746 + PCI_CRYPT_NETWORK,
4747 + PCI_CRYPT_ENTERTAINMENT,
4748 + PCI_CRYPT_OTHER = 0x80
4749 +} pci_crypt_subclasses;
4750 +
4751 +typedef enum {
4752 + PCI_DSP_DPIO,
4753 + PCI_DSP_OTHER = 0x80
4754 +} pci_dsp_subclasses;
4755 +
4756 +/* Header types */
4757 +typedef enum {
4758 + PCI_HEADER_NORMAL,
4759 + PCI_HEADER_BRIDGE,
4760 + PCI_HEADER_CARDBUS
4761 +} pci_header_types;
4762 +
4763 +
4764 +/* Overlay for a PCI-to-PCI bridge */
4765 +
4766 +#define PPB_RSVDA_MAX 2
4767 +#define PPB_RSVDD_MAX 8
4768 +
4769 +typedef struct _ppb_config_regs {
4770 + unsigned short vendor;
4771 + unsigned short device;
4772 + unsigned short command;
4773 + unsigned short status;
4774 + unsigned char rev_id;
4775 + unsigned char prog_if;
4776 + unsigned char sub_class;
4777 + unsigned char base_class;
4778 + unsigned char cache_line_size;
4779 + unsigned char latency_timer;
4780 + unsigned char header_type;
4781 + unsigned char bist;
4782 + unsigned long rsvd_a[PPB_RSVDA_MAX];
4783 + unsigned char prim_bus;
4784 + unsigned char sec_bus;
4785 + unsigned char sub_bus;
4786 + unsigned char sec_lat;
4787 + unsigned char io_base;
4788 + unsigned char io_lim;
4789 + unsigned short sec_status;
4790 + unsigned short mem_base;
4791 + unsigned short mem_lim;
4792 + unsigned short pf_mem_base;
4793 + unsigned short pf_mem_lim;
4794 + unsigned long pf_mem_base_hi;
4795 + unsigned long pf_mem_lim_hi;
4796 + unsigned short io_base_hi;
4797 + unsigned short io_lim_hi;
4798 + unsigned short subsys_vendor;
4799 + unsigned short subsys_id;
4800 + unsigned long rsvd_b;
4801 + unsigned char rsvd_c;
4802 + unsigned char int_pin;
4803 + unsigned short bridge_ctrl;
4804 + unsigned char chip_ctrl;
4805 + unsigned char diag_ctrl;
4806 + unsigned short arb_ctrl;
4807 + unsigned long rsvd_d[PPB_RSVDD_MAX];
4808 + unsigned char dev_dep[192];
4809 +} ppb_config_regs;
4810 +
4811 +
4812 +/* PCI CAPABILITY DEFINES */
4813 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
4814 +#define PCI_CAP_MSICAP_ID 0x05
4815 +#define PCI_CAP_PCIECAP_ID 0x10
4816 +
4817 +/* Data structure to define the Message Signalled Interrupt facility
4818 + * Valid for PCI and PCIE configurations */
4819 +typedef struct _pciconfig_cap_msi {
4820 + unsigned char capID;
4821 + unsigned char nextptr;
4822 + unsigned short msgctrl;
4823 + unsigned int msgaddr;
4824 +} pciconfig_cap_msi;
4825 +
4826 +/* Data structure to define the Power managment facility
4827 + * Valid for PCI and PCIE configurations */
4828 +typedef struct _pciconfig_cap_pwrmgmt {
4829 + unsigned char capID;
4830 + unsigned char nextptr;
4831 + unsigned short pme_cap;
4832 + unsigned short pme_sts_ctrl;
4833 + unsigned char pme_bridge_ext;
4834 + unsigned char data;
4835 +} pciconfig_cap_pwrmgmt;
4836 +
4837 +/* Data structure to define the PCIE capability */
4838 +typedef struct _pciconfig_cap_pcie {
4839 + unsigned char capID;
4840 + unsigned char nextptr;
4841 + unsigned short pcie_cap;
4842 + unsigned int dev_cap;
4843 + unsigned short dev_ctrl;
4844 + unsigned short dev_status;
4845 + unsigned int link_cap;
4846 + unsigned short link_ctrl;
4847 + unsigned short link_status;
4848 +} pciconfig_cap_pcie;
4849 +
4850 +/* PCIE Enhanced CAPABILITY DEFINES */
4851 +#define PCIE_EXTCFG_OFFSET 0x100
4852 +#define PCIE_ADVERRREP_CAPID 0x0001
4853 +#define PCIE_VC_CAPID 0x0002
4854 +#define PCIE_DEVSNUM_CAPID 0x0003
4855 +#define PCIE_PWRBUDGET_CAPID 0x0004
4856 +
4857 +/* Header to define the PCIE specific capabilities in the extended config space */
4858 +typedef struct _pcie_enhanced_caphdr {
4859 + unsigned short capID;
4860 + unsigned short cap_ver : 4;
4861 + unsigned short next_ptr : 12;
4862 +} pcie_enhanced_caphdr;
4863 +
4864 +
4865 +/* Everything below is BRCM HND proprietary */
4866 +
4867 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
4868 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
4869 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
4870 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
4871 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
4872 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
4873 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
4874 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
4875 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
4876 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
4877 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
4878 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
4879 +
4880 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
4881 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
4882 +
4883 +/* PCI_INT_STATUS */
4884 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
4885 +
4886 +/* PCI_INT_MASK */
4887 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
4888 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
4889 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
4890 +
4891 +/* PCI_SPROM_CONTROL */
4892 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
4893 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
4894 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
4895 +
4896 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
4897 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
4898 +
4899 +/* PCI_CFG_CMD_STAT */
4900 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
4901 +
4902 +#endif
4903 diff -urN linux.old/arch/mips/bcm947xx/include/pmon_osl.h linux.dev/arch/mips/bcm947xx/include/pmon_osl.h
4904 --- linux.old/arch/mips/bcm947xx/include/pmon_osl.h 1970-01-01 01:00:00.000000000 +0100
4905 +++ linux.dev/arch/mips/bcm947xx/include/pmon_osl.h 2005-11-07 21:57:07.869587250 +0100
4906 @@ -0,0 +1,126 @@
4907 +/*
4908 + * MIPS PMON boot loader OS Abstraction Layer.
4909 + *
4910 + * Copyright 2005, Broadcom Corporation
4911 + * All Rights Reserved.
4912 + *
4913 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
4914 + * the contents of this file may not be disclosed to third parties, copied
4915 + * or duplicated in any form, in whole or in part, without the prior
4916 + * written permission of Broadcom Corporation.
4917 + * $Id$
4918 + */
4919 +
4920 +#ifndef _pmon_osl_h_
4921 +#define _pmon_osl_h_
4922 +
4923 +#include <typedefs.h>
4924 +#include <mips.h>
4925 +#include <string.h>
4926 +#include <utypes.h>
4927 +
4928 +extern int printf(char *fmt,...);
4929 +extern int sprintf(char *dst,char *fmt,...);
4930 +
4931 +#define OSL_UNCACHED(va) phy2k1(log2phy((va)))
4932 +#define REG_MAP(pa, size) phy2k1((pa))
4933 +#define REG_UNMAP(va) /* nop */
4934 +
4935 +/* Common macros */
4936 +
4937 +#define BUSPROBE(val, addr) ((val) = *(addr))
4938 +
4939 +#define ASSERT(exp)
4940 +
4941 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) bzero(buf, size)
4942 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
4943 +
4944 +/* kludge */
4945 +#define OSL_PCI_READ_CONFIG(loc, offset, size) ((offset == 8)? 0: 0xffffffff)
4946 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) ASSERT(0)
4947 +
4948 +#define wreg32(r,v) (*(volatile uint32 *)(r) = (v))
4949 +#define rreg32(r) (*(volatile uint32 *)(r))
4950 +#ifdef IL_BIGENDIAN
4951 +#define wreg16(r,v) (*(volatile uint16 *)((uint32)r^2) = (v))
4952 +#define rreg16(r) (*(volatile uint16 *)((uint32)r^2))
4953 +#else
4954 +#define wreg16(r,v) (*(volatile uint16 *)(r) = (v))
4955 +#define rreg16(r) (*(volatile uint16 *)(r))
4956 +#endif
4957 +
4958 +#include <memory.h>
4959 +#define bcopy(src, dst, len) memcpy(dst, src, len)
4960 +#define bcmp(b1, b2, len) memcmp(b1, b2, len)
4961 +#define bzero(b, len) memset(b, '\0', len)
4962 +
4963 +/* register access macros */
4964 +#define R_REG(r) ((sizeof *(r) == sizeof (uint32))? rreg32(r): rreg16(r))
4965 +#define W_REG(r,v) ((sizeof *(r) == sizeof (uint32))? wreg32(r,(uint32)v): wreg16(r,(uint16)v))
4966 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
4967 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
4968 +
4969 +#define R_SM(r) *(r)
4970 +#define W_SM(r, v) (*(r) = (v))
4971 +#define BZERO_SM(r, len) memset(r, '\0', len)
4972 +
4973 +/* Host/Bus architecture specific swap. Noop for little endian systems, possible swap on big endian */
4974 +#define BUS_SWAP32(v) (v)
4975 +
4976 +#define OSL_DELAY(usec) delay_us(usec)
4977 +extern void delay_us(uint usec);
4978 +
4979 +#define OSL_GETCYCLES(x) ((x) = 0)
4980 +
4981 +#define osl_attach(pdev) (pdev)
4982 +#define osl_detach(osh)
4983 +
4984 +#define MALLOC(osh, size) malloc(size)
4985 +#define MFREE(osh, addr, size) free(addr)
4986 +#define MALLOCED(osh) (0)
4987 +#define MALLOC_DUMP(osh, buf, sz)
4988 +#define MALLOC_FAILED(osh)
4989 +extern void *malloc();
4990 +extern void free(void *addr);
4991 +
4992 +#define DMA_CONSISTENT_ALIGN sizeof (int)
4993 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) et_dma_alloc_consistent(osh, size, pap)
4994 +#define DMA_FREE_CONSISTENT(osh, va, size, pa)
4995 +extern void* et_dma_alloc_consistent(void *osh, uint size, ulong *pap);
4996 +#define DMA_TX 0
4997 +#define DMA_RX 1
4998 +
4999 +#define DMA_MAP(osh, va, size, direction, p) osl_dma_map(osh, (void*)va, size, direction)
5000 +#define DMA_UNMAP(osh, pa, size, direction, p) /* nop */
5001 +extern void* osl_dma_map(void *osh, void *va, uint size, uint direction);
5002 +
5003 +struct lbuf {
5004 + struct lbuf *next; /* pointer to next lbuf on freelist */
5005 + uchar *buf; /* pointer to buffer */
5006 + uint len; /* nbytes of data */
5007 +};
5008 +
5009 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
5010 +#define PKTBUFSZ 2048
5011 +
5012 +/* packet primitives */
5013 +#define PKTGET(drv, len, send) et_pktget(drv, len, send)
5014 +#define PKTFREE(drv, lb, send) et_pktfree(drv, (struct lbuf*)lb, send)
5015 +#define PKTDATA(drv, lb) ((uchar*)OSL_UNCACHED(((struct lbuf*)lb)->buf))
5016 +#define PKTLEN(drv, lb) ((struct lbuf*)lb)->len
5017 +#define PKTHEADROOM(drv, lb) (0)
5018 +#define PKTTAILROOM(drv, lb) (0)
5019 +#define PKTNEXT(drv, lb) NULL
5020 +#define PKTSETNEXT(lb, x) ASSERT(0)
5021 +#define PKTSETLEN(drv, lb, bytes) ((struct lbuf*)lb)->len = bytes
5022 +#define PKTPUSH(drv, lb, bytes) ASSERT(0)
5023 +#define PKTPULL(drv, lb, bytes) ASSERT(0)
5024 +#define PKTDUP(drv, lb) ASSERT(0)
5025 +#define PKTLINK(lb) ((struct lbuf*)lb)->next
5026 +#define PKTSETLINK(lb, x) ((struct lbuf*)lb)->next = (struct lbuf*)x
5027 +#define PKTPRIO(lb) (0)
5028 +#define PKTSETPRIO(lb, x) do {} while (0)
5029 +extern void *et_pktget(void *drv, uint len, bool send);
5030 +extern void et_pktfree(void *drv, struct lbuf *lb, bool send);
5031 +
5032 +#endif /* _pmon_osl_h_ */
5033 diff -urN linux.old/arch/mips/bcm947xx/include/proto/802.11.h linux.dev/arch/mips/bcm947xx/include/proto/802.11.h
5034 --- linux.old/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
5035 +++ linux.dev/arch/mips/bcm947xx/include/proto/802.11.h 2005-11-07 22:51:38.784726500 +0100
5036 @@ -0,0 +1,930 @@
5037 +/*
5038 + * Copyright 2005, Broadcom Corporation
5039 + * All Rights Reserved.
5040 + *
5041 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5042 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5043 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5044 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5045 + *
5046 + * Fundamental types and constants relating to 802.11
5047 + *
5048 + * $Id$
5049 + */
5050 +
5051 +#ifndef _802_11_H_
5052 +#define _802_11_H_
5053 +
5054 +#ifndef _TYPEDEFS_H_
5055 +#include <typedefs.h>
5056 +#endif
5057 +
5058 +#ifndef _NET_ETHERNET_H_
5059 +#include <proto/ethernet.h>
5060 +#endif
5061 +
5062 +#include <proto/wpa.h>
5063 +
5064 +
5065 +/* enable structure packing */
5066 +#if defined(__GNUC__)
5067 +#define PACKED __attribute__((packed))
5068 +#else
5069 +#pragma pack(1)
5070 +#define PACKED
5071 +#endif
5072 +
5073 +#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
5074 +
5075 +/* Generic 802.11 frame constants */
5076 +#define DOT11_A3_HDR_LEN 24
5077 +#define DOT11_A4_HDR_LEN 30
5078 +#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
5079 +#define DOT11_FCS_LEN 4
5080 +#define DOT11_ICV_LEN 4
5081 +#define DOT11_ICV_AES_LEN 8
5082 +#define DOT11_QOS_LEN 2
5083 +
5084 +#define DOT11_KEY_INDEX_SHIFT 6
5085 +#define DOT11_IV_LEN 4
5086 +#define DOT11_IV_TKIP_LEN 8
5087 +#define DOT11_IV_AES_OCB_LEN 4
5088 +#define DOT11_IV_AES_CCM_LEN 8
5089 +
5090 +/* Includes MIC */
5091 +#define DOT11_MAX_MPDU_BODY_LEN 2304
5092 +/* A4 header + QoS + CCMP + PDU + ICV + FCS = 2352 */
5093 +#define DOT11_MAX_MPDU_LEN (DOT11_A4_HDR_LEN + \
5094 + DOT11_QOS_LEN + \
5095 + DOT11_IV_AES_CCM_LEN + \
5096 + DOT11_MAX_MPDU_BODY_LEN + \
5097 + DOT11_ICV_LEN + \
5098 + DOT11_FCS_LEN)
5099 +
5100 +#define DOT11_MAX_SSID_LEN 32
5101 +
5102 +/* dot11RTSThreshold */
5103 +#define DOT11_DEFAULT_RTS_LEN 2347
5104 +#define DOT11_MAX_RTS_LEN 2347
5105 +
5106 +/* dot11FragmentationThreshold */
5107 +#define DOT11_MIN_FRAG_LEN 256
5108 +#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
5109 +#define DOT11_DEFAULT_FRAG_LEN 2346
5110 +
5111 +/* dot11BeaconPeriod */
5112 +#define DOT11_MIN_BEACON_PERIOD 1
5113 +#define DOT11_MAX_BEACON_PERIOD 0xFFFF
5114 +
5115 +/* dot11DTIMPeriod */
5116 +#define DOT11_MIN_DTIM_PERIOD 1
5117 +#define DOT11_MAX_DTIM_PERIOD 0xFF
5118 +
5119 +/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
5120 +#define DOT11_LLC_SNAP_HDR_LEN 8
5121 +#define DOT11_OUI_LEN 3
5122 +struct dot11_llc_snap_header {
5123 + uint8 dsap; /* always 0xAA */
5124 + uint8 ssap; /* always 0xAA */
5125 + uint8 ctl; /* always 0x03 */
5126 + uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
5127 + Bridge-Tunnel: 0x00 0x00 0xF8 */
5128 + uint16 type; /* ethertype */
5129 +} PACKED;
5130 +
5131 +/* RFC1042 header used by 802.11 per 802.1H */
5132 +#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
5133 +
5134 +/* Generic 802.11 MAC header */
5135 +/*
5136 + * N.B.: This struct reflects the full 4 address 802.11 MAC header.
5137 + * The fields are defined such that the shorter 1, 2, and 3
5138 + * address headers just use the first k fields.
5139 + */
5140 +struct dot11_header {
5141 + uint16 fc; /* frame control */
5142 + uint16 durid; /* duration/ID */
5143 + struct ether_addr a1; /* address 1 */
5144 + struct ether_addr a2; /* address 2 */
5145 + struct ether_addr a3; /* address 3 */
5146 + uint16 seq; /* sequence control */
5147 + struct ether_addr a4; /* address 4 */
5148 +} PACKED;
5149 +
5150 +/* Control frames */
5151 +
5152 +struct dot11_rts_frame {
5153 + uint16 fc; /* frame control */
5154 + uint16 durid; /* duration/ID */
5155 + struct ether_addr ra; /* receiver address */
5156 + struct ether_addr ta; /* transmitter address */
5157 +} PACKED;
5158 +#define DOT11_RTS_LEN 16
5159 +
5160 +struct dot11_cts_frame {
5161 + uint16 fc; /* frame control */
5162 + uint16 durid; /* duration/ID */
5163 + struct ether_addr ra; /* receiver address */
5164 +} PACKED;
5165 +#define DOT11_CTS_LEN 10
5166 +
5167 +struct dot11_ack_frame {
5168 + uint16 fc; /* frame control */
5169 + uint16 durid; /* duration/ID */
5170 + struct ether_addr ra; /* receiver address */
5171 +} PACKED;
5172 +#define DOT11_ACK_LEN 10
5173 +
5174 +struct dot11_ps_poll_frame {
5175 + uint16 fc; /* frame control */
5176 + uint16 durid; /* AID */
5177 + struct ether_addr bssid; /* receiver address, STA in AP */
5178 + struct ether_addr ta; /* transmitter address */
5179 +} PACKED;
5180 +#define DOT11_PS_POLL_LEN 16
5181 +
5182 +struct dot11_cf_end_frame {
5183 + uint16 fc; /* frame control */
5184 + uint16 durid; /* duration/ID */
5185 + struct ether_addr ra; /* receiver address */
5186 + struct ether_addr bssid; /* transmitter address, STA in AP */
5187 +} PACKED;
5188 +#define DOT11_CS_END_LEN 16
5189 +
5190 +/* Management frame header */
5191 +struct dot11_management_header {
5192 + uint16 fc; /* frame control */
5193 + uint16 durid; /* duration/ID */
5194 + struct ether_addr da; /* receiver address */
5195 + struct ether_addr sa; /* transmitter address */
5196 + struct ether_addr bssid; /* BSS ID */
5197 + uint16 seq; /* sequence control */
5198 +} PACKED;
5199 +#define DOT11_MGMT_HDR_LEN 24
5200 +
5201 +/* Management frame payloads */
5202 +
5203 +struct dot11_bcn_prb {
5204 + uint32 timestamp[2];
5205 + uint16 beacon_interval;
5206 + uint16 capability;
5207 +} PACKED;
5208 +#define DOT11_BCN_PRB_LEN 12
5209 +
5210 +struct dot11_auth {
5211 + uint16 alg; /* algorithm */
5212 + uint16 seq; /* sequence control */
5213 + uint16 status; /* status code */
5214 +} PACKED;
5215 +#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
5216 +
5217 +struct dot11_assoc_req {
5218 + uint16 capability; /* capability information */
5219 + uint16 listen; /* listen interval */
5220 +} PACKED;
5221 +#define DOT11_ASSOC_REQ_FIXED_LEN 4 /* length of assoc frame without info elts */
5222 +
5223 +struct dot11_reassoc_req {
5224 + uint16 capability; /* capability information */
5225 + uint16 listen; /* listen interval */
5226 + struct ether_addr ap; /* Current AP address */
5227 +} PACKED;
5228 +#define DOT11_REASSOC_REQ_FIXED_LEN 10 /* length of assoc frame without info elts */
5229 +
5230 +struct dot11_assoc_resp {
5231 + uint16 capability; /* capability information */
5232 + uint16 status; /* status code */
5233 + uint16 aid; /* association ID */
5234 +} PACKED;
5235 +
5236 +struct dot11_action_measure {
5237 + uint8 category;
5238 + uint8 action;
5239 + uint8 token;
5240 + uint8 data[1];
5241 +} PACKED;
5242 +#define DOT11_ACTION_MEASURE_LEN 3
5243 +
5244 +struct dot11_action_switch_channel {
5245 + uint8 category;
5246 + uint8 action;
5247 + uint8 data[5]; /* for switch IE */
5248 +} PACKED;
5249 +
5250 +/**************
5251 + 802.11h related definitions.
5252 +**************/
5253 +typedef struct {
5254 + uint8 id;
5255 + uint8 len;
5256 + uint8 power;
5257 +} dot11_power_cnst_t;
5258 +
5259 +typedef struct {
5260 + uint8 min;
5261 + uint8 max;
5262 +} dot11_power_cap_t;
5263 +
5264 +typedef struct {
5265 + uint8 id;
5266 + uint8 len;
5267 + uint8 tx_pwr;
5268 + uint8 margin;
5269 +} dot11_tpc_rep_t;
5270 +#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
5271 +
5272 +typedef struct {
5273 + uint8 id;
5274 + uint8 len;
5275 + uint8 first_channel;
5276 + uint8 num_channels;
5277 +} dot11_supp_channels_t;
5278 +
5279 +/* csa mode type */
5280 +#define DOT11_CSA_MODE_ADVISORY 0
5281 +#define DOT11_CSA_MODE_NO_TX 1
5282 +struct dot11_channel_switch {
5283 + uint8 id;
5284 + uint8 len;
5285 + uint8 mode;
5286 + uint8 channel;
5287 + uint8 count;
5288 +} PACKED;
5289 +typedef struct dot11_channel_switch dot11_channel_switch_t;
5290 +
5291 +/* length of IE data, not including 2 byte header */
5292 +#define DOT11_SWITCH_IE_LEN 3
5293 +
5294 +/* 802.11h Measurement Request/Report IEs */
5295 +/* Measurement Type field */
5296 +#define DOT11_MEASURE_TYPE_BASIC 0
5297 +#define DOT11_MEASURE_TYPE_CCA 1
5298 +#define DOT11_MEASURE_TYPE_RPI 2
5299 +
5300 +/* Measurement Mode field */
5301 +
5302 +/* Measurement Request Modes */
5303 +#define DOT11_MEASURE_MODE_ENABLE (1<<1)
5304 +#define DOT11_MEASURE_MODE_REQUEST (1<<2)
5305 +#define DOT11_MEASURE_MODE_REPORT (1<<3)
5306 +/* Measurement Report Modes */
5307 +#define DOT11_MEASURE_MODE_LATE (1<<0)
5308 +#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
5309 +#define DOT11_MEASURE_MODE_REFUSED (1<<2)
5310 +/* Basic Measurement Map bits */
5311 +#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
5312 +#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
5313 +#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
5314 +#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
5315 +#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
5316 +
5317 +typedef struct {
5318 + uint8 id;
5319 + uint8 len;
5320 + uint8 token;
5321 + uint8 mode;
5322 + uint8 type;
5323 + uint8 channel;
5324 + uint8 start_time[8];
5325 + uint16 duration;
5326 +} dot11_meas_req_t;
5327 +#define DOT11_MNG_IE_MREQ_LEN 14
5328 +/* length of Measure Request IE data not including variable len */
5329 +#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
5330 +
5331 +struct dot11_meas_rep {
5332 + uint8 id;
5333 + uint8 len;
5334 + uint8 token;
5335 + uint8 mode;
5336 + uint8 type;
5337 + union
5338 + {
5339 + struct {
5340 + uint8 channel;
5341 + uint8 start_time[8];
5342 + uint16 duration;
5343 + uint8 map;
5344 + } PACKED basic;
5345 + uint8 data[1];
5346 + } PACKED rep;
5347 +} PACKED;
5348 +typedef struct dot11_meas_rep dot11_meas_rep_t;
5349 +
5350 +/* length of Measure Report IE data not including variable len */
5351 +#define DOT11_MNG_IE_MREP_FIXED_LEN 3
5352 +
5353 +struct dot11_meas_rep_basic {
5354 + uint8 channel;
5355 + uint8 start_time[8];
5356 + uint16 duration;
5357 + uint8 map;
5358 +} PACKED;
5359 +typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
5360 +#define DOT11_MEASURE_BASIC_REP_LEN 12
5361 +
5362 +struct dot11_quiet {
5363 + uint8 id;
5364 + uint8 len;
5365 + uint8 count; /* TBTTs until beacon interval in quiet starts */
5366 + uint8 period; /* Beacon intervals between periodic quiet periods ? */
5367 + uint16 duration;/* Length of quiet period, in TU's */
5368 + uint16 offset; /* TU's offset from TBTT in Count field */
5369 +} PACKED;
5370 +typedef struct dot11_quiet dot11_quiet_t;
5371 +
5372 +typedef struct {
5373 + uint8 channel;
5374 + uint8 map;
5375 +} chan_map_tuple_t;
5376 +
5377 +typedef struct {
5378 + uint8 id;
5379 + uint8 len;
5380 + uint8 eaddr[ETHER_ADDR_LEN];
5381 + uint8 interval;
5382 + chan_map_tuple_t map[1];
5383 +} dot11_ibss_dfs_t;
5384 +
5385 +/* WME Elements */
5386 +#define WME_OUI "\x00\x50\xf2"
5387 +#define WME_VER 1
5388 +#define WME_TYPE 2
5389 +#define WME_SUBTYPE_IE 0 /* Information Element */
5390 +#define WME_SUBTYPE_PARAM_IE 1 /* Parameter Element */
5391 +#define WME_SUBTYPE_TSPEC 2 /* Traffic Specification */
5392 +
5393 +/* WME Access Category Indices (ACIs) */
5394 +#define AC_BE 0 /* Best Effort */
5395 +#define AC_BK 1 /* Background */
5396 +#define AC_VI 2 /* Video */
5397 +#define AC_VO 3 /* Voice */
5398 +#define AC_MAX 4
5399 +
5400 +/* WME Information Element (IE) */
5401 +struct wme_ie {
5402 + uint8 oui[3];
5403 + uint8 type;
5404 + uint8 subtype;
5405 + uint8 version;
5406 + uint8 acinfo;
5407 +} PACKED;
5408 +typedef struct wme_ie wme_ie_t;
5409 +#define WME_IE_LEN 7
5410 +
5411 +struct wme_acparam {
5412 + uint8 ACI;
5413 + uint8 ECW;
5414 + uint16 TXOP; /* stored in network order (ls octet first) */
5415 +} PACKED;
5416 +typedef struct wme_acparam wme_acparam_t;
5417 +
5418 +/* WME Parameter Element (PE) */
5419 +struct wme_params {
5420 + uint8 oui[3];
5421 + uint8 type;
5422 + uint8 subtype;
5423 + uint8 version;
5424 + uint8 acinfo;
5425 + uint8 rsvd;
5426 + wme_acparam_t acparam[4];
5427 +} PACKED;
5428 +typedef struct wme_params wme_params_t;
5429 +#define WME_PARAMS_IE_LEN 24
5430 +
5431 +/* acinfo */
5432 +#define WME_COUNT_MASK 0x0f
5433 +/* ACI */
5434 +#define WME_AIFS_MASK 0x0f
5435 +#define WME_ACM_MASK 0x10
5436 +#define WME_ACI_MASK 0x60
5437 +#define WME_ACI_SHIFT 5
5438 +/* ECW */
5439 +#define WME_CWMIN_MASK 0x0f
5440 +#define WME_CWMAX_MASK 0xf0
5441 +#define WME_CWMAX_SHIFT 4
5442 +
5443 +#define WME_TXOP_UNITS 32
5444 +
5445 +/* AP: default params to be announced in the Beacon Frames/Probe Responses Table 12 WME Draft*/
5446 +/* AP: default params to be Used in the AP Side Table 14 WME Draft January 2004 802.11-03-504r5 */
5447 +#define WME_AC_BK_ACI_STA 0x27
5448 +#define WME_AC_BK_ECW_STA 0xA4
5449 +#define WME_AC_BK_TXOP_STA 0x0000
5450 +#define WME_AC_BE_ACI_STA 0x03
5451 +#define WME_AC_BE_ECW_STA 0xA4
5452 +#define WME_AC_BE_TXOP_STA 0x0000
5453 +#define WME_AC_VI_ACI_STA 0x42
5454 +#define WME_AC_VI_ECW_STA 0x43
5455 +#define WME_AC_VI_TXOP_STA 0x005e
5456 +#define WME_AC_VO_ACI_STA 0x62
5457 +#define WME_AC_VO_ECW_STA 0x32
5458 +#define WME_AC_VO_TXOP_STA 0x002f
5459 +
5460 +#define WME_AC_BK_ACI_AP 0x27
5461 +#define WME_AC_BK_ECW_AP 0xA4
5462 +#define WME_AC_BK_TXOP_AP 0x0000
5463 +#define WME_AC_BE_ACI_AP 0x03
5464 +#define WME_AC_BE_ECW_AP 0x64
5465 +#define WME_AC_BE_TXOP_AP 0x0000
5466 +#define WME_AC_VI_ACI_AP 0x41
5467 +#define WME_AC_VI_ECW_AP 0x43
5468 +#define WME_AC_VI_TXOP_AP 0x005e
5469 +#define WME_AC_VO_ACI_AP 0x61
5470 +#define WME_AC_VO_ECW_AP 0x32
5471 +#define WME_AC_VO_TXOP_AP 0x002f
5472 +
5473 +/* WME Traffic Specification (TSPEC) element */
5474 +#define WME_SUBTYPE_TSPEC 2
5475 +#define WME_TSPEC_HDR_LEN 2
5476 +#define WME_TSPEC_BODY_OFF 2
5477 +struct wme_tspec {
5478 + uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
5479 + uint8 type; /* WME_TYPE */
5480 + uint8 subtype; /* WME_SUBTYPE_TSPEC */
5481 + uint8 version; /* WME_VERSION */
5482 + uint16 ts_info; /* TS Info */
5483 + uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
5484 + uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
5485 + uint32 min_service_interval; /* Minimum Service Interval (us) */
5486 + uint32 max_service_interval; /* Maximum Service Interval (us) */
5487 + uint32 inactivity_interval; /* Inactivity Interval (us) */
5488 + uint32 service_start; /* Service Start Time (us) */
5489 + uint32 min_rate; /* Minimum Data Rate (bps) */
5490 + uint32 mean_rate; /* Mean Data Rate (bps) */
5491 + uint32 max_burst_size; /* Maximum Burst Size (bytes) */
5492 + uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
5493 + uint32 peak_rate; /* Peak Data Rate (bps) */
5494 + uint32 delay_bound; /* Delay Bound (us) */
5495 + uint16 surplus_bandwidth; /* Surplus Bandwidth Allowance Factor */
5496 + uint16 medium_time; /* Medium Time (32 us/s periods) */
5497 +} PACKED;
5498 +typedef struct wme_tspec wme_tspec_t;
5499 +#define WME_TSPEC_LEN 56 /* not including 2-byte header */
5500 +
5501 +/* ts_info */
5502 +/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
5503 +#define TS_INFO_PRIO_SHIFT_HI 11
5504 +#define TS_INFO_PRIO_MASK_HI (0x7 << TS_INFO_PRIO_SHIFT_HI)
5505 +#define TS_INFO_PRIO_SHIFT_LO 1
5506 +#define TS_INFO_PRIO_MASK_LO (0x7 << TS_INFO_PRIO_SHIFT_LO)
5507 +#define TS_INFO_CONTENTION_SHIFT 7
5508 +#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT)
5509 +#define TS_INFO_DIRECTION_SHIFT 5
5510 +#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT)
5511 +#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT)
5512 +#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT)
5513 +#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT)
5514 +
5515 +/* nom_msdu_size */
5516 +#define FIXED_MSDU_SIZE 0x8000 /* MSDU size is fixed */
5517 +#define MSDU_SIZE_MASK 0x7fff /* (Nominal or fixed) MSDU size */
5518 +
5519 +/* surplus_bandwidth */
5520 +/* Represented as 3 bits of integer, binary point, 13 bits fraction */
5521 +#define INTEGER_SHIFT 13
5522 +#define FRACTION_MASK 0x1FFF
5523 +
5524 +/* Management Notification Frame */
5525 +struct dot11_management_notification {
5526 + uint8 category; /* DOT11_ACTION_NOTIFICATION */
5527 + uint8 action;
5528 + uint8 token;
5529 + uint8 status;
5530 + uint8 data[1]; /* Elements */
5531 +} PACKED;
5532 +#define DOT11_MGMT_NOTIFICATION_LEN 4 /* Fixed length */
5533 +
5534 +/* WME Action Codes */
5535 +#define WME_SETUP_REQUEST 0
5536 +#define WME_SETUP_RESPONSE 1
5537 +#define WME_TEARDOWN 2
5538 +
5539 +/* WME Setup Response Status Codes */
5540 +#define WME_ADMISSION_ACCEPTED 0
5541 +#define WME_INVALID_PARAMETERS 1
5542 +#define WME_ADMISSION_REFUSED 3
5543 +
5544 +/* Macro to take a pointer to a beacon or probe response
5545 + * header and return the char* pointer to the SSID info element
5546 + */
5547 +#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
5548 +
5549 +/* Authentication frame payload constants */
5550 +#define DOT11_OPEN_SYSTEM 0
5551 +#define DOT11_SHARED_KEY 1
5552 +#define DOT11_CHALLENGE_LEN 128
5553 +
5554 +/* Frame control macros */
5555 +#define FC_PVER_MASK 0x3
5556 +#define FC_PVER_SHIFT 0
5557 +#define FC_TYPE_MASK 0xC
5558 +#define FC_TYPE_SHIFT 2
5559 +#define FC_SUBTYPE_MASK 0xF0
5560 +#define FC_SUBTYPE_SHIFT 4
5561 +#define FC_TODS 0x100
5562 +#define FC_TODS_SHIFT 8
5563 +#define FC_FROMDS 0x200
5564 +#define FC_FROMDS_SHIFT 9
5565 +#define FC_MOREFRAG 0x400
5566 +#define FC_MOREFRAG_SHIFT 10
5567 +#define FC_RETRY 0x800
5568 +#define FC_RETRY_SHIFT 11
5569 +#define FC_PM 0x1000
5570 +#define FC_PM_SHIFT 12
5571 +#define FC_MOREDATA 0x2000
5572 +#define FC_MOREDATA_SHIFT 13
5573 +#define FC_WEP 0x4000
5574 +#define FC_WEP_SHIFT 14
5575 +#define FC_ORDER 0x8000
5576 +#define FC_ORDER_SHIFT 15
5577 +
5578 +/* sequence control macros */
5579 +#define SEQNUM_SHIFT 4
5580 +#define FRAGNUM_MASK 0xF
5581 +
5582 +/* Frame Control type/subtype defs */
5583 +
5584 +/* FC Types */
5585 +#define FC_TYPE_MNG 0
5586 +#define FC_TYPE_CTL 1
5587 +#define FC_TYPE_DATA 2
5588 +
5589 +/* Management Subtypes */
5590 +#define FC_SUBTYPE_ASSOC_REQ 0
5591 +#define FC_SUBTYPE_ASSOC_RESP 1
5592 +#define FC_SUBTYPE_REASSOC_REQ 2
5593 +#define FC_SUBTYPE_REASSOC_RESP 3
5594 +#define FC_SUBTYPE_PROBE_REQ 4
5595 +#define FC_SUBTYPE_PROBE_RESP 5
5596 +#define FC_SUBTYPE_BEACON 8
5597 +#define FC_SUBTYPE_ATIM 9
5598 +#define FC_SUBTYPE_DISASSOC 10
5599 +#define FC_SUBTYPE_AUTH 11
5600 +#define FC_SUBTYPE_DEAUTH 12
5601 +#define FC_SUBTYPE_ACTION 13
5602 +
5603 +/* Control Subtypes */
5604 +#define FC_SUBTYPE_PS_POLL 10
5605 +#define FC_SUBTYPE_RTS 11
5606 +#define FC_SUBTYPE_CTS 12
5607 +#define FC_SUBTYPE_ACK 13
5608 +#define FC_SUBTYPE_CF_END 14
5609 +#define FC_SUBTYPE_CF_END_ACK 15
5610 +
5611 +/* Data Subtypes */
5612 +#define FC_SUBTYPE_DATA 0
5613 +#define FC_SUBTYPE_DATA_CF_ACK 1
5614 +#define FC_SUBTYPE_DATA_CF_POLL 2
5615 +#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
5616 +#define FC_SUBTYPE_NULL 4
5617 +#define FC_SUBTYPE_CF_ACK 5
5618 +#define FC_SUBTYPE_CF_POLL 6
5619 +#define FC_SUBTYPE_CF_ACK_POLL 7
5620 +#define FC_SUBTYPE_QOS_DATA 8
5621 +#define FC_SUBTYPE_QOS_NULL 12
5622 +
5623 +/* type-subtype combos */
5624 +#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
5625 +
5626 +#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
5627 +
5628 +#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
5629 +#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
5630 +#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
5631 +#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
5632 +#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
5633 +#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
5634 +#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
5635 +#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
5636 +#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
5637 +#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
5638 +#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
5639 +
5640 +#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
5641 +#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
5642 +#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
5643 +#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
5644 +#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
5645 +#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
5646 +
5647 +#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
5648 +#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
5649 +#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
5650 +#define FC_QOS_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_DATA)
5651 +#define FC_QOS_NULL FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_NULL)
5652 +
5653 +/* QoS Control Field */
5654 +
5655 +/* 802.1D Tag */
5656 +#define QOS_PRIO_SHIFT 0
5657 +#define QOS_PRIO_MASK 0x0007
5658 +#define QOS_PRIO(qos) (((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT)
5659 +
5660 +#define QOS_TID_SHIFT 0
5661 +#define QOS_TID_MASK 0x000f
5662 +#define QOS_TID(qos) (((qos) & QOS_TID_MASK) >> QOS_TID_SHIFT)
5663 +
5664 +/* Ack Policy (0 means Acknowledge) */
5665 +#define QOS_ACK_SHIFT 5
5666 +#define QOS_ACK_MASK 0x0060
5667 +#define QOS_ACK(qos) (((qos) & QOS_ACK_MASK) >> QOS_ACK_SHIFT)
5668 +
5669 +/* Management Frames */
5670 +
5671 +/* Management Frame Constants */
5672 +
5673 +/* Fixed fields */
5674 +#define DOT11_MNG_AUTH_ALGO_LEN 2
5675 +#define DOT11_MNG_AUTH_SEQ_LEN 2
5676 +#define DOT11_MNG_BEACON_INT_LEN 2
5677 +#define DOT11_MNG_CAP_LEN 2
5678 +#define DOT11_MNG_AP_ADDR_LEN 6
5679 +#define DOT11_MNG_LISTEN_INT_LEN 2
5680 +#define DOT11_MNG_REASON_LEN 2
5681 +#define DOT11_MNG_AID_LEN 2
5682 +#define DOT11_MNG_STATUS_LEN 2
5683 +#define DOT11_MNG_TIMESTAMP_LEN 8
5684 +
5685 +/* DUR/ID field in assoc resp is 0xc000 | AID */
5686 +#define DOT11_AID_MASK 0x3fff
5687 +
5688 +/* Reason Codes */
5689 +#define DOT11_RC_RESERVED 0
5690 +#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
5691 +#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
5692 +#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
5693 + leaving (or has left) IBSS or ESS */
5694 +#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
5695 +#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
5696 + all currently associated stations */
5697 +#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
5698 + nonauthenticated station */
5699 +#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
5700 + nonassociated station */
5701 +#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
5702 + leaving (or has left) BSS */
5703 +#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
5704 + not authenticated with responding station */
5705 +#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
5706 +
5707 +/* Status Codes */
5708 +#define DOT11_STATUS_SUCCESS 0 /* Successful */
5709 +#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
5710 +#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
5711 + in the Capability Information field */
5712 +#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
5713 + confirm that association exists */
5714 +#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
5715 + the scope of this standard */
5716 +#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
5717 + specified authentication algorithm */
5718 +#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
5719 + authentication transaction sequence number
5720 + out of expected sequence */
5721 +#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
5722 +#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
5723 + for next frame in sequence */
5724 +#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
5725 + handle additional associated stations */
5726 +#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
5727 + not supporting all of the data rates in the
5728 + BSSBasicRateSet parameter */
5729 +#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
5730 + not supporting the Short Preamble option */
5731 +#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
5732 + not supporting the PBCC Modulation option */
5733 +#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
5734 + not supporting the Channel Agility option */
5735 +#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
5736 + capability is required. */
5737 +#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
5738 + Power Cap element is unacceptable. */
5739 +#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
5740 + Supported Channel element is unacceptable */
5741 +#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
5742 + not supporting the Short Slot Time option */
5743 +#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
5744 + not supporting the ER-PBCC Modulation option */
5745 +#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
5746 + not supporting the DSS-OFDM option */
5747 +
5748 +/* Info Elts, length of INFORMATION portion of Info Elts */
5749 +#define DOT11_MNG_DS_PARAM_LEN 1
5750 +#define DOT11_MNG_IBSS_PARAM_LEN 2
5751 +
5752 +/* TIM Info element has 3 bytes fixed info in INFORMATION field,
5753 + * followed by 1 to 251 bytes of Partial Virtual Bitmap */
5754 +#define DOT11_MNG_TIM_FIXED_LEN 3
5755 +#define DOT11_MNG_TIM_DTIM_COUNT 0
5756 +#define DOT11_MNG_TIM_DTIM_PERIOD 1
5757 +#define DOT11_MNG_TIM_BITMAP_CTL 2
5758 +#define DOT11_MNG_TIM_PVB 3
5759 +
5760 +/* TLV defines */
5761 +#define TLV_TAG_OFF 0
5762 +#define TLV_LEN_OFF 1
5763 +#define TLV_HDR_LEN 2
5764 +#define TLV_BODY_OFF 2
5765 +
5766 +/* Management Frame Information Element IDs */
5767 +#define DOT11_MNG_SSID_ID 0
5768 +#define DOT11_MNG_RATES_ID 1
5769 +#define DOT11_MNG_FH_PARMS_ID 2
5770 +#define DOT11_MNG_DS_PARMS_ID 3
5771 +#define DOT11_MNG_CF_PARMS_ID 4
5772 +#define DOT11_MNG_TIM_ID 5
5773 +#define DOT11_MNG_IBSS_PARMS_ID 6
5774 +#define DOT11_MNG_COUNTRY_ID 7
5775 +#define DOT11_MNG_HOPPING_PARMS_ID 8
5776 +#define DOT11_MNG_HOPPING_TABLE_ID 9
5777 +#define DOT11_MNG_REQUEST_ID 10
5778 +#define DOT11_MNG_CHALLENGE_ID 16
5779 +#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
5780 +#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
5781 +#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
5782 +#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
5783 +#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
5784 +#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
5785 +#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
5786 +#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
5787 +#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
5788 +#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
5789 +#define DOT11_MNG_ERP_ID 42
5790 +#define DOT11_MNG_NONERP_ID 47
5791 +#ifdef BCMWPA2
5792 +#define DOT11_MNG_RSN_ID 48
5793 +#endif /* BCMWPA2 */
5794 +#define DOT11_MNG_EXT_RATES_ID 50
5795 +#define DOT11_MNG_WPA_ID 221
5796 +#define DOT11_MNG_PROPR_ID 221
5797 +
5798 +/* ERP info element bit values */
5799 +#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
5800 +#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
5801 +#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
5802 +#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
5803 +
5804 +/* Capability Information Field */
5805 +#define DOT11_CAP_ESS 0x0001
5806 +#define DOT11_CAP_IBSS 0x0002
5807 +#define DOT11_CAP_POLLABLE 0x0004
5808 +#define DOT11_CAP_POLL_RQ 0x0008
5809 +#define DOT11_CAP_PRIVACY 0x0010
5810 +#define DOT11_CAP_SHORT 0x0020
5811 +#define DOT11_CAP_PBCC 0x0040
5812 +#define DOT11_CAP_AGILITY 0x0080
5813 +#define DOT11_CAP_SPECTRUM 0x0100
5814 +#define DOT11_CAP_SHORTSLOT 0x0400
5815 +#define DOT11_CAP_CCK_OFDM 0x2000
5816 +
5817 +/* Action Frame Constants */
5818 +#define DOT11_ACTION_CAT_ERR_MASK 0x80
5819 +#define DOT11_ACTION_CAT_SPECT_MNG 0x00
5820 +#define DOT11_ACTION_NOTIFICATION 0x11 /* 17 */
5821 +
5822 +#define DOT11_ACTION_ID_M_REQ 0
5823 +#define DOT11_ACTION_ID_M_REP 1
5824 +#define DOT11_ACTION_ID_TPC_REQ 2
5825 +#define DOT11_ACTION_ID_TPC_REP 3
5826 +#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
5827 +
5828 +/* MLME Enumerations */
5829 +#define DOT11_BSSTYPE_INFRASTRUCTURE 0
5830 +#define DOT11_BSSTYPE_INDEPENDENT 1
5831 +#define DOT11_BSSTYPE_ANY 2
5832 +#define DOT11_SCANTYPE_ACTIVE 0
5833 +#define DOT11_SCANTYPE_PASSIVE 1
5834 +
5835 +/* 802.11 A PHY constants */
5836 +#define APHY_SLOT_TIME 9
5837 +#define APHY_SIFS_TIME 16
5838 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
5839 +#define APHY_PREAMBLE_TIME 16
5840 +#define APHY_SIGNAL_TIME 4
5841 +#define APHY_SYMBOL_TIME 4
5842 +#define APHY_SERVICE_NBITS 16
5843 +#define APHY_TAIL_NBITS 6
5844 +#define APHY_CWMIN 15
5845 +
5846 +/* 802.11 B PHY constants */
5847 +#define BPHY_SLOT_TIME 20
5848 +#define BPHY_SIFS_TIME 10
5849 +#define BPHY_DIFS_TIME 50
5850 +#define BPHY_PLCP_TIME 192
5851 +#define BPHY_PLCP_SHORT_TIME 96
5852 +#define BPHY_CWMIN 31
5853 +
5854 +/* 802.11 G constants */
5855 +#define DOT11_OFDM_SIGNAL_EXTENSION 6
5856 +
5857 +#define PHY_CWMAX 1023
5858 +
5859 +#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
5860 +
5861 +/* dot11Counters Table - 802.11 spec., Annex D */
5862 +typedef struct d11cnt {
5863 + uint32 txfrag; /* dot11TransmittedFragmentCount */
5864 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
5865 + uint32 txfail; /* dot11FailedCount */
5866 + uint32 txretry; /* dot11RetryCount */
5867 + uint32 txretrie; /* dot11MultipleRetryCount */
5868 + uint32 rxdup; /* dot11FrameduplicateCount */
5869 + uint32 txrts; /* dot11RTSSuccessCount */
5870 + uint32 txnocts; /* dot11RTSFailureCount */
5871 + uint32 txnoack; /* dot11ACKFailureCount */
5872 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
5873 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
5874 + uint32 rxcrc; /* dot11FCSErrorCount */
5875 + uint32 txfrmsnt; /* dot11TransmittedFrameCount */
5876 + uint32 rxundec; /* dot11WEPUndecryptableCount */
5877 +} d11cnt_t;
5878 +
5879 +/* BRCM OUI */
5880 +#define BRCM_OUI "\x00\x10\x18"
5881 +
5882 +/* BRCM info element */
5883 +struct brcm_ie {
5884 + uchar id; /* 221, DOT11_MNG_PROPR_ID */
5885 + uchar len;
5886 + uchar oui[3];
5887 + uchar ver;
5888 + uchar assoc; /* # of assoc STAs */
5889 + uchar flags; /* misc flags */
5890 +} PACKED;
5891 +#define BRCM_IE_LEN 8
5892 +typedef struct brcm_ie brcm_ie_t;
5893 +#define BRCM_IE_VER 2
5894 +#define BRCM_IE_LEGACY_AES_VER 1
5895 +
5896 +/* brcm_ie flags */
5897 +#define BRF_ABCAP 0x1 /* afterburner capable */
5898 +#define BRF_ABRQRD 0x2 /* afterburner requested */
5899 +#define BRF_LZWDS 0x4 /* lazy wds enabled */
5900 +#define BRF_ABCOUNTER_MASK 0xf0 /* afterburner wds "state" counter */
5901 +#define BRF_ABCOUNTER_SHIFT 4
5902 +
5903 +#define AB_WDS_TIMEOUT_MAX 15 /* afterburner wds Max count indicating not locally capable */
5904 +#define AB_WDS_TIMEOUT_MIN 1 /* afterburner wds, use zero count as indicating "downrev" */
5905 +
5906 +
5907 +/* OUI for BRCM proprietary IE */
5908 +#define BRCM_PROP_OUI "\x00\x90\x4C"
5909 +
5910 +/* Vendor IE structure */
5911 +struct vndr_ie {
5912 + uchar id;
5913 + uchar len;
5914 + uchar oui [3];
5915 + uchar data [1]; /* Variable size data */
5916 +}PACKED;
5917 +typedef struct vndr_ie vndr_ie_t;
5918 +
5919 +#define VNDR_IE_HDR_LEN 2 /* id + len field */
5920 +#define VNDR_IE_MIN_LEN 3 /* size of the oui field */
5921 +#define VNDR_IE_MAX_LEN 256
5922 +
5923 +/* WPA definitions */
5924 +#define WPA_VERSION 1
5925 +#define WPA_OUI "\x00\x50\xF2"
5926 +
5927 +#ifdef BCMWPA2
5928 +#define WPA2_VERSION 1
5929 +#define WPA2_VERSION_LEN 2
5930 +#define WPA2_OUI "\x00\x0F\xAC"
5931 +#endif /* BCMWPA2 */
5932 +
5933 +#define WPA_OUI_LEN 3
5934 +
5935 +/* RSN authenticated key managment suite */
5936 +#define RSN_AKM_NONE 0 /* None (IBSS) */
5937 +#define RSN_AKM_UNSPECIFIED 1 /* Over 802.1x */
5938 +#define RSN_AKM_PSK 2 /* Pre-shared Key */
5939 +
5940 +
5941 +/* Key related defines */
5942 +#define DOT11_MAX_DEFAULT_KEYS 4 /* number of default keys */
5943 +#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
5944 +#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
5945 +#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
5946 +
5947 +#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
5948 +#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
5949 +#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
5950 +#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
5951 +#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
5952 +#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
5953 +#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
5954 +#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
5955 +#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
5956 +#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
5957 +#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
5958 +#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
5959 +#define AES_KEY_SIZE 16 /* size of AES key */
5960 +
5961 +#undef PACKED
5962 +#if !defined(__GNUC__)
5963 +#pragma pack()
5964 +#endif
5965 +
5966 +#endif /* _802_11_H_ */
5967 diff -urN linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h
5968 --- linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h 1970-01-01 01:00:00.000000000 +0100
5969 +++ linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h 2005-11-07 22:51:38.784726500 +0100
5970 @@ -0,0 +1,103 @@
5971 +/*
5972 + * Broadcom Ethernettype protocol definitions
5973 + *
5974 + * Copyright 2005, Broadcom Corporation
5975 + * All Rights Reserved.
5976 + *
5977 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5978 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5979 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5980 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5981 + *
5982 + */
5983 +
5984 +/*
5985 + * Broadcom Ethernet protocol defines
5986 + *
5987 + */
5988 +
5989 +#ifndef _BCMETH_H_
5990 +#define _BCMETH_H_
5991 +
5992 +/* enable structure packing */
5993 +#if defined(__GNUC__)
5994 +#define PACKED __attribute__((packed))
5995 +#else
5996 +#pragma pack(1)
5997 +#define PACKED
5998 +#endif
5999 +
6000 +/* ETHER_TYPE_BRCM is defined in ethernet.h */
6001 +
6002 +/*
6003 + * Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
6004 + * in one of two formats: (only subtypes 32768-65535 are in use now)
6005 + *
6006 + * subtypes 0-32767:
6007 + * 8 bit subtype (0-127)
6008 + * 8 bit length in bytes (0-255)
6009 + *
6010 + * subtypes 32768-65535:
6011 + * 16 bit big-endian subtype
6012 + * 16 bit big-endian length in bytes (0-65535)
6013 + *
6014 + * length is the number of additional bytes beyond the 4 or 6 byte header
6015 + *
6016 + * Reserved values:
6017 + * 0 reserved
6018 + * 5-15 reserved for iLine protocol assignments
6019 + * 17-126 reserved, assignable
6020 + * 127 reserved
6021 + * 32768 reserved
6022 + * 32769-65534 reserved, assignable
6023 + * 65535 reserved
6024 + */
6025 +
6026 +/*
6027 + * While adding the subtypes and their specific processing code make sure
6028 + * bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
6029 + */
6030 +
6031 +#define BCMILCP_SUBTYPE_RATE 1
6032 +#define BCMILCP_SUBTYPE_LINK 2
6033 +#define BCMILCP_SUBTYPE_CSA 3
6034 +#define BCMILCP_SUBTYPE_LARQ 4
6035 +#define BCMILCP_SUBTYPE_VENDOR 5
6036 +#define BCMILCP_SUBTYPE_FLH 17
6037 +
6038 +#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
6039 +#define BCMILCP_SUBTYPE_CERT 32770
6040 +#define BCMILCP_SUBTYPE_SES 32771
6041 +
6042 +
6043 +#define BCMILCP_BCM_SUBTYPE_RESERVED 0
6044 +#define BCMILCP_BCM_SUBTYPE_EVENT 1
6045 +#define BCMILCP_BCM_SUBTYPE_SES 2
6046 +/*
6047 +The EAPOL type is not used anymore. Instead EAPOL messages are now embedded
6048 +within BCMILCP_BCM_SUBTYPE_EVENT type messages
6049 +*/
6050 +/*#define BCMILCP_BCM_SUBTYPE_EAPOL 3*/
6051 +
6052 +#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
6053 +#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
6054 +
6055 +/* These fields are stored in network order */
6056 +typedef struct bcmeth_hdr
6057 +{
6058 + uint16 subtype; /* Vendor specific..32769*/
6059 + uint16 length;
6060 + uint8 version; /* Version is 0*/
6061 + uint8 oui[3]; /* Broadcom OUI*/
6062 + /* user specific Data */
6063 + uint16 usr_subtype;
6064 +} PACKED bcmeth_hdr_t;
6065 +
6066 +
6067 +
6068 +#undef PACKED
6069 +#if !defined(__GNUC__)
6070 +#pragma pack()
6071 +#endif
6072 +
6073 +#endif
6074 diff -urN linux.old/arch/mips/bcm947xx/include/proto/bcmip.h linux.dev/arch/mips/bcm947xx/include/proto/bcmip.h
6075 --- linux.old/arch/mips/bcm947xx/include/proto/bcmip.h 1970-01-01 01:00:00.000000000 +0100
6076 +++ linux.dev/arch/mips/bcm947xx/include/proto/bcmip.h 2005-11-08 00:15:47.881307500 +0100
6077 @@ -0,0 +1,42 @@
6078 +/*
6079 + * Copyright 2005, Broadcom Corporation
6080 + * All Rights Reserved.
6081 + *
6082 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
6083 + * the contents of this file may not be disclosed to third parties, copied
6084 + * or duplicated in any form, in whole or in part, without the prior
6085 + * written permission of Broadcom Corporation.
6086 + *
6087 + * Fundamental constants relating to IP Protocol
6088 + *
6089 + * $Id$
6090 + */
6091 +
6092 +#ifndef _bcmip_h_
6093 +#define _bcmip_h_
6094 +
6095 +/* IP header */
6096 +#define IPV4_VERIHL_OFFSET 0 /* version and ihl byte offset */
6097 +#define IPV4_TOS_OFFSET 1 /* TOS offset */
6098 +#define IPV4_PROT_OFFSET 9 /* protocol type offset */
6099 +#define IPV4_CHKSUM_OFFSET 10 /* IP header checksum offset */
6100 +#define IPV4_SRC_IP_OFFSET 12 /* src IP addr offset */
6101 +#define IPV4_DEST_IP_OFFSET 16 /* dest IP addr offset */
6102 +
6103 +#define IPV4_VER_MASK 0xf0
6104 +#define IPV4_IHL_MASK 0x0f
6105 +
6106 +#define IPV4_PROT_UDP 17 /* UDP protocol type */
6107 +
6108 +#define IPV4_ADDR_LEN 4 /* IP v4 address length */
6109 +
6110 +#define IPV4_VER_NUM 0x40 /* IP v4 version number */
6111 +
6112 +/* NULL IP address check */
6113 +#define IPV4_ISNULLADDR(a) ((((uint8 *)(a))[0] + ((uint8 *)(a))[1] + \
6114 + ((uint8 *)(a))[2] + ((uint8 *)(a))[3]) == 0)
6115 +
6116 +#define IPV4_ADDR_STR_LEN 16
6117 +
6118 +#endif /* #ifndef _bcmip_h_ */
6119 +
6120 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
6121 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
6122 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-11-07 22:51:38.784726500 +0100
6123 @@ -0,0 +1,169 @@
6124 +/*******************************************************************************
6125 + * $Id$
6126 + * Copyright 2005, Broadcom Corporation
6127 + * All Rights Reserved.
6128 + *
6129 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6130 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6131 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6132 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6133 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
6134 + ******************************************************************************/
6135 +
6136 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
6137 +#define _NET_ETHERNET_H_
6138 +
6139 +#ifndef _TYPEDEFS_H_
6140 +#include "typedefs.h"
6141 +#endif
6142 +
6143 +/* enable structure packing */
6144 +#if defined(__GNUC__)
6145 +#define PACKED __attribute__((packed))
6146 +#else
6147 +#pragma pack(1)
6148 +#define PACKED
6149 +#endif
6150 +
6151 +/*
6152 + * The number of bytes in an ethernet (MAC) address.
6153 + */
6154 +#define ETHER_ADDR_LEN 6
6155 +
6156 +/*
6157 + * The number of bytes in the type field.
6158 + */
6159 +#define ETHER_TYPE_LEN 2
6160 +
6161 +/*
6162 + * The number of bytes in the trailing CRC field.
6163 + */
6164 +#define ETHER_CRC_LEN 4
6165 +
6166 +/*
6167 + * The length of the combined header.
6168 + */
6169 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
6170 +
6171 +/*
6172 + * The minimum packet length.
6173 + */
6174 +#define ETHER_MIN_LEN 64
6175 +
6176 +/*
6177 + * The minimum packet user data length.
6178 + */
6179 +#define ETHER_MIN_DATA 46
6180 +
6181 +/*
6182 + * The maximum packet length.
6183 + */
6184 +#define ETHER_MAX_LEN 1518
6185 +
6186 +/*
6187 + * The maximum packet user data length.
6188 + */
6189 +#define ETHER_MAX_DATA 1500
6190 +
6191 +/* ether types */
6192 +#define ETHER_TYPE_IP 0x0800 /* IP */
6193 +#define ETHER_TYPE_ARP 0x0806 /* ARP */
6194 +#define ETHER_TYPE_8021Q 0x8100 /* 802.1Q */
6195 +#define ETHER_TYPE_BRCM 0x886c /* Broadcom Corp. */
6196 +#define ETHER_TYPE_802_1X 0x888e /* 802.1x */
6197 +#define ETHER_TYPE_802_1X_PREAUTH 0x88c7 /* 802.1x preauthentication*/
6198 +
6199 +/* Broadcom subtype follows ethertype; First 2 bytes are reserved; Next 2 are subtype; */
6200 +#define ETHER_BRCM_SUBTYPE_LEN 4 /* Broadcom 4 byte subtype */
6201 +#define ETHER_BRCM_CRAM 0x1 /* Broadcom subtype cram protocol */
6202 +
6203 +/* ether header */
6204 +#define ETHER_DEST_OFFSET 0 /* dest address offset */
6205 +#define ETHER_SRC_OFFSET 6 /* src address offset */
6206 +#define ETHER_TYPE_OFFSET 12 /* ether type offset */
6207 +
6208 +/*
6209 + * A macro to validate a length with
6210 + */
6211 +#define ETHER_IS_VALID_LEN(foo) \
6212 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
6213 +
6214 +
6215 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
6216 +/*
6217 + * Structure of a 10Mb/s Ethernet header.
6218 + */
6219 +struct ether_header {
6220 + uint8 ether_dhost[ETHER_ADDR_LEN];
6221 + uint8 ether_shost[ETHER_ADDR_LEN];
6222 + uint16 ether_type;
6223 +} PACKED;
6224 +
6225 +/*
6226 + * Structure of a 48-bit Ethernet address.
6227 + */
6228 +struct ether_addr {
6229 + uint8 octet[ETHER_ADDR_LEN];
6230 +} PACKED;
6231 +#endif
6232 +
6233 +/*
6234 + * Takes a pointer, sets locally admininistered
6235 + * address bit in the 48-bit Ethernet address.
6236 + */
6237 +#define ETHER_SET_LOCALADDR(ea) ( ((uint8 *)(ea))[0] = \
6238 + (((uint8 *)(ea))[0] | 2) )
6239 +
6240 +/*
6241 + * Takes a pointer, returns true if a 48-bit multicast address
6242 + * (including broadcast, since it is all ones)
6243 + */
6244 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
6245 +
6246 +
6247 +/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
6248 +#define ether_cmp(a, b) ( \
6249 + !(((short*)a)[0] == ((short*)b)[0]) | \
6250 + !(((short*)a)[1] == ((short*)b)[1]) | \
6251 + !(((short*)a)[2] == ((short*)b)[2]))
6252 +
6253 +/* copy an ethernet address - assumes the pointers can be referenced as shorts */
6254 +#define ether_copy(s, d) { \
6255 + ((short*)d)[0] = ((short*)s)[0]; \
6256 + ((short*)d)[1] = ((short*)s)[1]; \
6257 + ((short*)d)[2] = ((short*)s)[2]; }
6258 +
6259 +/*
6260 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
6261 + */
6262 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
6263 + ((uint8 *)(ea))[1] & \
6264 + ((uint8 *)(ea))[2] & \
6265 + ((uint8 *)(ea))[3] & \
6266 + ((uint8 *)(ea))[4] & \
6267 + ((uint8 *)(ea))[5]) == 0xff)
6268 +
6269 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
6270 +
6271 +/*
6272 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
6273 + */
6274 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
6275 + ((uint8 *)(ea))[1] | \
6276 + ((uint8 *)(ea))[2] | \
6277 + ((uint8 *)(ea))[3] | \
6278 + ((uint8 *)(ea))[4] | \
6279 + ((uint8 *)(ea))[5]) == 0)
6280 +
6281 +/* Differentiated Services Codepoint - upper 6 bits of tos in iphdr */
6282 +#define DSCP_MASK 0xFC /* upper 6 bits */
6283 +#define DSCP_SHIFT 2
6284 +#define DSCP_WME_PRI_MASK 0xE0 /* upper 3 bits */
6285 +#define DSCP_WME_PRI_SHIFT 5
6286 +
6287 +#undef PACKED
6288 +#if !defined(__GNUC__)
6289 +#pragma pack()
6290 +#endif
6291 +
6292 +#endif /* _NET_ETHERNET_H_ */
6293 diff -urN linux.old/arch/mips/bcm947xx/include/proto/vlan.h linux.dev/arch/mips/bcm947xx/include/proto/vlan.h
6294 --- linux.old/arch/mips/bcm947xx/include/proto/vlan.h 1970-01-01 01:00:00.000000000 +0100
6295 +++ linux.dev/arch/mips/bcm947xx/include/proto/vlan.h 2005-11-07 21:57:07.873587500 +0100
6296 @@ -0,0 +1,50 @@
6297 +/*
6298 + * 802.1Q VLAN protocol definitions
6299 + *
6300 + * Copyright 2005, Broadcom Corporation
6301 + * All Rights Reserved.
6302 + *
6303 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6304 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6305 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6306 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6307 + *
6308 + * $Id$
6309 + */
6310 +
6311 +#ifndef _vlan_h_
6312 +#define _vlan_h_
6313 +
6314 +/* enable structure packing */
6315 +#if defined(__GNUC__)
6316 +#define PACKED __attribute__((packed))
6317 +#else
6318 +#pragma pack(1)
6319 +#define PACKED
6320 +#endif
6321 +
6322 +#define VLAN_VID_MASK 0xfff /* low 12 bits are vlan id */
6323 +#define VLAN_CFI_SHIFT 12 /* canonical format indicator bit */
6324 +#define VLAN_PRI_SHIFT 13 /* user priority */
6325 +
6326 +#define VLAN_PRI_MASK 7 /* 3 bits of priority */
6327 +
6328 +#define VLAN_TAG_LEN 4
6329 +#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN)
6330 +
6331 +struct ethervlan_header {
6332 + uint8 ether_dhost[ETHER_ADDR_LEN];
6333 + uint8 ether_shost[ETHER_ADDR_LEN];
6334 + uint16 vlan_type; /* 0x8100 */
6335 + uint16 vlan_tag; /* priority, cfi and vid */
6336 + uint16 ether_type;
6337 +};
6338 +
6339 +#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
6340 +
6341 +#undef PACKED
6342 +#if !defined(__GNUC__)
6343 +#pragma pack()
6344 +#endif
6345 +
6346 +#endif /* _vlan_h_ */
6347 diff -urN linux.old/arch/mips/bcm947xx/include/proto/wpa.h linux.dev/arch/mips/bcm947xx/include/proto/wpa.h
6348 --- linux.old/arch/mips/bcm947xx/include/proto/wpa.h 1970-01-01 01:00:00.000000000 +0100
6349 +++ linux.dev/arch/mips/bcm947xx/include/proto/wpa.h 2005-11-07 21:57:07.873587500 +0100
6350 @@ -0,0 +1,140 @@
6351 +/*
6352 + * Fundamental types and constants relating to WPA
6353 + *
6354 + * Copyright 2005, Broadcom Corporation
6355 + * All Rights Reserved.
6356 + *
6357 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6358 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6359 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6360 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6361 + *
6362 + * $Id$
6363 + */
6364 +
6365 +#ifndef _proto_wpa_h_
6366 +#define _proto_wpa_h_
6367 +
6368 +#include <typedefs.h>
6369 +#include <proto/ethernet.h>
6370 +
6371 +/* enable structure packing */
6372 +#if defined(__GNUC__)
6373 +#define PACKED __attribute__((packed))
6374 +#else
6375 +#pragma pack(1)
6376 +#define PACKED
6377 +#endif
6378 +
6379 +/* Reason Codes */
6380 +
6381 +/* 10 and 11 are from TGh. */
6382 +#define DOT11_RC_BAD_PC 10 /* Unacceptable power capability element */
6383 +#define DOT11_RC_BAD_CHANNELS 11 /* Unacceptable supported channels element */
6384 +/* 12 is unused */
6385 +/* 13 through 23 taken from P802.11i/D3.0, November 2002 */
6386 +#define DOT11_RC_INVALID_WPA_IE 13 /* Invalid info. element */
6387 +#define DOT11_RC_MIC_FAILURE 14 /* Michael failure */
6388 +#define DOT11_RC_4WH_TIMEOUT 15 /* 4-way handshake timeout */
6389 +#define DOT11_RC_GTK_UPDATE_TIMEOUT 16 /* Group key update timeout */
6390 +#define DOT11_RC_WPA_IE_MISMATCH 17 /* WPA IE in 4-way handshake differs from (re-)assoc. request/probe response */
6391 +#define DOT11_RC_INVALID_MC_CIPHER 18 /* Invalid multicast cipher */
6392 +#define DOT11_RC_INVALID_UC_CIPHER 19 /* Invalid unicast cipher */
6393 +#define DOT11_RC_INVALID_AKMP 20 /* Invalid authenticated key management protocol */
6394 +#define DOT11_RC_BAD_WPA_VERSION 21 /* Unsupported WPA version */
6395 +#define DOT11_RC_INVALID_WPA_CAP 22 /* Invalid WPA IE capabilities */
6396 +#define DOT11_RC_8021X_AUTH_FAIL 23 /* 802.1X authentication failure */
6397 +
6398 +#define WPA2_PMKID_LEN 16
6399 +
6400 +/* WPA IE fixed portion */
6401 +typedef struct
6402 +{
6403 + uint8 tag; /* TAG */
6404 + uint8 length; /* TAG length */
6405 + uint8 oui[3]; /* IE OUI */
6406 + uint8 oui_type; /* OUI type */
6407 + struct {
6408 + uint8 low;
6409 + uint8 high;
6410 + } PACKED version; /* IE version */
6411 +} PACKED wpa_ie_fixed_t;
6412 +#define WPA_IE_OUITYPE_LEN 4
6413 +#define WPA_IE_FIXED_LEN 8
6414 +#define WPA_IE_TAG_FIXED_LEN 6
6415 +
6416 +typedef struct {
6417 + uint8 tag; /* TAG */
6418 + uint8 length; /* TAG length */
6419 + struct {
6420 + uint8 low;
6421 + uint8 high;
6422 + } PACKED version; /* IE version */
6423 +} PACKED wpa_rsn_ie_fixed_t;
6424 +#define WPA_RSN_IE_FIXED_LEN 4
6425 +#define WPA_RSN_IE_TAG_FIXED_LEN 2
6426 +typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
6427 +
6428 +/* WPA suite/multicast suite */
6429 +typedef struct
6430 +{
6431 + uint8 oui[3];
6432 + uint8 type;
6433 +} PACKED wpa_suite_t, wpa_suite_mcast_t;
6434 +#define WPA_SUITE_LEN 4
6435 +
6436 +/* WPA unicast suite list/key management suite list */
6437 +typedef struct
6438 +{
6439 + struct {
6440 + uint8 low;
6441 + uint8 high;
6442 + } PACKED count;
6443 + wpa_suite_t list[1];
6444 +} PACKED wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
6445 +#define WPA_IE_SUITE_COUNT_LEN 2
6446 +typedef struct
6447 +{
6448 + struct {
6449 + uint8 low;
6450 + uint8 high;
6451 + } PACKED count;
6452 + wpa_pmkid_t list[1];
6453 +} PACKED wpa_pmkid_list_t;
6454 +
6455 +/* WPA cipher suites */
6456 +#define WPA_CIPHER_NONE 0 /* None */
6457 +#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
6458 +#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
6459 +#define WPA_CIPHER_AES_OCB 3 /* AES (OCB) */
6460 +#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
6461 +#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
6462 +
6463 +#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
6464 + (cipher) == WPA_CIPHER_WEP_40 || \
6465 + (cipher) == WPA_CIPHER_WEP_104 || \
6466 + (cipher) == WPA_CIPHER_TKIP || \
6467 + (cipher) == WPA_CIPHER_AES_OCB || \
6468 + (cipher) == WPA_CIPHER_AES_CCM)
6469 +
6470 +/* WPA TKIP countermeasures parameters */
6471 +#define WPA_TKIP_CM_DETECT 60 /* multiple MIC failure window (seconds) */
6472 +#define WPA_TKIP_CM_BLOCK 60 /* countermeasures active window (seconds) */
6473 +
6474 +/* WPA capabilities defined in 802.11i */
6475 +#define WPA_CAP_4_REPLAY_CNTRS 2
6476 +#define WPA_CAP_16_REPLAY_CNTRS 3
6477 +#define WPA_CAP_REPLAY_CNTR_SHIFT 2
6478 +#define WPA_CAP_REPLAY_CNTR_MASK 0x000c
6479 +
6480 +/* WPA Specific defines */
6481 +#define WPA_CAP_LEN 2
6482 +
6483 +#define WPA_CAP_WPA2_PREAUTH 1
6484 +
6485 +#undef PACKED
6486 +#if !defined(__GNUC__)
6487 +#pragma pack()
6488 +#endif
6489 +
6490 +#endif /* _proto_wpa_h_ */
6491 diff -urN linux.old/arch/mips/bcm947xx/include/rts/crc.h linux.dev/arch/mips/bcm947xx/include/rts/crc.h
6492 --- linux.old/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
6493 +++ linux.dev/arch/mips/bcm947xx/include/rts/crc.h 2005-11-07 21:57:07.873587500 +0100
6494 @@ -0,0 +1,69 @@
6495 +/*******************************************************************************
6496 + * $Id$
6497 + * Copyright 2005, Broadcom Corporation
6498 + * All Rights Reserved.
6499 + *
6500 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6501 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6502 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6503 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6504 + * crc.h - a function to compute crc for iLine10 headers
6505 + ******************************************************************************/
6506 +
6507 +#ifndef _RTS_CRC_H_
6508 +#define _RTS_CRC_H_ 1
6509 +
6510 +#include "typedefs.h"
6511 +
6512 +#ifdef __cplusplus
6513 +extern "C" {
6514 +#endif
6515 +
6516 +
6517 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6518 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6519 +#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
6520 +
6521 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6522 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6523 +
6524 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6525 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6526 +
6527 +void hcs(uint8 *, uint);
6528 +uint8 crc8(uint8 *, uint, uint8);
6529 +uint16 crc16(uint8 *, uint, uint16);
6530 +uint32 crc32(uint8 *, uint, uint32);
6531 +
6532 +/* macros for common usage */
6533 +
6534 +#define APPEND_CRC8(pbytes, nbytes) \
6535 +do { \
6536 + uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
6537 + (pbytes)[(nbytes)] = tmp; \
6538 + (nbytes) += 1; \
6539 +} while (0)
6540 +
6541 +#define APPEND_CRC16(pbytes, nbytes) \
6542 +do { \
6543 + uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
6544 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6545 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6546 + (nbytes) += 2; \
6547 +} while (0)
6548 +
6549 +#define APPEND_CRC32(pbytes, nbytes) \
6550 +do { \
6551 + uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
6552 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6553 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6554 + (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
6555 + (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
6556 + (nbytes) += 4; \
6557 +} while (0)
6558 +
6559 +#ifdef __cplusplus
6560 +}
6561 +#endif
6562 +
6563 +#endif /* _RTS_CRC_H_ */
6564 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
6565 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6566 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-11-07 22:51:38.784726500 +0100
6567 @@ -0,0 +1,440 @@
6568 +/*
6569 + * SiliconBackplane Chipcommon core hardware definitions.
6570 + *
6571 + * The chipcommon core provides chip identification, SB control,
6572 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6573 + * gpio interface, extbus, and support for serial and parallel flashes.
6574 + *
6575 + * $Id$
6576 + * Copyright 2005, Broadcom Corporation
6577 + * All Rights Reserved.
6578 + *
6579 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6580 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6581 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6582 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6583 + *
6584 + */
6585 +
6586 +#ifndef _SBCHIPC_H
6587 +#define _SBCHIPC_H
6588 +
6589 +
6590 +#ifndef _LANGUAGE_ASSEMBLY
6591 +
6592 +/* cpp contortions to concatenate w/arg prescan */
6593 +#ifndef PAD
6594 +#define _PADLINE(line) pad ## line
6595 +#define _XSTR(line) _PADLINE(line)
6596 +#define PAD _XSTR(__LINE__)
6597 +#endif /* PAD */
6598 +
6599 +typedef volatile struct {
6600 + uint32 chipid; /* 0x0 */
6601 + uint32 capabilities;
6602 + uint32 corecontrol; /* corerev >= 1 */
6603 + uint32 bist;
6604 +
6605 + /* OTP */
6606 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6607 + uint32 otpcontrol;
6608 + uint32 otpprog;
6609 + uint32 PAD;
6610 +
6611 + /* Interrupt control */
6612 + uint32 intstatus; /* 0x20 */
6613 + uint32 intmask;
6614 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6615 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6616 +
6617 + /* Jtag Master */
6618 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6619 + uint32 jtagir;
6620 + uint32 jtagdr;
6621 + uint32 jtagctrl;
6622 +
6623 + /* serial flash interface registers */
6624 + uint32 flashcontrol; /* 0x40 */
6625 + uint32 flashaddress;
6626 + uint32 flashdata;
6627 + uint32 PAD[1];
6628 +
6629 + /* Silicon backplane configuration broadcast control */
6630 + uint32 broadcastaddress; /* 0x50 */
6631 + uint32 broadcastdata;
6632 + uint32 PAD[2];
6633 +
6634 + /* gpio - cleared only by power-on-reset */
6635 + uint32 gpioin; /* 0x60 */
6636 + uint32 gpioout;
6637 + uint32 gpioouten;
6638 + uint32 gpiocontrol;
6639 + uint32 gpiointpolarity;
6640 + uint32 gpiointmask;
6641 + uint32 PAD[2];
6642 +
6643 + /* Watchdog timer */
6644 + uint32 watchdog; /* 0x80 */
6645 + uint32 PAD[1];
6646 +
6647 + /*GPIO based LED powersave registers corerev >= 16*/
6648 + uint32 gpiotimerval; /*0x88 */
6649 + uint32 gpiotimeroutmask;
6650 +
6651 + /* clock control */
6652 + uint32 clockcontrol_n; /* 0x90 */
6653 + uint32 clockcontrol_sb; /* aka m0 */
6654 + uint32 clockcontrol_pci; /* aka m1 */
6655 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6656 + uint32 clockcontrol_mips; /* aka m3 */
6657 + uint32 clkdiv; /* corerev >= 3 */
6658 + uint32 PAD[2];
6659 +
6660 + /* pll delay registers (corerev >= 4) */
6661 + uint32 pll_on_delay; /* 0xb0 */
6662 + uint32 fref_sel_delay;
6663 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6664 + uint32 PAD[1];
6665 +
6666 + /* Instaclock registers (corerev >= 10) */
6667 + uint32 system_clk_ctl; /* 0xc0 */
6668 + uint32 clkstatestretch;
6669 + uint32 PAD[14];
6670 +
6671 + /* ExtBus control registers (corerev >= 3) */
6672 + uint32 pcmcia_config; /* 0x100 */
6673 + uint32 pcmcia_memwait;
6674 + uint32 pcmcia_attrwait;
6675 + uint32 pcmcia_iowait;
6676 + uint32 ide_config;
6677 + uint32 ide_memwait;
6678 + uint32 ide_attrwait;
6679 + uint32 ide_iowait;
6680 + uint32 prog_config;
6681 + uint32 prog_waitcount;
6682 + uint32 flash_config;
6683 + uint32 flash_waitcount;
6684 + uint32 PAD[116];
6685 +
6686 + /* uarts */
6687 + uint8 uart0data; /* 0x300 */
6688 + uint8 uart0imr;
6689 + uint8 uart0fcr;
6690 + uint8 uart0lcr;
6691 + uint8 uart0mcr;
6692 + uint8 uart0lsr;
6693 + uint8 uart0msr;
6694 + uint8 uart0scratch;
6695 + uint8 PAD[248]; /* corerev >= 1 */
6696 +
6697 + uint8 uart1data; /* 0x400 */
6698 + uint8 uart1imr;
6699 + uint8 uart1fcr;
6700 + uint8 uart1lcr;
6701 + uint8 uart1mcr;
6702 + uint8 uart1lsr;
6703 + uint8 uart1msr;
6704 + uint8 uart1scratch;
6705 +} chipcregs_t;
6706 +
6707 +#endif /* _LANGUAGE_ASSEMBLY */
6708 +
6709 +#define CC_CHIPID 0
6710 +#define CC_CAPABILITIES 4
6711 +#define CC_JTAGCMD 0x30
6712 +#define CC_JTAGIR 0x34
6713 +#define CC_JTAGDR 0x38
6714 +#define CC_JTAGCTRL 0x3c
6715 +#define CC_WATCHDOG 0x80
6716 +#define CC_CLKC_N 0x90
6717 +#define CC_CLKC_M0 0x94
6718 +#define CC_CLKC_M1 0x98
6719 +#define CC_CLKC_M2 0x9c
6720 +#define CC_CLKC_M3 0xa0
6721 +#define CC_CLKDIV 0xa4
6722 +#define CC_SYS_CLK_CTL 0xc0
6723 +#define CC_OTP 0x800
6724 +
6725 +/* chipid */
6726 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6727 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6728 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6729 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6730 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6731 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6732 +#define CID_CC_SHIFT 24
6733 +
6734 +/* capabilities */
6735 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6736 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6737 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6738 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6739 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6740 +#define CAP_EXTBUS 0x00000040 /* External bus present */
6741 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6742 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6743 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6744 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6745 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6746 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6747 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6748 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6749 +
6750 +/* PLL type */
6751 +#define PLL_NONE 0x00000000
6752 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6753 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6754 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6755 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6756 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6757 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6758 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6759 +
6760 +/* corecontrol */
6761 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6762 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6763 +
6764 +/* Fields in the otpstatus register */
6765 +#define OTPS_PROGFAIL 0x80000000
6766 +#define OTPS_PROTECT 0x00000007
6767 +#define OTPS_HW_PROTECT 0x00000001
6768 +#define OTPS_SW_PROTECT 0x00000002
6769 +#define OTPS_CID_PROTECT 0x00000004
6770 +
6771 +/* Fields in the otpcontrol register */
6772 +#define OTPC_RECWAIT 0xff000000
6773 +#define OTPC_PROGWAIT 0x00ffff00
6774 +#define OTPC_PRW_SHIFT 8
6775 +#define OTPC_MAXFAIL 0x00000038
6776 +#define OTPC_VSEL 0x00000006
6777 +#define OTPC_SELVL 0x00000001
6778 +
6779 +/* Fields in otpprog */
6780 +#define OTPP_COL_MASK 0x000000ff
6781 +#define OTPP_ROW_MASK 0x0000ff00
6782 +#define OTPP_ROW_SHIFT 8
6783 +#define OTPP_READERR 0x10000000
6784 +#define OTPP_VALUE 0x20000000
6785 +#define OTPP_VALUE_SHIFT 29
6786 +#define OTPP_READ 0x40000000
6787 +#define OTPP_START 0x80000000
6788 +#define OTPP_BUSY 0x80000000
6789 +
6790 +/* jtagcmd */
6791 +#define JCMD_START 0x80000000
6792 +#define JCMD_BUSY 0x80000000
6793 +#define JCMD_PAUSE 0x40000000
6794 +#define JCMD0_ACC_MASK 0x0000f000
6795 +#define JCMD0_ACC_IRDR 0x00000000
6796 +#define JCMD0_ACC_DR 0x00001000
6797 +#define JCMD0_ACC_IR 0x00002000
6798 +#define JCMD0_ACC_RESET 0x00003000
6799 +#define JCMD0_ACC_IRPDR 0x00004000
6800 +#define JCMD0_ACC_PDR 0x00005000
6801 +#define JCMD0_IRW_MASK 0x00000f00
6802 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6803 +#define JCMD_ACC_IRDR 0x00000000
6804 +#define JCMD_ACC_DR 0x00010000
6805 +#define JCMD_ACC_IR 0x00020000
6806 +#define JCMD_ACC_RESET 0x00030000
6807 +#define JCMD_ACC_IRPDR 0x00040000
6808 +#define JCMD_ACC_PDR 0x00050000
6809 +#define JCMD_IRW_MASK 0x00001f00
6810 +#define JCMD_IRW_SHIFT 8
6811 +#define JCMD_DRW_MASK 0x0000003f
6812 +
6813 +/* jtagctrl */
6814 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6815 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6816 +#define JCTRL_EN 1 /* Enable Jtag master */
6817 +
6818 +/* Fields in clkdiv */
6819 +#define CLKD_SFLASH 0x0f000000
6820 +#define CLKD_SFLASH_SHIFT 24
6821 +#define CLKD_OTP 0x000f0000
6822 +#define CLKD_OTP_SHIFT 16
6823 +#define CLKD_JTAG 0x00000f00
6824 +#define CLKD_JTAG_SHIFT 8
6825 +#define CLKD_UART 0x000000ff
6826 +
6827 +/* intstatus/intmask */
6828 +#define CI_GPIO 0x00000001 /* gpio intr */
6829 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6830 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6831 +
6832 +/* slow_clk_ctl */
6833 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6834 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6835 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6836 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6837 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6838 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
6839 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
6840 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
6841 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
6842 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6843 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6844 +#define SCC_CD_SHIFT 16
6845 +
6846 +/* system_clk_ctl */
6847 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6848 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6849 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6850 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6851 +#define SYCC_HR 0x00000010 /* Force HT */
6852 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
6853 +#define SYCC_CD_SHIFT 16
6854 +
6855 +/* gpiotimerval*/
6856 +#define GPIO_ONTIME_SHIFT 16
6857 +
6858 +/* clockcontrol_n */
6859 +#define CN_N1_MASK 0x3f /* n1 control */
6860 +#define CN_N2_MASK 0x3f00 /* n2 control */
6861 +#define CN_N2_SHIFT 8
6862 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6863 +#define CN_PLLC_SHIFT 16
6864 +
6865 +/* clockcontrol_sb/pci/uart */
6866 +#define CC_M1_MASK 0x3f /* m1 control */
6867 +#define CC_M2_MASK 0x3f00 /* m2 control */
6868 +#define CC_M2_SHIFT 8
6869 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6870 +#define CC_M3_SHIFT 16
6871 +#define CC_MC_MASK 0x1f000000 /* mux control */
6872 +#define CC_MC_SHIFT 24
6873 +
6874 +/* N3M Clock control magic field values */
6875 +#define CC_F6_2 0x02 /* A factor of 2 in */
6876 +#define CC_F6_3 0x03 /* 6-bit fields like */
6877 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6878 +#define CC_F6_5 0x09
6879 +#define CC_F6_6 0x11
6880 +#define CC_F6_7 0x21
6881 +
6882 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6883 +
6884 +#define CC_MC_BYPASS 0x08
6885 +#define CC_MC_M1 0x04
6886 +#define CC_MC_M1M2 0x02
6887 +#define CC_MC_M1M2M3 0x01
6888 +#define CC_MC_M1M3 0x11
6889 +
6890 +/* Type 2 Clock control magic field values */
6891 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6892 +#define CC_T2M2_BIAS 3 /* m2 bias */
6893 +
6894 +#define CC_T2MC_M1BYP 1
6895 +#define CC_T2MC_M2BYP 2
6896 +#define CC_T2MC_M3BYP 4
6897 +
6898 +/* Type 6 Clock control magic field values */
6899 +#define CC_T6_MMASK 1 /* bits of interest in m */
6900 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6901 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6902 +#define SB2MIPS_T6(sb) (2 * (sb))
6903 +
6904 +/* Common clock base */
6905 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6906 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6907 +
6908 +/* Clock control values for 200Mhz in 5350 */
6909 +#define CLKC_5350_N 0x0311
6910 +#define CLKC_5350_M 0x04020009
6911 +
6912 +/* Flash types in the chipcommon capabilities register */
6913 +#define FLASH_NONE 0x000 /* No flash */
6914 +#define SFLASH_ST 0x100 /* ST serial flash */
6915 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6916 +#define PFLASH 0x700 /* Parallel flash */
6917 +
6918 +/* Bits in the config registers */
6919 +#define CC_CFG_EN 0x0001 /* Enable */
6920 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6921 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
6922 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
6923 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
6924 +#define CC_CFG_EM_IDE 0x000a /* IDE */
6925 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6926 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6927 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6928 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6929 +
6930 +/* Start/busy bit in flashcontrol */
6931 +#define SFLASH_START 0x80000000
6932 +#define SFLASH_BUSY SFLASH_START
6933 +
6934 +/* flashcontrol opcodes for ST flashes */
6935 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6936 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6937 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6938 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6939 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6940 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6941 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6942 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6943 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6944 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6945 +
6946 +/* Status register bits for ST flashes */
6947 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6948 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6949 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6950 +#define SFLASH_ST_BP_SHIFT 2
6951 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6952 +
6953 +/* flashcontrol opcodes for Atmel flashes */
6954 +#define SFLASH_AT_READ 0x07e8
6955 +#define SFLASH_AT_PAGE_READ 0x07d2
6956 +#define SFLASH_AT_BUF1_READ
6957 +#define SFLASH_AT_BUF2_READ
6958 +#define SFLASH_AT_STATUS 0x01d7
6959 +#define SFLASH_AT_BUF1_WRITE 0x0384
6960 +#define SFLASH_AT_BUF2_WRITE 0x0387
6961 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6962 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6963 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6964 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6965 +#define SFLASH_AT_PAGE_ERASE 0x0281
6966 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6967 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6968 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6969 +#define SFLASH_AT_BUF1_LOAD 0x0253
6970 +#define SFLASH_AT_BUF2_LOAD 0x0255
6971 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6972 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6973 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6974 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6975 +
6976 +/* Status register bits for Atmel flashes */
6977 +#define SFLASH_AT_READY 0x80
6978 +#define SFLASH_AT_MISMATCH 0x40
6979 +#define SFLASH_AT_ID_MASK 0x38
6980 +#define SFLASH_AT_ID_SHIFT 3
6981 +
6982 +/* OTP regions */
6983 +#define OTP_HW_REGION OTPS_HW_PROTECT
6984 +#define OTP_SW_REGION OTPS_SW_PROTECT
6985 +#define OTP_CID_REGION OTPS_CID_PROTECT
6986 +
6987 +/* OTP regions (Byte offsets from otp size) */
6988 +#define OTP_SWLIM_OFF (-8)
6989 +#define OTP_CIDBASE_OFF 0
6990 +#define OTP_CIDLIM_OFF 8
6991 +
6992 +/* Predefined OTP words (Word offset from otp size) */
6993 +#define OTP_BOUNDARY_OFF (-4)
6994 +#define OTP_HWSIGN_OFF (-3)
6995 +#define OTP_SWSIGN_OFF (-2)
6996 +#define OTP_CIDSIGN_OFF (-1)
6997 +
6998 +#define OTP_CID_OFF 0
6999 +#define OTP_PKG_OFF 1
7000 +#define OTP_FID_OFF 2
7001 +#define OTP_RSV_OFF 3
7002 +#define OTP_LIM_OFF 4
7003 +
7004 +#define OTP_SIGNATURE 0x578a
7005 +#define OTP_MAGIC 0x4e56
7006 +
7007 +#endif /* _SBCHIPC_H */
7008 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
7009 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
7010 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-11-07 22:51:38.784726500 +0100
7011 @@ -0,0 +1,342 @@
7012 +/*
7013 + * Broadcom SiliconBackplane hardware register definitions.
7014 + *
7015 + * Copyright 2005, Broadcom Corporation
7016 + * All Rights Reserved.
7017 + *
7018 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7019 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7020 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7021 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7022 + * $Id$
7023 + */
7024 +
7025 +#ifndef _SBCONFIG_H
7026 +#define _SBCONFIG_H
7027 +
7028 +/* cpp contortions to concatenate w/arg prescan */
7029 +#ifndef PAD
7030 +#define _PADLINE(line) pad ## line
7031 +#define _XSTR(line) _PADLINE(line)
7032 +#define PAD _XSTR(__LINE__)
7033 +#endif
7034 +
7035 +/*
7036 + * SiliconBackplane Address Map.
7037 + * All regions may not exist on all chips.
7038 + */
7039 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
7040 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
7041 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
7042 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
7043 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
7044 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
7045 +
7046 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
7047 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
7048 +
7049 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
7050 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
7051 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
7052 +
7053 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
7054 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
7055 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
7056 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
7057 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
7058 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
7059 +
7060 +
7061 +/* enumeration space related defs */
7062 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
7063 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
7064 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
7065 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
7066 +
7067 +/* mips address */
7068 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
7069 +
7070 +/*
7071 + * Sonics Configuration Space Registers.
7072 + */
7073 +#define SBIPSFLAG 0x08
7074 +#define SBTPSFLAG 0x18
7075 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
7076 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
7077 +#define SBADMATCH3 0x60
7078 +#define SBADMATCH2 0x68
7079 +#define SBADMATCH1 0x70
7080 +#define SBIMSTATE 0x90
7081 +#define SBINTVEC 0x94
7082 +#define SBTMSTATELOW 0x98
7083 +#define SBTMSTATEHIGH 0x9c
7084 +#define SBBWA0 0xa0
7085 +#define SBIMCONFIGLOW 0xa8
7086 +#define SBIMCONFIGHIGH 0xac
7087 +#define SBADMATCH0 0xb0
7088 +#define SBTMCONFIGLOW 0xb8
7089 +#define SBTMCONFIGHIGH 0xbc
7090 +#define SBBCONFIG 0xc0
7091 +#define SBBSTATE 0xc8
7092 +#define SBACTCNFG 0xd8
7093 +#define SBFLAGST 0xe8
7094 +#define SBIDLOW 0xf8
7095 +#define SBIDHIGH 0xfc
7096 +
7097 +#ifndef _LANGUAGE_ASSEMBLY
7098 +
7099 +typedef volatile struct _sbconfig {
7100 + uint32 PAD[2];
7101 + uint32 sbipsflag; /* initiator port ocp slave flag */
7102 + uint32 PAD[3];
7103 + uint32 sbtpsflag; /* target port ocp slave flag */
7104 + uint32 PAD[11];
7105 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
7106 + uint32 PAD;
7107 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
7108 + uint32 PAD[3];
7109 + uint32 sbadmatch3; /* address match3 */
7110 + uint32 PAD;
7111 + uint32 sbadmatch2; /* address match2 */
7112 + uint32 PAD;
7113 + uint32 sbadmatch1; /* address match1 */
7114 + uint32 PAD[7];
7115 + uint32 sbimstate; /* initiator agent state */
7116 + uint32 sbintvec; /* interrupt mask */
7117 + uint32 sbtmstatelow; /* target state */
7118 + uint32 sbtmstatehigh; /* target state */
7119 + uint32 sbbwa0; /* bandwidth allocation table0 */
7120 + uint32 PAD;
7121 + uint32 sbimconfiglow; /* initiator configuration */
7122 + uint32 sbimconfighigh; /* initiator configuration */
7123 + uint32 sbadmatch0; /* address match0 */
7124 + uint32 PAD;
7125 + uint32 sbtmconfiglow; /* target configuration */
7126 + uint32 sbtmconfighigh; /* target configuration */
7127 + uint32 sbbconfig; /* broadcast configuration */
7128 + uint32 PAD;
7129 + uint32 sbbstate; /* broadcast state */
7130 + uint32 PAD[3];
7131 + uint32 sbactcnfg; /* activate configuration */
7132 + uint32 PAD[3];
7133 + uint32 sbflagst; /* current sbflags */
7134 + uint32 PAD[3];
7135 + uint32 sbidlow; /* identification */
7136 + uint32 sbidhigh; /* identification */
7137 +} sbconfig_t;
7138 +
7139 +#endif /* _LANGUAGE_ASSEMBLY */
7140 +
7141 +/* sbipsflag */
7142 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
7143 +#define SBIPS_INT1_SHIFT 0
7144 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
7145 +#define SBIPS_INT2_SHIFT 8
7146 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
7147 +#define SBIPS_INT3_SHIFT 16
7148 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
7149 +#define SBIPS_INT4_SHIFT 24
7150 +
7151 +/* sbtpsflag */
7152 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
7153 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
7154 +
7155 +/* sbtmerrlog */
7156 +#define SBTMEL_CM 0x00000007 /* command */
7157 +#define SBTMEL_CI 0x0000ff00 /* connection id */
7158 +#define SBTMEL_EC 0x0f000000 /* error code */
7159 +#define SBTMEL_ME 0x80000000 /* multiple error */
7160 +
7161 +/* sbimstate */
7162 +#define SBIM_PC 0xf /* pipecount */
7163 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
7164 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
7165 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
7166 +#define SBIM_AP_TK 0x20 /* use token only */
7167 +#define SBIM_AP_RSV 0x30 /* reserved */
7168 +#define SBIM_IBE 0x20000 /* inbanderror */
7169 +#define SBIM_TO 0x40000 /* timeout */
7170 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
7171 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
7172 +
7173 +/* sbtmstatelow */
7174 +#define SBTML_RESET 0x1 /* reset */
7175 +#define SBTML_REJ_MASK 0x6 /* reject */
7176 +#define SBTML_REJ_SHIFT 1
7177 +#define SBTML_CLK 0x10000 /* clock enable */
7178 +#define SBTML_FGC 0x20000 /* force gated clocks on */
7179 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
7180 +#define SBTML_PE 0x40000000 /* pme enable */
7181 +#define SBTML_BE 0x80000000 /* bist enable */
7182 +
7183 +/* sbtmstatehigh */
7184 +#define SBTMH_SERR 0x1 /* serror */
7185 +#define SBTMH_INT 0x2 /* interrupt */
7186 +#define SBTMH_BUSY 0x4 /* busy */
7187 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
7188 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
7189 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
7190 +#define SBTMH_GCR 0x20000000 /* gated clock request */
7191 +#define SBTMH_BISTF 0x40000000 /* bist failed */
7192 +#define SBTMH_BISTD 0x80000000 /* bist done */
7193 +
7194 +
7195 +/* sbbwa0 */
7196 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
7197 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
7198 +#define SBBWA_TAB1_SHIFT 16
7199 +
7200 +/* sbimconfiglow */
7201 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
7202 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
7203 +#define SBIMCL_RTO_SHIFT 4
7204 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
7205 +#define SBIMCL_CID_SHIFT 16
7206 +
7207 +/* sbimconfighigh */
7208 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
7209 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
7210 +#define SBIMCH_TEM_SHIFT 4
7211 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
7212 +#define SBIMCH_BEM_SHIFT 6
7213 +
7214 +/* sbadmatch0 */
7215 +#define SBAM_TYPE_MASK 0x3 /* address type */
7216 +#define SBAM_AD64 0x4 /* reserved */
7217 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
7218 +#define SBAM_ADINT0_SHIFT 3
7219 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
7220 +#define SBAM_ADINT1_SHIFT 3
7221 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
7222 +#define SBAM_ADINT2_SHIFT 3
7223 +#define SBAM_ADEN 0x400 /* enable */
7224 +#define SBAM_ADNEG 0x800 /* negative decode */
7225 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
7226 +#define SBAM_BASE0_SHIFT 8
7227 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
7228 +#define SBAM_BASE1_SHIFT 12
7229 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
7230 +#define SBAM_BASE2_SHIFT 16
7231 +
7232 +/* sbtmconfiglow */
7233 +#define SBTMCL_CD_MASK 0xff /* clock divide */
7234 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
7235 +#define SBTMCL_CO_SHIFT 11
7236 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
7237 +#define SBTMCL_IF_SHIFT 18
7238 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
7239 +#define SBTMCL_IM_SHIFT 24
7240 +
7241 +/* sbtmconfighigh */
7242 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
7243 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
7244 +#define SBTMCH_RM_SHIFT 2
7245 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
7246 +#define SBTMCH_SM_SHIFT 4
7247 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
7248 +#define SBTMCH_EM_SHIFT 8
7249 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
7250 +#define SBTMCH_IM_SHIFT 10
7251 +
7252 +/* sbbconfig */
7253 +#define SBBC_LAT_MASK 0x3 /* sb latency */
7254 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
7255 +#define SBBC_MAX0_SHIFT 16
7256 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
7257 +#define SBBC_MAX1_SHIFT 20
7258 +
7259 +/* sbbstate */
7260 +#define SBBS_SRD 0x1 /* st reg disable */
7261 +#define SBBS_HRD 0x2 /* hold reg disable */
7262 +
7263 +/* sbidlow */
7264 +#define SBIDL_CS_MASK 0x3 /* config space */
7265 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
7266 +#define SBIDL_AR_SHIFT 3
7267 +#define SBIDL_SYNCH 0x40 /* sync */
7268 +#define SBIDL_INIT 0x80 /* initiator */
7269 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
7270 +#define SBIDL_MINLAT_SHIFT 8
7271 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
7272 +#define SBIDL_MAXLAT_SHIFT 12
7273 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
7274 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
7275 +#define SBIDL_CW_SHIFT 18
7276 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
7277 +#define SBIDL_TP_SHIFT 20
7278 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
7279 +#define SBIDL_IP_SHIFT 24
7280 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
7281 +#define SBIDL_RV_SHIFT 28
7282 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
7283 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
7284 +
7285 +/* sbidhigh */
7286 +#define SBIDH_RC_MASK 0x000f /* revision code */
7287 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
7288 +#define SBIDH_RCE_SHIFT 8
7289 +#define SBCOREREV(sbidh) \
7290 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
7291 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
7292 +#define SBIDH_CC_SHIFT 4
7293 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
7294 +#define SBIDH_VC_SHIFT 16
7295 +
7296 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
7297 +
7298 +/* vendor codes */
7299 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
7300 +
7301 +/* core codes */
7302 +#define SB_CC 0x800 /* chipcommon core */
7303 +#define SB_ILINE20 0x801 /* iline20 core */
7304 +#define SB_SDRAM 0x803 /* sdram core */
7305 +#define SB_PCI 0x804 /* pci core */
7306 +#define SB_MIPS 0x805 /* mips core */
7307 +#define SB_ENET 0x806 /* enet mac core */
7308 +#define SB_CODEC 0x807 /* v90 codec core */
7309 +#define SB_USB 0x808 /* usb 1.1 host/device core */
7310 +#define SB_ADSL 0x809 /* ADSL core */
7311 +#define SB_ILINE100 0x80a /* iline100 core */
7312 +#define SB_IPSEC 0x80b /* ipsec core */
7313 +#define SB_PCMCIA 0x80d /* pcmcia core */
7314 +#define SB_SOCRAM 0x80e /* internal memory core */
7315 +#define SB_MEMC 0x80f /* memc sdram core */
7316 +#define SB_EXTIF 0x811 /* external interface core */
7317 +#define SB_D11 0x812 /* 802.11 MAC core */
7318 +#define SB_MIPS33 0x816 /* mips3302 core */
7319 +#define SB_USB11H 0x817 /* usb 1.1 host core */
7320 +#define SB_USB11D 0x818 /* usb 1.1 device core */
7321 +#define SB_USB20H 0x819 /* usb 2.0 host core */
7322 +#define SB_USB20D 0x81a /* usb 2.0 device core */
7323 +#define SB_SDIOH 0x81b /* sdio host core */
7324 +#define SB_ROBO 0x81c /* roboswitch core */
7325 +#define SB_ATA100 0x81d /* parallel ATA core */
7326 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
7327 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
7328 +#define SB_PCIE 0x820 /* pci express core */
7329 +#define SB_SRAMC 0x822 /* SRAM controller core */
7330 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
7331 +
7332 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
7333 +
7334 +/* Not really related to Silicon Backplane, but a couple of software
7335 + * conventions for the use the flash space:
7336 + */
7337 +
7338 +/* Minumum amount of flash we support */
7339 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
7340 +
7341 +/* A boot/binary may have an embedded block that describes its size */
7342 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
7343 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
7344 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
7345 +#define BISZ_TXTST_IDX 1 /* 1: text start */
7346 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
7347 +#define BISZ_DATAST_IDX 3 /* 3: text start */
7348 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
7349 +#define BISZ_BSSST_IDX 5 /* 5: text start */
7350 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
7351 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
7352 +
7353 +#endif /* _SBCONFIG_H */
7354 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
7355 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
7356 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-11-07 21:57:07.877587750 +0100
7357 @@ -0,0 +1,242 @@
7358 +/*
7359 + * Hardware-specific External Interface I/O core definitions
7360 + * for the BCM47xx family of SiliconBackplane-based chips.
7361 + *
7362 + * The External Interface core supports a total of three external chip selects
7363 + * supporting external interfaces. One of the external chip selects is
7364 + * used for Flash, one is used for PCMCIA, and the other may be
7365 + * programmed to support either a synchronous interface or an
7366 + * asynchronous interface. The asynchronous interface can be used to
7367 + * support external devices such as UARTs and the BCM2019 Bluetooth
7368 + * baseband processor.
7369 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
7370 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
7371 + *
7372 + * Copyright 2005, Broadcom Corporation
7373 + * All Rights Reserved.
7374 + *
7375 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7376 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7377 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7378 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7379 + * $Id$
7380 + */
7381 +
7382 +#ifndef _SBEXTIF_H
7383 +#define _SBEXTIF_H
7384 +
7385 +/* external interface address space */
7386 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
7387 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
7388 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
7389 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
7390 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
7391 +
7392 +/* cpp contortions to concatenate w/arg prescan */
7393 +#ifndef PAD
7394 +#define _PADLINE(line) pad ## line
7395 +#define _XSTR(line) _PADLINE(line)
7396 +#define PAD _XSTR(__LINE__)
7397 +#endif /* PAD */
7398 +
7399 +/*
7400 + * The multiple instances of output and output enable registers
7401 + * are present to allow driver software for multiple cores to control
7402 + * gpio outputs without needing to share a single register pair.
7403 + */
7404 +struct gpiouser {
7405 + uint32 out;
7406 + uint32 outen;
7407 +};
7408 +#define NGPIOUSER 5
7409 +
7410 +typedef volatile struct {
7411 + uint32 corecontrol;
7412 + uint32 extstatus;
7413 + uint32 PAD[2];
7414 +
7415 + /* pcmcia control registers */
7416 + uint32 pcmcia_config;
7417 + uint32 pcmcia_memwait;
7418 + uint32 pcmcia_attrwait;
7419 + uint32 pcmcia_iowait;
7420 +
7421 + /* programmable interface control registers */
7422 + uint32 prog_config;
7423 + uint32 prog_waitcount;
7424 +
7425 + /* flash control registers */
7426 + uint32 flash_config;
7427 + uint32 flash_waitcount;
7428 + uint32 PAD[4];
7429 +
7430 + uint32 watchdog;
7431 +
7432 + /* clock control */
7433 + uint32 clockcontrol_n;
7434 + uint32 clockcontrol_sb;
7435 + uint32 clockcontrol_pci;
7436 + uint32 clockcontrol_mii;
7437 + uint32 PAD[3];
7438 +
7439 + /* gpio */
7440 + uint32 gpioin;
7441 + struct gpiouser gpio[NGPIOUSER];
7442 + uint32 PAD;
7443 + uint32 ejtagouten;
7444 + uint32 gpiointpolarity;
7445 + uint32 gpiointmask;
7446 + uint32 PAD[153];
7447 +
7448 + uint8 uartdata;
7449 + uint8 PAD[3];
7450 + uint8 uartimer;
7451 + uint8 PAD[3];
7452 + uint8 uartfcr;
7453 + uint8 PAD[3];
7454 + uint8 uartlcr;
7455 + uint8 PAD[3];
7456 + uint8 uartmcr;
7457 + uint8 PAD[3];
7458 + uint8 uartlsr;
7459 + uint8 PAD[3];
7460 + uint8 uartmsr;
7461 + uint8 PAD[3];
7462 + uint8 uartscratch;
7463 + uint8 PAD[3];
7464 +} extifregs_t;
7465 +
7466 +/* corecontrol */
7467 +#define CC_UE (1 << 0) /* uart enable */
7468 +
7469 +/* extstatus */
7470 +#define ES_EM (1 << 0) /* endian mode (ro) */
7471 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7472 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7473 +
7474 +/* gpio bit mask */
7475 +#define GPIO_BIT0 (1 << 0)
7476 +#define GPIO_BIT1 (1 << 1)
7477 +#define GPIO_BIT2 (1 << 2)
7478 +#define GPIO_BIT3 (1 << 3)
7479 +#define GPIO_BIT4 (1 << 4)
7480 +#define GPIO_BIT5 (1 << 5)
7481 +#define GPIO_BIT6 (1 << 6)
7482 +#define GPIO_BIT7 (1 << 7)
7483 +
7484 +
7485 +/* pcmcia/prog/flash_config */
7486 +#define CF_EN (1 << 0) /* enable */
7487 +#define CF_EM_MASK 0xe /* mode */
7488 +#define CF_EM_SHIFT 1
7489 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7490 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7491 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7492 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7493 +#define CF_BS (1 << 5) /* byteswap */
7494 +#define CF_CD_MASK 0xc0 /* clock divider */
7495 +#define CF_CD_SHIFT 6
7496 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7497 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7498 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7499 +#define CF_CE (1 << 8) /* clock enable */
7500 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7501 +
7502 +/* pcmcia_memwait */
7503 +#define PM_W0_MASK 0x3f /* waitcount0 */
7504 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7505 +#define PM_W1_SHIFT 8
7506 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7507 +#define PM_W2_SHIFT 16
7508 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7509 +#define PM_W3_SHIFT 24
7510 +
7511 +/* pcmcia_attrwait */
7512 +#define PA_W0_MASK 0x3f /* waitcount0 */
7513 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7514 +#define PA_W1_SHIFT 8
7515 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7516 +#define PA_W2_SHIFT 16
7517 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7518 +#define PA_W3_SHIFT 24
7519 +
7520 +/* pcmcia_iowait */
7521 +#define PI_W0_MASK 0x3f /* waitcount0 */
7522 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7523 +#define PI_W1_SHIFT 8
7524 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7525 +#define PI_W2_SHIFT 16
7526 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7527 +#define PI_W3_SHIFT 24
7528 +
7529 +/* prog_waitcount */
7530 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7531 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7532 +#define PW_W1_SHIFT 8
7533 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7534 +#define PW_W2_SHIFT 16
7535 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7536 +#define PW_W3_SHIFT 24
7537 +
7538 +#define PW_W0 0x0000000c
7539 +#define PW_W1 0x00000a00
7540 +#define PW_W2 0x00020000
7541 +#define PW_W3 0x01000000
7542 +
7543 +/* flash_waitcount */
7544 +#define FW_W0_MASK 0x1f /* waitcount0 */
7545 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7546 +#define FW_W1_SHIFT 8
7547 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7548 +#define FW_W2_SHIFT 16
7549 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7550 +#define FW_W3_SHIFT 24
7551 +
7552 +/* watchdog */
7553 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7554 +
7555 +/* clockcontrol_n */
7556 +#define CN_N1_MASK 0x3f /* n1 control */
7557 +#define CN_N2_MASK 0x3f00 /* n2 control */
7558 +#define CN_N2_SHIFT 8
7559 +
7560 +/* clockcontrol_sb/pci/mii */
7561 +#define CC_M1_MASK 0x3f /* m1 control */
7562 +#define CC_M2_MASK 0x3f00 /* m2 control */
7563 +#define CC_M2_SHIFT 8
7564 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7565 +#define CC_M3_SHIFT 16
7566 +#define CC_MC_MASK 0x1f000000 /* mux control */
7567 +#define CC_MC_SHIFT 24
7568 +
7569 +/* Clock control default values */
7570 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7571 +#define CC_DEF_100 0x04020011
7572 +#define CC_DEF_33 0x11030011
7573 +#define CC_DEF_25 0x11050011
7574 +
7575 +/* Clock control values for 125Mhz */
7576 +#define CC_125_N 0x0802
7577 +#define CC_125_M 0x04020009
7578 +#define CC_125_M25 0x11090009
7579 +#define CC_125_M33 0x11090005
7580 +
7581 +/* Clock control magic field values */
7582 +#define CC_F6_2 0x02 /* A factor of 2 in */
7583 +#define CC_F6_3 0x03 /* 6-bit fields like */
7584 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7585 +#define CC_F6_5 0x09
7586 +#define CC_F6_6 0x11
7587 +#define CC_F6_7 0x21
7588 +
7589 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7590 +
7591 +#define CC_MC_BYPASS 0x08
7592 +#define CC_MC_M1 0x04
7593 +#define CC_MC_M1M2 0x02
7594 +#define CC_MC_M1M2M3 0x01
7595 +#define CC_MC_M1M3 0x11
7596 +
7597 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7598 +
7599 +#endif /* _SBEXTIF_H */
7600 diff -urN linux.old/arch/mips/bcm947xx/include/sbhnddma.h linux.dev/arch/mips/bcm947xx/include/sbhnddma.h
7601 --- linux.old/arch/mips/bcm947xx/include/sbhnddma.h 1970-01-01 01:00:00.000000000 +0100
7602 +++ linux.dev/arch/mips/bcm947xx/include/sbhnddma.h 2005-11-07 23:37:03.453685750 +0100
7603 @@ -0,0 +1,312 @@
7604 +/*
7605 + * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
7606 + * This supports the following chips: BCM42xx, 44xx, 47xx .
7607 + *
7608 + * Copyright 2005, Broadcom Corporation
7609 + * All Rights Reserved.
7610 + *
7611 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7612 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7613 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7614 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7615 + * $Id$
7616 + */
7617 +
7618 +#ifndef _sbhnddma_h_
7619 +#define _sbhnddma_h_
7620 +
7621 +
7622 +/* 2byte-wide pio register set per channel(xmt or rcv) */
7623 +typedef volatile struct {
7624 + uint16 fifocontrol;
7625 + uint16 fifodata;
7626 + uint16 fifofree; /* only valid in xmt channel, not in rcv channel */
7627 + uint16 PAD;
7628 +} pio2regs_t;
7629 +
7630 +/* a pair of pio channels(tx and rx) */
7631 +typedef volatile struct {
7632 + pio2regs_t tx;
7633 + pio2regs_t rx;
7634 +} pio2regp_t;
7635 +
7636 +/* 4byte-wide pio register set per channel(xmt or rcv) */
7637 +typedef volatile struct {
7638 + uint32 fifocontrol;
7639 + uint32 fifodata;
7640 +} pio4regs_t;
7641 +
7642 +/* a pair of pio channels(tx and rx) */
7643 +typedef volatile struct {
7644 + pio4regs_t tx;
7645 + pio4regs_t rx;
7646 +} pio4regp_t;
7647 +
7648 +
7649 +
7650 +/* DMA structure:
7651 + * support two DMA engines: 32 bits address or 64 bit addressing
7652 + * basic DMA register set is per channel(transmit or receive)
7653 + * a pair of channels is defined for convenience
7654 + */
7655 +
7656 +
7657 +/*** 32 bits addressing ***/
7658 +
7659 +/* dma registers per channel(xmt or rcv) */
7660 +typedef volatile struct {
7661 + uint32 control; /* enable, et al */
7662 + uint32 addr; /* descriptor ring base address (4K aligned) */
7663 + uint32 ptr; /* last descriptor posted to chip */
7664 + uint32 status; /* current active descriptor, et al */
7665 +} dma32regs_t;
7666 +
7667 +typedef volatile struct {
7668 + dma32regs_t xmt; /* dma tx channel */
7669 + dma32regs_t rcv; /* dma rx channel */
7670 +} dma32regp_t;
7671 +
7672 +typedef volatile struct { /* diag access */
7673 + uint32 fifoaddr; /* diag address */
7674 + uint32 fifodatalow; /* low 32bits of data */
7675 + uint32 fifodatahigh; /* high 32bits of data */
7676 + uint32 pad; /* reserved */
7677 +} dma32diag_t;
7678 +
7679 +/*
7680 + * DMA Descriptor
7681 + * Descriptors are only read by the hardware, never written back.
7682 + */
7683 +typedef volatile struct {
7684 + uint32 ctrl; /* misc control bits & bufcount */
7685 + uint32 addr; /* data buffer address */
7686 +} dma32dd_t;
7687 +
7688 +/*
7689 + * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
7690 + */
7691 +#define D32MAXRINGSZ 4096
7692 +#define D32RINGALIGN 4096
7693 +#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
7694 +
7695 +/* transmit channel control */
7696 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
7697 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
7698 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
7699 +#define XC_FL ((uint32)1 << 4) /* flush request */
7700 +#define XC_AE ((uint32)3 << 16) /* address extension bits */
7701 +#define XC_AE_SHIFT 16
7702 +
7703 +/* transmit descriptor table pointer */
7704 +#define XP_LD_MASK 0xfff /* last valid descriptor */
7705 +
7706 +/* transmit channel status */
7707 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
7708 +#define XS_XS_MASK 0xf000 /* transmit state */
7709 +#define XS_XS_SHIFT 12
7710 +#define XS_XS_DISABLED 0x0000 /* disabled */
7711 +#define XS_XS_ACTIVE 0x1000 /* active */
7712 +#define XS_XS_IDLE 0x2000 /* idle wait */
7713 +#define XS_XS_STOPPED 0x3000 /* stopped */
7714 +#define XS_XS_SUSP 0x4000 /* suspend pending */
7715 +#define XS_XE_MASK 0xf0000 /* transmit errors */
7716 +#define XS_XE_SHIFT 16
7717 +#define XS_XE_NOERR 0x00000 /* no error */
7718 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
7719 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
7720 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
7721 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
7722 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
7723 +#define XS_AD_SHIFT 20
7724 +
7725 +/* receive channel control */
7726 +#define RC_RE ((uint32)1 << 0) /* receive enable */
7727 +#define RC_RO_MASK 0xfe /* receive frame offset */
7728 +#define RC_RO_SHIFT 1
7729 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
7730 +#define RC_AE ((uint32)3 << 16) /* address extension bits */
7731 +#define RC_AE_SHIFT 16
7732 +
7733 +/* receive descriptor table pointer */
7734 +#define RP_LD_MASK 0xfff /* last valid descriptor */
7735 +
7736 +/* receive channel status */
7737 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
7738 +#define RS_RS_MASK 0xf000 /* receive state */
7739 +#define RS_RS_SHIFT 12
7740 +#define RS_RS_DISABLED 0x0000 /* disabled */
7741 +#define RS_RS_ACTIVE 0x1000 /* active */
7742 +#define RS_RS_IDLE 0x2000 /* idle wait */
7743 +#define RS_RS_STOPPED 0x3000 /* reserved */
7744 +#define RS_RE_MASK 0xf0000 /* receive errors */
7745 +#define RS_RE_SHIFT 16
7746 +#define RS_RE_NOERR 0x00000 /* no error */
7747 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
7748 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
7749 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
7750 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
7751 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
7752 +#define RS_AD_SHIFT 20
7753 +
7754 +/* fifoaddr */
7755 +#define FA_OFF_MASK 0xffff /* offset */
7756 +#define FA_SEL_MASK 0xf0000 /* select */
7757 +#define FA_SEL_SHIFT 16
7758 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
7759 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
7760 +#define FA_SEL_RDD 0x40000 /* receive dma data */
7761 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
7762 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
7763 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7764 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
7765 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7766 +#define FA_SEL_RSD 0xe0000 /* receive frame status data */
7767 +#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
7768 +
7769 +/* descriptor control flags */
7770 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
7771 +#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
7772 +#define CTRL_AE_SHIFT 16
7773 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
7774 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
7775 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
7776 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
7777 +
7778 +/* control flags in the range [27:20] are core-specific and not defined here */
7779 +#define CTRL_CORE_MASK 0x0ff00000
7780 +
7781 +/*** 64 bits addressing ***/
7782 +
7783 +/* dma registers per channel(xmt or rcv) */
7784 +typedef volatile struct {
7785 + uint32 control; /* enable, et al */
7786 + uint32 ptr; /* last descriptor posted to chip */
7787 + uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
7788 + uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
7789 + uint32 status0; /* current descriptor, xmt state */
7790 + uint32 status1; /* active descriptor, xmt error */
7791 +} dma64regs_t;
7792 +
7793 +typedef volatile struct {
7794 + dma64regs_t tx; /* dma64 tx channel */
7795 + dma64regs_t rx; /* dma64 rx channel */
7796 +} dma64regp_t;
7797 +
7798 +typedef volatile struct { /* diag access */
7799 + uint32 fifoaddr; /* diag address */
7800 + uint32 fifodatalow; /* low 32bits of data */
7801 + uint32 fifodatahigh; /* high 32bits of data */
7802 + uint32 pad; /* reserved */
7803 +} dma64diag_t;
7804 +
7805 +/*
7806 + * DMA Descriptor
7807 + * Descriptors are only read by the hardware, never written back.
7808 + */
7809 +typedef volatile struct {
7810 + uint32 ctrl1; /* misc control bits & bufcount */
7811 + uint32 ctrl2; /* buffer count and address extension */
7812 + uint32 addrlow; /* memory address of the first byte of the date buffer, bits 31:0 */
7813 + uint32 addrhigh; /* memory address of the first byte of the date buffer, bits 63:32 */
7814 +} dma64dd_t;
7815 +
7816 +/*
7817 + * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
7818 + */
7819 +#define D64MAXRINGSZ 8192
7820 +#define D64RINGALIGN 8192
7821 +#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
7822 +
7823 +/* transmit channel control */
7824 +#define D64_XC_XE 0x00000001 /* transmit enable */
7825 +#define D64_XC_SE 0x00000002 /* transmit suspend request */
7826 +#define D64_XC_LE 0x00000004 /* loopback enable */
7827 +#define D64_XC_FL 0x00000010 /* flush request */
7828 +#define D64_XC_AE 0x00110000 /* address extension bits */
7829 +#define D64_XC_AE_SHIFT 16
7830 +
7831 +/* transmit descriptor table pointer */
7832 +#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
7833 +
7834 +/* transmit channel status */
7835 +#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
7836 +#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
7837 +#define D64_XS0_XS_SHIFT 28
7838 +#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
7839 +#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
7840 +#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
7841 +#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
7842 +#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
7843 +
7844 +#define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
7845 +#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
7846 +#define D64_XS1_XE_SHIFT 28
7847 +#define D64_XS1_XE_NOERR 0x00000000 /* no error */
7848 +#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
7849 +#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
7850 +#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
7851 +#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
7852 +#define D64_XS1_XE_COREE 0x50000000 /* core error */
7853 +
7854 +/* receive channel control */
7855 +#define D64_RC_RE 0x00000001 /* receive enable */
7856 +#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
7857 +#define D64_RC_RO_SHIFT 1
7858 +#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
7859 +#define D64_RC_AE 0x00110000 /* address extension bits */
7860 +#define D64_RC_AE_SHIFT 16
7861 +
7862 +/* receive descriptor table pointer */
7863 +#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
7864 +
7865 +/* receive channel status */
7866 +#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
7867 +#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
7868 +#define D64_RS0_RS_SHIFT 28
7869 +#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
7870 +#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
7871 +#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
7872 +#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
7873 +#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
7874 +
7875 +#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
7876 +#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
7877 +#define D64_RS1_RE_SHIFT 28
7878 +#define D64_RS1_RE_NOERR 0x00000000 /* no error */
7879 +#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
7880 +#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
7881 +#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
7882 +#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
7883 +#define D64_RS1_RE_COREE 0x50000000 /* core error */
7884 +
7885 +/* fifoaddr */
7886 +#define D64_FA_OFF_MASK 0xffff /* offset */
7887 +#define D64_FA_SEL_MASK 0xf0000 /* select */
7888 +#define D64_FA_SEL_SHIFT 16
7889 +#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
7890 +#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
7891 +#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
7892 +#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
7893 +#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
7894 +#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7895 +#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
7896 +#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7897 +#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
7898 +#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
7899 +
7900 +/* descriptor control flags 1 */
7901 +#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
7902 +#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
7903 +#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
7904 +#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
7905 +
7906 +/* descriptor control flags 2 */
7907 +#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
7908 +#define D64_CTRL2_AE 0x00110000 /* address extension bits */
7909 +#define D64_CTRL2_AE_SHIFT 16
7910 +
7911 +/* control flags in the range [27:20] are core-specific and not defined here */
7912 +#define D64_CTRL_CORE_MASK 0x0ff00000
7913 +
7914 +
7915 +#endif /* _sbhnddma_h_ */
7916 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7917 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7918 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-11-07 22:51:38.784726500 +0100
7919 @@ -0,0 +1,148 @@
7920 +/*
7921 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7922 + *
7923 + * Copyright 2005, Broadcom Corporation
7924 + * All Rights Reserved.
7925 + *
7926 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7927 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7928 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7929 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7930 + *
7931 + * $Id$
7932 + */
7933 +
7934 +#ifndef _SBMEMC_H
7935 +#define _SBMEMC_H
7936 +
7937 +#ifdef _LANGUAGE_ASSEMBLY
7938 +
7939 +#define MEMC_CONTROL 0x00
7940 +#define MEMC_CONFIG 0x04
7941 +#define MEMC_REFRESH 0x08
7942 +#define MEMC_BISTSTAT 0x0c
7943 +#define MEMC_MODEBUF 0x10
7944 +#define MEMC_BKCLS 0x14
7945 +#define MEMC_PRIORINV 0x18
7946 +#define MEMC_DRAMTIM 0x1c
7947 +#define MEMC_INTSTAT 0x20
7948 +#define MEMC_INTMASK 0x24
7949 +#define MEMC_INTINFO 0x28
7950 +#define MEMC_NCDLCTL 0x30
7951 +#define MEMC_RDNCDLCOR 0x34
7952 +#define MEMC_WRNCDLCOR 0x38
7953 +#define MEMC_MISCDLYCTL 0x3c
7954 +#define MEMC_DQSGATENCDL 0x40
7955 +#define MEMC_SPARE 0x44
7956 +#define MEMC_TPADDR 0x48
7957 +#define MEMC_TPDATA 0x4c
7958 +#define MEMC_BARRIER 0x50
7959 +#define MEMC_CORE 0x54
7960 +
7961 +
7962 +#else
7963 +
7964 +/* Sonics side: MEMC core registers */
7965 +typedef volatile struct sbmemcregs {
7966 + uint32 control;
7967 + uint32 config;
7968 + uint32 refresh;
7969 + uint32 biststat;
7970 + uint32 modebuf;
7971 + uint32 bkcls;
7972 + uint32 priorinv;
7973 + uint32 dramtim;
7974 + uint32 intstat;
7975 + uint32 intmask;
7976 + uint32 intinfo;
7977 + uint32 reserved1;
7978 + uint32 ncdlctl;
7979 + uint32 rdncdlcor;
7980 + uint32 wrncdlcor;
7981 + uint32 miscdlyctl;
7982 + uint32 dqsgatencdl;
7983 + uint32 spare;
7984 + uint32 tpaddr;
7985 + uint32 tpdata;
7986 + uint32 barrier;
7987 + uint32 core;
7988 +} sbmemcregs_t;
7989 +
7990 +#endif
7991 +
7992 +/* MEMC Core Init values (OCP ID 0x80f) */
7993 +
7994 +/* For sdr: */
7995 +#define MEMC_SD_CONFIG_INIT 0x00048000
7996 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7997 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7998 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7999 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
8000 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
8001 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
8002 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
8003 +#define MEMC_SD_CONTROL_INIT0 0x00000002
8004 +#define MEMC_SD_CONTROL_INIT1 0x00000008
8005 +#define MEMC_SD_CONTROL_INIT2 0x00000004
8006 +#define MEMC_SD_CONTROL_INIT3 0x00000010
8007 +#define MEMC_SD_CONTROL_INIT4 0x00000001
8008 +#define MEMC_SD_MODEBUF_INIT 0x00000000
8009 +#define MEMC_SD_REFRESH_INIT 0x0000840f
8010 +
8011 +
8012 +/* This is for SDRM8X8X4 */
8013 +#define MEMC_SDR_INIT 0x0008
8014 +#define MEMC_SDR_MODE 0x32
8015 +#define MEMC_SDR_NCDL 0x00020032
8016 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
8017 +
8018 +/* For ddr: */
8019 +#define MEMC_CONFIG_INIT 0x00048000
8020 +#define MEMC_DRAMTIM2_INIT 0x000754d8
8021 +#define MEMC_DRAMTIM25_INIT 0x000754d9
8022 +#define MEMC_RDNCDLCOR_INIT 0x00000000
8023 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
8024 +#define MEMC_WRNCDLCOR_INIT 0x49351200
8025 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
8026 +#define MEMC_DQSGATENCDL_INIT 0x00030000
8027 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
8028 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
8029 +#define MEMC_NCDLCTL_INIT 0x00002001
8030 +#define MEMC_CONTROL_INIT0 0x00000002
8031 +#define MEMC_CONTROL_INIT1 0x00000008
8032 +#define MEMC_MODEBUF_INIT0 0x00004000
8033 +#define MEMC_CONTROL_INIT2 0x00000010
8034 +#define MEMC_MODEBUF_INIT1 0x00000100
8035 +#define MEMC_CONTROL_INIT3 0x00000010
8036 +#define MEMC_CONTROL_INIT4 0x00000008
8037 +#define MEMC_REFRESH_INIT 0x0000840f
8038 +#define MEMC_CONTROL_INIT5 0x00000004
8039 +#define MEMC_MODEBUF_INIT2 0x00000000
8040 +#define MEMC_CONTROL_INIT6 0x00000010
8041 +#define MEMC_CONTROL_INIT7 0x00000001
8042 +
8043 +
8044 +/* This is for DDRM16X16X2 */
8045 +#define MEMC_DDR_INIT 0x0009
8046 +#define MEMC_DDR_MODE 0x62
8047 +#define MEMC_DDR_NCDL 0x0005050a
8048 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
8049 +
8050 +/* mask for sdr/ddr calibration registers */
8051 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
8052 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
8053 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
8054 +
8055 +/* masks for miscdlyctl registers */
8056 +#define MEMC_MISC_SM_MASK 0x30000000
8057 +#define MEMC_MISC_SM_SHIFT 28
8058 +#define MEMC_MISC_SD_MASK 0x0f000000
8059 +#define MEMC_MISC_SD_SHIFT 24
8060 +
8061 +/* hw threshhold for calculating wr/rd for sdr memc */
8062 +#define MEMC_CD_THRESHOLD 128
8063 +
8064 +/* Low bit of init register says if memc is ddr or sdr */
8065 +#define MEMC_CONFIG_DDR 0x00000001
8066 +
8067 +#endif /* _SBMEMC_H */
8068 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
8069 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
8070 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-11-07 22:51:38.784726500 +0100
8071 @@ -0,0 +1,62 @@
8072 +/*
8073 + * Broadcom SiliconBackplane MIPS definitions
8074 + *
8075 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
8076 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
8077 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
8078 + * interface. The core revision is stored in the SB ID register in SB
8079 + * configuration space.
8080 + *
8081 + * Copyright 2005, Broadcom Corporation
8082 + * All Rights Reserved.
8083 + *
8084 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8085 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8086 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8087 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8088 + *
8089 + * $Id$
8090 + */
8091 +
8092 +#ifndef _SBMIPS_H
8093 +#define _SBMIPS_H
8094 +
8095 +#include <mipsinc.h>
8096 +
8097 +#ifndef _LANGUAGE_ASSEMBLY
8098 +
8099 +/* cpp contortions to concatenate w/arg prescan */
8100 +#ifndef PAD
8101 +#define _PADLINE(line) pad ## line
8102 +#define _XSTR(line) _PADLINE(line)
8103 +#define PAD _XSTR(__LINE__)
8104 +#endif /* PAD */
8105 +
8106 +typedef volatile struct {
8107 + uint32 corecontrol;
8108 + uint32 PAD[2];
8109 + uint32 biststatus;
8110 + uint32 PAD[4];
8111 + uint32 intstatus;
8112 + uint32 intmask;
8113 + uint32 timer;
8114 +} mipsregs_t;
8115 +
8116 +extern uint32 sb_flag(sb_t *sbh);
8117 +extern uint sb_irq(sb_t *sbh);
8118 +
8119 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
8120 +
8121 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
8122 +extern void sb_jtagm_disable(void *h);
8123 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
8124 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
8125 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
8126 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
8127 +extern void BCMINIT(enable_pfc)(uint32 mode);
8128 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
8129 +
8130 +
8131 +#endif /* _LANGUAGE_ASSEMBLY */
8132 +
8133 +#endif /* _SBMIPS_H */
8134 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
8135 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
8136 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-11-07 22:51:38.788726750 +0100
8137 @@ -0,0 +1,122 @@
8138 +/*
8139 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
8140 + *
8141 + * $Id$
8142 + * Copyright 2005, Broadcom Corporation
8143 + * All Rights Reserved.
8144 + *
8145 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8146 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8147 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8148 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8149 + */
8150 +
8151 +#ifndef _SBPCI_H
8152 +#define _SBPCI_H
8153 +
8154 +/* cpp contortions to concatenate w/arg prescan */
8155 +#ifndef PAD
8156 +#define _PADLINE(line) pad ## line
8157 +#define _XSTR(line) _PADLINE(line)
8158 +#define PAD _XSTR(__LINE__)
8159 +#endif
8160 +
8161 +/* Sonics side: PCI core and host control registers */
8162 +typedef struct sbpciregs {
8163 + uint32 control; /* PCI control */
8164 + uint32 PAD[3];
8165 + uint32 arbcontrol; /* PCI arbiter control */
8166 + uint32 PAD[3];
8167 + uint32 intstatus; /* Interrupt status */
8168 + uint32 intmask; /* Interrupt mask */
8169 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
8170 + uint32 PAD[9];
8171 + uint32 bcastaddr; /* Sonics broadcast address */
8172 + uint32 bcastdata; /* Sonics broadcast data */
8173 + uint32 PAD[2];
8174 + uint32 gpioin; /* ro: gpio input (>=rev2) */
8175 + uint32 gpioout; /* rw: gpio output (>=rev2) */
8176 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
8177 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
8178 + uint32 PAD[36];
8179 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
8180 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
8181 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
8182 + uint32 PAD[445];
8183 + uint16 sprom[36]; /* SPROM shadow Area */
8184 + uint32 PAD[46];
8185 +} sbpciregs_t;
8186 +
8187 +/* PCI control */
8188 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
8189 +#define PCI_RST 0x02 /* Value driven out to pin */
8190 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
8191 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
8192 +
8193 +/* PCI arbiter control */
8194 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
8195 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
8196 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
8197 +#define PCI_PARKID_SHIFT 1
8198 +#define PCI_PARKID_LAST 0 /* Last requestor */
8199 +#define PCI_PARKID_4710 1 /* 4710 */
8200 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
8201 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
8202 +
8203 +/* Interrupt status/mask */
8204 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
8205 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
8206 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
8207 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
8208 +#define PCI_PME 0x10 /* PCI PME# is asserted */
8209 +
8210 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
8211 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
8212 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
8213 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
8214 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
8215 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
8216 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
8217 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
8218 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
8219 +
8220 +/* Sonics broadcast address */
8221 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
8222 +
8223 +/* Sonics to PCI translation types */
8224 +#define SBTOPCI0_MASK 0xfc000000
8225 +#define SBTOPCI1_MASK 0xfc000000
8226 +#define SBTOPCI2_MASK 0xc0000000
8227 +#define SBTOPCI_MEM 0
8228 +#define SBTOPCI_IO 1
8229 +#define SBTOPCI_CFG0 2
8230 +#define SBTOPCI_CFG1 3
8231 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
8232 +#define SBTOPCI_BURST 0x8 /* burst enable */
8233 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
8234 +#define SBTOPCI_RC_READ 0x00 /* memory read */
8235 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
8236 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
8237 +
8238 +/* PCI core index in SROM shadow area */
8239 +#define SRSH_PI_OFFSET 0 /* first word */
8240 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
8241 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
8242 +
8243 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
8244 +#define cap_list rsvd_a[0]
8245 +#define bar0_window dev_dep[0x80 - 0x40]
8246 +#define bar1_window dev_dep[0x84 - 0x40]
8247 +#define sprom_control dev_dep[0x88 - 0x40]
8248 +
8249 +#ifndef _LANGUAGE_ASSEMBLY
8250 +
8251 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
8252 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
8253 +extern void sbpci_ban(uint16 core);
8254 +extern int sbpci_init(sb_t *sbh);
8255 +extern void sbpci_check(sb_t *sbh);
8256 +
8257 +#endif /* !_LANGUAGE_ASSEMBLY */
8258 +
8259 +#endif /* _SBPCI_H */
8260 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
8261 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
8262 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2005-11-07 23:39:41.403557000 +0100
8263 @@ -0,0 +1,199 @@
8264 +/*
8265 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
8266 + *
8267 + * $Id:
8268 + * Copyright 2005, Broadcom Corporation
8269 + * All Rights Reserved.
8270 + *
8271 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8272 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8273 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8274 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8275 + */
8276 +
8277 +#ifndef _SBPCIE_H
8278 +#define _SBPCIE_H
8279 +
8280 +/* cpp contortions to concatenate w/arg prescan */
8281 +#ifndef PAD
8282 +#define _PADLINE(line) pad ## line
8283 +#define _XSTR(line) _PADLINE(line)
8284 +#define PAD _XSTR(__LINE__)
8285 +#endif
8286 +
8287 +/* PCIE Enumeration space offsets*/
8288 +#define PCIE_CORE_CONFIG_OFFSET 0x0
8289 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
8290 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
8291 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
8292 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
8293 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
8294 +#define PCIE_SBCONFIG_OFFSET 0xE00
8295 +
8296 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
8297 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
8298 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
8299 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
8300 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
8301 +
8302 +/* SB side: PCIE core and host control registers */
8303 +typedef struct sbpcieregs {
8304 +
8305 + uint32 PAD[3];
8306 + uint32 biststatus; /* bist Status: 0x00C*/
8307 + uint32 PAD[6];
8308 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028*/
8309 + uint32 PAD[54];
8310 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
8311 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
8312 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
8313 + uint32 PAD[4];
8314 +
8315 + /* pcie core supports in direct access to config space */
8316 + uint32 configaddr; /* pcie config space access: Address field: 0x120*/
8317 + uint32 configdata; /* pcie config space access: Data field: 0x124*/
8318 +
8319 + /* mdio access to serdes */
8320 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
8321 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
8322 +
8323 + /* pcie protocol phy/dllp/tlp register access mechanism*/
8324 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
8325 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
8326 +
8327 + uint32 PAD[434];
8328 + uint16 sprom[36]; /* SPROM shadow Area */
8329 +} sbpcieregs_t;
8330 +
8331 +/* SB to PCIE translation masks */
8332 +#define SBTOPCIE0_MASK 0xfc000000
8333 +#define SBTOPCIE1_MASK 0xfc000000
8334 +#define SBTOPCIE2_MASK 0xc0000000
8335 +
8336 +/* Access type bits (0:1)*/
8337 +#define SBTOPCIE_MEM 0
8338 +#define SBTOPCIE_IO 1
8339 +#define SBTOPCIE_CFG0 2
8340 +#define SBTOPCIE_CFG1 3
8341 +
8342 +/*Prefetch enable bit 2*/
8343 +#define SBTOPCIE_PF 4
8344 +
8345 +/*Write Burst enable for memory write bit 3*/
8346 +#define SBTOPCIE_WR_BURST 8
8347 +
8348 +/* config access */
8349 +#define CONFIGADDR_FUNC_MASK 0x7000
8350 +#define CONFIGADDR_FUNC_SHF 12
8351 +#define CONFIGADDR_REG_MASK 0x0FFF
8352 +#define CONFIGADDR_REG_SHF 0
8353 +
8354 +/* PCIE protocol regs Indirect Address */
8355 +#define PCIEADDR_PROT_MASK 0x300
8356 +#define PCIEADDR_PROT_SHF 8
8357 +#define PCIEADDR_PL_TLP 0
8358 +#define PCIEADDR_PL_DLLP 1
8359 +#define PCIEADDR_PL_PLP 2
8360 +
8361 +/* PCIE protocol PHY diagnostic registers */
8362 +#define PCIE_PLP_MODEREG 0x200 /* Mode*/
8363 +#define PCIE_PLP_STATUSREG 0x204 /* Status*/
8364 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
8365 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number*/
8366 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number*/
8367 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
8368 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
8369 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
8370 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
8371 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error*/
8372 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
8373 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg*/
8374 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
8375 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
8376 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag*/
8377 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag*/
8378 +
8379 +/* PCIE protocol DLLP diagnostic registers */
8380 +#define PCIE_DLLP_LCREG 0x100 /* Link Control*/
8381 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
8382 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention*/
8383 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
8384 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num*/
8385 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num*/
8386 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num*/
8387 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
8388 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay*/
8389 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout*/
8390 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold*/
8391 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr*/
8392 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr*/
8393 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr*/
8394 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write*/
8395 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
8396 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
8397 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter*/
8398 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter*/
8399 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
8400 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST*/
8401 +
8402 +/* PCIE protocol TLP diagnostic registers */
8403 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
8404 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
8405 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address*/
8406 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address*/
8407 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req*/
8408 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address*/
8409 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address*/
8410 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req*/
8411 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address*/
8412 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address*/
8413 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req*/
8414 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len*/
8415 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs*/
8416 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req*/
8417 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len*/
8418 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0*/
8419 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1*/
8420 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2*/
8421 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
8422 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
8423 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
8424 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len*/
8425 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0*/
8426 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1*/
8427 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func*/
8428 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter*/
8429 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value*/
8430 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1*/
8431 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2*/
8432 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3*/
8433 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4*/
8434 +
8435 +/* MDIO control */
8436 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
8437 +#define MDIOCTL_DIVISOR_VAL 0x2
8438 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
8439 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
8440 +
8441 +/* MDIO Data */
8442 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
8443 +#define MDIODATA_TA 0x00020000 /* Turnaround */
8444 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
8445 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
8446 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
8447 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
8448 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
8449 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
8450 +#define MDIODATA_START 0x40000000 /* start of Transaction */
8451 +
8452 +/* MDIO devices (SERDES modules) */
8453 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
8454 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
8455 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
8456 +
8457 +/* SERDES registers */
8458 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
8459 +#define SERDES_RX_CDR 6 /* CDR */
8460 +#define SERDES_RX_CDRBW 7 /* CDR BW */
8461 +
8462 +#endif /* _SBPCIE_H */
8463 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
8464 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
8465 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2005-11-07 22:51:38.788726750 +0100
8466 @@ -0,0 +1,146 @@
8467 +/*
8468 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
8469 + *
8470 + * $Id$
8471 + * Copyright 2005, Broadcom Corporation
8472 + * All Rights Reserved.
8473 + *
8474 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8475 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8476 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8477 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8478 + */
8479 +
8480 +#ifndef _SBPCMCIA_H
8481 +#define _SBPCMCIA_H
8482 +
8483 +
8484 +/* All the addresses that are offsets in attribute space are divided
8485 + * by two to account for the fact that odd bytes are invalid in
8486 + * attribute space and our read/write routines make the space appear
8487 + * as if they didn't exist. Still we want to show the original numbers
8488 + * as documented in the hnd_pcmcia core manual.
8489 + */
8490 +
8491 +/* PCMCIA Function Configuration Registers */
8492 +#define PCMCIA_FCR (0x700 / 2)
8493 +
8494 +#define FCR0_OFF 0
8495 +#define FCR1_OFF (0x40 / 2)
8496 +#define FCR2_OFF (0x80 / 2)
8497 +#define FCR3_OFF (0xc0 / 2)
8498 +
8499 +#define PCMCIA_FCR0 (0x700 / 2)
8500 +#define PCMCIA_FCR1 (0x740 / 2)
8501 +#define PCMCIA_FCR2 (0x780 / 2)
8502 +#define PCMCIA_FCR3 (0x7c0 / 2)
8503 +
8504 +/* Standard PCMCIA FCR registers */
8505 +
8506 +#define PCMCIA_COR 0
8507 +
8508 +#define COR_RST 0x80
8509 +#define COR_LEV 0x40
8510 +#define COR_IRQEN 0x04
8511 +#define COR_BLREN 0x01
8512 +#define COR_FUNEN 0x01
8513 +
8514 +
8515 +#define PCICIA_FCSR (2 / 2)
8516 +#define PCICIA_PRR (4 / 2)
8517 +#define PCICIA_SCR (6 / 2)
8518 +#define PCICIA_ESR (8 / 2)
8519 +
8520 +
8521 +#define PCM_MEMOFF 0x0000
8522 +#define F0_MEMOFF 0x1000
8523 +#define F1_MEMOFF 0x2000
8524 +#define F2_MEMOFF 0x3000
8525 +#define F3_MEMOFF 0x4000
8526 +
8527 +/* Memory base in the function fcr's */
8528 +#define MEM_ADDR0 (0x728 / 2)
8529 +#define MEM_ADDR1 (0x72a / 2)
8530 +#define MEM_ADDR2 (0x72c / 2)
8531 +
8532 +/* PCMCIA base plus Srom access in fcr0: */
8533 +#define PCMCIA_ADDR0 (0x072e / 2)
8534 +#define PCMCIA_ADDR1 (0x0730 / 2)
8535 +#define PCMCIA_ADDR2 (0x0732 / 2)
8536 +
8537 +#define MEM_SEG (0x0734 / 2)
8538 +#define SROM_CS (0x0736 / 2)
8539 +#define SROM_DATAL (0x0738 / 2)
8540 +#define SROM_DATAH (0x073a / 2)
8541 +#define SROM_ADDRL (0x073c / 2)
8542 +#define SROM_ADDRH (0x073e / 2)
8543 +
8544 +/* Values for srom_cs: */
8545 +#define SROM_IDLE 0
8546 +#define SROM_WRITE 1
8547 +#define SROM_READ 2
8548 +#define SROM_WEN 4
8549 +#define SROM_WDS 7
8550 +#define SROM_DONE 8
8551 +
8552 +/* CIS stuff */
8553 +
8554 +/* The CIS stops where the FCRs start */
8555 +#define CIS_SIZE PCMCIA_FCR
8556 +
8557 +/* Standard tuples we know about */
8558 +
8559 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
8560 +#define CISTPL_FUNCE 0x22 /* Function extensions */
8561 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
8562 +
8563 +/* Function extensions for LANs */
8564 +
8565 +#define LAN_TECH 1 /* Technology type */
8566 +#define LAN_SPEED 2 /* Raw bit rate */
8567 +#define LAN_MEDIA 3 /* Transmission media */
8568 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
8569 +#define LAN_CONN 5 /* Connector standard */
8570 +
8571 +
8572 +/* CFTable */
8573 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
8574 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
8575 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
8576 +
8577 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
8578 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
8579 + */
8580 +
8581 +#define CISTPL_BRCM_HNBU 0x80
8582 +
8583 +/* Subtypes of BRCM_HNBU: */
8584 +
8585 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
8586 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
8587 + * device id and chiprev
8588 + */
8589 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
8590 +#define HNBU_PAPARMS 0x03 /* PA parameters: 1 (old), 8 (sreomrev == 1)
8591 + * or 9 (sromrev > 1) bytes */
8592 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
8593 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
8594 +#define HNBU_AA 0x06 /* Antennas available */
8595 +#define HNBU_AG 0x07 /* Antenna gain */
8596 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
8597 +#define HNBU_LEDS 0x09 /* LED set */
8598 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
8599 + * in rev 2
8600 + */
8601 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
8602 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
8603 +
8604 +
8605 +/* sbtmstatelow */
8606 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
8607 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
8608 +
8609 +/* sbtmstatehigh */
8610 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
8611 +
8612 +#endif /* _SBPCMCIA_H */
8613 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
8614 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
8615 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-11-07 21:57:07.877587750 +0100
8616 @@ -0,0 +1,75 @@
8617 +/*
8618 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
8619 + *
8620 + * Copyright 2005, Broadcom Corporation
8621 + * All Rights Reserved.
8622 + *
8623 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8624 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8625 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8626 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8627 + * $Id$
8628 + */
8629 +
8630 +#ifndef _SBSDRAM_H
8631 +#define _SBSDRAM_H
8632 +
8633 +#ifndef _LANGUAGE_ASSEMBLY
8634 +
8635 +/* Sonics side: SDRAM core registers */
8636 +typedef volatile struct sbsdramregs {
8637 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
8638 + uint32 config; /* Initializes external SDRAM mode register */
8639 + uint32 refresh; /* Controls external SDRAM refresh rate */
8640 + uint32 pad1;
8641 + uint32 pad2;
8642 +} sbsdramregs_t;
8643 +
8644 +#endif
8645 +
8646 +/* SDRAM initialization control (initcontrol) register bits */
8647 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
8648 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
8649 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
8650 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
8651 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
8652 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
8653 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
8654 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
8655 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
8656 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
8657 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
8658 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
8659 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
8660 +
8661 +/* SDRAM configuration (config) register bits */
8662 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
8663 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
8664 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
8665 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
8666 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
8667 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
8668 +
8669 +/* SDRAM refresh control (refresh) register bits */
8670 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
8671 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
8672 +
8673 +/* SDRAM Core default Init values (OCP ID 0x803) */
8674 +#define SDRAM_INIT MEM4MX16X2
8675 +#define SDRAM_CONFIG SDRAM_BURSTFULL
8676 +#define SDRAM_REFRESH SDRAM_REF(0x40)
8677 +
8678 +#define MEM1MX16 0x009 /* 2 MB */
8679 +#define MEM1MX16X2 0x409 /* 4 MB */
8680 +#define MEM2MX8X2 0x809 /* 4 MB */
8681 +#define MEM2MX8X4 0xc09 /* 8 MB */
8682 +#define MEM2MX32 0x439 /* 8 MB */
8683 +#define MEM4MX16 0x019 /* 8 MB */
8684 +#define MEM4MX16X2 0x419 /* 16 MB */
8685 +#define MEM8MX8X2 0x819 /* 16 MB */
8686 +#define MEM8MX16 0x829 /* 16 MB */
8687 +#define MEM4MX32 0x429 /* 16 MB */
8688 +#define MEM8MX8X4 0xc19 /* 32 MB */
8689 +#define MEM8MX16X2 0xc29 /* 32 MB */
8690 +
8691 +#endif /* _SBSDRAM_H */
8692 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
8693 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
8694 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2005-11-07 21:57:07.877587750 +0100
8695 @@ -0,0 +1,37 @@
8696 +/*
8697 + * BCM47XX Sonics SiliconBackplane embedded ram core
8698 + *
8699 + * Copyright 2005, Broadcom Corporation
8700 + * All Rights Reserved.
8701 + *
8702 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8703 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8704 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8705 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8706 + *
8707 + * $Id$
8708 + */
8709 +
8710 +#ifndef _SBSOCRAM_H
8711 +#define _SBSOCRAM_H
8712 +
8713 +#define SOCRAM_MEMSIZE 0x00
8714 +#define SOCRAM_BISTSTAT 0x0c
8715 +
8716 +
8717 +#ifndef _LANGUAGE_ASSEMBLY
8718 +
8719 +/* Memcsocram core registers */
8720 +typedef volatile struct sbsocramregs {
8721 + uint32 memsize;
8722 + uint32 biststat;
8723 +} sbsocramregs_t;
8724 +
8725 +#endif
8726 +
8727 +/* Them memory size is 2 to the power of the following
8728 + * base added to the contents of the memsize register.
8729 + */
8730 +#define SOCRAM_MEMSIZE_BASESHIFT 16
8731 +
8732 +#endif /* _SBSOCRAM_H */
8733 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
8734 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
8735 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-11-07 22:51:38.788726750 +0100
8736 @@ -0,0 +1,140 @@
8737 +/*
8738 + * Misc utility routines for accessing chip-specific features
8739 + * of Broadcom HNBU SiliconBackplane-based chips.
8740 + *
8741 + * Copyright 2005, Broadcom Corporation
8742 + * All Rights Reserved.
8743 + *
8744 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8745 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8746 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8747 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8748 + *
8749 + * $Id$
8750 + */
8751 +
8752 +#ifndef _sbutils_h_
8753 +#define _sbutils_h_
8754 +
8755 +/*
8756 + * Datastructure to export all chip specific common variables
8757 + * public (read-only) portion of sbutils handle returned by
8758 + * sb_attach()/sb_kattach()
8759 +*/
8760 +
8761 +struct sb_pub {
8762 +
8763 + uint bustype; /* SB_BUS, PCI_BUS */
8764 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
8765 + uint buscorerev; /* buscore rev */
8766 + uint buscoreidx; /* buscore index */
8767 + int ccrev; /* chip common core rev */
8768 + uint boardtype; /* board type */
8769 + uint boardvendor; /* board vendor */
8770 + uint chip; /* chip number */
8771 + uint chiprev; /* chip revision */
8772 + uint chippkg; /* chip package option */
8773 + uint sonicsrev; /* sonics backplane rev */
8774 +};
8775 +
8776 +typedef const struct sb_pub sb_t;
8777 +
8778 +/*
8779 + * Many of the routines below take an 'sbh' handle as their first arg.
8780 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8781 + * At any one time, the sbh is logically focused on one particular sb core
8782 + * (the "current core").
8783 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8784 + */
8785 +
8786 +/* exported externs */
8787 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
8788 +extern sb_t * BCMINIT(sb_kattach)(void);
8789 +extern void sb_detach(sb_t *sbh);
8790 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
8791 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
8792 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
8793 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
8794 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
8795 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
8796 +extern uint BCMINIT(sb_pcmciarev)(sb_t *sbh);
8797 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
8798 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
8799 +extern uint sb_bus(sb_t *sbh);
8800 +extern uint sb_buscoretype(sb_t *sbh);
8801 +extern uint sb_buscorerev(sb_t *sbh);
8802 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8803 +extern uint sb_coreid(sb_t *sbh);
8804 +extern uint sb_coreidx(sb_t *sbh);
8805 +extern uint sb_coreunit(sb_t *sbh);
8806 +extern uint sb_corevendor(sb_t *sbh);
8807 +extern uint sb_corerev(sb_t *sbh);
8808 +extern void *sb_osh(sb_t *sbh);
8809 +extern void *sb_coreregs(sb_t *sbh);
8810 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8811 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8812 +extern bool sb_iscoreup(sb_t *sbh);
8813 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8814 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8815 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
8816 +extern void sb_commit(sb_t *sbh);
8817 +extern uint32 sb_base(uint32 admatch);
8818 +extern uint32 sb_size(uint32 admatch);
8819 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
8820 +extern void sb_core_tofixup(sb_t *sbh);
8821 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8822 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8823 +extern uint32 sb_clock(sb_t *sbh);
8824 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8825 +extern void sb_pcmcia_init(sb_t *sbh);
8826 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8827 +extern void *sb_gpiosetcore(sb_t *sbh);
8828 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8829 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8830 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8831 +extern uint32 sb_gpioin(sb_t *sbh);
8832 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8833 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8834 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8835 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8836 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8837 +
8838 +extern void sb_clkctl_init(sb_t *sbh);
8839 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8840 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8841 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8842 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
8843 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
8844 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8845 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
8846 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
8847 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8848 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8849 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8850 +
8851 +
8852 +
8853 +/*
8854 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8855 +* The returned path is NULL terminated and has trailing '/'.
8856 +* Return 0 on success, nonzero otherwise.
8857 +*/
8858 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8859 +
8860 +/* clkctl xtal what flags */
8861 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8862 +#define PLL 0x2 /* main chip pll */
8863 +
8864 +/* clkctl clk mode */
8865 +#define CLK_FAST 0 /* force fast (pll) clock */
8866 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8867 +
8868 +
8869 +/* GPIO usage priorities */
8870 +#define GPIO_DRV_PRIORITY 0
8871 +#define GPIO_APP_PRIORITY 1
8872 +
8873 +/* device path */
8874 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8875 +
8876 +#endif /* _sbutils_h_ */
8877 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8878 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8879 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-11-07 21:57:07.881588000 +0100
8880 @@ -0,0 +1,36 @@
8881 +/*
8882 + * Broadcom SiliconBackplane chipcommon serial flash interface
8883 + *
8884 + * Copyright 2005, Broadcom Corporation
8885 + * All Rights Reserved.
8886 + *
8887 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8888 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8889 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8890 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8891 + *
8892 + * $Id$
8893 + */
8894 +
8895 +#ifndef _sflash_h_
8896 +#define _sflash_h_
8897 +
8898 +#include <typedefs.h>
8899 +#include <sbchipc.h>
8900 +
8901 +struct sflash {
8902 + uint blocksize; /* Block size */
8903 + uint numblocks; /* Number of blocks */
8904 + uint32 type; /* Type */
8905 + uint size; /* Total size in bytes */
8906 +};
8907 +
8908 +/* Utility functions */
8909 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8910 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8911 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8912 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8913 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8914 +extern struct sflash * sflash_init(chipcregs_t *cc);
8915 +
8916 +#endif /* _sflash_h_ */
8917 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8918 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8919 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-11-07 21:57:07.881588000 +0100
8920 @@ -0,0 +1,33 @@
8921 +/*
8922 + * TRX image file header format.
8923 + *
8924 + * Copyright 2005, Broadcom Corporation
8925 + * All Rights Reserved.
8926 + *
8927 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8928 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8929 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8930 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8931 + *
8932 + * $Id$
8933 + */
8934 +
8935 +#include <typedefs.h>
8936 +
8937 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8938 +#define TRX_VERSION 1
8939 +#define TRX_MAX_LEN 0x3A0000
8940 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8941 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8942 +#define TRX_MAX_OFFSET 3
8943 +
8944 +struct trx_header {
8945 + uint32 magic; /* "HDR0" */
8946 + uint32 len; /* Length of file including header */
8947 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8948 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8949 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8950 +};
8951 +
8952 +/* Compatibility */
8953 +typedef struct trx_header TRXHDR, *PTRXHDR;
8954 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8955 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8956 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-11-07 22:51:38.788726750 +0100
8957 @@ -0,0 +1,326 @@
8958 +/*
8959 + * Copyright 2005, Broadcom Corporation
8960 + * All Rights Reserved.
8961 + *
8962 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8963 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8964 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8965 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8966 + * $Id$
8967 + */
8968 +
8969 +#ifndef _TYPEDEFS_H_
8970 +#define _TYPEDEFS_H_
8971 +
8972 +
8973 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8974 + * typedef file "site_typedefs.h".
8975 + *
8976 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8977 + * section of this file makes inferences about the compile environment
8978 + * based on defined symbols and possibly compiler pragmas.
8979 + *
8980 + * Following these two sections is the "Default Typedefs"
8981 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8982 + * defined. This section has a default set of typedefs and a few
8983 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8984 + */
8985 +
8986 +#ifdef SITE_TYPEDEFS
8987 +
8988 +/*******************************************************************************
8989 + * Site Specific Typedefs
8990 + *******************************************************************************/
8991 +
8992 +#include "site_typedefs.h"
8993 +
8994 +#else
8995 +
8996 +/*******************************************************************************
8997 + * Inferred Typedefs
8998 + *******************************************************************************/
8999 +
9000 +/* Infer the compile environment based on preprocessor symbols and pramas.
9001 + * Override type definitions as needed, and include configuration dependent
9002 + * header files to define types.
9003 + */
9004 +
9005 +#ifdef __cplusplus
9006 +
9007 +#define TYPEDEF_BOOL
9008 +#ifndef FALSE
9009 +#define FALSE false
9010 +#endif
9011 +#ifndef TRUE
9012 +#define TRUE true
9013 +#endif
9014 +
9015 +#else /* ! __cplusplus */
9016 +
9017 +#if defined(_WIN32)
9018 +
9019 +#define TYPEDEF_BOOL
9020 +typedef unsigned char bool; /* consistent w/BOOL */
9021 +
9022 +#endif /* _WIN32 */
9023 +
9024 +#endif /* ! __cplusplus */
9025 +
9026 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
9027 +#if defined(_WIN64)
9028 +#include <basetsd.h>
9029 +#define TYPEDEF_UINTPTR
9030 +typedef ULONG_PTR uintptr;
9031 +#endif
9032 +
9033 +#ifdef _HNDRTE_
9034 +typedef long unsigned int size_t;
9035 +#endif
9036 +
9037 +#ifdef _MSC_VER /* Microsoft C */
9038 +#define TYPEDEF_INT64
9039 +#define TYPEDEF_UINT64
9040 +typedef signed __int64 int64;
9041 +typedef unsigned __int64 uint64;
9042 +#endif
9043 +
9044 +#if defined(MACOSX) && defined(KERNEL)
9045 +#define TYPEDEF_BOOL
9046 +#endif
9047 +
9048 +
9049 +#if defined(linux)
9050 +#define TYPEDEF_UINT
9051 +#define TYPEDEF_USHORT
9052 +#define TYPEDEF_ULONG
9053 +#endif
9054 +
9055 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
9056 +#define TYPEDEF_UINT
9057 +#define TYPEDEF_USHORT
9058 +#endif
9059 +
9060 +
9061 +/* Do not support the (u)int64 types with strict ansi for GNU C */
9062 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
9063 +#define TYPEDEF_INT64
9064 +#define TYPEDEF_UINT64
9065 +#endif
9066 +
9067 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
9068 + * for singned or unsigned */
9069 +#if defined(__ICL)
9070 +
9071 +#define TYPEDEF_INT64
9072 +
9073 +#if defined(__STDC__)
9074 +#define TYPEDEF_UINT64
9075 +#endif
9076 +
9077 +#endif /* __ICL */
9078 +
9079 +
9080 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
9081 +
9082 +/* pick up ushort & uint from standard types.h */
9083 +#if defined(linux) && defined(__KERNEL__)
9084 +
9085 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
9086 +
9087 +#else
9088 +
9089 +#include <sys/types.h>
9090 +
9091 +#endif
9092 +
9093 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
9094 +
9095 +#if defined(MACOSX) && defined(KERNEL)
9096 +#include <IOKit/IOTypes.h>
9097 +#endif
9098 +
9099 +
9100 +/* use the default typedefs in the next section of this file */
9101 +#define USE_TYPEDEF_DEFAULTS
9102 +
9103 +#endif /* SITE_TYPEDEFS */
9104 +
9105 +
9106 +/*******************************************************************************
9107 + * Default Typedefs
9108 + *******************************************************************************/
9109 +
9110 +#ifdef USE_TYPEDEF_DEFAULTS
9111 +#undef USE_TYPEDEF_DEFAULTS
9112 +
9113 +#ifndef TYPEDEF_BOOL
9114 +typedef /*@abstract@*/ unsigned char bool;
9115 +#endif
9116 +
9117 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
9118 +
9119 +#ifndef TYPEDEF_UCHAR
9120 +typedef unsigned char uchar;
9121 +#endif
9122 +
9123 +#ifndef TYPEDEF_USHORT
9124 +typedef unsigned short ushort;
9125 +#endif
9126 +
9127 +#ifndef TYPEDEF_UINT
9128 +typedef unsigned int uint;
9129 +#endif
9130 +
9131 +#ifndef TYPEDEF_ULONG
9132 +typedef unsigned long ulong;
9133 +#endif
9134 +
9135 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
9136 +
9137 +#ifndef TYPEDEF_UINT8
9138 +typedef unsigned char uint8;
9139 +#endif
9140 +
9141 +#ifndef TYPEDEF_UINT16
9142 +typedef unsigned short uint16;
9143 +#endif
9144 +
9145 +#ifndef TYPEDEF_UINT32
9146 +typedef unsigned int uint32;
9147 +#endif
9148 +
9149 +#ifndef TYPEDEF_UINT64
9150 +typedef unsigned long long uint64;
9151 +#endif
9152 +
9153 +#ifndef TYPEDEF_UINTPTR
9154 +typedef unsigned int uintptr;
9155 +#endif
9156 +
9157 +#ifndef TYPEDEF_INT8
9158 +typedef signed char int8;
9159 +#endif
9160 +
9161 +#ifndef TYPEDEF_INT16
9162 +typedef signed short int16;
9163 +#endif
9164 +
9165 +#ifndef TYPEDEF_INT32
9166 +typedef signed int int32;
9167 +#endif
9168 +
9169 +#ifndef TYPEDEF_INT64
9170 +typedef signed long long int64;
9171 +#endif
9172 +
9173 +/*----------------------- define float32/64, float_t -----------------------*/
9174 +
9175 +#ifndef TYPEDEF_FLOAT32
9176 +typedef float float32;
9177 +#endif
9178 +
9179 +#ifndef TYPEDEF_FLOAT64
9180 +typedef double float64;
9181 +#endif
9182 +
9183 +/*
9184 + * abstracted floating point type allows for compile time selection of
9185 + * single or double precision arithmetic. Compiling with -DFLOAT32
9186 + * selects single precision; the default is double precision.
9187 + */
9188 +
9189 +#ifndef TYPEDEF_FLOAT_T
9190 +
9191 +#if defined(FLOAT32)
9192 +typedef float32 float_t;
9193 +#else /* default to double precision floating point */
9194 +typedef float64 float_t;
9195 +#endif
9196 +
9197 +#endif /* TYPEDEF_FLOAT_T */
9198 +
9199 +/*----------------------- define macro values -----------------------------*/
9200 +
9201 +#ifndef FALSE
9202 +#define FALSE 0
9203 +#endif
9204 +
9205 +#ifndef TRUE
9206 +#define TRUE 1
9207 +#endif
9208 +
9209 +#ifndef NULL
9210 +#define NULL 0
9211 +#endif
9212 +
9213 +#ifndef OFF
9214 +#define OFF 0
9215 +#endif
9216 +
9217 +#ifndef ON
9218 +#define ON 1
9219 +#endif
9220 +
9221 +#define AUTO (-1)
9222 +
9223 +/* Reclaiming text and data :
9224 + The following macros specify special linker sections that can be reclaimed
9225 + after a system is considered 'up'.
9226 + */
9227 +#if defined(__GNUC__) && defined(BCMRECLAIM)
9228 +extern bool bcmreclaimed;
9229 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
9230 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
9231 +#define BCMINIT(_id) _id##_ini
9232 +#else
9233 +#define BCMINITDATA(_data) _data
9234 +#define BCMINITFN(_fn) _fn
9235 +#define BCMINIT(_id) _id
9236 +#define bcmreclaimed 0
9237 +#endif
9238 +
9239 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
9240 +
9241 +#ifndef PTRSZ
9242 +#define PTRSZ sizeof (char*)
9243 +#endif
9244 +
9245 +#ifndef INLINE
9246 +
9247 +#ifdef _MSC_VER
9248 +
9249 +#define INLINE __inline
9250 +
9251 +#elif __GNUC__
9252 +
9253 +#define INLINE __inline__
9254 +
9255 +#else
9256 +
9257 +#define INLINE
9258 +
9259 +#endif /* _MSC_VER */
9260 +
9261 +#endif /* INLINE */
9262 +
9263 +#undef TYPEDEF_BOOL
9264 +#undef TYPEDEF_UCHAR
9265 +#undef TYPEDEF_USHORT
9266 +#undef TYPEDEF_UINT
9267 +#undef TYPEDEF_ULONG
9268 +#undef TYPEDEF_UINT8
9269 +#undef TYPEDEF_UINT16
9270 +#undef TYPEDEF_UINT32
9271 +#undef TYPEDEF_UINT64
9272 +#undef TYPEDEF_UINTPTR
9273 +#undef TYPEDEF_INT8
9274 +#undef TYPEDEF_INT16
9275 +#undef TYPEDEF_INT32
9276 +#undef TYPEDEF_INT64
9277 +#undef TYPEDEF_FLOAT32
9278 +#undef TYPEDEF_FLOAT64
9279 +#undef TYPEDEF_FLOAT_T
9280 +
9281 +#endif /* USE_TYPEDEF_DEFAULTS */
9282 +
9283 +#endif /* _TYPEDEFS_H_ */
9284 diff -urN linux.old/arch/mips/bcm947xx/include/wlioctl.h linux.dev/arch/mips/bcm947xx/include/wlioctl.h
9285 --- linux.old/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
9286 +++ linux.dev/arch/mips/bcm947xx/include/wlioctl.h 2005-11-07 22:51:38.792727000 +0100
9287 @@ -0,0 +1,1030 @@
9288 +/*
9289 + * Custom OID/ioctl definitions for
9290 + * Broadcom 802.11abg Networking Device Driver
9291 + *
9292 + * Definitions subject to change without notice.
9293 + *
9294 + * Copyright 2005, Broadcom Corporation
9295 + * All Rights Reserved.
9296 + *
9297 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9298 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9299 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9300 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9301 + *
9302 + * $Id$
9303 + */
9304 +
9305 +#ifndef _wlioctl_h_
9306 +#define _wlioctl_h_
9307 +
9308 +#include <typedefs.h>
9309 +#include <proto/ethernet.h>
9310 +#include <proto/bcmeth.h>
9311 +#include <proto/bcmevent.h>
9312 +#include <proto/802.11.h>
9313 +
9314 +/* require default structure packing */
9315 +#if !defined(__GNUC__)
9316 +#pragma pack(push,8)
9317 +#endif
9318 +
9319 +#define WL_NUMRATES 255 /* max # of rates in a rateset */
9320 +
9321 +typedef struct wl_rateset {
9322 + uint32 count; /* # rates in this set */
9323 + uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
9324 +} wl_rateset_t;
9325 +
9326 +#define WL_CHANSPEC_CHAN_MASK 0x0fff
9327 +#define WL_CHANSPEC_BAND_MASK 0xf000
9328 +#define WL_CHANSPEC_BAND_SHIFT 12
9329 +#define WL_CHANSPEC_BAND_A 0x1000
9330 +#define WL_CHANSPEC_BAND_B 0x2000
9331 +
9332 +/*
9333 + * Per-bss information structure.
9334 + */
9335 +
9336 +#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
9337 +
9338 +typedef struct wl_bss_info {
9339 + uint32 version; /* version field */
9340 + uint32 length; /* byte length of data in this record, starting at version and including IEs */
9341 + struct ether_addr BSSID;
9342 + uint16 beacon_period; /* units are Kusec */
9343 + uint16 capability; /* Capability information */
9344 + uint8 SSID_len;
9345 + uint8 SSID[32];
9346 + struct {
9347 + uint count; /* # rates in this set */
9348 + uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
9349 + } rateset; /* supported rates */
9350 + uint8 channel; /* Channel no. */
9351 + uint16 atim_window; /* units are Kusec */
9352 + uint8 dtim_period; /* DTIM period */
9353 + int16 RSSI; /* receive signal strength (in dBm) */
9354 + int8 phy_noise; /* noise (in dBm) */
9355 + uint32 ie_length; /* byte length of Information Elements */
9356 + /* variable length Information Elements */
9357 +} wl_bss_info_t;
9358 +
9359 +typedef struct wlc_ssid {
9360 + uint32 SSID_len;
9361 + uchar SSID[32];
9362 +} wlc_ssid_t;
9363 +
9364 +typedef struct wl_scan_params {
9365 + wlc_ssid_t ssid; /* default is {0, ""} */
9366 + struct ether_addr bssid;/* default is bcast */
9367 + int8 bss_type; /* default is any, DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT */
9368 + int8 scan_type; /* -1 use default, DOT11_SCANTYPE_ACTIVE/PASSIVE */
9369 + int32 nprobes; /* -1 use default, number of probes per channel */
9370 + int32 active_time; /* -1 use default, dwell time per channel for active scanning */
9371 + int32 passive_time; /* -1 use default, dwell time per channel for passive scanning */
9372 + int32 home_time; /* -1 use default, dwell time for the home channel between channel scans */
9373 + int32 channel_num; /* 0 use default (all available channels), count of channels in channel_list */
9374 + uint16 channel_list[1]; /* list of chanspecs */
9375 +} wl_scan_params_t;
9376 +/* size of wl_scan_params not including variable length array */
9377 +#define WL_SCAN_PARAMS_FIXED_SIZE 64
9378 +
9379 +typedef struct wl_scan_results {
9380 + uint32 buflen;
9381 + uint32 version;
9382 + uint32 count;
9383 + wl_bss_info_t bss_info[1];
9384 +} wl_scan_results_t;
9385 +/* size of wl_scan_results not including variable length array */
9386 +#define WL_SCAN_RESULTS_FIXED_SIZE 12
9387 +
9388 +/* uint32 list */
9389 +typedef struct wl_uint32_list {
9390 + /* in - # of elements, out - # of entries */
9391 + uint32 count;
9392 + /* variable length uint32 list */
9393 + uint32 element[1];
9394 +} wl_uint32_list_t;
9395 +
9396 +#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
9397 +
9398 +typedef struct wl_channels_in_country {
9399 + uint32 buflen;
9400 + uint32 band;
9401 + char country_abbrev[WLC_CNTRY_BUF_SZ];
9402 + uint32 count;
9403 + uint32 channel[1];
9404 +} wl_channels_in_country_t;
9405 +
9406 +typedef struct wl_country_list {
9407 + uint32 buflen;
9408 + uint32 band_set;
9409 + uint32 band;
9410 + uint32 count;
9411 + char country_abbrev[1];
9412 +} wl_country_list_t;
9413 +
9414 +#define WL_RM_TYPE_BASIC 1
9415 +#define WL_RM_TYPE_CCA 2
9416 +#define WL_RM_TYPE_RPI 3
9417 +
9418 +#define WL_RM_FLAG_PARALLEL (1<<0)
9419 +
9420 +#define WL_RM_FLAG_LATE (1<<1)
9421 +#define WL_RM_FLAG_INCAPABLE (1<<2)
9422 +#define WL_RM_FLAG_REFUSED (1<<3)
9423 +
9424 +typedef struct wl_rm_req_elt {
9425 + int8 type;
9426 + int8 flags;
9427 + uint16 chanspec;
9428 + uint32 token; /* token for this measurement */
9429 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
9430 + uint32 tsf_l; /* TSF low 32-bits */
9431 + uint32 dur; /* TUs */
9432 +} wl_rm_req_elt_t;
9433 +
9434 +typedef struct wl_rm_req {
9435 + uint32 token; /* overall measurement set token */
9436 + uint32 count; /* number of measurement reqests */
9437 + wl_rm_req_elt_t req[1]; /* variable length block of requests */
9438 +} wl_rm_req_t;
9439 +#define WL_RM_REQ_FIXED_LEN 8
9440 +
9441 +typedef struct wl_rm_rep_elt {
9442 + int8 type;
9443 + int8 flags;
9444 + uint16 chanspec;
9445 + uint32 token; /* token for this measurement */
9446 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
9447 + uint32 tsf_l; /* TSF low 32-bits */
9448 + uint32 dur; /* TUs */
9449 + uint32 len; /* byte length of data block */
9450 + uint8 data[1]; /* variable length data block */
9451 +} wl_rm_rep_elt_t;
9452 +#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */
9453 +
9454 +#define WL_RPI_REP_BIN_NUM 8
9455 +typedef struct wl_rm_rpi_rep {
9456 + uint8 rpi[WL_RPI_REP_BIN_NUM];
9457 + int8 rpi_max[WL_RPI_REP_BIN_NUM];
9458 +} wl_rm_rpi_rep_t;
9459 +
9460 +typedef struct wl_rm_rep {
9461 + uint32 token; /* overall measurement set token */
9462 + uint32 len; /* length of measurement report block */
9463 + wl_rm_rep_elt_t rep[1]; /* variable length block of reports */
9464 +} wl_rm_rep_t;
9465 +#define WL_RM_REP_FIXED_LEN 8
9466 +
9467 +
9468 +#if defined(BCMSUP_PSK)
9469 +typedef enum sup_auth_status {
9470 + WLC_SUP_DISCONNECTED = 0,
9471 + WLC_SUP_CONNECTING,
9472 + WLC_SUP_IDREQUIRED,
9473 + WLC_SUP_AUTHENTICATING,
9474 + WLC_SUP_AUTHENTICATED,
9475 + WLC_SUP_KEYXCHANGE,
9476 + WLC_SUP_KEYED,
9477 + WLC_SUP_TIMEOUT
9478 +} sup_auth_status_t;
9479 +#endif /* BCMCCX | BCMSUP_PSK */
9480 +
9481 +/* Enumerate crypto algorithms */
9482 +#define CRYPTO_ALGO_OFF 0
9483 +#define CRYPTO_ALGO_WEP1 1
9484 +#define CRYPTO_ALGO_TKIP 2
9485 +#define CRYPTO_ALGO_WEP128 3
9486 +#define CRYPTO_ALGO_AES_CCM 4
9487 +#define CRYPTO_ALGO_AES_OCB_MSDU 5
9488 +#define CRYPTO_ALGO_AES_OCB_MPDU 6
9489 +#define CRYPTO_ALGO_NALG 7
9490 +
9491 +#define WSEC_GEN_MIC_ERROR 0x0001
9492 +#define WSEC_GEN_REPLAY 0x0002
9493 +
9494 +#define WL_SOFT_KEY (1 << 0) /* Indicates this key is using soft encrypt */
9495 +#define WL_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
9496 +#define WL_KF_RES_4 (1 << 4) /* Reserved for backward compat */
9497 +#define WL_KF_RES_5 (1 << 5) /* Reserved for backward compat */
9498 +
9499 +typedef struct wl_wsec_key {
9500 + uint32 index; /* key index */
9501 + uint32 len; /* key length */
9502 + uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
9503 + uint32 pad_1[18];
9504 + uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
9505 + uint32 flags; /* misc flags */
9506 + uint32 pad_2[2];
9507 + int pad_3;
9508 + int iv_initialized; /* has IV been initialized already? */
9509 + int pad_4;
9510 + /* Rx IV */
9511 + struct {
9512 + uint32 hi; /* upper 32 bits of IV */
9513 + uint16 lo; /* lower 16 bits of IV */
9514 + } rxiv;
9515 + uint32 pad_5[2];
9516 + struct ether_addr ea; /* per station */
9517 +} wl_wsec_key_t;
9518 +
9519 +
9520 +#define WSEC_MIN_PSK_LEN 8
9521 +#define WSEC_MAX_PSK_LEN 64
9522 +
9523 +/* Flag for key material needing passhash'ing */
9524 +#define WSEC_PASSPHRASE (1<<0)
9525 +
9526 +/* recepticle for WLC_SET_WSEC_PMK parameter */
9527 +typedef struct {
9528 + ushort key_len; /* octets in key material */
9529 + ushort flags; /* key handling qualification */
9530 + uint8 key[WSEC_MAX_PSK_LEN]; /* PMK material */
9531 +} wsec_pmk_t;
9532 +
9533 +/* wireless security bitvec */
9534 +#define WEP_ENABLED 0x0001
9535 +#define TKIP_ENABLED 0x0002
9536 +#define AES_ENABLED 0x0004
9537 +#define WSEC_SWFLAG 0x0008
9538 +#define SES_OW_ENABLED 0x0040 /* to go into transition mode without setting wep */
9539 +
9540 +/* WPA authentication mode bitvec */
9541 +#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
9542 +#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
9543 +#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
9544 +#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
9545 +/*#define WPA_AUTH_8021X 0x0020*/ /* 802.1x, reserved */
9546 +
9547 +#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
9548 +#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
9549 +
9550 +
9551 +
9552 +/* pmkid */
9553 +#define MAXPMKID 16
9554 +
9555 +typedef struct _pmkid
9556 +{
9557 + struct ether_addr BSSID;
9558 + uint8 PMKID[WPA2_PMKID_LEN];
9559 +} pmkid_t;
9560 +
9561 +typedef struct _pmkid_list
9562 +{
9563 + uint32 npmkid;
9564 + pmkid_t pmkid[1];
9565 +} pmkid_list_t;
9566 +
9567 +typedef struct _pmkid_cand {
9568 + struct ether_addr BSSID;
9569 + uint8 preauth;
9570 +} pmkid_cand_t;
9571 +
9572 +typedef struct _pmkid_cand_list {
9573 + uint32 npmkid_cand;
9574 + pmkid_cand_t pmkid_cand[1];
9575 +} pmkid_cand_list_t;
9576 +
9577 +
9578 +typedef struct wl_led_info {
9579 + uint32 index; /* led index */
9580 + uint32 behavior;
9581 + bool activehi;
9582 +} wl_led_info_t;
9583 +
9584 +typedef struct wlc_assoc_info {
9585 + uint32 req_len;
9586 + uint32 resp_len;
9587 + uint32 flags;
9588 + struct dot11_assoc_req req;
9589 + struct ether_addr reassoc_bssid; /* used in reassoc's */
9590 + struct dot11_assoc_resp resp;
9591 +} wl_assoc_info_t;
9592 +/* flags */
9593 +#define WLC_ASSOC_REQ_IS_REASSOC 0x01 /* assoc req was actually a reassoc */
9594 +/* srom read/write struct passed through ioctl */
9595 +typedef struct {
9596 + uint byteoff; /* byte offset */
9597 + uint nbytes; /* number of bytes */
9598 + uint16 buf[1];
9599 +} srom_rw_t;
9600 +
9601 +/* R_REG and W_REG struct passed through ioctl */
9602 +typedef struct {
9603 + uint32 byteoff; /* byte offset of the field in d11regs_t */
9604 + uint32 val; /* read/write value of the field */
9605 + uint32 size; /* sizeof the field */
9606 + uint band; /* band (optional) */
9607 +} rw_reg_t;
9608 +
9609 +/* Structure used by GET/SET_ATTEN ioctls */
9610 +typedef struct {
9611 + uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
9612 + uint16 bb; /* Baseband attenuation */
9613 + uint16 radio; /* Radio attenuation */
9614 + uint16 txctl1; /* Radio TX_CTL1 value */
9615 +} atten_t;
9616 +
9617 +/* Used to get specific STA parameters */
9618 +typedef struct {
9619 + uint32 val;
9620 + struct ether_addr ea;
9621 +} scb_val_t;
9622 +
9623 +
9624 +/* Event data type */
9625 +typedef struct wlc_event {
9626 + wl_event_msg_t event; /* encapsulated event */
9627 + struct ether_addr *addr; /* used to keep a trace of the potential present of
9628 + an address in wlc_event_msg_t */
9629 + void *data; /* used to hang additional data on an event */
9630 + struct wlc_event *next; /* enables ordered list of pending events */
9631 +} wlc_event_t;
9632 +
9633 +#define BCM_MAC_STATUS_INDICATION (0x40010200L)
9634 +
9635 +typedef struct {
9636 + uint16 ver; /* version of this struct */
9637 + uint16 len; /* length in bytes of this structure */
9638 + uint16 cap; /* sta's advertized capabilities */
9639 + uint32 flags; /* flags defined below */
9640 + uint32 idle; /* time since data pkt rx'd from sta */
9641 + struct ether_addr ea; /* Station address */
9642 + wl_rateset_t rateset; /* rateset in use */
9643 + uint32 in; /* seconds elapsed since associated */
9644 + uint32 listen_interval_inms; /* Min Listen interval in ms for this STA*/
9645 +} sta_info_t;
9646 +
9647 +#define WL_STA_VER 2
9648 +
9649 +/* flags fields */
9650 +#define WL_STA_BRCM 0x01
9651 +#define WL_STA_WME 0x02
9652 +#define WL_STA_ABCAP 0x04
9653 +#define WL_STA_AUTHE 0x08
9654 +#define WL_STA_ASSOC 0x10
9655 +#define WL_STA_AUTHO 0x20
9656 +#define WL_STA_WDS 0x40
9657 +#define WL_WDS_LINKUP 0x80
9658 +
9659 +
9660 +/*
9661 + * Country locale determines which channels are available to us.
9662 + */
9663 +typedef enum _wlc_locale {
9664 + WLC_WW = 0, /* Worldwide */
9665 + WLC_THA, /* Thailand */
9666 + WLC_ISR, /* Israel */
9667 + WLC_JDN, /* Jordan */
9668 + WLC_PRC, /* China */
9669 + WLC_JPN, /* Japan */
9670 + WLC_FCC, /* USA */
9671 + WLC_EUR, /* Europe */
9672 + WLC_USL, /* US Low Band only */
9673 + WLC_JPH, /* Japan High Band only */
9674 + WLC_ALL, /* All the channels in this band */
9675 + WLC_11D, /* Represents locale recieved by 11d beacons */
9676 + WLC_LAST_LOCALE,
9677 + WLC_UNDEFINED_LOCALE = 0xf
9678 +} wlc_locale_t;
9679 +
9680 +/* channel encoding */
9681 +typedef struct channel_info {
9682 + int hw_channel;
9683 + int target_channel;
9684 + int scan_channel;
9685 +} channel_info_t;
9686 +
9687 +/* For ioctls that take a list of MAC addresses */
9688 +struct maclist {
9689 + uint count; /* number of MAC addresses */
9690 + struct ether_addr ea[1]; /* variable length array of MAC addresses */
9691 +};
9692 +
9693 +/* get pkt count struct passed through ioctl */
9694 +typedef struct get_pktcnt {
9695 + uint rx_good_pkt;
9696 + uint rx_bad_pkt;
9697 + uint tx_good_pkt;
9698 + uint tx_bad_pkt;
9699 +} get_pktcnt_t;
9700 +
9701 +/* Linux network driver ioctl encoding */
9702 +typedef struct wl_ioctl {
9703 + uint cmd; /* common ioctl definition */
9704 + void *buf; /* pointer to user buffer */
9705 + uint len; /* length of user buffer */
9706 + bool set; /* get or set request (optional) */
9707 + uint used; /* bytes read or written (optional) */
9708 + uint needed; /* bytes needed (optional) */
9709 +} wl_ioctl_t;
9710 +
9711 +/*
9712 + * Structure for passing hardware and software
9713 + * revision info up from the driver.
9714 + */
9715 +typedef struct wlc_rev_info {
9716 + uint vendorid; /* PCI vendor id */
9717 + uint deviceid; /* device id of chip */
9718 + uint radiorev; /* radio revision */
9719 + uint chiprev; /* chip revision */
9720 + uint corerev; /* core revision */
9721 + uint boardid; /* board identifier (usu. PCI sub-device id) */
9722 + uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
9723 + uint boardrev; /* board revision */
9724 + uint driverrev; /* driver version */
9725 + uint ucoderev; /* microcode version */
9726 + uint bus; /* bus type */
9727 + uint chipnum; /* chip number */
9728 +} wlc_rev_info_t;
9729 +
9730 +#define WL_BRAND_MAX 10
9731 +typedef struct wl_instance_info {
9732 + uint instance;
9733 + char brand[WL_BRAND_MAX];
9734 +} wl_instance_info_t;
9735 +
9736 +/* check this magic number */
9737 +#define WLC_IOCTL_MAGIC 0x14e46c77
9738 +
9739 +/* bump this number if you change the ioctl interface */
9740 +#define WLC_IOCTL_VERSION 1
9741 +
9742 +#define WLC_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
9743 +#define WLC_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
9744 +
9745 +/* common ioctl definitions */
9746 +#define WLC_GET_MAGIC 0
9747 +#define WLC_GET_VERSION 1
9748 +#define WLC_UP 2
9749 +#define WLC_DOWN 3
9750 +#define WLC_DUMP 6
9751 +#define WLC_GET_MSGLEVEL 7
9752 +#define WLC_SET_MSGLEVEL 8
9753 +#define WLC_GET_PROMISC 9
9754 +#define WLC_SET_PROMISC 10
9755 +#define WLC_GET_RATE 12
9756 +/* #define WLC_SET_RATE 13 */ /* no longer supported */
9757 +#define WLC_GET_INSTANCE 14
9758 +/* #define WLC_GET_FRAG 15 */ /* no longer supported */
9759 +/* #define WLC_SET_FRAG 16 */ /* no longer supported */
9760 +/* #define WLC_GET_RTS 17 */ /* no longer supported */
9761 +/* #define WLC_SET_RTS 18 */ /* no longer supported */
9762 +#define WLC_GET_INFRA 19
9763 +#define WLC_SET_INFRA 20
9764 +#define WLC_GET_AUTH 21
9765 +#define WLC_SET_AUTH 22
9766 +#define WLC_GET_BSSID 23
9767 +#define WLC_SET_BSSID 24
9768 +#define WLC_GET_SSID 25
9769 +#define WLC_SET_SSID 26
9770 +#define WLC_RESTART 27
9771 +#define WLC_GET_CHANNEL 29
9772 +#define WLC_SET_CHANNEL 30
9773 +#define WLC_GET_SRL 31
9774 +#define WLC_SET_SRL 32
9775 +#define WLC_GET_LRL 33
9776 +#define WLC_SET_LRL 34
9777 +#define WLC_GET_PLCPHDR 35
9778 +#define WLC_SET_PLCPHDR 36
9779 +#define WLC_GET_RADIO 37
9780 +#define WLC_SET_RADIO 38
9781 +#define WLC_GET_PHYTYPE 39
9782 +/* #define WLC_GET_WEP 42 */ /* no longer supported */
9783 +/* #define WLC_SET_WEP 43 */ /* no longer supported */
9784 +#define WLC_GET_KEY 44
9785 +#define WLC_SET_KEY 45
9786 +#define WLC_GET_REGULATORY 46
9787 +#define WLC_SET_REGULATORY 47
9788 +#define WLC_SCAN 50
9789 +#define WLC_SCAN_RESULTS 51
9790 +#define WLC_DISASSOC 52
9791 +#define WLC_REASSOC 53
9792 +#define WLC_GET_ROAM_TRIGGER 54
9793 +#define WLC_SET_ROAM_TRIGGER 55
9794 +#define WLC_GET_TXANT 61
9795 +#define WLC_SET_TXANT 62
9796 +#define WLC_GET_ANTDIV 63
9797 +#define WLC_SET_ANTDIV 64
9798 +/* #define WLC_GET_TXPWR 65 */ /* no longer supported */
9799 +/* #define WLC_SET_TXPWR 66 */ /* no longer supported */
9800 +#define WLC_GET_CLOSED 67
9801 +#define WLC_SET_CLOSED 68
9802 +#define WLC_GET_MACLIST 69
9803 +#define WLC_SET_MACLIST 70
9804 +#define WLC_GET_RATESET 71
9805 +#define WLC_SET_RATESET 72
9806 +#define WLC_GET_LOCALE 73
9807 +#define WLC_LONGTRAIN 74
9808 +#define WLC_GET_BCNPRD 75
9809 +#define WLC_SET_BCNPRD 76
9810 +#define WLC_GET_DTIMPRD 77
9811 +#define WLC_SET_DTIMPRD 78
9812 +#define WLC_GET_SROM 79
9813 +#define WLC_SET_SROM 80
9814 +#define WLC_GET_WEP_RESTRICT 81
9815 +#define WLC_SET_WEP_RESTRICT 82
9816 +#define WLC_GET_COUNTRY 83
9817 +#define WLC_SET_COUNTRY 84
9818 +#define WLC_GET_REVINFO 98
9819 +#define WLC_GET_MACMODE 105
9820 +#define WLC_SET_MACMODE 106
9821 +#define WLC_GET_GMODE 109
9822 +#define WLC_SET_GMODE 110
9823 +#define WLC_GET_CURR_RATESET 114 /* current rateset */
9824 +#define WLC_GET_SCANSUPPRESS 115
9825 +#define WLC_SET_SCANSUPPRESS 116
9826 +#define WLC_GET_AP 117
9827 +#define WLC_SET_AP 118
9828 +#define WLC_GET_EAP_RESTRICT 119
9829 +#define WLC_SET_EAP_RESTRICT 120
9830 +#define WLC_GET_WDSLIST 123
9831 +#define WLC_SET_WDSLIST 124
9832 +#define WLC_GET_RSSI 127
9833 +#define WLC_GET_WSEC 133
9834 +#define WLC_SET_WSEC 134
9835 +#define WLC_GET_BSS_INFO 136
9836 +#define WLC_GET_LAZYWDS 138
9837 +#define WLC_SET_LAZYWDS 139
9838 +#define WLC_GET_BANDLIST 140
9839 +#define WLC_GET_BAND 141
9840 +#define WLC_SET_BAND 142
9841 +#define WLC_GET_SHORTSLOT 144
9842 +#define WLC_GET_SHORTSLOT_OVERRIDE 145
9843 +#define WLC_SET_SHORTSLOT_OVERRIDE 146
9844 +#define WLC_GET_SHORTSLOT_RESTRICT 147
9845 +#define WLC_SET_SHORTSLOT_RESTRICT 148
9846 +#define WLC_GET_GMODE_PROTECTION 149
9847 +#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
9848 +#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
9849 +#define WLC_UPGRADE 152
9850 +/* #define WLC_GET_MRATE 153 */ /* no longer supported */
9851 +/* #define WLC_SET_MRATE 154 */ /* no longer supported */
9852 +#define WLC_GET_ASSOCLIST 159
9853 +#define WLC_GET_CLK 160
9854 +#define WLC_SET_CLK 161
9855 +#define WLC_GET_UP 162
9856 +#define WLC_OUT 163
9857 +#define WLC_GET_WPA_AUTH 164
9858 +#define WLC_SET_WPA_AUTH 165
9859 +#define WLC_GET_GMODE_PROTECTION_CONTROL 178
9860 +#define WLC_SET_GMODE_PROTECTION_CONTROL 179
9861 +#define WLC_GET_PHYLIST 180
9862 +#define WLC_GET_KEY_SEQ 183
9863 +#define WLC_GET_GMODE_PROTECTION_CTS 198
9864 +#define WLC_SET_GMODE_PROTECTION_CTS 199
9865 +#define WLC_GET_PIOMODE 203
9866 +#define WLC_SET_PIOMODE 204
9867 +#define WLC_SET_LED 209
9868 +#define WLC_GET_LED 210
9869 +#define WLC_GET_CHANNEL_SEL 215
9870 +#define WLC_START_CHANNEL_SEL 216
9871 +#define WLC_GET_VALID_CHANNELS 217
9872 +#define WLC_GET_FAKEFRAG 218
9873 +#define WLC_SET_FAKEFRAG 219
9874 +#define WLC_GET_WET 230
9875 +#define WLC_SET_WET 231
9876 +#define WLC_GET_KEY_PRIMARY 235
9877 +#define WLC_SET_KEY_PRIMARY 236
9878 +#define WLC_GET_RADAR 242
9879 +#define WLC_SET_RADAR 243
9880 +#define WLC_SET_SPECT_MANAGMENT 244
9881 +#define WLC_GET_SPECT_MANAGMENT 245
9882 +#define WLC_WDS_GET_REMOTE_HWADDR 246 /* currently handled in wl_linux.c/wl_vx.c */
9883 +#define WLC_SET_CS_SCAN_TIMER 248
9884 +#define WLC_GET_CS_SCAN_TIMER 249
9885 +#define WLC_SEND_PWR_CONSTRAINT 254
9886 +#define WLC_CURRENT_PWR 256
9887 +#define WLC_GET_CHANNELS_IN_COUNTRY 260
9888 +#define WLC_GET_COUNTRY_LIST 261
9889 +#define WLC_GET_VAR 262 /* get value of named variable */
9890 +#define WLC_SET_VAR 263 /* set named variable to value */
9891 +#define WLC_NVRAM_GET 264
9892 +#define WLC_NVRAM_SET 265
9893 +#define WLC_SET_WSEC_PMK 268
9894 +#define WLC_GET_AUTH_MODE 269
9895 +#define WLC_SET_AUTH_MODE 270
9896 +#define WLC_NDCONFIG_ITEM 273 /* currently handled in wl_oid.c */
9897 +#define WLC_NVOTPW 274
9898 +/* #define WLC_OTPW 275 */ /* no longer supported */
9899 +#define WLC_SET_LOCALE 278
9900 +#define WLC_LAST 279 /* do not change - use get_var/set_var */
9901 +
9902 +/*
9903 + * Minor kludge alert:
9904 + * Duplicate a few definitions that irelay requires from epiioctl.h here
9905 + * so caller doesn't have to include this file and epiioctl.h .
9906 + * If this grows any more, it would be time to move these irelay-specific
9907 + * definitions out of the epiioctl.h and into a separate driver common file.
9908 + */
9909 +#ifndef EPICTRL_COOKIE
9910 +#define EPICTRL_COOKIE 0xABADCEDE
9911 +#endif
9912 +
9913 +/* vx wlc ioctl's offset */
9914 +#define CMN_IOCTL_OFF 0x180
9915 +
9916 +/*
9917 + * custom OID support
9918 + *
9919 + * 0xFF - implementation specific OID
9920 + * 0xE4 - first byte of Broadcom PCI vendor ID
9921 + * 0x14 - second byte of Broadcom PCI vendor ID
9922 + * 0xXX - the custom OID number
9923 + */
9924 +
9925 +/* begin 0x1f values beyond the start of the ET driver range. */
9926 +#define WL_OID_BASE 0xFFE41420
9927 +
9928 +/* NDIS overrides */
9929 +#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
9930 +#define OID_WL_NDCONFIG_ITEM (WL_OID_BASE + WLC_NDCONFIG_ITEM)
9931 +
9932 +#define WL_DECRYPT_STATUS_SUCCESS 1
9933 +#define WL_DECRYPT_STATUS_FAILURE 2
9934 +#define WL_DECRYPT_STATUS_UNKNOWN 3
9935 +
9936 +/* allows user-mode app to poll the status of USB image upgrade */
9937 +#define WLC_UPGRADE_SUCCESS 0
9938 +#define WLC_UPGRADE_PENDING 1
9939 +
9940 +#ifdef CONFIG_USBRNDIS_RETAIL
9941 +/* struct passed in for WLC_NDCONFIG_ITEM */
9942 +typedef struct {
9943 + char *name;
9944 + void *param;
9945 +} ndconfig_item_t;
9946 +#endif
9947 +
9948 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
9949 +#define WL_RADIO_SW_DISABLE (1<<0)
9950 +#define WL_RADIO_HW_DISABLE (1<<1)
9951 +#define WL_RADIO_MPC_DISABLE (1<<2)
9952 +#define WL_RADIO_COUNTRY_DISABLE (1<<3) /* some countries don't support any 802.11 channel */
9953 +
9954 +/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
9955 +#define WL_TXPWR_OVERRIDE (1<<31)
9956 +
9957 +/* "diag" iovar argument and error code */
9958 +#define WL_DIAG_INTERRUPT 1 /* d11 loopback interrupt test */
9959 +#define WL_DIAG_MEMORY 3 /* d11 memory test */
9960 +#define WL_DIAG_LED 4 /* LED test */
9961 +#define WL_DIAG_REG 5 /* d11/phy register test */
9962 +#define WL_DIAG_SROM 6 /* srom read/crc test */
9963 +#define WL_DIAG_DMA 7 /* DMA test */
9964 +
9965 +#define WL_DIAGERR_SUCCESS 0
9966 +#define WL_DIAGERR_FAIL_TO_RUN 1 /* unable to run requested diag */
9967 +#define WL_DIAGERR_NOT_SUPPORTED 2 /* diag requested is not supported */
9968 +#define WL_DIAGERR_INTERRUPT_FAIL 3 /* loopback interrupt test failed */
9969 +#define WL_DIAGERR_LOOPBACK_FAIL 4 /* loopback data test failed */
9970 +#define WL_DIAGERR_SROM_FAIL 5 /* srom read failed */
9971 +#define WL_DIAGERR_SROM_BADCRC 6 /* srom crc failed */
9972 +#define WL_DIAGERR_REG_FAIL 7 /* d11/phy register test failed */
9973 +#define WL_DIAGERR_MEMORY_FAIL 8 /* d11 memory test failed */
9974 +#define WL_DIAGERR_NOMEM 9 /* diag test failed due to no memory */
9975 +#define WL_DIAGERR_DMA_FAIL 10 /* DMA test failed */
9976 +
9977 +/* Bus types */
9978 +#define WL_SB_BUS 0 /* Silicon Backplane */
9979 +#define WL_PCI_BUS 1 /* PCI target */
9980 +#define WL_PCMCIA_BUS 2 /* PCMCIA target */
9981 +
9982 +/* band types */
9983 +#define WLC_BAND_AUTO 0 /* auto-select */
9984 +#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
9985 +#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
9986 +#define WLC_BAND_ALL 3 /* all bands */
9987 +
9988 +/* phy types (returned by WLC_GET_PHYTPE) */
9989 +#define WLC_PHY_TYPE_A 0
9990 +#define WLC_PHY_TYPE_B 1
9991 +#define WLC_PHY_TYPE_G 2
9992 +#define WLC_PHY_TYPE_NULL 0xf
9993 +
9994 +/* MAC list modes */
9995 +#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
9996 +#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
9997 +#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
9998 +
9999 +/*
10000 + *
10001 + */
10002 +#define GMODE_LEGACY_B 0
10003 +#define GMODE_AUTO 1
10004 +#define GMODE_ONLY 2
10005 +#define GMODE_B_DEFERRED 3
10006 +#define GMODE_PERFORMANCE 4
10007 +#define GMODE_LRS 5
10008 +#define GMODE_MAX 6
10009 +
10010 +/* values for PLCPHdr_override */
10011 +#define WLC_PLCP_AUTO -1
10012 +#define WLC_PLCP_SHORT 0
10013 +#define WLC_PLCP_LONG 1
10014 +
10015 +/* values for g_protection_override */
10016 +#define WLC_G_PROTECTION_AUTO -1
10017 +#define WLC_G_PROTECTION_OFF 0
10018 +#define WLC_G_PROTECTION_ON 1
10019 +
10020 +/* values for g_protection_control */
10021 +#define WLC_G_PROTECTION_CTL_OFF 0
10022 +#define WLC_G_PROTECTION_CTL_LOCAL 1
10023 +#define WLC_G_PROTECTION_CTL_OVERLAP 2
10024 +
10025 +/* Values for PM */
10026 +#define PM_OFF 0
10027 +#define PM_MAX 1
10028 +#define PM_FAST 2
10029 +
10030 +
10031 +
10032 +typedef struct {
10033 + int npulses; /* required number of pulses at n * t_int */
10034 + int ncontig; /* required number of pulses at t_int */
10035 + int min_pw; /* minimum pulse width (20 MHz clocks) */
10036 + int max_pw; /* maximum pulse width (20 MHz clocks) */
10037 + uint16 thresh0; /* Radar detection, thresh 0 */
10038 + uint16 thresh1; /* Radar detection, thresh 1 */
10039 +} wl_radar_args_t;
10040 +
10041 +/* radar iovar SET defines */
10042 +#define WL_RADRA_DETECTOR_OFF 0 /* radar dector off */
10043 +#define WL_RADAR_DETECTOR_ON 1 /* radar detector on */
10044 +#define WL_RADAR_SIMULATED 2 /* force radar detector to declare detection once */
10045 +
10046 +/* dfs_status iovar-related defines */
10047 +
10048 +/* cac - channel availability check,
10049 + * ism - in-service monitoring
10050 + * csa - channel switching anouncement
10051 + */
10052 +
10053 +/* cac state values */
10054 +#define WL_DFS_CACSTATE_IDLE 0 /* state for operating in non-radar channel */
10055 +#define WL_DFS_CACSTATE_PREISM_CAC 1 /* CAC in progress */
10056 +#define WL_DFS_CACSTATE_ISM 2 /* ISM in progress */
10057 +#define WL_DFS_CACSTATE_CSA 3 /* csa */
10058 +#define WL_DFS_CACSTATE_POSTISM_CAC 4 /* ISM CAC */
10059 +#define WL_DFS_CACSTATE_PREISM_OOC 5 /* PREISM OOC */
10060 +#define WL_DFS_CACSTATE_POSTISM_OOC 6 /* POSTISM OOC */
10061 +#define WL_DFS_CACSTATES 7 /* this many states exist */
10062 +
10063 +/* data structure used in 'dfs_status' wl interface, which is used to query dfs status */
10064 +typedef struct {
10065 + uint state; /* noted by WL_DFS_CACSTATE_XX. */
10066 + uint duration; /* time spent in ms in state. */
10067 + /* as dfs enters ISM state, it removes the operational channel from quiet channel list
10068 + * and notes the channel in channel_cleared. set to 0 if no channel is cleared
10069 + */
10070 + uint channel_cleared;
10071 +} wl_dfs_status_t;
10072 +
10073 +#define NUM_PWRCTRL_RATES 12
10074 +
10075 +
10076 +/* 802.11h enforcement levels */
10077 +#define SPECT_MNGMT_OFF 0 /* 11h disabled */
10078 +#define SPECT_MNGMT_LOOSE 1 /* allow scan lists to contain non-11h AP */
10079 +#define SPECT_MNGMT_STRICT 2 /* prune out non-11h APs from scan list */
10080 +#define SPECT_MNGMT_11D 3 /* switch to 802.11D mode */
10081 +
10082 +#define WL_CHAN_VALID_HW (1 << 0) /* valid with current HW */
10083 +#define WL_CHAN_VALID_SW (1 << 1) /* valid with current country setting */
10084 +#define WL_CHAN_BAND_A (1 << 2) /* A-band channel */
10085 +#define WL_CHAN_RADAR (1 << 3) /* radar sensitive channel */
10086 +#define WL_CHAN_INACTIVE (1 << 4) /* temporarily out of service due to radar */
10087 +#define WL_CHAN_RADAR_PASSIVE (1 << 5) /* radar channel is in passive mode */
10088 +
10089 +#define WL_MPC_VAL 0x00400000
10090 +#define WL_APSTA_VAL 0x00800000
10091 +#define WL_DFS_VAL 0x01000000
10092 +
10093 +/* max # of leds supported by GPIO (gpio pin# == led index#) */
10094 +#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
10095 +
10096 +/* led per-pin behaviors */
10097 +#define WL_LED_OFF 0 /* always off */
10098 +#define WL_LED_ON 1 /* always on */
10099 +#define WL_LED_ACTIVITY 2 /* activity */
10100 +#define WL_LED_RADIO 3 /* radio enabled */
10101 +#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
10102 +#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
10103 +#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
10104 +#define WL_LED_WI1 7
10105 +#define WL_LED_WI2 8
10106 +#define WL_LED_WI3 9
10107 +#define WL_LED_ASSOC 10 /* associated state indicator */
10108 +#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
10109 +#define WL_LED_NUMBEHAVIOR 12
10110 +
10111 +/* led behavior numeric value format */
10112 +#define WL_LED_BEH_MASK 0x7f /* behavior mask */
10113 +#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
10114 +
10115 +
10116 +/* WDS link local endpoint WPA role */
10117 +#define WL_WDS_WPA_ROLE_AUTH 0 /* authenticator */
10118 +#define WL_WDS_WPA_ROLE_SUP 1 /* supplicant */
10119 +#define WL_WDS_WPA_ROLE_AUTO 255 /* auto, based on mac addr value */
10120 +
10121 +/* number of bytes needed to define a 128-bit mask for MAC event reporting */
10122 +#define WL_EVENTING_MASK_LEN 16
10123 +
10124 +/* Structures and constants used for "vndr_ie" IOVar interface */
10125 +#define VNDR_IE_CMD_LEN 4 /* length of the set command string: "add", "del" (+ NULL) */
10126 +
10127 +/* 802.11 Mgmt Packet flags */
10128 +#define VNDR_IE_BEACON_FLAG 0x1
10129 +#define VNDR_IE_PRBRSP_FLAG 0x2
10130 +#define VNDR_IE_ASSOCRSP_FLAG 0x4
10131 +#define VNDR_IE_AUTHRSP_FLAG 0x8
10132 +
10133 +typedef struct {
10134 + uint32 pktflag; /* bitmask indicating which packet(s) contain this IE */
10135 + vndr_ie_t vndr_ie_data; /* vendor IE data */
10136 +} vndr_ie_info_t;
10137 +
10138 +typedef struct {
10139 + int iecount; /* number of entries in the vndr_ie_list[] array */
10140 + vndr_ie_info_t vndr_ie_list[1]; /* variable size list of vndr_ie_info_t structs */
10141 +} vndr_ie_buf_t;
10142 +
10143 +typedef struct {
10144 + char cmd[VNDR_IE_CMD_LEN]; /* vndr_ie IOVar set command : "add", "del" + NULL */
10145 + vndr_ie_buf_t vndr_ie_buffer; /* buffer containing Vendor IE list information */
10146 +} vndr_ie_setbuf_t;
10147 +
10148 +/* join target preference types */
10149 +#define WL_JOIN_PREF_RSSI 1 /* by RSSI, mandatory */
10150 +#define WL_JOIN_PREF_WPA 2 /* by akm and ciphers, optional, RSN and WPA as values */
10151 +#define WL_JOIN_PREF_BAND 3 /* by 802.11 band, optional, WLC_BAND_XXXX as values */
10152 +
10153 +/* band preference */
10154 +#define WLJP_BAND_ASSOC_PREF 255 /* use assoc preference settings */
10155 + /* others use WLC_BAND_XXXX as values */
10156 +
10157 +/* any multicast cipher suite */
10158 +#define WL_WPA_ACP_MCS_ANY "\x00\x00\x00\x00"
10159 +
10160 +#if !defined(__GNUC__)
10161 +#pragma pack(pop)
10162 +#endif
10163 +
10164 +#define NFIFO 6 /* # tx/rx fifopairs */
10165 +
10166 +#define WL_CNT_T_VERSION 1 /* current version of wl_cnt_t struct */
10167 +
10168 +typedef struct {
10169 + uint16 version; /* see definition of WL_CNT_T_VERSION */
10170 + uint16 length; /* length of entire structure */
10171 +
10172 + /* transmit stat counters */
10173 + uint32 txframe; /* tx data frames */
10174 + uint32 txbyte; /* tx data bytes */
10175 + uint32 txretrans; /* tx mac retransmits */
10176 + uint32 txerror; /* tx data errors */
10177 + uint32 txctl; /* tx management frames */
10178 + uint32 txprshort; /* tx short preamble frames */
10179 + uint32 txserr; /* tx status errors */
10180 + uint32 txnobuf; /* tx out of buffers errors */
10181 + uint32 txnoassoc; /* tx discard because we're not associated */
10182 + uint32 txrunt; /* tx runt frames */
10183 + uint32 txchit; /* tx header cache hit (fastpath) */
10184 + uint32 txcmiss; /* tx header cache miss (slowpath) */
10185 +
10186 + /* transmit chip error counters */
10187 + uint32 txuflo; /* tx fifo underflows */
10188 + uint32 txphyerr; /* tx phy errors (indicated in tx status) */
10189 + uint32 txphycrs;
10190 +
10191 + /* receive stat counters */
10192 + uint32 rxframe; /* rx data frames */
10193 + uint32 rxbyte; /* rx data bytes */
10194 + uint32 rxerror; /* rx data errors */
10195 + uint32 rxctl; /* rx management frames */
10196 + uint32 rxnobuf; /* rx out of buffers errors */
10197 + uint32 rxnondata; /* rx non data frames in the data channel errors */
10198 + uint32 rxbadds; /* rx bad DS errors */
10199 + uint32 rxbadcm; /* rx bad control or management frames */
10200 + uint32 rxfragerr; /* rx fragmentation errors */
10201 + uint32 rxrunt; /* rx runt frames */
10202 + uint32 rxgiant; /* rx giant frames */
10203 + uint32 rxnoscb; /* rx no scb error */
10204 + uint32 rxbadproto; /* rx invalid frames */
10205 + uint32 rxbadsrcmac; /* rx frames with Invalid Src Mac*/
10206 + uint32 rxbadda; /* rx frames tossed for invalid da */
10207 + uint32 rxfilter; /* rx frames filtered out */
10208 +
10209 + /* receive chip error counters */
10210 + uint32 rxoflo; /* rx fifo overflow errors */
10211 + uint32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */
10212 +
10213 + uint32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */
10214 + uint32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */
10215 + uint32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */
10216 +
10217 + /* misc counters */
10218 + uint32 dmade; /* tx/rx dma descriptor errors */
10219 + uint32 dmada; /* tx/rx dma data errors */
10220 + uint32 dmape; /* tx/rx dma descriptor protocol errors */
10221 + uint32 reset; /* reset count */
10222 + uint32 tbtt; /* cnts the TBTT int's */
10223 + uint32 txdmawar;
10224 +
10225 + /* MAC counters: 32-bit version of d11.h's macstat_t */
10226 + uint32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS,
10227 + Control Management (includes retransmissions) */
10228 + uint32 txrtsfrm; /* number of RTS sent out by the MAC */
10229 + uint32 txctsfrm; /* number of CTS sent out by the MAC */
10230 + uint32 txackfrm; /* number of ACK frames sent out */
10231 + uint32 txdnlfrm; /* Not used */
10232 + uint32 txbcnfrm; /* beacons transmitted */
10233 + uint32 txfunfl[8]; /* per-fifo tx underflows */
10234 + uint32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS or BCN) */
10235 + uint32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for
10236 + driver enqueued frames*/
10237 + uint32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */
10238 + uint32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */
10239 + uint32 rxinvmachdr; /* Either the protocol version != 0 or frame type not
10240 + data/control/management*/
10241 + uint32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */
10242 + uint32 rxbadplcp; /* parity check of the PLCP header failed */
10243 + uint32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */
10244 + uint32 rxstrt; /* Number of received frames with a good PLCP (i.e. passing parity check) */
10245 + uint32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
10246 + uint32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
10247 + uint32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */
10248 + uint32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */
10249 + uint32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS)*/
10250 + uint32 rxackucast; /* number of ucast ACKS received (good FCS)*/
10251 + uint32 rxdfrmocast; /* number of received DATA frames with good FCS and not matching RA */
10252 + uint32 rxmfrmocast; /* number of received MGMT frames with good FCS and not matching RA */
10253 + uint32 rxcfrmocast; /* number of received CNTRL frame with good FCS and not matching RA */
10254 + uint32 rxrtsocast; /* number of received RTS not addressed to the MAC */
10255 + uint32 rxctsocast; /* number of received CTS not addressed to the MAC */
10256 + uint32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */
10257 + uint32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */
10258 + uint32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC (unlikely
10259 + to see these) */
10260 + uint32 rxbeaconmbss; /* beacons received from member of BSS */
10261 + uint32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from other BSS (WDS FRAME) */
10262 + uint32 rxbeaconobss; /* beacons received from other BSS */
10263 + uint32 rxrsptmout; /* Number of response timeouts for transmitted frames expecting a
10264 + response */
10265 + uint32 bcntxcancl; /* transmit beacons cancelled due to receipt of beacon (IBSS) */
10266 + uint32 rxf0ovfl; /* Number of receive fifo 0 overflows */
10267 + uint32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */
10268 + uint32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */
10269 + uint32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */
10270 + uint32 pmqovfl; /* Number of PMQ overflows */
10271 + uint32 rxcgprqfrm; /* Number of received Probe requests that made it into the PRQ fifo */
10272 + uint32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */
10273 + uint32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did not get ACK */
10274 + uint32 txcgprssuc; /* Tx Probe Rresponse Success (ACK was received) */
10275 + uint32 prs_timeout; /* Number of probe requests that were dropped from the PRQ fifo because
10276 + a probe response could not be sent out within the time limit defined
10277 + in M_PRS_MAXTIME */
10278 + uint32 rxnack; /* Number of NACKS received (Afterburner) */
10279 + uint32 frmscons; /* Number of frames completed without transmission because of an
10280 + Afterburner re-queue */
10281 + uint32 txnack; /* Number of NACKs transmtitted (Afterburner) */
10282 + uint32 txglitch_nack; /* obsolete */
10283 + uint32 txburst; /* obsolete */
10284 + uint32 rxburst; /* obsolete */
10285 +
10286 + /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
10287 + uint32 txfrag; /* dot11TransmittedFragmentCount */
10288 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
10289 + uint32 txfail; /* dot11FailedCount */
10290 + uint32 txretry; /* dot11RetryCount */
10291 + uint32 txretrie; /* dot11MultipleRetryCount */
10292 + uint32 rxdup; /* dot11FrameduplicateCount */
10293 + uint32 txrts; /* dot11RTSSuccessCount */
10294 + uint32 txnocts; /* dot11RTSFailureCount */
10295 + uint32 txnoack; /* dot11ACKFailureCount */
10296 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
10297 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
10298 + uint32 rxcrc; /* dot11FCSErrorCount */
10299 + uint32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */
10300 + uint32 rxundec; /* dot11WEPUndecryptableCount */
10301 +
10302 + /* WPA2 counters (see rxundec for DecryptFailureCount) */
10303 + uint32 tkipmicfaill; /* TKIPLocalMICFailures */
10304 + uint32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */
10305 + uint32 tkipreplay; /* TKIPReplays */
10306 + uint32 ccmpfmterr; /* CCMPFormatErrors */
10307 + uint32 ccmpreplay; /* CCMPReplays */
10308 + uint32 ccmpundec; /* CCMPDecryptErrors */
10309 + uint32 fourwayfail; /* FourWayHandshakeFailures */
10310 + uint32 wepundec; /* dot11WEPUndecryptableCount */
10311 + uint32 wepicverr; /* dot11WEPICVErrorCount */
10312 + uint32 decsuccess; /* DecryptSuccessCount */
10313 + uint32 tkipicverr; /* TKIPICVErrorCount */
10314 + uint32 wepexcluded; /* dot11WEPExcludedCount */
10315 +} wl_cnt_t;
10316 +
10317 +#endif /* _wlioctl_h_ */
10318 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
10319 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
10320 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2005-11-07 21:57:07.881588000 +0100
10321 @@ -0,0 +1,321 @@
10322 +/*
10323 + * NVRAM variable manipulation (common)
10324 + *
10325 + * Copyright 2004, Broadcom Corporation
10326 + * All Rights Reserved.
10327 + *
10328 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10329 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10330 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10331 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10332 + *
10333 + * $Id$
10334 + */
10335 +
10336 +#include <typedefs.h>
10337 +#include <osl.h>
10338 +#include <bcmendian.h>
10339 +#include <bcmnvram.h>
10340 +#include <bcmutils.h>
10341 +#include <sbsdram.h>
10342 +
10343 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
10344 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
10345 +extern int BCMINIT(_nvram_read)(void *buf);
10346 +
10347 +char * BCMINIT(_nvram_get)(const char *name);
10348 +int BCMINIT(_nvram_set)(const char *name, const char *value);
10349 +int BCMINIT(_nvram_unset)(const char *name);
10350 +int BCMINIT(_nvram_getall)(char *buf, int count);
10351 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
10352 +int BCMINIT(_nvram_init)(void);
10353 +void BCMINIT(_nvram_exit)(void);
10354 +
10355 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
10356 +static struct nvram_tuple * nvram_dead;
10357 +
10358 +/* Free all tuples. Should be locked. */
10359 +static void
10360 +BCMINITFN(nvram_free)(void)
10361 +{
10362 + uint i;
10363 + struct nvram_tuple *t, *next;
10364 +
10365 + /* Free hash table */
10366 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10367 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
10368 + next = t->next;
10369 + BCMINIT(_nvram_free)(t);
10370 + }
10371 + BCMINIT(nvram_hash)[i] = NULL;
10372 + }
10373 +
10374 + /* Free dead table */
10375 + for (t = nvram_dead; t; t = next) {
10376 + next = t->next;
10377 + BCMINIT(_nvram_free)(t);
10378 + }
10379 + nvram_dead = NULL;
10380 +
10381 + /* Indicate to per-port code that all tuples have been freed */
10382 + BCMINIT(_nvram_free)(NULL);
10383 +}
10384 +
10385 +/* String hash */
10386 +static INLINE uint
10387 +hash(const char *s)
10388 +{
10389 + uint hash = 0;
10390 +
10391 + while (*s)
10392 + hash = 31 * hash + *s++;
10393 +
10394 + return hash;
10395 +}
10396 +
10397 +/* (Re)initialize the hash table. Should be locked. */
10398 +static int
10399 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
10400 +{
10401 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
10402 +
10403 + /* (Re)initialize hash table */
10404 + BCMINIT(nvram_free)();
10405 +
10406 + /* Parse and set "name=value\0 ... \0\0" */
10407 + name = (char *) &header[1];
10408 + end = (char *) header + NVRAM_SPACE - 2;
10409 + end[0] = end[1] = '\0';
10410 + for (; *name; name = value + strlen(value) + 1) {
10411 + if (!(eq = strchr(name, '=')))
10412 + break;
10413 + *eq = '\0';
10414 + value = eq + 1;
10415 + BCMINIT(_nvram_set)(name, value);
10416 + *eq = '=';
10417 + }
10418 +
10419 + /* Set special SDRAM parameters */
10420 + if (!BCMINIT(_nvram_get)("sdram_init")) {
10421 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
10422 + BCMINIT(_nvram_set)("sdram_init", buf);
10423 + }
10424 + if (!BCMINIT(_nvram_get)("sdram_config")) {
10425 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
10426 + BCMINIT(_nvram_set)("sdram_config", buf);
10427 + }
10428 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
10429 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
10430 + BCMINIT(_nvram_set)("sdram_refresh", buf);
10431 + }
10432 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
10433 + sprintf(buf, "0x%08X", header->config_ncdl);
10434 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
10435 + }
10436 +
10437 + return 0;
10438 +}
10439 +
10440 +/* Get the value of an NVRAM variable. Should be locked. */
10441 +char *
10442 +BCMINITFN(_nvram_get)(const char *name)
10443 +{
10444 + uint i;
10445 + struct nvram_tuple *t;
10446 + char *value;
10447 +
10448 + if (!name)
10449 + return NULL;
10450 +
10451 + /* Hash the name */
10452 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10453 +
10454 + /* Find the associated tuple in the hash table */
10455 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
10456 +
10457 + value = t ? t->value : NULL;
10458 +
10459 + return value;
10460 +}
10461 +
10462 +/* Get the value of an NVRAM variable. Should be locked. */
10463 +int
10464 +BCMINITFN(_nvram_set)(const char *name, const char *value)
10465 +{
10466 + uint i;
10467 + struct nvram_tuple *t, *u, **prev;
10468 +
10469 + /* Hash the name */
10470 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10471 +
10472 + /* Find the associated tuple in the hash table */
10473 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
10474 +
10475 + /* (Re)allocate tuple */
10476 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
10477 + return -12; /* -ENOMEM */
10478 +
10479 + /* Value reallocated */
10480 + if (t && t == u)
10481 + return 0;
10482 +
10483 + /* Move old tuple to the dead table */
10484 + if (t) {
10485 + *prev = t->next;
10486 + t->next = nvram_dead;
10487 + nvram_dead = t;
10488 + }
10489 +
10490 + /* Add new tuple to the hash table */
10491 + u->next = BCMINIT(nvram_hash)[i];
10492 + BCMINIT(nvram_hash)[i] = u;
10493 +
10494 + return 0;
10495 +}
10496 +
10497 +/* Unset the value of an NVRAM variable. Should be locked. */
10498 +int
10499 +BCMINITFN(_nvram_unset)(const char *name)
10500 +{
10501 + uint i;
10502 + struct nvram_tuple *t, **prev;
10503 +
10504 + if (!name)
10505 + return 0;
10506 +
10507 + /* Hash the name */
10508 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10509 +
10510 + /* Find the associated tuple in the hash table */
10511 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
10512 +
10513 + /* Move it to the dead table */
10514 + if (t) {
10515 + *prev = t->next;
10516 + t->next = nvram_dead;
10517 + nvram_dead = t;
10518 + }
10519 +
10520 + return 0;
10521 +}
10522 +
10523 +/* Get all NVRAM variables. Should be locked. */
10524 +int
10525 +BCMINITFN(_nvram_getall)(char *buf, int count)
10526 +{
10527 + uint i;
10528 + struct nvram_tuple *t;
10529 + int len = 0;
10530 +
10531 + bzero(buf, count);
10532 +
10533 + /* Write name=value\0 ... \0\0 */
10534 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10535 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
10536 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
10537 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
10538 + else
10539 + break;
10540 + }
10541 + }
10542 +
10543 + return 0;
10544 +}
10545 +
10546 +/* Regenerate NVRAM. Should be locked. */
10547 +int
10548 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
10549 +{
10550 + char *init, *config, *refresh, *ncdl;
10551 + char *ptr, *end;
10552 + int i;
10553 + struct nvram_tuple *t;
10554 + struct nvram_header tmp;
10555 + uint8 crc;
10556 +
10557 + /* Regenerate header */
10558 + header->magic = NVRAM_MAGIC;
10559 + header->crc_ver_init = (NVRAM_VERSION << 8);
10560 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
10561 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
10562 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
10563 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
10564 + header->crc_ver_init |= SDRAM_INIT << 16;
10565 + header->config_refresh = SDRAM_CONFIG;
10566 + header->config_refresh |= SDRAM_REFRESH << 16;
10567 + header->config_ncdl = 0;
10568 + } else {
10569 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
10570 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
10571 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
10572 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
10573 + }
10574 +
10575 + /* Clear data area */
10576 + ptr = (char *) header + sizeof(struct nvram_header);
10577 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
10578 +
10579 + /* Leave space for a double NUL at the end */
10580 + end = (char *) header + NVRAM_SPACE - 2;
10581 +
10582 + /* Write out all tuples */
10583 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10584 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
10585 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
10586 + break;
10587 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
10588 + }
10589 + }
10590 +
10591 + /* End with a double NUL */
10592 + ptr += 2;
10593 +
10594 + /* Set new length */
10595 + header->len = ROUNDUP(ptr - (char *) header, 4);
10596 +
10597 + /* Little-endian CRC8 over the last 11 bytes of the header */
10598 + tmp.crc_ver_init = htol32(header->crc_ver_init);
10599 + tmp.config_refresh = htol32(header->config_refresh);
10600 + tmp.config_ncdl = htol32(header->config_ncdl);
10601 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
10602 +
10603 + /* Continue CRC8 over data bytes */
10604 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
10605 +
10606 + /* Set new CRC8 */
10607 + header->crc_ver_init |= crc;
10608 +
10609 + /* Reinitialize hash table */
10610 + return BCMINIT(nvram_rehash)(header);
10611 +}
10612 +
10613 +/* Initialize hash table. Should be locked. */
10614 +int
10615 +BCMINITFN(_nvram_init)(void)
10616 +{
10617 + struct nvram_header *header;
10618 + int ret;
10619 + void *osh;
10620 +
10621 + /* get kernel osl handler */
10622 + osh = osl_attach(NULL);
10623 +
10624 + if (!(header = (struct nvram_header *) MALLOC(osh, NVRAM_SPACE))) {
10625 + printf("nvram_init: out of memory, malloced %d bytes\n", MALLOCED(osh));
10626 + return -12; /* -ENOMEM */
10627 + }
10628 +
10629 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
10630 + header->magic == NVRAM_MAGIC)
10631 + BCMINIT(nvram_rehash)(header);
10632 +
10633 + MFREE(osh, header, NVRAM_SPACE);
10634 + return ret;
10635 +}
10636 +
10637 +/* Free hash table. Should be locked. */
10638 +void
10639 +BCMINITFN(_nvram_exit)(void)
10640 +{
10641 + BCMINIT(nvram_free)();
10642 +}
10643 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
10644 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
10645 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2005-11-08 00:54:56.755597250 +0100
10646 @@ -0,0 +1,633 @@
10647 +/*
10648 + * NVRAM variable manipulation (Linux kernel half)
10649 + *
10650 + * Copyright 2005, Broadcom Corporation
10651 + * All Rights Reserved.
10652 + *
10653 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10654 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10655 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10656 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10657 + *
10658 + * $Id$
10659 + */
10660 +
10661 +#include <linux/config.h>
10662 +#include <linux/init.h>
10663 +#include <linux/module.h>
10664 +#include <linux/kernel.h>
10665 +#include <linux/string.h>
10666 +#include <linux/interrupt.h>
10667 +#include <linux/spinlock.h>
10668 +#include <linux/slab.h>
10669 +#include <linux/bootmem.h>
10670 +#include <linux/wrapper.h>
10671 +#include <linux/fs.h>
10672 +#include <linux/miscdevice.h>
10673 +#include <linux/mtd/mtd.h>
10674 +#include <asm/addrspace.h>
10675 +#include <asm/io.h>
10676 +#include <asm/uaccess.h>
10677 +
10678 +#include <typedefs.h>
10679 +#include <bcmendian.h>
10680 +#include <bcmnvram.h>
10681 +#include <bcmutils.h>
10682 +#include <sbconfig.h>
10683 +#include <sbchipc.h>
10684 +#include <sbutils.h>
10685 +#include <sbmips.h>
10686 +#include <sflash.h>
10687 +
10688 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
10689 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
10690 +
10691 +#ifdef MODULE
10692 +
10693 +#define early_nvram_get(name) nvram_get(name)
10694 +
10695 +#else /* !MODULE */
10696 +
10697 +/* Global SB handle */
10698 +extern void *bcm947xx_sbh;
10699 +extern spinlock_t bcm947xx_sbh_lock;
10700 +
10701 +/* Convenience */
10702 +#define sbh bcm947xx_sbh
10703 +#define sbh_lock bcm947xx_sbh_lock
10704 +#define KB * 1024
10705 +#define MB * 1024 * 1024
10706 +
10707 +/* Probe for NVRAM header */
10708 +static void __init
10709 +early_nvram_init(void)
10710 +{
10711 + struct nvram_header *header;
10712 + chipcregs_t *cc;
10713 + struct sflash *info = NULL;
10714 + int i;
10715 + uint32 base, off, lim;
10716 + u32 *src, *dst;
10717 +
10718 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
10719 + base = KSEG1ADDR(SB_FLASH2);
10720 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
10721 + case PFLASH:
10722 + lim = SB_FLASH2_SZ;
10723 + break;
10724 +
10725 + case SFLASH_ST:
10726 + case SFLASH_AT:
10727 + if ((info = sflash_init(cc)) == NULL)
10728 + return;
10729 + lim = info->size;
10730 + break;
10731 +
10732 + case FLASH_NONE:
10733 + default:
10734 + return;
10735 + }
10736 + } else {
10737 + /* extif assumed, Stop at 4 MB */
10738 + base = KSEG1ADDR(SB_FLASH1);
10739 + lim = SB_FLASH1_SZ;
10740 + }
10741 +
10742 + off = FLASH_MIN;
10743 + while (off <= lim) {
10744 + /* Windowed flash access */
10745 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
10746 + if (header->magic == NVRAM_MAGIC)
10747 + goto found;
10748 + off <<= 1;
10749 + }
10750 +
10751 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
10752 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
10753 + if (header->magic == NVRAM_MAGIC)
10754 + goto found;
10755 +
10756 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
10757 + if (header->magic == NVRAM_MAGIC)
10758 + goto found;
10759 +
10760 + printk("early_nvram_init: NVRAM not found\n");
10761 + return;
10762 +
10763 +found:
10764 + src = (u32 *) header;
10765 + dst = (u32 *) nvram_buf;
10766 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
10767 + *dst++ = *src++;
10768 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
10769 + *dst++ = ltoh32(*src++);
10770 +}
10771 +
10772 +/* Early (before mm or mtd) read-only access to NVRAM */
10773 +static char * __init
10774 +early_nvram_get(const char *name)
10775 +{
10776 + char *var, *value, *end, *eq;
10777 +
10778 + if (!name)
10779 + return NULL;
10780 +
10781 + /* Too early? */
10782 + if (sbh == NULL)
10783 + return NULL;
10784 +
10785 + if (!nvram_buf[0])
10786 + early_nvram_init();
10787 +
10788 + /* Look for name=value and return value */
10789 + var = &nvram_buf[sizeof(struct nvram_header)];
10790 + end = nvram_buf + sizeof(nvram_buf) - 2;
10791 + end[0] = end[1] = '\0';
10792 + for (; *var; var = value + strlen(value) + 1) {
10793 + if (!(eq = strchr(var, '=')))
10794 + break;
10795 + value = eq + 1;
10796 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
10797 + return value;
10798 + }
10799 +
10800 + return NULL;
10801 +}
10802 +
10803 +#endif /* !MODULE */
10804 +
10805 +extern char * _nvram_get(const char *name);
10806 +extern int _nvram_set(const char *name, const char *value);
10807 +extern int _nvram_unset(const char *name);
10808 +extern int _nvram_getall(char *buf, int count);
10809 +extern int _nvram_commit(struct nvram_header *header);
10810 +extern int _nvram_init(void);
10811 +extern void _nvram_exit(void);
10812 +
10813 +/* Globals */
10814 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
10815 +static struct semaphore nvram_sem;
10816 +static unsigned long nvram_offset = 0;
10817 +static int nvram_major = -1;
10818 +static devfs_handle_t nvram_handle = NULL;
10819 +static struct mtd_info *nvram_mtd = NULL;
10820 +
10821 +int
10822 +_nvram_read(char *buf)
10823 +{
10824 + struct nvram_header *header = (struct nvram_header *) buf;
10825 + size_t len;
10826 +
10827 + if (!nvram_mtd ||
10828 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
10829 + len != NVRAM_SPACE ||
10830 + header->magic != NVRAM_MAGIC) {
10831 + /* Maybe we can recover some data from early initialization */
10832 + memcpy(buf, nvram_buf, NVRAM_SPACE);
10833 + }
10834 +
10835 + return 0;
10836 +}
10837 +
10838 +struct nvram_tuple *
10839 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
10840 +{
10841 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
10842 + return NULL;
10843 +
10844 + if (!t) {
10845 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
10846 + return NULL;
10847 +
10848 + /* Copy name */
10849 + t->name = (char *) &t[1];
10850 + strcpy(t->name, name);
10851 +
10852 + t->value = NULL;
10853 + }
10854 +
10855 + /* Copy value */
10856 + if (!t->value || strcmp(t->value, value)) {
10857 + t->value = &nvram_buf[nvram_offset];
10858 + strcpy(t->value, value);
10859 + nvram_offset += strlen(value) + 1;
10860 + }
10861 +
10862 + return t;
10863 +}
10864 +
10865 +void
10866 +_nvram_free(struct nvram_tuple *t)
10867 +{
10868 + if (!t)
10869 + nvram_offset = 0;
10870 + else
10871 + kfree(t);
10872 +}
10873 +
10874 +int
10875 +nvram_set(const char *name, const char *value)
10876 +{
10877 + unsigned long flags;
10878 + int ret;
10879 + struct nvram_header *header;
10880 +
10881 + spin_lock_irqsave(&nvram_lock, flags);
10882 + if ((ret = _nvram_set(name, value))) {
10883 + /* Consolidate space and try again */
10884 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
10885 + if (_nvram_commit(header) == 0)
10886 + ret = _nvram_set(name, value);
10887 + kfree(header);
10888 + }
10889 + }
10890 + spin_unlock_irqrestore(&nvram_lock, flags);
10891 +
10892 + return ret;
10893 +}
10894 +
10895 +char *
10896 +real_nvram_get(const char *name)
10897 +{
10898 + unsigned long flags;
10899 + char *value;
10900 +
10901 + spin_lock_irqsave(&nvram_lock, flags);
10902 + value = _nvram_get(name);
10903 + spin_unlock_irqrestore(&nvram_lock, flags);
10904 +
10905 + return value;
10906 +}
10907 +
10908 +char *
10909 +nvram_get(const char *name)
10910 +{
10911 + if (nvram_major >= 0)
10912 + return real_nvram_get(name);
10913 + else
10914 + return early_nvram_get(name);
10915 +}
10916 +
10917 +int
10918 +nvram_unset(const char *name)
10919 +{
10920 + unsigned long flags;
10921 + int ret;
10922 +
10923 + spin_lock_irqsave(&nvram_lock, flags);
10924 + ret = _nvram_unset(name);
10925 + spin_unlock_irqrestore(&nvram_lock, flags);
10926 +
10927 + return ret;
10928 +}
10929 +
10930 +static void
10931 +erase_callback(struct erase_info *done)
10932 +{
10933 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
10934 + wake_up(wait_q);
10935 +}
10936 +
10937 +int
10938 +nvram_commit(void)
10939 +{
10940 + char *buf;
10941 + size_t erasesize, len;
10942 + unsigned int i;
10943 + int ret;
10944 + struct nvram_header *header;
10945 + unsigned long flags;
10946 + u_int32_t offset;
10947 + DECLARE_WAITQUEUE(wait, current);
10948 + wait_queue_head_t wait_q;
10949 + struct erase_info erase;
10950 +
10951 + if (!nvram_mtd) {
10952 + printk("nvram_commit: NVRAM not found\n");
10953 + return -ENODEV;
10954 + }
10955 +
10956 + if (in_interrupt()) {
10957 + printk("nvram_commit: not committing in interrupt\n");
10958 + return -EINVAL;
10959 + }
10960 +
10961 + /* Backup sector blocks to be erased */
10962 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
10963 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
10964 + printk("nvram_commit: out of memory\n");
10965 + return -ENOMEM;
10966 + }
10967 +
10968 + down(&nvram_sem);
10969 +
10970 + if ((i = erasesize - NVRAM_SPACE) > 0) {
10971 + offset = nvram_mtd->size - erasesize;
10972 + len = 0;
10973 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
10974 + if (ret || len != i) {
10975 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
10976 + ret = -EIO;
10977 + goto done;
10978 + }
10979 + header = (struct nvram_header *)(buf + i);
10980 + } else {
10981 + offset = nvram_mtd->size - NVRAM_SPACE;
10982 + header = (struct nvram_header *)buf;
10983 + }
10984 +
10985 + /* Regenerate NVRAM */
10986 + spin_lock_irqsave(&nvram_lock, flags);
10987 + ret = _nvram_commit(header);
10988 + spin_unlock_irqrestore(&nvram_lock, flags);
10989 + if (ret)
10990 + goto done;
10991 +
10992 + /* Erase sector blocks */
10993 + init_waitqueue_head(&wait_q);
10994 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
10995 + erase.mtd = nvram_mtd;
10996 + erase.addr = offset;
10997 + erase.len = nvram_mtd->erasesize;
10998 + erase.callback = erase_callback;
10999 + erase.priv = (u_long) &wait_q;
11000 +
11001 + set_current_state(TASK_INTERRUPTIBLE);
11002 + add_wait_queue(&wait_q, &wait);
11003 +
11004 + /* Unlock sector blocks */
11005 + if (nvram_mtd->unlock)
11006 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
11007 +
11008 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
11009 + set_current_state(TASK_RUNNING);
11010 + remove_wait_queue(&wait_q, &wait);
11011 + printk("nvram_commit: erase error\n");
11012 + goto done;
11013 + }
11014 +
11015 + /* Wait for erase to finish */
11016 + schedule();
11017 + remove_wait_queue(&wait_q, &wait);
11018 + }
11019 +
11020 + /* Write partition up to end of data area */
11021 + offset = nvram_mtd->size - erasesize;
11022 + i = erasesize - NVRAM_SPACE + header->len;
11023 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
11024 + if (ret || len != i) {
11025 + printk("nvram_commit: write error\n");
11026 + ret = -EIO;
11027 + goto done;
11028 + }
11029 +
11030 + offset = nvram_mtd->size - erasesize;
11031 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
11032 +
11033 + done:
11034 + up(&nvram_sem);
11035 + kfree(buf);
11036 + return ret;
11037 +}
11038 +
11039 +int
11040 +nvram_getall(char *buf, int count)
11041 +{
11042 + unsigned long flags;
11043 + int ret;
11044 +
11045 + spin_lock_irqsave(&nvram_lock, flags);
11046 + ret = _nvram_getall(buf, count);
11047 + spin_unlock_irqrestore(&nvram_lock, flags);
11048 +
11049 + return ret;
11050 +}
11051 +
11052 +EXPORT_SYMBOL(nvram_get);
11053 +EXPORT_SYMBOL(nvram_getall);
11054 +EXPORT_SYMBOL(nvram_set);
11055 +EXPORT_SYMBOL(nvram_unset);
11056 +EXPORT_SYMBOL(nvram_commit);
11057 +
11058 +/* User mode interface below */
11059 +
11060 +static ssize_t
11061 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
11062 +{
11063 + char tmp[100], *name = tmp, *value;
11064 + ssize_t ret;
11065 + unsigned long off;
11066 +
11067 + if (count > sizeof(tmp)) {
11068 + if (!(name = kmalloc(count, GFP_KERNEL)))
11069 + return -ENOMEM;
11070 + }
11071 +
11072 + if (copy_from_user(name, buf, count)) {
11073 + ret = -EFAULT;
11074 + goto done;
11075 + }
11076 +
11077 + if (*name == '\0') {
11078 + /* Get all variables */
11079 + ret = nvram_getall(name, count);
11080 + if (ret == 0) {
11081 + if (copy_to_user(buf, name, count)) {
11082 + ret = -EFAULT;
11083 + goto done;
11084 + }
11085 + ret = count;
11086 + }
11087 + } else {
11088 + if (!(value = nvram_get(name))) {
11089 + ret = 0;
11090 + goto done;
11091 + }
11092 +
11093 + /* Provide the offset into mmap() space */
11094 + off = (unsigned long) value - (unsigned long) nvram_buf;
11095 +
11096 + if (put_user(off, (unsigned long *) buf)) {
11097 + ret = -EFAULT;
11098 + goto done;
11099 + }
11100 +
11101 + ret = sizeof(unsigned long);
11102 + }
11103 +
11104 + flush_cache_all();
11105 +
11106 +done:
11107 + if (name != tmp)
11108 + kfree(name);
11109 +
11110 + return ret;
11111 +}
11112 +
11113 +static ssize_t
11114 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
11115 +{
11116 + char tmp[100], *name = tmp, *value;
11117 + ssize_t ret;
11118 +
11119 + if (count > sizeof(tmp)) {
11120 + if (!(name = kmalloc(count, GFP_KERNEL)))
11121 + return -ENOMEM;
11122 + }
11123 +
11124 + if (copy_from_user(name, buf, count)) {
11125 + ret = -EFAULT;
11126 + goto done;
11127 + }
11128 +
11129 + value = name;
11130 + name = strsep(&value, "=");
11131 + if (value)
11132 + ret = nvram_set(name, value) ? : count;
11133 + else
11134 + ret = nvram_unset(name) ? : count;
11135 +
11136 + done:
11137 + if (name != tmp)
11138 + kfree(name);
11139 +
11140 + return ret;
11141 +}
11142 +
11143 +static int
11144 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
11145 +{
11146 + if (cmd != NVRAM_MAGIC)
11147 + return -EINVAL;
11148 + return nvram_commit();
11149 +}
11150 +
11151 +static int
11152 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
11153 +{
11154 + unsigned long offset = virt_to_phys(nvram_buf);
11155 +
11156 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
11157 + vma->vm_page_prot))
11158 + return -EAGAIN;
11159 +
11160 + return 0;
11161 +}
11162 +
11163 +static int
11164 +dev_nvram_open(struct inode *inode, struct file * file)
11165 +{
11166 + MOD_INC_USE_COUNT;
11167 + return 0;
11168 +}
11169 +
11170 +static int
11171 +dev_nvram_release(struct inode *inode, struct file * file)
11172 +{
11173 + MOD_DEC_USE_COUNT;
11174 + return 0;
11175 +}
11176 +
11177 +static struct file_operations dev_nvram_fops = {
11178 + owner: THIS_MODULE,
11179 + open: dev_nvram_open,
11180 + release: dev_nvram_release,
11181 + read: dev_nvram_read,
11182 + write: dev_nvram_write,
11183 + ioctl: dev_nvram_ioctl,
11184 + mmap: dev_nvram_mmap,
11185 +};
11186 +
11187 +static void
11188 +dev_nvram_exit(void)
11189 +{
11190 + int order = 0;
11191 + struct page *page, *end;
11192 +
11193 + if (nvram_handle)
11194 + devfs_unregister(nvram_handle);
11195 +
11196 + if (nvram_major >= 0)
11197 + devfs_unregister_chrdev(nvram_major, "nvram");
11198 +
11199 + if (nvram_mtd)
11200 + put_mtd_device(nvram_mtd);
11201 +
11202 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
11203 + order++;
11204 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
11205 + for (page = virt_to_page(nvram_buf); page <= end; page++)
11206 + mem_map_unreserve(page);
11207 +
11208 + _nvram_exit();
11209 +}
11210 +
11211 +static int __init
11212 +dev_nvram_init(void)
11213 +{
11214 + int order = 0, ret = 0;
11215 + struct page *page, *end;
11216 + unsigned int i;
11217 +
11218 + /* Allocate and reserve memory to mmap() */
11219 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
11220 + order++;
11221 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
11222 + for (page = virt_to_page(nvram_buf); page <= end; page++)
11223 + mem_map_reserve(page);
11224 +
11225 +#ifdef CONFIG_MTD
11226 + /* Find associated MTD device */
11227 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
11228 + nvram_mtd = get_mtd_device(NULL, i);
11229 + if (nvram_mtd) {
11230 + if (!strcmp(nvram_mtd->name, "nvram") &&
11231 + nvram_mtd->size >= NVRAM_SPACE)
11232 + break;
11233 + put_mtd_device(nvram_mtd);
11234 + }
11235 + }
11236 + if (i >= MAX_MTD_DEVICES)
11237 + nvram_mtd = NULL;
11238 +#endif
11239 +
11240 + /* Initialize hash table lock */
11241 + spin_lock_init(&nvram_lock);
11242 +
11243 + /* Initialize commit semaphore */
11244 + init_MUTEX(&nvram_sem);
11245 +
11246 + /* Register char device */
11247 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
11248 + ret = nvram_major;
11249 + goto err;
11250 + }
11251 +
11252 + /* Initialize hash table */
11253 + _nvram_init();
11254 +
11255 + /* Create /dev/nvram handle */
11256 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
11257 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
11258 +
11259 + /* Set the SDRAM NCDL value into NVRAM if not already done */
11260 + if (getintvar(NULL, "sdram_ncdl") == 0) {
11261 + unsigned int ncdl;
11262 + char buf[] = "0x00000000";
11263 +
11264 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
11265 + sprintf(buf, "0x%08x", ncdl);
11266 + nvram_set("sdram_ncdl", buf);
11267 + nvram_commit();
11268 + }
11269 + }
11270 +
11271 + return 0;
11272 +
11273 + err:
11274 + dev_nvram_exit();
11275 + return ret;
11276 +}
11277 +
11278 +module_init(dev_nvram_init);
11279 +module_exit(dev_nvram_exit);
11280 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
11281 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
11282 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2005-11-07 23:59:38.908750500 +0100
11283 @@ -0,0 +1,355 @@
11284 +/*
11285 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
11286 + *
11287 + * Copyright 2005, Broadcom Corporation
11288 + * All Rights Reserved.
11289 + *
11290 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11291 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11292 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11293 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11294 + *
11295 + * $Id$
11296 + */
11297 +
11298 +#include <linux/config.h>
11299 +#include <linux/types.h>
11300 +#include <linux/kernel.h>
11301 +#include <linux/sched.h>
11302 +#include <linux/pci.h>
11303 +#include <linux/init.h>
11304 +#include <linux/delay.h>
11305 +#include <asm/io.h>
11306 +#include <asm/irq.h>
11307 +#include <asm/paccess.h>
11308 +
11309 +#include <typedefs.h>
11310 +#include <bcmutils.h>
11311 +#include <sbconfig.h>
11312 +#include <sbutils.h>
11313 +#include <sbpci.h>
11314 +#include <pcicfg.h>
11315 +#include <bcmdevs.h>
11316 +#include <bcmnvram.h>
11317 +
11318 +/* Global SB handle */
11319 +extern sb_t *bcm947xx_sbh;
11320 +extern spinlock_t bcm947xx_sbh_lock;
11321 +
11322 +/* Convenience */
11323 +#define sbh bcm947xx_sbh
11324 +#define sbh_lock bcm947xx_sbh_lock
11325 +
11326 +static int
11327 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
11328 +{
11329 + unsigned long flags;
11330 + int ret;
11331 +
11332 + spin_lock_irqsave(&sbh_lock, flags);
11333 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11334 + spin_unlock_irqrestore(&sbh_lock, flags);
11335 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11336 +}
11337 +
11338 +static int
11339 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
11340 +{
11341 + unsigned long flags;
11342 + int ret;
11343 +
11344 + spin_lock_irqsave(&sbh_lock, flags);
11345 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11346 + spin_unlock_irqrestore(&sbh_lock, flags);
11347 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11348 +}
11349 +
11350 +static int
11351 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
11352 +{
11353 + unsigned long flags;
11354 + int ret;
11355 +
11356 + spin_lock_irqsave(&sbh_lock, flags);
11357 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11358 + spin_unlock_irqrestore(&sbh_lock, flags);
11359 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11360 +}
11361 +
11362 +static int
11363 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
11364 +{
11365 + unsigned long flags;
11366 + int ret;
11367 +
11368 + spin_lock_irqsave(&sbh_lock, flags);
11369 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11370 + spin_unlock_irqrestore(&sbh_lock, flags);
11371 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11372 +}
11373 +
11374 +static int
11375 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
11376 +{
11377 + unsigned long flags;
11378 + int ret;
11379 +
11380 + spin_lock_irqsave(&sbh_lock, flags);
11381 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11382 + spin_unlock_irqrestore(&sbh_lock, flags);
11383 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11384 +}
11385 +
11386 +static int
11387 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
11388 +{
11389 + unsigned long flags;
11390 + int ret;
11391 +
11392 + spin_lock_irqsave(&sbh_lock, flags);
11393 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11394 + spin_unlock_irqrestore(&sbh_lock, flags);
11395 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11396 +}
11397 +
11398 +static struct pci_ops pcibios_ops = {
11399 + sbpci_read_config_byte,
11400 + sbpci_read_config_word,
11401 + sbpci_read_config_dword,
11402 + sbpci_write_config_byte,
11403 + sbpci_write_config_word,
11404 + sbpci_write_config_dword
11405 +};
11406 +
11407 +
11408 +void __init
11409 +pcibios_init(void)
11410 +{
11411 + ulong flags;
11412 +
11413 + if (!(sbh = sb_kattach()))
11414 + panic("sb_kattach failed");
11415 + spin_lock_init(&sbh_lock);
11416 +
11417 + spin_lock_irqsave(&sbh_lock, flags);
11418 + sbpci_init(sbh);
11419 + spin_unlock_irqrestore(&sbh_lock, flags);
11420 +
11421 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11422 +
11423 + mdelay(300); //By Joey for Atheros Card
11424 +
11425 + /* Scan the SB bus */
11426 + pci_scan_bus(0, &pcibios_ops, NULL);
11427 +
11428 +}
11429 +
11430 +char * __init
11431 +pcibios_setup(char *str)
11432 +{
11433 + if (!strncmp(str, "ban=", 4)) {
11434 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
11435 + return NULL;
11436 + }
11437 +
11438 + return (str);
11439 +}
11440 +
11441 +static u32 pci_iobase = 0x100;
11442 +static u32 pci_membase = SB_PCI_DMA;
11443 +
11444 +void __init
11445 +pcibios_fixup_bus(struct pci_bus *b)
11446 +{
11447 + struct list_head *ln;
11448 + struct pci_dev *d;
11449 + struct resource *res;
11450 + int pos, size;
11451 + u32 *base;
11452 + u8 irq;
11453 +
11454 + printk("PCI: Fixing up bus %d\n", b->number);
11455 +
11456 + /* Fix up SB */
11457 + if (b->number == 0) {
11458 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
11459 + d = pci_dev_b(ln);
11460 + /* Fix up interrupt lines */
11461 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
11462 + d->irq = irq + 2;
11463 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11464 + }
11465 + }
11466 +
11467 + /* Fix up external PCI */
11468 + else {
11469 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
11470 + d = pci_dev_b(ln);
11471 + /* Fix up resource bases */
11472 + for (pos = 0; pos < 6; pos++) {
11473 + res = &d->resource[pos];
11474 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
11475 + if (res->end) {
11476 + size = res->end - res->start + 1;
11477 + if (*base & (size - 1))
11478 + *base = (*base + size) & ~(size - 1);
11479 + res->start = *base;
11480 + res->end = res->start + size - 1;
11481 + *base += size;
11482 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11483 + }
11484 + /* Fix up PCI bridge BAR0 only */
11485 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
11486 + break;
11487 + }
11488 + /* Fix up interrupt lines */
11489 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11490 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11491 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11492 + }
11493 + }
11494 +}
11495 +
11496 +unsigned int
11497 +pcibios_assign_all_busses(void)
11498 +{
11499 + return 1;
11500 +}
11501 +
11502 +void
11503 +pcibios_align_resource(void *data, struct resource *res,
11504 + unsigned long size, unsigned long align)
11505 +{
11506 +}
11507 +
11508 +int
11509 +pcibios_enable_resources(struct pci_dev *dev)
11510 +{
11511 + u16 cmd, old_cmd;
11512 + int idx;
11513 + struct resource *r;
11514 +
11515 + /* External PCI only */
11516 + if (dev->bus->number == 0)
11517 + return 0;
11518 +
11519 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
11520 + old_cmd = cmd;
11521 + for(idx=0; idx<6; idx++) {
11522 + r = &dev->resource[idx];
11523 + if (r->flags & IORESOURCE_IO)
11524 + cmd |= PCI_COMMAND_IO;
11525 + if (r->flags & IORESOURCE_MEM)
11526 + cmd |= PCI_COMMAND_MEMORY;
11527 + }
11528 + if (dev->resource[PCI_ROM_RESOURCE].start)
11529 + cmd |= PCI_COMMAND_MEMORY;
11530 + if (cmd != old_cmd) {
11531 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
11532 + pci_write_config_word(dev, PCI_COMMAND, cmd);
11533 + }
11534 + return 0;
11535 +}
11536 +
11537 +int
11538 +pcibios_enable_device(struct pci_dev *dev, int mask)
11539 +{
11540 + ulong flags;
11541 + uint coreidx;
11542 +
11543 + /* External PCI device enable */
11544 + if (dev->bus->number != 0)
11545 + return pcibios_enable_resources(dev);
11546 +
11547 + /* These cores come out of reset enabled */
11548 + if (dev->device == SB_MIPS ||
11549 + dev->device == SB_MIPS33 ||
11550 + dev->device == SB_EXTIF ||
11551 + dev->device == SB_CC)
11552 + return 0;
11553 +
11554 + spin_lock_irqsave(&sbh_lock, flags);
11555 + coreidx = sb_coreidx(sbh);
11556 + if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
11557 + return PCIBIOS_DEVICE_NOT_FOUND;
11558 +
11559 + /*
11560 + * The USB core requires a special bit to be set during core
11561 + * reset to enable host (OHCI) mode. Resetting the SB core in
11562 + * pcibios_enable_device() is a hack for compatibility with
11563 + * vanilla usb-ohci so that it does not have to know about
11564 + * SB. A driver that wants to use the USB core in device mode
11565 + * should know about SB and should reset the bit back to 0
11566 + * after calling pcibios_enable_device().
11567 + */
11568 + if (sb_coreid(sbh) == SB_USB) {
11569 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11570 + sb_core_reset(sbh, 1 << 29);
11571 + } else
11572 + sb_core_reset(sbh, 0);
11573 +
11574 + sb_setcoreidx(sbh, coreidx);
11575 + spin_unlock_irqrestore(&sbh_lock, flags);
11576 +
11577 + return 0;
11578 +}
11579 +
11580 +void
11581 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
11582 + struct resource *res, int resource)
11583 +{
11584 + unsigned long where, size;
11585 + u32 reg;
11586 +
11587 + /* External PCI only */
11588 + if (dev->bus->number == 0)
11589 + return;
11590 +
11591 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
11592 + size = res->end - res->start;
11593 + pci_read_config_dword(dev, where, &reg);
11594 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
11595 + pci_write_config_dword(dev, where, reg);
11596 +}
11597 +
11598 +static void __init
11599 +quirk_sbpci_bridge(struct pci_dev *dev)
11600 +{
11601 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11602 + return;
11603 +
11604 + printk("PCI: Fixing up bridge\n");
11605 +
11606 + /* Enable PCI bridge bus mastering and memory space */
11607 + pci_set_master(dev);
11608 + pcibios_enable_resources(dev);
11609 +
11610 + /* Enable PCI bridge BAR1 prefetch and burst */
11611 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11612 +}
11613 +
11614 +struct pci_fixup pcibios_fixups[] = {
11615 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
11616 + { 0 }
11617 +};
11618 +
11619 +/*
11620 + * If we set up a device for bus mastering, we need to check the latency
11621 + * timer as certain crappy BIOSes forget to set it properly.
11622 + */
11623 +unsigned int pcibios_max_latency = 255;
11624 +
11625 +void pcibios_set_master(struct pci_dev *dev)
11626 +{
11627 + u8 lat;
11628 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
11629 + if (lat < 16)
11630 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
11631 + else if (lat > pcibios_max_latency)
11632 + lat = pcibios_max_latency;
11633 + else
11634 + return;
11635 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
11636 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
11637 +}
11638 +
11639 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11640 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11641 +++ linux.dev/arch/mips/bcm947xx/prom.c 2005-11-07 21:57:07.885588250 +0100
11642 @@ -0,0 +1,41 @@
11643 +/*
11644 + * Early initialization code for BCM94710 boards
11645 + *
11646 + * Copyright 2004, Broadcom Corporation
11647 + * All Rights Reserved.
11648 + *
11649 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11650 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11651 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11652 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11653 + *
11654 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
11655 + */
11656 +
11657 +#include <linux/config.h>
11658 +#include <linux/init.h>
11659 +#include <linux/kernel.h>
11660 +#include <linux/types.h>
11661 +#include <asm/bootinfo.h>
11662 +
11663 +void __init
11664 +prom_init(int argc, const char **argv)
11665 +{
11666 + unsigned long mem;
11667 +
11668 + mips_machgroup = MACH_GROUP_BRCM;
11669 + mips_machtype = MACH_BCM947XX;
11670 +
11671 + /* Figure out memory size by finding aliases */
11672 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11673 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11674 + *(unsigned long *)(prom_init))
11675 + break;
11676 + }
11677 + add_memory_region(0, mem, BOOT_MEM_RAM);
11678 +}
11679 +
11680 +void __init
11681 +prom_free_prom_memory(void)
11682 +{
11683 +}
11684 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
11685 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
11686 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2005-11-07 23:55:45.682174750 +0100
11687 @@ -0,0 +1,1038 @@
11688 +/*
11689 + * BCM47XX Sonics SiliconBackplane MIPS core routines
11690 + *
11691 + * Copyright 2005, Broadcom Corporation
11692 + * All Rights Reserved.
11693 + *
11694 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11695 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11696 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11697 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11698 + *
11699 + * $Id$
11700 + */
11701 +
11702 +#include <typedefs.h>
11703 +#include <osl.h>
11704 +#include <sbutils.h>
11705 +#include <bcmdevs.h>
11706 +#include <bcmnvram.h>
11707 +#include <bcmutils.h>
11708 +#include <hndmips.h>
11709 +#include <sbconfig.h>
11710 +#include <sbextif.h>
11711 +#include <sbchipc.h>
11712 +#include <sbmemc.h>
11713 +#include <mipsinc.h>
11714 +#include <sbutils.h>
11715 +
11716 +/*
11717 + * Returns TRUE if an external UART exists at the given base
11718 + * register.
11719 + */
11720 +static bool
11721 +BCMINITFN(serial_exists)(uint8 *regs)
11722 +{
11723 + uint8 save_mcr, status1;
11724 +
11725 + save_mcr = R_REG(&regs[UART_MCR]);
11726 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
11727 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
11728 + W_REG(&regs[UART_MCR], save_mcr);
11729 +
11730 + return (status1 == 0x90);
11731 +}
11732 +
11733 +/*
11734 + * Initializes UART access. The callback function will be called once
11735 + * per found UART.
11736 + */
11737 +void
11738 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
11739 +{
11740 + void *regs;
11741 + ulong base;
11742 + uint irq;
11743 + int i, n;
11744 +
11745 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
11746 + extifregs_t *eir = (extifregs_t *) regs;
11747 + sbconfig_t *sb;
11748 +
11749 + /* Determine external UART register base */
11750 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
11751 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
11752 +
11753 + /* Determine IRQ */
11754 + irq = sb_irq(sbh);
11755 +
11756 + /* Disable GPIO interrupt initially */
11757 + W_REG(&eir->gpiointpolarity, 0);
11758 + W_REG(&eir->gpiointmask, 0);
11759 +
11760 + /* Search for external UARTs */
11761 + n = 2;
11762 + for (i = 0; i < 2; i++) {
11763 + regs = (void *) REG_MAP(base + (i * 8), 8);
11764 + if (BCMINIT(serial_exists)(regs)) {
11765 + /* Set GPIO 1 to be the external UART IRQ */
11766 + W_REG(&eir->gpiointmask, 2);
11767 + if (add)
11768 + add(regs, irq, 13500000, 0);
11769 + }
11770 + }
11771 +
11772 + /* Add internal UART if enabled */
11773 + if (R_REG(&eir->corecontrol) & CC_UE)
11774 + if (add)
11775 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
11776 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
11777 + chipcregs_t *cc = (chipcregs_t *) regs;
11778 + uint32 rev, cap, pll, baud_base, div;
11779 +
11780 + /* Determine core revision and capabilities */
11781 + rev = sb_corerev(sbh);
11782 + cap = R_REG(&cc->capabilities);
11783 + pll = cap & CAP_PLL_MASK;
11784 +
11785 + /* Determine IRQ */
11786 + irq = sb_irq(sbh);
11787 +
11788 + if (pll == PLL_TYPE1) {
11789 + /* PLL clock */
11790 + baud_base = sb_clock_rate(pll,
11791 + R_REG(&cc->clockcontrol_n),
11792 + R_REG(&cc->clockcontrol_m2));
11793 + div = 1;
11794 + } else {
11795 + if (rev >= 11) {
11796 + /* Fixed ALP clock */
11797 + baud_base = 20000000;
11798 + div = 1;
11799 + /* Set the override bit so we don't divide it */
11800 + W_REG(&cc->corecontrol, CC_UARTCLKO);
11801 + } else if (rev >= 3) {
11802 + /* Internal backplane clock */
11803 + baud_base = sb_clock(sbh);
11804 + div = 2; /* Minimum divisor */
11805 + W_REG(&cc->clkdiv,
11806 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
11807 + } else {
11808 + /* Fixed internal backplane clock */
11809 + baud_base = 88000000;
11810 + div = 48;
11811 + }
11812 +
11813 + /* Clock source depends on strapping if UartClkOverride is unset */
11814 + if ((rev > 0) &&
11815 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
11816 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
11817 + /* Internal divided backplane clock */
11818 + baud_base /= div;
11819 + } else {
11820 + /* Assume external clock of 1.8432 MHz */
11821 + baud_base = 1843200;
11822 + }
11823 + }
11824 + }
11825 +
11826 + /* Add internal UARTs */
11827 + n = cap & CAP_UARTS_MASK;
11828 + for (i = 0; i < n; i++) {
11829 + /* Register offset changed after revision 0 */
11830 + if (rev)
11831 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
11832 + else
11833 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
11834 +
11835 + if (add)
11836 + add(regs, irq, baud_base, 0);
11837 + }
11838 + }
11839 +}
11840 +
11841 +/*
11842 + * Initialize jtag master and return handle for
11843 + * jtag_rwreg. Returns NULL on failure.
11844 + */
11845 +void *
11846 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
11847 +{
11848 + void *regs;
11849 +
11850 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
11851 + chipcregs_t *cc = (chipcregs_t *) regs;
11852 + uint32 tmp;
11853 +
11854 + /*
11855 + * Determine jtagm availability from
11856 + * core revision and capabilities.
11857 + */
11858 + tmp = sb_corerev(sbh);
11859 + /*
11860 + * Corerev 10 has jtagm, but the only chip
11861 + * with it does not have a mips, and
11862 + * the layout of the jtagcmd register is
11863 + * different. We'll only accept >= 11.
11864 + */
11865 + if (tmp < 11)
11866 + return (NULL);
11867 +
11868 + tmp = R_REG(&cc->capabilities);
11869 + if ((tmp & CAP_JTAGP) == 0)
11870 + return (NULL);
11871 +
11872 + /* Set clock divider if requested */
11873 + if (clkd != 0) {
11874 + tmp = R_REG(&cc->clkdiv);
11875 + tmp = (tmp & ~CLKD_JTAG) |
11876 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
11877 + W_REG(&cc->clkdiv, tmp);
11878 + }
11879 +
11880 + /* Enable jtagm */
11881 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
11882 + W_REG(&cc->jtagctrl, tmp);
11883 + }
11884 +
11885 + return (regs);
11886 +}
11887 +
11888 +void
11889 +sb_jtagm_disable(void *h)
11890 +{
11891 + chipcregs_t *cc = (chipcregs_t *)h;
11892 +
11893 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
11894 +}
11895 +
11896 +/*
11897 + * Read/write a jtag register. Assumes a target with
11898 + * 8 bit IR and 32 bit DR.
11899 + */
11900 +#define IRWIDTH 8
11901 +#define DRWIDTH 32
11902 +uint32
11903 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
11904 +{
11905 + chipcregs_t *cc = (chipcregs_t *) h;
11906 + uint32 tmp;
11907 +
11908 + W_REG(&cc->jtagir, ir);
11909 + W_REG(&cc->jtagdr, dr);
11910 + tmp = JCMD_START | JCMD_ACC_IRDR |
11911 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
11912 + (DRWIDTH - 1);
11913 + W_REG(&cc->jtagcmd, tmp);
11914 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
11915 + /* OSL_DELAY(1); */
11916 + }
11917 +
11918 + tmp = R_REG(&cc->jtagdr);
11919 + return (tmp);
11920 +}
11921 +
11922 +/* Returns the SB interrupt flag of the current core. */
11923 +uint32
11924 +sb_flag(sb_t *sbh)
11925 +{
11926 + void *regs;
11927 + sbconfig_t *sb;
11928 +
11929 + regs = sb_coreregs(sbh);
11930 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11931 +
11932 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
11933 +}
11934 +
11935 +static const uint32 sbips_int_mask[] = {
11936 + 0,
11937 + SBIPS_INT1_MASK,
11938 + SBIPS_INT2_MASK,
11939 + SBIPS_INT3_MASK,
11940 + SBIPS_INT4_MASK
11941 +};
11942 +
11943 +static const uint32 sbips_int_shift[] = {
11944 + 0,
11945 + 0,
11946 + SBIPS_INT2_SHIFT,
11947 + SBIPS_INT3_SHIFT,
11948 + SBIPS_INT4_SHIFT
11949 +};
11950 +
11951 +/*
11952 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
11953 + * 0 is returned.
11954 + */
11955 +uint
11956 +sb_irq(sb_t *sbh)
11957 +{
11958 + uint idx;
11959 + void *regs;
11960 + sbconfig_t *sb;
11961 + uint32 flag, sbipsflag;
11962 + uint irq = 0;
11963 +
11964 + flag = sb_flag(sbh);
11965 +
11966 + idx = sb_coreidx(sbh);
11967 +
11968 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
11969 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
11970 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11971 +
11972 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
11973 + sbipsflag = R_REG(&sb->sbipsflag);
11974 + for (irq = 1; irq <= 4; irq++) {
11975 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
11976 + break;
11977 + }
11978 + if (irq == 5)
11979 + irq = 0;
11980 + }
11981 +
11982 + sb_setcoreidx(sbh, idx);
11983 +
11984 + return irq;
11985 +}
11986 +
11987 +/* Clears the specified MIPS IRQ. */
11988 +static void
11989 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
11990 +{
11991 + void *regs;
11992 + sbconfig_t *sb;
11993 +
11994 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
11995 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
11996 + ASSERT(regs);
11997 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11998 +
11999 + if (irq == 0)
12000 + W_REG(&sb->sbintvec, 0);
12001 + else
12002 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
12003 +}
12004 +
12005 +/*
12006 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
12007 + * IRQ 0 may be assigned more than once.
12008 + */
12009 +static void
12010 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
12011 +{
12012 + void *regs;
12013 + sbconfig_t *sb;
12014 + uint32 flag;
12015 +
12016 + regs = sb_setcore(sbh, coreid, coreunit);
12017 + ASSERT(regs);
12018 + flag = sb_flag(sbh);
12019 +
12020 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
12021 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
12022 + ASSERT(regs);
12023 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12024 +
12025 + if (irq == 0)
12026 + OR_REG(&sb->sbintvec, 1 << flag);
12027 + else {
12028 + flag <<= sbips_int_shift[irq];
12029 + ASSERT(!(flag & ~sbips_int_mask[irq]));
12030 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
12031 + W_REG(&sb->sbipsflag, flag);
12032 + }
12033 +}
12034 +
12035 +/*
12036 + * Initializes clocks and interrupts. SB and NVRAM access must be
12037 + * initialized prior to calling.
12038 + */
12039 +void
12040 +BCMINITFN(sb_mips_init)(sb_t *sbh)
12041 +{
12042 + ulong hz, ns, tmp;
12043 + extifregs_t *eir;
12044 + chipcregs_t *cc;
12045 + char *value;
12046 + uint irq;
12047 +
12048 + /* Figure out current SB clock speed */
12049 + if ((hz = sb_clock(sbh)) == 0)
12050 + hz = 100000000;
12051 + ns = 1000000000 / hz;
12052 +
12053 + /* Setup external interface timing */
12054 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
12055 + /* Initialize extif so we can get to the LEDs and external UART */
12056 + W_REG(&eir->prog_config, CF_EN);
12057 +
12058 + /* Set timing for the flash */
12059 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
12060 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
12061 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
12062 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
12063 +
12064 + /* Set programmable interface timing for external uart */
12065 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
12066 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
12067 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
12068 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
12069 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
12070 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
12071 + /* Set timing for the flash */
12072 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
12073 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
12074 + tmp |= CEIL(120, ns); /* W0 = 120nS */
12075 +
12076 + // Added by Chen-I for 5365
12077 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
12078 + {
12079 + W_REG(&cc->flash_waitcount, tmp);
12080 + W_REG(&cc->pcmcia_memwait, tmp);
12081 + }
12082 + else
12083 + {
12084 + if (sb_corerev(sbh) < 9)
12085 + W_REG(&cc->flash_waitcount, tmp);
12086 +
12087 + if ((sb_corerev(sbh) < 9) ||
12088 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
12089 + W_REG(&cc->pcmcia_memwait, tmp);
12090 + }
12091 + }
12092 + }
12093 +
12094 + /* Chip specific initialization */
12095 + switch (BCMINIT(sb_chip)(sbh)) {
12096 + case BCM4710_DEVICE_ID:
12097 + /* Clear interrupt map */
12098 + for (irq = 0; irq <= 4; irq++)
12099 + BCMINIT(sb_clearirq)(sbh, irq);
12100 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
12101 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
12102 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
12103 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
12104 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
12105 + ASSERT(eir);
12106 + value = BCMINIT(nvram_get)("et0phyaddr");
12107 + if (value && !strcmp(value, "31")) {
12108 + /* Enable internal UART */
12109 + W_REG(&eir->corecontrol, CC_UE);
12110 + /* Give USB its own interrupt */
12111 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
12112 + } else {
12113 + /* Disable internal UART */
12114 + W_REG(&eir->corecontrol, 0);
12115 + /* Give Ethernet its own interrupt */
12116 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
12117 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
12118 + }
12119 + break;
12120 + case BCM5350_DEVICE_ID:
12121 + /* Clear interrupt map */
12122 + for (irq = 0; irq <= 4; irq++)
12123 + BCMINIT(sb_clearirq)(sbh, irq);
12124 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
12125 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
12126 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
12127 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
12128 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
12129 + break;
12130 + }
12131 +}
12132 +
12133 +uint32
12134 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
12135 +{
12136 + extifregs_t *eir;
12137 + chipcregs_t *cc;
12138 + uint32 n, m;
12139 + uint idx;
12140 + uint32 pll_type, rate = 0;
12141 +
12142 + /* get index of the current core */
12143 + idx = sb_coreidx(sbh);
12144 + pll_type = PLL_TYPE1;
12145 +
12146 + /* switch to extif or chipc core */
12147 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
12148 + n = R_REG(&eir->clockcontrol_n);
12149 + m = R_REG(&eir->clockcontrol_sb);
12150 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
12151 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
12152 + n = R_REG(&cc->clockcontrol_n);
12153 + if ((pll_type == PLL_TYPE2) ||
12154 + (pll_type == PLL_TYPE4) ||
12155 + (pll_type == PLL_TYPE6) ||
12156 + (pll_type == PLL_TYPE7))
12157 + m = R_REG(&cc->clockcontrol_mips);
12158 + else if (pll_type == PLL_TYPE5) {
12159 + rate = 200000000;
12160 + goto out;
12161 + }
12162 + else if (pll_type == PLL_TYPE3) {
12163 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
12164 + rate = 200000000;
12165 + goto out;
12166 + } else
12167 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
12168 + } else
12169 + m = R_REG(&cc->clockcontrol_sb);
12170 + } else
12171 + goto out;
12172 +
12173 + // Added by Chen-I for 5365
12174 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
12175 + rate = 100000000;
12176 + else
12177 + /* calculate rate */
12178 + rate = sb_clock_rate(pll_type, n, m);
12179 +
12180 + if (pll_type == PLL_TYPE6)
12181 + rate = SB2MIPS_T6(rate);
12182 +
12183 +out:
12184 + /* switch back to previous core */
12185 + sb_setcoreidx(sbh, idx);
12186 +
12187 + return rate;
12188 +}
12189 +
12190 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
12191 +
12192 +static void
12193 +BCMINITFN(handler)(void)
12194 +{
12195 + /* Step 11 */
12196 + __asm__ (
12197 + ".set\tmips32\n\t"
12198 + "ssnop\n\t"
12199 + "ssnop\n\t"
12200 + /* Disable interrupts */
12201 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
12202 + "mfc0 $15, $12\n\t"
12203 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
12204 + "li $14, -31746\n\t"
12205 + "and $15, $15, $14\n\t"
12206 + "mtc0 $15, $12\n\t"
12207 + "eret\n\t"
12208 + "nop\n\t"
12209 + "nop\n\t"
12210 + ".set\tmips0"
12211 + );
12212 +}
12213 +
12214 +/* The following MUST come right after handler() */
12215 +static void
12216 +BCMINITFN(afterhandler)(void)
12217 +{
12218 +}
12219 +
12220 +/*
12221 + * Set the MIPS, backplane and PCI clocks as closely as possible.
12222 + */
12223 +bool
12224 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
12225 +{
12226 + extifregs_t *eir = NULL;
12227 + chipcregs_t *cc = NULL;
12228 + mipsregs_t *mipsr = NULL;
12229 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
12230 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
12231 + uint32 pll_type, sync_mode;
12232 + uint ic_size, ic_lsize;
12233 + uint idx, i;
12234 + typedef struct {
12235 + uint32 mipsclock;
12236 + uint16 n;
12237 + uint32 sb;
12238 + uint32 pci33;
12239 + uint32 pci25;
12240 + } n3m_table_t;
12241 + static n3m_table_t BCMINITDATA(type1_table)[] = {
12242 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
12243 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
12244 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
12245 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
12246 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
12247 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
12248 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
12249 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
12250 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
12251 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
12252 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
12253 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
12254 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
12255 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
12256 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
12257 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
12258 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
12259 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
12260 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
12261 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
12262 + };
12263 + typedef struct {
12264 + uint32 mipsclock;
12265 + uint16 n;
12266 + uint32 m2; /* that is the clockcontrol_m2 */
12267 + } type3_table_t;
12268 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
12269 + { 150000000, 0x311, 0x4020005 },
12270 + { 200000000, 0x311, 0x4020003 },
12271 + };
12272 + typedef struct {
12273 + uint32 mipsclock;
12274 + uint32 sbclock;
12275 + uint16 n;
12276 + uint32 sb;
12277 + uint32 pci33;
12278 + uint32 m2;
12279 + uint32 m3;
12280 + uint32 ratio_cfg;
12281 + uint32 ratio_parm;
12282 + } n4m_table_t;
12283 +
12284 + static n4m_table_t BCMINITDATA(type2_table)[] = {
12285 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12286 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
12287 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
12288 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12289 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12290 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12291 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12292 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12293 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
12294 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12295 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12296 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12297 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
12298 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12299 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
12300 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12301 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
12302 + };
12303 +
12304 + static n4m_table_t BCMINITDATA(type4_table)[] = {
12305 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12306 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12307 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
12308 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12309 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12310 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12311 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12312 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12313 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
12314 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12315 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
12316 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12317 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
12318 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
12319 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
12320 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12321 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12322 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12323 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
12324 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
12325 + };
12326 +
12327 + static n4m_table_t BCMINITDATA(type7_table)[] = {
12328 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12329 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12330 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12331 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
12332 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
12333 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12334 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12335 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12336 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12337 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12338 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12339 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12340 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
12341 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
12342 + };
12343 +
12344 + ulong start, end, dst;
12345 + bool ret = FALSE;
12346 +
12347 + /* get index of the current core */
12348 + idx = sb_coreidx(sbh);
12349 + clockcontrol_m2 = NULL;
12350 +
12351 + /* switch to extif or chipc core */
12352 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
12353 + pll_type = PLL_TYPE1;
12354 + clockcontrol_n = &eir->clockcontrol_n;
12355 + clockcontrol_sb = &eir->clockcontrol_sb;
12356 + clockcontrol_pci = &eir->clockcontrol_pci;
12357 + clockcontrol_m2 = &cc->clockcontrol_m2;
12358 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
12359 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
12360 + if (pll_type == PLL_TYPE6) {
12361 + clockcontrol_n = NULL;
12362 + clockcontrol_sb = NULL;
12363 + clockcontrol_pci = NULL;
12364 + } else {
12365 + clockcontrol_n = &cc->clockcontrol_n;
12366 + clockcontrol_sb = &cc->clockcontrol_sb;
12367 + clockcontrol_pci = &cc->clockcontrol_pci;
12368 + clockcontrol_m2 = &cc->clockcontrol_m2;
12369 + }
12370 + } else
12371 + goto done;
12372 +
12373 + if (pll_type == PLL_TYPE6) {
12374 + /* Silence compilers */
12375 + orig_n = orig_sb = orig_pci = 0;
12376 + } else {
12377 + /* Store the current clock register values */
12378 + orig_n = R_REG(clockcontrol_n);
12379 + orig_sb = R_REG(clockcontrol_sb);
12380 + orig_pci = R_REG(clockcontrol_pci);
12381 + }
12382 +
12383 + if (pll_type == PLL_TYPE1) {
12384 + /* Keep the current PCI clock if not specified */
12385 + if (pciclock == 0) {
12386 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
12387 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
12388 + }
12389 +
12390 + /* Search for the closest MIPS clock less than or equal to a preferred value */
12391 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
12392 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
12393 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
12394 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
12395 + break;
12396 + }
12397 + if (i == 0) {
12398 + ret = FALSE;
12399 + goto done;
12400 + } else {
12401 + ret = TRUE;
12402 + i--;
12403 + }
12404 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
12405 +
12406 + /* No PLL change */
12407 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
12408 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
12409 + (orig_pci == BCMINIT(type1_table)[i].pci33))
12410 + goto done;
12411 +
12412 + /* Set the PLL controls */
12413 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
12414 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
12415 + if (pciclock == 25000000)
12416 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
12417 + else
12418 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
12419 +
12420 + /* Reset */
12421 + sb_watchdog(sbh, 1);
12422 +
12423 + while (1);
12424 + } else if ((pll_type == PLL_TYPE3) &&
12425 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
12426 + /* 5350 */
12427 + /* Search for the closest MIPS clock less than or equal to a preferred value */
12428 +
12429 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
12430 + if (type3_table[i].mipsclock > mipsclock)
12431 + break;
12432 + }
12433 + if (i == 0) {
12434 + ret = FALSE;
12435 + goto done;
12436 + } else {
12437 + ret = TRUE;
12438 + i--;
12439 + }
12440 + ASSERT(type3_table[i].mipsclock <= mipsclock);
12441 +
12442 + /* No PLL change */
12443 + orig_m2 = R_REG(&cc->clockcontrol_m2);
12444 + if ((orig_n == type3_table[i].n) &&
12445 + (orig_m2 == type3_table[i].m2)) {
12446 + goto done;
12447 + }
12448 +
12449 + /* Set the PLL controls */
12450 + W_REG(clockcontrol_n, type3_table[i].n);
12451 + W_REG(clockcontrol_m2, type3_table[i].m2);
12452 +
12453 + /* Reset */
12454 + sb_watchdog(sbh, 1);
12455 + while (1);
12456 + } else if ((pll_type == PLL_TYPE2) ||
12457 + (pll_type == PLL_TYPE4) ||
12458 + (pll_type == PLL_TYPE6) ||
12459 + (pll_type == PLL_TYPE7)) {
12460 + n4m_table_t *table = NULL, *te;
12461 + uint tabsz = 0;
12462 +
12463 + ASSERT(cc);
12464 +
12465 + orig_mips = R_REG(&cc->clockcontrol_mips);
12466 +
12467 + if (pll_type == PLL_TYPE6) {
12468 + uint32 new_mips = 0;
12469 +
12470 + ret = TRUE;
12471 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
12472 + new_mips = CC_T6_MMASK;
12473 +
12474 + if (orig_mips == new_mips)
12475 + goto done;
12476 +
12477 + W_REG(&cc->clockcontrol_mips, new_mips);
12478 + goto end_fill;
12479 + }
12480 +
12481 + if (pll_type == PLL_TYPE2) {
12482 + table = BCMINIT(type2_table);
12483 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
12484 + } else if (pll_type == PLL_TYPE4) {
12485 + table = BCMINIT(type4_table);
12486 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
12487 + } else if (pll_type == PLL_TYPE7) {
12488 + table = BCMINIT(type7_table);
12489 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
12490 + } else
12491 + ASSERT("No table for plltype" == NULL);
12492 +
12493 + /* Store the current clock register values */
12494 + orig_m2 = R_REG(&cc->clockcontrol_m2);
12495 + orig_ratio_parm = 0;
12496 + orig_ratio_cfg = 0;
12497 +
12498 + /* Look up current ratio */
12499 + for (i = 0; i < tabsz; i++) {
12500 + if ((orig_n == table[i].n) &&
12501 + (orig_sb == table[i].sb) &&
12502 + (orig_pci == table[i].pci33) &&
12503 + (orig_m2 == table[i].m2) &&
12504 + (orig_mips == table[i].m3)) {
12505 + orig_ratio_parm = table[i].ratio_parm;
12506 + orig_ratio_cfg = table[i].ratio_cfg;
12507 + break;
12508 + }
12509 + }
12510 +
12511 + /* Search for the closest MIPS clock greater or equal to a preferred value */
12512 + for (i = 0; i < tabsz; i++) {
12513 + ASSERT(table[i].mipsclock ==
12514 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
12515 + if ((mipsclock <= table[i].mipsclock) &&
12516 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
12517 + break;
12518 + }
12519 + if (i == tabsz) {
12520 + ret = FALSE;
12521 + goto done;
12522 + } else {
12523 + te = &table[i];
12524 + ret = TRUE;
12525 + }
12526 +
12527 + /* No PLL change */
12528 + if ((orig_n == te->n) &&
12529 + (orig_sb == te->sb) &&
12530 + (orig_pci == te->pci33) &&
12531 + (orig_m2 == te->m2) &&
12532 + (orig_mips == te->m3))
12533 + goto done;
12534 +
12535 + /* Set the PLL controls */
12536 + W_REG(clockcontrol_n, te->n);
12537 + W_REG(clockcontrol_sb, te->sb);
12538 + W_REG(clockcontrol_pci, te->pci33);
12539 + W_REG(&cc->clockcontrol_m2, te->m2);
12540 + W_REG(&cc->clockcontrol_mips, te->m3);
12541 +
12542 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
12543 + if ((pll_type == PLL_TYPE7) &&
12544 + (te->sb != te->m2) &&
12545 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
12546 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
12547 +
12548 + /* No ratio change */
12549 + if (orig_ratio_parm == te->ratio_parm)
12550 + goto end_fill;
12551 +
12552 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
12553 +
12554 + /* Preload the code into the cache */
12555 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
12556 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
12557 + while (start < end) {
12558 + cache_op(start, Fill_I);
12559 + start += ic_lsize;
12560 + }
12561 +
12562 + /* Copy the handler */
12563 + start = (ulong) &BCMINIT(handler);
12564 + end = (ulong) &BCMINIT(afterhandler);
12565 + dst = KSEG1ADDR(0x180);
12566 + for (i = 0; i < (end - start); i += 4)
12567 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
12568 +
12569 + /* Preload handler into the cache one line at a time */
12570 + for (i = 0; i < (end - start); i += 4)
12571 + cache_op(dst + i, Fill_I);
12572 +
12573 + /* Clear BEV bit */
12574 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
12575 +
12576 + /* Enable interrupts */
12577 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
12578 +
12579 + /* Enable MIPS timer interrupt */
12580 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
12581 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
12582 + ASSERT(mipsr);
12583 + W_REG(&mipsr->intmask, 1);
12584 +
12585 + start_fill:
12586 + /* step 1, set clock ratios */
12587 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
12588 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
12589 +
12590 + /* step 2: program timer intr */
12591 + W_REG(&mipsr->timer, 100);
12592 + (void) R_REG(&mipsr->timer);
12593 +
12594 + /* step 3, switch to async */
12595 + sync_mode = MFC0(C0_BROADCOM, 4);
12596 + MTC0(C0_BROADCOM, 4, 1 << 22);
12597 +
12598 + /* step 4, set cfg active */
12599 + MTC0(C0_BROADCOM, 2, 0x9);
12600 +
12601 +
12602 + /* steps 5 & 6 */
12603 + __asm__ __volatile__ (
12604 + ".set\tmips3\n\t"
12605 + "wait\n\t"
12606 + ".set\tmips0"
12607 + );
12608 +
12609 + /* step 7, clear cfg_active */
12610 + MTC0(C0_BROADCOM, 2, 0);
12611 +
12612 + /* Additional Step: set back to orig sync mode */
12613 + MTC0(C0_BROADCOM, 4, sync_mode);
12614 +
12615 + /* step 8, fake soft reset */
12616 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
12617 +
12618 + end_fill:
12619 + /* step 9 set watchdog timer */
12620 + sb_watchdog(sbh, 20);
12621 + (void) R_REG(&cc->chipid);
12622 +
12623 + /* step 11 */
12624 + __asm__ __volatile__ (
12625 + ".set\tmips3\n\t"
12626 + "sync\n\t"
12627 + "wait\n\t"
12628 + ".set\tmips0"
12629 + );
12630 + while (1);
12631 + }
12632 +
12633 +done:
12634 + /* switch back to previous core */
12635 + sb_setcoreidx(sbh, idx);
12636 +
12637 + return ret;
12638 +}
12639 +
12640 +/*
12641 + * This also must be run from the cache on 47xx
12642 + * so there are no mips core BIU ops in progress
12643 + * when the PFC is enabled.
12644 + */
12645 +
12646 +static void
12647 +BCMINITFN(_enable_pfc)(uint32 mode)
12648 +{
12649 + /* write range */
12650 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
12651 +
12652 + /* enable */
12653 + *(volatile uint32 *)PFC_CR0 = mode;
12654 +}
12655 +
12656 +void
12657 +BCMINITFN(enable_pfc)(uint32 mode)
12658 +{
12659 + ulong start, end;
12660 + int i;
12661 +
12662 + /* If auto then choose the correct mode for this
12663 + platform, currently we only ever select one mode */
12664 + if (mode == PFC_AUTO)
12665 + mode = PFC_INST;
12666 +
12667 + /* enable prefetch cache if available */
12668 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
12669 + start = (ulong) &BCMINIT(_enable_pfc);
12670 + end = (ulong) &BCMINIT(enable_pfc);
12671 +
12672 + /* Preload handler into the cache one line at a time */
12673 + for (i = 0; i < (end - start); i += 4)
12674 + cache_op(start + i, Fill_I);
12675 +
12676 + BCMINIT(_enable_pfc)(mode);
12677 + }
12678 +}
12679 +
12680 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
12681 +uint32
12682 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
12683 +{
12684 + sbmemcregs_t *memc;
12685 + uint32 ret = 0;
12686 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
12687 + uint idx, rev;
12688 +
12689 + idx = sb_coreidx(sbh);
12690 +
12691 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
12692 + if (memc == 0)
12693 + goto out;
12694 +
12695 + rev = sb_corerev(sbh);
12696 +
12697 + config = R_REG(&memc->config);
12698 + wr = R_REG(&memc->wrncdlcor);
12699 + rd = R_REG(&memc->rdncdlcor);
12700 + misc = R_REG(&memc->miscdlyctl);
12701 + dqsg = R_REG(&memc->dqsgatencdl);
12702 +
12703 + rd &= MEMC_RDNCDLCOR_RD_MASK;
12704 + wr &= MEMC_WRNCDLCOR_WR_MASK;
12705 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
12706 +
12707 + if (config & MEMC_CONFIG_DDR) {
12708 + ret = (wr << 16) | (rd << 8) | dqsg;
12709 + } else {
12710 + if (rev > 0)
12711 + cd = rd;
12712 + else
12713 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
12714 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
12715 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
12716 + ret = (sm << 16) | (sd << 8) | cd;
12717 + }
12718 +
12719 +out:
12720 + /* switch back to previous core */
12721 + sb_setcoreidx(sbh, idx);
12722 +
12723 + return ret;
12724 +}
12725 +
12726 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
12727 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
12728 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2005-11-07 23:53:20.981131500 +0100
12729 @@ -0,0 +1,588 @@
12730 +/*
12731 + * Low-Level PCI and SB support for BCM47xx
12732 + *
12733 + * Copyright 2005, Broadcom Corporation
12734 + * All Rights Reserved.
12735 + *
12736 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12737 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12738 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12739 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12740 + *
12741 + * $Id$
12742 + */
12743 +
12744 +#include <typedefs.h>
12745 +#include <pcicfg.h>
12746 +#include <bcmdevs.h>
12747 +#include <sbconfig.h>
12748 +#include <osl.h>
12749 +#include <sbutils.h>
12750 +#include <sbpci.h>
12751 +#include <bcmendian.h>
12752 +#include <bcmutils.h>
12753 +#include <bcmnvram.h>
12754 +#include <hndmips.h>
12755 +
12756 +/* Can free sbpci_init() memory after boot */
12757 +#ifndef linux
12758 +#define __init
12759 +#endif
12760 +
12761 +/* Emulated configuration space */
12762 +static pci_config_regs sb_config_regs[SB_MAXCORES];
12763 +
12764 +/* Banned cores */
12765 +static uint16 pci_ban[32] = { 0 };
12766 +static uint pci_banned = 0;
12767 +
12768 +/* CardBus mode */
12769 +static bool cardbus = FALSE;
12770 +
12771 +/* Disable PCI host core */
12772 +static bool pci_disabled = FALSE;
12773 +
12774 +/*
12775 + * Functions for accessing external PCI configuration space
12776 + */
12777 +
12778 +/* Assume one-hot slot wiring */
12779 +#define PCI_SLOT_MAX 16
12780 +
12781 +static uint32
12782 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
12783 +{
12784 + uint coreidx;
12785 + sbpciregs_t *regs;
12786 + uint32 addr = 0;
12787 +
12788 + /* CardBusMode supports only one device */
12789 + if (cardbus && dev > 1)
12790 + return 0;
12791 +
12792 + coreidx = sb_coreidx(sbh);
12793 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
12794 +
12795 + /* Type 0 transaction */
12796 + if (bus == 1) {
12797 + /* Skip unwired slots */
12798 + if (dev < PCI_SLOT_MAX) {
12799 + /* Slide the PCI window to the appropriate slot */
12800 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
12801 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
12802 + (func << 8) | (off & ~3);
12803 + }
12804 + }
12805 +
12806 + /* Type 1 transaction */
12807 + else {
12808 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
12809 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
12810 + }
12811 +
12812 + sb_setcoreidx(sbh, coreidx);
12813 +
12814 + return addr;
12815 +}
12816 +
12817 +static int
12818 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12819 +{
12820 + uint32 addr, *reg = NULL, val;
12821 + int ret = 0;
12822 +
12823 + if (pci_disabled ||
12824 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
12825 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
12826 + BUSPROBE(val, reg))
12827 + val = 0xffffffff;
12828 +
12829 + val >>= 8 * (off & 3);
12830 + if (len == 4)
12831 + *((uint32 *) buf) = val;
12832 + else if (len == 2)
12833 + *((uint16 *) buf) = (uint16) val;
12834 + else if (len == 1)
12835 + *((uint8 *) buf) = (uint8) val;
12836 + else
12837 + ret = -1;
12838 +
12839 + if (reg)
12840 + REG_UNMAP(reg);
12841 +
12842 + return ret;
12843 +}
12844 +
12845 +static int
12846 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12847 +{
12848 + uint32 addr, *reg = NULL, val;
12849 + int ret = 0;
12850 +
12851 + if (pci_disabled ||
12852 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
12853 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
12854 + BUSPROBE(val, reg))
12855 + goto done;
12856 +
12857 + if (len == 4)
12858 + val = *((uint32 *) buf);
12859 + else if (len == 2) {
12860 + val &= ~(0xffff << (8 * (off & 3)));
12861 + val |= *((uint16 *) buf) << (8 * (off & 3));
12862 + } else if (len == 1) {
12863 + val &= ~(0xff << (8 * (off & 3)));
12864 + val |= *((uint8 *) buf) << (8 * (off & 3));
12865 + } else
12866 + ret = -1;
12867 +
12868 + W_REG(reg, val);
12869 +
12870 + done:
12871 + if (reg)
12872 + REG_UNMAP(reg);
12873 +
12874 + return ret;
12875 +}
12876 +
12877 +/*
12878 + * Functions for accessing translated SB configuration space
12879 + */
12880 +
12881 +static int
12882 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12883 +{
12884 + pci_config_regs *cfg;
12885 +
12886 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
12887 + return -1;
12888 + cfg = &sb_config_regs[dev];
12889 +
12890 + ASSERT(ISALIGNED(off, len));
12891 + ASSERT(ISALIGNED((uintptr)buf, len));
12892 +
12893 + if (len == 4)
12894 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
12895 + else if (len == 2)
12896 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
12897 + else if (len == 1)
12898 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
12899 + else
12900 + return -1;
12901 +
12902 + return 0;
12903 +}
12904 +
12905 +static int
12906 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12907 +{
12908 + uint coreidx, n;
12909 + void *regs;
12910 + sbconfig_t *sb;
12911 + pci_config_regs *cfg;
12912 +
12913 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
12914 + return -1;
12915 + cfg = &sb_config_regs[dev];
12916 +
12917 + ASSERT(ISALIGNED(off, len));
12918 + ASSERT(ISALIGNED((uintptr)buf, len));
12919 +
12920 + /* Emulate BAR sizing */
12921 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
12922 + len == 4 && *((uint32 *) buf) == ~0) {
12923 + coreidx = sb_coreidx(sbh);
12924 + if ((regs = sb_setcoreidx(sbh, dev))) {
12925 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12926 + /* Highest numbered address match register */
12927 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
12928 + if (off == OFFSETOF(pci_config_regs, base[0]))
12929 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
12930 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
12931 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
12932 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
12933 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
12934 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
12935 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
12936 + }
12937 + sb_setcoreidx(sbh, coreidx);
12938 + return 0;
12939 + }
12940 +
12941 + if (len == 4)
12942 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
12943 + else if (len == 2)
12944 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
12945 + else if (len == 1)
12946 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
12947 + else
12948 + return -1;
12949 +
12950 + return 0;
12951 +}
12952 +
12953 +int
12954 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12955 +{
12956 + if (bus == 0)
12957 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
12958 + else
12959 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
12960 +}
12961 +
12962 +int
12963 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12964 +{
12965 + if (bus == 0)
12966 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
12967 + else
12968 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
12969 +}
12970 +
12971 +void
12972 +sbpci_ban(uint16 core)
12973 +{
12974 + if (pci_banned < ARRAYSIZE(pci_ban))
12975 + pci_ban[pci_banned++] = core;
12976 +}
12977 +
12978 +static int
12979 +sbpci_init_pci(sb_t *sbh)
12980 +{
12981 + uint chip, chiprev, chippkg, host;
12982 + uint32 boardflags;
12983 + sbpciregs_t *pci;
12984 + sbconfig_t *sb;
12985 + uint32 val;
12986 +
12987 + chip = sb_chip(sbh);
12988 + chiprev = sb_chiprev(sbh);
12989 + chippkg = sb_chippkg(sbh);
12990 +
12991 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
12992 + printf("PCI: no core\n");
12993 + pci_disabled = TRUE;
12994 + return -1;
12995 + }
12996 + sb_core_reset(sbh, 0);
12997 +
12998 + boardflags = (uint32) getintvar(NULL, "boardflags");
12999 +
13000 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
13001 + pci_disabled = TRUE;
13002 +
13003 + /*
13004 + * The 200-pin BCM4712 package does not bond out PCI. Even when
13005 + * PCI is bonded out, some boards may leave the pins
13006 + * floating.
13007 + */
13008 + if (((chip == BCM4712_DEVICE_ID) &&
13009 + ((chippkg == BCM4712SMALL_PKG_ID) ||
13010 + (chippkg == BCM4712MID_PKG_ID))) ||
13011 + (boardflags & BFL_NOPCI))
13012 + pci_disabled = TRUE;
13013 +
13014 + /*
13015 + * If the PCI core should not be touched (disabled, not bonded
13016 + * out, or pins floating), do not even attempt to access core
13017 + * registers. Otherwise, try to determine if it is in host
13018 + * mode.
13019 + */
13020 + if (pci_disabled)
13021 + host = 0;
13022 + else
13023 + host = !BUSPROBE(val, &pci->control);
13024 +
13025 + if (!host) {
13026 + /* Disable PCI interrupts in client mode */
13027 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
13028 + W_REG(&sb->sbintvec, 0);
13029 +
13030 + /* Disable the PCI bridge in client mode */
13031 + sbpci_ban(SB_PCI);
13032 + printf("PCI: Disabled\n");
13033 + } else {
13034 + /* Reset the external PCI bus and enable the clock */
13035 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
13036 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
13037 + OSL_DELAY(150); /* delay > 100 us */
13038 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
13039 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
13040 + OSL_DELAY(1); /* delay 1 us */
13041 +
13042 + /* Enable CardBusMode */
13043 + cardbus = nvram_match("cardbus", "1");
13044 + if (cardbus) {
13045 + printf("PCI: Enabling CardBus\n");
13046 + /* GPIO 1 resets the CardBus device on bcm94710ap */
13047 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
13048 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
13049 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
13050 + }
13051 +
13052 + /* 64 MB I/O access window */
13053 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
13054 + /* 64 MB configuration access window */
13055 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
13056 + /* 1 GB memory access window */
13057 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
13058 +
13059 + /* Enable PCI bridge BAR0 prefetch and burst */
13060 + val = 6;
13061 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
13062 +
13063 + /* Enable PCI interrupts */
13064 + W_REG(&pci->intmask, PCI_INTA);
13065 + }
13066 +
13067 + return 0;
13068 +}
13069 +
13070 +static int
13071 +sbpci_init_cores(sb_t *sbh)
13072 +{
13073 + uint chip, chiprev, chippkg, coreidx, i;
13074 + sbconfig_t *sb;
13075 + pci_config_regs *cfg;
13076 + void *regs;
13077 + char varname[8];
13078 + uint wlidx = 0;
13079 + uint16 vendor, core;
13080 + uint8 class, subclass, progif;
13081 + uint32 val;
13082 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
13083 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
13084 +
13085 + chip = sb_chip(sbh);
13086 + chiprev = sb_chiprev(sbh);
13087 + chippkg = sb_chippkg(sbh);
13088 + coreidx = sb_coreidx(sbh);
13089 +
13090 + /* Scan the SB bus */
13091 + bzero(sb_config_regs, sizeof(sb_config_regs));
13092 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
13093 + cfg->vendor = 0xffff;
13094 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
13095 + continue;
13096 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
13097 +
13098 + /* Read ID register and parse vendor and core */
13099 + val = R_REG(&sb->sbidhigh);
13100 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
13101 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
13102 + progif = 0;
13103 +
13104 + /* Check if this core is banned */
13105 + for (i = 0; i < pci_banned; i++)
13106 + if (core == pci_ban[i])
13107 + break;
13108 + if (i < pci_banned)
13109 + continue;
13110 +
13111 + /* Known vendor translations */
13112 + switch (vendor) {
13113 + case SB_VEND_BCM:
13114 + vendor = VENDOR_BROADCOM;
13115 + break;
13116 + }
13117 +
13118 + /* Determine class based on known core codes */
13119 + switch (core) {
13120 + case SB_ILINE20:
13121 + class = PCI_CLASS_NET;
13122 + subclass = PCI_NET_ETHER;
13123 + core = BCM47XX_ILINE_ID;
13124 + break;
13125 + case SB_ILINE100:
13126 + class = PCI_CLASS_NET;
13127 + subclass = PCI_NET_ETHER;
13128 + core = BCM4610_ILINE_ID;
13129 + break;
13130 + case SB_ENET:
13131 + class = PCI_CLASS_NET;
13132 + subclass = PCI_NET_ETHER;
13133 + core = BCM47XX_ENET_ID;
13134 + break;
13135 + case SB_SDRAM:
13136 + case SB_MEMC:
13137 + class = PCI_CLASS_MEMORY;
13138 + subclass = PCI_MEMORY_RAM;
13139 + break;
13140 + case SB_PCI:
13141 + class = PCI_CLASS_BRIDGE;
13142 + subclass = PCI_BRIDGE_PCI;
13143 + break;
13144 + case SB_MIPS:
13145 + case SB_MIPS33:
13146 + class = PCI_CLASS_CPU;
13147 + subclass = PCI_CPU_MIPS;
13148 + break;
13149 + case SB_CODEC:
13150 + class = PCI_CLASS_COMM;
13151 + subclass = PCI_COMM_MODEM;
13152 + core = BCM47XX_V90_ID;
13153 + break;
13154 + case SB_USB:
13155 + class = PCI_CLASS_SERIAL;
13156 + subclass = PCI_SERIAL_USB;
13157 + progif = 0x10; /* OHCI */
13158 + core = BCM47XX_USB_ID;
13159 + break;
13160 + case SB_USB11H:
13161 + class = PCI_CLASS_SERIAL;
13162 + subclass = PCI_SERIAL_USB;
13163 + progif = 0x10; /* OHCI */
13164 + core = BCM47XX_USBH_ID;
13165 + break;
13166 + case SB_USB11D:
13167 + class = PCI_CLASS_SERIAL;
13168 + subclass = PCI_SERIAL_USB;
13169 + core = BCM47XX_USBD_ID;
13170 + break;
13171 + case SB_IPSEC:
13172 + class = PCI_CLASS_CRYPT;
13173 + subclass = PCI_CRYPT_NETWORK;
13174 + core = BCM47XX_IPSEC_ID;
13175 + break;
13176 + case SB_ROBO:
13177 + class = PCI_CLASS_NET;
13178 + subclass = PCI_NET_OTHER;
13179 + core = BCM47XX_ROBO_ID;
13180 + break;
13181 + case SB_EXTIF:
13182 + case SB_CC:
13183 + class = PCI_CLASS_MEMORY;
13184 + subclass = PCI_MEMORY_FLASH;
13185 + break;
13186 + case SB_D11:
13187 + class = PCI_CLASS_NET;
13188 + subclass = PCI_NET_OTHER;
13189 + /* Let an nvram variable override this */
13190 + sprintf(varname, "wl%did", wlidx);
13191 + wlidx++;
13192 + if ((core = getintvar(NULL, varname)) == 0) {
13193 + if (chip == BCM4712_DEVICE_ID) {
13194 + if (chippkg == BCM4712SMALL_PKG_ID)
13195 + core = BCM4306_D11G_ID;
13196 + else
13197 + core = BCM4306_D11DUAL_ID;
13198 + } else {
13199 + /* 4310 */
13200 + core = BCM4310_D11B_ID;
13201 + }
13202 + }
13203 + break;
13204 +
13205 + default:
13206 + class = subclass = progif = 0xff;
13207 + break;
13208 + }
13209 +
13210 + /* Supported translations */
13211 + cfg->vendor = htol16(vendor);
13212 + cfg->device = htol16(core);
13213 + cfg->rev_id = chiprev;
13214 + cfg->prog_if = progif;
13215 + cfg->sub_class = subclass;
13216 + cfg->base_class = class;
13217 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
13218 + cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
13219 + cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
13220 + cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
13221 + cfg->base[4] = 0;
13222 + cfg->base[5] = 0;
13223 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
13224 + cfg->header_type = PCI_HEADER_BRIDGE;
13225 + else
13226 + cfg->header_type = PCI_HEADER_NORMAL;
13227 + /* Save core interrupt flag */
13228 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
13229 + /* Default to MIPS shared interrupt 0 */
13230 + cfg->int_line = 0;
13231 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
13232 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
13233 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
13234 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
13235 + val = R_REG(&sb->sbipsflag);
13236 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
13237 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
13238 + break;
13239 + }
13240 + if (cfg->int_line > 4)
13241 + cfg->int_line = 0;
13242 + }
13243 + /* Emulated core */
13244 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
13245 + }
13246 +
13247 + sb_setcoreidx(sbh, coreidx);
13248 + return 0;
13249 +}
13250 +
13251 +int __init
13252 +sbpci_init(sb_t *sbh)
13253 +{
13254 + sbpci_init_pci(sbh);
13255 + sbpci_init_cores(sbh);
13256 + return 0;
13257 +}
13258 +
13259 +void
13260 +sbpci_check(sb_t *sbh)
13261 +{
13262 + uint coreidx;
13263 + sbpciregs_t *pci;
13264 + uint32 sbtopci1;
13265 + uint32 buf[64], *ptr, i;
13266 + ulong pa;
13267 + volatile uint j;
13268 +
13269 + coreidx = sb_coreidx(sbh);
13270 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
13271 +
13272 + /* Clear the test array */
13273 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
13274 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
13275 + memset(ptr, 0, sizeof(buf));
13276 +
13277 + /* Point PCI window 1 to memory */
13278 + sbtopci1 = R_REG(&pci->sbtopci1);
13279 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
13280 +
13281 + /* Fill the test array via PCI window 1 */
13282 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
13283 + for (i = 0; i < ARRAYSIZE(buf); i++) {
13284 + for (j = 0; j < 2; j++);
13285 + W_REG(&ptr[i], i);
13286 + }
13287 + REG_UNMAP(ptr);
13288 +
13289 + /* Restore PCI window 1 */
13290 + W_REG(&pci->sbtopci1, sbtopci1);
13291 +
13292 + /* Check the test array */
13293 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
13294 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
13295 + for (i = 0; i < ARRAYSIZE(buf); i++) {
13296 + if (ptr[i] != i)
13297 + break;
13298 + }
13299 +
13300 + /* Change the clock if the test fails */
13301 + if (i < ARRAYSIZE(buf)) {
13302 + uint32 req, cur;
13303 +
13304 + cur = sb_clock(sbh);
13305 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
13306 + for (req = 104000000; req < 176000000; req += 4000000) {
13307 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
13308 + /* This will only reset if the clocks are valid and have changed */
13309 + sb_mips_setclock(sbh, req, 0, 0);
13310 + }
13311 + /* Should not reach here */
13312 + ASSERT(0);
13313 + }
13314 +
13315 + sb_setcoreidx(sbh, coreidx);
13316 +}
13317 +
13318 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
13319 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
13320 +++ linux.dev/arch/mips/bcm947xx/setup.c 2005-11-08 00:11:55.346775000 +0100
13321 @@ -0,0 +1,272 @@
13322 +/*
13323 + * Generic setup routines for Broadcom MIPS boards
13324 + *
13325 + * Copyright 2005, Broadcom Corporation
13326 + * All Rights Reserved.
13327 + *
13328 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13329 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13330 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13331 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13332 + *
13333 + * $Id$
13334 + */
13335 +
13336 +#include <linux/config.h>
13337 +#include <linux/init.h>
13338 +#include <linux/kernel.h>
13339 +#include <linux/serialP.h>
13340 +#include <linux/ide.h>
13341 +#include <asm/bootinfo.h>
13342 +#include <asm/cpu.h>
13343 +#include <asm/time.h>
13344 +#include <asm/reboot.h>
13345 +
13346 +#ifdef CONFIG_MTD_PARTITIONS
13347 +#include <linux/mtd/mtd.h>
13348 +#include <linux/mtd/partitions.h>
13349 +#endif
13350 +
13351 +#include <typedefs.h>
13352 +#include <osl.h>
13353 +#include <sbutils.h>
13354 +#include <bcmutils.h>
13355 +#include <bcmnvram.h>
13356 +#include <sbmips.h>
13357 +#include <trxhdr.h>
13358 +
13359 +extern void bcm947xx_time_init(void);
13360 +extern void bcm947xx_timer_setup(struct irqaction *irq);
13361 +
13362 +#ifdef CONFIG_REMOTE_DEBUG
13363 +extern void set_debug_traps(void);
13364 +extern void rs_kgdb_hook(struct serial_state *);
13365 +extern void breakpoint(void);
13366 +#endif
13367 +
13368 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
13369 +extern struct ide_ops std_ide_ops;
13370 +#endif
13371 +
13372 +/* Global SB handle */
13373 +sb_t *bcm947xx_sbh = NULL;
13374 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
13375 +EXPORT_SYMBOL(bcm947xx_sbh);
13376 +EXPORT_SYMBOL(bcm947xx_sbh_lock);
13377 +
13378 +/* Convenience */
13379 +#define sbh bcm947xx_sbh
13380 +#define sbh_lock bcm947xx_sbh_lock
13381 +
13382 +/* Kernel command line */
13383 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
13384 +
13385 +void
13386 +bcm947xx_machine_restart(char *command)
13387 +{
13388 + printk("Please stand by while rebooting the system...\n");
13389 +
13390 + /* Set the watchdog timer to reset immediately */
13391 + __cli();
13392 + sb_watchdog(sbh, 1);
13393 + while (1);
13394 +}
13395 +
13396 +void
13397 +bcm947xx_machine_halt(void)
13398 +{
13399 + printk("System halted\n");
13400 +
13401 + /* Disable interrupts and watchdog and spin forever */
13402 + __cli();
13403 + sb_watchdog(sbh, 0);
13404 + while (1);
13405 +}
13406 +
13407 +#ifdef CONFIG_SERIAL
13408 +
13409 +static struct serial_struct rs = {
13410 + line: 0,
13411 + flags: ASYNC_BOOT_AUTOCONF,
13412 + io_type: SERIAL_IO_MEM,
13413 +};
13414 +
13415 +static void __init
13416 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
13417 +{
13418 + rs.iomem_base = regs;
13419 + rs.irq = irq + 2;
13420 + rs.baud_base = baud_base / 16;
13421 + rs.iomem_reg_shift = reg_shift;
13422 +
13423 + early_serial_setup(&rs);
13424 +
13425 + rs.line++;
13426 +}
13427 +
13428 +static void __init
13429 +serial_setup(sb_t *sbh)
13430 +{
13431 + sb_serial_init(sbh, serial_add);
13432 +
13433 +#ifdef CONFIG_REMOTE_DEBUG
13434 + /* Use the last port for kernel debugging */
13435 + if (rs.iomem_base)
13436 + rs_kgdb_hook(&rs);
13437 +#endif
13438 +}
13439 +
13440 +#endif /* CONFIG_SERIAL */
13441 +
13442 +void __init
13443 +brcm_setup(void)
13444 +{
13445 + char *value;
13446 +
13447 + /* Get global SB handle */
13448 + sbh = sb_kattach();
13449 +
13450 + /* Initialize clocks and interrupts */
13451 + sb_mips_init(sbh);
13452 +
13453 + if (BCM330X(current_cpu_data.processor_id) &&
13454 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
13455 + /*
13456 + * Now that the sbh is inited set the proper PFC value
13457 + */
13458 + printk("Setting the PFC to its default value\n");
13459 + enable_pfc(PFC_AUTO);
13460 + }
13461 +
13462 +
13463 +#ifdef CONFIG_SERIAL
13464 + /* Initialize UARTs */
13465 + serial_setup(sbh);
13466 +#endif
13467 +
13468 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
13469 + ide_ops = &std_ide_ops;
13470 +#endif
13471 +
13472 + /* Override default command line arguments */
13473 + value = nvram_get("kernel_cmdline");
13474 + if (value && strlen(value) && strncmp(value, "empty", 5))
13475 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
13476 +
13477 +
13478 + /* Generic setup */
13479 + _machine_restart = bcm947xx_machine_restart;
13480 + _machine_halt = bcm947xx_machine_halt;
13481 + _machine_power_off = bcm947xx_machine_halt;
13482 +
13483 + board_time_init = bcm947xx_time_init;
13484 + board_timer_setup = bcm947xx_timer_setup;
13485 +}
13486 +
13487 +const char *
13488 +get_system_type(void)
13489 +{
13490 + static char s[32];
13491 +
13492 + if (bcm947xx_sbh) {
13493 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
13494 + sb_chiprev(bcm947xx_sbh));
13495 + return s;
13496 + }
13497 + else
13498 + return "Broadcom BCM947XX";
13499 +}
13500 +
13501 +void __init
13502 +bus_error_init(void)
13503 +{
13504 +}
13505 +
13506 +#ifdef CONFIG_MTD_PARTITIONS
13507 +
13508 +static struct mtd_partition bcm947xx_parts[] = {
13509 + { name: "pmon", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
13510 + { name: "linux", offset: 0, size: 0, },
13511 + { name: "rootfs", offset: 0, size: 0, },
13512 + { name: "nvram", offset: 0, size: 0, },
13513 + { name: "OpenWrt", offset: 0, size: 0, },
13514 + { name: NULL, },
13515 +};
13516 +
13517 +static int __init
13518 +find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
13519 +{
13520 + struct trx_header *trx;
13521 + unsigned char buf[512];
13522 + int off;
13523 + size_t len;
13524 +
13525 + trx = (struct trx_header *) buf;
13526 +
13527 + for (off = (256*1024); off < size; off += mtd->erasesize) {
13528 + memset(buf, 0xe5, sizeof(buf));
13529 +
13530 + /*
13531 + * Read into buffer
13532 + */
13533 + if (MTD_READ(mtd, off, sizeof(buf), &len, buf) ||
13534 + len != sizeof(buf))
13535 + continue;
13536 +
13537 + /* found a TRX header */
13538 + if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
13539 + part->offset = le32_to_cpu(trx->offsets[2]) ? :
13540 + le32_to_cpu(trx->offsets[1]);
13541 + part->size = le32_to_cpu(trx->len);
13542 +
13543 + part->size -= part->offset;
13544 + part->offset += off;
13545 +
13546 + goto done;
13547 + }
13548 + }
13549 +
13550 + printk(KERN_NOTICE
13551 + "%s: Couldn't find root filesystem\n",
13552 + mtd->name);
13553 + return -1;
13554 +
13555 + done:
13556 + return part->size;
13557 +}
13558 +
13559 +struct mtd_partition * __init
13560 +init_mtd_partitions(struct mtd_info *mtd, size_t size)
13561 +{
13562 +
13563 + /* boot loader */
13564 + bcm947xx_parts[0].offset=0;
13565 + bcm947xx_parts[0].size=256*1024;
13566 +
13567 + /* nvram */
13568 + bcm947xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
13569 + bcm947xx_parts[3].size = size - bcm947xx_parts[3].offset;
13570 +
13571 + /* Size linux (kernel and rootfs) */
13572 + bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
13573 + bcm947xx_parts[1].size = bcm947xx_parts[3].offset - bcm947xx_parts[1].offset;
13574 +
13575 + /* Find and size rootfs */
13576 + if (find_root(mtd,size,&bcm947xx_parts[2])==0) {
13577 + /* entirely jffs2 */
13578 + bcm947xx_parts[2].size = bcm947xx_parts[3].offset - bcm947xx_parts[2].offset;
13579 + bcm947xx_parts[4].name = NULL;
13580 + } else {
13581 + /* legacy setup */
13582 + /* calculate leftover flash, and assign it to the jffs2 partition */
13583 + bcm947xx_parts[4].offset = bcm947xx_parts[2].offset + bcm947xx_parts[2].size;
13584 + bcm947xx_parts[4].offset = ROUNDUP(bcm947xx_parts[4].offset, mtd->erasesize);
13585 + bcm947xx_parts[4].size = bcm947xx_parts[3].offset - bcm947xx_parts[4].offset;
13586 + }
13587 +
13588 + return bcm947xx_parts;
13589 +}
13590 +
13591 +EXPORT_SYMBOL(init_mtd_partitions);
13592 +
13593 +#endif
13594 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
13595 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
13596 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2005-11-08 00:54:43.022739000 +0100
13597 @@ -0,0 +1,418 @@
13598 +/*
13599 + * Broadcom SiliconBackplane chipcommon serial flash interface
13600 + *
13601 + * Copyright 2005, Broadcom Corporation
13602 + * All Rights Reserved.
13603 + *
13604 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13605 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13606 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13607 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13608 + *
13609 + * $Id$
13610 + */
13611 +
13612 +#include <osl.h>
13613 +#include <typedefs.h>
13614 +#include <sbconfig.h>
13615 +#include <sbchipc.h>
13616 +#include <mipsinc.h>
13617 +#include <bcmutils.h>
13618 +#include <bcmdevs.h>
13619 +#include <sflash.h>
13620 +
13621 +/* Private global state */
13622 +static struct sflash sflash;
13623 +
13624 +/* Issue a serial flash command */
13625 +static INLINE void
13626 +sflash_cmd(chipcregs_t *cc, uint opcode)
13627 +{
13628 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
13629 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
13630 +}
13631 +
13632 +/* Initialize serial flash access */
13633 +struct sflash *
13634 +sflash_init(chipcregs_t *cc)
13635 +{
13636 + uint32 id, id2;
13637 +
13638 + bzero(&sflash, sizeof(sflash));
13639 +
13640 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
13641 +
13642 + switch (sflash.type) {
13643 + case SFLASH_ST:
13644 + /* Probe for ST chips */
13645 + sflash_cmd(cc, SFLASH_ST_DP);
13646 + sflash_cmd(cc, SFLASH_ST_RES);
13647 + id = R_REG(&cc->flashdata);
13648 + switch (id) {
13649 + case 0x11:
13650 + /* ST M25P20 2 Mbit Serial Flash */
13651 + sflash.blocksize = 64 * 1024;
13652 + sflash.numblocks = 4;
13653 + break;
13654 + case 0x12:
13655 + /* ST M25P40 4 Mbit Serial Flash */
13656 + sflash.blocksize = 64 * 1024;
13657 + sflash.numblocks = 8;
13658 + break;
13659 + case 0x13:
13660 + /* ST M25P80 8 Mbit Serial Flash */
13661 + sflash.blocksize = 64 * 1024;
13662 + sflash.numblocks = 16;
13663 + break;
13664 + case 0x14:
13665 + /* ST M25P16 16 Mbit Serial Flash */
13666 + sflash.blocksize = 64 * 1024;
13667 + sflash.numblocks = 32;
13668 + break;
13669 + case 0x15:
13670 + /* ST M25P32 32 Mbit Serial Flash */
13671 + sflash.blocksize = 64 * 1024;
13672 + sflash.numblocks = 64;
13673 + break;
13674 + case 0xbf:
13675 + W_REG(&cc->flashaddress, 1);
13676 + sflash_cmd(cc, SFLASH_ST_RES);
13677 + id2 = R_REG(&cc->flashdata);
13678 + if (id2 == 0x44) {
13679 + /* SST M25VF80 4 Mbit Serial Flash */
13680 + sflash.blocksize = 64 * 1024;
13681 + sflash.numblocks = 8;
13682 + }
13683 + break;
13684 + }
13685 + break;
13686 +
13687 + case SFLASH_AT:
13688 + /* Probe for Atmel chips */
13689 + sflash_cmd(cc, SFLASH_AT_STATUS);
13690 + id = R_REG(&cc->flashdata) & 0x3c;
13691 + switch (id) {
13692 + case 0xc:
13693 + /* Atmel AT45DB011 1Mbit Serial Flash */
13694 + sflash.blocksize = 256;
13695 + sflash.numblocks = 512;
13696 + break;
13697 + case 0x14:
13698 + /* Atmel AT45DB021 2Mbit Serial Flash */
13699 + sflash.blocksize = 256;
13700 + sflash.numblocks = 1024;
13701 + break;
13702 + case 0x1c:
13703 + /* Atmel AT45DB041 4Mbit Serial Flash */
13704 + sflash.blocksize = 256;
13705 + sflash.numblocks = 2048;
13706 + break;
13707 + case 0x24:
13708 + /* Atmel AT45DB081 8Mbit Serial Flash */
13709 + sflash.blocksize = 256;
13710 + sflash.numblocks = 4096;
13711 + break;
13712 + case 0x2c:
13713 + /* Atmel AT45DB161 16Mbit Serial Flash */
13714 + sflash.blocksize = 512;
13715 + sflash.numblocks = 4096;
13716 + break;
13717 + case 0x34:
13718 + /* Atmel AT45DB321 32Mbit Serial Flash */
13719 + sflash.blocksize = 512;
13720 + sflash.numblocks = 8192;
13721 + break;
13722 + case 0x3c:
13723 + /* Atmel AT45DB642 64Mbit Serial Flash */
13724 + sflash.blocksize = 1024;
13725 + sflash.numblocks = 8192;
13726 + break;
13727 + }
13728 + break;
13729 + }
13730 +
13731 + sflash.size = sflash.blocksize * sflash.numblocks;
13732 + return sflash.size ? &sflash : NULL;
13733 +}
13734 +
13735 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
13736 +int
13737 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
13738 +{
13739 + int cnt;
13740 + uint32 *from, *to;
13741 +
13742 + if (!len)
13743 + return 0;
13744 +
13745 + if ((offset + len) > sflash.size)
13746 + return -22;
13747 +
13748 + if ((len >= 4) && (offset & 3))
13749 + cnt = 4 - (offset & 3);
13750 + else if ((len >= 4) && ((uint32)buf & 3))
13751 + cnt = 4 - ((uint32)buf & 3);
13752 + else
13753 + cnt = len;
13754 +
13755 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
13756 + to = (uint32 *)buf;
13757 +
13758 + if (cnt < 4) {
13759 + bcopy(from, to, cnt);
13760 + return cnt;
13761 + }
13762 +
13763 + while (cnt >= 4) {
13764 + *to++ = *from++;
13765 + cnt -= 4;
13766 + }
13767 +
13768 + return (len - cnt);
13769 +}
13770 +
13771 +/* Poll for command completion. Returns zero when complete. */
13772 +int
13773 +sflash_poll(chipcregs_t *cc, uint offset)
13774 +{
13775 + if (offset >= sflash.size)
13776 + return -22;
13777 +
13778 + switch (sflash.type) {
13779 + case SFLASH_ST:
13780 + /* Check for ST Write In Progress bit */
13781 + sflash_cmd(cc, SFLASH_ST_RDSR);
13782 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
13783 + case SFLASH_AT:
13784 + /* Check for Atmel Ready bit */
13785 + sflash_cmd(cc, SFLASH_AT_STATUS);
13786 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
13787 + }
13788 +
13789 + return 0;
13790 +}
13791 +
13792 +/* Write len bytes starting at offset into buf. Returns number of bytes
13793 + * written. Caller should poll for completion.
13794 + */
13795 +int
13796 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
13797 +{
13798 + struct sflash *sfl;
13799 + int ret = 0;
13800 + bool is4712b0;
13801 + uint32 page, byte, mask;
13802 +
13803 + if (!len)
13804 + return 0;
13805 +
13806 + if ((offset + len) > sflash.size)
13807 + return -22;
13808 +
13809 + sfl = &sflash;
13810 + switch (sfl->type) {
13811 + case SFLASH_ST:
13812 + mask = R_REG(&cc->chipid);
13813 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
13814 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
13815 + /* Enable writes */
13816 + sflash_cmd(cc, SFLASH_ST_WREN);
13817 + if (is4712b0) {
13818 + mask = 1 << 14;
13819 + W_REG(&cc->flashaddress, offset);
13820 + W_REG(&cc->flashdata, *buf++);
13821 + /* Set chip select */
13822 + OR_REG(&cc->gpioout, mask);
13823 + /* Issue a page program with the first byte */
13824 + sflash_cmd(cc, SFLASH_ST_PP);
13825 + ret = 1;
13826 + offset++;
13827 + len--;
13828 + while (len > 0) {
13829 + if ((offset & 255) == 0) {
13830 + /* Page boundary, drop cs and return */
13831 + AND_REG(&cc->gpioout, ~mask);
13832 + if (!sflash_poll(cc, offset)) {
13833 + /* Flash rejected command */
13834 + return -11;
13835 + }
13836 + return ret;
13837 + } else {
13838 + /* Write single byte */
13839 + sflash_cmd(cc, *buf++);
13840 + }
13841 + ret++;
13842 + offset++;
13843 + len--;
13844 + }
13845 + /* All done, drop cs if needed */
13846 + if ((offset & 255) != 1) {
13847 + /* Drop cs */
13848 + AND_REG(&cc->gpioout, ~mask);
13849 + if (!sflash_poll(cc, offset)) {
13850 + /* Flash rejected command */
13851 + return -12;
13852 + }
13853 + }
13854 + } else {
13855 + ret = 1;
13856 + W_REG(&cc->flashaddress, offset);
13857 + W_REG(&cc->flashdata, *buf);
13858 + /* Page program */
13859 + sflash_cmd(cc, SFLASH_ST_PP);
13860 + }
13861 + break;
13862 + case SFLASH_AT:
13863 + mask = sfl->blocksize - 1;
13864 + page = (offset & ~mask) << 1;
13865 + byte = offset & mask;
13866 + /* Read main memory page into buffer 1 */
13867 + if (byte || len < sfl->blocksize) {
13868 + W_REG(&cc->flashaddress, page);
13869 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
13870 + /* 250 us for AT45DB321B */
13871 + SPINWAIT(sflash_poll(cc, offset), 1000);
13872 + ASSERT(!sflash_poll(cc, offset));
13873 + }
13874 + /* Write into buffer 1 */
13875 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
13876 + W_REG(&cc->flashaddress, byte++);
13877 + W_REG(&cc->flashdata, *buf++);
13878 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
13879 + }
13880 + /* Write buffer 1 into main memory page */
13881 + W_REG(&cc->flashaddress, page);
13882 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
13883 + break;
13884 + }
13885 +
13886 + return ret;
13887 +}
13888 +
13889 +/* Erase a region. Returns number of bytes scheduled for erasure.
13890 + * Caller should poll for completion.
13891 + */
13892 +int
13893 +sflash_erase(chipcregs_t *cc, uint offset)
13894 +{
13895 + struct sflash *sfl;
13896 +
13897 + if (offset >= sflash.size)
13898 + return -22;
13899 +
13900 + sfl = &sflash;
13901 + switch (sfl->type) {
13902 + case SFLASH_ST:
13903 + sflash_cmd(cc, SFLASH_ST_WREN);
13904 + W_REG(&cc->flashaddress, offset);
13905 + sflash_cmd(cc, SFLASH_ST_SE);
13906 + return sfl->blocksize;
13907 + case SFLASH_AT:
13908 + W_REG(&cc->flashaddress, offset << 1);
13909 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
13910 + return sfl->blocksize;
13911 + }
13912 +
13913 + return 0;
13914 +}
13915 +
13916 +/*
13917 + * writes the appropriate range of flash, a NULL buf simply erases
13918 + * the region of flash
13919 + */
13920 +int
13921 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
13922 +{
13923 + struct sflash *sfl;
13924 + uchar *block = NULL, *cur_ptr, *blk_ptr;
13925 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
13926 + uint blk_offset, blk_len, copied;
13927 + int bytes, ret = 0;
13928 +
13929 + /* Check address range */
13930 + if (len <= 0)
13931 + return 0;
13932 +
13933 + sfl = &sflash;
13934 + if ((offset + len) > sfl->size)
13935 + return -1;
13936 +
13937 + blocksize = sfl->blocksize;
13938 + mask = blocksize - 1;
13939 +
13940 + /* Allocate a block of mem */
13941 + if (!(block = MALLOC(NULL, blocksize)))
13942 + return -1;
13943 +
13944 + while (len) {
13945 + /* Align offset */
13946 + cur_offset = offset & ~mask;
13947 + cur_length = blocksize;
13948 + cur_ptr = block;
13949 +
13950 + remainder = blocksize - (offset & mask);
13951 + if (len < remainder)
13952 + cur_retlen = len;
13953 + else
13954 + cur_retlen = remainder;
13955 +
13956 + /* buf == NULL means erase only */
13957 + if (buf) {
13958 + /* Copy existing data into holding block if necessary */
13959 + if ((offset & mask) || (len < blocksize)) {
13960 + blk_offset = cur_offset;
13961 + blk_len = cur_length;
13962 + blk_ptr = cur_ptr;
13963 +
13964 + /* Copy entire block */
13965 + while(blk_len) {
13966 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
13967 + blk_offset += copied;
13968 + blk_len -= copied;
13969 + blk_ptr += copied;
13970 + }
13971 + }
13972 +
13973 + /* Copy input data into holding block */
13974 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
13975 + }
13976 +
13977 + /* Erase block */
13978 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
13979 + goto done;
13980 + while (sflash_poll(cc, (uint) cur_offset));
13981 +
13982 + /* buf == NULL means erase only */
13983 + if (!buf) {
13984 + offset += cur_retlen;
13985 + len -= cur_retlen;
13986 + continue;
13987 + }
13988 +
13989 + /* Write holding block */
13990 + while (cur_length > 0) {
13991 + if ((bytes = sflash_write(cc,
13992 + (uint) cur_offset,
13993 + (uint) cur_length,
13994 + (uchar *) cur_ptr)) < 0) {
13995 + ret = bytes;
13996 + goto done;
13997 + }
13998 + while (sflash_poll(cc, (uint) cur_offset));
13999 + cur_offset += bytes;
14000 + cur_length -= bytes;
14001 + cur_ptr += bytes;
14002 + }
14003 +
14004 + offset += cur_retlen;
14005 + len -= cur_retlen;
14006 + buf += cur_retlen;
14007 + }
14008 +
14009 + ret = len;
14010 +done:
14011 + if (block)
14012 + MFREE(NULL, block, blocksize);
14013 + return ret;
14014 +}
14015 +
14016 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
14017 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
14018 +++ linux.dev/arch/mips/bcm947xx/time.c 2005-11-07 23:47:27.528101500 +0100
14019 @@ -0,0 +1,118 @@
14020 +/*
14021 + * Copyright 2004, Broadcom Corporation
14022 + * All Rights Reserved.
14023 + *
14024 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14025 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14026 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14027 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14028 + *
14029 + * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
14030 + */
14031 +#include <linux/config.h>
14032 +#include <linux/init.h>
14033 +#include <linux/kernel.h>
14034 +#include <linux/sched.h>
14035 +#include <linux/serial_reg.h>
14036 +#include <linux/interrupt.h>
14037 +#include <asm/addrspace.h>
14038 +#include <asm/io.h>
14039 +#include <asm/time.h>
14040 +
14041 +#include <typedefs.h>
14042 +#include <osl.h>
14043 +#include <sbutils.h>
14044 +#include <bcmnvram.h>
14045 +#include <sbconfig.h>
14046 +#include <sbextif.h>
14047 +#include <sbmips.h>
14048 +
14049 +/* Global SB handle */
14050 +extern void *bcm947xx_sbh;
14051 +extern spinlock_t bcm947xx_sbh_lock;
14052 +
14053 +/* Convenience */
14054 +#define sbh bcm947xx_sbh
14055 +#define sbh_lock bcm947xx_sbh_lock
14056 +
14057 +extern int panic_timeout;
14058 +static int watchdog = 0;
14059 +static u8 *mcr = NULL;
14060 +
14061 +void __init
14062 +bcm947xx_time_init(void)
14063 +{
14064 + unsigned int hz;
14065 + extifregs_t *eir;
14066 +
14067 + /*
14068 + * Use deterministic values for initial counter interrupt
14069 + * so that calibrate delay avoids encountering a counter wrap.
14070 + */
14071 + write_c0_count(0);
14072 + write_c0_compare(0xffff);
14073 +
14074 + if (!(hz = sb_mips_clock(sbh)))
14075 + hz = 100000000;
14076 +
14077 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
14078 + (hz + 500000) / 1000000);
14079 +
14080 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
14081 + mips_hpt_frequency = hz / 2;
14082 +
14083 + /* Set watchdog interval in ms */
14084 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
14085 +
14086 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
14087 + if (watchdog > 0) {
14088 + if (watchdog < 3000)
14089 + watchdog = 3000;
14090 + }
14091 +
14092 +
14093 + /* Set panic timeout in seconds */
14094 + panic_timeout = watchdog / 1000;
14095 +
14096 + /* Setup blink */
14097 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
14098 + sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
14099 + unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
14100 + mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
14101 + }
14102 +}
14103 +
14104 +static void
14105 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
14106 +{
14107 + /* Generic MIPS timer code */
14108 + timer_interrupt(irq, dev_id, regs);
14109 +
14110 + /* Set the watchdog timer to reset after the specified number of ms */
14111 + if (watchdog > 0)
14112 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
14113 +
14114 +#ifdef CONFIG_HWSIM
14115 + (*((int *)0xa0000f1c))++;
14116 +#else
14117 + /* Blink one of the LEDs in the external UART */
14118 + if (mcr && !(jiffies % (HZ/2)))
14119 + writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
14120 +#endif
14121 +}
14122 +
14123 +static struct irqaction bcm947xx_timer_irqaction = {
14124 + bcm947xx_timer_interrupt,
14125 + SA_INTERRUPT,
14126 + 0,
14127 + "timer",
14128 + NULL,
14129 + NULL
14130 +};
14131 +
14132 +void __init
14133 +bcm947xx_timer_setup(struct irqaction *irq)
14134 +{
14135 + /* Enable the timer interrupt */
14136 + setup_irq(7, &bcm947xx_timer_irqaction);
14137 +}
14138 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
14139 --- linux.old/arch/mips/config-shared.in 2005-11-07 23:12:50.850903750 +0100
14140 +++ linux.dev/arch/mips/config-shared.in 2005-11-07 21:57:07.889588500 +0100
14141 @@ -208,6 +208,14 @@
14142 fi
14143 define_bool CONFIG_MIPS_RTC y
14144 fi
14145 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
14146 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
14147 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14148 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
14149 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
14150 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
14151 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
14152 +fi
14153 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
14154 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
14155 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
14156 @@ -229,6 +237,11 @@
14157 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
14158
14159 #
14160 +# Provide an option for a default kernel command line
14161 +#
14162 +string 'Default kernel command string' CONFIG_CMDLINE ""
14163 +
14164 +#
14165 # Select some configuration options automatically based on user selections.
14166 #
14167 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
14168 @@ -554,6 +567,13 @@
14169 define_bool CONFIG_SWAP_IO_SPACE_L y
14170 define_bool CONFIG_BOOT_ELF32 y
14171 fi
14172 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14173 + define_bool CONFIG_PCI y
14174 + define_bool CONFIG_NONCOHERENT_IO y
14175 + define_bool CONFIG_NEW_TIME_C y
14176 + define_bool CONFIG_NEW_IRQ y
14177 + define_bool CONFIG_HND y
14178 +fi
14179 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
14180 define_bool CONFIG_ARC32 y
14181 define_bool CONFIG_ARC_MEMORY y
14182 @@ -1042,7 +1062,11 @@
14183
14184 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
14185 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
14186 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
14187 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14188 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
14189 +else
14190 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
14191 +fi
14192 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
14193 if [ "$CONFIG_KGDB" = "y" ]; then
14194 define_bool CONFIG_DEBUG_INFO y
14195 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
14196 --- linux.old/arch/mips/kernel/cpu-probe.c 2005-11-07 23:12:50.890906250 +0100
14197 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-11-07 21:57:07.893588750 +0100
14198 @@ -163,7 +163,7 @@
14199
14200 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
14201 {
14202 - switch (c->processor_id & 0xff00) {
14203 + switch (c->processor_id & PRID_IMP_MASK) {
14204 case PRID_IMP_R2000:
14205 c->cputype = CPU_R2000;
14206 c->isa_level = MIPS_CPU_ISA_I;
14207 @@ -173,7 +173,7 @@
14208 c->tlbsize = 64;
14209 break;
14210 case PRID_IMP_R3000:
14211 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
14212 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
14213 if (cpu_has_confreg())
14214 c->cputype = CPU_R3081E;
14215 else
14216 @@ -188,12 +188,12 @@
14217 break;
14218 case PRID_IMP_R4000:
14219 if (read_c0_config() & CONF_SC) {
14220 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
14221 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
14222 c->cputype = CPU_R4400PC;
14223 else
14224 c->cputype = CPU_R4000PC;
14225 } else {
14226 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
14227 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
14228 c->cputype = CPU_R4400SC;
14229 else
14230 c->cputype = CPU_R4000SC;
14231 @@ -439,7 +439,7 @@
14232 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
14233 {
14234 decode_config1(c);
14235 - switch (c->processor_id & 0xff00) {
14236 + switch (c->processor_id & PRID_IMP_MASK) {
14237 case PRID_IMP_4KC:
14238 c->cputype = CPU_4KC;
14239 c->isa_level = MIPS_CPU_ISA_M32;
14240 @@ -480,10 +480,10 @@
14241 {
14242 decode_config1(c);
14243 c->options |= MIPS_CPU_PREFETCH;
14244 - switch (c->processor_id & 0xff00) {
14245 + switch (c->processor_id & PRID_IMP_MASK) {
14246 case PRID_IMP_AU1_REV1:
14247 case PRID_IMP_AU1_REV2:
14248 - switch ((c->processor_id >> 24) & 0xff) {
14249 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
14250 case 0:
14251 c->cputype = CPU_AU1000;
14252 break;
14253 @@ -511,10 +511,34 @@
14254 }
14255 }
14256
14257 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
14258 +{
14259 + decode_config1(c);
14260 + c->options |= MIPS_CPU_PREFETCH;
14261 + switch (c->processor_id & PRID_IMP_MASK) {
14262 + case PRID_IMP_BCM4710:
14263 + c->cputype = CPU_BCM4710;
14264 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
14265 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
14266 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
14267 + break;
14268 + case PRID_IMP_4KC:
14269 + case PRID_IMP_BCM3302:
14270 + c->cputype = CPU_BCM3302;
14271 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
14272 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
14273 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
14274 + break;
14275 + default:
14276 + c->cputype = CPU_UNKNOWN;
14277 + break;
14278 + }
14279 +}
14280 +
14281 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
14282 {
14283 decode_config1(c);
14284 - switch (c->processor_id & 0xff00) {
14285 + switch (c->processor_id & PRID_IMP_MASK) {
14286 case PRID_IMP_SB1:
14287 c->cputype = CPU_SB1;
14288 c->isa_level = MIPS_CPU_ISA_M64;
14289 @@ -536,7 +560,7 @@
14290 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
14291 {
14292 decode_config1(c);
14293 - switch (c->processor_id & 0xff00) {
14294 + switch (c->processor_id & PRID_IMP_MASK) {
14295 case PRID_IMP_SR71000:
14296 c->cputype = CPU_SR71000;
14297 c->isa_level = MIPS_CPU_ISA_M64;
14298 @@ -561,7 +585,7 @@
14299 c->cputype = CPU_UNKNOWN;
14300
14301 c->processor_id = read_c0_prid();
14302 - switch (c->processor_id & 0xff0000) {
14303 + switch (c->processor_id & PRID_COMP_MASK) {
14304
14305 case PRID_COMP_LEGACY:
14306 cpu_probe_legacy(c);
14307 @@ -572,6 +596,9 @@
14308 case PRID_COMP_ALCHEMY:
14309 cpu_probe_alchemy(c);
14310 break;
14311 + case PRID_COMP_BROADCOM:
14312 + cpu_probe_broadcom(c);
14313 + break;
14314 case PRID_COMP_SIBYTE:
14315 cpu_probe_sibyte(c);
14316 break;
14317 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
14318 --- linux.old/arch/mips/kernel/head.S 2005-11-07 23:12:50.898906750 +0100
14319 +++ linux.dev/arch/mips/kernel/head.S 2005-11-07 21:57:07.893588750 +0100
14320 @@ -28,12 +28,20 @@
14321 #include <asm/mipsregs.h>
14322 #include <asm/stackframe.h>
14323
14324 +#ifdef CONFIG_BCM4710
14325 +#undef eret
14326 +#define eret nop; nop; eret
14327 +#endif
14328 +
14329 .text
14330 + j kernel_entry
14331 + nop
14332 +
14333 /*
14334 * Reserved space for exception handlers.
14335 * Necessary for machines which link their kernels at KSEG0.
14336 */
14337 - .fill 0x400
14338 + .fill 0x3f4
14339
14340 /* The following two symbols are used for kernel profiling. */
14341 EXPORT(stext)
14342 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
14343 --- linux.old/arch/mips/kernel/proc.c 2005-11-07 23:12:50.906907250 +0100
14344 +++ linux.dev/arch/mips/kernel/proc.c 2005-11-07 21:57:07.893588750 +0100
14345 @@ -78,9 +78,10 @@
14346 [CPU_AU1550] "Au1550",
14347 [CPU_24K] "MIPS 24K",
14348 [CPU_AU1200] "Au1200",
14349 + [CPU_BCM4710] "BCM4710",
14350 + [CPU_BCM3302] "BCM3302",
14351 };
14352
14353 -
14354 static int show_cpuinfo(struct seq_file *m, void *v)
14355 {
14356 unsigned int version = current_cpu_data.processor_id;
14357 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
14358 --- linux.old/arch/mips/kernel/setup.c 2005-11-07 23:12:50.906907250 +0100
14359 +++ linux.dev/arch/mips/kernel/setup.c 2005-11-07 21:57:07.893588750 +0100
14360 @@ -493,6 +493,7 @@
14361 void swarm_setup(void);
14362 void hp_setup(void);
14363 void au1x00_setup(void);
14364 + void brcm_setup(void);
14365 void frame_info_init(void);
14366
14367 frame_info_init();
14368 @@ -691,6 +692,11 @@
14369 pmc_yosemite_setup();
14370 break;
14371 #endif
14372 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
14373 + case MACH_GROUP_BRCM:
14374 + brcm_setup();
14375 + break;
14376 +#endif
14377 default:
14378 panic("Unsupported architecture");
14379 }
14380 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
14381 --- linux.old/arch/mips/kernel/traps.c 2005-11-07 23:12:50.922908250 +0100
14382 +++ linux.dev/arch/mips/kernel/traps.c 2005-11-07 21:57:07.893588750 +0100
14383 @@ -920,6 +920,7 @@
14384 void __init trap_init(void)
14385 {
14386 extern char except_vec1_generic;
14387 + extern char except_vec2_generic;
14388 extern char except_vec3_generic, except_vec3_r4000;
14389 extern char except_vec_ejtag_debug;
14390 extern char except_vec4;
14391 @@ -927,6 +928,7 @@
14392
14393 /* Copy the generic exception handler code to it's final destination. */
14394 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
14395 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
14396
14397 /*
14398 * Setup default vectors
14399 @@ -985,6 +987,12 @@
14400 set_except_vector(13, handle_tr);
14401 set_except_vector(22, handle_mdmx);
14402
14403 + if (current_cpu_data.cputype == CPU_SB1) {
14404 + /* Enable timer interrupt and scd mapped interrupt */
14405 + clear_c0_status(0xf000);
14406 + set_c0_status(0xc00);
14407 + }
14408 +
14409 if (cpu_has_fpu && !cpu_has_nofpuex)
14410 set_except_vector(15, handle_fpe);
14411
14412 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
14413 --- linux.old/arch/mips/mm/c-r4k.c 2005-11-07 23:12:50.954910250 +0100
14414 +++ linux.dev/arch/mips/mm/c-r4k.c 2005-11-07 21:57:08.157605250 +0100
14415 @@ -1166,3 +1166,47 @@
14416 build_clear_page();
14417 build_copy_page();
14418 }
14419 +
14420 +#ifdef CONFIG_BCM4704
14421 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
14422 +{
14423 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
14424 + int i;
14425 + for (i = 0; i < nbytes; i += ic_lsize)
14426 + fill_icache_line((addr + i));
14427 +}
14428 +
14429 +/*
14430 + * This must be run from the cache on 4704A0
14431 + * so there are no mips core BIU ops in progress
14432 + * when the PFC is enabled.
14433 + */
14434 +#define PFC_CR0 0xff400000 /* control reg 0 */
14435 +#define PFC_CR1 0xff400004 /* control reg 1 */
14436 +static void __init enable_pfc(u32 mode)
14437 +{
14438 + /* write range */
14439 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
14440 +
14441 + /* enable */
14442 + *(volatile u32 *)PFC_CR0 = mode;
14443 +}
14444 +#endif
14445 +
14446 +
14447 +void check_enable_mips_pfc(int val)
14448 +{
14449 +
14450 +#ifdef CONFIG_BCM4704
14451 + struct cpuinfo_mips *c = &current_cpu_data;
14452 +
14453 + /* enable prefetch cache */
14454 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
14455 + && (read_c0_diag() & (1 << 29))) {
14456 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
14457 + enable_pfc(val);
14458 + }
14459 +#endif
14460 +}
14461 +
14462 +
14463 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
14464 --- linux.old/arch/mips/pci/Makefile 2005-11-07 23:12:50.978911750 +0100
14465 +++ linux.dev/arch/mips/pci/Makefile 2005-11-07 21:57:07.897589000 +0100
14466 @@ -13,7 +13,9 @@
14467 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
14468 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
14469 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
14470 +ifndef CONFIG_BCM947XX
14471 obj-y += pci.o
14472 +endif
14473 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
14474
14475 include $(TOPDIR)/Rules.make
14476 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
14477 --- linux.old/drivers/char/serial.c 2005-11-07 23:12:51.038915500 +0100
14478 +++ linux.dev/drivers/char/serial.c 2005-11-07 21:57:07.901589250 +0100
14479 @@ -444,6 +444,10 @@
14480 return inb(info->port+1);
14481 #endif
14482 case SERIAL_IO_MEM:
14483 +#ifdef CONFIG_BCM4310
14484 + readb((unsigned long) info->iomem_base +
14485 + (UART_SCR<<info->iomem_reg_shift));
14486 +#endif
14487 return readb((unsigned long) info->iomem_base +
14488 (offset<<info->iomem_reg_shift));
14489 default:
14490 @@ -464,6 +468,9 @@
14491 case SERIAL_IO_MEM:
14492 writeb(value, (unsigned long) info->iomem_base +
14493 (offset<<info->iomem_reg_shift));
14494 +#ifdef CONFIG_BCM4704
14495 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
14496 +#endif
14497 break;
14498 default:
14499 outb(value, info->port+offset);
14500 @@ -1728,7 +1735,7 @@
14501 /* Special case since 134 is really 134.5 */
14502 quot = (2*baud_base / 269);
14503 else if (baud)
14504 - quot = baud_base / baud;
14505 + quot = (baud_base + (baud / 2)) / baud;
14506 }
14507 /* If the quotient is zero refuse the change */
14508 if (!quot && old_termios) {
14509 @@ -1745,12 +1752,12 @@
14510 /* Special case since 134 is really 134.5 */
14511 quot = (2*baud_base / 269);
14512 else if (baud)
14513 - quot = baud_base / baud;
14514 + quot = (baud_base + (baud / 2)) / baud;
14515 }
14516 }
14517 /* As a last resort, if the quotient is zero, default to 9600 bps */
14518 if (!quot)
14519 - quot = baud_base / 9600;
14520 + quot = (baud_base + 4800) / 9600;
14521 /*
14522 * Work around a bug in the Oxford Semiconductor 952 rev B
14523 * chip which causes it to seriously miscalculate baud rates
14524 @@ -5984,6 +5991,13 @@
14525 * Divisor, bytesize and parity
14526 */
14527 state = rs_table + co->index;
14528 + /*
14529 + * Safe guard: state structure must have been initialized
14530 + */
14531 + if (state->iomem_base == NULL) {
14532 + printk("!unable to setup serial console!\n");
14533 + return -1;
14534 + }
14535 if (doflow)
14536 state->flags |= ASYNC_CONS_FLOW;
14537 info = &async_sercons;
14538 @@ -5997,7 +6011,7 @@
14539 info->io_type = state->io_type;
14540 info->iomem_base = state->iomem_base;
14541 info->iomem_reg_shift = state->iomem_reg_shift;
14542 - quot = state->baud_base / baud;
14543 + quot = (state->baud_base + (baud / 2)) / baud;
14544 cval = cflag & (CSIZE | CSTOPB);
14545 #if defined(__powerpc__) || defined(__alpha__)
14546 cval >>= 8;
14547 diff -urN linux.old/drivers/mtd/maps/Config.in linux.dev/drivers/mtd/maps/Config.in
14548 --- linux.old/drivers/mtd/maps/Config.in 2005-11-07 23:12:51.086918500 +0100
14549 +++ linux.dev/drivers/mtd/maps/Config.in 2005-11-07 21:57:07.901589250 +0100
14550 @@ -48,6 +48,7 @@
14551 fi
14552
14553 if [ "$CONFIG_MIPS" = "y" ]; then
14554 + dep_tristate ' CFI Flash device mapped on Broadcom BCM947XX boards' CONFIG_MTD_BCM947XX $CONFIG_MTD_CFI
14555 dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
14556 dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
14557 dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
14558 diff -urN linux.old/drivers/mtd/maps/Makefile linux.dev/drivers/mtd/maps/Makefile
14559 --- linux.old/drivers/mtd/maps/Makefile 2005-11-07 23:12:51.086918500 +0100
14560 +++ linux.dev/drivers/mtd/maps/Makefile 2005-11-07 21:57:07.905589500 +0100
14561 @@ -3,6 +3,8 @@
14562 #
14563 # $Id: Makefile,v 1.37 2003/01/24 14:26:38 dwmw2 Exp $
14564
14565 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
14566 +
14567 BELOW25 := $(shell echo $(PATCHLEVEL) | sed s/[1234]/y/)
14568
14569 ifeq ($(BELOW25),y)
14570 @@ -10,6 +12,7 @@
14571 endif
14572
14573 # Chip mappings
14574 +obj-$(CONFIG_MTD_BCM947XX) += bcm947xx-flash.o
14575 obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
14576 obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
14577 obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
14578 diff -urN linux.old/drivers/mtd/maps/bcm947xx-flash.c linux.dev/drivers/mtd/maps/bcm947xx-flash.c
14579 --- linux.old/drivers/mtd/maps/bcm947xx-flash.c 1970-01-01 01:00:00.000000000 +0100
14580 +++ linux.dev/drivers/mtd/maps/bcm947xx-flash.c 2005-11-07 23:33:20.715765500 +0100
14581 @@ -0,0 +1,237 @@
14582 +/*
14583 + * Flash mapping for BCM947XX boards
14584 + *
14585 + * Copyright 2004, Broadcom Corporation
14586 + * All Rights Reserved.
14587 + *
14588 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14589 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14590 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14591 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14592 + *
14593 + * $Id: bcm947xx-flash.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
14594 + */
14595 +
14596 +#include <linux/module.h>
14597 +#include <linux/types.h>
14598 +#include <linux/kernel.h>
14599 +#include <asm/io.h>
14600 +#include <linux/mtd/mtd.h>
14601 +#include <linux/mtd/map.h>
14602 +#include <linux/mtd/partitions.h>
14603 +#include <linux/config.h>
14604 +
14605 +#include <osl.h>
14606 +#include <typedefs.h>
14607 +#include <bcmnvram.h>
14608 +#include <bcmutils.h>
14609 +#include <sbconfig.h>
14610 +#include <sbchipc.h>
14611 +#include <sbutils.h>
14612 +#include <trxhdr.h>
14613 +
14614 +/* Global SB handle */
14615 +extern void *bcm947xx_sbh;
14616 +extern spinlock_t bcm947xx_sbh_lock;
14617 +
14618 +/* Convenience */
14619 +#define sbh bcm947xx_sbh
14620 +#define sbh_lock bcm947xx_sbh_lock
14621 +
14622 +#ifdef CONFIG_MTD_PARTITIONS
14623 +extern struct mtd_partition * init_mtd_partitions(struct mtd_info *mtd, size_t size);
14624 +#endif
14625 +
14626 +#define WINDOW_ADDR 0x1fc00000
14627 +#define WINDOW_SIZE 0x400000
14628 +#define BUSWIDTH 2
14629 +
14630 +/* e.g., flash=2M or flash=4M */
14631 +static int flash = 0;
14632 +MODULE_PARM(flash, "i");
14633 +static int __init
14634 +bcm947xx_setup(char *str)
14635 +{
14636 + flash = memparse(str, &str);
14637 + return 1;
14638 +}
14639 +__setup("flash=", bcm947xx_setup);
14640 +
14641 +static struct mtd_info *bcm947xx_mtd;
14642 +
14643 +__u8 bcm947xx_map_read8(struct map_info *map, unsigned long ofs)
14644 +{
14645 + if (map->map_priv_2 == 1)
14646 + return __raw_readb(map->map_priv_1 + ofs);
14647 +
14648 + u16 val = __raw_readw(map->map_priv_1 + (ofs & ~1));
14649 + if (ofs & 1)
14650 + return ((val >> 8) & 0xff);
14651 + else
14652 + return (val & 0xff);
14653 +}
14654 +
14655 +__u16 bcm947xx_map_read16(struct map_info *map, unsigned long ofs)
14656 +{
14657 + return __raw_readw(map->map_priv_1 + ofs);
14658 +}
14659 +
14660 +__u32 bcm947xx_map_read32(struct map_info *map, unsigned long ofs)
14661 +{
14662 + return __raw_readl(map->map_priv_1 + ofs);
14663 +}
14664 +
14665 +void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
14666 +{
14667 + if (len==1) {
14668 + memcpy_fromio(to, map->map_priv_1 + from, len);
14669 + } else {
14670 + int i;
14671 + u16 *dest = (u16 *) to;
14672 + u16 *src = (u16 *) (map->map_priv_1 + from);
14673 + for (i = 0; i < (len / 2); i++) {
14674 + dest[i] = src[i];
14675 + }
14676 + if (len & 1)
14677 + *((u8 *)dest+len-1) = src[i] & 0xff;
14678 + }
14679 +}
14680 +
14681 +void bcm947xx_map_write8(struct map_info *map, __u8 d, unsigned long adr)
14682 +{
14683 + __raw_writeb(d, map->map_priv_1 + adr);
14684 + mb();
14685 +}
14686 +
14687 +void bcm947xx_map_write16(struct map_info *map, __u16 d, unsigned long adr)
14688 +{
14689 + __raw_writew(d, map->map_priv_1 + adr);
14690 + mb();
14691 +}
14692 +
14693 +void bcm947xx_map_write32(struct map_info *map, __u32 d, unsigned long adr)
14694 +{
14695 + __raw_writel(d, map->map_priv_1 + adr);
14696 + mb();
14697 +}
14698 +
14699 +void bcm947xx_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
14700 +{
14701 + memcpy_toio(map->map_priv_1 + to, from, len);
14702 +}
14703 +
14704 +struct map_info bcm947xx_map = {
14705 + name: "Physically mapped flash",
14706 + size: WINDOW_SIZE,
14707 + buswidth: BUSWIDTH,
14708 + read8: bcm947xx_map_read8,
14709 + read16: bcm947xx_map_read16,
14710 + read32: bcm947xx_map_read32,
14711 + copy_from: bcm947xx_map_copy_from,
14712 + write8: bcm947xx_map_write8,
14713 + write16: bcm947xx_map_write16,
14714 + write32: bcm947xx_map_write32,
14715 + copy_to: bcm947xx_map_copy_to
14716 +};
14717 +
14718 +#if LINUX_VERSION_CODE < 0x20212 && defined(MODULE)
14719 +#define init_bcm947xx_map init_module
14720 +#define cleanup_bcm947xx_map cleanup_module
14721 +#endif
14722 +
14723 +mod_init_t init_bcm947xx_map(void)
14724 +{
14725 + ulong flags;
14726 + uint coreidx;
14727 + chipcregs_t *cc;
14728 + uint32 fltype;
14729 + uint window_addr = 0, window_size = 0;
14730 + size_t size;
14731 + int ret = 0;
14732 +#ifdef CONFIG_MTD_PARTITIONS
14733 + struct mtd_partition *parts;
14734 + int i;
14735 +#endif
14736 +
14737 + spin_lock_irqsave(&sbh_lock, flags);
14738 + coreidx = sb_coreidx(sbh);
14739 +
14740 + /* Check strapping option if chipcommon exists */
14741 + if ((cc = sb_setcore(sbh, SB_CC, 0))) {
14742 + fltype = readl(&cc->capabilities) & CAP_FLASH_MASK;
14743 + if (fltype == PFLASH) {
14744 + bcm947xx_map.map_priv_2 = 1;
14745 + window_addr = 0x1c000000;
14746 + bcm947xx_map.size = window_size = 32 * 1024 * 1024;
14747 + if ((readl(&cc->flash_config) & CC_CFG_DS) == 0)
14748 + bcm947xx_map.buswidth = 1;
14749 + }
14750 + } else {
14751 + fltype = PFLASH;
14752 + bcm947xx_map.map_priv_2 = 0;
14753 + window_addr = WINDOW_ADDR;
14754 + window_size = WINDOW_SIZE;
14755 + }
14756 +
14757 + sb_setcoreidx(sbh, coreidx);
14758 + spin_unlock_irqrestore(&sbh_lock, flags);
14759 +
14760 + if (fltype != PFLASH) {
14761 + printk(KERN_ERR "pflash: found no supported devices\n");
14762 + ret = -ENODEV;
14763 + goto fail;
14764 + }
14765 +
14766 + bcm947xx_map.map_priv_1 = (unsigned long) ioremap(window_addr, window_size);
14767 + if (!bcm947xx_map.map_priv_1) {
14768 + printk(KERN_ERR "pflash: ioremap failed\n");
14769 + ret = -EIO;
14770 + goto fail;
14771 + }
14772 +
14773 + if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
14774 + printk(KERN_ERR "pflash: cfi_probe failed\n");
14775 + ret = -ENXIO;
14776 + goto fail;
14777 + }
14778 +
14779 + bcm947xx_mtd->module = THIS_MODULE;
14780 +
14781 + /* Allow size override for testing */
14782 + size = flash ? : bcm947xx_mtd->size;
14783 +
14784 + printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, window_addr);
14785 +
14786 +#ifdef CONFIG_MTD_PARTITIONS
14787 + parts = init_mtd_partitions(bcm947xx_mtd, size);
14788 + for (i = 0; parts[i].name; i++);
14789 + ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
14790 + if (ret) {
14791 + printk(KERN_ERR "pflash: add_mtd_partitions failed\n");
14792 + goto fail;
14793 + }
14794 +#endif
14795 +
14796 + return 0;
14797 +
14798 + fail:
14799 + if (bcm947xx_mtd)
14800 + map_destroy(bcm947xx_mtd);
14801 + if (bcm947xx_map.map_priv_1)
14802 + iounmap((void *) bcm947xx_map.map_priv_1);
14803 + bcm947xx_map.map_priv_1 = 0;
14804 + return ret;
14805 +}
14806 +
14807 +mod_exit_t cleanup_bcm947xx_map(void)
14808 +{
14809 +#ifdef CONFIG_MTD_PARTITIONS
14810 + del_mtd_partitions(bcm947xx_mtd);
14811 +#endif
14812 + map_destroy(bcm947xx_mtd);
14813 + iounmap((void *) bcm947xx_map.map_priv_1);
14814 + bcm947xx_map.map_priv_1 = 0;
14815 +}
14816 +
14817 +module_init(init_bcm947xx_map);
14818 +module_exit(cleanup_bcm947xx_map);
14819 diff -urN linux.old/drivers/net/Config.in linux.dev/drivers/net/Config.in
14820 --- linux.old/drivers/net/Config.in 2005-11-07 23:12:51.110920000 +0100
14821 +++ linux.dev/drivers/net/Config.in 2005-11-07 21:57:07.905589500 +0100
14822 @@ -2,6 +2,8 @@
14823 # Network device configuration
14824 #
14825
14826 +tristate 'Broadcom Home Network Division' CONFIG_HND $CONFIG_PCI
14827 +
14828 source drivers/net/arcnet/Config.in
14829
14830 tristate 'Dummy net driver support' CONFIG_DUMMY
14831 @@ -174,6 +176,7 @@
14832
14833 dep_tristate ' Apricot Xen-II on board Ethernet' CONFIG_APRICOT $CONFIG_ISA
14834 dep_tristate ' Broadcom 4400 ethernet support (EXPERIMENTAL)' CONFIG_B44 $CONFIG_PCI $CONFIG_EXPERIMENTAL
14835 + dep_tristate ' Proprietary Broadcom 10/100 Ethernet support' CONFIG_ET $CONFIG_PCI
14836 dep_tristate ' CS89x0 support' CONFIG_CS89x0 $CONFIG_ISA
14837 dep_tristate ' DECchip Tulip (dc21x4x) PCI support' CONFIG_TULIP $CONFIG_PCI
14838 if [ "$CONFIG_TULIP" = "y" -o "$CONFIG_TULIP" = "m" ]; then
14839 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
14840 --- linux.old/drivers/net/Makefile 2005-11-07 23:12:51.110920000 +0100
14841 +++ linux.dev/drivers/net/Makefile 2005-11-07 21:57:07.905589500 +0100
14842 @@ -3,6 +3,8 @@
14843 # Makefile for the Linux network (ethercard) device drivers.
14844 #
14845
14846 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
14847 +
14848 obj-y :=
14849 obj-m :=
14850 obj-n :=
14851 @@ -39,6 +41,9 @@
14852 obj-$(CONFIG_ISDN) += slhc.o
14853 endif
14854
14855 +subdir-$(CONFIG_HND) += hnd
14856 +subdir-$(CONFIG_ET) += et
14857 +subdir-$(CONFIG_WL) += wl
14858 subdir-$(CONFIG_NET_PCMCIA) += pcmcia
14859 subdir-$(CONFIG_NET_WIRELESS) += wireless
14860 subdir-$(CONFIG_TULIP) += tulip
14861 @@ -69,6 +74,16 @@
14862 obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
14863 obj-$(CONFIG_SUNGEM) += sungem.o
14864
14865 +ifeq ($(CONFIG_HND),y)
14866 + obj-y += hnd/hnd.o
14867 +endif
14868 +ifeq ($(CONFIG_ET),y)
14869 + obj-y += et/et.o
14870 +endif
14871 +ifeq ($(CONFIG_WL),y)
14872 + obj-y += wl/wl.o
14873 +endif
14874 +
14875 obj-$(CONFIG_MACE) += mace.o
14876 obj-$(CONFIG_BMAC) += bmac.o
14877 obj-$(CONFIG_GMAC) += gmac.o
14878 @@ -266,6 +281,7 @@
14879 endif
14880 endif
14881
14882 +
14883 include $(TOPDIR)/Rules.make
14884
14885 clean:
14886 diff -urN linux.old/drivers/net/et/Makefile linux.dev/drivers/net/et/Makefile
14887 --- linux.old/drivers/net/et/Makefile 1970-01-01 01:00:00.000000000 +0100
14888 +++ linux.dev/drivers/net/et/Makefile 2005-11-07 21:57:07.905589500 +0100
14889 @@ -0,0 +1,21 @@
14890 +#
14891 +# Makefile for the Broadcom et driver
14892 +#
14893 +# Copyright 2004, Broadcom Corporation
14894 +# All Rights Reserved.
14895 +#
14896 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14897 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14898 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14899 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14900 +#
14901 +# $Id: Makefile,v 1.1 2005/03/16 13:50:00 wbx Exp $
14902 +#
14903 +
14904 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCM47XX_CHOPS -DDMA -DBCMDRIVER
14905 +
14906 +O_TARGET := et.o
14907 +obj-y := et_linux.o etc.o etc47xx.o etc_robo.o etc_adm.o
14908 +obj-m := $(O_TARGET)
14909 +
14910 +include $(TOPDIR)/Rules.make
14911 diff -urN linux.old/drivers/net/hnd/Makefile linux.dev/drivers/net/hnd/Makefile
14912 --- linux.old/drivers/net/hnd/Makefile 1970-01-01 01:00:00.000000000 +0100
14913 +++ linux.dev/drivers/net/hnd/Makefile 2005-11-07 21:57:07.905589500 +0100
14914 @@ -0,0 +1,19 @@
14915 +#
14916 +# Makefile for the BCM47xx specific kernel interface routines
14917 +# under Linux.
14918 +#
14919 +
14920 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
14921 +
14922 +O_TARGET := hnd.o
14923 +
14924 +HND_OBJS := bcmutils.o hnddma.o linux_osl.o sbutils.o bcmsrom.o
14925 +
14926 +export-objs := shared_ksyms.o
14927 +obj-y := shared_ksyms.o $(HND_OBJS)
14928 +obj-m := $(O_TARGET)
14929 +
14930 +include $(TOPDIR)/Rules.make
14931 +
14932 +shared_ksyms.c: shared_ksyms.sh $(HND_OBJS)
14933 + sh -e $< $(HND_OBJS) > $@
14934 diff -urN linux.old/drivers/net/hnd/bcmsrom.c linux.dev/drivers/net/hnd/bcmsrom.c
14935 --- linux.old/drivers/net/hnd/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
14936 +++ linux.dev/drivers/net/hnd/bcmsrom.c 2005-11-07 22:28:05.077337250 +0100
14937 @@ -0,0 +1,936 @@
14938 +/*
14939 + * Misc useful routines to access NIC SROM/OTP .
14940 + *
14941 + * Copyright 2005, Broadcom Corporation
14942 + * All Rights Reserved.
14943 + *
14944 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14945 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14946 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14947 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14948 + * $Id$
14949 + */
14950 +
14951 +#include <typedefs.h>
14952 +#include <osl.h>
14953 +#include <bcmutils.h>
14954 +#include <bcmsrom.h>
14955 +#include <bcmdevs.h>
14956 +#include <bcmendian.h>
14957 +#include <sbpcmcia.h>
14958 +#include <pcicfg.h>
14959 +#include <sbutils.h>
14960 +#include <bcmnvram.h>
14961 +
14962 +#include <proto/ethernet.h> /* for sprom content groking */
14963 +
14964 +#define VARS_MAX 4096 /* should be reduced */
14965 +
14966 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
14967 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
14968 +
14969 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
14970 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count);
14971 +static int initvars_flash_sb(void *sbh, char **vars, int *count);
14972 +static int srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count);
14973 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
14974 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
14975 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
14976 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
14977 +
14978 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
14979 +static int initvars_flash(osl_t *osh, char **vp, int len, char *devpath);
14980 +
14981 +/*
14982 + * Initialize local vars from the right source for this platform.
14983 + * Return 0 on success, nonzero on error.
14984 + */
14985 +int
14986 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
14987 +{
14988 + ASSERT(bustype == BUSTYPE(bustype));
14989 + if (vars == NULL || count == NULL)
14990 + return (0);
14991 +
14992 + switch (BUSTYPE(bustype)) {
14993 + case SB_BUS:
14994 + case JTAG_BUS:
14995 + return initvars_flash_sb(sbh, vars, count);
14996 +
14997 + case PCI_BUS:
14998 + ASSERT(curmap); /* can not be NULL */
14999 + return initvars_srom_pci(sbh, curmap, vars, count);
15000 +
15001 + case PCMCIA_BUS:
15002 + return initvars_cis_pcmcia(sbh, osh, vars, count);
15003 +
15004 +
15005 + default:
15006 + ASSERT(0);
15007 + }
15008 + return (-1);
15009 +}
15010 +
15011 +/* support only 16-bit word read from srom */
15012 +int
15013 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
15014 +{
15015 + void *srom;
15016 + uint i, off, nw;
15017 +
15018 + ASSERT(bustype == BUSTYPE(bustype));
15019 +
15020 + /* check input - 16-bit access only */
15021 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
15022 + return 1;
15023 +
15024 + off = byteoff / 2;
15025 + nw = nbytes / 2;
15026 +
15027 + if (BUSTYPE(bustype) == PCI_BUS) {
15028 + if (!curmap)
15029 + return 1;
15030 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
15031 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
15032 + return 1;
15033 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
15034 + for (i = 0; i < nw; i++) {
15035 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
15036 + return 1;
15037 + }
15038 + } else {
15039 + return 1;
15040 + }
15041 +
15042 + return 0;
15043 +}
15044 +
15045 +/* support only 16-bit word write into srom */
15046 +int
15047 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
15048 +{
15049 + uint16 *srom;
15050 + uint i, off, nw, crc_range;
15051 + uint16 image[SPROM_SIZE], *p;
15052 + uint8 crc;
15053 + volatile uint32 val32;
15054 +
15055 + ASSERT(bustype == BUSTYPE(bustype));
15056 +
15057 + /* check input - 16-bit access only */
15058 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
15059 + return 1;
15060 +
15061 + crc_range = (((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
15062 +
15063 + /* if changes made inside crc cover range */
15064 + if (byteoff < crc_range) {
15065 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
15066 + /* read data including entire first 64 words from srom */
15067 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
15068 + return 1;
15069 + /* make changes */
15070 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
15071 + /* calculate crc */
15072 + htol16_buf(image, crc_range);
15073 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
15074 + ltoh16_buf(image, crc_range);
15075 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
15076 + p = image;
15077 + off = 0;
15078 + } else {
15079 + p = buf;
15080 + off = byteoff / 2;
15081 + nw = nbytes / 2;
15082 + }
15083 +
15084 + if (BUSTYPE(bustype) == PCI_BUS) {
15085 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
15086 + /* enable writes to the SPROM */
15087 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
15088 + val32 |= SPROM_WRITEEN;
15089 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
15090 + bcm_mdelay(WRITE_ENABLE_DELAY);
15091 + /* write srom */
15092 + for (i = 0; i < nw; i++) {
15093 + W_REG(&srom[off + i], p[i]);
15094 + bcm_mdelay(WRITE_WORD_DELAY);
15095 + }
15096 + /* disable writes to the SPROM */
15097 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
15098 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
15099 + /* enable writes to the SPROM */
15100 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
15101 + return 1;
15102 + bcm_mdelay(WRITE_ENABLE_DELAY);
15103 + /* write srom */
15104 + for (i = 0; i < nw; i++) {
15105 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
15106 + bcm_mdelay(WRITE_WORD_DELAY);
15107 + }
15108 + /* disable writes to the SPROM */
15109 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
15110 + return 1;
15111 + } else {
15112 + return 1;
15113 + }
15114 +
15115 + bcm_mdelay(WRITE_ENABLE_DELAY);
15116 + return 0;
15117 +}
15118 +
15119 +
15120 +static int
15121 +srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count)
15122 +{
15123 + char eabuf[32];
15124 + char *vp, *base;
15125 + uint8 tup, tlen, sromrev = 1;
15126 + int i, j;
15127 + uint varsize;
15128 + bool ag_init = FALSE;
15129 + uint32 w32;
15130 +
15131 + ASSERT(vars);
15132 + ASSERT(count);
15133 +
15134 + base = vp = MALLOC(osh, VARS_MAX);
15135 + ASSERT(vp);
15136 + if (!vp)
15137 + return -2;
15138 +
15139 + i = 0;
15140 + do {
15141 + tup = cis[i++];
15142 + tlen = cis[i++];
15143 + if ((i + tlen) >= CIS_SIZE)
15144 + break;
15145 +
15146 + switch (tup) {
15147 + case CISTPL_MANFID:
15148 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
15149 + vp++;
15150 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
15151 + vp++;
15152 + break;
15153 +
15154 + case CISTPL_FUNCE:
15155 + if (cis[i] == LAN_NID) {
15156 + ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
15157 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
15158 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
15159 + vp++;
15160 + }
15161 + break;
15162 +
15163 + case CISTPL_CFTABLE:
15164 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
15165 + vp++;
15166 + break;
15167 +
15168 + case CISTPL_BRCM_HNBU:
15169 + switch (cis[i]) {
15170 + case HNBU_SROMREV:
15171 + sromrev = cis[i + 1];
15172 + break;
15173 +
15174 + case HNBU_CHIPID:
15175 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
15176 + vp++;
15177 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
15178 + vp++;
15179 + if (tlen == 7) {
15180 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
15181 + vp++;
15182 + }
15183 + break;
15184 +
15185 + case HNBU_BOARDREV:
15186 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
15187 + vp++;
15188 + break;
15189 +
15190 + case HNBU_AA:
15191 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
15192 + vp++;
15193 + break;
15194 +
15195 + case HNBU_AG:
15196 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
15197 + vp++;
15198 + ag_init = TRUE;
15199 + break;
15200 +
15201 + case HNBU_CC:
15202 + ASSERT(sromrev > 1);
15203 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
15204 + vp++;
15205 + break;
15206 +
15207 + case HNBU_PAPARMS:
15208 + if (tlen == 2) {
15209 + ASSERT(sromrev == 1);
15210 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
15211 + vp++;
15212 + } else if (tlen >= 9) {
15213 + if (tlen == 10) {
15214 + ASSERT(sromrev == 2);
15215 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
15216 + vp++;
15217 + } else
15218 + ASSERT(tlen == 9);
15219 +
15220 + for (j = 0; j < 3; j++) {
15221 + vp += sprintf(vp, "pa0b%d=%d", j,
15222 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
15223 + vp++;
15224 + }
15225 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
15226 + vp++;
15227 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
15228 + vp++;
15229 + } else
15230 + ASSERT(tlen >= 9);
15231 + break;
15232 +
15233 + case HNBU_OEM:
15234 + ASSERT(sromrev == 1);
15235 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
15236 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
15237 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
15238 + vp++;
15239 + break;
15240 +
15241 + case HNBU_BOARDFLAGS:
15242 + w32 = (cis[i + 2] << 8) + cis[i + 1];
15243 + if (tlen == 5)
15244 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
15245 + vp += sprintf(vp, "boardflags=0x%x", w32);
15246 + vp++;
15247 + break;
15248 +
15249 + case HNBU_LEDS:
15250 + if (cis[i + 1] != 0xff) {
15251 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
15252 + vp++;
15253 + }
15254 + if (cis[i + 2] != 0xff) {
15255 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
15256 + vp++;
15257 + }
15258 + if (cis[i + 3] != 0xff) {
15259 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
15260 + vp++;
15261 + }
15262 + if (cis[i + 4] != 0xff) {
15263 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
15264 + vp++;
15265 + }
15266 + break;
15267 +
15268 + case HNBU_CCODE:
15269 + ASSERT(sromrev > 1);
15270 + vp += sprintf(vp, "ccode=%c%c", cis[i + 1], cis[i + 2]);
15271 + vp++;
15272 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
15273 + vp++;
15274 + break;
15275 +
15276 + case HNBU_CCKPO:
15277 + ASSERT(sromrev > 2);
15278 + vp += sprintf(vp, "cckpo=0x%x", (cis[i + 2] << 8) | cis[i + 1]);
15279 + vp++;
15280 + break;
15281 +
15282 + case HNBU_OFDMPO:
15283 + ASSERT(sromrev > 2);
15284 + vp += sprintf(vp, "ofdmpo=0x%x", (cis[i + 4] << 24) |
15285 + (cis[i + 3] << 16) | (cis[i + 2] << 8) | cis[i + 1]);
15286 + vp++;
15287 + break;
15288 + }
15289 + break;
15290 +
15291 + }
15292 + i += tlen;
15293 + } while (tup != 0xff);
15294 +
15295 + /* Set the srom version */
15296 + vp += sprintf(vp, "sromrev=%d", sromrev);
15297 + vp++;
15298 +
15299 + /* if there is no antenna gain field, set default */
15300 + if (ag_init == FALSE) {
15301 + ASSERT(sromrev == 1);
15302 + vp += sprintf(vp, "ag0=%d", 0xff);
15303 + vp++;
15304 + }
15305 +
15306 + /* final nullbyte terminator */
15307 + *vp++ = '\0';
15308 + varsize = (uint)(vp - base);
15309 +
15310 + ASSERT((vp - base) < VARS_MAX);
15311 +
15312 + if (varsize == VARS_MAX) {
15313 + *vars = base;
15314 + } else {
15315 + vp = MALLOC(osh, varsize);
15316 + ASSERT(vp);
15317 + if (vp)
15318 + bcopy(base, vp, varsize);
15319 + MFREE(osh, base, VARS_MAX);
15320 + *vars = vp;
15321 + if (!vp) {
15322 + *count = 0;
15323 + return -2;
15324 + }
15325 + }
15326 + *count = varsize;
15327 +
15328 + return (0);
15329 +}
15330 +
15331 +
15332 +/* set PCMCIA sprom command register */
15333 +static int
15334 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
15335 +{
15336 + uint8 status = 0;
15337 + uint wait_cnt = 1000;
15338 +
15339 + /* write sprom command register */
15340 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
15341 +
15342 + /* wait status */
15343 + while (wait_cnt--) {
15344 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
15345 + if (status & SROM_DONE)
15346 + return 0;
15347 + }
15348 +
15349 + return 1;
15350 +}
15351 +
15352 +/* read a word from the PCMCIA srom */
15353 +static int
15354 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
15355 +{
15356 + uint8 addr_l, addr_h, data_l, data_h;
15357 +
15358 + addr_l = (uint8)((addr * 2) & 0xff);
15359 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
15360 +
15361 + /* set address */
15362 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
15363 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
15364 +
15365 + /* do read */
15366 + if (sprom_cmd_pcmcia(osh, SROM_READ))
15367 + return 1;
15368 +
15369 + /* read data */
15370 + data_h = data_l = 0;
15371 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
15372 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
15373 +
15374 + *data = (data_h << 8) | data_l;
15375 + return 0;
15376 +}
15377 +
15378 +/* write a word to the PCMCIA srom */
15379 +static int
15380 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
15381 +{
15382 + uint8 addr_l, addr_h, data_l, data_h;
15383 +
15384 + addr_l = (uint8)((addr * 2) & 0xff);
15385 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
15386 + data_l = (uint8)(data & 0xff);
15387 + data_h = (uint8)((data >> 8) & 0xff);
15388 +
15389 + /* set address */
15390 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
15391 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
15392 +
15393 + /* write data */
15394 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
15395 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
15396 +
15397 + /* do write */
15398 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
15399 +}
15400 +
15401 +/*
15402 + * Read in and validate sprom.
15403 + * Return 0 on success, nonzero on error.
15404 + */
15405 +static int
15406 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
15407 +{
15408 + int err = 0;
15409 + uint i;
15410 +
15411 + /* read the sprom */
15412 + for (i = 0; i < nwords; i++)
15413 + buf[i] = R_REG(&sprom[wordoff + i]);
15414 +
15415 + if (check_crc) {
15416 + /* fixup the endianness so crc8 will pass */
15417 + htol16_buf(buf, nwords * 2);
15418 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
15419 + err = 1;
15420 + /* now correct the endianness of the byte array */
15421 + ltoh16_buf(buf, nwords * 2);
15422 + }
15423 +
15424 + return err;
15425 +}
15426 +
15427 +/*
15428 +* Create variable table from memory.
15429 +* Return 0 on success, nonzero on error.
15430 +*/
15431 +static int
15432 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
15433 +{
15434 + int c = (int)(end - start);
15435 +
15436 + /* do it only when there is more than just the null string */
15437 + if (c > 1) {
15438 + char *vp = MALLOC(osh, c);
15439 + ASSERT(vp);
15440 + if (!vp)
15441 + return BCME_NOMEM;
15442 + bcopy(start, vp, c);
15443 + *vars = vp;
15444 + *count = c;
15445 + }
15446 + else {
15447 + *vars = NULL;
15448 + *count = 0;
15449 + }
15450 +
15451 + return 0;
15452 +}
15453 +
15454 +/*
15455 +* Find variables with <devpath> from flash. 'base' points to the beginning
15456 +* of the table upon enter and to the end of the table upon exit when success.
15457 +* Return 0 on success, nonzero on error.
15458 +*/
15459 +static int
15460 +initvars_flash(osl_t *osh, char **base, int size, char *devpath)
15461 +{
15462 + char *vp = *base;
15463 + char *flash;
15464 + int err;
15465 + char *s;
15466 + uint l, dl, copy_len;
15467 +
15468 + /* allocate memory and read in flash */
15469 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
15470 + return BCME_NOMEM;
15471 + if ((err = BCMINIT(nvram_getall)(flash, NVRAM_SPACE)))
15472 + goto exit;
15473 +
15474 + /* grab vars with the <devpath> prefix in name */
15475 + dl = strlen(devpath);
15476 + for (s = flash; s && *s; s += l + 1) {
15477 + l = strlen(s);
15478 +
15479 + /* skip non-matching variable */
15480 + if (strncmp(s, devpath, dl))
15481 + continue;
15482 +
15483 + /* is there enough room to copy? */
15484 + copy_len = l - dl + 1;
15485 + if (size < (int)copy_len) {
15486 + err = BCME_BUFTOOSHORT;
15487 + goto exit;
15488 + }
15489 +
15490 + /* no prefix, just the name=value */
15491 + strcpy(vp, &s[dl]);
15492 + vp += copy_len;
15493 + size -= copy_len;
15494 + }
15495 +
15496 + /* add null string as terminator */
15497 + if (size < 1) {
15498 + err = BCME_BUFTOOSHORT;
15499 + goto exit;
15500 + }
15501 + *vp++ = '\0';
15502 +
15503 + *base = vp;
15504 +
15505 +exit: MFREE(osh, flash, NVRAM_SPACE);
15506 + return err;
15507 +}
15508 +
15509 +/*
15510 + * Initialize nonvolatile variable table from flash.
15511 + * Return 0 on success, nonzero on error.
15512 + */
15513 +static int
15514 +initvars_flash_sb(void *sbh, char **vars, int *count)
15515 +{
15516 + osl_t *osh = sb_osh(sbh);
15517 + char devpath[SB_DEVPATH_BUFSZ];
15518 + char *vp, *base;
15519 + int err;
15520 +
15521 + ASSERT(vars);
15522 + ASSERT(count);
15523 +
15524 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
15525 + return err;
15526 +
15527 + base = vp = MALLOC(osh, VARS_MAX);
15528 + ASSERT(vp);
15529 + if (!vp)
15530 + return BCME_NOMEM;
15531 +
15532 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
15533 + goto err;
15534 +
15535 + err = initvars_table(osh, base, vp, vars, count);
15536 +
15537 +err: MFREE(osh, base, VARS_MAX);
15538 + return err;
15539 +}
15540 +
15541 +/*
15542 + * Initialize nonvolatile variable table from sprom.
15543 + * Return 0 on success, nonzero on error.
15544 + */
15545 +static int
15546 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
15547 +{
15548 + uint16 w, b[64];
15549 + uint8 sromrev;
15550 + struct ether_addr ea;
15551 + char eabuf[32];
15552 + uint32 w32;
15553 + int woff, i;
15554 + char *vp, *base;
15555 + osl_t *osh = sb_osh(sbh);
15556 + bool flash = FALSE;
15557 + char name[SB_DEVPATH_BUFSZ+16], *value;
15558 + char devpath[SB_DEVPATH_BUFSZ];
15559 + int err;
15560 +
15561 + /*
15562 + * Apply CRC over SROM content regardless SROM is present or not,
15563 + * and use variable <devpath>sromrev's existance in flash to decide
15564 + * if we should return an error when CRC fails or read SROM variables
15565 + * from flash.
15566 + */
15567 + if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE)) {
15568 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
15569 + return err;
15570 + sprintf(name, "%ssromrev", devpath);
15571 + if (!(value = getvar(NULL, name)))
15572 + return (-1);
15573 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
15574 + flash = TRUE;
15575 + }
15576 + /* srom is good */
15577 + else {
15578 + /* top word of sprom contains version and crc8 */
15579 + sromrev = b[63] & 0xff;
15580 + /* bcm4401 sroms misprogrammed */
15581 + if (sromrev == 0x10)
15582 + sromrev = 1;
15583 + }
15584 +
15585 + /* srom version check */
15586 + if (sromrev > 3)
15587 + return (-2);
15588 +
15589 + ASSERT(vars);
15590 + ASSERT(count);
15591 +
15592 + base = vp = MALLOC(osh, VARS_MAX);
15593 + ASSERT(vp);
15594 + if (!vp)
15595 + return -2;
15596 +
15597 + /* read variables from flash */
15598 + if (flash) {
15599 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
15600 + goto err;
15601 + goto done;
15602 + }
15603 +
15604 + vp += sprintf(vp, "sromrev=%d", sromrev);
15605 + vp++;
15606 +
15607 + if (sromrev >= 3) {
15608 + /* New section takes over the 3th hardware function space */
15609 +
15610 + /* Words 22+23 are 11a (mid) ofdm power offsets */
15611 + w32 = ((uint32)b[23] << 16) | b[22];
15612 + vp += sprintf(vp, "ofdmapo=%d", w32);
15613 + vp++;
15614 +
15615 + /* Words 24+25 are 11a (low) ofdm power offsets */
15616 + w32 = ((uint32)b[25] << 16) | b[24];
15617 + vp += sprintf(vp, "ofdmalpo=%d", w32);
15618 + vp++;
15619 +
15620 + /* Words 26+27 are 11a (high) ofdm power offsets */
15621 + w32 = ((uint32)b[27] << 16) | b[26];
15622 + vp += sprintf(vp, "ofdmahpo=%d", w32);
15623 + vp++;
15624 +
15625 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
15626 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
15627 + vp += sprintf(vp, "gpiotimerval=%d", w32);
15628 +
15629 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
15630 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
15631 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
15632 + vp += sprintf(vp, "gpiotimerval=%d", w32);
15633 +
15634 + vp++;
15635 + }
15636 +
15637 + if (sromrev >= 2) {
15638 + /* New section takes over the 4th hardware function space */
15639 +
15640 + /* Word 29 is max power 11a high/low */
15641 + w = b[29];
15642 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
15643 + vp++;
15644 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
15645 + vp++;
15646 +
15647 + /* Words 30-32 set the 11alow pa settings,
15648 + * 33-35 are the 11ahigh ones.
15649 + */
15650 + for (i = 0; i < 3; i++) {
15651 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
15652 + vp++;
15653 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
15654 + vp++;
15655 + }
15656 + w = b[59];
15657 + if (w == 0)
15658 + vp += sprintf(vp, "ccode=");
15659 + else
15660 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
15661 + vp++;
15662 +
15663 + }
15664 +
15665 + /* parameter section of sprom starts at byte offset 72 */
15666 + woff = 72/2;
15667 +
15668 + /* first 6 bytes are il0macaddr */
15669 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15670 + ea.octet[1] = b[woff] & 0xff;
15671 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15672 + ea.octet[3] = b[woff+1] & 0xff;
15673 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15674 + ea.octet[5] = b[woff+2] & 0xff;
15675 + woff += ETHER_ADDR_LEN/2 ;
15676 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15677 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
15678 + vp++;
15679 +
15680 + /* next 6 bytes are et0macaddr */
15681 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15682 + ea.octet[1] = b[woff] & 0xff;
15683 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15684 + ea.octet[3] = b[woff+1] & 0xff;
15685 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15686 + ea.octet[5] = b[woff+2] & 0xff;
15687 + woff += ETHER_ADDR_LEN/2 ;
15688 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15689 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
15690 + vp++;
15691 +
15692 + /* next 6 bytes are et1macaddr */
15693 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15694 + ea.octet[1] = b[woff] & 0xff;
15695 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15696 + ea.octet[3] = b[woff+1] & 0xff;
15697 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15698 + ea.octet[5] = b[woff+2] & 0xff;
15699 + woff += ETHER_ADDR_LEN/2 ;
15700 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15701 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
15702 + vp++;
15703 +
15704 + /*
15705 + * Enet phy settings one or two singles or a dual
15706 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
15707 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
15708 + * Bit 14 : Mdio for enet0
15709 + * Bit 15 : Mdio for enet1
15710 + */
15711 + w = b[woff];
15712 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
15713 + vp++;
15714 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
15715 + vp++;
15716 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
15717 + vp++;
15718 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
15719 + vp++;
15720 +
15721 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
15722 + w = b[46];
15723 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
15724 + vp++;
15725 +
15726 + if (sromrev > 1)
15727 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
15728 + else
15729 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
15730 + vp++;
15731 +
15732 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
15733 + vp++;
15734 +
15735 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
15736 + vp++;
15737 +
15738 + /* Words 47-49 set the (wl) pa settings */
15739 + woff = 47;
15740 +
15741 + for (i = 0; i < 3; i++) {
15742 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
15743 + vp++;
15744 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
15745 + vp++;
15746 + }
15747 +
15748 + /*
15749 + * Words 50-51 set the customer-configured wl led behavior.
15750 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
15751 + * LED behavior values defined in wlioctl.h .
15752 + */
15753 + w = b[50];
15754 + if ((w != 0) && (w != 0xffff)) {
15755 + /* gpio0 */
15756 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
15757 + vp++;
15758 +
15759 + /* gpio1 */
15760 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
15761 + vp++;
15762 + }
15763 + w = b[51];
15764 + if ((w != 0) && (w != 0xffff)) {
15765 + /* gpio2 */
15766 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
15767 + vp++;
15768 +
15769 + /* gpio3 */
15770 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
15771 + vp++;
15772 + }
15773 +
15774 + /* Word 52 is max power 0/1 */
15775 + w = b[52];
15776 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
15777 + vp++;
15778 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
15779 + vp++;
15780 +
15781 + /* Word 56 is idle tssi target 0/1 */
15782 + w = b[56];
15783 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
15784 + vp++;
15785 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
15786 + vp++;
15787 +
15788 + /* Word 57 is boardflags, if not programmed make it zero */
15789 + w32 = (uint32)b[57];
15790 + if (w32 == 0xffff) w32 = 0;
15791 + if (sromrev > 1) {
15792 + /* Word 28 is the high bits of boardflags */
15793 + w32 |= (uint32)b[28] << 16;
15794 + }
15795 + vp += sprintf(vp, "boardflags=%d", w32);
15796 + vp++;
15797 +
15798 + /* Word 58 is antenna gain 0/1 */
15799 + w = b[58];
15800 + vp += sprintf(vp, "ag0=%d", w & 0xff);
15801 + vp++;
15802 +
15803 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
15804 + vp++;
15805 +
15806 + if (sromrev == 1) {
15807 + /* set the oem string */
15808 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
15809 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
15810 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
15811 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
15812 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
15813 + vp++;
15814 + } else if (sromrev == 2) {
15815 + /* Word 60 OFDM tx power offset from CCK level */
15816 + /* OFDM Power Offset - opo */
15817 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
15818 + vp++;
15819 + } else {
15820 + /* Word 60: cck power offsets */
15821 + vp += sprintf(vp, "cckpo=%d", b[60]);
15822 + vp++;
15823 +
15824 + /* Words 61+62: 11g ofdm power offsets */
15825 + w32 = ((uint32)b[62] << 16) | b[61];
15826 + vp += sprintf(vp, "ofdmgpo=%d", w32);
15827 + vp++;
15828 + }
15829 +
15830 + /* final nullbyte terminator */
15831 + *vp++ = '\0';
15832 +
15833 + ASSERT((vp - base) <= VARS_MAX);
15834 +
15835 +done: err = initvars_table(osh, base, vp, vars, count);
15836 +
15837 +err: MFREE(osh, base, VARS_MAX);
15838 + return err;
15839 +}
15840 +
15841 +/*
15842 + * Read the cis and call parsecis to initialize the vars.
15843 + * Return 0 on success, nonzero on error.
15844 + */
15845 +static int
15846 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count)
15847 +{
15848 + uint8 *cis = NULL;
15849 + int rc;
15850 + uint data_sz;
15851 +
15852 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
15853 +
15854 + if ((cis = MALLOC(osh, data_sz)) == NULL)
15855 + return (-2);
15856 +
15857 + if (sb_pcmciarev(sbh) == 1) {
15858 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
15859 + MFREE(osh, cis, data_sz);
15860 + return (-1);
15861 + }
15862 + /* fix up endianess for 16-bit data vs 8-bit parsing */
15863 + ltoh16_buf((uint16 *)cis, data_sz);
15864 + } else
15865 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
15866 +
15867 + rc = srom_parsecis(osh, cis, vars, count);
15868 +
15869 + MFREE(osh, cis, data_sz);
15870 +
15871 + return (rc);
15872 +}
15873 +
15874 diff -urN linux.old/drivers/net/hnd/bcmutils.c linux.dev/drivers/net/hnd/bcmutils.c
15875 --- linux.old/drivers/net/hnd/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
15876 +++ linux.dev/drivers/net/hnd/bcmutils.c 2005-11-08 12:52:21.836276500 +0100
15877 @@ -0,0 +1,1081 @@
15878 +/*
15879 + * Misc useful OS-independent routines.
15880 + *
15881 + * Copyright 2005, Broadcom Corporation
15882 + * All Rights Reserved.
15883 + *
15884 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15885 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15886 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15887 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15888 + * $Id$
15889 + */
15890 +
15891 +#include <typedefs.h>
15892 +#ifdef BCMDRIVER
15893 +#include <osl.h>
15894 +#include <sbutils.h>
15895 +#include <bcmnvram.h>
15896 +#else
15897 +#include <stdio.h>
15898 +#include <string.h>
15899 +#endif
15900 +#include <bcmutils.h>
15901 +#include <bcmendian.h>
15902 +#include <bcmdevs.h>
15903 +
15904 +#ifdef BCMDRIVER
15905 +/* copy a pkt buffer chain into a buffer */
15906 +uint
15907 +pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
15908 +{
15909 + uint n, ret = 0;
15910 +
15911 + if (len < 0)
15912 + len = 4096; /* "infinite" */
15913 +
15914 + /* skip 'offset' bytes */
15915 + for (; p && offset; p = PKTNEXT(osh, p)) {
15916 + if (offset < (uint)PKTLEN(osh, p))
15917 + break;
15918 + offset -= PKTLEN(osh, p);
15919 + }
15920 +
15921 + if (!p)
15922 + return 0;
15923 +
15924 + /* copy the data */
15925 + for (; p && len; p = PKTNEXT(osh, p)) {
15926 + n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
15927 + bcopy(PKTDATA(osh, p) + offset, buf, n);
15928 + buf += n;
15929 + len -= n;
15930 + ret += n;
15931 + offset = 0;
15932 + }
15933 +
15934 + return ret;
15935 +}
15936 +
15937 +/* return total length of buffer chain */
15938 +uint
15939 +pkttotlen(osl_t *osh, void *p)
15940 +{
15941 + uint total;
15942 +
15943 + total = 0;
15944 + for (; p; p = PKTNEXT(osh, p))
15945 + total += PKTLEN(osh, p);
15946 + return (total);
15947 +}
15948 +
15949 +void
15950 +pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[])
15951 +{
15952 + q->head = q->tail = NULL;
15953 + q->maxlen = maxlen;
15954 + q->len = 0;
15955 + if (prio_map) {
15956 + q->priority = TRUE;
15957 + bcopy(prio_map, q->prio_map, sizeof(q->prio_map));
15958 + }
15959 + else
15960 + q->priority = FALSE;
15961 +}
15962 +
15963 +/* should always check pktq_full before calling pktenq */
15964 +void
15965 +pktenq(struct pktq *q, void *p, bool lifo)
15966 +{
15967 + void *next, *prev;
15968 +
15969 + /* allow 10 pkts slack */
15970 + ASSERT(q->len < (q->maxlen + 10));
15971 +
15972 + /* Queueing chains not allowed */
15973 + ASSERT(PKTLINK(p) == NULL);
15974 +
15975 + /* Queue is empty */
15976 + if (q->tail == NULL) {
15977 + ASSERT(q->head == NULL);
15978 + q->head = q->tail = p;
15979 + }
15980 +
15981 + /* Insert at head or tail */
15982 + else if (q->priority == FALSE) {
15983 + /* Insert at head (LIFO) */
15984 + if (lifo) {
15985 + PKTSETLINK(p, q->head);
15986 + q->head = p;
15987 + }
15988 + /* Insert at tail (FIFO) */
15989 + else {
15990 + ASSERT(PKTLINK(q->tail) == NULL);
15991 + PKTSETLINK(q->tail, p);
15992 + PKTSETLINK(p, NULL);
15993 + q->tail = p;
15994 + }
15995 + }
15996 +
15997 + /* Insert by priority */
15998 + else {
15999 + /* legal priorities 0-7 */
16000 + ASSERT(PKTPRIO(p) <= MAXPRIO);
16001 +
16002 + ASSERT(q->head);
16003 + ASSERT(q->tail);
16004 + /* Shortcut to insertion at tail */
16005 + if (_pktq_pri(q, PKTPRIO(p)) < _pktq_pri(q, PKTPRIO(q->tail)) ||
16006 + (!lifo && _pktq_pri(q, PKTPRIO(p)) <= _pktq_pri(q, PKTPRIO(q->tail)))) {
16007 + prev = q->tail;
16008 + next = NULL;
16009 + }
16010 + /* Insert at head or in the middle */
16011 + else {
16012 + prev = NULL;
16013 + next = q->head;
16014 + }
16015 + /* Walk the queue */
16016 + for (; next; prev = next, next = PKTLINK(next)) {
16017 + /* Priority queue invariant */
16018 + ASSERT(!prev || _pktq_pri(q, PKTPRIO(prev)) >= _pktq_pri(q, PKTPRIO(next)));
16019 + /* Insert at head of string of packets of same priority (LIFO) */
16020 + if (lifo) {
16021 + if (_pktq_pri(q, PKTPRIO(p)) >= _pktq_pri(q, PKTPRIO(next)))
16022 + break;
16023 + }
16024 + /* Insert at tail of string of packets of same priority (FIFO) */
16025 + else {
16026 + if (_pktq_pri(q, PKTPRIO(p)) > _pktq_pri(q, PKTPRIO(next)))
16027 + break;
16028 + }
16029 + }
16030 + /* Insert at tail */
16031 + if (next == NULL) {
16032 + ASSERT(PKTLINK(q->tail) == NULL);
16033 + PKTSETLINK(q->tail, p);
16034 + PKTSETLINK(p, NULL);
16035 + q->tail = p;
16036 + }
16037 + /* Insert in the middle */
16038 + else if (prev) {
16039 + PKTSETLINK(prev, p);
16040 + PKTSETLINK(p, next);
16041 + }
16042 + /* Insert at head */
16043 + else {
16044 + PKTSETLINK(p, q->head);
16045 + q->head = p;
16046 + }
16047 + }
16048 +
16049 + /* List invariants after insertion */
16050 + ASSERT(q->head);
16051 + ASSERT(PKTLINK(q->tail) == NULL);
16052 +
16053 + q->len++;
16054 +}
16055 +
16056 +/* dequeue packet at head */
16057 +void*
16058 +pktdeq(struct pktq *q)
16059 +{
16060 + void *p;
16061 +
16062 + if ((p = q->head)) {
16063 + ASSERT(q->tail);
16064 + q->head = PKTLINK(p);
16065 + PKTSETLINK(p, NULL);
16066 + q->len--;
16067 + if (q->head == NULL)
16068 + q->tail = NULL;
16069 + }
16070 + else {
16071 + ASSERT(q->tail == NULL);
16072 + }
16073 +
16074 + return (p);
16075 +}
16076 +
16077 +/* dequeue packet at tail */
16078 +void*
16079 +pktdeqtail(struct pktq *q)
16080 +{
16081 + void *p;
16082 + void *next, *prev;
16083 +
16084 + if (q->head == q->tail) { /* last packet on queue or queue empty */
16085 + p = q->head;
16086 + q->head = q->tail = NULL;
16087 + q->len = 0;
16088 + return(p);
16089 + }
16090 +
16091 + /* start walk at head */
16092 + prev = NULL;
16093 + next = q->head;
16094 +
16095 + /* Walk the queue to find prev of q->tail */
16096 + for (; next; prev = next, next = PKTLINK(next)) {
16097 + if (next == q->tail)
16098 + break;
16099 + }
16100 +
16101 + ASSERT(prev);
16102 +
16103 + PKTSETLINK(prev, NULL);
16104 + q->tail = prev;
16105 + q->len--;
16106 + p = next;
16107 +
16108 + return (p);
16109 +}
16110 +
16111 +unsigned char bcm_ctype[] = {
16112 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
16113 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
16114 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
16115 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
16116 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
16117 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
16118 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
16119 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
16120 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
16121 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
16122 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
16123 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
16124 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
16125 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
16126 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
16127 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
16128 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
16129 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
16130 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
16131 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
16132 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
16133 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
16134 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
16135 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
16136 +};
16137 +
16138 +uchar
16139 +bcm_toupper(uchar c)
16140 +{
16141 + if (bcm_islower(c))
16142 + c -= 'a'-'A';
16143 + return (c);
16144 +}
16145 +
16146 +ulong
16147 +bcm_strtoul(char *cp, char **endp, uint base)
16148 +{
16149 + ulong result, value;
16150 + bool minus;
16151 +
16152 + minus = FALSE;
16153 +
16154 + while (bcm_isspace(*cp))
16155 + cp++;
16156 +
16157 + if (cp[0] == '+')
16158 + cp++;
16159 + else if (cp[0] == '-') {
16160 + minus = TRUE;
16161 + cp++;
16162 + }
16163 +
16164 + if (base == 0) {
16165 + if (cp[0] == '0') {
16166 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
16167 + base = 16;
16168 + cp = &cp[2];
16169 + } else {
16170 + base = 8;
16171 + cp = &cp[1];
16172 + }
16173 + } else
16174 + base = 10;
16175 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
16176 + cp = &cp[2];
16177 + }
16178 +
16179 + result = 0;
16180 +
16181 + while (bcm_isxdigit(*cp) &&
16182 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
16183 + result = result*base + value;
16184 + cp++;
16185 + }
16186 +
16187 + if (minus)
16188 + result = (ulong)(result * -1);
16189 +
16190 + if (endp)
16191 + *endp = (char *)cp;
16192 +
16193 + return (result);
16194 +}
16195 +
16196 +uint
16197 +bcm_atoi(char *s)
16198 +{
16199 + uint n;
16200 +
16201 + n = 0;
16202 +
16203 + while (bcm_isdigit(*s))
16204 + n = (n * 10) + *s++ - '0';
16205 + return (n);
16206 +}
16207 +
16208 +/* return pointer to location of substring 'needle' in 'haystack' */
16209 +char*
16210 +bcmstrstr(char *haystack, char *needle)
16211 +{
16212 + int len, nlen;
16213 + int i;
16214 +
16215 + if ((haystack == NULL) || (needle == NULL))
16216 + return (haystack);
16217 +
16218 + nlen = strlen(needle);
16219 + len = strlen(haystack) - nlen + 1;
16220 +
16221 + for (i = 0; i < len; i++)
16222 + if (bcmp(needle, &haystack[i], nlen) == 0)
16223 + return (&haystack[i]);
16224 + return (NULL);
16225 +}
16226 +
16227 +char*
16228 +bcmstrcat(char *dest, const char *src)
16229 +{
16230 + strcpy(&dest[strlen(dest)], src);
16231 + return (dest);
16232 +}
16233 +
16234 +#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
16235 +/* registry routine buffer preparation utility functions:
16236 + * parameter order is like strncpy, but returns count
16237 + * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
16238 + */
16239 +ulong
16240 +wchar2ascii(
16241 + char *abuf,
16242 + ushort *wbuf,
16243 + ushort wbuflen,
16244 + ulong abuflen
16245 +)
16246 +{
16247 + ulong copyct = 1;
16248 + ushort i;
16249 +
16250 + if (abuflen == 0)
16251 + return 0;
16252 +
16253 + /* wbuflen is in bytes */
16254 + wbuflen /= sizeof(ushort);
16255 +
16256 + for (i = 0; i < wbuflen; ++i) {
16257 + if (--abuflen == 0)
16258 + break;
16259 + *abuf++ = (char) *wbuf++;
16260 + ++copyct;
16261 + }
16262 + *abuf = '\0';
16263 +
16264 + return copyct;
16265 +}
16266 +#endif
16267 +
16268 +char*
16269 +bcm_ether_ntoa(char *ea, char *buf)
16270 +{
16271 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
16272 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
16273 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
16274 + return (buf);
16275 +}
16276 +
16277 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
16278 +int
16279 +bcm_ether_atoe(char *p, char *ea)
16280 +{
16281 + int i = 0;
16282 +
16283 + for (;;) {
16284 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
16285 + if (!*p++ || i == 6)
16286 + break;
16287 + }
16288 +
16289 + return (i == 6);
16290 +}
16291 +
16292 +void
16293 +bcm_mdelay(uint ms)
16294 +{
16295 + uint i;
16296 +
16297 + for (i = 0; i < ms; i++) {
16298 + OSL_DELAY(1000);
16299 + }
16300 +}
16301 +
16302 +/*
16303 + * Search the name=value vars for a specific one and return its value.
16304 + * Returns NULL if not found.
16305 + */
16306 +char*
16307 +getvar(char *vars, char *name)
16308 +{
16309 + char *s;
16310 + int len;
16311 +
16312 + len = strlen(name);
16313 +
16314 + /* first look in vars[] */
16315 + for (s = vars; s && *s; ) {
16316 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
16317 + return (&s[len+1]);
16318 +
16319 + while (*s++)
16320 + ;
16321 + }
16322 +
16323 + /* then query nvram */
16324 + return (BCMINIT(nvram_get)(name));
16325 +}
16326 +
16327 +/*
16328 + * Search the vars for a specific one and return its value as
16329 + * an integer. Returns 0 if not found.
16330 + */
16331 +int
16332 +getintvar(char *vars, char *name)
16333 +{
16334 + char *val;
16335 +
16336 + if ((val = getvar(vars, name)) == NULL)
16337 + return (0);
16338 +
16339 + return (bcm_strtoul(val, NULL, 0));
16340 +}
16341 +
16342 +
16343 +/* Search for token in comma separated token-string */
16344 +static int
16345 +findmatch(char *string, char *name)
16346 +{
16347 + uint len;
16348 + char *c;
16349 +
16350 + len = strlen(name);
16351 + while ((c = strchr(string, ',')) != NULL) {
16352 + if (len == (uint)(c - string) && !strncmp(string, name, len))
16353 + return 1;
16354 + string = c + 1;
16355 + }
16356 +
16357 + return (!strcmp(string, name));
16358 +}
16359 +
16360 +/* Return gpio pin number assigned to the named pin */
16361 +/*
16362 +* Variable should be in format:
16363 +*
16364 +* gpio<N>=pin_name,pin_name
16365 +*
16366 +* This format allows multiple features to share the gpio with mutual
16367 +* understanding.
16368 +*
16369 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
16370 +* and if def_pin is not used by others.
16371 +*/
16372 +uint
16373 +getgpiopin(char *vars, char *pin_name, uint def_pin)
16374 +{
16375 + char name[] = "gpioXXXX";
16376 + char *val;
16377 + uint pin;
16378 +
16379 + /* Go thru all possibilities till a match in pin name */
16380 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
16381 + sprintf(name, "gpio%d", pin);
16382 + val = getvar(vars, name);
16383 + if (val && findmatch(val, pin_name))
16384 + return pin;
16385 + }
16386 +
16387 + if (def_pin != GPIO_PIN_NOTDEFINED) {
16388 + /* make sure the default pin is not used by someone else */
16389 + sprintf(name, "gpio%d", def_pin);
16390 + if (getvar(vars, name)) {
16391 + def_pin = GPIO_PIN_NOTDEFINED;
16392 + }
16393 + }
16394 +
16395 + return def_pin;
16396 +}
16397 +
16398 +
16399 +static char bcm_undeferrstr[BCME_STRLEN];
16400 +
16401 +static const char *bcmerrorstrtable[] = \
16402 +{ "OK", /* 0 */
16403 + "Undefined error", /* BCME_ERROR */
16404 + "Bad Argument", /* BCME_BADARG*/
16405 + "Bad Option", /* BCME_BADOPTION*/
16406 + "Not up", /* BCME_NOTUP */
16407 + "Not down", /* BCME_NOTDOWN */
16408 + "Not AP", /* BCME_NOTAP */
16409 + "Not STA", /* BCME_NOTSTA */
16410 + "Bad Key Index", /* BCME_BADKEYIDX */
16411 + "Radio Off", /* BCME_RADIOOFF */
16412 + "Not band locked", /* BCME_NOTBANDLOCKED */
16413 + "No clock", /* BCME_NOCLK */
16414 + "Bad Rate valueset", /* BCME_BADRATESET */
16415 + "Bad Band", /* BCME_BADBAND */
16416 + "Buffer too short", /* BCME_BUFTOOSHORT */
16417 + "Buffer too length", /* BCME_BUFTOOLONG */
16418 + "Busy", /* BCME_BUSY */
16419 + "Not Associated", /* BCME_NOTASSOCIATED */
16420 + "Bad SSID len", /* BCME_BADSSIDLEN */
16421 + "Out of Range Channel", /* BCME_OUTOFRANGECHAN */
16422 + "Bad Channel", /* BCME_BADCHAN */
16423 + "Bad Address", /* BCME_BADADDR */
16424 + "Not Enough Resources", /* BCME_NORESOURCE */
16425 + "Unsupported", /* BCME_UNSUPPORTED */
16426 + "Bad length", /* BCME_BADLENGTH */
16427 + "Not Ready", /* BCME_NOTREADY */
16428 + "Not Permitted", /* BCME_EPERM */
16429 + "No Memory", /* BCME_NOMEM */
16430 + "Associated", /* BCME_ASSOCIATED */
16431 + "Not In Range", /* BCME_RANGE */
16432 + "Not Found" /* BCME_NOTFOUND */
16433 + };
16434 +
16435 +/* Convert the Error codes into related Error strings */
16436 +const char *
16437 +bcmerrorstr(int bcmerror)
16438 +{
16439 + int abs_bcmerror;
16440 +
16441 + abs_bcmerror = ABS(bcmerror);
16442 +
16443 + /* check if someone added a bcmerror code but forgot to add errorstring */
16444 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(bcmerrorstrtable) - 1));
16445 + if ( (bcmerror > 0) || (abs_bcmerror > ABS(BCME_LAST))) {
16446 + sprintf(bcm_undeferrstr, "undefined Error %d", bcmerror);
16447 + return bcm_undeferrstr;
16448 + }
16449 +
16450 + ASSERT((strlen((char*)bcmerrorstrtable[abs_bcmerror])) < BCME_STRLEN);
16451 +
16452 + return bcmerrorstrtable[abs_bcmerror];
16453 +}
16454 +#endif /* #ifdef BCMDRIVER */
16455 +
16456 +
16457 +/*******************************************************************************
16458 + * crc8
16459 + *
16460 + * Computes a crc8 over the input data using the polynomial:
16461 + *
16462 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
16463 + *
16464 + * The caller provides the initial value (either CRC8_INIT_VALUE
16465 + * or the previous returned value) to allow for processing of
16466 + * discontiguous blocks of data. When generating the CRC the
16467 + * caller is responsible for complementing the final return value
16468 + * and inserting it into the byte stream. When checking, a final
16469 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
16470 + *
16471 + * Reference: Dallas Semiconductor Application Note 27
16472 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
16473 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
16474 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
16475 + *
16476 + ******************************************************************************/
16477 +
16478 +static uint8 crc8_table[256] = {
16479 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
16480 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
16481 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
16482 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
16483 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
16484 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
16485 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
16486 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
16487 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
16488 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
16489 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
16490 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
16491 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
16492 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
16493 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
16494 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
16495 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
16496 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
16497 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
16498 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
16499 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
16500 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
16501 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
16502 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
16503 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
16504 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
16505 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
16506 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
16507 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
16508 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
16509 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
16510 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
16511 +};
16512 +
16513 +#define CRC_INNER_LOOP(n, c, x) \
16514 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
16515 +
16516 +uint8
16517 +hndcrc8(
16518 + uint8 *pdata, /* pointer to array of data to process */
16519 + uint nbytes, /* number of input data bytes to process */
16520 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
16521 +)
16522 +{
16523 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
16524 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
16525 + while (nbytes-- > 0)
16526 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
16527 +
16528 + return crc;
16529 +}
16530 +
16531 +/*******************************************************************************
16532 + * crc16
16533 + *
16534 + * Computes a crc16 over the input data using the polynomial:
16535 + *
16536 + * x^16 + x^12 +x^5 + 1
16537 + *
16538 + * The caller provides the initial value (either CRC16_INIT_VALUE
16539 + * or the previous returned value) to allow for processing of
16540 + * discontiguous blocks of data. When generating the CRC the
16541 + * caller is responsible for complementing the final return value
16542 + * and inserting it into the byte stream. When checking, a final
16543 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
16544 + *
16545 + * Reference: Dallas Semiconductor Application Note 27
16546 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
16547 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
16548 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
16549 + *
16550 + ******************************************************************************/
16551 +
16552 +static uint16 crc16_table[256] = {
16553 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
16554 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
16555 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
16556 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
16557 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
16558 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
16559 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
16560 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
16561 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
16562 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
16563 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
16564 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
16565 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
16566 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
16567 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
16568 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
16569 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
16570 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
16571 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
16572 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
16573 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
16574 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
16575 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
16576 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
16577 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
16578 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
16579 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
16580 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
16581 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
16582 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
16583 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
16584 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
16585 +};
16586 +
16587 +uint16
16588 +hndcrc16(
16589 + uint8 *pdata, /* pointer to array of data to process */
16590 + uint nbytes, /* number of input data bytes to process */
16591 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
16592 +)
16593 +{
16594 + while (nbytes-- > 0)
16595 + CRC_INNER_LOOP(16, crc, *pdata++);
16596 + return crc;
16597 +}
16598 +
16599 +static uint32 crc32_table[256] = {
16600 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
16601 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
16602 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
16603 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
16604 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
16605 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
16606 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
16607 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
16608 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
16609 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
16610 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
16611 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
16612 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
16613 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
16614 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
16615 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
16616 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
16617 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
16618 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
16619 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
16620 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
16621 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
16622 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
16623 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
16624 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
16625 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
16626 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
16627 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
16628 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
16629 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
16630 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
16631 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
16632 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
16633 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
16634 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
16635 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
16636 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
16637 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
16638 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
16639 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
16640 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
16641 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
16642 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
16643 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
16644 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
16645 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
16646 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
16647 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
16648 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
16649 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
16650 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
16651 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
16652 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
16653 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
16654 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
16655 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
16656 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
16657 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
16658 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
16659 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
16660 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
16661 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
16662 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
16663 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
16664 +};
16665 +
16666 +uint32
16667 +hndcrc32(
16668 + uint8 *pdata, /* pointer to array of data to process */
16669 + uint nbytes, /* number of input data bytes to process */
16670 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
16671 +)
16672 +{
16673 + uint8 *pend;
16674 +#ifdef __mips__
16675 + uint8 tmp[4];
16676 + ulong *tptr = (ulong *)tmp;
16677 +
16678 + /* in case the beginning of the buffer isn't aligned */
16679 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
16680 + nbytes -= (pend - pdata);
16681 + while (pdata < pend)
16682 + CRC_INNER_LOOP(32, crc, *pdata++);
16683 +
16684 + /* handle bulk of data as 32-bit words */
16685 + pend = pdata + (nbytes & 0xfffffffc);
16686 + while (pdata < pend) {
16687 + tptr = *((ulong *) pdata);
16688 + *((ulong *) pdata) += 1;
16689 + CRC_INNER_LOOP(32, crc, tmp[0]);
16690 + CRC_INNER_LOOP(32, crc, tmp[1]);
16691 + CRC_INNER_LOOP(32, crc, tmp[2]);
16692 + CRC_INNER_LOOP(32, crc, tmp[3]);
16693 + }
16694 +
16695 + /* 1-3 bytes at end of buffer */
16696 + pend = pdata + (nbytes & 0x03);
16697 + while (pdata < pend)
16698 + CRC_INNER_LOOP(32, crc, *pdata++);
16699 +#else
16700 + pend = pdata + nbytes;
16701 + while (pdata < pend)
16702 + CRC_INNER_LOOP(32, crc, *pdata++);
16703 +#endif
16704 +
16705 + return crc;
16706 +}
16707 +
16708 +#ifdef notdef
16709 +#define CLEN 1499
16710 +#define CBUFSIZ (CLEN+4)
16711 +#define CNBUFS 5
16712 +
16713 +void testcrc32(void)
16714 +{
16715 + uint j,k,l;
16716 + uint8 *buf;
16717 + uint len[CNBUFS];
16718 + uint32 crcr;
16719 + uint32 crc32tv[CNBUFS] =
16720 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
16721 +
16722 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
16723 +
16724 + /* step through all possible alignments */
16725 + for (l=0;l<=4;l++) {
16726 + for (j=0; j<CNBUFS; j++) {
16727 + len[j] = CLEN;
16728 + for (k=0; k<len[j]; k++)
16729 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
16730 + }
16731 +
16732 + for (j=0; j<CNBUFS; j++) {
16733 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
16734 + ASSERT(crcr == crc32tv[j]);
16735 + }
16736 + }
16737 +
16738 + MFREE(buf, CBUFSIZ*CNBUFS);
16739 + return;
16740 +}
16741 +#endif
16742 +
16743 +
16744 +/*
16745 + * Advance from the current 1-byte tag/1-byte length/variable-length value
16746 + * triple, to the next, returning a pointer to the next.
16747 + * If the current or next TLV is invalid (does not fit in given buffer length),
16748 + * NULL is returned.
16749 + * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
16750 + * by the TLV paramter's length if it is valid.
16751 + */
16752 +bcm_tlv_t *
16753 +bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
16754 +{
16755 + int len;
16756 +
16757 + /* validate current elt */
16758 + if (!bcm_valid_tlv(elt, *buflen))
16759 + return NULL;
16760 +
16761 + /* advance to next elt */
16762 + len = elt->len;
16763 + elt = (bcm_tlv_t*)(elt->data + len);
16764 + *buflen -= (2 + len);
16765 +
16766 + /* validate next elt */
16767 + if (!bcm_valid_tlv(elt, *buflen))
16768 + return NULL;
16769 +
16770 + return elt;
16771 +}
16772 +
16773 +/*
16774 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
16775 + * triples, returning a pointer to the substring whose first element
16776 + * matches tag
16777 + */
16778 +bcm_tlv_t *
16779 +bcm_parse_tlvs(void *buf, int buflen, uint key)
16780 +{
16781 + bcm_tlv_t *elt;
16782 + int totlen;
16783 +
16784 + elt = (bcm_tlv_t*)buf;
16785 + totlen = buflen;
16786 +
16787 + /* find tagged parameter */
16788 + while (totlen >= 2) {
16789 + int len = elt->len;
16790 +
16791 + /* validate remaining totlen */
16792 + if ((elt->id == key) && (totlen >= (len + 2)))
16793 + return (elt);
16794 +
16795 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
16796 + totlen -= (len + 2);
16797 + }
16798 +
16799 + return NULL;
16800 +}
16801 +
16802 +/*
16803 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
16804 + * triples, returning a pointer to the substring whose first element
16805 + * matches tag. Stop parsing when we see an element whose ID is greater
16806 + * than the target key.
16807 + */
16808 +bcm_tlv_t *
16809 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
16810 +{
16811 + bcm_tlv_t *elt;
16812 + int totlen;
16813 +
16814 + elt = (bcm_tlv_t*)buf;
16815 + totlen = buflen;
16816 +
16817 + /* find tagged parameter */
16818 + while (totlen >= 2) {
16819 + uint id = elt->id;
16820 + int len = elt->len;
16821 +
16822 + /* Punt if we start seeing IDs > than target key */
16823 + if (id > key)
16824 + return(NULL);
16825 +
16826 + /* validate remaining totlen */
16827 + if ((id == key) && (totlen >= (len + 2)))
16828 + return (elt);
16829 +
16830 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
16831 + totlen -= (len + 2);
16832 + }
16833 + return NULL;
16834 +}
16835 +/* routine to dump fields in a fileddesc structure */
16836 +
16837 +uint
16838 +bcmdumpfields(readreg_rtn read_rtn, void *arg0, void *arg1, struct fielddesc *fielddesc_array, char *buf, uint32 bufsize)
16839 +{
16840 + uint filled_len;
16841 + uint len;
16842 + struct fielddesc *cur_ptr;
16843 +
16844 + filled_len = 0;
16845 + cur_ptr = fielddesc_array;
16846 +
16847 + while (bufsize > (filled_len + 64)) {
16848 + if (cur_ptr->nameandfmt == NULL)
16849 + break;
16850 + len = sprintf(buf, cur_ptr->nameandfmt, read_rtn(arg0, arg1, cur_ptr->offset));
16851 + buf += len;
16852 + filled_len += len;
16853 + cur_ptr++;
16854 + }
16855 + return filled_len;
16856 +}
16857 +
16858 +uint
16859 +bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
16860 +{
16861 + uint len;
16862 +
16863 + len = strlen(name) + 1;
16864 +
16865 + if ((len + datalen) > buflen)
16866 + return 0;
16867 +
16868 + strcpy(buf, name);
16869 +
16870 + /* append data onto the end of the name string */
16871 + memcpy(&buf[len], data, datalen);
16872 + len += datalen;
16873 +
16874 + return len;
16875 +}
16876 +
16877 +/* Quarter dBm units to mW
16878 + * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
16879 + * Table is offset so the last entry is largest mW value that fits in
16880 + * a uint16.
16881 + */
16882 +
16883 +#define QDBM_OFFSET 153
16884 +#define QDBM_TABLE_LEN 40
16885 +
16886 +/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
16887 + * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
16888 + */
16889 +#define QDBM_TABLE_LOW_BOUND 6493
16890 +
16891 +/* Largest mW value that will round down to the last table entry,
16892 + * QDBM_OFFSET + QDBM_TABLE_LEN-1.
16893 + * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
16894 + */
16895 +#define QDBM_TABLE_HIGH_BOUND 64938
16896 +
16897 +static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
16898 +/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
16899 +/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
16900 +/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
16901 +/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
16902 +/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
16903 +/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
16904 +};
16905 +
16906 +uint16
16907 +bcm_qdbm_to_mw(uint8 qdbm)
16908 +{
16909 + uint factor = 1;
16910 + int idx = qdbm - QDBM_OFFSET;
16911 +
16912 + if (idx > QDBM_TABLE_LEN) {
16913 + /* clamp to max uint16 mW value */
16914 + return 0xFFFF;
16915 + }
16916 +
16917 + /* scale the qdBm index up to the range of the table 0-40
16918 + * where an offset of 40 qdBm equals a factor of 10 mW.
16919 + */
16920 + while (idx < 0) {
16921 + idx += 40;
16922 + factor *= 10;
16923 + }
16924 +
16925 + /* return the mW value scaled down to the correct factor of 10,
16926 + * adding in factor/2 to get proper rounding. */
16927 + return ((nqdBm_to_mW_map[idx] + factor/2) / factor);
16928 +}
16929 +
16930 +uint8
16931 +bcm_mw_to_qdbm(uint16 mw)
16932 +{
16933 + uint8 qdbm;
16934 + int offset;
16935 + uint mw_uint = mw;
16936 + uint boundary;
16937 +
16938 + /* handle boundary case */
16939 + if (mw_uint <= 1)
16940 + return 0;
16941 +
16942 + offset = QDBM_OFFSET;
16943 +
16944 + /* move mw into the range of the table */
16945 + while (mw_uint < QDBM_TABLE_LOW_BOUND) {
16946 + mw_uint *= 10;
16947 + offset -= 40;
16948 + }
16949 +
16950 + for (qdbm = 0; qdbm < QDBM_TABLE_LEN-1; qdbm++) {
16951 + boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm+1] - nqdBm_to_mW_map[qdbm])/2;
16952 + if (mw_uint < boundary) break;
16953 + }
16954 +
16955 + qdbm += (uint8)offset;
16956 +
16957 + return(qdbm);
16958 +}
16959 diff -urN linux.old/drivers/net/hnd/hnddma.c linux.dev/drivers/net/hnd/hnddma.c
16960 --- linux.old/drivers/net/hnd/hnddma.c 1970-01-01 01:00:00.000000000 +0100
16961 +++ linux.dev/drivers/net/hnd/hnddma.c 2005-11-08 16:07:38.846817500 +0100
16962 @@ -0,0 +1,1527 @@
16963 +/*
16964 + * Generic Broadcom Home Networking Division (HND) DMA module.
16965 + * This supports the following chips: BCM42xx, 44xx, 47xx .
16966 + *
16967 + * Copyright 2005, Broadcom Corporation
16968 + * All Rights Reserved.
16969 + *
16970 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
16971 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
16972 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16973 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16974 + *
16975 + * $Id$
16976 + */
16977 +
16978 +#include <typedefs.h>
16979 +#include <osl.h>
16980 +#include <bcmendian.h>
16981 +#include <sbconfig.h>
16982 +#include <bcmutils.h>
16983 +#include <bcmdevs.h>
16984 +#include <sbutils.h>
16985 +
16986 +struct dma_info; /* forward declaration */
16987 +#define di_t struct dma_info
16988 +
16989 +#include <sbhnddma.h>
16990 +#include <hnddma.h>
16991 +
16992 +/* debug/trace */
16993 +#define DMA_ERROR(args)
16994 +#define DMA_TRACE(args)
16995 +
16996 +/* default dma message level (if input msg_level pointer is null in dma_attach()) */
16997 +static uint dma_msg_level =
16998 + 0;
16999 +
17000 +#define MAXNAMEL 8
17001 +
17002 +/* dma engine software state */
17003 +typedef struct dma_info {
17004 + hnddma_t hnddma; /* exported structure */
17005 + uint *msg_level; /* message level pointer */
17006 + char name[MAXNAMEL]; /* callers name for diag msgs */
17007 +
17008 + void *osh; /* os handle */
17009 + sb_t *sbh; /* sb handle */
17010 +
17011 + bool dma64; /* dma64 enabled */
17012 + bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
17013 +
17014 + dma32regs_t *d32txregs; /* 32 bits dma tx engine registers */
17015 + dma32regs_t *d32rxregs; /* 32 bits dma rx engine registers */
17016 + dma64regs_t *d64txregs; /* 64 bits dma tx engine registers */
17017 + dma64regs_t *d64rxregs; /* 64 bits dma rx engine registers */
17018 +
17019 + uint32 dma64align; /* either 8k or 4k depends on number of dd */
17020 + dma32dd_t *txd32; /* pointer to dma32 tx descriptor ring */
17021 + dma64dd_t *txd64; /* pointer to dma64 tx descriptor ring */
17022 + uint ntxd; /* # tx descriptors tunable */
17023 + uint txin; /* index of next descriptor to reclaim */
17024 + uint txout; /* index of next descriptor to post */
17025 + uint txavail; /* # free tx descriptors */
17026 + void **txp; /* pointer to parallel array of pointers to packets */
17027 + ulong txdpa; /* physical address of descriptor ring */
17028 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
17029 + uint txdalloc; /* #bytes allocated for the ring */
17030 +
17031 + dma32dd_t *rxd32; /* pointer to dma32 rx descriptor ring */
17032 + dma64dd_t *rxd64; /* pointer to dma64 rx descriptor ring */
17033 + uint nrxd; /* # rx descriptors tunable */
17034 + uint rxin; /* index of next descriptor to reclaim */
17035 + uint rxout; /* index of next descriptor to post */
17036 + void **rxp; /* pointer to parallel array of pointers to packets */
17037 + ulong rxdpa; /* physical address of descriptor ring */
17038 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
17039 + uint rxdalloc; /* #bytes allocated for the ring */
17040 +
17041 + /* tunables */
17042 + uint rxbufsize; /* rx buffer size in bytes */
17043 + uint nrxpost; /* # rx buffers to keep posted */
17044 + uint rxoffset; /* rxcontrol offset */
17045 + uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
17046 + uint ddoffsethigh; /* add to get dma address of descriptor ring, high 32 bits */
17047 + uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
17048 + uint dataoffsethigh; /* add to get dma address of data buffer, high 32 bits */
17049 +} dma_info_t;
17050 +
17051 +#ifdef BCMDMA64
17052 +#define DMA64_ENAB(di) ((di)->dma64)
17053 +#else
17054 +#define DMA64_ENAB(di) (0)
17055 +#endif
17056 +
17057 +/* descriptor bumping macros */
17058 +#define XXD(x, n) ((x) & ((n) - 1))
17059 +#define TXD(x) XXD((x), di->ntxd)
17060 +#define RXD(x) XXD((x), di->nrxd)
17061 +#define NEXTTXD(i) TXD(i + 1)
17062 +#define PREVTXD(i) TXD(i - 1)
17063 +#define NEXTRXD(i) RXD(i + 1)
17064 +#define NTXDACTIVE(h, t) TXD(t - h)
17065 +#define NRXDACTIVE(h, t) RXD(t - h)
17066 +
17067 +/* macros to convert between byte offsets and indexes */
17068 +#define B2I(bytes, type) ((bytes) / sizeof(type))
17069 +#define I2B(index, type) ((index) * sizeof(type))
17070 +
17071 +#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
17072 +#define PCI32ADDR_HIGH_SHIFT 30
17073 +
17074 +
17075 +/* prototypes */
17076 +static bool dma_isaddrext(dma_info_t *di);
17077 +static bool dma_alloc(dma_info_t *di, uint direction);
17078 +
17079 +static bool dma32_alloc(dma_info_t *di, uint direction);
17080 +static void dma32_txreset(dma_info_t *di);
17081 +static void dma32_rxreset(dma_info_t *di);
17082 +static bool dma32_txsuspendedidle(dma_info_t *di);
17083 +static int dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags);
17084 +static void* dma32_getnexttxp(dma_info_t *di, bool forceall);
17085 +static void* dma32_getnextrxp(dma_info_t *di, bool forceall);
17086 +static void dma32_txrotate(di_t *di);
17087 +
17088 +/* prototype or stubs */
17089 +#ifdef BCMDMA64
17090 +static bool dma64_alloc(dma_info_t *di, uint direction);
17091 +static void dma64_txreset(dma_info_t *di);
17092 +static void dma64_rxreset(dma_info_t *di);
17093 +static bool dma64_txsuspendedidle(dma_info_t *di);
17094 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags);
17095 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall);
17096 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall);
17097 +static void dma64_txrotate(di_t *di);
17098 +#else
17099 +static bool dma64_alloc(dma_info_t *di, uint direction) { return TRUE; }
17100 +static void dma64_txreset(dma_info_t *di) {}
17101 +static void dma64_rxreset(dma_info_t *di) {}
17102 +static bool dma64_txsuspendedidle(dma_info_t *di) { return TRUE;}
17103 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags) { return 0; }
17104 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall) { return NULL; }
17105 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall) { return NULL; }
17106 +static void dma64_txrotate(di_t *di) { return; }
17107 +#endif
17108 +
17109 +/* old dmaregs struct for compatibility */
17110 +typedef volatile struct {
17111 + /* transmit channel */
17112 + uint32 xmtcontrol; /* enable, et al */
17113 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
17114 + uint32 xmtptr; /* last descriptor posted to chip */
17115 + uint32 xmtstatus; /* current active descriptor, et al */
17116 +
17117 + /* receive channel */
17118 + uint32 rcvcontrol; /* enable, et al */
17119 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
17120 + uint32 rcvptr; /* last descriptor posted to chip */
17121 + uint32 rcvstatus; /* current active descriptor, et al */
17122 +} dmaregs_t;
17123 +
17124 +typedef struct {
17125 + uint ddoffset;
17126 + uint dataoffset;
17127 +} compat_data;
17128 +
17129 +static compat_data *ugly_hack = NULL;
17130 +
17131 +void*
17132 +dma_attold(void *drv, void *osh, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
17133 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
17134 +{
17135 + dma32regs_t *dtx = regs;
17136 + dma32regs_t *drx = dtx + 1;
17137 +
17138 + ugly_hack = kmalloc(sizeof(ugly_hack), GFP_KERNEL);
17139 + ugly_hack->ddoffset = ddoffset;
17140 + ugly_hack->dataoffset = dataoffset;
17141 + dma_attach((osl_t *) osh, name, NULL, dtx, drx, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, msg_level);
17142 + ugly_hack = NULL;
17143 +}
17144 +
17145 +
17146 +void*
17147 +dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
17148 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level)
17149 +{
17150 + dma_info_t *di;
17151 + uint size;
17152 +
17153 + /* allocate private info structure */
17154 + if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
17155 + return (NULL);
17156 + }
17157 + bzero((char*)di, sizeof (dma_info_t));
17158 +
17159 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
17160 +
17161 + if (sbh != NULL)
17162 + di->dma64 = ((sb_coreflagshi(sbh, 0, 0) & SBTMH_DMA64) == SBTMH_DMA64);
17163 +
17164 +#ifndef BCMDMA64
17165 + if (di->dma64) {
17166 + DMA_ERROR(("dma_attach: driver doesn't have the capability to support 64 bits DMA\n"));
17167 + goto fail;
17168 + }
17169 +#endif
17170 +
17171 + /* check arguments */
17172 + ASSERT(ISPOWEROF2(ntxd));
17173 + ASSERT(ISPOWEROF2(nrxd));
17174 + if (nrxd == 0)
17175 + ASSERT(dmaregsrx == NULL);
17176 + if (ntxd == 0)
17177 + ASSERT(dmaregstx == NULL);
17178 +
17179 +
17180 + /* init dma reg pointer */
17181 + if (di->dma64) {
17182 + ASSERT(ntxd <= D64MAXDD);
17183 + ASSERT(nrxd <= D64MAXDD);
17184 + di->d64txregs = (dma64regs_t *)dmaregstx;
17185 + di->d64rxregs = (dma64regs_t *)dmaregsrx;
17186 +
17187 + di->dma64align = D64RINGALIGN;
17188 + if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
17189 + /* for smaller dd table, HW relax the alignment requirement */
17190 + di->dma64align = D64RINGALIGN / 2;
17191 + }
17192 + } else {
17193 + ASSERT(ntxd <= D32MAXDD);
17194 + ASSERT(nrxd <= D32MAXDD);
17195 + di->d32txregs = (dma32regs_t *)dmaregstx;
17196 + di->d32rxregs = (dma32regs_t *)dmaregsrx;
17197 + }
17198 +
17199 +
17200 + /* make a private copy of our callers name */
17201 + strncpy(di->name, name, MAXNAMEL);
17202 + di->name[MAXNAMEL-1] = '\0';
17203 +
17204 + di->osh = osh;
17205 + di->sbh = sbh;
17206 +
17207 + /* save tunables */
17208 + di->ntxd = ntxd;
17209 + di->nrxd = nrxd;
17210 + di->rxbufsize = rxbufsize;
17211 + di->nrxpost = nrxpost;
17212 + di->rxoffset = rxoffset;
17213 +
17214 + /*
17215 + * figure out the DMA physical address offset for dd and data
17216 + * for old chips w/o sb, use zero
17217 + * for new chips w sb,
17218 + * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
17219 + * Other bus: use zero
17220 + * SB_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
17221 + */
17222 + di->ddoffsetlow = 0;
17223 + di->dataoffsetlow = 0;
17224 + if (ugly_hack != NULL) {
17225 + di->ddoffsetlow = ugly_hack->ddoffset;
17226 + di->dataoffsetlow = ugly_hack->dataoffset;
17227 + di->ddoffsethigh = 0;
17228 + di->dataoffsethigh = 0;
17229 + } else if (sbh != NULL) {
17230 + if (sbh->bustype == PCI_BUS) { /* for pci bus, add offset */
17231 + if ((sbh->buscoretype == SB_PCIE) && di->dma64){
17232 + di->ddoffsetlow = 0;
17233 + di->ddoffsethigh = SB_PCIE_DMA_H32;
17234 + } else {
17235 + di->ddoffsetlow = SB_PCI_DMA;
17236 + di->ddoffsethigh = 0;
17237 + }
17238 + di->dataoffsetlow = di->ddoffsetlow;
17239 + di->dataoffsethigh = di->ddoffsethigh;
17240 + }
17241 +#if defined(__mips__) && defined(IL_BIGENDIAN)
17242 + /* use sdram swapped region for data buffers but not dma descriptors */
17243 + di->dataoffsetlow = di->dataoffsetlow + SB_SDRAM_SWAPPED;
17244 +#endif
17245 + }
17246 +
17247 + di->addrext = ((ugly_hack == NULL) ? dma_isaddrext(di) : 0);
17248 +
17249 + DMA_TRACE(("%s: dma_attach: osh %p ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n",
17250 + name, osh, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, di->ddoffsetlow, di->dataoffsetlow));
17251 +
17252 + /* allocate tx packet pointer vector */
17253 + if (ntxd) {
17254 + size = ntxd * sizeof (void*);
17255 + if ((di->txp = MALLOC(osh, size)) == NULL) {
17256 + DMA_ERROR(("%s: dma_attach: out of tx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
17257 + goto fail;
17258 + }
17259 + bzero((char*)di->txp, size);
17260 + }
17261 +
17262 + /* allocate rx packet pointer vector */
17263 + if (nrxd) {
17264 + size = nrxd * sizeof (void*);
17265 + if ((di->rxp = MALLOC(osh, size)) == NULL) {
17266 + DMA_ERROR(("%s: dma_attach: out of rx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
17267 + goto fail;
17268 + }
17269 + bzero((char*)di->rxp, size);
17270 + }
17271 +
17272 + /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
17273 + if (ntxd) {
17274 + if (!dma_alloc(di, DMA_TX))
17275 + goto fail;
17276 + }
17277 +
17278 + /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
17279 + if (nrxd) {
17280 + if (!dma_alloc(di, DMA_RX))
17281 + goto fail;
17282 + }
17283 +
17284 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->txdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17285 + DMA_ERROR(("%s: dma_attach: txdpa 0x%lx: addrext not supported\n", di->name, di->txdpa));
17286 + goto fail;
17287 + }
17288 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->rxdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17289 + DMA_ERROR(("%s: dma_attach: rxdpa 0x%lx: addrext not supported\n", di->name, di->rxdpa));
17290 + goto fail;
17291 + }
17292 +
17293 + return ((void*)di);
17294 +
17295 +fail:
17296 + dma_detach((void*)di);
17297 + return (NULL);
17298 +}
17299 +
17300 +static bool
17301 +dma_alloc(dma_info_t *di, uint direction)
17302 +{
17303 + if (DMA64_ENAB(di)) {
17304 + return dma64_alloc(di, direction);
17305 + } else {
17306 + return dma32_alloc(di, direction);
17307 + }
17308 +}
17309 +
17310 +/* may be called with core in reset */
17311 +void
17312 +dma_detach(dma_info_t *di)
17313 +{
17314 + if (di == NULL)
17315 + return;
17316 +
17317 + DMA_TRACE(("%s: dma_detach\n", di->name));
17318 +
17319 + /* shouldn't be here if descriptors are unreclaimed */
17320 + ASSERT(di->txin == di->txout);
17321 + ASSERT(di->rxin == di->rxout);
17322 +
17323 + /* free dma descriptor rings */
17324 + if (di->txd32)
17325 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd32 - di->txdalign), di->txdalloc, (di->txdpa - di->txdalign));
17326 + if (di->rxd32)
17327 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd32 - di->rxdalign), di->rxdalloc, (di->rxdpa - di->rxdalign));
17328 +
17329 + /* free packet pointer vectors */
17330 + if (di->txp)
17331 + MFREE(di->osh, (void*)di->txp, (di->ntxd * sizeof (void*)));
17332 + if (di->rxp)
17333 + MFREE(di->osh, (void*)di->rxp, (di->nrxd * sizeof (void*)));
17334 +
17335 + /* free our private info structure */
17336 + MFREE(di->osh, (void*)di, sizeof (dma_info_t));
17337 +}
17338 +
17339 +/* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
17340 +static bool
17341 +dma_isaddrext(dma_info_t *di)
17342 +{
17343 + uint32 w;
17344 +
17345 + if (DMA64_ENAB(di)) {
17346 + OR_REG(&di->d64txregs->control, D64_XC_AE);
17347 + w = R_REG(&di->d32txregs->control);
17348 + AND_REG(&di->d32txregs->control, ~D64_XC_AE);
17349 + return ((w & XC_AE) == D64_XC_AE);
17350 + } else {
17351 + OR_REG(&di->d32txregs->control, XC_AE);
17352 + w = R_REG(&di->d32txregs->control);
17353 + AND_REG(&di->d32txregs->control, ~XC_AE);
17354 + return ((w & XC_AE) == XC_AE);
17355 + }
17356 +}
17357 +
17358 +void
17359 +dma_txreset(dma_info_t *di)
17360 +{
17361 + DMA_TRACE(("%s: dma_txreset\n", di->name));
17362 +
17363 + if (DMA64_ENAB(di))
17364 + dma64_txreset(di);
17365 + else
17366 + dma32_txreset(di);
17367 +}
17368 +
17369 +void
17370 +dma_rxreset(dma_info_t *di)
17371 +{
17372 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
17373 +
17374 + if (DMA64_ENAB(di))
17375 + dma64_rxreset(di);
17376 + else
17377 + dma32_rxreset(di);
17378 +}
17379 +
17380 +/* initialize descriptor table base address */
17381 +static void
17382 +dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
17383 +{
17384 + if (DMA64_ENAB(di)) {
17385 + if (direction == DMA_TX) {
17386 + W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
17387 + W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
17388 + } else {
17389 + W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
17390 + W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
17391 + }
17392 + } else {
17393 + uint32 offset = di->ddoffsetlow;
17394 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17395 + if (direction == DMA_TX)
17396 + W_REG(&di->d32txregs->addr, (pa + offset));
17397 + else
17398 + W_REG(&di->d32rxregs->addr, (pa + offset));
17399 + } else {
17400 + /* dma32 address extension */
17401 + uint32 ae;
17402 + ASSERT(di->addrext);
17403 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17404 +
17405 + if (direction == DMA_TX) {
17406 + W_REG(&di->d32txregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
17407 + SET_REG(&di->d32txregs->control, XC_AE, (ae << XC_AE_SHIFT));
17408 + } else {
17409 + W_REG(&di->d32rxregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
17410 + SET_REG(&di->d32rxregs->control, RC_AE, (ae << RC_AE_SHIFT));
17411 + }
17412 + }
17413 + }
17414 +}
17415 +
17416 +/* init the tx or rx descriptor */
17417 +static INLINE void
17418 +dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, ulong pa, uint outidx, uint32 *ctrl)
17419 +{
17420 + uint offset = di->dataoffsetlow;
17421 +
17422 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17423 + W_SM(&ddring[outidx].addr, BUS_SWAP32(pa + offset));
17424 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
17425 + } else {
17426 + /* address extension */
17427 + uint32 ae;
17428 + ASSERT(di->addrext);
17429 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17430 +
17431 + *ctrl |= (ae << CTRL_AE_SHIFT);
17432 + W_SM(&ddring[outidx].addr, BUS_SWAP32((pa & ~PCI32ADDR_HIGH) + offset));
17433 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
17434 + }
17435 +}
17436 +
17437 +/* init the tx or rx descriptor */
17438 +static INLINE void
17439 +dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, ulong pa, uint outidx, uint32 *flags, uint32 bufcount)
17440 +{
17441 + uint32 bufaddr_low = pa + di->dataoffsetlow;
17442 + uint32 bufaddr_high = 0 + di->dataoffsethigh;
17443 +
17444 + uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
17445 +
17446 + W_SM(&ddring[outidx].addrlow, BUS_SWAP32(bufaddr_low));
17447 + W_SM(&ddring[outidx].addrhigh, BUS_SWAP32(bufaddr_high));
17448 + W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
17449 + W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
17450 +}
17451 +
17452 +void
17453 +dma_txinit(dma_info_t *di)
17454 +{
17455 + DMA_TRACE(("%s: dma_txinit\n", di->name));
17456 +
17457 + di->txin = di->txout = 0;
17458 + di->txavail = di->ntxd - 1;
17459 +
17460 + /* clear tx descriptor ring */
17461 + if (DMA64_ENAB(di)) {
17462 + BZERO_SM((void*)di->txd64, (di->ntxd * sizeof (dma64dd_t)));
17463 + W_REG(&di->d64txregs->control, XC_XE);
17464 + dma_ddtable_init(di, DMA_TX, di->txdpa);
17465 + } else {
17466 + BZERO_SM((void*)di->txd32, (di->ntxd * sizeof (dma32dd_t)));
17467 + W_REG(&di->d32txregs->control, XC_XE);
17468 + dma_ddtable_init(di, DMA_TX, di->txdpa);
17469 + }
17470 +}
17471 +
17472 +bool
17473 +dma_txenabled(dma_info_t *di)
17474 +{
17475 + uint32 xc;
17476 +
17477 + /* If the chip is dead, it is not enabled :-) */
17478 + if (DMA64_ENAB(di)) {
17479 + xc = R_REG(&di->d64txregs->control);
17480 + return ((xc != 0xffffffff) && (xc & D64_XC_XE));
17481 + } else {
17482 + xc = R_REG(&di->d32txregs->control);
17483 + return ((xc != 0xffffffff) && (xc & XC_XE));
17484 + }
17485 +}
17486 +
17487 +void
17488 +dma_txsuspend(dma_info_t *di)
17489 +{
17490 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
17491 + if (DMA64_ENAB(di))
17492 + OR_REG(&di->d64txregs->control, D64_XC_SE);
17493 + else
17494 + OR_REG(&di->d32txregs->control, XC_SE);
17495 +}
17496 +
17497 +void
17498 +dma_txresume(dma_info_t *di)
17499 +{
17500 + DMA_TRACE(("%s: dma_txresume\n", di->name));
17501 + if (DMA64_ENAB(di))
17502 + AND_REG(&di->d64txregs->control, ~D64_XC_SE);
17503 + else
17504 + AND_REG(&di->d32txregs->control, ~XC_SE);
17505 +}
17506 +
17507 +bool
17508 +dma_txsuspendedidle(dma_info_t *di)
17509 +{
17510 + if (DMA64_ENAB(di))
17511 + return dma64_txsuspendedidle(di);
17512 + else
17513 + return dma32_txsuspendedidle(di);
17514 +}
17515 +
17516 +bool
17517 +dma_txsuspended(dma_info_t *di)
17518 +{
17519 + if (DMA64_ENAB(di))
17520 + return ((R_REG(&di->d64txregs->control) & D64_XC_SE) == D64_XC_SE);
17521 + else
17522 + return ((R_REG(&di->d32txregs->control) & XC_SE) == XC_SE);
17523 +}
17524 +
17525 +bool
17526 +dma_txstopped(dma_info_t *di)
17527 +{
17528 + if (DMA64_ENAB(di))
17529 + return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_STOPPED);
17530 + else
17531 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_STOPPED);
17532 +}
17533 +
17534 +bool
17535 +dma_rxstopped(dma_info_t *di)
17536 +{
17537 + if (DMA64_ENAB(di))
17538 + return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) == D64_RS0_RS_STOPPED);
17539 + else
17540 + return ((R_REG(&di->d32rxregs->status) & RS_RS_MASK) == RS_RS_STOPPED);
17541 +}
17542 +
17543 +void
17544 +dma_fifoloopbackenable(dma_info_t *di)
17545 +{
17546 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
17547 + if (DMA64_ENAB(di))
17548 + OR_REG(&di->d64txregs->control, D64_XC_LE);
17549 + else
17550 + OR_REG(&di->d32txregs->control, XC_LE);
17551 +}
17552 +
17553 +void
17554 +dma_rxinit(dma_info_t *di)
17555 +{
17556 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
17557 +
17558 + di->rxin = di->rxout = 0;
17559 +
17560 + /* clear rx descriptor ring */
17561 + if (DMA64_ENAB(di)) {
17562 + BZERO_SM((void*)di->rxd64, (di->nrxd * sizeof (dma64dd_t)));
17563 + dma_rxenable(di);
17564 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
17565 + } else {
17566 + BZERO_SM((void*)di->rxd32, (di->nrxd * sizeof (dma32dd_t)));
17567 + dma_rxenable(di);
17568 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
17569 + }
17570 +}
17571 +
17572 +void
17573 +dma_rxenable(dma_info_t *di)
17574 +{
17575 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
17576 + if (DMA64_ENAB(di))
17577 + W_REG(&di->d64rxregs->control, ((di->rxoffset << D64_RC_RO_SHIFT) | D64_RC_RE));
17578 + else
17579 + W_REG(&di->d32rxregs->control, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
17580 +}
17581 +
17582 +bool
17583 +dma_rxenabled(dma_info_t *di)
17584 +{
17585 + uint32 rc;
17586 +
17587 + if (DMA64_ENAB(di)) {
17588 + rc = R_REG(&di->d64rxregs->control);
17589 + return ((rc != 0xffffffff) && (rc & D64_RC_RE));
17590 + } else {
17591 + rc = R_REG(&di->d32rxregs->control);
17592 + return ((rc != 0xffffffff) && (rc & RC_RE));
17593 + }
17594 +}
17595 +
17596 +
17597 +/* !! tx entry routine */
17598 +int
17599 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
17600 +{
17601 + if (DMA64_ENAB(di)) {
17602 + return dma64_txfast(di, p0, coreflags);
17603 + } else {
17604 + return dma32_txfast(di, p0, coreflags);
17605 + }
17606 +}
17607 +
17608 +/* !! rx entry routine, returns a pointer to the next frame received, or NULL if there are no more */
17609 +void*
17610 +dma_rx(dma_info_t *di)
17611 +{
17612 + void *p;
17613 + uint len;
17614 + int skiplen = 0;
17615 +
17616 + while ((p = dma_getnextrxp(di, FALSE))) {
17617 + /* skip giant packets which span multiple rx descriptors */
17618 + if (skiplen > 0) {
17619 + skiplen -= di->rxbufsize;
17620 + if (skiplen < 0)
17621 + skiplen = 0;
17622 + PKTFREE(di->osh, p, FALSE);
17623 + continue;
17624 + }
17625 +
17626 + len = ltoh16(*(uint16*)(PKTDATA(di->osh, p)));
17627 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
17628 +
17629 + /* bad frame length check */
17630 + if (len > (di->rxbufsize - di->rxoffset)) {
17631 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
17632 + if (len > 0)
17633 + skiplen = len - (di->rxbufsize - di->rxoffset);
17634 + PKTFREE(di->osh, p, FALSE);
17635 + di->hnddma.rxgiants++;
17636 + continue;
17637 + }
17638 +
17639 + /* set actual length */
17640 + PKTSETLEN(di->osh, p, (di->rxoffset + len));
17641 +
17642 + break;
17643 + }
17644 +
17645 + return (p);
17646 +}
17647 +
17648 +/* post receive buffers */
17649 +void
17650 +dma_rxfill(dma_info_t *di)
17651 +{
17652 + void *p;
17653 + uint rxin, rxout;
17654 + uint32 ctrl;
17655 + uint n;
17656 + uint i;
17657 + uint32 pa;
17658 + uint rxbufsize;
17659 +
17660 + /*
17661 + * Determine how many receive buffers we're lacking
17662 + * from the full complement, allocate, initialize,
17663 + * and post them, then update the chip rx lastdscr.
17664 + */
17665 +
17666 + rxin = di->rxin;
17667 + rxout = di->rxout;
17668 + rxbufsize = di->rxbufsize;
17669 +
17670 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
17671 +
17672 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
17673 +
17674 + for (i = 0; i < n; i++) {
17675 + if ((p = PKTGET(di->osh, rxbufsize, FALSE)) == NULL) {
17676 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
17677 + di->hnddma.rxnobuf++;
17678 + break;
17679 + }
17680 +
17681 + /* Do a cached write instead of uncached write since DMA_MAP
17682 + * will flush the cache. */
17683 + *(uint32*)(PKTDATA(di->osh, p)) = 0;
17684 +
17685 + pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->osh, p), rxbufsize, DMA_RX, p);
17686 + ASSERT(ISALIGNED(pa, 4));
17687 +
17688 + /* save the free packet pointer */
17689 + ASSERT(di->rxp[rxout] == NULL);
17690 + di->rxp[rxout] = p;
17691 +
17692 + if (DMA64_ENAB(di)) {
17693 + /* prep the descriptor control value */
17694 + if (rxout == (di->nrxd - 1))
17695 + ctrl = CTRL_EOT;
17696 +
17697 + dma64_dd_upd(di, di->rxd64, pa, rxout, &ctrl, rxbufsize);
17698 + } else {
17699 + /* prep the descriptor control value */
17700 + ctrl = rxbufsize;
17701 + if (rxout == (di->nrxd - 1))
17702 + ctrl |= CTRL_EOT;
17703 + dma32_dd_upd(di, di->rxd32, pa, rxout, &ctrl);
17704 + }
17705 +
17706 + rxout = NEXTRXD(rxout);
17707 + }
17708 +
17709 + di->rxout = rxout;
17710 +
17711 + /* update the chip lastdscr pointer */
17712 + if (DMA64_ENAB(di)) {
17713 + W_REG(&di->d64rxregs->ptr, I2B(rxout, dma64dd_t));
17714 + } else {
17715 + W_REG(&di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
17716 + }
17717 +}
17718 +
17719 +void
17720 +dma_txreclaim(dma_info_t *di, bool forceall)
17721 +{
17722 + void *p;
17723 +
17724 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
17725 +
17726 + while ((p = dma_getnexttxp(di, forceall)))
17727 + PKTFREE(di->osh, p, TRUE);
17728 +}
17729 +
17730 +/*
17731 + * Reclaim next completed txd (txds if using chained buffers) and
17732 + * return associated packet.
17733 + * If 'force' is true, reclaim txd(s) and return associated packet
17734 + * regardless of the value of the hardware "curr" pointer.
17735 + */
17736 +void*
17737 +dma_getnexttxp(dma_info_t *di, bool forceall)
17738 +{
17739 + if (DMA64_ENAB(di)) {
17740 + return dma64_getnexttxp(di, forceall);
17741 + } else {
17742 + return dma32_getnexttxp(di, forceall);
17743 + }
17744 +}
17745 +
17746 +/* like getnexttxp but no reclaim */
17747 +void*
17748 +dma_peeknexttxp(dma_info_t *di)
17749 +{
17750 + uint end, i;
17751 +
17752 + if (DMA64_ENAB(di)) {
17753 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
17754 + } else {
17755 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
17756 + }
17757 +
17758 + for (i = di->txin; i != end; i = NEXTTXD(i))
17759 + if (di->txp[i])
17760 + return (di->txp[i]);
17761 +
17762 + return (NULL);
17763 +}
17764 +
17765 +/*
17766 + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
17767 + */
17768 +void
17769 +dma_txrotate(di_t *di)
17770 +{
17771 + if (DMA64_ENAB(di)) {
17772 + dma64_txrotate(di);
17773 + } else {
17774 + dma32_txrotate(di);
17775 + }
17776 +}
17777 +
17778 +void
17779 +dma_rxreclaim(dma_info_t *di)
17780 +{
17781 + void *p;
17782 +
17783 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
17784 +
17785 + while ((p = dma_getnextrxp(di, TRUE)))
17786 + PKTFREE(di->osh, p, FALSE);
17787 +}
17788 +
17789 +void *
17790 +dma_getnextrxp(dma_info_t *di, bool forceall)
17791 +{
17792 + if (DMA64_ENAB(di)) {
17793 + return dma64_getnextrxp(di, forceall);
17794 + } else {
17795 + return dma32_getnextrxp(di, forceall);
17796 + }
17797 +}
17798 +
17799 +uintptr
17800 +dma_getvar(dma_info_t *di, char *name)
17801 +{
17802 + if (!strcmp(name, "&txavail"))
17803 + return ((uintptr) &di->txavail);
17804 + else {
17805 + ASSERT(0);
17806 + }
17807 + return (0);
17808 +}
17809 +
17810 +void
17811 +dma_txblock(dma_info_t *di)
17812 +{
17813 + di->txavail = 0;
17814 +}
17815 +
17816 +void
17817 +dma_txunblock(dma_info_t *di)
17818 +{
17819 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17820 +}
17821 +
17822 +uint
17823 +dma_txactive(dma_info_t *di)
17824 +{
17825 + return (NTXDACTIVE(di->txin, di->txout));
17826 +}
17827 +
17828 +void
17829 +dma_rxpiomode(dma32regs_t *regs)
17830 +{
17831 + W_REG(&regs->control, RC_FM);
17832 +}
17833 +
17834 +void
17835 +dma_txpioloopback(dma32regs_t *regs)
17836 +{
17837 + OR_REG(&regs->control, XC_LE);
17838 +}
17839 +
17840 +
17841 +
17842 +
17843 +/*** 32 bits DMA non-inline functions ***/
17844 +static bool
17845 +dma32_alloc(dma_info_t *di, uint direction)
17846 +{
17847 + uint size;
17848 + uint ddlen;
17849 + void *va;
17850 +
17851 + ddlen = sizeof (dma32dd_t);
17852 +
17853 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
17854 +
17855 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, D32RINGALIGN))
17856 + size += D32RINGALIGN;
17857 +
17858 +
17859 + if (direction == DMA_TX) {
17860 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
17861 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
17862 + return FALSE;
17863 + }
17864 +
17865 + di->txd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
17866 + di->txdalign = (uint)((int8*)di->txd32 - (int8*)va);
17867 + di->txdpa += di->txdalign;
17868 + di->txdalloc = size;
17869 + ASSERT(ISALIGNED((uintptr)di->txd32, D32RINGALIGN));
17870 + } else {
17871 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
17872 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
17873 + return FALSE;
17874 + }
17875 + di->rxd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
17876 + di->rxdalign = (uint)((int8*)di->rxd32 - (int8*)va);
17877 + di->rxdpa += di->rxdalign;
17878 + di->rxdalloc = size;
17879 + ASSERT(ISALIGNED((uintptr)di->rxd32, D32RINGALIGN));
17880 + }
17881 +
17882 + return TRUE;
17883 +}
17884 +
17885 +static void
17886 +dma32_txreset(dma_info_t *di)
17887 +{
17888 + uint32 status;
17889 +
17890 + /* suspend tx DMA first */
17891 + W_REG(&di->d32txregs->control, XC_SE);
17892 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED &&
17893 + status != XS_XS_IDLE &&
17894 + status != XS_XS_STOPPED,
17895 + 10000);
17896 +
17897 + W_REG(&di->d32txregs->control, 0);
17898 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED,
17899 + 10000);
17900 +
17901 + if (status != XS_XS_DISABLED) {
17902 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
17903 + }
17904 +
17905 + /* wait for the last transaction to complete */
17906 + OSL_DELAY(300);
17907 +}
17908 +
17909 +static void
17910 +dma32_rxreset(dma_info_t *di)
17911 +{
17912 + uint32 status;
17913 +
17914 + W_REG(&di->d32rxregs->control, 0);
17915 + SPINWAIT((status = (R_REG(&di->d32rxregs->status) & RS_RS_MASK)) != RS_RS_DISABLED,
17916 + 10000);
17917 +
17918 + if (status != RS_RS_DISABLED) {
17919 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
17920 + }
17921 +}
17922 +
17923 +static bool
17924 +dma32_txsuspendedidle(dma_info_t *di)
17925 +{
17926 + if (!(R_REG(&di->d32txregs->control) & XC_SE))
17927 + return 0;
17928 +
17929 + if ((R_REG(&di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
17930 + return 0;
17931 +
17932 + OSL_DELAY(2);
17933 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_IDLE);
17934 +}
17935 +
17936 +/*
17937 + * supports full 32bit dma engine buffer addressing so
17938 + * dma buffers can cross 4 Kbyte page boundaries.
17939 + */
17940 +static int
17941 +dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags)
17942 +{
17943 + void *p, *next;
17944 + uchar *data;
17945 + uint len;
17946 + uint txout;
17947 + uint32 ctrl;
17948 + uint32 pa;
17949 +
17950 + DMA_TRACE(("%s: dma_txfast\n", di->name));
17951 +
17952 + txout = di->txout;
17953 + ctrl = 0;
17954 +
17955 + /*
17956 + * Walk the chain of packet buffers
17957 + * allocating and initializing transmit descriptor entries.
17958 + */
17959 + for (p = p0; p; p = next) {
17960 + data = PKTDATA(di->osh, p);
17961 + len = PKTLEN(di->osh, p);
17962 + next = PKTNEXT(di->osh, p);
17963 +
17964 + /* return nonzero if out of tx descriptors */
17965 + if (NEXTTXD(txout) == di->txin)
17966 + goto outoftxd;
17967 +
17968 + if (len == 0)
17969 + continue;
17970 +
17971 + /* get physical address of buffer start */
17972 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
17973 +
17974 + /* build the descriptor control value */
17975 + ctrl = len & CTRL_BC_MASK;
17976 +
17977 + ctrl |= coreflags;
17978 +
17979 + if (p == p0)
17980 + ctrl |= CTRL_SOF;
17981 + if (next == NULL)
17982 + ctrl |= (CTRL_IOC | CTRL_EOF);
17983 + if (txout == (di->ntxd - 1))
17984 + ctrl |= CTRL_EOT;
17985 +
17986 + if (DMA64_ENAB(di)) {
17987 + dma64_dd_upd(di, di->txd64, pa, txout, &ctrl, len);
17988 + } else {
17989 + dma32_dd_upd(di, di->txd32, pa, txout, &ctrl);
17990 + }
17991 +
17992 + ASSERT(di->txp[txout] == NULL);
17993 +
17994 + txout = NEXTTXD(txout);
17995 + }
17996 +
17997 + /* if last txd eof not set, fix it */
17998 + if (!(ctrl & CTRL_EOF))
17999 + W_SM(&di->txd32[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
18000 +
18001 + /* save the packet */
18002 + di->txp[PREVTXD(txout)] = p0;
18003 +
18004 + /* bump the tx descriptor index */
18005 + di->txout = txout;
18006 +
18007 + /* kick the chip */
18008 + if (DMA64_ENAB(di)) {
18009 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
18010 + } else {
18011 + W_REG(&di->d32txregs->ptr, I2B(txout, dma32dd_t));
18012 + }
18013 +
18014 + /* tx flow control */
18015 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18016 +
18017 + return (0);
18018 +
18019 + outoftxd:
18020 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
18021 + PKTFREE(di->osh, p0, TRUE);
18022 + di->txavail = 0;
18023 + di->hnddma.txnobuf++;
18024 + return (-1);
18025 +}
18026 +
18027 +static void*
18028 +dma32_getnexttxp(dma_info_t *di, bool forceall)
18029 +{
18030 + uint start, end, i;
18031 + void *txp;
18032 +
18033 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
18034 +
18035 + txp = NULL;
18036 +
18037 + start = di->txin;
18038 + if (forceall)
18039 + end = di->txout;
18040 + else
18041 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
18042 +
18043 + if ((start == 0) && (end > di->txout))
18044 + goto bogus;
18045 +
18046 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
18047 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd32[i].addr)) - di->dataoffsetlow),
18048 + (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
18049 +
18050 + W_SM(&di->txd32[i].addr, 0xdeadbeef);
18051 + txp = di->txp[i];
18052 + di->txp[i] = NULL;
18053 + }
18054 +
18055 + di->txin = i;
18056 +
18057 + /* tx flow control */
18058 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18059 +
18060 + return (txp);
18061 +
18062 +bogus:
18063 +/*
18064 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
18065 + start, end, di->txout, forceall));
18066 +*/
18067 + return (NULL);
18068 +}
18069 +
18070 +static void *
18071 +dma32_getnextrxp(dma_info_t *di, bool forceall)
18072 +{
18073 + uint i;
18074 + void *rxp;
18075 +
18076 + /* if forcing, dma engine must be disabled */
18077 + ASSERT(!forceall || !dma_rxenabled(di));
18078 +
18079 + i = di->rxin;
18080 +
18081 + /* return if no packets posted */
18082 + if (i == di->rxout)
18083 + return (NULL);
18084 +
18085 + /* ignore curr if forceall */
18086 + if (!forceall && (i == B2I(R_REG(&di->d32rxregs->status) & RS_CD_MASK, dma32dd_t)))
18087 + return (NULL);
18088 +
18089 + /* get the packet pointer that corresponds to the rx descriptor */
18090 + rxp = di->rxp[i];
18091 + ASSERT(rxp);
18092 + di->rxp[i] = NULL;
18093 +
18094 + /* clear this packet from the descriptor ring */
18095 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) - di->dataoffsetlow),
18096 + di->rxbufsize, DMA_RX, rxp);
18097 + W_SM(&di->rxd32[i].addr, 0xdeadbeef);
18098 +
18099 + di->rxin = NEXTRXD(i);
18100 +
18101 + return (rxp);
18102 +}
18103 +
18104 +static void
18105 +dma32_txrotate(di_t *di)
18106 +{
18107 + uint ad;
18108 + uint nactive;
18109 + uint rot;
18110 + uint old, new;
18111 + uint32 w;
18112 + uint first, last;
18113 +
18114 + ASSERT(dma_txsuspendedidle(di));
18115 +
18116 + nactive = dma_txactive(di);
18117 + ad = B2I(((R_REG(&di->d32txregs->status) & XS_AD_MASK) >> XS_AD_SHIFT), dma32dd_t);
18118 + rot = TXD(ad - di->txin);
18119 +
18120 + ASSERT(rot < di->ntxd);
18121 +
18122 + /* full-ring case is a lot harder - don't worry about this */
18123 + if (rot >= (di->ntxd - nactive)) {
18124 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
18125 + return;
18126 + }
18127 +
18128 + first = di->txin;
18129 + last = PREVTXD(di->txout);
18130 +
18131 + /* move entries starting at last and moving backwards to first */
18132 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
18133 + new = TXD(old + rot);
18134 +
18135 + /*
18136 + * Move the tx dma descriptor.
18137 + * EOT is set only in the last entry in the ring.
18138 + */
18139 + w = R_SM(&di->txd32[old].ctrl) & ~CTRL_EOT;
18140 + if (new == (di->ntxd - 1))
18141 + w |= CTRL_EOT;
18142 + W_SM(&di->txd32[new].ctrl, w);
18143 + W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
18144 +
18145 + /* zap the old tx dma descriptor address field */
18146 + W_SM(&di->txd32[old].addr, 0xdeadbeef);
18147 +
18148 + /* move the corresponding txp[] entry */
18149 + ASSERT(di->txp[new] == NULL);
18150 + di->txp[new] = di->txp[old];
18151 + di->txp[old] = NULL;
18152 + }
18153 +
18154 + /* update txin and txout */
18155 + di->txin = ad;
18156 + di->txout = TXD(di->txout + rot);
18157 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18158 +
18159 + /* kick the chip */
18160 + W_REG(&di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
18161 +}
18162 +
18163 +/*** 64 bits DMA non-inline functions ***/
18164 +
18165 +#ifdef BCMDMA64
18166 +
18167 +static bool
18168 +dma64_alloc(dma_info_t *di, uint direction)
18169 +{
18170 + uint size;
18171 + uint ddlen;
18172 + uint32 alignbytes;
18173 + void *va;
18174 +
18175 + ddlen = sizeof (dma64dd_t);
18176 +
18177 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
18178 +
18179 + alignbytes = di->dma64align;
18180 +
18181 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, alignbytes))
18182 + size += alignbytes;
18183 +
18184 +
18185 + if (direction == DMA_TX) {
18186 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
18187 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
18188 + return FALSE;
18189 + }
18190 +
18191 + di->txd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
18192 + di->txdalign = (uint)((int8*)di->txd64 - (int8*)va);
18193 + di->txdpa += di->txdalign;
18194 + di->txdalloc = size;
18195 + ASSERT(ISALIGNED((uintptr)di->txd64, alignbytes));
18196 + } else {
18197 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
18198 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
18199 + return FALSE;
18200 + }
18201 + di->rxd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
18202 + di->rxdalign = (uint)((int8*)di->rxd64 - (int8*)va);
18203 + di->rxdpa += di->rxdalign;
18204 + di->rxdalloc = size;
18205 + ASSERT(ISALIGNED((uintptr)di->rxd64, alignbytes));
18206 + }
18207 +
18208 + return TRUE;
18209 +}
18210 +
18211 +static void
18212 +dma64_txreset(dma_info_t *di)
18213 +{
18214 + uint32 status;
18215 +
18216 + /* suspend tx DMA first */
18217 + W_REG(&di->d64txregs->control, D64_XC_SE);
18218 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED &&
18219 + status != D64_XS0_XS_IDLE &&
18220 + status != D64_XS0_XS_STOPPED,
18221 + 10000);
18222 +
18223 + W_REG(&di->d64txregs->control, 0);
18224 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED,
18225 + 10000);
18226 +
18227 + if (status != D64_XS0_XS_DISABLED) {
18228 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
18229 + }
18230 +
18231 + /* wait for the last transaction to complete */
18232 + OSL_DELAY(300);
18233 +}
18234 +
18235 +static void
18236 +dma64_rxreset(dma_info_t *di)
18237 +{
18238 + uint32 status;
18239 +
18240 + W_REG(&di->d64rxregs->control, 0);
18241 + SPINWAIT((status = (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED,
18242 + 10000);
18243 +
18244 + if (status != D64_RS0_RS_DISABLED) {
18245 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
18246 + }
18247 +}
18248 +
18249 +static bool
18250 +dma64_txsuspendedidle(dma_info_t *di)
18251 +{
18252 +
18253 + if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
18254 + return 0;
18255 +
18256 + if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_IDLE)
18257 + return 1;
18258 +
18259 + return 0;
18260 +}
18261 +
18262 +/*
18263 + * supports full 32bit dma engine buffer addressing so
18264 + * dma buffers can cross 4 Kbyte page boundaries.
18265 + */
18266 +static int
18267 +dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags)
18268 +{
18269 + void *p, *next;
18270 + uchar *data;
18271 + uint len;
18272 + uint txout;
18273 + uint32 flags;
18274 + uint32 pa;
18275 +
18276 + DMA_TRACE(("%s: dma_txfast\n", di->name));
18277 +
18278 + txout = di->txout;
18279 + flags = 0;
18280 +
18281 + /*
18282 + * Walk the chain of packet buffers
18283 + * allocating and initializing transmit descriptor entries.
18284 + */
18285 + for (p = p0; p; p = next) {
18286 + data = PKTDATA(di->osh, p);
18287 + len = PKTLEN(di->osh, p);
18288 + next = PKTNEXT(di->osh, p);
18289 +
18290 + /* return nonzero if out of tx descriptors */
18291 + if (NEXTTXD(txout) == di->txin)
18292 + goto outoftxd;
18293 +
18294 + if (len == 0)
18295 + continue;
18296 +
18297 + /* get physical address of buffer start */
18298 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
18299 +
18300 + flags = coreflags;
18301 +
18302 + if (p == p0)
18303 + flags |= D64_CTRL1_SOF;
18304 + if (next == NULL)
18305 + flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
18306 + if (txout == (di->ntxd - 1))
18307 + flags |= D64_CTRL1_EOT;
18308 +
18309 + dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
18310 +
18311 + ASSERT(di->txp[txout] == NULL);
18312 +
18313 + txout = NEXTTXD(txout);
18314 + }
18315 +
18316 + /* if last txd eof not set, fix it */
18317 + if (!(flags & D64_CTRL1_EOF))
18318 + W_SM(&di->txd64[PREVTXD(txout)].ctrl1, BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
18319 +
18320 + /* save the packet */
18321 + di->txp[PREVTXD(txout)] = p0;
18322 +
18323 + /* bump the tx descriptor index */
18324 + di->txout = txout;
18325 +
18326 + /* kick the chip */
18327 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
18328 +
18329 + /* tx flow control */
18330 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18331 +
18332 + return (0);
18333 +
18334 +outoftxd:
18335 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
18336 + PKTFREE(di->osh, p0, TRUE);
18337 + di->txavail = 0;
18338 + di->hnddma.txnobuf++;
18339 + return (-1);
18340 +}
18341 +
18342 +static void*
18343 +dma64_getnexttxp(dma_info_t *di, bool forceall)
18344 +{
18345 + uint start, end, i;
18346 + void *txp;
18347 +
18348 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
18349 +
18350 + txp = NULL;
18351 +
18352 + start = di->txin;
18353 + if (forceall)
18354 + end = di->txout;
18355 + else
18356 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
18357 +
18358 + if ((start == 0) && (end > di->txout))
18359 + goto bogus;
18360 +
18361 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
18362 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) - di->dataoffsetlow),
18363 + (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) & D64_CTRL2_BC_MASK), DMA_TX, di->txp[i]);
18364 +
18365 + W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
18366 + W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
18367 +
18368 + txp = di->txp[i];
18369 + di->txp[i] = NULL;
18370 + }
18371 +
18372 + di->txin = i;
18373 +
18374 + /* tx flow control */
18375 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18376 +
18377 + return (txp);
18378 +
18379 +bogus:
18380 +/*
18381 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
18382 + start, end, di->txout, forceall));
18383 +*/
18384 + return (NULL);
18385 +}
18386 +
18387 +static void *
18388 +dma64_getnextrxp(dma_info_t *di, bool forceall)
18389 +{
18390 + uint i;
18391 + void *rxp;
18392 +
18393 + /* if forcing, dma engine must be disabled */
18394 + ASSERT(!forceall || !dma_rxenabled(di));
18395 +
18396 + i = di->rxin;
18397 +
18398 + /* return if no packets posted */
18399 + if (i == di->rxout)
18400 + return (NULL);
18401 +
18402 + /* ignore curr if forceall */
18403 + if (!forceall && (i == B2I(R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK, dma64dd_t)))
18404 + return (NULL);
18405 +
18406 + /* get the packet pointer that corresponds to the rx descriptor */
18407 + rxp = di->rxp[i];
18408 + ASSERT(rxp);
18409 + di->rxp[i] = NULL;
18410 +
18411 + /* clear this packet from the descriptor ring */
18412 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) - di->dataoffsetlow),
18413 + di->rxbufsize, DMA_RX, rxp);
18414 +
18415 + W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
18416 + W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
18417 +
18418 + di->rxin = NEXTRXD(i);
18419 +
18420 + return (rxp);
18421 +}
18422 +
18423 +static void
18424 +dma64_txrotate(di_t *di)
18425 +{
18426 + uint ad;
18427 + uint nactive;
18428 + uint rot;
18429 + uint old, new;
18430 + uint32 w;
18431 + uint first, last;
18432 +
18433 + ASSERT(dma_txsuspendedidle(di));
18434 +
18435 + nactive = dma_txactive(di);
18436 + ad = B2I((R_REG(&di->d64txregs->status1) & D64_XS1_AD_MASK), dma64dd_t);
18437 + rot = TXD(ad - di->txin);
18438 +
18439 + ASSERT(rot < di->ntxd);
18440 +
18441 + /* full-ring case is a lot harder - don't worry about this */
18442 + if (rot >= (di->ntxd - nactive)) {
18443 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
18444 + return;
18445 + }
18446 +
18447 + first = di->txin;
18448 + last = PREVTXD(di->txout);
18449 +
18450 + /* move entries starting at last and moving backwards to first */
18451 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
18452 + new = TXD(old + rot);
18453 +
18454 + /*
18455 + * Move the tx dma descriptor.
18456 + * EOT is set only in the last entry in the ring.
18457 + */
18458 + w = R_SM(&di->txd64[old].ctrl1) & ~D64_CTRL1_EOT;
18459 + if (new == (di->ntxd - 1))
18460 + w |= D64_CTRL1_EOT;
18461 + W_SM(&di->txd64[new].ctrl1, w);
18462 +
18463 + w = R_SM(&di->txd64[old].ctrl2);
18464 + W_SM(&di->txd64[new].ctrl2, w);
18465 +
18466 + W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
18467 + W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
18468 +
18469 + /* zap the old tx dma descriptor address field */
18470 + W_SM(&di->txd64[old].addrlow, 0xdeadbeef);
18471 + W_SM(&di->txd64[old].addrhigh, 0xdeadbeef);
18472 +
18473 + /* move the corresponding txp[] entry */
18474 + ASSERT(di->txp[new] == NULL);
18475 + di->txp[new] = di->txp[old];
18476 + di->txp[old] = NULL;
18477 + }
18478 +
18479 + /* update txin and txout */
18480 + di->txin = ad;
18481 + di->txout = TXD(di->txout + rot);
18482 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18483 +
18484 + /* kick the chip */
18485 + W_REG(&di->d64txregs->ptr, I2B(di->txout, dma64dd_t));
18486 +}
18487 +
18488 +#endif
18489 +
18490 diff -urN linux.old/drivers/net/hnd/linux_osl.c linux.dev/drivers/net/hnd/linux_osl.c
18491 --- linux.old/drivers/net/hnd/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
18492 +++ linux.dev/drivers/net/hnd/linux_osl.c 2005-11-07 23:38:26.782893500 +0100
18493 @@ -0,0 +1,708 @@
18494 +/*
18495 + * Linux OS Independent Layer
18496 + *
18497 + * Copyright 2005, Broadcom Corporation
18498 + * All Rights Reserved.
18499 + *
18500 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18501 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18502 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18503 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18504 + *
18505 + * $Id$
18506 + */
18507 +
18508 +#define LINUX_OSL
18509 +
18510 +#include <typedefs.h>
18511 +#include <bcmendian.h>
18512 +#include <linux/module.h>
18513 +#include <linuxver.h>
18514 +#include <osl.h>
18515 +#include <bcmutils.h>
18516 +#include <linux/delay.h>
18517 +#ifdef mips
18518 +#include <asm/paccess.h>
18519 +#endif
18520 +#include <pcicfg.h>
18521 +
18522 +#define PCI_CFG_RETRY 10
18523 +
18524 +#define OS_HANDLE_MAGIC 0x1234abcd
18525 +#define BCM_MEM_FILENAME_LEN 24
18526 +
18527 +typedef struct bcm_mem_link {
18528 + struct bcm_mem_link *prev;
18529 + struct bcm_mem_link *next;
18530 + uint size;
18531 + int line;
18532 + char file[BCM_MEM_FILENAME_LEN];
18533 +} bcm_mem_link_t;
18534 +
18535 +struct os_handle {
18536 + uint magic;
18537 + void *pdev;
18538 + uint malloced;
18539 + uint failed;
18540 + bcm_mem_link_t *dbgmem_list;
18541 +};
18542 +
18543 +static int16 linuxbcmerrormap[] = \
18544 +{ 0, /* 0 */
18545 + -EINVAL, /* BCME_ERROR */
18546 + -EINVAL, /* BCME_BADARG*/
18547 + -EINVAL, /* BCME_BADOPTION*/
18548 + -EINVAL, /* BCME_NOTUP */
18549 + -EINVAL, /* BCME_NOTDOWN */
18550 + -EINVAL, /* BCME_NOTAP */
18551 + -EINVAL, /* BCME_NOTSTA */
18552 + -EINVAL, /* BCME_BADKEYIDX */
18553 + -EINVAL, /* BCME_RADIOOFF */
18554 + -EINVAL, /* BCME_NOTBANDLOCKED */
18555 + -EINVAL, /* BCME_NOCLK */
18556 + -EINVAL, /* BCME_BADRATESET */
18557 + -EINVAL, /* BCME_BADBAND */
18558 + -E2BIG, /* BCME_BUFTOOSHORT */
18559 + -E2BIG, /* BCME_BUFTOOLONG */
18560 + -EBUSY, /* BCME_BUSY */
18561 + -EINVAL, /* BCME_NOTASSOCIATED */
18562 + -EINVAL, /* BCME_BADSSIDLEN */
18563 + -EINVAL, /* BCME_OUTOFRANGECHAN */
18564 + -EINVAL, /* BCME_BADCHAN */
18565 + -EFAULT, /* BCME_BADADDR */
18566 + -ENOMEM, /* BCME_NORESOURCE */
18567 + -EOPNOTSUPP, /* BCME_UNSUPPORTED */
18568 + -EMSGSIZE, /* BCME_BADLENGTH */
18569 + -EINVAL, /* BCME_NOTREADY */
18570 + -EPERM, /* BCME_NOTPERMITTED */
18571 + -ENOMEM, /* BCME_NOMEM */
18572 + -EINVAL, /* BCME_ASSOCIATED */
18573 + -ERANGE, /* BCME_RANGE */
18574 + -EINVAL /* BCME_NOTFOUND */
18575 +};
18576 +
18577 +/* translate bcmerrors into linux errors*/
18578 +int
18579 +osl_error(int bcmerror)
18580 +{
18581 + int abs_bcmerror;
18582 + int array_size = ARRAYSIZE(linuxbcmerrormap);
18583 +
18584 + abs_bcmerror = ABS(bcmerror);
18585 +
18586 + if (bcmerror > 0)
18587 + abs_bcmerror = 0;
18588 +
18589 + else if (abs_bcmerror >= array_size)
18590 + abs_bcmerror = BCME_ERROR;
18591 +
18592 + return linuxbcmerrormap[abs_bcmerror];
18593 +}
18594 +
18595 +osl_t *
18596 +osl_attach(void *pdev)
18597 +{
18598 + osl_t *osh;
18599 +
18600 + osh = kmalloc(sizeof(osl_t), GFP_ATOMIC);
18601 + ASSERT(osh);
18602 +
18603 + /*
18604 + * check the cases where
18605 + * 1.Error code Added to bcmerror table, but forgot to add it to the OS
18606 + * dependent error code
18607 + * 2. Error code is added to the bcmerror table, but forgot to add the
18608 + * corresponding errorstring(dummy call to bcmerrorstr)
18609 + */
18610 + bcmerrorstr(0);
18611 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
18612 +
18613 + osh->magic = OS_HANDLE_MAGIC;
18614 + osh->malloced = 0;
18615 + osh->failed = 0;
18616 + osh->dbgmem_list = NULL;
18617 + osh->pdev = pdev;
18618 +
18619 + return osh;
18620 +}
18621 +
18622 +void
18623 +osl_detach(osl_t *osh)
18624 +{
18625 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC));
18626 + kfree(osh);
18627 +}
18628 +
18629 +void*
18630 +osl_pktget(osl_t *osh, uint len, bool send)
18631 +{
18632 + struct sk_buff *skb;
18633 +
18634 + if ((skb = dev_alloc_skb(len)) == NULL)
18635 + return (NULL);
18636 +
18637 + skb_put(skb, len);
18638 +
18639 + /* ensure the cookie field is cleared */
18640 + PKTSETCOOKIE(skb, NULL);
18641 +
18642 + return ((void*) skb);
18643 +}
18644 +
18645 +void
18646 +osl_pktfree(void *p)
18647 +{
18648 + struct sk_buff *skb, *nskb;
18649 +
18650 + skb = (struct sk_buff*) p;
18651 +
18652 + /* perversion: we use skb->next to chain multi-skb packets */
18653 + while (skb) {
18654 + nskb = skb->next;
18655 + skb->next = NULL;
18656 + if (skb->destructor) {
18657 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
18658 + dev_kfree_skb_any(skb);
18659 + } else {
18660 + /* can free immediately (even in_irq()) if destructor does not exist */
18661 + dev_kfree_skb(skb);
18662 + }
18663 + skb = nskb;
18664 + }
18665 +}
18666 +
18667 +uint32
18668 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
18669 +{
18670 + uint val;
18671 + uint retry=PCI_CFG_RETRY;
18672 +
18673 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18674 +
18675 + /* only 4byte access supported */
18676 + ASSERT(size == 4);
18677 +
18678 + do {
18679 + pci_read_config_dword(osh->pdev, offset, &val);
18680 + if (val != 0xffffffff)
18681 + break;
18682 + } while (retry--);
18683 +
18684 +
18685 + return (val);
18686 +}
18687 +
18688 +void
18689 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
18690 +{
18691 + uint retry=PCI_CFG_RETRY;
18692 +
18693 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18694 +
18695 + /* only 4byte access supported */
18696 + ASSERT(size == 4);
18697 +
18698 + do {
18699 + pci_write_config_dword(osh->pdev, offset, val);
18700 + if (offset!=PCI_BAR0_WIN)
18701 + break;
18702 + if (osl_pci_read_config(osh,offset,size) == val)
18703 + break;
18704 + } while (retry--);
18705 +
18706 +}
18707 +
18708 +/* return bus # for the pci device pointed by osh->pdev */
18709 +uint
18710 +osl_pci_bus(osl_t *osh)
18711 +{
18712 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
18713 +
18714 + return ((struct pci_dev *)osh->pdev)->bus->number;
18715 +}
18716 +
18717 +/* return slot # for the pci device pointed by osh->pdev */
18718 +uint
18719 +osl_pci_slot(osl_t *osh)
18720 +{
18721 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
18722 +
18723 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
18724 +}
18725 +
18726 +static void
18727 +osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
18728 +{
18729 +}
18730 +
18731 +void
18732 +osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
18733 +{
18734 + osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
18735 +}
18736 +
18737 +void
18738 +osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
18739 +{
18740 + osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
18741 +}
18742 +
18743 +
18744 +#ifdef BCMDBG_MEM
18745 +
18746 +void*
18747 +osl_debug_malloc(osl_t *osh, uint size, int line, char* file)
18748 +{
18749 + bcm_mem_link_t *p;
18750 + char* basename;
18751 +
18752 + ASSERT(size);
18753 +
18754 + if ((p = (bcm_mem_link_t*)osl_malloc(osh, sizeof(bcm_mem_link_t) + size)) == NULL)
18755 + return (NULL);
18756 +
18757 + p->size = size;
18758 + p->line = line;
18759 +
18760 + basename = strrchr(file, '/');
18761 + /* skip the '/' */
18762 + if (basename)
18763 + basename++;
18764 +
18765 + if (!basename)
18766 + basename = file;
18767 +
18768 + strncpy(p->file, basename, BCM_MEM_FILENAME_LEN);
18769 + p->file[BCM_MEM_FILENAME_LEN - 1] = '\0';
18770 +
18771 + /* link this block */
18772 + p->prev = NULL;
18773 + p->next = osh->dbgmem_list;
18774 + if (p->next)
18775 + p->next->prev = p;
18776 + osh->dbgmem_list = p;
18777 +
18778 + return p + 1;
18779 +}
18780 +
18781 +void
18782 +osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file)
18783 +{
18784 + bcm_mem_link_t *p = (bcm_mem_link_t *)((int8*)addr - sizeof(bcm_mem_link_t));
18785 +
18786 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18787 +
18788 + if (p->size == 0) {
18789 + printk("osl_debug_mfree: double free on addr 0x%x size %d at line %d file %s\n",
18790 + (uint)addr, size, line, file);
18791 + ASSERT(p->size);
18792 + return;
18793 + }
18794 +
18795 + if (p->size != size) {
18796 + printk("osl_debug_mfree: dealloc size %d does not match alloc size %d on addr 0x%x at line %d file %s\n",
18797 + size, p->size, (uint)addr, line, file);
18798 + ASSERT(p->size == size);
18799 + return;
18800 + }
18801 +
18802 + /* unlink this block */
18803 + if (p->prev)
18804 + p->prev->next = p->next;
18805 + if (p->next)
18806 + p->next->prev = p->prev;
18807 + if (osh->dbgmem_list == p)
18808 + osh->dbgmem_list = p->next;
18809 + p->next = p->prev = NULL;
18810 +
18811 + osl_mfree(osh, p, size + sizeof(bcm_mem_link_t));
18812 +}
18813 +
18814 +char*
18815 +osl_debug_memdump(osl_t *osh, char *buf, uint sz)
18816 +{
18817 + bcm_mem_link_t *p;
18818 + char *obuf;
18819 +
18820 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18821 + obuf = buf;
18822 +
18823 + buf += sprintf(buf, " Address\tSize\tFile:line\n");
18824 + for (p = osh->dbgmem_list; p && ((buf - obuf) < (sz - 128)); p = p->next)
18825 + buf += sprintf(buf, "0x%08x\t%5d\t%s:%d\n",
18826 + (int)p + sizeof(bcm_mem_link_t), p->size, p->file, p->line);
18827 +
18828 + return (obuf);
18829 +}
18830 +
18831 +#endif /* BCMDBG_MEM */
18832 +
18833 +void*
18834 +osl_malloc(osl_t *osh, uint size)
18835 +{
18836 + void *addr;
18837 +
18838 + /* only ASSERT if osh is defined */
18839 + if (osh)
18840 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18841 +
18842 + if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
18843 + if(osh)
18844 + osh->failed++;
18845 + return (NULL);
18846 + }
18847 + if (osh)
18848 + osh->malloced += size;
18849 +
18850 + return (addr);
18851 +}
18852 +
18853 +void
18854 +osl_mfree(osl_t *osh, void *addr, uint size)
18855 +{
18856 + if (osh) {
18857 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18858 + osh->malloced -= size;
18859 + }
18860 + kfree(addr);
18861 +}
18862 +
18863 +uint
18864 +osl_malloced(osl_t *osh)
18865 +{
18866 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18867 + return (osh->malloced);
18868 +}
18869 +
18870 +uint osl_malloc_failed(osl_t *osh)
18871 +{
18872 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18873 + return (osh->failed);
18874 +}
18875 +
18876 +void*
18877 +osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
18878 +{
18879 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18880 +
18881 + return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
18882 +}
18883 +
18884 +void
18885 +osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
18886 +{
18887 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18888 +
18889 + pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
18890 +}
18891 +
18892 +uint
18893 +osl_dma_map(osl_t *osh, void *va, uint size, int direction)
18894 +{
18895 + int dir;
18896 +
18897 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18898 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
18899 + return (pci_map_single(osh->pdev, va, size, dir));
18900 +}
18901 +
18902 +void
18903 +osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
18904 +{
18905 + int dir;
18906 +
18907 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18908 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
18909 + pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
18910 +}
18911 +
18912 +#if defined(BINOSL)
18913 +void
18914 +osl_assert(char *exp, char *file, int line)
18915 +{
18916 + char tempbuf[255];
18917 +
18918 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
18919 + panic(tempbuf);
18920 +}
18921 +#endif /* BCMDBG || BINOSL */
18922 +
18923 +void
18924 +osl_delay(uint usec)
18925 +{
18926 + uint d;
18927 +
18928 + while (usec > 0) {
18929 + d = MIN(usec, 1000);
18930 + udelay(d);
18931 + usec -= d;
18932 + }
18933 +}
18934 +
18935 +/*
18936 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
18937 + */
18938 +#ifdef BINOSL
18939 +
18940 +int
18941 +osl_printf(const char *format, ...)
18942 +{
18943 + va_list args;
18944 + char buf[1024];
18945 + int len;
18946 +
18947 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
18948 + va_start(args, format);
18949 + len = vsprintf(buf, format, args);
18950 + va_end(args);
18951 +
18952 + if (len > sizeof (buf)) {
18953 + printk("osl_printf: buffer overrun\n");
18954 + return (0);
18955 + }
18956 +
18957 + return (printk(buf));
18958 +}
18959 +
18960 +int
18961 +osl_sprintf(char *buf, const char *format, ...)
18962 +{
18963 + va_list args;
18964 + int rc;
18965 +
18966 + va_start(args, format);
18967 + rc = vsprintf(buf, format, args);
18968 + va_end(args);
18969 + return (rc);
18970 +}
18971 +
18972 +int
18973 +osl_strcmp(const char *s1, const char *s2)
18974 +{
18975 + return (strcmp(s1, s2));
18976 +}
18977 +
18978 +int
18979 +osl_strncmp(const char *s1, const char *s2, uint n)
18980 +{
18981 + return (strncmp(s1, s2, n));
18982 +}
18983 +
18984 +int
18985 +osl_strlen(const char *s)
18986 +{
18987 + return (strlen(s));
18988 +}
18989 +
18990 +char*
18991 +osl_strcpy(char *d, const char *s)
18992 +{
18993 + return (strcpy(d, s));
18994 +}
18995 +
18996 +char*
18997 +osl_strncpy(char *d, const char *s, uint n)
18998 +{
18999 + return (strncpy(d, s, n));
19000 +}
19001 +
19002 +void
19003 +bcopy(const void *src, void *dst, int len)
19004 +{
19005 + memcpy(dst, src, len);
19006 +}
19007 +
19008 +int
19009 +bcmp(const void *b1, const void *b2, int len)
19010 +{
19011 + return (memcmp(b1, b2, len));
19012 +}
19013 +
19014 +void
19015 +bzero(void *b, int len)
19016 +{
19017 + memset(b, '\0', len);
19018 +}
19019 +
19020 +uint32
19021 +osl_readl(volatile uint32 *r)
19022 +{
19023 + return (readl(r));
19024 +}
19025 +
19026 +uint16
19027 +osl_readw(volatile uint16 *r)
19028 +{
19029 + return (readw(r));
19030 +}
19031 +
19032 +uint8
19033 +osl_readb(volatile uint8 *r)
19034 +{
19035 + return (readb(r));
19036 +}
19037 +
19038 +void
19039 +osl_writel(uint32 v, volatile uint32 *r)
19040 +{
19041 + writel(v, r);
19042 +}
19043 +
19044 +void
19045 +osl_writew(uint16 v, volatile uint16 *r)
19046 +{
19047 + writew(v, r);
19048 +}
19049 +
19050 +void
19051 +osl_writeb(uint8 v, volatile uint8 *r)
19052 +{
19053 + writeb(v, r);
19054 +}
19055 +
19056 +void *
19057 +osl_uncached(void *va)
19058 +{
19059 +#ifdef mips
19060 + return ((void*)KSEG1ADDR(va));
19061 +#else
19062 + return ((void*)va);
19063 +#endif
19064 +}
19065 +
19066 +uint
19067 +osl_getcycles(void)
19068 +{
19069 + uint cycles;
19070 +
19071 +#if defined(mips)
19072 + cycles = read_c0_count() * 2;
19073 +#elif defined(__i386__)
19074 + rdtscl(cycles);
19075 +#else
19076 + cycles = 0;
19077 +#endif
19078 + return cycles;
19079 +}
19080 +
19081 +void *
19082 +osl_reg_map(uint32 pa, uint size)
19083 +{
19084 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
19085 +}
19086 +
19087 +void
19088 +osl_reg_unmap(void *va)
19089 +{
19090 + iounmap(va);
19091 +}
19092 +
19093 +int
19094 +osl_busprobe(uint32 *val, uint32 addr)
19095 +{
19096 +#ifdef mips
19097 + return get_dbe(*val, (uint32*)addr);
19098 +#else
19099 + *val = readl(addr);
19100 + return 0;
19101 +#endif
19102 +}
19103 +
19104 +uchar*
19105 +osl_pktdata(osl_t *osh, void *skb)
19106 +{
19107 + return (((struct sk_buff*)skb)->data);
19108 +}
19109 +
19110 +uint
19111 +osl_pktlen(osl_t *osh, void *skb)
19112 +{
19113 + return (((struct sk_buff*)skb)->len);
19114 +}
19115 +
19116 +uint
19117 +osl_pktheadroom(osl_t *osh, void *skb)
19118 +{
19119 + return (uint) skb_headroom((struct sk_buff *) skb);
19120 +}
19121 +
19122 +uint
19123 +osl_pkttailroom(osl_t *osh, void *skb)
19124 +{
19125 + return (uint) skb_tailroom((struct sk_buff *) skb);
19126 +}
19127 +
19128 +void*
19129 +osl_pktnext(osl_t *osh, void *skb)
19130 +{
19131 + return (((struct sk_buff*)skb)->next);
19132 +}
19133 +
19134 +void
19135 +osl_pktsetnext(void *skb, void *x)
19136 +{
19137 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
19138 +}
19139 +
19140 +void
19141 +osl_pktsetlen(osl_t *osh, void *skb, uint len)
19142 +{
19143 + __skb_trim((struct sk_buff*)skb, len);
19144 +}
19145 +
19146 +uchar*
19147 +osl_pktpush(osl_t *osh, void *skb, int bytes)
19148 +{
19149 + return (skb_push((struct sk_buff*)skb, bytes));
19150 +}
19151 +
19152 +uchar*
19153 +osl_pktpull(osl_t *osh, void *skb, int bytes)
19154 +{
19155 + return (skb_pull((struct sk_buff*)skb, bytes));
19156 +}
19157 +
19158 +void*
19159 +osl_pktdup(osl_t *osh, void *skb)
19160 +{
19161 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
19162 +}
19163 +
19164 +void*
19165 +osl_pktcookie(void *skb)
19166 +{
19167 + return ((void*)((struct sk_buff*)skb)->csum);
19168 +}
19169 +
19170 +void
19171 +osl_pktsetcookie(void *skb, void *x)
19172 +{
19173 + ((struct sk_buff*)skb)->csum = (uint)x;
19174 +}
19175 +
19176 +void*
19177 +osl_pktlink(void *skb)
19178 +{
19179 + return (((struct sk_buff*)skb)->prev);
19180 +}
19181 +
19182 +void
19183 +osl_pktsetlink(void *skb, void *x)
19184 +{
19185 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
19186 +}
19187 +
19188 +uint
19189 +osl_pktprio(void *skb)
19190 +{
19191 + return (((struct sk_buff*)skb)->priority);
19192 +}
19193 +
19194 +void
19195 +osl_pktsetprio(void *skb, uint x)
19196 +{
19197 + ((struct sk_buff*)skb)->priority = x;
19198 +}
19199 +
19200 +
19201 +#endif /* BINOSL */
19202 diff -urN linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.c
19203 --- linux.old/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
19204 +++ linux.dev/drivers/net/hnd/sbutils.c 2005-11-08 17:58:18.918914500 +0100
19205 @@ -0,0 +1,2837 @@
19206 +/*
19207 + * Misc utility routines for accessing chip-specific features
19208 + * of the SiliconBackplane-based Broadcom chips.
19209 + *
19210 + * Copyright 2005, Broadcom Corporation
19211 + * All Rights Reserved.
19212 + *
19213 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19214 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19215 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19216 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19217 + * $Id$
19218 + */
19219 +
19220 +#include <typedefs.h>
19221 +#include <osl.h>
19222 +#include <sbutils.h>
19223 +#include <bcmutils.h>
19224 +#include <bcmdevs.h>
19225 +#include <sbconfig.h>
19226 +#include <sbchipc.h>
19227 +#include <sbpci.h>
19228 +#include <sbpcie.h>
19229 +#include <pcicfg.h>
19230 +#include <sbpcmcia.h>
19231 +#include <sbextif.h>
19232 +#include <bcmsrom.h>
19233 +
19234 +/* debug/trace */
19235 +#define SB_ERROR(args)
19236 +
19237 +
19238 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
19239 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
19240 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
19241 +
19242 +/* misc sb info needed by some of the routines */
19243 +typedef struct sb_info {
19244 +
19245 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
19246 +
19247 + void *osh; /* osl os handle */
19248 + void *sdh; /* bcmsdh handle */
19249 +
19250 + void *curmap; /* current regs va */
19251 + void *regs[SB_MAXCORES]; /* other regs va */
19252 +
19253 + uint curidx; /* current core index */
19254 + uint dev_coreid; /* the core provides driver functions */
19255 +
19256 + bool memseg; /* flag to toggle MEM_SEG register */
19257 +
19258 + uint gpioidx; /* gpio control core index */
19259 + uint gpioid; /* gpio control coretype */
19260 +
19261 + uint numcores; /* # discovered cores */
19262 + uint coreid[SB_MAXCORES]; /* id of each core */
19263 +
19264 + void *intr_arg; /* interrupt callback function arg */
19265 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
19266 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
19267 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
19268 +
19269 +} sb_info_t;
19270 +
19271 +/* local prototypes */
19272 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
19273 + uint bustype, void *sdh, char **vars, int *varsz);
19274 +static void BCMINIT(sb_scan)(sb_info_t *si);
19275 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
19276 +static uint _sb_coreidx(sb_info_t *si);
19277 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
19278 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
19279 +static uint BCMINIT(sb_chip2numcores)(uint chip);
19280 +static bool sb_ispcie(sb_info_t *si);
19281 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
19282 +static int sb_pci_fixcfg(sb_info_t *si);
19283 +
19284 +/* routines to access mdio slave device registers */
19285 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
19286 +static void BCMINIT(sb_war30841)(sb_info_t *si);
19287 +
19288 +/* delay needed between the mdio control/ mdiodata register data access */
19289 +#define PR28829_DELAY() OSL_DELAY(10)
19290 +
19291 +
19292 +/* global variable to indicate reservation/release of gpio's*/
19293 +static uint32 sb_gpioreservation = 0;
19294 +
19295 +#define SB_INFO(sbh) (sb_info_t*)sbh
19296 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
19297 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
19298 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
19299 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
19300 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
19301 +#define BADIDX (SB_MAXCORES+1)
19302 +#define NOREV -1
19303 +
19304 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
19305 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
19306 +
19307 +/* sonicsrev */
19308 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
19309 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
19310 +
19311 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
19312 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
19313 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
19314 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
19315 +
19316 +/*
19317 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
19318 + * after core switching to avoid invalid register accesss inside ISR.
19319 + */
19320 +#define INTR_OFF(si, intr_val) \
19321 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
19322 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
19323 +#define INTR_RESTORE(si, intr_val) \
19324 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
19325 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
19326 +
19327 +/* dynamic clock control defines */
19328 +#define LPOMINFREQ 25000 /* low power oscillator min */
19329 +#define LPOMAXFREQ 43000 /* low power oscillator max */
19330 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
19331 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
19332 +#define PCIMINFREQ 25000000 /* 25 MHz */
19333 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
19334 +
19335 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
19336 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
19337 +
19338 +#define MIN_DUMPBUFLEN 32 /* debug */
19339 +
19340 +/* different register spaces to access thr'u pcie indirect access*/
19341 +#define PCIE_CONFIGREGS 1
19342 +#define PCIE_PCIEREGS 2
19343 +
19344 +/* GPIO Based LED powersave defines */
19345 +#define DEFAULT_GPIO_ONTIME 10
19346 +#define DEFAULT_GPIO_OFFTIME 90
19347 +
19348 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
19349 +
19350 +static uint32
19351 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
19352 +{
19353 + uint8 tmp;
19354 + uint32 val, intr_val = 0;
19355 +
19356 +
19357 + /*
19358 + * compact flash only has 11 bits address, while we needs 12 bits address.
19359 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
19360 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
19361 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
19362 + */
19363 + if(si->memseg) {
19364 + INTR_OFF(si, intr_val);
19365 + tmp = 1;
19366 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19367 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
19368 + }
19369 +
19370 + val = R_REG(sbr);
19371 +
19372 + if(si->memseg) {
19373 + tmp = 0;
19374 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19375 + INTR_RESTORE(si, intr_val);
19376 + }
19377 +
19378 + return (val);
19379 +}
19380 +
19381 +static void
19382 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
19383 +{
19384 + uint8 tmp;
19385 + volatile uint32 dummy;
19386 + uint32 intr_val = 0;
19387 +
19388 +
19389 + /*
19390 + * compact flash only has 11 bits address, while we needs 12 bits address.
19391 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
19392 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
19393 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
19394 + */
19395 + if(si->memseg) {
19396 + INTR_OFF(si, intr_val);
19397 + tmp = 1;
19398 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19399 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
19400 + }
19401 +
19402 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19403 +#ifdef IL_BIGENDIAN
19404 + dummy = R_REG(sbr);
19405 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
19406 + dummy = R_REG(sbr);
19407 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
19408 +#else
19409 + dummy = R_REG(sbr);
19410 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
19411 + dummy = R_REG(sbr);
19412 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
19413 +#endif
19414 + } else
19415 + W_REG(sbr, v);
19416 +
19417 + if(si->memseg) {
19418 + tmp = 0;
19419 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19420 + INTR_RESTORE(si, intr_val);
19421 + }
19422 +}
19423 +
19424 +/*
19425 + * Allocate a sb handle.
19426 + * devid - pci device id (used to determine chip#)
19427 + * osh - opaque OS handle
19428 + * regs - virtual address of initial core registers
19429 + * bustype - pci/pcmcia/sb/sdio/etc
19430 + * vars - pointer to a pointer area for "environment" variables
19431 + * varsz - pointer to int to return the size of the vars
19432 + */
19433 +sb_t *
19434 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
19435 + uint bustype, void *sdh, char **vars, int *varsz)
19436 +{
19437 + sb_info_t *si;
19438 +
19439 + /* alloc sb_info_t */
19440 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
19441 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
19442 + return (NULL);
19443 + }
19444 +
19445 + if (BCMINIT(sb_doattach)(si, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
19446 + MFREE(osh, si, sizeof (sb_info_t));
19447 + return (NULL);
19448 + }
19449 + return (sb_t *)si;
19450 +}
19451 +
19452 +/* Using sb_kattach depends on SB_BUS support, either implicit */
19453 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
19454 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
19455 +
19456 +/* global kernel resource */
19457 +static sb_info_t ksi;
19458 +
19459 +/* generic kernel variant of sb_attach() */
19460 +sb_t *
19461 +BCMINITFN(sb_kattach)()
19462 +{
19463 + uint32 *regs;
19464 +
19465 + if (ksi.curmap == NULL) {
19466 + uint32 cid;
19467 +
19468 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
19469 + cid = R_REG((uint32 *)regs);
19470 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
19471 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
19472 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
19473 + uint32 *scc, val;
19474 +
19475 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
19476 + val = R_REG(scc);
19477 + SB_ERROR((" initial scc = 0x%x\n", val));
19478 + val |= SCC_SS_XTAL;
19479 + W_REG(scc, val);
19480 + }
19481 +
19482 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
19483 + SB_BUS, NULL, NULL, NULL) == NULL) {
19484 + return NULL;
19485 + }
19486 + }
19487 +
19488 + return (sb_t *)&ksi;
19489 +}
19490 +#endif
19491 +
19492 +static sb_info_t *
19493 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
19494 + uint bustype, void *sdh, char **vars, int *varsz)
19495 +{
19496 + uint origidx;
19497 + chipcregs_t *cc;
19498 + sbconfig_t *sb;
19499 + uint32 w;
19500 +
19501 + ASSERT(GOODREGS(regs));
19502 +
19503 + bzero((uchar*)si, sizeof (sb_info_t));
19504 +
19505 + si->sb.buscoreidx = si->gpioidx = BADIDX;
19506 +
19507 + si->osh = osh;
19508 + si->curmap = regs;
19509 + si->sdh = sdh;
19510 +
19511 + /* check to see if we are a sb core mimic'ing a pci core */
19512 + if (bustype == PCI_BUS) {
19513 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
19514 + bustype = SB_BUS;
19515 + else
19516 + bustype = PCI_BUS;
19517 + }
19518 +
19519 + si->sb.bustype = bustype;
19520 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
19521 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
19522 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
19523 + return NULL;
19524 + }
19525 +
19526 + /* need to set memseg flag for CF card first before any sb registers access */
19527 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
19528 + si->memseg = TRUE;
19529 +
19530 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
19531 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
19532 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
19533 +
19534 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19535 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
19536 + if (!GOODCOREADDR(w))
19537 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
19538 + }
19539 +
19540 + /* initialize current core index value */
19541 + si->curidx = _sb_coreidx(si);
19542 +
19543 + if (si->curidx == BADIDX) {
19544 + SB_ERROR(("sb_doattach: bad core index\n"));
19545 + return NULL;
19546 + }
19547 +
19548 + /* get sonics backplane revision */
19549 + sb = REGS2SB(si->curmap);
19550 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
19551 +
19552 + /* keep and reuse the initial register mapping */
19553 + origidx = si->curidx;
19554 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
19555 + si->regs[origidx] = regs;
19556 +
19557 + /* is core-0 a chipcommon core? */
19558 + si->numcores = 1;
19559 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
19560 + if (sb_coreid(&si->sb) != SB_CC)
19561 + cc = NULL;
19562 +
19563 + /* determine chip id and rev */
19564 + if (cc) {
19565 + /* chip common core found! */
19566 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
19567 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
19568 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
19569 + } else {
19570 + /* The only pcmcia chip without a chipcommon core is a 4301 */
19571 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
19572 + devid = BCM4301_DEVICE_ID;
19573 +
19574 + /* no chip common core -- must convert device id to chip id */
19575 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
19576 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
19577 + sb_setcoreidx(&si->sb, origidx);
19578 + return NULL;
19579 + }
19580 + }
19581 +
19582 + /* get chipcommon rev */
19583 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
19584 +
19585 + /* determine numcores */
19586 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
19587 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
19588 + else
19589 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
19590 +
19591 + /* return to original core */
19592 + sb_setcoreidx(&si->sb, origidx);
19593 +
19594 + /* sanity checks */
19595 + ASSERT(si->sb.chip);
19596 +
19597 + /* scan for cores */
19598 + BCMINIT(sb_scan)(si);
19599 +
19600 + /* fixup necessary chip/core configurations */
19601 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19602 + if (sb_pci_fixcfg(si)) {
19603 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
19604 + return NULL;
19605 + }
19606 + }
19607 +
19608 + /* srom_var_init() depends on sb_scan() info */
19609 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
19610 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
19611 + return (NULL);
19612 + }
19613 +
19614 + if (cc == NULL) {
19615 + /*
19616 + * The chip revision number is hardwired into all
19617 + * of the pci function config rev fields and is
19618 + * independent from the individual core revision numbers.
19619 + * For example, the "A0" silicon of each chip is chip rev 0.
19620 + * For PCMCIA we get it from the CIS instead.
19621 + */
19622 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19623 + ASSERT(vars);
19624 + si->sb.chiprev = getintvar(*vars, "chiprev");
19625 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19626 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
19627 + si->sb.chiprev = w & 0xff;
19628 + } else
19629 + si->sb.chiprev = 0;
19630 + }
19631 +
19632 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19633 + w = getintvar(*vars, "regwindowsz");
19634 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
19635 + }
19636 +
19637 + /* gpio control core is required */
19638 + if (!GOODIDX(si->gpioidx)) {
19639 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
19640 + return NULL;
19641 + }
19642 +
19643 + /* get boardtype and boardrev */
19644 + switch (BUSTYPE(si->sb.bustype)) {
19645 + case PCI_BUS:
19646 + /* do a pci config read to get subsystem id and subvendor id */
19647 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
19648 + si->sb.boardvendor = w & 0xffff;
19649 + si->sb.boardtype = (w >> 16) & 0xffff;
19650 + break;
19651 +
19652 + case PCMCIA_BUS:
19653 + case SDIO_BUS:
19654 + si->sb.boardvendor = getintvar(*vars, "manfid");
19655 + si->sb.boardtype = getintvar(*vars, "prodid");
19656 + break;
19657 +
19658 + case SB_BUS:
19659 + case JTAG_BUS:
19660 + si->sb.boardvendor = VENDOR_BROADCOM;
19661 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
19662 + si->sb.boardtype = 0xffff;
19663 + break;
19664 + }
19665 +
19666 + if (si->sb.boardtype == 0) {
19667 + SB_ERROR(("sb_doattach: unknown board type\n"));
19668 + ASSERT(si->sb.boardtype);
19669 + }
19670 +
19671 + /* setup the GPIO based LED powersave register */
19672 + if (si->sb.ccrev >= 16) {
19673 + w = getintvar(*vars, "gpiotimerval");
19674 + if (!w)
19675 + w = DEFAULT_GPIOTIMERVAL;
19676 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
19677 + }
19678 +
19679 +
19680 + return (si);
19681 +}
19682 +
19683 +uint
19684 +sb_coreid(sb_t *sbh)
19685 +{
19686 + sb_info_t *si;
19687 + sbconfig_t *sb;
19688 +
19689 + si = SB_INFO(sbh);
19690 + sb = REGS2SB(si->curmap);
19691 +
19692 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
19693 +}
19694 +
19695 +uint
19696 +sb_coreidx(sb_t *sbh)
19697 +{
19698 + sb_info_t *si;
19699 +
19700 + si = SB_INFO(sbh);
19701 + return (si->curidx);
19702 +}
19703 +
19704 +/* return current index of core */
19705 +static uint
19706 +_sb_coreidx(sb_info_t *si)
19707 +{
19708 + sbconfig_t *sb;
19709 + uint32 sbaddr = 0;
19710 +
19711 + ASSERT(si);
19712 +
19713 + switch (BUSTYPE(si->sb.bustype)) {
19714 + case SB_BUS:
19715 + sb = REGS2SB(si->curmap);
19716 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
19717 + break;
19718 +
19719 + case PCI_BUS:
19720 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
19721 + break;
19722 +
19723 + case PCMCIA_BUS: {
19724 + uint8 tmp = 0;
19725 +
19726 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
19727 + sbaddr = (uint)tmp << 12;
19728 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
19729 + sbaddr |= (uint)tmp << 16;
19730 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
19731 + sbaddr |= (uint)tmp << 24;
19732 + break;
19733 + }
19734 +
19735 +#ifdef BCMJTAG
19736 + case JTAG_BUS:
19737 + sbaddr = (uint32)si->curmap;
19738 + break;
19739 +#endif /* BCMJTAG */
19740 +
19741 + default:
19742 + ASSERT(0);
19743 + }
19744 +
19745 + if (!GOODCOREADDR(sbaddr))
19746 + return BADIDX;
19747 +
19748 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
19749 +}
19750 +
19751 +uint
19752 +sb_corevendor(sb_t *sbh)
19753 +{
19754 + sb_info_t *si;
19755 + sbconfig_t *sb;
19756 +
19757 + si = SB_INFO(sbh);
19758 + sb = REGS2SB(si->curmap);
19759 +
19760 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
19761 +}
19762 +
19763 +uint
19764 +sb_corerev(sb_t *sbh)
19765 +{
19766 + sb_info_t *si;
19767 + sbconfig_t *sb;
19768 + uint sbidh;
19769 +
19770 + si = SB_INFO(sbh);
19771 + sb = REGS2SB(si->curmap);
19772 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
19773 +
19774 + return (SBCOREREV(sbidh));
19775 +}
19776 +
19777 +void *
19778 +sb_osh(sb_t *sbh)
19779 +{
19780 + sb_info_t *si;
19781 +
19782 + si = SB_INFO(sbh);
19783 + return si->osh;
19784 +}
19785 +
19786 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
19787 +
19788 +/* set/clear sbtmstatelow core-specific flags */
19789 +uint32
19790 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
19791 +{
19792 + sb_info_t *si;
19793 + sbconfig_t *sb;
19794 + uint32 w;
19795 +
19796 + si = SB_INFO(sbh);
19797 + sb = REGS2SB(si->curmap);
19798 +
19799 + ASSERT((val & ~mask) == 0);
19800 + ASSERT((mask & ~SBTML_ALLOW) == 0);
19801 +
19802 + /* mask and set */
19803 + if (mask || val) {
19804 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
19805 + W_SBREG(si, &sb->sbtmstatelow, w);
19806 + }
19807 +
19808 + /* return the new value */
19809 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
19810 +}
19811 +
19812 +/* set/clear sbtmstatehigh core-specific flags */
19813 +uint32
19814 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
19815 +{
19816 + sb_info_t *si;
19817 + sbconfig_t *sb;
19818 + uint32 w;
19819 +
19820 + si = SB_INFO(sbh);
19821 + sb = REGS2SB(si->curmap);
19822 +
19823 + ASSERT((val & ~mask) == 0);
19824 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
19825 +
19826 + /* mask and set */
19827 + if (mask || val) {
19828 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
19829 + W_SBREG(si, &sb->sbtmstatehigh, w);
19830 + }
19831 +
19832 + /* return the new value */
19833 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
19834 +}
19835 +
19836 +/* caller needs to take care of core-specific bist hazards */
19837 +int
19838 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
19839 +{
19840 + uint32 sblo;
19841 + uint coreidx;
19842 + sb_info_t *si;
19843 + int result = 0;
19844 +
19845 + si = SB_INFO(sbh);
19846 +
19847 + coreidx = sb_findcoreidx(si, coreid, coreunit);
19848 + if (!GOODIDX(coreidx))
19849 + result = BCME_ERROR;
19850 + else {
19851 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
19852 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
19853 +
19854 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
19855 +
19856 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
19857 + result = BCME_ERROR;
19858 +
19859 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
19860 + }
19861 +
19862 + return result;
19863 +}
19864 +
19865 +bool
19866 +sb_iscoreup(sb_t *sbh)
19867 +{
19868 + sb_info_t *si;
19869 + sbconfig_t *sb;
19870 +
19871 + si = SB_INFO(sbh);
19872 + sb = REGS2SB(si->curmap);
19873 +
19874 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
19875 +}
19876 +
19877 +/*
19878 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
19879 + * switch back to the original core, and return the new value.
19880 + */
19881 +static uint
19882 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
19883 +{
19884 + uint origidx;
19885 + uint32 *r;
19886 + uint w;
19887 + uint intr_val = 0;
19888 +
19889 + ASSERT(GOODIDX(coreidx));
19890 + ASSERT(regoff < SB_CORE_SIZE);
19891 + ASSERT((val & ~mask) == 0);
19892 +
19893 + INTR_OFF(si, intr_val);
19894 +
19895 + /* save current core index */
19896 + origidx = sb_coreidx(&si->sb);
19897 +
19898 + /* switch core */
19899 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
19900 +
19901 + /* mask and set */
19902 + if (mask || val) {
19903 + if (regoff >= SBCONFIGOFF) {
19904 + w = (R_SBREG(si, r) & ~mask) | val;
19905 + W_SBREG(si, r, w);
19906 + } else {
19907 + w = (R_REG(r) & ~mask) | val;
19908 + W_REG(r, w);
19909 + }
19910 + }
19911 +
19912 + /* readback */
19913 + if (regoff >= SBCONFIGOFF)
19914 + w = R_SBREG(si, r);
19915 + else
19916 + w = R_REG(r);
19917 +
19918 + /* restore core index */
19919 + if (origidx != coreidx)
19920 + sb_setcoreidx(&si->sb, origidx);
19921 +
19922 + INTR_RESTORE(si, intr_val);
19923 + return (w);
19924 +}
19925 +
19926 +#define DWORD_ALIGN(x) (x & ~(0x03))
19927 +#define BYTE_POS(x) (x & 0x3)
19928 +#define WORD_POS(x) (x & 0x1)
19929 +
19930 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
19931 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
19932 +
19933 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
19934 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
19935 +
19936 +#define read_pci_cfg_byte(a) \
19937 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
19938 +
19939 +#define read_pci_cfg_write(a) \
19940 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
19941 +
19942 +
19943 +/* return TRUE if requested capability exists in the PCI config space */
19944 +static bool
19945 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
19946 +{
19947 + uint8 cap_id;
19948 + uint8 cap_ptr;
19949 + uint32 bufsize;
19950 + uint8 byte_val;
19951 +
19952 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
19953 + return FALSE;
19954 +
19955 + /* check for Header type 0*/
19956 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
19957 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
19958 + return FALSE;
19959 +
19960 + /* check if the capability pointer field exists */
19961 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
19962 + if (!(byte_val & PCI_CAPPTR_PRESENT))
19963 + return FALSE;
19964 +
19965 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
19966 + /* check if the capability pointer is 0x00 */
19967 + if (cap_ptr == 0x00)
19968 + return FALSE;
19969 +
19970 +
19971 + /* loop thr'u the capability list and see if the pcie capabilty exists */
19972 +
19973 + cap_id = read_pci_cfg_byte(cap_ptr);
19974 +
19975 + while (cap_id != req_cap_id) {
19976 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
19977 + if (cap_ptr == 0x00) break;
19978 + cap_id = read_pci_cfg_byte(cap_ptr);
19979 + }
19980 + if (cap_id != req_cap_id) {
19981 + return FALSE;
19982 + }
19983 + /* found the caller requested capability */
19984 + if ((buf != NULL) && (buflen != NULL)) {
19985 + bufsize = *buflen;
19986 + if (!bufsize) goto end;
19987 + *buflen = 0;
19988 + /* copy the cpability data excluding cap ID and next ptr */
19989 + cap_ptr += 2;
19990 + if ((bufsize + cap_ptr) > SZPCR)
19991 + bufsize = SZPCR - cap_ptr;
19992 + *buflen = bufsize;
19993 + while (bufsize--) {
19994 + *buf = read_pci_cfg_byte(cap_ptr);
19995 + cap_ptr++;
19996 + buf++;
19997 + }
19998 + }
19999 +end:
20000 + return TRUE;
20001 +}
20002 +
20003 +/* return TRUE if PCIE capability exists the pci config space */
20004 +static bool
20005 +sb_ispcie(sb_info_t *si)
20006 +{
20007 + return(sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
20008 +}
20009 +
20010 +/* scan the sb enumerated space to identify all cores */
20011 +static void
20012 +BCMINITFN(sb_scan)(sb_info_t *si)
20013 +{
20014 + uint origidx;
20015 + uint i;
20016 + bool pci;
20017 + bool pcie;
20018 + uint pciidx;
20019 + uint pcieidx;
20020 + uint pcirev;
20021 + uint pcierev;
20022 +
20023 +
20024 +
20025 + /* numcores should already be set */
20026 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
20027 +
20028 + /* save current core index */
20029 + origidx = sb_coreidx(&si->sb);
20030 +
20031 + si->sb.buscorerev = NOREV;
20032 + si->sb.buscoreidx = BADIDX;
20033 +
20034 + si->gpioidx = BADIDX;
20035 +
20036 + pci = pcie = FALSE;
20037 + pcirev = pcierev = NOREV;
20038 + pciidx = pcieidx = BADIDX;
20039 +
20040 + for (i = 0; i < si->numcores; i++) {
20041 + sb_setcoreidx(&si->sb, i);
20042 + si->coreid[i] = sb_coreid(&si->sb);
20043 +
20044 + if (si->coreid[i] == SB_PCI) {
20045 + pciidx = i;
20046 + pcirev = sb_corerev(&si->sb);
20047 + pci = TRUE;
20048 + } else if (si->coreid[i] == SB_PCIE) {
20049 + pcieidx = i;
20050 + pcierev = sb_corerev(&si->sb);
20051 + pcie = TRUE;
20052 + } else if (si->coreid[i] == SB_PCMCIA) {
20053 + si->sb.buscorerev = sb_corerev(&si->sb);
20054 + si->sb.buscoretype = si->coreid[i];
20055 + si->sb.buscoreidx = i;
20056 + }
20057 + }
20058 + if (pci && pcie) {
20059 + if (sb_ispcie(si))
20060 + pci = FALSE;
20061 + else
20062 + pcie = FALSE;
20063 + }
20064 + if (pci) {
20065 + si->sb.buscoretype = SB_PCI;
20066 + si->sb.buscorerev = pcirev;
20067 + si->sb.buscoreidx = pciidx;
20068 + }
20069 + else if (pcie) {
20070 + si->sb.buscoretype = SB_PCIE;
20071 + si->sb.buscorerev = pcierev;
20072 + si->sb.buscoreidx = pcieidx;
20073 + }
20074 +
20075 + /*
20076 + * Find the gpio "controlling core" type and index.
20077 + * Precedence:
20078 + * - if there's a chip common core - use that
20079 + * - else if there's a pci core (rev >= 2) - use that
20080 + * - else there had better be an extif core (4710 only)
20081 + */
20082 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
20083 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
20084 + si->gpioid = SB_CC;
20085 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
20086 + si->gpioidx = si->sb.buscoreidx;
20087 + si->gpioid = SB_PCI;
20088 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
20089 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
20090 + si->gpioid = SB_EXTIF;
20091 + } else
20092 + ASSERT(si->gpioidx != BADIDX);
20093 +
20094 + /* return to original core index */
20095 + sb_setcoreidx(&si->sb, origidx);
20096 +}
20097 +
20098 +/* may be called with core in reset */
20099 +void
20100 +sb_detach(sb_t *sbh)
20101 +{
20102 + sb_info_t *si;
20103 + uint idx;
20104 +
20105 + si = SB_INFO(sbh);
20106 +
20107 + if (si == NULL)
20108 + return;
20109 +
20110 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
20111 + for (idx = 0; idx < SB_MAXCORES; idx++)
20112 + if (si->regs[idx]) {
20113 + REG_UNMAP(si->regs[idx]);
20114 + si->regs[idx] = NULL;
20115 + }
20116 +
20117 + if (si != &ksi)
20118 + MFREE(si->osh, si, sizeof (sb_info_t));
20119 +}
20120 +
20121 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
20122 +static uint
20123 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
20124 +{
20125 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
20126 + return (BCM4710_DEVICE_ID);
20127 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
20128 + return (BCM4402_DEVICE_ID);
20129 + if (pcidev == BCM4401_ENET_ID)
20130 + return (BCM4402_DEVICE_ID);
20131 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
20132 + return (BCM4307_DEVICE_ID);
20133 + if (pcidev == BCM4301_DEVICE_ID)
20134 + return (BCM4301_DEVICE_ID);
20135 +
20136 + return (0);
20137 +}
20138 +
20139 +/* convert chip number to number of i/o cores */
20140 +static uint
20141 +BCMINITFN(sb_chip2numcores)(uint chip)
20142 +{
20143 + if (chip == BCM4710_DEVICE_ID)
20144 + return (9);
20145 + if (chip == BCM4402_DEVICE_ID)
20146 + return (3);
20147 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
20148 + return (5);
20149 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
20150 + return (6);
20151 + if (chip == BCM4704_DEVICE_ID)
20152 + return (9);
20153 + if (chip == BCM5365_DEVICE_ID)
20154 + return (7);
20155 +
20156 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
20157 + ASSERT(0);
20158 + return (1);
20159 +}
20160 +
20161 +/* return index of coreid or BADIDX if not found */
20162 +static uint
20163 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
20164 +{
20165 + uint found;
20166 + uint i;
20167 +
20168 + found = 0;
20169 +
20170 + for (i = 0; i < si->numcores; i++)
20171 + if (si->coreid[i] == coreid) {
20172 + if (found == coreunit)
20173 + return (i);
20174 + found++;
20175 + }
20176 +
20177 + return (BADIDX);
20178 +}
20179 +
20180 +/*
20181 + * this function changes logical "focus" to the indiciated core,
20182 + * must be called with interrupt off.
20183 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
20184 + */
20185 +void*
20186 +sb_setcoreidx(sb_t *sbh, uint coreidx)
20187 +{
20188 + sb_info_t *si;
20189 + uint32 sbaddr;
20190 + uint8 tmp;
20191 +
20192 + si = SB_INFO(sbh);
20193 +
20194 + if (coreidx >= si->numcores)
20195 + return (NULL);
20196 +
20197 + /*
20198 + * If the user has provided an interrupt mask enabled function,
20199 + * then assert interrupts are disabled before switching the core.
20200 + */
20201 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
20202 +
20203 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
20204 +
20205 + switch (BUSTYPE(si->sb.bustype)) {
20206 + case SB_BUS:
20207 + /* map new one */
20208 + if (!si->regs[coreidx]) {
20209 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
20210 + ASSERT(GOODREGS(si->regs[coreidx]));
20211 + }
20212 + si->curmap = si->regs[coreidx];
20213 + break;
20214 +
20215 + case PCI_BUS:
20216 + /* point bar0 window */
20217 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
20218 + break;
20219 +
20220 + case PCMCIA_BUS:
20221 + tmp = (sbaddr >> 12) & 0x0f;
20222 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
20223 + tmp = (sbaddr >> 16) & 0xff;
20224 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
20225 + tmp = (sbaddr >> 24) & 0xff;
20226 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
20227 + break;
20228 +#ifdef BCMJTAG
20229 + case JTAG_BUS:
20230 + /* map new one */
20231 + if (!si->regs[coreidx]) {
20232 + si->regs[coreidx] = (void *)sbaddr;
20233 + ASSERT(GOODREGS(si->regs[coreidx]));
20234 + }
20235 + si->curmap = si->regs[coreidx];
20236 + break;
20237 +#endif /* BCMJTAG */
20238 + }
20239 +
20240 + si->curidx = coreidx;
20241 +
20242 + return (si->curmap);
20243 +}
20244 +
20245 +/*
20246 + * this function changes logical "focus" to the indiciated core,
20247 + * must be called with interrupt off.
20248 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
20249 + */
20250 +void*
20251 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
20252 +{
20253 + sb_info_t *si;
20254 + uint idx;
20255 +
20256 + si = SB_INFO(sbh);
20257 + idx = sb_findcoreidx(si, coreid, coreunit);
20258 + if (!GOODIDX(idx))
20259 + return (NULL);
20260 +
20261 + return (sb_setcoreidx(sbh, idx));
20262 +}
20263 +
20264 +/* return chip number */
20265 +uint
20266 +BCMINITFN(sb_chip)(sb_t *sbh)
20267 +{
20268 + sb_info_t *si;
20269 +
20270 + si = SB_INFO(sbh);
20271 + return (si->sb.chip);
20272 +}
20273 +
20274 +/* return chip revision number */
20275 +uint
20276 +BCMINITFN(sb_chiprev)(sb_t *sbh)
20277 +{
20278 + sb_info_t *si;
20279 +
20280 + si = SB_INFO(sbh);
20281 + return (si->sb.chiprev);
20282 +}
20283 +
20284 +/* return chip common revision number */
20285 +uint
20286 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
20287 +{
20288 + sb_info_t *si;
20289 +
20290 + si = SB_INFO(sbh);
20291 + return (si->sb.ccrev);
20292 +}
20293 +
20294 +/* return chip package option */
20295 +uint
20296 +BCMINITFN(sb_chippkg)(sb_t *sbh)
20297 +{
20298 + sb_info_t *si;
20299 +
20300 + si = SB_INFO(sbh);
20301 + return (si->sb.chippkg);
20302 +}
20303 +
20304 +/* return PCI core rev. */
20305 +uint
20306 +BCMINITFN(sb_pcirev)(sb_t *sbh)
20307 +{
20308 + sb_info_t *si;
20309 +
20310 + si = SB_INFO(sbh);
20311 + return (si->sb.buscorerev);
20312 +}
20313 +
20314 +bool
20315 +BCMINITFN(sb_war16165)(sb_t *sbh)
20316 +{
20317 + sb_info_t *si;
20318 +
20319 + si = SB_INFO(sbh);
20320 +
20321 + return (PCI(si) && (si->sb.buscorerev <= 10));
20322 +}
20323 +
20324 +static void
20325 +BCMINITFN(sb_war30841)(sb_info_t *si)
20326 +{
20327 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
20328 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
20329 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
20330 +}
20331 +
20332 +/* return PCMCIA core rev. */
20333 +uint
20334 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
20335 +{
20336 + sb_info_t *si;
20337 +
20338 + si = SB_INFO(sbh);
20339 + return (si->sb.buscorerev);
20340 +}
20341 +
20342 +/* return board vendor id */
20343 +uint
20344 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
20345 +{
20346 + sb_info_t *si;
20347 +
20348 + si = SB_INFO(sbh);
20349 + return (si->sb.boardvendor);
20350 +}
20351 +
20352 +/* return boardtype */
20353 +uint
20354 +BCMINITFN(sb_boardtype)(sb_t *sbh)
20355 +{
20356 + sb_info_t *si;
20357 + char *var;
20358 +
20359 + si = SB_INFO(sbh);
20360 +
20361 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
20362 + /* boardtype format is a hex string */
20363 + si->sb.boardtype = getintvar(NULL, "boardtype");
20364 +
20365 + /* backward compatibility for older boardtype string format */
20366 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
20367 + if (!strcmp(var, "bcm94710dev"))
20368 + si->sb.boardtype = BCM94710D_BOARD;
20369 + else if (!strcmp(var, "bcm94710ap"))
20370 + si->sb.boardtype = BCM94710AP_BOARD;
20371 + else if (!strcmp(var, "bu4710"))
20372 + si->sb.boardtype = BU4710_BOARD;
20373 + else if (!strcmp(var, "bcm94702mn"))
20374 + si->sb.boardtype = BCM94702MN_BOARD;
20375 + else if (!strcmp(var, "bcm94710r1"))
20376 + si->sb.boardtype = BCM94710R1_BOARD;
20377 + else if (!strcmp(var, "bcm94710r4"))
20378 + si->sb.boardtype = BCM94710R4_BOARD;
20379 + else if (!strcmp(var, "bcm94702cpci"))
20380 + si->sb.boardtype = BCM94702CPCI_BOARD;
20381 + else if (!strcmp(var, "bcm95380_rr"))
20382 + si->sb.boardtype = BCM95380RR_BOARD;
20383 + }
20384 + }
20385 +
20386 + return (si->sb.boardtype);
20387 +}
20388 +
20389 +/* return bus type of sbh device */
20390 +uint
20391 +sb_bus(sb_t *sbh)
20392 +{
20393 + sb_info_t *si;
20394 +
20395 + si = SB_INFO(sbh);
20396 + return (si->sb.bustype);
20397 +}
20398 +
20399 +/* return bus core type */
20400 +uint
20401 +sb_buscoretype(sb_t *sbh)
20402 +{
20403 + sb_info_t *si;
20404 +
20405 + si = SB_INFO(sbh);
20406 +
20407 + return (si->sb.buscoretype);
20408 +}
20409 +
20410 +/* return bus core revision */
20411 +uint
20412 +sb_buscorerev(sb_t *sbh)
20413 +{
20414 + sb_info_t *si;
20415 + si = SB_INFO(sbh);
20416 +
20417 + return (si->sb.buscorerev);
20418 +}
20419 +
20420 +/* return list of found cores */
20421 +uint
20422 +sb_corelist(sb_t *sbh, uint coreid[])
20423 +{
20424 + sb_info_t *si;
20425 +
20426 + si = SB_INFO(sbh);
20427 +
20428 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
20429 + return (si->numcores);
20430 +}
20431 +
20432 +/* return current register mapping */
20433 +void *
20434 +sb_coreregs(sb_t *sbh)
20435 +{
20436 + sb_info_t *si;
20437 +
20438 + si = SB_INFO(sbh);
20439 + ASSERT(GOODREGS(si->curmap));
20440 +
20441 + return (si->curmap);
20442 +}
20443 +
20444 +
20445 +/* do buffered registers update */
20446 +void
20447 +sb_commit(sb_t *sbh)
20448 +{
20449 + sb_info_t *si;
20450 + uint origidx;
20451 + uint intr_val = 0;
20452 +
20453 + si = SB_INFO(sbh);
20454 +
20455 + origidx = si->curidx;
20456 + ASSERT(GOODIDX(origidx));
20457 +
20458 + INTR_OFF(si, intr_val);
20459 +
20460 + /* switch over to chipcommon core if there is one, else use pci */
20461 + if (si->sb.ccrev != NOREV) {
20462 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
20463 +
20464 + /* do the buffer registers update */
20465 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
20466 + W_REG(&ccregs->broadcastdata, 0x0);
20467 + } else if (PCI(si)) {
20468 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
20469 +
20470 + /* do the buffer registers update */
20471 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
20472 + W_REG(&pciregs->bcastdata, 0x0);
20473 + } else
20474 + ASSERT(0);
20475 +
20476 + /* restore core index */
20477 + sb_setcoreidx(sbh, origidx);
20478 + INTR_RESTORE(si, intr_val);
20479 +}
20480 +
20481 +/* reset and re-enable a core */
20482 +void
20483 +sb_core_reset(sb_t *sbh, uint32 bits)
20484 +{
20485 + sb_info_t *si;
20486 + sbconfig_t *sb;
20487 + volatile uint32 dummy;
20488 +
20489 + si = SB_INFO(sbh);
20490 + ASSERT(GOODREGS(si->curmap));
20491 + sb = REGS2SB(si->curmap);
20492 +
20493 + /*
20494 + * Must do the disable sequence first to work for arbitrary current core state.
20495 + */
20496 + sb_core_disable(sbh, bits);
20497 +
20498 + /*
20499 + * Now do the initialization sequence.
20500 + */
20501 +
20502 + /* set reset while enabling the clock and forcing them on throughout the core */
20503 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
20504 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20505 + OSL_DELAY(1);
20506 +
20507 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
20508 + W_SBREG(si, &sb->sbtmstatehigh, 0);
20509 + }
20510 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
20511 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
20512 + }
20513 +
20514 + /* clear reset and allow it to propagate throughout the core */
20515 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
20516 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20517 + OSL_DELAY(1);
20518 +
20519 + /* leave clock enabled */
20520 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
20521 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20522 + OSL_DELAY(1);
20523 +}
20524 +
20525 +void
20526 +sb_core_tofixup(sb_t *sbh)
20527 +{
20528 + sb_info_t *si;
20529 + sbconfig_t *sb;
20530 +
20531 + si = SB_INFO(sbh);
20532 +
20533 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) || (PCI(si) && (si->sb.buscorerev >= 5)) )
20534 + return;
20535 +
20536 + ASSERT(GOODREGS(si->curmap));
20537 + sb = REGS2SB(si->curmap);
20538 +
20539 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
20540 + SET_SBREG(si, &sb->sbimconfiglow,
20541 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20542 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
20543 + } else {
20544 + if (sb_coreid(sbh) == SB_PCI) {
20545 + SET_SBREG(si, &sb->sbimconfiglow,
20546 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20547 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
20548 + } else {
20549 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
20550 + }
20551 + }
20552 +
20553 + sb_commit(sbh);
20554 +}
20555 +
20556 +/*
20557 + * Set the initiator timeout for the "master core".
20558 + * The master core is defined to be the core in control
20559 + * of the chip and so it issues accesses to non-memory
20560 + * locations (Because of dma *any* core can access memeory).
20561 + *
20562 + * The routine uses the bus to decide who is the master:
20563 + * SB_BUS => mips
20564 + * JTAG_BUS => chipc
20565 + * PCI_BUS => pci or pcie
20566 + * PCMCIA_BUS => pcmcia
20567 + * SDIO_BUS => pcmcia
20568 + *
20569 + * This routine exists so callers can disable initiator
20570 + * timeouts so accesses to very slow devices like otp
20571 + * won't cause an abort. The routine allows arbitrary
20572 + * settings of the service and request timeouts, though.
20573 + *
20574 + * Returns the timeout state before changing it or -1
20575 + * on error.
20576 + */
20577 +
20578 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
20579 +
20580 +uint32
20581 +sb_set_initiator_to(sb_t *sbh, uint32 to)
20582 +{
20583 + sb_info_t *si;
20584 + uint origidx, idx;
20585 + uint intr_val = 0;
20586 + uint32 tmp, ret = 0xffffffff;
20587 + sbconfig_t *sb;
20588 +
20589 + si = SB_INFO(sbh);
20590 +
20591 + if ((to & ~TO_MASK) != 0)
20592 + return ret;
20593 +
20594 + /* Figure out the master core */
20595 + idx = BADIDX;
20596 + switch (BUSTYPE(si->sb.bustype)) {
20597 + case PCI_BUS:
20598 + idx = si->sb.buscoreidx;
20599 + break;
20600 + case JTAG_BUS:
20601 + idx = SB_CC_IDX;
20602 + break;
20603 + case PCMCIA_BUS:
20604 + case SDIO_BUS:
20605 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
20606 + break;
20607 + case SB_BUS:
20608 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
20609 + idx = sb_findcoreidx(si, SB_MIPS, 0);
20610 + break;
20611 + default:
20612 + ASSERT(0);
20613 + }
20614 + if (idx == BADIDX)
20615 + return ret;
20616 +
20617 + INTR_OFF(si, intr_val);
20618 + origidx = sb_coreidx(sbh);
20619 +
20620 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
20621 +
20622 + tmp = R_SBREG(si, &sb->sbimconfiglow);
20623 + ret = tmp & TO_MASK;
20624 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
20625 +
20626 + sb_commit(sbh);
20627 + sb_setcoreidx(sbh, origidx);
20628 + INTR_RESTORE(si, intr_val);
20629 + return ret;
20630 +}
20631 +
20632 +void
20633 +sb_core_disable(sb_t *sbh, uint32 bits)
20634 +{
20635 + sb_info_t *si;
20636 + volatile uint32 dummy;
20637 + uint32 rej;
20638 + sbconfig_t *sb;
20639 +
20640 + si = SB_INFO(sbh);
20641 +
20642 + ASSERT(GOODREGS(si->curmap));
20643 + sb = REGS2SB(si->curmap);
20644 +
20645 + /* if core is already in reset, just return */
20646 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
20647 + return;
20648 +
20649 + /* reject value changed between sonics 2.2 and 2.3 */
20650 + if (si->sb.sonicsrev == SONICS_2_2)
20651 + rej = (1 << SBTML_REJ_SHIFT);
20652 + else
20653 + rej = (2 << SBTML_REJ_SHIFT);
20654 +
20655 + /* if clocks are not enabled, put into reset and return */
20656 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
20657 + goto disable;
20658 +
20659 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
20660 + OR_SBREG(si, &sb->sbtmstatelow, rej);
20661 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20662 + OSL_DELAY(1);
20663 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
20664 +
20665 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
20666 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
20667 + dummy = R_SBREG(si, &sb->sbimstate);
20668 + OSL_DELAY(1);
20669 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
20670 + }
20671 +
20672 + /* set reset and reject while enabling the clocks */
20673 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
20674 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20675 + OSL_DELAY(10);
20676 +
20677 + /* don't forget to clear the initiator reject bit */
20678 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
20679 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
20680 +
20681 +disable:
20682 + /* leave reset and reject asserted */
20683 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
20684 + OSL_DELAY(1);
20685 +}
20686 +
20687 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
20688 +void
20689 +sb_watchdog(sb_t *sbh, uint ticks)
20690 +{
20691 + sb_info_t *si = SB_INFO(sbh);
20692 +
20693 + /* instant NMI */
20694 + switch (si->gpioid) {
20695 + case SB_CC:
20696 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
20697 + break;
20698 + case SB_EXTIF:
20699 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
20700 + break;
20701 + }
20702 +}
20703 +
20704 +/* initialize the pcmcia core */
20705 +void
20706 +sb_pcmcia_init(sb_t *sbh)
20707 +{
20708 + sb_info_t *si;
20709 + uint8 cor;
20710 +
20711 + si = SB_INFO(sbh);
20712 +
20713 + /* enable d11 mac interrupts */
20714 + if (si->sb.chip == BCM4301_DEVICE_ID) {
20715 + /* Have to use FCR2 in 4301 */
20716 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
20717 + cor |= COR_IRQEN | COR_FUNEN;
20718 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
20719 + } else {
20720 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
20721 + cor |= COR_IRQEN | COR_FUNEN;
20722 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
20723 + }
20724 +
20725 +}
20726 +
20727 +
20728 +/*
20729 + * Configure the pci core for pci client (NIC) action
20730 + * coremask is the bitvec of cores by index to be enabled.
20731 + */
20732 +void
20733 +sb_pci_setup(sb_t *sbh, uint coremask)
20734 +{
20735 + sb_info_t *si;
20736 + sbconfig_t *sb;
20737 + sbpciregs_t *pciregs;
20738 + uint32 sbflag;
20739 + uint32 w;
20740 + uint idx;
20741 + int reg_val;
20742 +
20743 + si = SB_INFO(sbh);
20744 +
20745 + /* if not pci bus, we're done */
20746 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
20747 + return;
20748 +
20749 + ASSERT(PCI(si) || PCIE(si));
20750 + ASSERT(si->sb.buscoreidx != BADIDX);
20751 +
20752 + /* get current core index */
20753 + idx = si->curidx;
20754 +
20755 + /* we interrupt on this backplane flag number */
20756 + ASSERT(GOODREGS(si->curmap));
20757 + sb = REGS2SB(si->curmap);
20758 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
20759 +
20760 + /* switch over to pci core */
20761 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
20762 + sb = REGS2SB(pciregs);
20763 +
20764 + /*
20765 + * Enable sb->pci interrupts. Assume
20766 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
20767 + */
20768 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
20769 + /* pci config write to set this core bit in PCIIntMask */
20770 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
20771 + w |= (coremask << PCI_SBIM_SHIFT);
20772 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
20773 + } else {
20774 + /* set sbintvec bit for our flag number */
20775 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
20776 + }
20777 +
20778 + if (PCI(si)) {
20779 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
20780 + if (si->sb.buscorerev >= 11)
20781 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
20782 + if (si->sb.buscorerev < 5) {
20783 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20784 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
20785 + sb_commit(sbh);
20786 + }
20787 + }
20788 +
20789 + if (PCIE(si) && (si->sb.buscorerev == 0)) {
20790 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG);
20791 + reg_val |= 0x8;
20792 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG, reg_val);
20793 +
20794 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG);
20795 + reg_val &= ~(0x40);
20796 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
20797 +
20798 + BCMINIT(sb_war30841)(si);
20799 + }
20800 +
20801 + /* switch back to previous core */
20802 + sb_setcoreidx(sbh, idx);
20803 +}
20804 +
20805 +uint32
20806 +sb_base(uint32 admatch)
20807 +{
20808 + uint32 base;
20809 + uint type;
20810 +
20811 + type = admatch & SBAM_TYPE_MASK;
20812 + ASSERT(type < 3);
20813 +
20814 + base = 0;
20815 +
20816 + if (type == 0) {
20817 + base = admatch & SBAM_BASE0_MASK;
20818 + } else if (type == 1) {
20819 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20820 + base = admatch & SBAM_BASE1_MASK;
20821 + } else if (type == 2) {
20822 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20823 + base = admatch & SBAM_BASE2_MASK;
20824 + }
20825 +
20826 + return (base);
20827 +}
20828 +
20829 +uint32
20830 +sb_size(uint32 admatch)
20831 +{
20832 + uint32 size;
20833 + uint type;
20834 +
20835 + type = admatch & SBAM_TYPE_MASK;
20836 + ASSERT(type < 3);
20837 +
20838 + size = 0;
20839 +
20840 + if (type == 0) {
20841 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
20842 + } else if (type == 1) {
20843 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20844 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
20845 + } else if (type == 2) {
20846 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20847 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
20848 + }
20849 +
20850 + return (size);
20851 +}
20852 +
20853 +/* return the core-type instantiation # of the current core */
20854 +uint
20855 +sb_coreunit(sb_t *sbh)
20856 +{
20857 + sb_info_t *si;
20858 + uint idx;
20859 + uint coreid;
20860 + uint coreunit;
20861 + uint i;
20862 +
20863 + si = SB_INFO(sbh);
20864 + coreunit = 0;
20865 +
20866 + idx = si->curidx;
20867 +
20868 + ASSERT(GOODREGS(si->curmap));
20869 + coreid = sb_coreid(sbh);
20870 +
20871 + /* count the cores of our type */
20872 + for (i = 0; i < idx; i++)
20873 + if (si->coreid[i] == coreid)
20874 + coreunit++;
20875 +
20876 + return (coreunit);
20877 +}
20878 +
20879 +static INLINE uint32
20880 +factor6(uint32 x)
20881 +{
20882 + switch (x) {
20883 + case CC_F6_2: return 2;
20884 + case CC_F6_3: return 3;
20885 + case CC_F6_4: return 4;
20886 + case CC_F6_5: return 5;
20887 + case CC_F6_6: return 6;
20888 + case CC_F6_7: return 7;
20889 + default: return 0;
20890 + }
20891 +}
20892 +
20893 +/* calculate the speed the SB would run at given a set of clockcontrol values */
20894 +uint32
20895 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
20896 +{
20897 + uint32 n1, n2, clock, m1, m2, m3, mc;
20898 +
20899 + n1 = n & CN_N1_MASK;
20900 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
20901 +
20902 + if (pll_type == PLL_TYPE6) {
20903 + if (m & CC_T6_MMASK)
20904 + return CC_T6_M1;
20905 + else
20906 + return CC_T6_M0;
20907 + } else if ((pll_type == PLL_TYPE1) ||
20908 + (pll_type == PLL_TYPE3) ||
20909 + (pll_type == PLL_TYPE4) ||
20910 + (pll_type == PLL_TYPE7)) {
20911 + n1 = factor6(n1);
20912 + n2 += CC_F5_BIAS;
20913 + } else if (pll_type == PLL_TYPE2) {
20914 + n1 += CC_T2_BIAS;
20915 + n2 += CC_T2_BIAS;
20916 + ASSERT((n1 >= 2) && (n1 <= 7));
20917 + ASSERT((n2 >= 5) && (n2 <= 23));
20918 + } else if (pll_type == PLL_TYPE5) {
20919 + return (100000000);
20920 + } else
20921 + ASSERT(0);
20922 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
20923 + if ((pll_type == PLL_TYPE3) ||
20924 + (pll_type == PLL_TYPE7)) {
20925 + clock = CC_CLOCK_BASE2 * n1 * n2;
20926 + }
20927 + else
20928 + clock = CC_CLOCK_BASE1 * n1 * n2;
20929 +
20930 + if (clock == 0)
20931 + return 0;
20932 +
20933 + m1 = m & CC_M1_MASK;
20934 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
20935 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
20936 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
20937 +
20938 + if ((pll_type == PLL_TYPE1) ||
20939 + (pll_type == PLL_TYPE3) ||
20940 + (pll_type == PLL_TYPE4) ||
20941 + (pll_type == PLL_TYPE7)) {
20942 + m1 = factor6(m1);
20943 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
20944 + m2 += CC_F5_BIAS;
20945 + else
20946 + m2 = factor6(m2);
20947 + m3 = factor6(m3);
20948 +
20949 + switch (mc) {
20950 + case CC_MC_BYPASS: return (clock);
20951 + case CC_MC_M1: return (clock / m1);
20952 + case CC_MC_M1M2: return (clock / (m1 * m2));
20953 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
20954 + case CC_MC_M1M3: return (clock / (m1 * m3));
20955 + default: return (0);
20956 + }
20957 + } else {
20958 + ASSERT(pll_type == PLL_TYPE2);
20959 +
20960 + m1 += CC_T2_BIAS;
20961 + m2 += CC_T2M2_BIAS;
20962 + m3 += CC_T2_BIAS;
20963 + ASSERT((m1 >= 2) && (m1 <= 7));
20964 + ASSERT((m2 >= 3) && (m2 <= 10));
20965 + ASSERT((m3 >= 2) && (m3 <= 7));
20966 +
20967 + if ((mc & CC_T2MC_M1BYP) == 0)
20968 + clock /= m1;
20969 + if ((mc & CC_T2MC_M2BYP) == 0)
20970 + clock /= m2;
20971 + if ((mc & CC_T2MC_M3BYP) == 0)
20972 + clock /= m3;
20973 +
20974 + return(clock);
20975 + }
20976 +}
20977 +
20978 +/* returns the current speed the SB is running at */
20979 +uint32
20980 +sb_clock(sb_t *sbh)
20981 +{
20982 + sb_info_t *si;
20983 + extifregs_t *eir;
20984 + chipcregs_t *cc;
20985 + uint32 n, m;
20986 + uint idx;
20987 + uint32 pll_type, rate;
20988 + uint intr_val = 0;
20989 +
20990 + si = SB_INFO(sbh);
20991 + idx = si->curidx;
20992 + pll_type = PLL_TYPE1;
20993 +
20994 + INTR_OFF(si, intr_val);
20995 +
20996 + /* switch to extif or chipc core */
20997 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
20998 + n = R_REG(&eir->clockcontrol_n);
20999 + m = R_REG(&eir->clockcontrol_sb);
21000 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
21001 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
21002 + n = R_REG(&cc->clockcontrol_n);
21003 + if (pll_type == PLL_TYPE6)
21004 + m = R_REG(&cc->clockcontrol_mips);
21005 + else if (pll_type == PLL_TYPE3)
21006 + {
21007 + // Added by Chen-I for 5365
21008 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
21009 + m = R_REG(&cc->clockcontrol_sb);
21010 + else
21011 + m = R_REG(&cc->clockcontrol_m2);
21012 + }
21013 + else
21014 + m = R_REG(&cc->clockcontrol_sb);
21015 + } else {
21016 + INTR_RESTORE(si, intr_val);
21017 + return 0;
21018 + }
21019 +
21020 + // Added by Chen-I for 5365
21021 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
21022 + {
21023 + rate = 100000000;
21024 + }
21025 + else
21026 + {
21027 + /* calculate rate */
21028 + rate = sb_clock_rate(pll_type, n, m);
21029 + if (pll_type == PLL_TYPE3)
21030 + rate = rate / 2;
21031 + }
21032 +
21033 + /* switch back to previous core */
21034 + sb_setcoreidx(sbh, idx);
21035 +
21036 + INTR_RESTORE(si, intr_val);
21037 +
21038 + return rate;
21039 +}
21040 +
21041 +/* change logical "focus" to the gpio core for optimized access */
21042 +void*
21043 +sb_gpiosetcore(sb_t *sbh)
21044 +{
21045 + sb_info_t *si;
21046 +
21047 + si = SB_INFO(sbh);
21048 +
21049 + return (sb_setcoreidx(sbh, si->gpioidx));
21050 +}
21051 +
21052 +/* mask&set gpiocontrol bits */
21053 +uint32
21054 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21055 +{
21056 + sb_info_t *si;
21057 + uint regoff;
21058 +
21059 + si = SB_INFO(sbh);
21060 + regoff = 0;
21061 +
21062 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21063 +
21064 + /* gpios could be shared on router platforms */
21065 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21066 + mask = priority ? (sb_gpioreservation & mask) :
21067 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21068 + val &= mask;
21069 + }
21070 +
21071 + switch (si->gpioid) {
21072 + case SB_CC:
21073 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
21074 + break;
21075 +
21076 + case SB_PCI:
21077 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
21078 + break;
21079 +
21080 + case SB_EXTIF:
21081 + return (0);
21082 + }
21083 +
21084 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21085 +}
21086 +
21087 +/* mask&set gpio output enable bits */
21088 +uint32
21089 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21090 +{
21091 + sb_info_t *si;
21092 + uint regoff;
21093 +
21094 + si = SB_INFO(sbh);
21095 + regoff = 0;
21096 +
21097 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21098 +
21099 + /* gpios could be shared on router platforms */
21100 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21101 + mask = priority ? (sb_gpioreservation & mask) :
21102 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21103 + val &= mask;
21104 + }
21105 +
21106 + switch (si->gpioid) {
21107 + case SB_CC:
21108 + regoff = OFFSETOF(chipcregs_t, gpioouten);
21109 + break;
21110 +
21111 + case SB_PCI:
21112 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
21113 + break;
21114 +
21115 + case SB_EXTIF:
21116 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
21117 + break;
21118 + }
21119 +
21120 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21121 +}
21122 +
21123 +/* mask&set gpio output bits */
21124 +uint32
21125 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21126 +{
21127 + sb_info_t *si;
21128 + uint regoff;
21129 +
21130 + si = SB_INFO(sbh);
21131 + regoff = 0;
21132 +
21133 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21134 +
21135 + /* gpios could be shared on router platforms */
21136 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21137 + mask = priority ? (sb_gpioreservation & mask) :
21138 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21139 + val &= mask;
21140 + }
21141 +
21142 + switch (si->gpioid) {
21143 + case SB_CC:
21144 + regoff = OFFSETOF(chipcregs_t, gpioout);
21145 + break;
21146 +
21147 + case SB_PCI:
21148 + regoff = OFFSETOF(sbpciregs_t, gpioout);
21149 + break;
21150 +
21151 + case SB_EXTIF:
21152 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
21153 + break;
21154 + }
21155 +
21156 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21157 +}
21158 +
21159 +/* reserve one gpio */
21160 +uint32
21161 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
21162 +{
21163 + sb_info_t *si;
21164 +
21165 + si = SB_INFO(sbh);
21166 +
21167 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21168 +
21169 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
21170 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
21171 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
21172 + return -1;
21173 + }
21174 + /* make sure only one bit is set */
21175 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
21176 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
21177 + return -1;
21178 + }
21179 +
21180 + /* already reserved */
21181 + if (sb_gpioreservation & gpio_bitmask)
21182 + return -1;
21183 + /* set reservation */
21184 + sb_gpioreservation |= gpio_bitmask;
21185 +
21186 + return sb_gpioreservation;
21187 +}
21188 +
21189 +/* release one gpio */
21190 +/*
21191 + * releasing the gpio doesn't change the current value on the GPIO last write value
21192 + * persists till some one overwrites it
21193 +*/
21194 +
21195 +uint32
21196 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
21197 +{
21198 + sb_info_t *si;
21199 +
21200 + si = SB_INFO(sbh);
21201 +
21202 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21203 +
21204 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
21205 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
21206 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
21207 + return -1;
21208 + }
21209 + /* make sure only one bit is set */
21210 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
21211 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
21212 + return -1;
21213 + }
21214 +
21215 + /* already released */
21216 + if (!(sb_gpioreservation & gpio_bitmask))
21217 + return -1;
21218 +
21219 + /* clear reservation */
21220 + sb_gpioreservation &= ~gpio_bitmask;
21221 +
21222 + return sb_gpioreservation;
21223 +}
21224 +
21225 +/* return the current gpioin register value */
21226 +uint32
21227 +sb_gpioin(sb_t *sbh)
21228 +{
21229 + sb_info_t *si;
21230 + uint regoff;
21231 +
21232 + si = SB_INFO(sbh);
21233 + regoff = 0;
21234 +
21235 + switch (si->gpioid) {
21236 + case SB_CC:
21237 + regoff = OFFSETOF(chipcregs_t, gpioin);
21238 + break;
21239 +
21240 + case SB_PCI:
21241 + regoff = OFFSETOF(sbpciregs_t, gpioin);
21242 + break;
21243 +
21244 + case SB_EXTIF:
21245 + regoff = OFFSETOF(extifregs_t, gpioin);
21246 + break;
21247 + }
21248 +
21249 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
21250 +}
21251 +
21252 +/* mask&set gpio interrupt polarity bits */
21253 +uint32
21254 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21255 +{
21256 + sb_info_t *si;
21257 + uint regoff;
21258 +
21259 + si = SB_INFO(sbh);
21260 + regoff = 0;
21261 +
21262 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21263 +
21264 + /* gpios could be shared on router platforms */
21265 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21266 + mask = priority ? (sb_gpioreservation & mask) :
21267 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21268 + val &= mask;
21269 + }
21270 +
21271 + switch (si->gpioid) {
21272 + case SB_CC:
21273 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
21274 + break;
21275 +
21276 + case SB_PCI:
21277 + /* pci gpio implementation does not support interrupt polarity */
21278 + ASSERT(0);
21279 + break;
21280 +
21281 + case SB_EXTIF:
21282 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
21283 + break;
21284 + }
21285 +
21286 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21287 +}
21288 +
21289 +/* mask&set gpio interrupt mask bits */
21290 +uint32
21291 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21292 +{
21293 + sb_info_t *si;
21294 + uint regoff;
21295 +
21296 + si = SB_INFO(sbh);
21297 + regoff = 0;
21298 +
21299 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21300 +
21301 + /* gpios could be shared on router platforms */
21302 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21303 + mask = priority ? (sb_gpioreservation & mask) :
21304 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21305 + val &= mask;
21306 + }
21307 +
21308 + switch (si->gpioid) {
21309 + case SB_CC:
21310 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
21311 + break;
21312 +
21313 + case SB_PCI:
21314 + /* pci gpio implementation does not support interrupt mask */
21315 + ASSERT(0);
21316 + break;
21317 +
21318 + case SB_EXTIF:
21319 + regoff = OFFSETOF(extifregs_t, gpiointmask);
21320 + break;
21321 + }
21322 +
21323 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21324 +}
21325 +
21326 +/* assign the gpio to an led */
21327 +uint32
21328 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
21329 +{
21330 + sb_info_t *si;
21331 +
21332 + si = SB_INFO(sbh);
21333 + if (si->sb.ccrev < 16)
21334 + return -1;
21335 +
21336 + /* gpio led powersave reg */
21337 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
21338 +}
21339 +
21340 +/* mask&set gpio timer val */
21341 +uint32
21342 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
21343 +{
21344 + sb_info_t *si;
21345 + si = SB_INFO(sbh);
21346 +
21347 + if (si->sb.ccrev < 16)
21348 + return -1;
21349 +
21350 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
21351 +}
21352 +
21353 +
21354 +/* return the slow clock source - LPO, XTAL, or PCI */
21355 +static uint
21356 +sb_slowclk_src(sb_info_t *si)
21357 +{
21358 + chipcregs_t *cc;
21359 +
21360 +
21361 + ASSERT(sb_coreid(&si->sb) == SB_CC);
21362 +
21363 + if (si->sb.ccrev < 6) {
21364 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
21365 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
21366 + return (SCC_SS_PCI);
21367 + else
21368 + return (SCC_SS_XTAL);
21369 + } else if (si->sb.ccrev < 10) {
21370 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
21371 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
21372 + } else /* Insta-clock */
21373 + return (SCC_SS_XTAL);
21374 +}
21375 +
21376 +/* return the ILP (slowclock) min or max frequency */
21377 +static uint
21378 +sb_slowclk_freq(sb_info_t *si, bool max)
21379 +{
21380 + chipcregs_t *cc;
21381 + uint32 slowclk;
21382 + uint div;
21383 +
21384 +
21385 + ASSERT(sb_coreid(&si->sb) == SB_CC);
21386 +
21387 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
21388 +
21389 + /* shouldn't be here unless we've established the chip has dynamic clk control */
21390 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
21391 +
21392 + slowclk = sb_slowclk_src(si);
21393 + if (si->sb.ccrev < 6) {
21394 + if (slowclk == SCC_SS_PCI)
21395 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
21396 + else
21397 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
21398 + } else if (si->sb.ccrev < 10) {
21399 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
21400 + if (slowclk == SCC_SS_LPO)
21401 + return (max? LPOMAXFREQ : LPOMINFREQ);
21402 + else if (slowclk == SCC_SS_XTAL)
21403 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
21404 + else if (slowclk == SCC_SS_PCI)
21405 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
21406 + else
21407 + ASSERT(0);
21408 + } else {
21409 + /* Chipc rev 10 is InstaClock */
21410 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
21411 + div = 4 * (div + 1);
21412 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
21413 + }
21414 + return (0);
21415 +}
21416 +
21417 +static void
21418 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
21419 +{
21420 + chipcregs_t * cc;
21421 + uint slowmaxfreq, pll_delay, slowclk;
21422 + uint pll_on_delay, fref_sel_delay;
21423 +
21424 + pll_delay = PLL_DELAY;
21425 +
21426 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
21427 + * since the xtal will also be powered down by dynamic clk control logic.
21428 + */
21429 + slowclk = sb_slowclk_src(si);
21430 + if (slowclk != SCC_SS_XTAL)
21431 + pll_delay += XTAL_ON_DELAY;
21432 +
21433 + /* Starting with 4318 it is ILP that is used for the delays */
21434 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
21435 +
21436 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
21437 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
21438 +
21439 + cc = (chipcregs_t *)chipcregs;
21440 + W_REG(&cc->pll_on_delay, pll_on_delay);
21441 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
21442 +}
21443 +
21444 +int
21445 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
21446 +{
21447 + sb_info_t *si;
21448 + uint origidx;
21449 + chipcregs_t *cc;
21450 + uint intr_val = 0;
21451 + uint err = 0;
21452 +
21453 + si = SB_INFO(sbh);
21454 +
21455 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
21456 + if (si->sb.ccrev < 6)
21457 + return 1;
21458 +
21459 + /* chipcommon cores rev10 are a whole new ball game */
21460 + if (si->sb.ccrev >= 10)
21461 + return 1;
21462 +
21463 + if (set && ((*div % 4) || (*div < 4)))
21464 + return 2;
21465 +
21466 + INTR_OFF(si, intr_val);
21467 + origidx = si->curidx;
21468 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
21469 + ASSERT(cc != NULL);
21470 +
21471 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
21472 + err = 3;
21473 + goto done;
21474 + }
21475 +
21476 + if (set) {
21477 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
21478 + sb_clkctl_setdelay(sbh, (void *)cc);
21479 + } else
21480 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
21481 +
21482 +done:
21483 + sb_setcoreidx(sbh, origidx);
21484 + INTR_RESTORE(si, intr_val);
21485 + return err;
21486 +}
21487 +
21488 +/* initialize power control delay registers */
21489 +void sb_clkctl_init(sb_t *sbh)
21490 +{
21491 + sb_info_t *si;
21492 + uint origidx;
21493 + chipcregs_t *cc;
21494 +
21495 + si = SB_INFO(sbh);
21496 +
21497 + origidx = si->curidx;
21498 +
21499 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
21500 + return;
21501 +
21502 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21503 + goto done;
21504 +
21505 + /* 4317pc does not work with SlowClock less than 5 MHz */
21506 + if ((BUSTYPE(si->sb.bustype) == PCMCIA_BUS) && (si->sb.ccrev >= 6) && (si->sb.ccrev < 10))
21507 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (ILP_DIV_5MHZ << SCC_CD_SHIFT));
21508 +
21509 + /* set all Instaclk chip ILP to 1 MHz */
21510 + else if (si->sb.ccrev >= 10)
21511 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
21512 +
21513 + sb_clkctl_setdelay(si, (void *)cc);
21514 +
21515 +done:
21516 + sb_setcoreidx(sbh, origidx);
21517 +}
21518 +void sb_pwrctl_init(sb_t *sbh)
21519 +{
21520 +sb_clkctl_init(sbh);
21521 +}
21522 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
21523 +uint16
21524 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
21525 +{
21526 + sb_info_t *si;
21527 + uint origidx;
21528 + chipcregs_t *cc;
21529 + uint slowminfreq;
21530 + uint16 fpdelay;
21531 + uint intr_val = 0;
21532 +
21533 + si = SB_INFO(sbh);
21534 + fpdelay = 0;
21535 + origidx = si->curidx;
21536 +
21537 + INTR_OFF(si, intr_val);
21538 +
21539 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
21540 + goto done;
21541 +
21542 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21543 + goto done;
21544 +
21545 + slowminfreq = sb_slowclk_freq(si, FALSE);
21546 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
21547 +
21548 +done:
21549 + sb_setcoreidx(sbh, origidx);
21550 + INTR_RESTORE(si, intr_val);
21551 + return (fpdelay);
21552 +}
21553 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
21554 +{
21555 +return sb_clkctl_fast_pwrup_delay(sbh);
21556 +}
21557 +/* turn primary xtal and/or pll off/on */
21558 +int
21559 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
21560 +{
21561 + sb_info_t *si;
21562 + uint32 in, out, outen;
21563 +
21564 + si = SB_INFO(sbh);
21565 +
21566 + switch (BUSTYPE(si->sb.bustype)) {
21567 +
21568 +
21569 + case PCMCIA_BUS:
21570 + return (0);
21571 +
21572 +
21573 + case PCI_BUS:
21574 +
21575 + /* pcie core doesn't have any mapping to control the xtal pu */
21576 + if (PCIE(si))
21577 + return -1;
21578 +
21579 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
21580 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
21581 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
21582 +
21583 + /*
21584 + * Avoid glitching the clock if GPRS is already using it.
21585 + * We can't actually read the state of the PLLPD so we infer it
21586 + * by the value of XTAL_PU which *is* readable via gpioin.
21587 + */
21588 + if (on && (in & PCI_CFG_GPIO_XTAL))
21589 + return (0);
21590 +
21591 + if (what & XTAL)
21592 + outen |= PCI_CFG_GPIO_XTAL;
21593 + if (what & PLL)
21594 + outen |= PCI_CFG_GPIO_PLL;
21595 +
21596 + if (on) {
21597 + /* turn primary xtal on */
21598 + if (what & XTAL) {
21599 + out |= PCI_CFG_GPIO_XTAL;
21600 + if (what & PLL)
21601 + out |= PCI_CFG_GPIO_PLL;
21602 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21603 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
21604 + OSL_DELAY(XTAL_ON_DELAY);
21605 + }
21606 +
21607 + /* turn pll on */
21608 + if (what & PLL) {
21609 + out &= ~PCI_CFG_GPIO_PLL;
21610 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21611 + OSL_DELAY(2000);
21612 + }
21613 + } else {
21614 + if (what & XTAL)
21615 + out &= ~PCI_CFG_GPIO_XTAL;
21616 + if (what & PLL)
21617 + out |= PCI_CFG_GPIO_PLL;
21618 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21619 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
21620 + }
21621 +
21622 + default:
21623 + return (-1);
21624 + }
21625 +
21626 + return (0);
21627 +}
21628 +
21629 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
21630 +{
21631 +return sb_clkctl_xtal(sbh,what,on);
21632 +}
21633 +
21634 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
21635 +/* returns true if ignore pll off is set and false if it is not */
21636 +bool
21637 +sb_clkctl_clk(sb_t *sbh, uint mode)
21638 +{
21639 + sb_info_t *si;
21640 + uint origidx;
21641 + chipcregs_t *cc;
21642 + uint32 scc;
21643 + bool forcefastclk=FALSE;
21644 + uint intr_val = 0;
21645 +
21646 + si = SB_INFO(sbh);
21647 +
21648 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
21649 + if (si->sb.ccrev < 6)
21650 + return (FALSE);
21651 +
21652 + /* chipcommon cores rev10 are a whole new ball game */
21653 + if (si->sb.ccrev >= 10)
21654 + return (FALSE);
21655 +
21656 + INTR_OFF(si, intr_val);
21657 +
21658 + origidx = si->curidx;
21659 +
21660 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
21661 + ASSERT(cc != NULL);
21662 +
21663 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21664 + goto done;
21665 +
21666 + switch (mode) {
21667 + case CLK_FAST: /* force fast (pll) clock */
21668 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
21669 + sb_clkctl_xtal(&si->sb, XTAL, ON);
21670 +
21671 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
21672 + break;
21673 +
21674 + case CLK_DYNAMIC: /* enable dynamic clock control */
21675 + scc = R_REG(&cc->slow_clk_ctl);
21676 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
21677 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
21678 + scc |= SCC_XC;
21679 + W_REG(&cc->slow_clk_ctl, scc);
21680 +
21681 + /* for dynamic control, we have to release our xtal_pu "force on" */
21682 + if (scc & SCC_XC)
21683 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
21684 + break;
21685 +
21686 + default:
21687 + ASSERT(0);
21688 + }
21689 +
21690 + /* Is the h/w forcing the use of the fast clk */
21691 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
21692 +
21693 +done:
21694 + sb_setcoreidx(sbh, origidx);
21695 + INTR_RESTORE(si, intr_val);
21696 + return (forcefastclk);
21697 +}
21698 +
21699 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
21700 +{
21701 +return sb_clkctl_clk(sbh, mode);
21702 +}
21703 +/* register driver interrupt disabling and restoring callback functions */
21704 +void
21705 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
21706 +{
21707 + sb_info_t *si;
21708 +
21709 + si = SB_INFO(sbh);
21710 + si->intr_arg = intr_arg;
21711 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
21712 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
21713 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
21714 + /* save current core id. when this function called, the current core
21715 + * must be the core which provides driver functions(il, et, wl, etc.)
21716 + */
21717 + si->dev_coreid = si->coreid[si->curidx];
21718 +}
21719 +
21720 +
21721 +void
21722 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
21723 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
21724 +{
21725 + uint vendor, core, unit;
21726 + uint chip, chippkg;
21727 + char varname[8];
21728 + uint8 class, subclass, progif;
21729 +
21730 + vendor = sb_corevendor(sbh);
21731 + core = sb_coreid(sbh);
21732 + unit = sb_coreunit(sbh);
21733 +
21734 + chip = BCMINIT(sb_chip)(sbh);
21735 + chippkg = BCMINIT(sb_chippkg)(sbh);
21736 +
21737 + progif = 0;
21738 +
21739 + /* Known vendor translations */
21740 + switch (vendor) {
21741 + case SB_VEND_BCM:
21742 + vendor = VENDOR_BROADCOM;
21743 + break;
21744 + }
21745 +
21746 + /* Determine class based on known core codes */
21747 + switch (core) {
21748 + case SB_ILINE20:
21749 + class = PCI_CLASS_NET;
21750 + subclass = PCI_NET_ETHER;
21751 + core = BCM47XX_ILINE_ID;
21752 + break;
21753 + case SB_ENET:
21754 + class = PCI_CLASS_NET;
21755 + subclass = PCI_NET_ETHER;
21756 + core = BCM47XX_ENET_ID;
21757 + break;
21758 + case SB_SDRAM:
21759 + case SB_MEMC:
21760 + class = PCI_CLASS_MEMORY;
21761 + subclass = PCI_MEMORY_RAM;
21762 + break;
21763 + case SB_PCI:
21764 + case SB_PCIE:
21765 + class = PCI_CLASS_BRIDGE;
21766 + subclass = PCI_BRIDGE_PCI;
21767 + break;
21768 + case SB_MIPS:
21769 + case SB_MIPS33:
21770 + class = PCI_CLASS_CPU;
21771 + subclass = PCI_CPU_MIPS;
21772 + break;
21773 + case SB_CODEC:
21774 + class = PCI_CLASS_COMM;
21775 + subclass = PCI_COMM_MODEM;
21776 + core = BCM47XX_V90_ID;
21777 + break;
21778 + case SB_USB:
21779 + class = PCI_CLASS_SERIAL;
21780 + subclass = PCI_SERIAL_USB;
21781 + progif = 0x10; /* OHCI */
21782 + core = BCM47XX_USB_ID;
21783 + break;
21784 + case SB_USB11H:
21785 + class = PCI_CLASS_SERIAL;
21786 + subclass = PCI_SERIAL_USB;
21787 + progif = 0x10; /* OHCI */
21788 + core = BCM47XX_USBH_ID;
21789 + break;
21790 + case SB_USB11D:
21791 + class = PCI_CLASS_SERIAL;
21792 + subclass = PCI_SERIAL_USB;
21793 + core = BCM47XX_USBD_ID;
21794 + break;
21795 + case SB_IPSEC:
21796 + class = PCI_CLASS_CRYPT;
21797 + subclass = PCI_CRYPT_NETWORK;
21798 + core = BCM47XX_IPSEC_ID;
21799 + break;
21800 + case SB_ROBO:
21801 + class = PCI_CLASS_NET;
21802 + subclass = PCI_NET_OTHER;
21803 + core = BCM47XX_ROBO_ID;
21804 + break;
21805 + case SB_EXTIF:
21806 + case SB_CC:
21807 + class = PCI_CLASS_MEMORY;
21808 + subclass = PCI_MEMORY_FLASH;
21809 + break;
21810 + case SB_D11:
21811 + class = PCI_CLASS_NET;
21812 + subclass = PCI_NET_OTHER;
21813 + /* Let an nvram variable override this */
21814 + sprintf(varname, "wl%did", unit);
21815 + if ((core = getintvar(NULL, varname)) == 0) {
21816 + if (chip == BCM4712_DEVICE_ID) {
21817 + if (chippkg == BCM4712SMALL_PKG_ID)
21818 + core = BCM4306_D11G_ID;
21819 + else
21820 + core = BCM4306_D11DUAL_ID;
21821 + }
21822 + }
21823 + break;
21824 +
21825 + default:
21826 + class = subclass = progif = 0xff;
21827 + break;
21828 + }
21829 +
21830 + *pcivendor = (uint16)vendor;
21831 + *pcidevice = (uint16)core;
21832 + *pciclass = class;
21833 + *pcisubclass = subclass;
21834 + *pciprogif = progif;
21835 +}
21836 +
21837 +
21838 +
21839 +
21840 +/* use the mdio interface to write to mdio slaves */
21841 +static int
21842 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
21843 +{
21844 + uint mdiodata;
21845 + uint i = 0;
21846 + sbpcieregs_t *pcieregs;
21847 +
21848 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
21849 + ASSERT (pcieregs);
21850 +
21851 + /* enable mdio access to SERDES */
21852 + W_REG((&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
21853 +
21854 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
21855 + (physmedia << MDIODATA_DEVADDR_SHF) |
21856 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
21857 +
21858 + W_REG((&pcieregs->mdiodata), mdiodata);
21859 +
21860 + PR28829_DELAY();
21861 +
21862 + /* retry till the transaction is complete */
21863 + while ( i < 10 ) {
21864 + if (R_REG(&(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
21865 + /* Disable mdio access to SERDES */
21866 + W_REG((&pcieregs->mdiocontrol), 0);
21867 + return 0;
21868 + }
21869 + OSL_DELAY(1000);
21870 + i++;
21871 + }
21872 +
21873 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
21874 + /* Disable mdio access to SERDES */
21875 + W_REG((&pcieregs->mdiocontrol), 0);
21876 + ASSERT(0);
21877 + return 1;
21878 +
21879 +}
21880 +
21881 +/* indirect way to read pcie config regs*/
21882 +uint
21883 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
21884 +{
21885 + sb_info_t *si;
21886 + sb_t *sbh;
21887 + uint retval = 0xFFFFFFFF;
21888 + sbpcieregs_t *pcieregs;
21889 + uint addrtype;
21890 +
21891 + sbh = (sb_t *)sb;
21892 + si = SB_INFO(sbh);
21893 + ASSERT (PCIE(si));
21894 +
21895 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
21896 + ASSERT (pcieregs);
21897 +
21898 + addrtype = (uint)((uintptr)arg1);
21899 + switch(addrtype) {
21900 + case PCIE_CONFIGREGS:
21901 + W_REG((&pcieregs->configaddr),offset);
21902 + retval = R_REG(&(pcieregs->configdata));
21903 + break;
21904 + case PCIE_PCIEREGS:
21905 + W_REG(&(pcieregs->pcieaddr),offset);
21906 + retval = R_REG(&(pcieregs->pciedata));
21907 + break;
21908 + default:
21909 + ASSERT(0);
21910 + break;
21911 + }
21912 + return retval;
21913 +}
21914 +
21915 +/* indirect way to write pcie config/mdio/pciecore regs*/
21916 +uint
21917 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
21918 +{
21919 + sb_info_t *si;
21920 + sbpcieregs_t *pcieregs;
21921 + uint addrtype;
21922 +
21923 + si = SB_INFO(sbh);
21924 + ASSERT (PCIE(si));
21925 +
21926 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
21927 + ASSERT (pcieregs);
21928 +
21929 + addrtype = (uint)((uintptr)arg1);
21930 +
21931 + switch(addrtype) {
21932 + case PCIE_CONFIGREGS:
21933 + W_REG((&pcieregs->configaddr),offset);
21934 + W_REG((&pcieregs->configdata),val);
21935 + break;
21936 + case PCIE_PCIEREGS:
21937 + W_REG((&pcieregs->pcieaddr),offset);
21938 + W_REG((&pcieregs->pciedata),val);
21939 + break;
21940 + default:
21941 + ASSERT(0);
21942 + break;
21943 + }
21944 + return 0;
21945 +}
21946 +
21947 +
21948 +/* Build device path. Support SB, PCI, and JTAG for now. */
21949 +int
21950 +sb_devpath(sb_t *sbh, char *path, int size)
21951 +{
21952 + ASSERT(path);
21953 + ASSERT(size >= SB_DEVPATH_BUFSZ);
21954 +
21955 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
21956 + case SB_BUS:
21957 + case JTAG_BUS:
21958 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
21959 + break;
21960 + case PCI_BUS:
21961 + ASSERT((SB_INFO(sbh))->osh);
21962 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
21963 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
21964 + break;
21965 + case PCMCIA_BUS:
21966 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
21967 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
21968 + sprintf(path, "pc/%u/%u/", 1, 1);
21969 + break;
21970 + case SDIO_BUS:
21971 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
21972 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
21973 + break;
21974 + default:
21975 + ASSERT(0);
21976 + break;
21977 + }
21978 +
21979 + return 0;
21980 +}
21981 +
21982 +/* Fix chip's configuration. The current core may be changed upon return */
21983 +static int
21984 +sb_pci_fixcfg(sb_info_t *si)
21985 +{
21986 + uint origidx, pciidx;
21987 + sbpciregs_t *pciregs;
21988 + sbpcieregs_t *pcieregs;
21989 + uint16 val16, *reg16;
21990 + char name[SB_DEVPATH_BUFSZ+16], *value;
21991 + char devpath[SB_DEVPATH_BUFSZ];
21992 +
21993 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
21994 +
21995 + /* Fix PCI(e) SROM shadow area */
21996 + /* save the current index */
21997 + origidx = sb_coreidx(&si->sb);
21998 +
21999 + /* check 'pi' is correct and fix it if not */
22000 + if (si->sb.buscoretype == SB_PCIE) {
22001 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
22002 + ASSERT(pcieregs);
22003 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
22004 + }
22005 + else if (si->sb.buscoretype == SB_PCI) {
22006 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
22007 + ASSERT(pciregs);
22008 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
22009 + }
22010 + else {
22011 + ASSERT(0);
22012 + return -1;
22013 + }
22014 + pciidx = sb_coreidx(&si->sb);
22015 + val16 = R_REG(reg16);
22016 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
22017 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
22018 + W_REG(reg16, val16);
22019 + }
22020 +
22021 + /* restore the original index */
22022 + sb_setcoreidx(&si->sb, origidx);
22023 +
22024 + /* Fix bar0window */
22025 + /* !do it last, it changes the current core! */
22026 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
22027 + return -1;
22028 + sprintf(name, "%sb0w", devpath);
22029 + if ((value = getvar(NULL, name))) {
22030 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
22031 + bcm_strtoul(value, NULL, 16));
22032 + /* update curidx since the current core is changed */
22033 + si->curidx = _sb_coreidx(si);
22034 + if (si->curidx == BADIDX) {
22035 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
22036 + return -1;
22037 + }
22038 + }
22039 +
22040 + return 0;
22041 +}
22042 +
22043 diff -urN linux.old/drivers/net/hnd/shared_ksyms.sh linux.dev/drivers/net/hnd/shared_ksyms.sh
22044 --- linux.old/drivers/net/hnd/shared_ksyms.sh 1970-01-01 01:00:00.000000000 +0100
22045 +++ linux.dev/drivers/net/hnd/shared_ksyms.sh 2005-11-07 21:57:07.917590250 +0100
22046 @@ -0,0 +1,21 @@
22047 +#!/bin/sh
22048 +#
22049 +# Copyright 2004, Broadcom Corporation
22050 +# All Rights Reserved.
22051 +#
22052 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
22053 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
22054 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
22055 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22056 +#
22057 +# $Id: shared_ksyms.sh,v 1.1 2005/03/16 13:50:00 wbx Exp $
22058 +#
22059 +
22060 +cat <<EOF
22061 +#include <linux/config.h>
22062 +#include <linux/module.h>
22063 +EOF
22064 +
22065 +for file in $* ; do
22066 + ${NM} $file | sed -ne 's/[0-9A-Fa-f]* [DT] \([^ ]*\)/extern void \1; EXPORT_SYMBOL(\1);/p'
22067 +done
22068 diff -urN linux.old/drivers/net/wireless/Config.in linux.dev/drivers/net/wireless/Config.in
22069 --- linux.old/drivers/net/wireless/Config.in 2005-11-07 23:12:51.258929250 +0100
22070 +++ linux.dev/drivers/net/wireless/Config.in 2005-11-07 21:57:07.941591750 +0100
22071 @@ -13,6 +13,7 @@
22072 fi
22073
22074 if [ "$CONFIG_PCI" = "y" ]; then
22075 + dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support' CONFIG_WL
22076 dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
22077 dep_tristate ' Hermes in TMD7160/NCP130 based PCI adaptor support (Pheecom WL-PCI etc.) (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
22078 dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
22079 diff -urN linux.old/drivers/net/wl/Makefile linux.dev/drivers/net/wl/Makefile
22080 --- linux.old/drivers/net/wl/Makefile 1970-01-01 01:00:00.000000000 +0100
22081 +++ linux.dev/drivers/net/wl/Makefile 2005-11-07 21:57:07.941591750 +0100
22082 @@ -0,0 +1,26 @@
22083 +#
22084 +# Makefile for the Broadcom wl driver
22085 +#
22086 +# Copyright 2004, Broadcom Corporation
22087 +# All Rights Reserved.
22088 +#
22089 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
22090 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
22091 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
22092 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22093 +#
22094 +# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
22095 +
22096 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include
22097 +
22098 +O_TARGET := wl.o
22099 +
22100 +obj-y := apsta_aeskeywrap.o apsta_aes.o apsta_bcmwpa.o apsta_d11ucode.o
22101 +obj-y += apsta_hmac.o apsta_md5.o apsta_passhash.o apsta_prf.o apsta_rc4.o
22102 +obj-y += apsta_rijndael-alg-fst.o apsta_sha1.o apsta_tkhash.o apsta_wlc_led.o
22103 +obj-y += apsta_wlc_phy.o apsta_wlc_rate.o apsta_wlc_security.o
22104 +obj-y += apsta_wlc_sup.o apsta_wlc_wet.o apsta_wl_linux.o apsta_wlc.o
22105 +
22106 +obj-m := $(O_TARGET)
22107 +
22108 +include $(TOPDIR)/Rules.make
22109 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
22110 --- linux.old/drivers/parport/Config.in 2005-11-07 23:12:51.306932250 +0100
22111 +++ linux.dev/drivers/parport/Config.in 2005-11-07 21:57:07.941591750 +0100
22112 @@ -11,6 +11,7 @@
22113 tristate 'Parallel port support' CONFIG_PARPORT
22114 if [ "$CONFIG_PARPORT" != "n" ]; then
22115 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
22116 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
22117 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
22118 if [ "$CONFIG_SERIAL" = "m" ]; then
22119 define_tristate CONFIG_PARPORT_PC_CML1 m
22120 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
22121 --- linux.old/drivers/parport/Makefile 2005-11-07 23:12:51.318933000 +0100
22122 +++ linux.dev/drivers/parport/Makefile 2005-11-07 21:57:07.941591750 +0100
22123 @@ -22,6 +22,7 @@
22124
22125 obj-$(CONFIG_PARPORT) += parport.o
22126 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
22127 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
22128 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
22129 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
22130 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
22131 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
22132 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
22133 +++ linux.dev/drivers/parport/parport_splink.c 2005-11-07 21:57:07.941591750 +0100
22134 @@ -0,0 +1,345 @@
22135 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
22136 + *
22137 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
22138 + * Based on parport_pc source
22139 + */
22140 +
22141 +#include <linux/config.h>
22142 +#include <linux/module.h>
22143 +#include <linux/init.h>
22144 +#include <linux/ioport.h>
22145 +#include <linux/kernel.h>
22146 +#include <linux/slab.h>
22147 +#include <linux/parport.h>
22148 +#include <linux/parport_pc.h>
22149 +
22150 +#define SPLINK_ADDRESS 0xBF800010
22151 +
22152 +#undef DEBUG
22153 +
22154 +#ifdef DEBUG
22155 +#define DPRINTK printk
22156 +#else
22157 +#define DPRINTK(stuff...)
22158 +#endif
22159 +
22160 +
22161 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
22162 + * it doesn't do any extra masking. */
22163 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
22164 + unsigned char mask,
22165 + unsigned char val)
22166 +{
22167 + struct parport_pc_private *priv = p->physport->private_data;
22168 + unsigned char *io = (unsigned char *) p->base;
22169 + unsigned char ctr = priv->ctr;
22170 +#ifdef DEBUG_PARPORT
22171 + printk (KERN_DEBUG
22172 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
22173 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
22174 +#endif
22175 + ctr = (ctr & ~mask) ^ val;
22176 + ctr &= priv->ctr_writable; /* only write writable bits. */
22177 + *(io+2) = ctr;
22178 + priv->ctr = ctr; /* Update soft copy */
22179 + return ctr;
22180 +}
22181 +
22182 +
22183 +
22184 +static void parport_splink_data_forward (struct parport *p)
22185 +{
22186 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
22187 + __parport_splink_frob_control (p, 0x20, 0);
22188 +}
22189 +
22190 +static void parport_splink_data_reverse (struct parport *p)
22191 +{
22192 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
22193 + __parport_splink_frob_control (p, 0x20, 0x20);
22194 +}
22195 +
22196 +/*
22197 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
22198 +{
22199 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
22200 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
22201 +}
22202 +*/
22203 +
22204 +static void parport_splink_enable_irq(struct parport *p)
22205 +{
22206 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
22207 + __parport_splink_frob_control (p, 0x10, 0x10);
22208 +}
22209 +
22210 +static void parport_splink_disable_irq(struct parport *p)
22211 +{
22212 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
22213 + __parport_splink_frob_control (p, 0x10, 0);
22214 +}
22215 +
22216 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
22217 +{
22218 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
22219 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
22220 + if (dev->irq_func &&
22221 + dev->port->irq != PARPORT_IRQ_NONE)
22222 + /* Set ackIntEn */
22223 + s->u.pc.ctr |= 0x10;
22224 +}
22225 +
22226 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
22227 +{
22228 + const struct parport_pc_private *priv = p->physport->private_data;
22229 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
22230 + s->u.pc.ctr = priv->ctr;
22231 +}
22232 +
22233 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
22234 +{
22235 + struct parport_pc_private *priv = p->physport->private_data;
22236 + unsigned char *io = (unsigned char *) p->base;
22237 + unsigned char ctr = s->u.pc.ctr;
22238 +
22239 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
22240 + *(io+2) = ctr;
22241 + priv->ctr = ctr;
22242 +}
22243 +
22244 +static void parport_splink_setup_interrupt(void) {
22245 + return;
22246 +}
22247 +
22248 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
22249 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
22250 + unsigned char *io = (unsigned char *) p->base;
22251 + *io = d;
22252 +}
22253 +
22254 +static unsigned char parport_splink_read_data(struct parport *p) {
22255 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
22256 + unsigned char *io = (unsigned char *) p->base;
22257 + return *io;
22258 +}
22259 +
22260 +static void parport_splink_write_control(struct parport *p, unsigned char d)
22261 +{
22262 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22263 + PARPORT_CONTROL_AUTOFD |
22264 + PARPORT_CONTROL_INIT |
22265 + PARPORT_CONTROL_SELECT);
22266 +
22267 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
22268 + /* Take this out when drivers have adapted to the newer interface. */
22269 + if (d & 0x20) {
22270 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
22271 + p->name, p->cad->name);
22272 + parport_splink_data_reverse (p);
22273 + }
22274 +
22275 + __parport_splink_frob_control (p, wm, d & wm);
22276 +}
22277 +
22278 +static unsigned char parport_splink_read_control(struct parport *p)
22279 +{
22280 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22281 + PARPORT_CONTROL_AUTOFD |
22282 + PARPORT_CONTROL_INIT |
22283 + PARPORT_CONTROL_SELECT);
22284 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
22285 + const struct parport_pc_private *priv = p->physport->private_data;
22286 + return priv->ctr & wm; /* Use soft copy */
22287 +}
22288 +
22289 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
22290 + unsigned char val)
22291 +{
22292 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22293 + PARPORT_CONTROL_AUTOFD |
22294 + PARPORT_CONTROL_INIT |
22295 + PARPORT_CONTROL_SELECT);
22296 +
22297 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
22298 + /* Take this out when drivers have adapted to the newer interface. */
22299 + if (mask & 0x20) {
22300 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
22301 + p->name, p->cad->name,
22302 + (val & 0x20) ? "reverse" : "forward");
22303 + if (val & 0x20)
22304 + parport_splink_data_reverse (p);
22305 + else
22306 + parport_splink_data_forward (p);
22307 + }
22308 +
22309 + /* Restrict mask and val to control lines. */
22310 + mask &= wm;
22311 + val &= wm;
22312 +
22313 + return __parport_splink_frob_control (p, mask, val);
22314 +}
22315 +
22316 +static unsigned char parport_splink_read_status(struct parport *p)
22317 +{
22318 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
22319 + unsigned char *io = (unsigned char *) p->base;
22320 + return *(io+1);
22321 +}
22322 +
22323 +static void parport_splink_inc_use_count(void)
22324 +{
22325 +#ifdef MODULE
22326 + MOD_INC_USE_COUNT;
22327 +#endif
22328 +}
22329 +
22330 +static void parport_splink_dec_use_count(void)
22331 +{
22332 +#ifdef MODULE
22333 + MOD_DEC_USE_COUNT;
22334 +#endif
22335 +}
22336 +
22337 +static struct parport_operations parport_splink_ops =
22338 +{
22339 + parport_splink_write_data,
22340 + parport_splink_read_data,
22341 +
22342 + parport_splink_write_control,
22343 + parport_splink_read_control,
22344 + parport_splink_frob_control,
22345 +
22346 + parport_splink_read_status,
22347 +
22348 + parport_splink_enable_irq,
22349 + parport_splink_disable_irq,
22350 +
22351 + parport_splink_data_forward,
22352 + parport_splink_data_reverse,
22353 +
22354 + parport_splink_init_state,
22355 + parport_splink_save_state,
22356 + parport_splink_restore_state,
22357 +
22358 + parport_splink_inc_use_count,
22359 + parport_splink_dec_use_count,
22360 +
22361 + parport_ieee1284_epp_write_data,
22362 + parport_ieee1284_epp_read_data,
22363 + parport_ieee1284_epp_write_addr,
22364 + parport_ieee1284_epp_read_addr,
22365 +
22366 + parport_ieee1284_ecp_write_data,
22367 + parport_ieee1284_ecp_read_data,
22368 + parport_ieee1284_ecp_write_addr,
22369 +
22370 + parport_ieee1284_write_compat,
22371 + parport_ieee1284_read_nibble,
22372 + parport_ieee1284_read_byte,
22373 +};
22374 +
22375 +/* --- Initialisation code -------------------------------- */
22376 +
22377 +static struct parport *parport_splink_probe_port (unsigned long int base)
22378 +{
22379 + struct parport_pc_private *priv;
22380 + struct parport_operations *ops;
22381 + struct parport *p;
22382 +
22383 + if (check_mem_region(base, 3)) {
22384 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
22385 + return NULL;
22386 + }
22387 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
22388 + if (!priv) {
22389 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
22390 + return NULL;
22391 + }
22392 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
22393 + if (!ops) {
22394 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
22395 + base);
22396 + kfree (priv);
22397 + return NULL;
22398 + }
22399 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
22400 + priv->ctr = 0xc;
22401 + priv->ctr_writable = 0xff;
22402 +
22403 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
22404 + PARPORT_DMA_NONE, ops))) {
22405 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
22406 + base);
22407 + kfree (priv);
22408 + kfree (ops);
22409 + return NULL;
22410 + }
22411 +
22412 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
22413 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
22414 + p->private_data = priv;
22415 +
22416 + parport_proc_register(p);
22417 + request_mem_region (p->base, 3, p->name);
22418 +
22419 + /* Done probing. Now put the port into a sensible start-up state. */
22420 + parport_splink_write_data(p, 0);
22421 + parport_splink_data_forward (p);
22422 +
22423 + /* Now that we've told the sharing engine about the port, and
22424 + found out its characteristics, let the high-level drivers
22425 + know about it. */
22426 + parport_announce_port (p);
22427 +
22428 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
22429 + base);
22430 + return p;
22431 +}
22432 +
22433 +static void parport_splink_unregister_port(struct parport *p) {
22434 + struct parport_pc_private *priv = p->private_data;
22435 + struct parport_operations *ops = p->ops;
22436 +
22437 + if (p->irq != PARPORT_IRQ_NONE)
22438 + free_irq(p->irq, p);
22439 + release_mem_region(p->base, 3);
22440 + parport_proc_unregister(p);
22441 + kfree (priv);
22442 + parport_unregister_port(p);
22443 + kfree (ops);
22444 +}
22445 +
22446 +
22447 +int parport_splink_init(void)
22448 +{
22449 + int ret;
22450 +
22451 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
22452 + parport_splink_setup_interrupt();
22453 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
22454 +
22455 + return ret;
22456 +}
22457 +
22458 +void parport_splink_cleanup(void) {
22459 + struct parport *p = parport_enumerate(), *tmp;
22460 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
22461 + if (p->size) {
22462 + if (p->modes & PARPORT_MODE_PCSPP) {
22463 + while(p) {
22464 + tmp = p->next;
22465 + parport_splink_unregister_port(p);
22466 + p = tmp;
22467 + }
22468 + }
22469 + }
22470 +}
22471 +
22472 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
22473 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
22474 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
22475 +MODULE_LICENSE("GPL");
22476 +
22477 +module_init(parport_splink_init)
22478 +module_exit(parport_splink_cleanup)
22479 +
22480 diff -urN linux.old/drivers/pcmcia/Makefile linux.dev/drivers/pcmcia/Makefile
22481 --- linux.old/drivers/pcmcia/Makefile 2005-11-07 23:12:51.350935000 +0100
22482 +++ linux.dev/drivers/pcmcia/Makefile 2005-11-07 21:57:07.941591750 +0100
22483 @@ -74,6 +74,10 @@
22484 au1000_ss-objs-$(CONFIG_MIPS_HYDROGEN3) += au1000_hydrogen3.o
22485 au1000_ss-objs-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o
22486
22487 +obj-$(CONFIG_PCMCIA_BCM4710) += bcm4710_ss.o
22488 +bcm4710_ss-objs := bcm4710_generic.o
22489 +bcm4710_ss-objs += bcm4710_pcmcia.o
22490 +
22491 obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o
22492 obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
22493 obj-$(CONFIG_PCMCIA_SIBYTE) += sibyte_generic.o
22494 @@ -112,5 +116,8 @@
22495 au1x00_ss.o: $(au1000_ss-objs-y)
22496 $(LD) -r -o $@ $(au1000_ss-objs-y)
22497
22498 +bcm4710_ss.o: $(bcm4710_ss-objs)
22499 + $(LD) -r -o $@ $(bcm4710_ss-objs)
22500 +
22501 yenta_socket.o: $(yenta_socket-objs)
22502 $(LD) $(LD_RFLAG) -r -o $@ $(yenta_socket-objs)
22503 diff -urN linux.old/drivers/pcmcia/bcm4710_generic.c linux.dev/drivers/pcmcia/bcm4710_generic.c
22504 --- linux.old/drivers/pcmcia/bcm4710_generic.c 1970-01-01 01:00:00.000000000 +0100
22505 +++ linux.dev/drivers/pcmcia/bcm4710_generic.c 2005-11-07 21:57:07.945592000 +0100
22506 @@ -0,0 +1,912 @@
22507 +/*
22508 + *
22509 + * bcm47xx pcmcia driver
22510 + *
22511 + * Copyright 2004, Broadcom Corporation
22512 + * All Rights Reserved.
22513 + *
22514 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
22515 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
22516 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
22517 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22518 + *
22519 + * Based on sa1100_generic.c from www.handhelds.org,
22520 + * and au1000_generic.c from oss.sgi.com.
22521 + *
22522 + * $Id: bcm4710_generic.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
22523 + */
22524 +#include <linux/module.h>
22525 +#include <linux/init.h>
22526 +#include <linux/config.h>
22527 +#include <linux/delay.h>
22528 +#include <linux/ioport.h>
22529 +#include <linux/kernel.h>
22530 +#include <linux/tqueue.h>
22531 +#include <linux/timer.h>
22532 +#include <linux/mm.h>
22533 +#include <linux/proc_fs.h>
22534 +#include <linux/version.h>
22535 +#include <linux/types.h>
22536 +#include <linux/vmalloc.h>
22537 +
22538 +#include <pcmcia/version.h>
22539 +#include <pcmcia/cs_types.h>
22540 +#include <pcmcia/cs.h>
22541 +#include <pcmcia/ss.h>
22542 +#include <pcmcia/bulkmem.h>
22543 +#include <pcmcia/cistpl.h>
22544 +#include <pcmcia/bus_ops.h>
22545 +#include "cs_internal.h"
22546 +
22547 +#include <asm/io.h>
22548 +#include <asm/irq.h>
22549 +#include <asm/system.h>
22550 +
22551 +#include <typedefs.h>
22552 +#include <bcm4710.h>
22553 +#include <sbextif.h>
22554 +
22555 +#include "bcm4710pcmcia.h"
22556 +
22557 +#ifdef PCMCIA_DEBUG
22558 +static int pc_debug = PCMCIA_DEBUG;
22559 +#endif
22560 +
22561 +MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm47xx Socket Controller");
22562 +
22563 +/* This structure maintains housekeeping state for each socket, such
22564 + * as the last known values of the card detect pins, or the Card Services
22565 + * callback value associated with the socket:
22566 + */
22567 +static struct bcm47xx_pcmcia_socket *pcmcia_socket;
22568 +static int socket_count;
22569 +
22570 +
22571 +/* Returned by the low-level PCMCIA interface: */
22572 +static struct pcmcia_low_level *pcmcia_low_level;
22573 +
22574 +/* Event poll timer structure */
22575 +static struct timer_list poll_timer;
22576 +
22577 +
22578 +/* Prototypes for routines which are used internally: */
22579 +
22580 +static int bcm47xx_pcmcia_driver_init(void);
22581 +static void bcm47xx_pcmcia_driver_shutdown(void);
22582 +static void bcm47xx_pcmcia_task_handler(void *data);
22583 +static void bcm47xx_pcmcia_poll_event(unsigned long data);
22584 +static void bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs);
22585 +static struct tq_struct bcm47xx_pcmcia_task;
22586 +
22587 +#ifdef CONFIG_PROC_FS
22588 +static int bcm47xx_pcmcia_proc_status(char *buf, char **start,
22589 + off_t pos, int count, int *eof, void *data);
22590 +#endif
22591 +
22592 +
22593 +/* Prototypes for operations which are exported to the
22594 + * in-kernel PCMCIA core:
22595 + */
22596 +
22597 +static int bcm47xx_pcmcia_init(unsigned int sock);
22598 +static int bcm47xx_pcmcia_suspend(unsigned int sock);
22599 +static int bcm47xx_pcmcia_register_callback(unsigned int sock,
22600 + void (*handler)(void *, unsigned int), void *info);
22601 +static int bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap);
22602 +static int bcm47xx_pcmcia_get_status(unsigned int sock, u_int *value);
22603 +static int bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state);
22604 +static int bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state);
22605 +static int bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *io);
22606 +static int bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *io);
22607 +static int bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *mem);
22608 +static int bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *mem);
22609 +#ifdef CONFIG_PROC_FS
22610 +static void bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base);
22611 +#endif
22612 +
22613 +static struct pccard_operations bcm47xx_pcmcia_operations = {
22614 + bcm47xx_pcmcia_init,
22615 + bcm47xx_pcmcia_suspend,
22616 + bcm47xx_pcmcia_register_callback,
22617 + bcm47xx_pcmcia_inquire_socket,
22618 + bcm47xx_pcmcia_get_status,
22619 + bcm47xx_pcmcia_get_socket,
22620 + bcm47xx_pcmcia_set_socket,
22621 + bcm47xx_pcmcia_get_io_map,
22622 + bcm47xx_pcmcia_set_io_map,
22623 + bcm47xx_pcmcia_get_mem_map,
22624 + bcm47xx_pcmcia_set_mem_map,
22625 +#ifdef CONFIG_PROC_FS
22626 + bcm47xx_pcmcia_proc_setup
22627 +#endif
22628 +};
22629 +
22630 +
22631 +/*
22632 + * bcm47xx_pcmcia_driver_init()
22633 + *
22634 + * This routine performs a basic sanity check to ensure that this
22635 + * kernel has been built with the appropriate board-specific low-level
22636 + * PCMCIA support, performs low-level PCMCIA initialization, registers
22637 + * this socket driver with Card Services, and then spawns the daemon
22638 + * thread which is the real workhorse of the socket driver.
22639 + *
22640 + * Please see linux/Documentation/arm/SA1100/PCMCIA for more information
22641 + * on the low-level kernel interface.
22642 + *
22643 + * Returns: 0 on success, -1 on error
22644 + */
22645 +static int __init bcm47xx_pcmcia_driver_init(void)
22646 +{
22647 + servinfo_t info;
22648 + struct pcmcia_init pcmcia_init;
22649 + struct pcmcia_state state;
22650 + unsigned int i;
22651 + unsigned long tmp;
22652 +
22653 +
22654 + printk("\nBCM47XX PCMCIA (CS release %s)\n", CS_RELEASE);
22655 +
22656 + CardServices(GetCardServicesInfo, &info);
22657 +
22658 + if (info.Revision != CS_RELEASE_CODE) {
22659 + printk(KERN_ERR "Card Services release codes do not match\n");
22660 + return -1;
22661 + }
22662 +
22663 +#ifdef CONFIG_BCM4710
22664 + pcmcia_low_level=&bcm4710_pcmcia_ops;
22665 +#else
22666 +#error Unsupported Broadcom BCM47XX board.
22667 +#endif
22668 +
22669 + pcmcia_init.handler=bcm47xx_pcmcia_interrupt;
22670 +
22671 + if ((socket_count = pcmcia_low_level->init(&pcmcia_init)) < 0) {
22672 + printk(KERN_ERR "Unable to initialize PCMCIA service.\n");
22673 + return -EIO;
22674 + } else {
22675 + printk("\t%d PCMCIA sockets initialized.\n", socket_count);
22676 + }
22677 +
22678 + pcmcia_socket =
22679 + kmalloc(sizeof(struct bcm47xx_pcmcia_socket) * socket_count,
22680 + GFP_KERNEL);
22681 + memset(pcmcia_socket, 0,
22682 + sizeof(struct bcm47xx_pcmcia_socket) * socket_count);
22683 + if (!pcmcia_socket) {
22684 + printk(KERN_ERR "Card Services can't get memory \n");
22685 + return -1;
22686 + }
22687 +
22688 + for (i = 0; i < socket_count; i++) {
22689 + if (pcmcia_low_level->socket_state(i, &state) < 0) {
22690 + printk(KERN_ERR "Unable to get PCMCIA status\n");
22691 + return -EIO;
22692 + }
22693 + pcmcia_socket[i].k_state = state;
22694 + pcmcia_socket[i].cs_state.csc_mask = SS_DETECT;
22695 +
22696 + if (i == 0) {
22697 + pcmcia_socket[i].virt_io =
22698 + (unsigned long)ioremap_nocache(EXTIF_PCMCIA_IOBASE(BCM4710_EXTIF), 0x1000);
22699 + /* Substract ioport base which gets added by in/out */
22700 + pcmcia_socket[i].virt_io -= mips_io_port_base;
22701 + pcmcia_socket[i].phys_attr =
22702 + (unsigned long)EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF);
22703 + pcmcia_socket[i].phys_mem =
22704 + (unsigned long)EXTIF_PCMCIA_MEMBASE(BCM4710_EXTIF);
22705 + } else {
22706 + printk(KERN_ERR "bcm4710: socket 1 not supported\n");
22707 + return 1;
22708 + }
22709 + }
22710 +
22711 + /* Only advertise as many sockets as we can detect: */
22712 + if (register_ss_entry(socket_count, &bcm47xx_pcmcia_operations) < 0) {
22713 + printk(KERN_ERR "Unable to register socket service routine\n");
22714 + return -ENXIO;
22715 + }
22716 +
22717 + /* Start the event poll timer.
22718 + * It will reschedule by itself afterwards.
22719 + */
22720 + bcm47xx_pcmcia_poll_event(0);
22721 +
22722 + DEBUG(1, "bcm4710: initialization complete\n");
22723 + return 0;
22724 +
22725 +}
22726 +
22727 +module_init(bcm47xx_pcmcia_driver_init);
22728 +
22729 +
22730 +/*
22731 + * bcm47xx_pcmcia_driver_shutdown()
22732 + *
22733 + * Invokes the low-level kernel service to free IRQs associated with this
22734 + * socket controller and reset GPIO edge detection.
22735 + */
22736 +static void __exit bcm47xx_pcmcia_driver_shutdown(void)
22737 +{
22738 + int i;
22739 +
22740 + del_timer_sync(&poll_timer);
22741 + unregister_ss_entry(&bcm47xx_pcmcia_operations);
22742 + pcmcia_low_level->shutdown();
22743 + flush_scheduled_tasks();
22744 + for (i = 0; i < socket_count; i++) {
22745 + if (pcmcia_socket[i].virt_io)
22746 + iounmap((void *)pcmcia_socket[i].virt_io);
22747 + if (pcmcia_socket[i].phys_attr)
22748 + iounmap((void *)pcmcia_socket[i].phys_attr);
22749 + if (pcmcia_socket[i].phys_mem)
22750 + iounmap((void *)pcmcia_socket[i].phys_mem);
22751 + }
22752 + DEBUG(1, "bcm4710: shutdown complete\n");
22753 +}
22754 +
22755 +module_exit(bcm47xx_pcmcia_driver_shutdown);
22756 +
22757 +/*
22758 + * bcm47xx_pcmcia_init()
22759 + * We perform all of the interesting initialization tasks in
22760 + * bcm47xx_pcmcia_driver_init().
22761 + *
22762 + * Returns: 0
22763 + */
22764 +static int bcm47xx_pcmcia_init(unsigned int sock)
22765 +{
22766 + DEBUG(1, "%s(): initializing socket %u\n", __FUNCTION__, sock);
22767 +
22768 + return 0;
22769 +}
22770 +
22771 +/*
22772 + * bcm47xx_pcmcia_suspend()
22773 + *
22774 + * We don't currently perform any actions on a suspend.
22775 + *
22776 + * Returns: 0
22777 + */
22778 +static int bcm47xx_pcmcia_suspend(unsigned int sock)
22779 +{
22780 + DEBUG(1, "%s(): suspending socket %u\n", __FUNCTION__, sock);
22781 +
22782 + return 0;
22783 +}
22784 +
22785 +
22786 +/*
22787 + * bcm47xx_pcmcia_events()
22788 + *
22789 + * Helper routine to generate a Card Services event mask based on
22790 + * state information obtained from the kernel low-level PCMCIA layer
22791 + * in a recent (and previous) sampling. Updates `prev_state'.
22792 + *
22793 + * Returns: an event mask for the given socket state.
22794 + */
22795 +static inline unsigned
22796 +bcm47xx_pcmcia_events(struct pcmcia_state *state,
22797 + struct pcmcia_state *prev_state,
22798 + unsigned int mask, unsigned int flags)
22799 +{
22800 + unsigned int events=0;
22801 +
22802 + if (state->bvd1 != prev_state->bvd1) {
22803 +
22804 + DEBUG(3, "%s(): card BVD1 value %u\n", __FUNCTION__, state->bvd1);
22805 +
22806 + events |= mask & (flags & SS_IOCARD) ? SS_STSCHG : SS_BATDEAD;
22807 + }
22808 +
22809 + if (state->bvd2 != prev_state->bvd2) {
22810 +
22811 + DEBUG(3, "%s(): card BVD2 value %u\n", __FUNCTION__, state->bvd2);
22812 +
22813 + events |= mask & (flags & SS_IOCARD) ? 0 : SS_BATWARN;
22814 + }
22815 +
22816 + if (state->detect != prev_state->detect) {
22817 +
22818 + DEBUG(3, "%s(): card detect value %u\n", __FUNCTION__, state->detect);
22819 +
22820 + events |= mask & SS_DETECT;
22821 + }
22822 +
22823 +
22824 + if (state->ready != prev_state->ready) {
22825 +
22826 + DEBUG(3, "%s(): card ready value %u\n", __FUNCTION__, state->ready);
22827 +
22828 + events |= mask & ((flags & SS_IOCARD) ? 0 : SS_READY);
22829 + }
22830 +
22831 + if (events != 0) {
22832 + DEBUG(2, "events: %s%s%s%s%s\n",
22833 + (events & SS_DETECT) ? "DETECT " : "",
22834 + (events & SS_READY) ? "READY " : "",
22835 + (events & SS_BATDEAD) ? "BATDEAD " : "",
22836 + (events & SS_BATWARN) ? "BATWARN " : "",
22837 + (events & SS_STSCHG) ? "STSCHG " : "");
22838 + }
22839 +
22840 + *prev_state=*state;
22841 + return events;
22842 +}
22843 +
22844 +
22845 +/*
22846 + * bcm47xx_pcmcia_task_handler()
22847 + *
22848 + * Processes serviceable socket events using the "eventd" thread context.
22849 + *
22850 + * Event processing (specifically, the invocation of the Card Services event
22851 + * callback) occurs in this thread rather than in the actual interrupt
22852 + * handler due to the use of scheduling operations in the PCMCIA core.
22853 + */
22854 +static void bcm47xx_pcmcia_task_handler(void *data)
22855 +{
22856 + struct pcmcia_state state;
22857 + int i, events, irq_status;
22858 +
22859 + DEBUG(4, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__);
22860 +
22861 + for (i = 0; i < socket_count; i++) {
22862 + if ((irq_status = pcmcia_low_level->socket_state(i, &state)) < 0)
22863 + printk(KERN_ERR "Error in kernel low-level PCMCIA service.\n");
22864 +
22865 + events = bcm47xx_pcmcia_events(&state,
22866 + &pcmcia_socket[i].k_state,
22867 + pcmcia_socket[i].cs_state.csc_mask,
22868 + pcmcia_socket[i].cs_state.flags);
22869 +
22870 + if (pcmcia_socket[i].handler != NULL) {
22871 + pcmcia_socket[i].handler(pcmcia_socket[i].handler_info,
22872 + events);
22873 + }
22874 + }
22875 +}
22876 +
22877 +static struct tq_struct bcm47xx_pcmcia_task = {
22878 + routine: bcm47xx_pcmcia_task_handler
22879 +};
22880 +
22881 +
22882 +/*
22883 + * bcm47xx_pcmcia_poll_event()
22884 + *
22885 + * Let's poll for events in addition to IRQs since IRQ only is unreliable...
22886 + */
22887 +static void bcm47xx_pcmcia_poll_event(unsigned long dummy)
22888 +{
22889 + DEBUG(4, "%s(): polling for events\n", __FUNCTION__);
22890 +
22891 + poll_timer.function = bcm47xx_pcmcia_poll_event;
22892 + poll_timer.expires = jiffies + BCM47XX_PCMCIA_POLL_PERIOD;
22893 + add_timer(&poll_timer);
22894 + schedule_task(&bcm47xx_pcmcia_task);
22895 +}
22896 +
22897 +
22898 +/*
22899 + * bcm47xx_pcmcia_interrupt()
22900 + *
22901 + * Service routine for socket driver interrupts (requested by the
22902 + * low-level PCMCIA init() operation via bcm47xx_pcmcia_thread()).
22903 + *
22904 + * The actual interrupt-servicing work is performed by
22905 + * bcm47xx_pcmcia_task(), largely because the Card Services event-
22906 + * handling code performs scheduling operations which cannot be
22907 + * executed from within an interrupt context.
22908 + */
22909 +static void
22910 +bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs)
22911 +{
22912 + DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq);
22913 + schedule_task(&bcm47xx_pcmcia_task);
22914 +}
22915 +
22916 +
22917 +/*
22918 + * bcm47xx_pcmcia_register_callback()
22919 + *
22920 + * Implements the register_callback() operation for the in-kernel
22921 + * PCMCIA service (formerly SS_RegisterCallback in Card Services). If
22922 + * the function pointer `handler' is not NULL, remember the callback
22923 + * location in the state for `sock', and increment the usage counter
22924 + * for the driver module. (The callback is invoked from the interrupt
22925 + * service routine, bcm47xx_pcmcia_interrupt(), to notify Card Services
22926 + * of interesting events.) Otherwise, clear the callback pointer in the
22927 + * socket state and decrement the module usage count.
22928 + *
22929 + * Returns: 0
22930 + */
22931 +static int
22932 +bcm47xx_pcmcia_register_callback(unsigned int sock,
22933 + void (*handler)(void *, unsigned int), void *info)
22934 +{
22935 + if (handler == NULL) {
22936 + pcmcia_socket[sock].handler = NULL;
22937 + MOD_DEC_USE_COUNT;
22938 + } else {
22939 + MOD_INC_USE_COUNT;
22940 + pcmcia_socket[sock].handler = handler;
22941 + pcmcia_socket[sock].handler_info = info;
22942 + }
22943 + return 0;
22944 +}
22945 +
22946 +
22947 +/*
22948 + * bcm47xx_pcmcia_inquire_socket()
22949 + *
22950 + * Implements the inquire_socket() operation for the in-kernel PCMCIA
22951 + * service (formerly SS_InquireSocket in Card Services). Of note is
22952 + * the setting of the SS_CAP_PAGE_REGS bit in the `features' field of
22953 + * `cap' to "trick" Card Services into tolerating large "I/O memory"
22954 + * addresses. Also set is SS_CAP_STATIC_MAP, which disables the memory
22955 + * resource database check. (Mapped memory is set up within the socket
22956 + * driver itself.)
22957 + *
22958 + * In conjunction with the STATIC_MAP capability is a new field,
22959 + * `io_offset', recommended by David Hinds. Rather than go through
22960 + * the SetIOMap interface (which is not quite suited for communicating
22961 + * window locations up from the socket driver), we just pass up
22962 + * an offset which is applied to client-requested base I/O addresses
22963 + * in alloc_io_space().
22964 + *
22965 + * Returns: 0 on success, -1 if no pin has been configured for `sock'
22966 + */
22967 +static int
22968 +bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap)
22969 +{
22970 + struct pcmcia_irq_info irq_info;
22971 +
22972 + if (sock >= socket_count) {
22973 + printk(KERN_ERR "bcm47xx: socket %u not configured\n", sock);
22974 + return -1;
22975 + }
22976 +
22977 + /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the
22978 + * force_low argument to validate_mem() in rsrc_mgr.c -- since in
22979 + * general, the mapped * addresses of the PCMCIA memory regions
22980 + * will not be within 0xffff, setting force_low would be
22981 + * undesirable.
22982 + *
22983 + * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory
22984 + * resource database; we instead pass up physical address ranges
22985 + * and allow other parts of Card Services to deal with remapping.
22986 + *
22987 + * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but
22988 + * not 32-bit CardBus devices.
22989 + */
22990 + cap->features = (SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD);
22991 +
22992 + irq_info.sock = sock;
22993 + irq_info.irq = -1;
22994 +
22995 + if (pcmcia_low_level->get_irq_info(&irq_info) < 0) {
22996 + printk(KERN_ERR "Error obtaining IRQ info socket %u\n", sock);
22997 + return -1;
22998 + }
22999 +
23000 + cap->irq_mask = 0;
23001 + cap->map_size = PAGE_SIZE;
23002 + cap->pci_irq = irq_info.irq;
23003 + cap->io_offset = pcmcia_socket[sock].virt_io;
23004 +
23005 + return 0;
23006 +}
23007 +
23008 +
23009 +/*
23010 + * bcm47xx_pcmcia_get_status()
23011 + *
23012 + * Implements the get_status() operation for the in-kernel PCMCIA
23013 + * service (formerly SS_GetStatus in Card Services). Essentially just
23014 + * fills in bits in `status' according to internal driver state or
23015 + * the value of the voltage detect chipselect register.
23016 + *
23017 + * As a debugging note, during card startup, the PCMCIA core issues
23018 + * three set_socket() commands in a row the first with RESET deasserted,
23019 + * the second with RESET asserted, and the last with RESET deasserted
23020 + * again. Following the third set_socket(), a get_status() command will
23021 + * be issued. The kernel is looking for the SS_READY flag (see
23022 + * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
23023 + *
23024 + * Returns: 0
23025 + */
23026 +static int
23027 +bcm47xx_pcmcia_get_status(unsigned int sock, unsigned int *status)
23028 +{
23029 + struct pcmcia_state state;
23030 +
23031 +
23032 + if ((pcmcia_low_level->socket_state(sock, &state)) < 0) {
23033 + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
23034 + return -1;
23035 + }
23036 +
23037 + pcmcia_socket[sock].k_state = state;
23038 +
23039 + *status = state.detect ? SS_DETECT : 0;
23040 +
23041 + *status |= state.ready ? SS_READY : 0;
23042 +
23043 + /* The power status of individual sockets is not available
23044 + * explicitly from the hardware, so we just remember the state
23045 + * and regurgitate it upon request:
23046 + */
23047 + *status |= pcmcia_socket[sock].cs_state.Vcc ? SS_POWERON : 0;
23048 +
23049 + if (pcmcia_socket[sock].cs_state.flags & SS_IOCARD)
23050 + *status |= state.bvd1 ? SS_STSCHG : 0;
23051 + else {
23052 + if (state.bvd1 == 0)
23053 + *status |= SS_BATDEAD;
23054 + else if (state.bvd2 == 0)
23055 + *status |= SS_BATWARN;
23056 + }
23057 +
23058 + *status |= state.vs_3v ? SS_3VCARD : 0;
23059 +
23060 + *status |= state.vs_Xv ? SS_XVCARD : 0;
23061 +
23062 + DEBUG(2, "\tstatus: %s%s%s%s%s%s%s%s\n",
23063 + (*status&SS_DETECT)?"DETECT ":"",
23064 + (*status&SS_READY)?"READY ":"",
23065 + (*status&SS_BATDEAD)?"BATDEAD ":"",
23066 + (*status&SS_BATWARN)?"BATWARN ":"",
23067 + (*status&SS_POWERON)?"POWERON ":"",
23068 + (*status&SS_STSCHG)?"STSCHG ":"",
23069 + (*status&SS_3VCARD)?"3VCARD ":"",
23070 + (*status&SS_XVCARD)?"XVCARD ":"");
23071 +
23072 + return 0;
23073 +}
23074 +
23075 +
23076 +/*
23077 + * bcm47xx_pcmcia_get_socket()
23078 + *
23079 + * Implements the get_socket() operation for the in-kernel PCMCIA
23080 + * service (formerly SS_GetSocket in Card Services). Not a very
23081 + * exciting routine.
23082 + *
23083 + * Returns: 0
23084 + */
23085 +static int
23086 +bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state)
23087 +{
23088 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
23089 +
23090 + /* This information was given to us in an earlier call to set_socket(),
23091 + * so we're just regurgitating it here:
23092 + */
23093 + *state = pcmcia_socket[sock].cs_state;
23094 + return 0;
23095 +}
23096 +
23097 +
23098 +/*
23099 + * bcm47xx_pcmcia_set_socket()
23100 + *
23101 + * Implements the set_socket() operation for the in-kernel PCMCIA
23102 + * service (formerly SS_SetSocket in Card Services). We more or
23103 + * less punt all of this work and let the kernel handle the details
23104 + * of power configuration, reset, &c. We also record the value of
23105 + * `state' in order to regurgitate it to the PCMCIA core later.
23106 + *
23107 + * Returns: 0
23108 + */
23109 +static int
23110 +bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state)
23111 +{
23112 + struct pcmcia_configure configure;
23113 +
23114 + DEBUG(2, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n"
23115 + "\tVcc %d Vpp %d irq %d\n",
23116 + (state->csc_mask == 0) ? "<NONE>" : "",
23117 + (state->csc_mask & SS_DETECT) ? "DETECT " : "",
23118 + (state->csc_mask & SS_READY) ? "READY " : "",
23119 + (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "",
23120 + (state->csc_mask & SS_BATWARN) ? "BATWARN " : "",
23121 + (state->csc_mask & SS_STSCHG) ? "STSCHG " : "",
23122 + (state->flags == 0) ? "<NONE>" : "",
23123 + (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "",
23124 + (state->flags & SS_IOCARD) ? "IOCARD " : "",
23125 + (state->flags & SS_RESET) ? "RESET " : "",
23126 + (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "",
23127 + (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "",
23128 + state->Vcc, state->Vpp, state->io_irq);
23129 +
23130 + configure.sock = sock;
23131 + configure.vcc = state->Vcc;
23132 + configure.vpp = state->Vpp;
23133 + configure.output = (state->flags & SS_OUTPUT_ENA) ? 1 : 0;
23134 + configure.speaker = (state->flags & SS_SPKR_ENA) ? 1 : 0;
23135 + configure.reset = (state->flags & SS_RESET) ? 1 : 0;
23136 +
23137 + if (pcmcia_low_level->configure_socket(&configure) < 0) {
23138 + printk(KERN_ERR "Unable to configure socket %u\n", sock);
23139 + return -1;
23140 + }
23141 +
23142 + pcmcia_socket[sock].cs_state = *state;
23143 + return 0;
23144 +}
23145 +
23146 +
23147 +/*
23148 + * bcm47xx_pcmcia_get_io_map()
23149 + *
23150 + * Implements the get_io_map() operation for the in-kernel PCMCIA
23151 + * service (formerly SS_GetIOMap in Card Services). Just returns an
23152 + * I/O map descriptor which was assigned earlier by a set_io_map().
23153 + *
23154 + * Returns: 0 on success, -1 if the map index was out of range
23155 + */
23156 +static int
23157 +bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *map)
23158 +{
23159 + DEBUG(2, "bcm47xx_pcmcia_get_io_map: sock %d\n", sock);
23160 +
23161 + if (map->map >= MAX_IO_WIN) {
23162 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23163 + __FUNCTION__, map->map);
23164 + return -1;
23165 + }
23166 +
23167 + *map = pcmcia_socket[sock].io_map[map->map];
23168 + return 0;
23169 +}
23170 +
23171 +
23172 +/*
23173 + * bcm47xx_pcmcia_set_io_map()
23174 + *
23175 + * Implements the set_io_map() operation for the in-kernel PCMCIA
23176 + * service (formerly SS_SetIOMap in Card Services). We configure
23177 + * the map speed as requested, but override the address ranges
23178 + * supplied by Card Services.
23179 + *
23180 + * Returns: 0 on success, -1 on error
23181 + */
23182 +int
23183 +bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *map)
23184 +{
23185 + unsigned int speed;
23186 + unsigned long start;
23187 +
23188 + DEBUG(2, "\tmap %u speed %u\n\tstart 0x%08lx stop 0x%08lx\n"
23189 + "\tflags: %s%s%s%s%s%s%s%s\n",
23190 + map->map, map->speed, map->start, map->stop,
23191 + (map->flags == 0) ? "<NONE>" : "",
23192 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
23193 + (map->flags & MAP_16BIT) ? "16BIT " : "",
23194 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
23195 + (map->flags & MAP_0WS) ? "0WS " : "",
23196 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
23197 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
23198 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
23199 +
23200 + if (map->map >= MAX_IO_WIN) {
23201 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23202 + __FUNCTION__, map->map);
23203 + return -1;
23204 + }
23205 +
23206 + if (map->flags & MAP_ACTIVE) {
23207 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_IO_SPEED;
23208 + pcmcia_socket[sock].speed_io = speed;
23209 + }
23210 +
23211 + start = map->start;
23212 +
23213 + if (map->stop == 1) {
23214 + map->stop = PAGE_SIZE - 1;
23215 + }
23216 +
23217 + map->start = pcmcia_socket[sock].virt_io;
23218 + map->stop = map->start + (map->stop - start);
23219 + pcmcia_socket[sock].io_map[map->map] = *map;
23220 + DEBUG(2, "set_io_map %d start %x stop %x\n",
23221 + map->map, map->start, map->stop);
23222 + return 0;
23223 +}
23224 +
23225 +
23226 +/*
23227 + * bcm47xx_pcmcia_get_mem_map()
23228 + *
23229 + * Implements the get_mem_map() operation for the in-kernel PCMCIA
23230 + * service (formerly SS_GetMemMap in Card Services). Just returns a
23231 + * memory map descriptor which was assigned earlier by a
23232 + * set_mem_map() request.
23233 + *
23234 + * Returns: 0 on success, -1 if the map index was out of range
23235 + */
23236 +static int
23237 +bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *map)
23238 +{
23239 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
23240 +
23241 + if (map->map >= MAX_WIN) {
23242 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23243 + __FUNCTION__, map->map);
23244 + return -1;
23245 + }
23246 +
23247 + *map = pcmcia_socket[sock].mem_map[map->map];
23248 + return 0;
23249 +}
23250 +
23251 +
23252 +/*
23253 + * bcm47xx_pcmcia_set_mem_map()
23254 + *
23255 + * Implements the set_mem_map() operation for the in-kernel PCMCIA
23256 + * service (formerly SS_SetMemMap in Card Services). We configure
23257 + * the map speed as requested, but override the address ranges
23258 + * supplied by Card Services.
23259 + *
23260 + * Returns: 0 on success, -1 on error
23261 + */
23262 +static int
23263 +bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *map)
23264 +{
23265 + unsigned int speed;
23266 + unsigned long start;
23267 + u_long flags;
23268 +
23269 + if (map->map >= MAX_WIN) {
23270 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23271 + __FUNCTION__, map->map);
23272 + return -1;
23273 + }
23274 +
23275 + DEBUG(2, "\tmap %u speed %u\n\tsys_start %#lx\n"
23276 + "\tsys_stop %#lx\n\tcard_start %#x\n"
23277 + "\tflags: %s%s%s%s%s%s%s%s\n",
23278 + map->map, map->speed, map->sys_start, map->sys_stop,
23279 + map->card_start, (map->flags == 0) ? "<NONE>" : "",
23280 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
23281 + (map->flags & MAP_16BIT) ? "16BIT " : "",
23282 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
23283 + (map->flags & MAP_0WS) ? "0WS " : "",
23284 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
23285 + (map->flags & MAP_ATTRIB) ? "ATTRIB " : "",
23286 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "");
23287 +
23288 + if (map->flags & MAP_ACTIVE) {
23289 + /* When clients issue RequestMap, the access speed is not always
23290 + * properly configured:
23291 + */
23292 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_MEM_SPEED;
23293 +
23294 + /* TBD */
23295 + if (map->flags & MAP_ATTRIB) {
23296 + pcmcia_socket[sock].speed_attr = speed;
23297 + } else {
23298 + pcmcia_socket[sock].speed_mem = speed;
23299 + }
23300 + }
23301 +
23302 + save_flags(flags);
23303 + cli();
23304 + start = map->sys_start;
23305 +
23306 + if (map->sys_stop == 0)
23307 + map->sys_stop = PAGE_SIZE - 1;
23308 +
23309 + if (map->flags & MAP_ATTRIB) {
23310 + map->sys_start = pcmcia_socket[sock].phys_attr +
23311 + map->card_start;
23312 + } else {
23313 + map->sys_start = pcmcia_socket[sock].phys_mem +
23314 + map->card_start;
23315 + }
23316 +
23317 + map->sys_stop = map->sys_start + (map->sys_stop - start);
23318 + pcmcia_socket[sock].mem_map[map->map] = *map;
23319 + restore_flags(flags);
23320 + DEBUG(2, "set_mem_map %d start %x stop %x card_start %x\n",
23321 + map->map, map->sys_start, map->sys_stop,
23322 + map->card_start);
23323 + return 0;
23324 +}
23325 +
23326 +
23327 +#if defined(CONFIG_PROC_FS)
23328 +
23329 +/*
23330 + * bcm47xx_pcmcia_proc_setup()
23331 + *
23332 + * Implements the proc_setup() operation for the in-kernel PCMCIA
23333 + * service (formerly SS_ProcSetup in Card Services).
23334 + *
23335 + * Returns: 0 on success, -1 on error
23336 + */
23337 +static void
23338 +bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base)
23339 +{
23340 + struct proc_dir_entry *entry;
23341 +
23342 + if ((entry = create_proc_entry("status", 0, base)) == NULL) {
23343 + printk(KERN_ERR "Unable to install \"status\" procfs entry\n");
23344 + return;
23345 + }
23346 +
23347 + entry->read_proc = bcm47xx_pcmcia_proc_status;
23348 + entry->data = (void *)sock;
23349 +}
23350 +
23351 +
23352 +/*
23353 + * bcm47xx_pcmcia_proc_status()
23354 + *
23355 + * Implements the /proc/bus/pccard/??/status file.
23356 + *
23357 + * Returns: the number of characters added to the buffer
23358 + */
23359 +static int
23360 +bcm47xx_pcmcia_proc_status(char *buf, char **start, off_t pos,
23361 + int count, int *eof, void *data)
23362 +{
23363 + char *p = buf;
23364 + unsigned int sock = (unsigned int)data;
23365 +
23366 + p += sprintf(p, "k_flags : %s%s%s%s%s%s%s\n",
23367 + pcmcia_socket[sock].k_state.detect ? "detect " : "",
23368 + pcmcia_socket[sock].k_state.ready ? "ready " : "",
23369 + pcmcia_socket[sock].k_state.bvd1 ? "bvd1 " : "",
23370 + pcmcia_socket[sock].k_state.bvd2 ? "bvd2 " : "",
23371 + pcmcia_socket[sock].k_state.wrprot ? "wrprot " : "",
23372 + pcmcia_socket[sock].k_state.vs_3v ? "vs_3v " : "",
23373 + pcmcia_socket[sock].k_state.vs_Xv ? "vs_Xv " : "");
23374 +
23375 + p += sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n",
23376 + pcmcia_socket[sock].k_state.detect ? "SS_DETECT " : "",
23377 + pcmcia_socket[sock].k_state.ready ? "SS_READY " : "",
23378 + pcmcia_socket[sock].cs_state.Vcc ? "SS_POWERON " : "",
23379 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ? "SS_IOCARD " : "",
23380 + (pcmcia_socket[sock].cs_state.flags & SS_IOCARD &&
23381 + pcmcia_socket[sock].k_state.bvd1) ? "SS_STSCHG " : "",
23382 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
23383 + (pcmcia_socket[sock].k_state.bvd1 == 0)) ? "SS_BATDEAD " : "",
23384 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
23385 + (pcmcia_socket[sock].k_state.bvd2 == 0)) ? "SS_BATWARN " : "",
23386 + pcmcia_socket[sock].k_state.vs_3v ? "SS_3VCARD " : "",
23387 + pcmcia_socket[sock].k_state.vs_Xv ? "SS_XVCARD " : "");
23388 +
23389 + p += sprintf(p, "mask : %s%s%s%s%s\n",
23390 + pcmcia_socket[sock].cs_state.csc_mask & SS_DETECT ? "SS_DETECT " : "",
23391 + pcmcia_socket[sock].cs_state.csc_mask & SS_READY ? "SS_READY " : "",
23392 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATDEAD ? "SS_BATDEAD " : "",
23393 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATWARN ? "SS_BATWARN " : "",
23394 + pcmcia_socket[sock].cs_state.csc_mask & SS_STSCHG ? "SS_STSCHG " : "");
23395 +
23396 + p += sprintf(p, "cs_flags : %s%s%s%s%s\n",
23397 + pcmcia_socket[sock].cs_state.flags & SS_PWR_AUTO ?
23398 + "SS_PWR_AUTO " : "",
23399 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ?
23400 + "SS_IOCARD " : "",
23401 + pcmcia_socket[sock].cs_state.flags & SS_RESET ?
23402 + "SS_RESET " : "",
23403 + pcmcia_socket[sock].cs_state.flags & SS_SPKR_ENA ?
23404 + "SS_SPKR_ENA " : "",
23405 + pcmcia_socket[sock].cs_state.flags & SS_OUTPUT_ENA ?
23406 + "SS_OUTPUT_ENA " : "");
23407 +
23408 + p += sprintf(p, "Vcc : %d\n", pcmcia_socket[sock].cs_state.Vcc);
23409 + p += sprintf(p, "Vpp : %d\n", pcmcia_socket[sock].cs_state.Vpp);
23410 + p += sprintf(p, "irq : %d\n", pcmcia_socket[sock].cs_state.io_irq);
23411 + p += sprintf(p, "I/O : %u\n", pcmcia_socket[sock].speed_io);
23412 + p += sprintf(p, "attribute: %u\n", pcmcia_socket[sock].speed_attr);
23413 + p += sprintf(p, "common : %u\n", pcmcia_socket[sock].speed_mem);
23414 + return p-buf;
23415 +}
23416 +
23417 +
23418 +#endif /* defined(CONFIG_PROC_FS) */
23419 diff -urN linux.old/drivers/pcmcia/bcm4710_pcmcia.c linux.dev/drivers/pcmcia/bcm4710_pcmcia.c
23420 --- linux.old/drivers/pcmcia/bcm4710_pcmcia.c 1970-01-01 01:00:00.000000000 +0100
23421 +++ linux.dev/drivers/pcmcia/bcm4710_pcmcia.c 2005-11-07 21:57:07.945592000 +0100
23422 @@ -0,0 +1,266 @@
23423 +/*
23424 + * BCM4710 specific pcmcia routines.
23425 + *
23426 + * Copyright 2004, Broadcom Corporation
23427 + * All Rights Reserved.
23428 + *
23429 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
23430 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
23431 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
23432 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
23433 + *
23434 + * $Id: bcm4710_pcmcia.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
23435 + */
23436 +#include <linux/module.h>
23437 +#include <linux/init.h>
23438 +#include <linux/config.h>
23439 +#include <linux/delay.h>
23440 +#include <linux/ioport.h>
23441 +#include <linux/kernel.h>
23442 +#include <linux/tqueue.h>
23443 +#include <linux/timer.h>
23444 +#include <linux/mm.h>
23445 +#include <linux/proc_fs.h>
23446 +#include <linux/version.h>
23447 +#include <linux/types.h>
23448 +#include <linux/pci.h>
23449 +
23450 +#include <pcmcia/version.h>
23451 +#include <pcmcia/cs_types.h>
23452 +#include <pcmcia/cs.h>
23453 +#include <pcmcia/ss.h>
23454 +#include <pcmcia/bulkmem.h>
23455 +#include <pcmcia/cistpl.h>
23456 +#include <pcmcia/bus_ops.h>
23457 +#include "cs_internal.h"
23458 +
23459 +#include <asm/io.h>
23460 +#include <asm/irq.h>
23461 +#include <asm/system.h>
23462 +
23463 +
23464 +#include <typedefs.h>
23465 +#include <bcmdevs.h>
23466 +#include <bcm4710.h>
23467 +#include <sbconfig.h>
23468 +#include <sbextif.h>
23469 +
23470 +#include "bcm4710pcmcia.h"
23471 +
23472 +/* Use a static var for irq dev_id */
23473 +static int bcm47xx_pcmcia_dev_id;
23474 +
23475 +/* Do we think we have a card or not? */
23476 +static int bcm47xx_pcmcia_present = 0;
23477 +
23478 +
23479 +static void bcm4710_pcmcia_reset(void)
23480 +{
23481 + extifregs_t *eir;
23482 + unsigned long s;
23483 + uint32 out0, out1, outen;
23484 +
23485 +
23486 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23487 +
23488 + save_and_cli(s);
23489 +
23490 + /* Use gpio7 to reset the pcmcia slot */
23491 + outen = readl(&eir->gpio[0].outen);
23492 + outen |= BCM47XX_PCMCIA_RESET;
23493 + out0 = readl(&eir->gpio[0].out);
23494 + out0 &= ~(BCM47XX_PCMCIA_RESET);
23495 + out1 = out0 | BCM47XX_PCMCIA_RESET;
23496 +
23497 + writel(out0, &eir->gpio[0].out);
23498 + writel(outen, &eir->gpio[0].outen);
23499 + mdelay(1);
23500 + writel(out1, &eir->gpio[0].out);
23501 + mdelay(1);
23502 + writel(out0, &eir->gpio[0].out);
23503 +
23504 + restore_flags(s);
23505 +}
23506 +
23507 +
23508 +static int bcm4710_pcmcia_init(struct pcmcia_init *init)
23509 +{
23510 + struct pci_dev *pdev;
23511 + extifregs_t *eir;
23512 + uint32 outen, intp, intm, tmp;
23513 + uint16 *attrsp;
23514 + int rc = 0, i;
23515 + extern unsigned long bcm4710_cpu_cycle;
23516 +
23517 +
23518 + if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_EXTIF, NULL))) {
23519 + printk(KERN_ERR "bcm4710_pcmcia: extif not found\n");
23520 + return -ENODEV;
23521 + }
23522 + eir = (extifregs_t *) ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
23523 +
23524 + /* Initialize the pcmcia i/f: 16bit no swap */
23525 + writel(CF_EM_PCMCIA | CF_DS | CF_EN, &eir->pcmcia_config);
23526 +
23527 +#ifdef notYet
23528 +
23529 + /* Set the timing for memory accesses */
23530 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23531 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23532 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23533 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23534 + writel(tmp, &eir->pcmcia_memwait); /* 0x01020a0c for a 100Mhz clock */
23535 +
23536 + /* Set the timing for I/O accesses */
23537 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23538 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23539 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23540 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23541 + writel(tmp, &eir->pcmcia_iowait); /* 0x01020a0c for a 100Mhz clock */
23542 +
23543 + /* Set the timing for attribute accesses */
23544 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23545 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23546 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23547 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23548 + writel(tmp, &eir->pcmcia_attrwait); /* 0x01020a0c for a 100Mhz clock */
23549 +
23550 +#endif
23551 + /* Make sure gpio0 and gpio5 are inputs */
23552 + outen = readl(&eir->gpio[0].outen);
23553 + outen &= ~(BCM47XX_PCMCIA_WP | BCM47XX_PCMCIA_STSCHG | BCM47XX_PCMCIA_RESET);
23554 + writel(outen, &eir->gpio[0].outen);
23555 +
23556 + /* Issue a reset to the pcmcia socket */
23557 + bcm4710_pcmcia_reset();
23558 +
23559 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
23560 + /* Setup gpio5 to be the STSCHG interrupt */
23561 + intp = readl(&eir->gpiointpolarity);
23562 + writel(intp | BCM47XX_PCMCIA_STSCHG, &eir->gpiointpolarity); /* Active low */
23563 + intm = readl(&eir->gpiointmask);
23564 + writel(intm | BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Enable it */
23565 +#endif
23566 +
23567 + DEBUG(2, "bcm4710_pcmcia after reset:\n");
23568 + DEBUG(2, "\textstatus\t= 0x%08x:\n", readl(&eir->extstatus));
23569 + DEBUG(2, "\tpcmcia_config\t= 0x%08x:\n", readl(&eir->pcmcia_config));
23570 + DEBUG(2, "\tpcmcia_memwait\t= 0x%08x:\n", readl(&eir->pcmcia_memwait));
23571 + DEBUG(2, "\tpcmcia_attrwait\t= 0x%08x:\n", readl(&eir->pcmcia_attrwait));
23572 + DEBUG(2, "\tpcmcia_iowait\t= 0x%08x:\n", readl(&eir->pcmcia_iowait));
23573 + DEBUG(2, "\tgpioin\t\t= 0x%08x:\n", readl(&eir->gpioin));
23574 + DEBUG(2, "\tgpio_outen0\t= 0x%08x:\n", readl(&eir->gpio[0].outen));
23575 + DEBUG(2, "\tgpio_out0\t= 0x%08x:\n", readl(&eir->gpio[0].out));
23576 + DEBUG(2, "\tgpiointpolarity\t= 0x%08x:\n", readl(&eir->gpiointpolarity));
23577 + DEBUG(2, "\tgpiointmask\t= 0x%08x:\n", readl(&eir->gpiointmask));
23578 +
23579 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
23580 + /* Request pcmcia interrupt */
23581 + rc = request_irq(BCM47XX_PCMCIA_IRQ, init->handler, SA_INTERRUPT,
23582 + "PCMCIA Interrupt", &bcm47xx_pcmcia_dev_id);
23583 +#endif
23584 +
23585 + attrsp = (uint16 *)ioremap_nocache(EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF), 0x1000);
23586 + tmp = readw(&attrsp[0]);
23587 + DEBUG(2, "\tattr[0] = 0x%04x\n", tmp);
23588 + if ((tmp == 0x7fff) || (tmp == 0x7f00)) {
23589 + bcm47xx_pcmcia_present = 0;
23590 + } else {
23591 + bcm47xx_pcmcia_present = 1;
23592 + }
23593 +
23594 + /* There's only one socket */
23595 + return 1;
23596 +}
23597 +
23598 +static int bcm4710_pcmcia_shutdown(void)
23599 +{
23600 + extifregs_t *eir;
23601 + uint32 intm;
23602 +
23603 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23604 +
23605 + /* Disable the pcmcia i/f */
23606 + writel(0, &eir->pcmcia_config);
23607 +
23608 + /* Reset gpio's */
23609 + intm = readl(&eir->gpiointmask);
23610 + writel(intm & ~BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Disable it */
23611 +
23612 + free_irq(BCM47XX_PCMCIA_IRQ, &bcm47xx_pcmcia_dev_id);
23613 +
23614 + return 0;
23615 +}
23616 +
23617 +static int
23618 +bcm4710_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
23619 +{
23620 + extifregs_t *eir;
23621 +
23622 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23623 +
23624 +
23625 + if (sock != 0) {
23626 + printk(KERN_ERR "bcm4710 socket_state bad sock %d\n", sock);
23627 + return -1;
23628 + }
23629 +
23630 + if (bcm47xx_pcmcia_present) {
23631 + state->detect = 1;
23632 + state->ready = 1;
23633 + state->bvd1 = 1;
23634 + state->bvd2 = 1;
23635 + state->wrprot = (readl(&eir->gpioin) & BCM47XX_PCMCIA_WP) == BCM47XX_PCMCIA_WP;
23636 + state->vs_3v = 0;
23637 + state->vs_Xv = 0;
23638 + } else {
23639 + state->detect = 0;
23640 + state->ready = 0;
23641 + }
23642 +
23643 + return 1;
23644 +}
23645 +
23646 +
23647 +static int bcm4710_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
23648 +{
23649 + if (info->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
23650 +
23651 + info->irq = BCM47XX_PCMCIA_IRQ;
23652 +
23653 + return 0;
23654 +}
23655 +
23656 +
23657 +static int
23658 +bcm4710_pcmcia_configure_socket(const struct pcmcia_configure *configure)
23659 +{
23660 + if (configure->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
23661 +
23662 +
23663 + DEBUG(2, "Vcc %dV Vpp %dV output %d speaker %d reset %d\n", configure->vcc,
23664 + configure->vpp, configure->output, configure->speaker, configure->reset);
23665 +
23666 + if ((configure->vcc != 50) || (configure->vpp != 50)) {
23667 + printk("%s: bad Vcc/Vpp (%d:%d)\n", __FUNCTION__, configure->vcc,
23668 + configure->vpp);
23669 + }
23670 +
23671 + if (configure->reset) {
23672 + /* Issue a reset to the pcmcia socket */
23673 + DEBUG(1, "%s: Reseting socket\n", __FUNCTION__);
23674 + bcm4710_pcmcia_reset();
23675 + }
23676 +
23677 +
23678 + return 0;
23679 +}
23680 +
23681 +struct pcmcia_low_level bcm4710_pcmcia_ops = {
23682 + bcm4710_pcmcia_init,
23683 + bcm4710_pcmcia_shutdown,
23684 + bcm4710_pcmcia_socket_state,
23685 + bcm4710_pcmcia_get_irq_info,
23686 + bcm4710_pcmcia_configure_socket
23687 +};
23688 +
23689 diff -urN linux.old/drivers/pcmcia/bcm4710pcmcia.h linux.dev/drivers/pcmcia/bcm4710pcmcia.h
23690 --- linux.old/drivers/pcmcia/bcm4710pcmcia.h 1970-01-01 01:00:00.000000000 +0100
23691 +++ linux.dev/drivers/pcmcia/bcm4710pcmcia.h 2005-11-07 21:57:07.945592000 +0100
23692 @@ -0,0 +1,118 @@
23693 +/*
23694 + *
23695 + * bcm47xx pcmcia driver
23696 + *
23697 + * Copyright 2004, Broadcom Corporation
23698 + * All Rights Reserved.
23699 + *
23700 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
23701 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
23702 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
23703 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
23704 + *
23705 + * Based on sa1100.h and include/asm-arm/arch-sa1100/pcmica.h
23706 + * from www.handhelds.org,
23707 + * and au1000_generic.c from oss.sgi.com.
23708 + *
23709 + * $Id: bcm4710pcmcia.h,v 1.1 2005/03/16 13:50:00 wbx Exp $
23710 + */
23711 +
23712 +#if !defined(_BCM4710PCMCIA_H)
23713 +#define _BCM4710PCMCIA_H
23714 +
23715 +#include <pcmcia/cs_types.h>
23716 +#include <pcmcia/ss.h>
23717 +#include <pcmcia/bulkmem.h>
23718 +#include <pcmcia/cistpl.h>
23719 +#include "cs_internal.h"
23720 +
23721 +
23722 +/* The 47xx can only support one socket */
23723 +#define BCM47XX_PCMCIA_MAX_SOCK 1
23724 +
23725 +/* In the bcm947xx gpio's are used for some pcmcia functions */
23726 +#define BCM47XX_PCMCIA_WP 0x01 /* Bit 0 is WP input */
23727 +#define BCM47XX_PCMCIA_STSCHG 0x20 /* Bit 5 is STSCHG input/interrupt */
23728 +#define BCM47XX_PCMCIA_RESET 0x80 /* Bit 7 is RESET */
23729 +
23730 +#define BCM47XX_PCMCIA_IRQ 2
23731 +
23732 +/* The socket driver actually works nicely in interrupt-driven form,
23733 + * so the (relatively infrequent) polling is "just to be sure."
23734 + */
23735 +#define BCM47XX_PCMCIA_POLL_PERIOD (2 * HZ)
23736 +
23737 +#define BCM47XX_PCMCIA_IO_SPEED (255)
23738 +#define BCM47XX_PCMCIA_MEM_SPEED (300)
23739 +
23740 +
23741 +struct pcmcia_state {
23742 + unsigned detect: 1,
23743 + ready: 1,
23744 + bvd1: 1,
23745 + bvd2: 1,
23746 + wrprot: 1,
23747 + vs_3v: 1,
23748 + vs_Xv: 1;
23749 +};
23750 +
23751 +
23752 +struct pcmcia_configure {
23753 + unsigned sock: 8,
23754 + vcc: 8,
23755 + vpp: 8,
23756 + output: 1,
23757 + speaker: 1,
23758 + reset: 1;
23759 +};
23760 +
23761 +struct pcmcia_irq_info {
23762 + unsigned int sock;
23763 + unsigned int irq;
23764 +};
23765 +
23766 +/* This structure encapsulates per-socket state which we might need to
23767 + * use when responding to a Card Services query of some kind.
23768 + */
23769 +struct bcm47xx_pcmcia_socket {
23770 + socket_state_t cs_state;
23771 + struct pcmcia_state k_state;
23772 + unsigned int irq;
23773 + void (*handler)(void *, unsigned int);
23774 + void *handler_info;
23775 + pccard_io_map io_map[MAX_IO_WIN];
23776 + pccard_mem_map mem_map[MAX_WIN];
23777 + ioaddr_t virt_io, phys_attr, phys_mem;
23778 + unsigned short speed_io, speed_attr, speed_mem;
23779 +};
23780 +
23781 +struct pcmcia_init {
23782 + void (*handler)(int irq, void *dev, struct pt_regs *regs);
23783 +};
23784 +
23785 +struct pcmcia_low_level {
23786 + int (*init)(struct pcmcia_init *);
23787 + int (*shutdown)(void);
23788 + int (*socket_state)(unsigned sock, struct pcmcia_state *);
23789 + int (*get_irq_info)(struct pcmcia_irq_info *);
23790 + int (*configure_socket)(const struct pcmcia_configure *);
23791 +};
23792 +
23793 +extern struct pcmcia_low_level bcm47xx_pcmcia_ops;
23794 +
23795 +/* I/O pins replacing memory pins
23796 + * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
23797 + *
23798 + * These signals change meaning when going from memory-only to
23799 + * memory-or-I/O interface:
23800 + */
23801 +#define iostschg bvd1
23802 +#define iospkr bvd2
23803 +
23804 +
23805 +/*
23806 + * Declaration for implementation specific low_level operations.
23807 + */
23808 +extern struct pcmcia_low_level bcm4710_pcmcia_ops;
23809 +
23810 +#endif /* !defined(_BCM4710PCMCIA_H) */
23811 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
23812 --- linux.old/include/asm-mips/bootinfo.h 2005-11-07 23:12:51.434940250 +0100
23813 +++ linux.dev/include/asm-mips/bootinfo.h 2005-11-07 21:57:07.945592000 +0100
23814 @@ -37,6 +37,7 @@
23815 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
23816 #define MACH_GROUP_LASAT 21
23817 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
23818 +#define MACH_GROUP_BRCM 23 /* Broadcom */
23819
23820 /*
23821 * Valid machtype values for group unknown (low order halfword of mips_machtype)
23822 @@ -197,6 +198,15 @@
23823 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
23824
23825 /*
23826 + * Valid machtypes for group Broadcom
23827 + */
23828 +#define MACH_BCM93725 0
23829 +#define MACH_BCM93725_VJ 1
23830 +#define MACH_BCM93730 2
23831 +#define MACH_BCM947XX 3
23832 +#define MACH_BCM933XX 4
23833 +
23834 +/*
23835 * Valid machtype for group TITAN
23836 */
23837 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
23838 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
23839 --- linux.old/include/asm-mips/cpu.h 2005-11-07 23:12:51.434940250 +0100
23840 +++ linux.dev/include/asm-mips/cpu.h 2005-11-07 21:57:07.965593250 +0100
23841 @@ -22,6 +22,11 @@
23842 spec.
23843 */
23844
23845 +#define PRID_COPT_MASK 0xff000000
23846 +#define PRID_COMP_MASK 0x00ff0000
23847 +#define PRID_IMP_MASK 0x0000ff00
23848 +#define PRID_REV_MASK 0x000000ff
23849 +
23850 #define PRID_COMP_LEGACY 0x000000
23851 #define PRID_COMP_MIPS 0x010000
23852 #define PRID_COMP_BROADCOM 0x020000
23853 @@ -58,6 +63,7 @@
23854 #define PRID_IMP_RM7000 0x2700
23855 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
23856 #define PRID_IMP_RM9000 0x3400
23857 +#define PRID_IMP_BCM4710 0x4000
23858 #define PRID_IMP_R5432 0x5400
23859 #define PRID_IMP_R5500 0x5500
23860 #define PRID_IMP_4KC 0x8000
23861 @@ -66,10 +72,16 @@
23862 #define PRID_IMP_4KEC 0x8400
23863 #define PRID_IMP_4KSC 0x8600
23864 #define PRID_IMP_25KF 0x8800
23865 +#define PRID_IMP_BCM3302 0x9000
23866 +#define PRID_IMP_BCM3303 0x9100
23867 #define PRID_IMP_24K 0x9300
23868
23869 #define PRID_IMP_UNKNOWN 0xff00
23870
23871 +#define BCM330X(id) \
23872 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
23873 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
23874 +
23875 /*
23876 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
23877 */
23878 @@ -174,7 +186,9 @@
23879 #define CPU_AU1550 57
23880 #define CPU_24K 58
23881 #define CPU_AU1200 59
23882 -#define CPU_LAST 59
23883 +#define CPU_BCM4710 60
23884 +#define CPU_BCM3302 61
23885 +#define CPU_LAST 61
23886
23887 /*
23888 * ISA Level encodings
23889 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
23890 --- linux.old/include/asm-mips/r4kcache.h 2005-11-07 23:12:51.438940500 +0100
23891 +++ linux.dev/include/asm-mips/r4kcache.h 2005-11-07 21:57:08.161605500 +0100
23892 @@ -658,4 +658,17 @@
23893 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
23894 }
23895
23896 +extern inline void fill_icache_line(unsigned long addr)
23897 +{
23898 + __asm__ __volatile__(
23899 + ".set noreorder\n\t"
23900 + ".set mips3\n\t"
23901 + "cache %1, (%0)\n\t"
23902 + ".set mips0\n\t"
23903 + ".set reorder"
23904 + :
23905 + : "r" (addr),
23906 + "i" (Fill));
23907 +}
23908 +
23909 #endif /* __ASM_R4KCACHE_H */
23910 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
23911 --- linux.old/include/asm-mips/serial.h 2005-11-07 23:12:51.442940750 +0100
23912 +++ linux.dev/include/asm-mips/serial.h 2005-11-07 21:57:07.993595000 +0100
23913 @@ -223,6 +223,13 @@
23914 #define TXX927_SERIAL_PORT_DEFNS
23915 #endif
23916
23917 +#ifdef CONFIG_BCM947XX
23918 +/* reserve 4 ports to be configured at runtime */
23919 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
23920 +#else
23921 +#define BCM947XX_SERIAL_PORT_DEFNS
23922 +#endif
23923 +
23924 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
23925 #define STD_SERIAL_PORT_DEFNS \
23926 /* UART CLK PORT IRQ FLAGS */ \
23927 @@ -470,6 +477,7 @@
23928 #define SERIAL_PORT_DFNS \
23929 ATLAS_SERIAL_PORT_DEFNS \
23930 AU1000_SERIAL_PORT_DEFNS \
23931 + BCM947XX_SERIAL_PORT_DEFNS \
23932 COBALT_SERIAL_PORT_DEFNS \
23933 DDB5477_SERIAL_PORT_DEFNS \
23934 EV96100_SERIAL_PORT_DEFNS \
23935 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
23936 --- linux.old/init/do_mounts.c 2005-11-07 23:12:51.458941750 +0100
23937 +++ linux.dev/init/do_mounts.c 2005-11-07 21:57:07.993595000 +0100
23938 @@ -254,7 +254,13 @@
23939 { "ftlb", 0x2c08 },
23940 { "ftlc", 0x2c10 },
23941 { "ftld", 0x2c18 },
23942 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
23943 { "mtdblock", 0x1f00 },
23944 + { "mtdblock0",0x1f00 },
23945 + { "mtdblock1",0x1f01 },
23946 + { "mtdblock2",0x1f02 },
23947 + { "mtdblock3",0x1f03 },
23948 +#endif
23949 { "nb", 0x2b00 },
23950 { NULL, 0 }
23951 };
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