8dd4e3ee107c4a74f7eaf642636368b42da2c4b5
[openwrt/svn-archive/archive.git] / openwrt / target / linux / linux-2.4 / patches / brcm / 001-bcm47xx.patch
1 diff -urN linux.old/Makefile linux.dev/Makefile
2 --- linux.old/Makefile 2005-08-26 13:41:41.689634168 +0200
3 +++ linux.dev/Makefile 2005-08-26 13:44:34.233403528 +0200
4 @@ -17,9 +17,9 @@
5 FINDHPATH = $(HPATH)/asm $(HPATH)/linux $(HPATH)/scsi $(HPATH)/net $(HPATH)/math-emu
6
7 HOSTCC = gcc
8 -HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
9 +HOSTCFLAGS = -Wall -Wstrict-prototypes -Os -fomit-frame-pointer
10
11 -CROSS_COMPILE =
12 +CROSS_COMPILE=
13
14 #
15 # Include the make variables (CC, etc...)
16 @@ -91,8 +91,10 @@
17
18 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
19
20 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
21 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
22 -fno-strict-aliasing -fno-common
23 +
24 +
25 ifndef CONFIG_FRAME_POINTER
26 CFLAGS += -fomit-frame-pointer
27 endif
28 @@ -354,7 +356,7 @@
29 @rm -f .ver1
30
31 include/linux/version.h: ./Makefile
32 - @expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
33 + @-expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
34 (echo KERNELRELEASE \"$(KERNELRELEASE)\" exceeds $(uts_len) characters >&2; false)
35 @echo \#define UTS_RELEASE \"$(KERNELRELEASE)\" > .ver
36 @echo \#define LINUX_VERSION_CODE `expr $(VERSION) \\* 65536 + $(PATCHLEVEL) \\* 256 + $(SUBLEVEL)` >> .ver
37 diff -urN linux.old/Rules.make linux.dev/Rules.make
38 --- linux.old/Rules.make 2005-11-07 23:12:50.538884250 +0100
39 +++ linux.dev/Rules.make 2005-11-07 21:57:07.837585250 +0100
40 @@ -176,7 +176,14 @@
41 _modinst__: dummy
42 ifneq "$(strip $(ALL_MOBJS))" ""
43 mkdir -p $(MODLIB)/kernel/$(MOD_DESTDIR)
44 - cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
45 + #@cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
46 + for f in $(ALL_MOBJS) ; do \
47 + $(OBJCOPY) -R __ksymtab -R .comment -R .note -x \
48 + `$(NM) $$f | cut -f3- -d' ' | sed -n \
49 + -e 's/__module_parm_\(.*\)/-K \1/p' \
50 + -e 's/__ks..tab_\(.*\)/-K \1/p'` \
51 + $$f $(MODLIB)/kernel/$(MOD_DESTDIR)$(MOD_TARGET)$$f; \
52 + done
53 endif
54
55 .PHONY: modules_install
56 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
57 --- linux.old/arch/mips/Makefile 2005-11-07 23:12:50.582887000 +0100
58 +++ linux.dev/arch/mips/Makefile 2005-11-07 21:57:08.537629000 +0100
59 @@ -46,10 +46,10 @@
60 GCCFLAGS := -I $(TOPDIR)/include/asm/gcc
61 GCCFLAGS += -G 0 -mno-abicalls -fno-pic -pipe
62 GCCFLAGS += $(call check_gcc, -finline-limit=100000,)
63 -LINKFLAGS += -G 0 -static -n
64 -MODFLAGS += -mlong-calls
65 +LINKFLAGS += -G 0 -static -n -nostdlib
66 +MODFLAGS += -mlong-calls -fno-common
67
68 -ifdef CONFIG_DEBUG_INFO
69 +ifdef CONFIG_REMOTE_DEBUG
70 GCCFLAGS += -g
71 ifdef CONFIG_SB1XXX_CORELIS
72 GCCFLAGS += -mno-sched-prolog -fno-omit-frame-pointer
73 @@ -71,13 +71,13 @@
74 set_gccflags = $(shell \
75 while :; do \
76 cpu=$(1); isa=-$(2); \
77 - for gcc_opt in -march= -mcpu=; do \
78 + for gcc_opt in -march= -mtune=; do \
79 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
80 -xc /dev/null > /dev/null 2>&1 && \
81 break 2; \
82 done; \
83 cpu=$(3); isa=-$(4); \
84 - for gcc_opt in -march= -mcpu=; do \
85 + for gcc_opt in -march= -mtune=; do \
86 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
87 -xc /dev/null > /dev/null 2>&1 && \
88 break 2; \
89 @@ -92,7 +92,7 @@
90 fi; \
91 gas_abi=-Wa,-32; gas_cpu=$$cpu; gas_isa=-Wa,$$isa; \
92 while :; do \
93 - for gas_opt in -Wa,-march= -Wa,-mcpu=; do \
94 + for gas_opt in -Wa,-march= -Wa,-mtune=; do \
95 $(CC) $$gas_abi $$gas_opt$$cpu $$gas_isa -Wa,-Z -c \
96 -o /dev/null -xassembler /dev/null > /dev/null 2>&1 && \
97 break 2; \
98 @@ -174,6 +174,7 @@
99 endif
100
101 AFLAGS += $(GCCFLAGS)
102 +ASFLAGS += $(GCCFLAGS)
103 CFLAGS += $(GCCFLAGS)
104
105 LD += -m $(ld-emul)
106 @@ -727,6 +728,19 @@
107 endif
108
109 #
110 +# Broadcom BCM947XX variants
111 +#
112 +ifdef CONFIG_BCM947XX
113 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
114 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
115 +LOADADDR := 0x80001000
116 +
117 +zImage: vmlinux
118 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
119 +export LOADADDR
120 +endif
121 +
122 +#
123 # Choosing incompatible machines durings configuration will result in
124 # error messages during linking. Select a default linkscript if
125 # none has been choosen above.
126 @@ -779,6 +793,7 @@
127 $(MAKE) -C arch/$(ARCH)/tools clean
128 $(MAKE) -C arch/mips/baget clean
129 $(MAKE) -C arch/mips/lasat clean
130 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
131
132 archmrproper:
133 @$(MAKEBOOT) mrproper
134 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
135 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
136 +++ linux.dev/arch/mips/bcm947xx/Makefile 2005-11-08 00:55:04.392074500 +0100
137 @@ -0,0 +1,15 @@
138 +#
139 +# Makefile for the BCM947xx specific kernel interface routines
140 +# under Linux.
141 +#
142 +
143 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
144 +
145 +O_TARGET := bcm947xx.o
146 +
147 +export-objs := nvram_linux.o setup.o
148 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
149 +obj-y += nvram.o nvram_linux.o sflash.o
150 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
151 +
152 +include $(TOPDIR)/Rules.make
153 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
154 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
155 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2005-11-07 21:57:07.841585500 +0100
156 @@ -0,0 +1,33 @@
157 +#
158 +# Makefile for Broadcom BCM947XX boards
159 +#
160 +# Copyright 2001-2003, Broadcom Corporation
161 +# All Rights Reserved.
162 +#
163 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
164 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
165 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
166 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
167 +#
168 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
169 +#
170 +
171 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
172 +SYSTEM ?= $(TOPDIR)/vmlinux
173 +
174 +all: vmlinuz
175 +
176 +# Don't build dependencies, this may die if $(CC) isn't gcc
177 +dep:
178 +
179 +# Create a gzipped version named vmlinuz for compatibility
180 +vmlinuz: piggy
181 + gzip -c9 $< > $@
182 +
183 +piggy: $(SYSTEM)
184 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
185 +
186 +mrproper: clean
187 +
188 +clean:
189 + rm -f vmlinuz piggy
190 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
191 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
192 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2005-11-07 21:57:07.841585500 +0100
193 @@ -0,0 +1,15 @@
194 +#
195 +# Makefile for the BCM947xx specific kernel interface routines
196 +# under Linux.
197 +#
198 +
199 +.S.s:
200 + $(CPP) $(AFLAGS) $< -o $*.s
201 +.S.o:
202 + $(CC) $(AFLAGS) -c $< -o $*.o
203 +
204 +O_TARGET := brcm.o
205 +
206 +obj-y := int-handler.o irq.o
207 +
208 +include $(TOPDIR)/Rules.make
209 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
210 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
211 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2005-11-07 21:57:07.841585500 +0100
212 @@ -0,0 +1,51 @@
213 +/*
214 + * Generic interrupt handler for Broadcom MIPS boards
215 + *
216 + * Copyright 2004, Broadcom Corporation
217 + * All Rights Reserved.
218 + *
219 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
220 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
221 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
222 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
223 + *
224 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
225 + */
226 +
227 +#include <linux/config.h>
228 +
229 +#include <asm/asm.h>
230 +#include <asm/mipsregs.h>
231 +#include <asm/regdef.h>
232 +#include <asm/stackframe.h>
233 +
234 +/*
235 + * MIPS IRQ Source
236 + * -------- ------
237 + * 0 Software (ignored)
238 + * 1 Software (ignored)
239 + * 2 Combined hardware interrupt (hw0)
240 + * 3 Hardware
241 + * 4 Hardware
242 + * 5 Hardware
243 + * 6 Hardware
244 + * 7 R4k timer
245 + */
246 +
247 + .text
248 + .set noreorder
249 + .set noat
250 + .align 5
251 + NESTED(brcmIRQ, PT_SIZE, sp)
252 + SAVE_ALL
253 + CLI
254 + .set at
255 + .set noreorder
256 +
257 + jal brcm_irq_dispatch
258 + move a0, sp
259 +
260 + j ret_from_irq
261 + nop
262 +
263 + END(brcmIRQ)
264 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
265 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
266 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2005-11-07 21:57:07.841585500 +0100
267 @@ -0,0 +1,130 @@
268 +/*
269 + * Generic interrupt control functions for Broadcom MIPS boards
270 + *
271 + * Copyright 2004, Broadcom Corporation
272 + * All Rights Reserved.
273 + *
274 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
275 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
276 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
277 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
278 + *
279 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
280 + */
281 +
282 +#include <linux/config.h>
283 +#include <linux/init.h>
284 +#include <linux/kernel.h>
285 +#include <linux/types.h>
286 +#include <linux/interrupt.h>
287 +#include <linux/irq.h>
288 +
289 +#include <asm/irq.h>
290 +#include <asm/mipsregs.h>
291 +#include <asm/gdb-stub.h>
292 +
293 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
294 +
295 +extern asmlinkage void brcmIRQ(void);
296 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
297 +
298 +void
299 +brcm_irq_dispatch(struct pt_regs *regs)
300 +{
301 + u32 cause;
302 +
303 + cause = read_c0_cause() &
304 + read_c0_status() &
305 + CAUSEF_IP;
306 +
307 +#ifdef CONFIG_KERNPROF
308 + change_c0_status(cause | 1, 1);
309 +#else
310 + clear_c0_status(cause);
311 +#endif
312 +
313 + if (cause & CAUSEF_IP7)
314 + do_IRQ(7, regs);
315 + if (cause & CAUSEF_IP2)
316 + do_IRQ(2, regs);
317 + if (cause & CAUSEF_IP3)
318 + do_IRQ(3, regs);
319 + if (cause & CAUSEF_IP4)
320 + do_IRQ(4, regs);
321 + if (cause & CAUSEF_IP5)
322 + do_IRQ(5, regs);
323 + if (cause & CAUSEF_IP6)
324 + do_IRQ(6, regs);
325 +}
326 +
327 +static void
328 +enable_brcm_irq(unsigned int irq)
329 +{
330 + if (irq < 8)
331 + set_c0_status(1 << (irq + 8));
332 + else
333 + set_c0_status(IE_IRQ0);
334 +}
335 +
336 +static void
337 +disable_brcm_irq(unsigned int irq)
338 +{
339 + if (irq < 8)
340 + clear_c0_status(1 << (irq + 8));
341 + else
342 + clear_c0_status(IE_IRQ0);
343 +}
344 +
345 +static void
346 +ack_brcm_irq(unsigned int irq)
347 +{
348 + /* Already done in brcm_irq_dispatch */
349 +}
350 +
351 +static unsigned int
352 +startup_brcm_irq(unsigned int irq)
353 +{
354 + enable_brcm_irq(irq);
355 +
356 + return 0; /* never anything pending */
357 +}
358 +
359 +static void
360 +end_brcm_irq(unsigned int irq)
361 +{
362 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
363 + enable_brcm_irq(irq);
364 +}
365 +
366 +static struct hw_interrupt_type brcm_irq_type = {
367 + typename: "MIPS",
368 + startup: startup_brcm_irq,
369 + shutdown: disable_brcm_irq,
370 + enable: enable_brcm_irq,
371 + disable: disable_brcm_irq,
372 + ack: ack_brcm_irq,
373 + end: end_brcm_irq,
374 + NULL
375 +};
376 +
377 +void __init
378 +init_IRQ(void)
379 +{
380 + int i;
381 +
382 + for (i = 0; i < NR_IRQS; i++) {
383 + irq_desc[i].status = IRQ_DISABLED;
384 + irq_desc[i].action = 0;
385 + irq_desc[i].depth = 1;
386 + irq_desc[i].handler = &brcm_irq_type;
387 + }
388 +
389 + set_except_vector(0, brcmIRQ);
390 + change_c0_status(ST0_IM, ALLINTS);
391 +
392 +#ifdef CONFIG_REMOTE_DEBUG
393 + printk("Breaking into debugger...\n");
394 + set_debug_traps();
395 + breakpoint();
396 +#endif
397 +}
398 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
399 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
400 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2005-11-07 23:58:34.968754500 +0100
401 @@ -0,0 +1,158 @@
402 +/*
403 + * GPIO char driver
404 + *
405 + * Copyright 2005, Broadcom Corporation
406 + * All Rights Reserved.
407 + *
408 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
409 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
410 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
411 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
412 + *
413 + * $Id$
414 + */
415 +
416 +#include <linux/module.h>
417 +#include <linux/init.h>
418 +#include <linux/fs.h>
419 +#include <linux/miscdevice.h>
420 +#include <asm/uaccess.h>
421 +
422 +#include <typedefs.h>
423 +#include <bcmutils.h>
424 +#include <sbutils.h>
425 +#include <bcmdevs.h>
426 +
427 +static sb_t *gpio_sbh;
428 +static int gpio_major;
429 +static devfs_handle_t gpio_dir;
430 +static struct {
431 + char *name;
432 + devfs_handle_t handle;
433 +} gpio_file[] = {
434 + { "in", NULL },
435 + { "out", NULL },
436 + { "outen", NULL },
437 + { "control", NULL }
438 +};
439 +
440 +static int
441 +gpio_open(struct inode *inode, struct file * file)
442 +{
443 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
444 + return -ENODEV;
445 +
446 + MOD_INC_USE_COUNT;
447 + return 0;
448 +}
449 +
450 +static int
451 +gpio_release(struct inode *inode, struct file * file)
452 +{
453 + MOD_DEC_USE_COUNT;
454 + return 0;
455 +}
456 +
457 +static ssize_t
458 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
459 +{
460 + u32 val;
461 +
462 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
463 + case 0:
464 + val = sb_gpioin(gpio_sbh);
465 + break;
466 + case 1:
467 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
468 + break;
469 + case 2:
470 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
471 + break;
472 + case 3:
473 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
474 + break;
475 + default:
476 + return -ENODEV;
477 + }
478 +
479 + if (put_user(val, (u32 *) buf))
480 + return -EFAULT;
481 +
482 + return sizeof(val);
483 +}
484 +
485 +static ssize_t
486 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
487 +{
488 + u32 val;
489 +
490 + if (get_user(val, (u32 *) buf))
491 + return -EFAULT;
492 +
493 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
494 + case 0:
495 + return -EACCES;
496 + case 1:
497 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
498 + break;
499 + case 2:
500 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
501 + break;
502 + case 3:
503 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
504 + break;
505 + default:
506 + return -ENODEV;
507 + }
508 +
509 + return sizeof(val);
510 +}
511 +
512 +static struct file_operations gpio_fops = {
513 + owner: THIS_MODULE,
514 + open: gpio_open,
515 + release: gpio_release,
516 + read: gpio_read,
517 + write: gpio_write,
518 +};
519 +
520 +static int __init
521 +gpio_init(void)
522 +{
523 + int i;
524 +
525 + if (!(gpio_sbh = sb_kattach()))
526 + return -ENODEV;
527 +
528 + sb_gpiosetcore(gpio_sbh);
529 +
530 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
531 + return gpio_major;
532 +
533 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
534 +
535 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
536 + gpio_file[i].handle = devfs_register(gpio_dir,
537 + gpio_file[i].name,
538 + DEVFS_FL_DEFAULT, gpio_major, i,
539 + S_IFCHR | S_IRUGO | S_IWUGO,
540 + &gpio_fops, NULL);
541 + }
542 +
543 + return 0;
544 +}
545 +
546 +static void __exit
547 +gpio_exit(void)
548 +{
549 + int i;
550 +
551 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
552 + devfs_unregister(gpio_file[i].handle);
553 + devfs_unregister(gpio_dir);
554 + devfs_unregister_chrdev(gpio_major, "gpio");
555 + sb_detach(gpio_sbh);
556 +}
557 +
558 +module_init(gpio_init);
559 +module_exit(gpio_exit);
560 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
561 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
562 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-11-07 22:51:38.772725750 +0100
563 @@ -0,0 +1,391 @@
564 +/*
565 + * Broadcom device-specific manifest constants.
566 + *
567 + * Copyright 2005, Broadcom Corporation
568 + * All Rights Reserved.
569 + *
570 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
571 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
572 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
573 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
574 + * $Id$
575 + */
576 +
577 +#ifndef _BCMDEVS_H
578 +#define _BCMDEVS_H
579 +
580 +
581 +/* Known PCI vendor Id's */
582 +#define VENDOR_EPIGRAM 0xfeda
583 +#define VENDOR_BROADCOM 0x14e4
584 +#define VENDOR_3COM 0x10b7
585 +#define VENDOR_NETGEAR 0x1385
586 +#define VENDOR_DIAMOND 0x1092
587 +#define VENDOR_DELL 0x1028
588 +#define VENDOR_HP 0x0e11
589 +#define VENDOR_APPLE 0x106b
590 +
591 +/* PCI Device Id's */
592 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
593 +#define BCM4211_DEVICE_ID 0x4211
594 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
595 +#define BCM4231_DEVICE_ID 0x4231
596 +
597 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
598 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
599 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
600 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
601 +
602 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
603 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
604 +
605 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
606 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
607 +
608 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
609 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
610 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
611 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
612 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
613 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
614 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
615 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
616 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
617 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
618 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
619 +
620 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
621 +
622 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
623 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
624 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
625 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
626 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
627 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
628 +
629 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
630 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
631 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
632 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
633 +
634 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
635 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
636 +
637 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
638 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
639 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
640 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
641 +
642 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
643 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
644 +#define BCM4306_D11G_ID2 0x4325
645 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
646 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
647 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
648 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
649 +
650 +#define BCM4309_PKG_ID 1 /* 4309 package id */
651 +
652 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
653 +#define BCM4303_PKG_ID 2 /* 4303 package id */
654 +
655 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
656 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
657 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
658 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
659 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
660 +
661 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
662 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
663 +
664 +
665 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
666 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
667 +
668 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
669 +
670 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
671 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
672 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
673 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
674 +
675 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
676 +
677 +/* Address map */
678 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
679 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
680 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
681 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
682 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
683 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
684 +
685 +/* Core register space */
686 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
687 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
688 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
689 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
690 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
691 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
692 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
693 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
694 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
695 +
696 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
697 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
698 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
699 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
700 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
701 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
702 +
703 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
704 +
705 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
706 +
707 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
708 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
709 +
710 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
711 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
712 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
713 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
714 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
715 +
716 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
717 +
718 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
719 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
720 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
721 +
722 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
723 +
724 +/* PCMCIA vendor Id's */
725 +
726 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
727 +
728 +/* SDIO vendor Id's */
729 +#define VENDOR_BROADCOM_SDIO 0x00BF
730 +
731 +
732 +/* boardflags */
733 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
734 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
735 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
736 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
737 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
738 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
739 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
740 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
741 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
742 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
743 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
744 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
745 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
746 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
747 +
748 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
749 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
750 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
751 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
752 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
753 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
754 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
755 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
756 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
757 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
758 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
759 +
760 +/* Bus types */
761 +#define SB_BUS 0 /* Silicon Backplane */
762 +#define PCI_BUS 1 /* PCI target */
763 +#define PCMCIA_BUS 2 /* PCMCIA target */
764 +#define SDIO_BUS 3 /* SDIO target */
765 +#define JTAG_BUS 4 /* JTAG */
766 +
767 +/* Allows optimization for single-bus support */
768 +#ifdef BCMBUSTYPE
769 +#define BUSTYPE(bus) (BCMBUSTYPE)
770 +#else
771 +#define BUSTYPE(bus) (bus)
772 +#endif
773 +
774 +/* power control defines */
775 +#define PLL_DELAY 150 /* us pll on delay */
776 +#define FREF_DELAY 200 /* us fref change delay */
777 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
778 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
779 +
780 +/* Reference Board Types */
781 +
782 +#define BU4710_BOARD 0x0400
783 +#define VSIM4710_BOARD 0x0401
784 +#define QT4710_BOARD 0x0402
785 +
786 +#define BU4610_BOARD 0x0403
787 +#define VSIM4610_BOARD 0x0404
788 +
789 +#define BU4307_BOARD 0x0405
790 +#define BCM94301CB_BOARD 0x0406
791 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
792 +#define BCM94301MP_BOARD 0x0407
793 +#define BCM94307MP_BOARD 0x0408
794 +#define BCMAP4307_BOARD 0x0409
795 +
796 +#define BU4309_BOARD 0x040a
797 +#define BCM94309CB_BOARD 0x040b
798 +#define BCM94309MP_BOARD 0x040c
799 +#define BCM4309AP_BOARD 0x040d
800 +
801 +#define BCM94302MP_BOARD 0x040e
802 +
803 +#define VSIM4310_BOARD 0x040f
804 +#define BU4711_BOARD 0x0410
805 +#define BCM94310U_BOARD 0x0411
806 +#define BCM94310AP_BOARD 0x0412
807 +#define BCM94310MP_BOARD 0x0414
808 +
809 +#define BU4306_BOARD 0x0416
810 +#define BCM94306CB_BOARD 0x0417
811 +#define BCM94306MP_BOARD 0x0418
812 +
813 +#define BCM94710D_BOARD 0x041a
814 +#define BCM94710R1_BOARD 0x041b
815 +#define BCM94710R4_BOARD 0x041c
816 +#define BCM94710AP_BOARD 0x041d
817 +
818 +
819 +#define BU2050_BOARD 0x041f
820 +
821 +
822 +#define BCM94309G_BOARD 0x0421
823 +
824 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
825 +
826 +#define BU4704_BOARD 0x0423
827 +#define BU4702_BOARD 0x0424
828 +
829 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
830 +
831 +#define BU4317_BOARD 0x0426
832 +
833 +
834 +#define BCM94702MN_BOARD 0x0428
835 +
836 +/* BCM4702 1U CompactPCI Board */
837 +#define BCM94702CPCI_BOARD 0x0429
838 +
839 +/* BCM4702 with BCM95380 VLAN Router */
840 +#define BCM95380RR_BOARD 0x042a
841 +
842 +/* cb4306 with SiGe PA */
843 +#define BCM94306CBSG_BOARD 0x042b
844 +
845 +/* mp4301 with 2050 radio */
846 +#define BCM94301MPL_BOARD 0x042c
847 +
848 +/* cb4306 with SiGe PA */
849 +#define PCSG94306_BOARD 0x042d
850 +
851 +/* bu4704 with sdram */
852 +#define BU4704SD_BOARD 0x042e
853 +
854 +/* Dual 11a/11g Router */
855 +#define BCM94704AGR_BOARD 0x042f
856 +
857 +/* 11a-only minipci */
858 +#define BCM94308MP_BOARD 0x0430
859 +
860 +
861 +
862 +/* BCM94317 boards */
863 +#define BCM94317CB_BOARD 0x0440
864 +#define BCM94317MP_BOARD 0x0441
865 +#define BCM94317PCMCIA_BOARD 0x0442
866 +#define BCM94317SDIO_BOARD 0x0443
867 +
868 +#define BU4712_BOARD 0x0444
869 +#define BU4712SD_BOARD 0x045d
870 +#define BU4712L_BOARD 0x045f
871 +
872 +/* BCM4712 boards */
873 +#define BCM94712AP_BOARD 0x0445
874 +#define BCM94712P_BOARD 0x0446
875 +
876 +/* BCM4318 boards */
877 +#define BU4318_BOARD 0x0447
878 +#define CB4318_BOARD 0x0448
879 +#define MPG4318_BOARD 0x0449
880 +#define MP4318_BOARD 0x044a
881 +#define SD4318_BOARD 0x044b
882 +
883 +/* BCM63XX boards */
884 +#define BCM96338_BOARD 0x6338
885 +#define BCM96345_BOARD 0x6345
886 +#define BCM96348_BOARD 0x6348
887 +
888 +/* Another mp4306 with SiGe */
889 +#define BCM94306P_BOARD 0x044c
890 +
891 +/* CF-like 4317 modules */
892 +#define BCM94317CF_BOARD 0x044d
893 +
894 +/* mp4303 */
895 +#define BCM94303MP_BOARD 0x044e
896 +
897 +/* mpsgh4306 */
898 +#define BCM94306MPSGH_BOARD 0x044f
899 +
900 +/* BRCM 4306 w/ Front End Modules */
901 +#define BCM94306MPM 0x0450
902 +#define BCM94306MPL 0x0453
903 +
904 +/* 4712agr */
905 +#define BCM94712AGR_BOARD 0x0451
906 +
907 +/* The real CF 4317 board */
908 +#define CFI4317_BOARD 0x0452
909 +
910 +/* pcmcia 4303 */
911 +#define PC4303_BOARD 0x0454
912 +
913 +/* 5350K */
914 +#define BCM95350K_BOARD 0x0455
915 +
916 +/* 5350R */
917 +#define BCM95350R_BOARD 0x0456
918 +
919 +/* 4306mplna */
920 +#define BCM94306MPLNA_BOARD 0x0457
921 +
922 +/* 4320 boards */
923 +#define BU4320_BOARD 0x0458
924 +#define BU4320S_BOARD 0x0459
925 +#define BCM94320PH_BOARD 0x045a
926 +
927 +/* 4306mph */
928 +#define BCM94306MPH_BOARD 0x045b
929 +
930 +/* 4306pciv */
931 +#define BCM94306PCIV_BOARD 0x045c
932 +
933 +#define BU4712SD_BOARD 0x045d
934 +
935 +#define BCM94320PFLSH_BOARD 0x045e
936 +
937 +#define BU4712L_BOARD 0x045f
938 +#define BCM94712LGR_BOARD 0x0460
939 +#define BCM94320R_BOARD 0x0461
940 +
941 +#define BU5352_BOARD 0x0462
942 +
943 +#define BCM94318MPGH_BOARD 0x0463
944 +
945 +
946 +#define BCM95352GR_BOARD 0x0467
947 +
948 +/* bcm95351agr */
949 +#define BCM95351AGR_BOARD 0x0470
950 +
951 +/* # of GPIO pins */
952 +#define GPIO_NUMPINS 16
953 +
954 +#endif /* _BCMDEVS_H */
955 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
956 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
957 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-11-07 22:51:38.772725750 +0100
958 @@ -0,0 +1,152 @@
959 +/*
960 + * local version of endian.h - byte order defines
961 + *
962 + * Copyright 2005, Broadcom Corporation
963 + * All Rights Reserved.
964 + *
965 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
966 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
967 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
968 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
969 + *
970 + * $Id$
971 +*/
972 +
973 +#ifndef _BCMENDIAN_H_
974 +#define _BCMENDIAN_H_
975 +
976 +#include <typedefs.h>
977 +
978 +/* Byte swap a 16 bit value */
979 +#define BCMSWAP16(val) \
980 + ((uint16)( \
981 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
982 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
983 +
984 +/* Byte swap a 32 bit value */
985 +#define BCMSWAP32(val) \
986 + ((uint32)( \
987 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
988 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
989 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
990 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
991 +
992 +/* 2 Byte swap a 32 bit value */
993 +#define BCMSWAP32BY16(val) \
994 + ((uint32)( \
995 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
996 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
997 +
998 +
999 +static INLINE uint16
1000 +bcmswap16(uint16 val)
1001 +{
1002 + return BCMSWAP16(val);
1003 +}
1004 +
1005 +static INLINE uint32
1006 +bcmswap32(uint32 val)
1007 +{
1008 + return BCMSWAP32(val);
1009 +}
1010 +
1011 +static INLINE uint32
1012 +bcmswap32by16(uint32 val)
1013 +{
1014 + return BCMSWAP32BY16(val);
1015 +}
1016 +
1017 +/* buf - start of buffer of shorts to swap */
1018 +/* len - byte length of buffer */
1019 +static INLINE void
1020 +bcmswap16_buf(uint16 *buf, uint len)
1021 +{
1022 + len = len/2;
1023 +
1024 + while(len--){
1025 + *buf = bcmswap16(*buf);
1026 + buf++;
1027 + }
1028 +}
1029 +
1030 +#ifndef hton16
1031 +#ifndef IL_BIGENDIAN
1032 +#define HTON16(i) BCMSWAP16(i)
1033 +#define hton16(i) bcmswap16(i)
1034 +#define hton32(i) bcmswap32(i)
1035 +#define ntoh16(i) bcmswap16(i)
1036 +#define ntoh32(i) bcmswap32(i)
1037 +#define ltoh16(i) (i)
1038 +#define ltoh32(i) (i)
1039 +#define htol16(i) (i)
1040 +#define htol32(i) (i)
1041 +#else
1042 +#define HTON16(i) (i)
1043 +#define hton16(i) (i)
1044 +#define hton32(i) (i)
1045 +#define ntoh16(i) (i)
1046 +#define ntoh32(i) (i)
1047 +#define ltoh16(i) bcmswap16(i)
1048 +#define ltoh32(i) bcmswap32(i)
1049 +#define htol16(i) bcmswap16(i)
1050 +#define htol32(i) bcmswap32(i)
1051 +#endif
1052 +#endif
1053 +
1054 +#ifndef IL_BIGENDIAN
1055 +#define ltoh16_buf(buf, i)
1056 +#define htol16_buf(buf, i)
1057 +#else
1058 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1059 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1060 +#endif
1061 +
1062 +/*
1063 +* load 16-bit value from unaligned little endian byte array.
1064 +*/
1065 +static INLINE uint16
1066 +ltoh16_ua(uint8 *bytes)
1067 +{
1068 + return (bytes[1]<<8)+bytes[0];
1069 +}
1070 +
1071 +/*
1072 +* load 32-bit value from unaligned little endian byte array.
1073 +*/
1074 +static INLINE uint32
1075 +ltoh32_ua(uint8 *bytes)
1076 +{
1077 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
1078 +}
1079 +
1080 +/*
1081 +* load 16-bit value from unaligned big(network) endian byte array.
1082 +*/
1083 +static INLINE uint16
1084 +ntoh16_ua(uint8 *bytes)
1085 +{
1086 + return (bytes[0]<<8)+bytes[1];
1087 +}
1088 +
1089 +/*
1090 +* load 32-bit value from unaligned big(network) endian byte array.
1091 +*/
1092 +static INLINE uint32
1093 +ntoh32_ua(uint8 *bytes)
1094 +{
1095 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
1096 +}
1097 +
1098 +#define ltoh_ua(ptr) ( \
1099 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1100 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
1101 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
1102 +)
1103 +
1104 +#define ntoh_ua(ptr) ( \
1105 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1106 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
1107 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
1108 +)
1109 +
1110 +#endif /* _BCMENDIAN_H_ */
1111 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h
1112 --- linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
1113 +++ linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-11-07 22:51:38.772725750 +0100
1114 @@ -0,0 +1,229 @@
1115 +/*
1116 + * Hardware-specific definitions for
1117 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
1118 + *
1119 + * Copyright 2005, Broadcom Corporation
1120 + * All Rights Reserved.
1121 + *
1122 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1123 + * the contents of this file may not be disclosed to third parties, copied
1124 + * or duplicated in any form, in whole or in part, without the prior
1125 + * written permission of Broadcom Corporation.
1126 + * $Id$
1127 + */
1128 +
1129 +#ifndef _bcmenet_47xx_h_
1130 +#define _bcmenet_47xx_h_
1131 +
1132 +#include <bcmenetmib.h>
1133 +#include <bcmenetrxh.h>
1134 +#include <bcmenetphy.h>
1135 +
1136 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
1137 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
1138 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
1139 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
1140 +
1141 +/* power management event wakeup pattern constants */
1142 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
1143 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
1144 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
1145 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
1146 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
1147 +
1148 +/* cpp contortions to concatenate w/arg prescan */
1149 +#ifndef PAD
1150 +#define _PADLINE(line) pad ## line
1151 +#define _XSTR(line) _PADLINE(line)
1152 +#define PAD _XSTR(__LINE__)
1153 +#endif /* PAD */
1154 +
1155 +/*
1156 + * Host Interface Registers
1157 + */
1158 +typedef volatile struct _bcmenettregs {
1159 + /* Device and Power Control */
1160 + uint32 devcontrol;
1161 + uint32 PAD[2];
1162 + uint32 biststatus;
1163 + uint32 wakeuplength;
1164 + uint32 PAD[3];
1165 +
1166 + /* Interrupt Control */
1167 + uint32 intstatus;
1168 + uint32 intmask;
1169 + uint32 gptimer;
1170 + uint32 PAD[23];
1171 +
1172 + /* Ethernet MAC Address Filtering Control */
1173 + uint32 PAD[2];
1174 + uint32 enetftaddr;
1175 + uint32 enetftdata;
1176 + uint32 PAD[2];
1177 +
1178 + /* Ethernet MAC Control */
1179 + uint32 emactxmaxburstlen;
1180 + uint32 emacrxmaxburstlen;
1181 + uint32 emaccontrol;
1182 + uint32 emacflowcontrol;
1183 +
1184 + uint32 PAD[20];
1185 +
1186 + /* DMA Lazy Interrupt Control */
1187 + uint32 intrecvlazy;
1188 + uint32 PAD[63];
1189 +
1190 + /* DMA engine */
1191 + dma32regp_t dmaregs;
1192 + dma32diag_t dmafifo;
1193 + uint32 PAD[116];
1194 +
1195 + /* EMAC Registers */
1196 + uint32 rxconfig;
1197 + uint32 rxmaxlength;
1198 + uint32 txmaxlength;
1199 + uint32 PAD;
1200 + uint32 mdiocontrol;
1201 + uint32 mdiodata;
1202 + uint32 emacintmask;
1203 + uint32 emacintstatus;
1204 + uint32 camdatalo;
1205 + uint32 camdatahi;
1206 + uint32 camcontrol;
1207 + uint32 enetcontrol;
1208 + uint32 txcontrol;
1209 + uint32 txwatermark;
1210 + uint32 mibcontrol;
1211 + uint32 PAD[49];
1212 +
1213 + /* EMAC MIB counters */
1214 + bcmenetmib_t mib;
1215 +
1216 + uint32 PAD[585];
1217 +
1218 + /* Sonics SiliconBackplane config registers */
1219 + sbconfig_t sbconfig;
1220 +} bcmenetregs_t;
1221 +
1222 +/* device control */
1223 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
1224 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
1225 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
1226 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
1227 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
1228 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
1229 +#define DC_PA_SHIFT 18
1230 +#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
1231 +#define DC_FS_SHIFT 23
1232 +#define DC_FS_4K 0 /* 4Kbytes */
1233 +#define DC_FS_512 1 /* 512bytes */
1234 +
1235 +/* wakeup length */
1236 +#define WL_P0_MASK 0x7f /* pattern 0 */
1237 +#define WL_D0 ((uint32)1 << 7)
1238 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
1239 +#define WL_P1_SHIFT 8
1240 +#define WL_D1 ((uint32)1 << 15)
1241 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
1242 +#define WL_P2_SHIFT 16
1243 +#define WL_D2 ((uint32)1 << 23)
1244 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
1245 +#define WL_P3_SHIFT 24
1246 +#define WL_D3 ((uint32)1 << 31)
1247 +
1248 +/* intstatus and intmask */
1249 +#define I_PME ((uint32)1 << 6) /* power management event */
1250 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
1251 +#define I_PC ((uint32)1 << 10) /* descriptor error */
1252 +#define I_PD ((uint32)1 << 11) /* data error */
1253 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
1254 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
1255 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
1256 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
1257 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
1258 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
1259 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
1260 +#define I_MW ((uint32)1 << 27) /* mii write */
1261 +#define I_MR ((uint32)1 << 28) /* mii read */
1262 +
1263 +/* emaccontrol */
1264 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
1265 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
1266 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
1267 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
1268 +#define EMC_LC_SHIFT 5
1269 +
1270 +/* emacflowcontrol */
1271 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
1272 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
1273 +
1274 +/* interrupt receive lazy */
1275 +#define IRL_TO_MASK 0x00ffffff /* timeout */
1276 +#define IRL_FC_MASK 0xff000000 /* frame count */
1277 +#define IRL_FC_SHIFT 24 /* frame count */
1278 +
1279 +/* emac receive config */
1280 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
1281 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
1282 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
1283 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
1284 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
1285 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
1286 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
1287 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
1288 +#define ERC_CA ((uint32)1 << 8) /* cam absent */
1289 +
1290 +/* emac mdio control */
1291 +#define MC_MF_MASK 0x7f /* mdc frequency */
1292 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
1293 +
1294 +/* emac mdio data */
1295 +#define MD_DATA_MASK 0xffff /* r/w data */
1296 +#define MD_TA_MASK 0x30000 /* turnaround value */
1297 +#define MD_TA_SHIFT 16
1298 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
1299 +#define MD_RA_MASK 0x7c0000 /* register address */
1300 +#define MD_RA_SHIFT 18
1301 +#define MD_PMD_MASK 0xf800000 /* physical media device */
1302 +#define MD_PMD_SHIFT 23
1303 +#define MD_OP_MASK 0x30000000 /* opcode */
1304 +#define MD_OP_SHIFT 28
1305 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
1306 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
1307 +#define MD_SB_MASK 0xc0000000 /* start bits */
1308 +#define MD_SB_SHIFT 30
1309 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
1310 +
1311 +/* emac intstatus and intmask */
1312 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
1313 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
1314 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
1315 +
1316 +/* emac cam data high */
1317 +#define CD_V ((uint32)1 << 16) /* valid bit */
1318 +
1319 +/* emac cam control */
1320 +#define CC_CE ((uint32)1 << 0) /* cam enable */
1321 +#define CC_MS ((uint32)1 << 1) /* mask select */
1322 +#define CC_RD ((uint32)1 << 2) /* read */
1323 +#define CC_WR ((uint32)1 << 3) /* write */
1324 +#define CC_INDEX_MASK 0x3f0000 /* index */
1325 +#define CC_INDEX_SHIFT 16
1326 +#define CC_CB ((uint32)1 << 31) /* cam busy */
1327 +
1328 +/* emac ethernet control */
1329 +#define EC_EE ((uint32)1 << 0) /* emac enable */
1330 +#define EC_ED ((uint32)1 << 1) /* emac disable */
1331 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
1332 +#define EC_EP ((uint32)1 << 3) /* external phy select */
1333 +
1334 +/* emac transmit control */
1335 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
1336 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
1337 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
1338 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
1339 +
1340 +/* emac mib control */
1341 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
1342 +
1343 +#endif /* _bcmenet_47xx_h_ */
1344 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetmib.h linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h
1345 --- linux.old/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
1346 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h 2005-11-07 21:57:07.845585750 +0100
1347 @@ -0,0 +1,81 @@
1348 +/*
1349 + * Hardware-specific MIB definition for
1350 + * Broadcom Home Networking Division
1351 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1352 + *
1353 + * Copyright 2005, Broadcom Corporation
1354 + * All Rights Reserved.
1355 + *
1356 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1357 + * the contents of this file may not be disclosed to third parties, copied
1358 + * or duplicated in any form, in whole or in part, without the prior
1359 + * written permission of Broadcom Corporation.
1360 + * $Id$
1361 + */
1362 +
1363 +#ifndef _bcmenetmib_h_
1364 +#define _bcmenetmib_h_
1365 +
1366 +/* cpp contortions to concatenate w/arg prescan */
1367 +#ifndef PAD
1368 +#define _PADLINE(line) pad ## line
1369 +#define _XSTR(line) _PADLINE(line)
1370 +#define PAD _XSTR(__LINE__)
1371 +#endif /* PAD */
1372 +
1373 +/*
1374 + * EMAC MIB Registers
1375 + */
1376 +typedef volatile struct {
1377 + uint32 tx_good_octets;
1378 + uint32 tx_good_pkts;
1379 + uint32 tx_octets;
1380 + uint32 tx_pkts;
1381 + uint32 tx_broadcast_pkts;
1382 + uint32 tx_multicast_pkts;
1383 + uint32 tx_len_64;
1384 + uint32 tx_len_65_to_127;
1385 + uint32 tx_len_128_to_255;
1386 + uint32 tx_len_256_to_511;
1387 + uint32 tx_len_512_to_1023;
1388 + uint32 tx_len_1024_to_max;
1389 + uint32 tx_jabber_pkts;
1390 + uint32 tx_oversize_pkts;
1391 + uint32 tx_fragment_pkts;
1392 + uint32 tx_underruns;
1393 + uint32 tx_total_cols;
1394 + uint32 tx_single_cols;
1395 + uint32 tx_multiple_cols;
1396 + uint32 tx_excessive_cols;
1397 + uint32 tx_late_cols;
1398 + uint32 tx_defered;
1399 + uint32 tx_carrier_lost;
1400 + uint32 tx_pause_pkts;
1401 + uint32 PAD[8];
1402 +
1403 + uint32 rx_good_octets;
1404 + uint32 rx_good_pkts;
1405 + uint32 rx_octets;
1406 + uint32 rx_pkts;
1407 + uint32 rx_broadcast_pkts;
1408 + uint32 rx_multicast_pkts;
1409 + uint32 rx_len_64;
1410 + uint32 rx_len_65_to_127;
1411 + uint32 rx_len_128_to_255;
1412 + uint32 rx_len_256_to_511;
1413 + uint32 rx_len_512_to_1023;
1414 + uint32 rx_len_1024_to_max;
1415 + uint32 rx_jabber_pkts;
1416 + uint32 rx_oversize_pkts;
1417 + uint32 rx_fragment_pkts;
1418 + uint32 rx_missed_pkts;
1419 + uint32 rx_crc_align_errs;
1420 + uint32 rx_undersize;
1421 + uint32 rx_crc_errs;
1422 + uint32 rx_align_errs;
1423 + uint32 rx_symbol_errs;
1424 + uint32 rx_pause_pkts;
1425 + uint32 rx_nonpause_pkts;
1426 +} bcmenetmib_t;
1427 +
1428 +#endif /* _bcmenetmib_h_ */
1429 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetphy.h linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h
1430 --- linux.old/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
1431 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h 2005-11-07 21:57:07.845585750 +0100
1432 @@ -0,0 +1,58 @@
1433 +/*
1434 + * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
1435 + *
1436 + * Copyright 2005, Broadcom Corporation
1437 + * All Rights Reserved.
1438 + *
1439 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1440 + * the contents of this file may not be disclosed to third parties, copied
1441 + * or duplicated in any form, in whole or in part, without the prior
1442 + * written permission of Broadcom Corporation.
1443 + * $Id$
1444 + */
1445 +
1446 +#ifndef _bcmenetphy_h_
1447 +#define _bcmenetphy_h_
1448 +
1449 +/* phy address */
1450 +#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
1451 +#define EPHY_MASK 0x1f
1452 +#define EPHY_NONE 31 /* nvram: no phy present at all */
1453 +#define EPHY_NOREG 30 /* nvram: no local phy regs */
1454 +
1455 +/* just a few phy registers */
1456 +#define CTL_RESET (1 << 15) /* reset */
1457 +#define CTL_LOOP (1 << 14) /* loopback */
1458 +#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
1459 +#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
1460 +#define CTL_RESTART (1 << 9) /* restart autonegotiation */
1461 +#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
1462 +
1463 +#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
1464 +#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
1465 +#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
1466 +#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
1467 +
1468 +/* link partner ability register */
1469 +#define LPA_SLCT 0x001f /* same as advertise selector */
1470 +#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
1471 +#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
1472 +#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
1473 +#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
1474 +#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
1475 +#define LPA_RESV 0x1c00 /* unused */
1476 +#define LPA_RFAULT 0x2000 /* link partner faulted */
1477 +#define LPA_LPACK 0x4000 /* link partner acked us */
1478 +#define LPA_NPAGE 0x8000 /* next page bit */
1479 +
1480 +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
1481 +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
1482 +
1483 +#define STAT_REMFAULT (1 << 4) /* remote fault */
1484 +#define STAT_LINK (1 << 2) /* link status */
1485 +#define STAT_JAB (1 << 1) /* jabber detected */
1486 +#define AUX_FORCED (1 << 2) /* forced 10/100 */
1487 +#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
1488 +#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
1489 +
1490 +#endif /* _bcmenetphy_h_ */
1491 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h
1492 --- linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
1493 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-11-07 21:57:07.845585750 +0100
1494 @@ -0,0 +1,43 @@
1495 +/*
1496 + * Hardware-specific Receive Data Header for the
1497 + * Broadcom Home Networking Division
1498 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1499 + *
1500 + * Copyright 2005, Broadcom Corporation
1501 + * All Rights Reserved.
1502 + *
1503 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1504 + * the contents of this file may not be disclosed to third parties, copied
1505 + * or duplicated in any form, in whole or in part, without the prior
1506 + * written permission of Broadcom Corporation.
1507 + * $Id$
1508 + */
1509 +
1510 +#ifndef _bcmenetrxh_h_
1511 +#define _bcmenetrxh_h_
1512 +
1513 +/*
1514 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
1515 + * with every frame consisting of
1516 + * 16bits of frame length, followed by
1517 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
1518 + */
1519 +typedef volatile struct {
1520 + uint16 len;
1521 + uint16 flags;
1522 + uint16 pad[12];
1523 +} bcmenetrxh_t;
1524 +
1525 +#define RXHDR_LEN 28
1526 +
1527 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
1528 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
1529 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
1530 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
1531 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
1532 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
1533 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
1534 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
1535 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
1536 +
1537 +#endif /* _bcmenetrxh_h_ */
1538 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
1539 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1540 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-11-07 22:51:38.772725750 +0100
1541 @@ -0,0 +1,141 @@
1542 +/*
1543 + * NVRAM variable manipulation
1544 + *
1545 + * Copyright 2005, Broadcom Corporation
1546 + * All Rights Reserved.
1547 + *
1548 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1549 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1550 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1551 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1552 + *
1553 + * $Id$
1554 + */
1555 +
1556 +#ifndef _bcmnvram_h_
1557 +#define _bcmnvram_h_
1558 +
1559 +#ifndef _LANGUAGE_ASSEMBLY
1560 +
1561 +#include <typedefs.h>
1562 +
1563 +struct nvram_header {
1564 + uint32 magic;
1565 + uint32 len;
1566 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
1567 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
1568 + uint32 config_ncdl; /* ncdl values for memc */
1569 +};
1570 +
1571 +struct nvram_tuple {
1572 + char *name;
1573 + char *value;
1574 + struct nvram_tuple *next;
1575 +};
1576 +
1577 +/*
1578 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1579 + * platforms.
1580 + */
1581 +extern int BCMINIT(nvram_init)(void *sbh);
1582 +
1583 +/*
1584 + * Disable NVRAM access. May be unnecessary or undefined on certain
1585 + * platforms.
1586 + */
1587 +extern void BCMINIT(nvram_exit)(void *sbh);
1588 +
1589 +/*
1590 + * Get the value of an NVRAM variable. The pointer returned may be
1591 + * invalid after a set.
1592 + * @param name name of variable to get
1593 + * @return value of variable or NULL if undefined
1594 + */
1595 +extern char * BCMINIT(nvram_get)(const char *name);
1596 +
1597 +/*
1598 + * Read the reset GPIO value from the nvram and set the GPIO
1599 + * as input
1600 + */
1601 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
1602 +
1603 +/*
1604 + * Get the value of an NVRAM variable.
1605 + * @param name name of variable to get
1606 + * @return value of variable or NUL if undefined
1607 + */
1608 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1609 +
1610 +/*
1611 + * Match an NVRAM variable.
1612 + * @param name name of variable to match
1613 + * @param match value to compare against value of variable
1614 + * @return TRUE if variable is defined and its value is string equal
1615 + * to match or FALSE otherwise
1616 + */
1617 +static INLINE int
1618 +nvram_match(char *name, char *match) {
1619 + const char *value = BCMINIT(nvram_get)(name);
1620 + return (value && !strcmp(value, match));
1621 +}
1622 +
1623 +/*
1624 + * Inversely match an NVRAM variable.
1625 + * @param name name of variable to match
1626 + * @param match value to compare against value of variable
1627 + * @return TRUE if variable is defined and its value is not string
1628 + * equal to invmatch or FALSE otherwise
1629 + */
1630 +static INLINE int
1631 +nvram_invmatch(char *name, char *invmatch) {
1632 + const char *value = BCMINIT(nvram_get)(name);
1633 + return (value && strcmp(value, invmatch));
1634 +}
1635 +
1636 +/*
1637 + * Set the value of an NVRAM variable. The name and value strings are
1638 + * copied into private storage. Pointers to previously set values
1639 + * may become invalid. The new value may be immediately
1640 + * retrieved but will not be permanently stored until a commit.
1641 + * @param name name of variable to set
1642 + * @param value value of variable
1643 + * @return 0 on success and errno on failure
1644 + */
1645 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1646 +
1647 +/*
1648 + * Unset an NVRAM variable. Pointers to previously set values
1649 + * remain valid until a set.
1650 + * @param name name of variable to unset
1651 + * @return 0 on success and errno on failure
1652 + * NOTE: use nvram_commit to commit this change to flash.
1653 + */
1654 +extern int BCMINIT(nvram_unset)(const char *name);
1655 +
1656 +/*
1657 + * Commit NVRAM variables to permanent storage. All pointers to values
1658 + * may be invalid after a commit.
1659 + * NVRAM values are undefined after a commit.
1660 + * @return 0 on success and errno on failure
1661 + */
1662 +extern int BCMINIT(nvram_commit)(void);
1663 +
1664 +/*
1665 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1666 + * @param buf buffer to store variables
1667 + * @param count size of buffer in bytes
1668 + * @return 0 on success and errno on failure
1669 + */
1670 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1671 +
1672 +#endif /* _LANGUAGE_ASSEMBLY */
1673 +
1674 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1675 +#define NVRAM_VERSION 1
1676 +#define NVRAM_HEADER_SIZE 20
1677 +#define NVRAM_SPACE 0x8000
1678 +
1679 +#define NVRAM_MAX_VALUE_LEN 255
1680 +#define NVRAM_MAX_PARAM_LEN 64
1681 +
1682 +#endif /* _bcmnvram_h_ */
1683 diff -urN linux.old/arch/mips/bcm947xx/include/bcmparams.h linux.dev/arch/mips/bcm947xx/include/bcmparams.h
1684 --- linux.old/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
1685 +++ linux.dev/arch/mips/bcm947xx/include/bcmparams.h 2005-11-07 22:51:38.776726000 +0100
1686 @@ -0,0 +1,25 @@
1687 +/*
1688 + * Misc system wide parameters.
1689 + *
1690 + * Copyright 2005, Broadcom Corporation
1691 + * All Rights Reserved.
1692 + *
1693 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1694 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1695 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1696 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1697 + * $Id$
1698 + */
1699 +
1700 +#ifndef _bcmparams_h_
1701 +#define _bcmparams_h_
1702 +
1703 +#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
1704 +
1705 +#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
1706 +
1707 +#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
1708 +
1709 +#define WL_MAXBSSCFG 16 /* maximum number of BSS Configs we can configure */
1710 +
1711 +#endif
1712 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
1713 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1714 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-11-07 22:51:38.776726000 +0100
1715 @@ -0,0 +1,23 @@
1716 +/*
1717 + * Misc useful routines to access NIC local SROM/OTP .
1718 + *
1719 + * Copyright 2005, Broadcom Corporation
1720 + * All Rights Reserved.
1721 + *
1722 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1723 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1724 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1725 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1726 + *
1727 + * $Id$
1728 + */
1729 +
1730 +#ifndef _bcmsrom_h_
1731 +#define _bcmsrom_h_
1732 +
1733 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
1734 +
1735 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1736 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1737 +
1738 +#endif /* _bcmsrom_h_ */
1739 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
1740 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1741 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-11-07 22:51:38.776726000 +0100
1742 @@ -0,0 +1,313 @@
1743 +/*
1744 + * Misc useful os-independent macros and functions.
1745 + *
1746 + * Copyright 2005, Broadcom Corporation
1747 + * All Rights Reserved.
1748 + *
1749 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1750 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1751 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1752 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1753 + * $Id$
1754 + */
1755 +
1756 +#ifndef _bcmutils_h_
1757 +#define _bcmutils_h_
1758 +
1759 +/*** driver-only section ***/
1760 +#ifdef BCMDRIVER
1761 +#include <osl.h>
1762 +
1763 +#define _BCM_U 0x01 /* upper */
1764 +#define _BCM_L 0x02 /* lower */
1765 +#define _BCM_D 0x04 /* digit */
1766 +#define _BCM_C 0x08 /* cntrl */
1767 +#define _BCM_P 0x10 /* punct */
1768 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1769 +#define _BCM_X 0x40 /* hex digit */
1770 +#define _BCM_SP 0x80 /* hard space (0x20) */
1771 +
1772 +#define GPIO_PIN_NOTDEFINED 0x20
1773 +
1774 +extern unsigned char bcm_ctype[];
1775 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1776 +
1777 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1778 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1779 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1780 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1781 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1782 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1783 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1784 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1785 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1786 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1787 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1788 +
1789 +/*
1790 + * Spin at most 'us' microseconds while 'exp' is true.
1791 + * Caller should explicitly test 'exp' when this completes
1792 + * and take appropriate error action if 'exp' is still true.
1793 + */
1794 +#define SPINWAIT(exp, us) { \
1795 + uint countdown = (us) + 9; \
1796 + while ((exp) && (countdown >= 10)) {\
1797 + OSL_DELAY(10); \
1798 + countdown -= 10; \
1799 + } \
1800 +}
1801 +
1802 +/* generic osl packet queue */
1803 +struct pktq {
1804 + void *head; /* first packet to dequeue */
1805 + void *tail; /* last packet to dequeue */
1806 + uint len; /* number of queued packets */
1807 + uint maxlen; /* maximum number of queued packets */
1808 + bool priority; /* enqueue by packet priority */
1809 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1810 +};
1811 +#define DEFAULT_QLEN 128
1812 +
1813 +#define pktq_len(q) ((q)->len)
1814 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1815 +#define pktq_head(q) ((q)->head)
1816 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1817 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1818 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1819 +
1820 +/* externs */
1821 +/* packet */
1822 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
1823 +extern uint pkttotlen(osl_t *osh, void *);
1824 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1825 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1826 +extern void *pktdeq(struct pktq *q);
1827 +extern void *pktdeqtail(struct pktq *q);
1828 +/* string */
1829 +extern uint bcm_atoi(char *s);
1830 +extern uchar bcm_toupper(uchar c);
1831 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1832 +extern char *bcmstrstr(char *haystack, char *needle);
1833 +extern char *bcmstrcat(char *dest, const char *src);
1834 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1835 +/* ethernet address */
1836 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1837 +extern int bcm_ether_atoe(char *p, char *ea);
1838 +/* delay */
1839 +extern void bcm_mdelay(uint ms);
1840 +/* variable access */
1841 +extern char *getvar(char *vars, char *name);
1842 +extern int getintvar(char *vars, char *name);
1843 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1844 +#define bcmlog(fmt, a1, a2)
1845 +#define bcmdumplog(buf, size) *buf = '\0'
1846 +#define bcmdumplogent(buf, idx) -1
1847 +
1848 +#endif /* #ifdef BCMDRIVER */
1849 +
1850 +/*** driver/apps-shared section ***/
1851 +
1852 +#define BCME_STRLEN 64
1853 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
1854 +
1855 +
1856 +/*
1857 + * error codes could be added but the defined ones shouldn't be changed/deleted
1858 + * these error codes are exposed to the user code
1859 + * when ever a new error code is added to this list
1860 + * please update errorstring table with the related error string and
1861 + * update osl files with os specific errorcode map
1862 +*/
1863 +
1864 +#define BCME_ERROR -1 /* Error generic */
1865 +#define BCME_BADARG -2 /* Bad Argument */
1866 +#define BCME_BADOPTION -3 /* Bad option */
1867 +#define BCME_NOTUP -4 /* Not up */
1868 +#define BCME_NOTDOWN -5 /* Not down */
1869 +#define BCME_NOTAP -6 /* Not AP */
1870 +#define BCME_NOTSTA -7 /* Not STA */
1871 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
1872 +#define BCME_RADIOOFF -9 /* Radio Off */
1873 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
1874 +#define BCME_NOCLK -11 /* No Clock*/
1875 +#define BCME_BADRATESET -12 /* BAD RateSet*/
1876 +#define BCME_BADBAND -13 /* BAD Band */
1877 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
1878 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
1879 +#define BCME_BUSY -16 /* Busy*/
1880 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
1881 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
1882 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
1883 +#define BCME_BADCHAN -20 /* BAD Channel */
1884 +#define BCME_BADADDR -21 /* BAD Address*/
1885 +#define BCME_NORESOURCE -22 /* No resources*/
1886 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
1887 +#define BCME_BADLEN -24 /* Bad Length*/
1888 +#define BCME_NOTREADY -25 /* Not ready Yet*/
1889 +#define BCME_EPERM -26 /* Not Permitted */
1890 +#define BCME_NOMEM -27 /* No Memory */
1891 +#define BCME_ASSOCIATED -28 /* Associated */
1892 +#define BCME_RANGE -29 /* Range Error*/
1893 +#define BCME_NOTFOUND -30 /* Not found */
1894 +#define BCME_LAST BCME_NOTFOUND
1895 +
1896 +#ifndef ABS
1897 +#define ABS(a) (((a)<0)?-(a):(a))
1898 +#endif
1899 +
1900 +#ifndef MIN
1901 +#define MIN(a, b) (((a)<(b))?(a):(b))
1902 +#endif
1903 +
1904 +#ifndef MAX
1905 +#define MAX(a, b) (((a)>(b))?(a):(b))
1906 +#endif
1907 +
1908 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1909 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1910 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1911 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1912 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
1913 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1914 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1915 +
1916 +/* bit map related macros */
1917 +#ifndef setbit
1918 +#define NBBY 8 /* 8 bits per byte */
1919 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1920 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1921 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1922 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1923 +#endif
1924 +
1925 +#define NBITS(type) (sizeof(type) * 8)
1926 +#define NBITVAL(bits) (1 << (bits))
1927 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
1928 +
1929 +/* crc defines */
1930 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1931 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1932 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1933 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1934 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1935 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1936 +
1937 +/* bcm_format_flags() bit description structure */
1938 +typedef struct bcm_bit_desc {
1939 + uint32 bit;
1940 + char* name;
1941 +} bcm_bit_desc_t;
1942 +
1943 +/* tag_ID/length/value_buffer tuple */
1944 +typedef struct bcm_tlv {
1945 + uint8 id;
1946 + uint8 len;
1947 + uint8 data[1];
1948 +} bcm_tlv_t;
1949 +
1950 +/* Check that bcm_tlv_t fits into the given buflen */
1951 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
1952 +
1953 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1954 +#define ETHER_ADDR_STR_LEN 18
1955 +
1956 +/* unaligned load and store macros */
1957 +#ifdef IL_BIGENDIAN
1958 +static INLINE uint32
1959 +load32_ua(uint8 *a)
1960 +{
1961 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1962 +}
1963 +
1964 +static INLINE void
1965 +store32_ua(uint8 *a, uint32 v)
1966 +{
1967 + a[0] = (v >> 24) & 0xff;
1968 + a[1] = (v >> 16) & 0xff;
1969 + a[2] = (v >> 8) & 0xff;
1970 + a[3] = v & 0xff;
1971 +}
1972 +
1973 +static INLINE uint16
1974 +load16_ua(uint8 *a)
1975 +{
1976 + return ((a[0] << 8) | a[1]);
1977 +}
1978 +
1979 +static INLINE void
1980 +store16_ua(uint8 *a, uint16 v)
1981 +{
1982 + a[0] = (v >> 8) & 0xff;
1983 + a[1] = v & 0xff;
1984 +}
1985 +
1986 +#else
1987 +
1988 +static INLINE uint32
1989 +load32_ua(uint8 *a)
1990 +{
1991 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
1992 +}
1993 +
1994 +static INLINE void
1995 +store32_ua(uint8 *a, uint32 v)
1996 +{
1997 + a[3] = (v >> 24) & 0xff;
1998 + a[2] = (v >> 16) & 0xff;
1999 + a[1] = (v >> 8) & 0xff;
2000 + a[0] = v & 0xff;
2001 +}
2002 +
2003 +static INLINE uint16
2004 +load16_ua(uint8 *a)
2005 +{
2006 + return ((a[1] << 8) | a[0]);
2007 +}
2008 +
2009 +static INLINE void
2010 +store16_ua(uint8 *a, uint16 v)
2011 +{
2012 + a[1] = (v >> 8) & 0xff;
2013 + a[0] = v & 0xff;
2014 +}
2015 +
2016 +#endif
2017 +
2018 +/* externs */
2019 +/* crc */
2020 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
2021 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
2022 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
2023 +/* format/print */
2024 +/* IE parsing */
2025 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
2026 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
2027 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
2028 +
2029 +/* bcmerror*/
2030 +extern const char *bcmerrorstr(int bcmerror);
2031 +
2032 +/* multi-bool data type: set of bools, mbool is true if any is set */
2033 +typedef uint32 mbool;
2034 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
2035 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
2036 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
2037 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
2038 +
2039 +/* power conversion */
2040 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
2041 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
2042 +
2043 +/* generic datastruct to help dump routines */
2044 +struct fielddesc {
2045 + char *nameandfmt;
2046 + uint32 offset;
2047 + uint32 len;
2048 +};
2049 +
2050 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
2051 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
2052 +
2053 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
2054 +
2055 +#endif /* _bcmutils_h_ */
2056 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
2057 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
2058 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-11-07 21:57:07.849586000 +0100
2059 @@ -0,0 +1,85 @@
2060 +/*
2061 + * bit manipulation utility functions
2062 + *
2063 + * Copyright 2005, Broadcom Corporation
2064 + * All Rights Reserved.
2065 + *
2066 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2067 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2068 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2069 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2070 + * $Id$
2071 + */
2072 +
2073 +#ifndef _BITFUNCS_H
2074 +#define _BITFUNCS_H
2075 +
2076 +#include <typedefs.h>
2077 +
2078 +/* local prototypes */
2079 +static INLINE uint32 find_msbit(uint32 x);
2080 +
2081 +
2082 +/*
2083 + * find_msbit: returns index of most significant set bit in x, with index
2084 + * range defined as 0-31. NOTE: returns zero if input is zero.
2085 + */
2086 +
2087 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
2088 +
2089 +/*
2090 + * Implementation for Pentium processors and gcc. Note that this
2091 + * instruction is actually very slow on some processors (e.g., family 5,
2092 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
2093 + * implementation instead.
2094 + */
2095 +static INLINE uint32 find_msbit(uint32 x)
2096 +{
2097 + uint msbit;
2098 + __asm__("bsrl %1,%0"
2099 + :"=r" (msbit)
2100 + :"r" (x));
2101 + return msbit;
2102 +}
2103 +
2104 +#else
2105 +
2106 +/*
2107 + * Generic Implementation
2108 + */
2109 +
2110 +#define DB_POW_MASK16 0xffff0000
2111 +#define DB_POW_MASK8 0x0000ff00
2112 +#define DB_POW_MASK4 0x000000f0
2113 +#define DB_POW_MASK2 0x0000000c
2114 +#define DB_POW_MASK1 0x00000002
2115 +
2116 +static INLINE uint32 find_msbit(uint32 x)
2117 +{
2118 + uint32 temp_x = x;
2119 + uint msbit = 0;
2120 + if (temp_x & DB_POW_MASK16) {
2121 + temp_x >>= 16;
2122 + msbit = 16;
2123 + }
2124 + if (temp_x & DB_POW_MASK8) {
2125 + temp_x >>= 8;
2126 + msbit += 8;
2127 + }
2128 + if (temp_x & DB_POW_MASK4) {
2129 + temp_x >>= 4;
2130 + msbit += 4;
2131 + }
2132 + if (temp_x & DB_POW_MASK2) {
2133 + temp_x >>= 2;
2134 + msbit += 2;
2135 + }
2136 + if (temp_x & DB_POW_MASK1) {
2137 + msbit += 1;
2138 + }
2139 + return(msbit);
2140 +}
2141 +
2142 +#endif
2143 +
2144 +#endif /* _BITFUNCS_H */
2145 diff -urN linux.old/arch/mips/bcm947xx/include/cfe_osl.h linux.dev/arch/mips/bcm947xx/include/cfe_osl.h
2146 --- linux.old/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
2147 +++ linux.dev/arch/mips/bcm947xx/include/cfe_osl.h 2005-11-07 22:51:38.776726000 +0100
2148 @@ -0,0 +1,191 @@
2149 +/*
2150 + * CFE boot loader OS Abstraction Layer.
2151 + *
2152 + * Copyright 2005, Broadcom Corporation
2153 + * All Rights Reserved.
2154 + *
2155 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
2156 + * the contents of this file may not be disclosed to third parties, copied
2157 + * or duplicated in any form, in whole or in part, without the prior
2158 + * written permission of Broadcom Corporation.
2159 + *
2160 + * $Id$
2161 + */
2162 +
2163 +#ifndef _cfe_osl_h_
2164 +#define _cfe_osl_h_
2165 +
2166 +#include <lib_types.h>
2167 +#include <lib_string.h>
2168 +#include <lib_printf.h>
2169 +#include <lib_malloc.h>
2170 +#include <cpu_config.h>
2171 +#include <cfe_timer.h>
2172 +#include <cfe_iocb.h>
2173 +#include <cfe_devfuncs.h>
2174 +#include <addrspace.h>
2175 +
2176 +#include <typedefs.h>
2177 +
2178 +/* dump string */
2179 +extern int (*xprinthook)(const char *str);
2180 +#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
2181 +
2182 +/* assert and panic */
2183 +#define ASSERT(exp) do {} while (0)
2184 +
2185 +/* PCMCIA attribute space access macros */
2186 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2187 + bzero(buf, size)
2188 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2189 + do {} while (0)
2190 +
2191 +/* PCI configuration space access macros */
2192 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
2193 + (offset == 8 ? 0 : 0xffffffff)
2194 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
2195 + do {} while (0)
2196 +
2197 +/* PCI device bus # and slot # */
2198 +#define OSL_PCI_BUS(osh) (0)
2199 +#define OSL_PCI_SLOT(osh) (0)
2200 +
2201 +/* register access macros */
2202 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
2203 +#define rreg32(r) (*(volatile uint32*)(r))
2204 +#ifdef IL_BIGENDIAN
2205 +#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
2206 +#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
2207 +#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
2208 +#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
2209 +#else
2210 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
2211 +#define rreg16(r) (*(volatile uint16*)(r))
2212 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
2213 +#define rreg8(r) (*(volatile uint8*)(r))
2214 +#endif
2215 +#define R_REG(r) ({ \
2216 + __typeof(*(r)) __osl_v; \
2217 + switch (sizeof(*(r))) { \
2218 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
2219 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
2220 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
2221 + } \
2222 + __osl_v; \
2223 +})
2224 +#define W_REG(r, v) do { \
2225 + switch (sizeof(*(r))) { \
2226 + case sizeof(uint8): wreg8((r), (v)); break; \
2227 + case sizeof(uint16): wreg16((r), (v)); break; \
2228 + case sizeof(uint32): wreg32((r), (v)); break; \
2229 + } \
2230 +} while (0)
2231 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2232 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2233 +
2234 +/* bcopy, bcmp, and bzero */
2235 +#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
2236 +
2237 +#define osl_attach(pdev) ((osl_t*)pdev)
2238 +#define osl_detach(osh)
2239 +
2240 +/* general purpose memory allocation */
2241 +#define MALLOC(osh, size) KMALLOC((size),0)
2242 +#define MFREE(osh, addr, size) KFREE((addr))
2243 +#define MALLOCED(osh) (0)
2244 +#define MALLOC_DUMP(osh, buf, sz)
2245 +#define MALLOC_FAILED(osh) (0)
2246 +
2247 +/* uncached virtual address */
2248 +#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
2249 +
2250 +/* host/bus architecture-specific address byte swap */
2251 +#define BUS_SWAP32(v) (v)
2252 +
2253 +/* get processor cycle count */
2254 +#define OSL_GETCYCLES(x) ((x) = 0)
2255 +
2256 +/* microsecond delay */
2257 +#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
2258 +
2259 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
2260 +
2261 +/* map/unmap physical to virtual I/O */
2262 +#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
2263 +#define REG_UNMAP(va) do {} while (0)
2264 +
2265 +/* dereference an address that may cause a bus exception */
2266 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
2267 +extern int osl_busprobe(uint32 *val, uint32 addr);
2268 +
2269 +/* allocate/free shared (dma-able) consistent (uncached) memory */
2270 +#define DMA_CONSISTENT_ALIGN 4096
2271 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2272 + osl_dma_alloc_consistent((size), (pap))
2273 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2274 + osl_dma_free_consistent((void*)(va))
2275 +extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
2276 +extern void osl_dma_free_consistent(void *va);
2277 +
2278 +/* map/unmap direction */
2279 +#define DMA_TX 1
2280 +#define DMA_RX 2
2281 +
2282 +/* map/unmap shared (dma-able) memory */
2283 +#define DMA_MAP(osh, va, size, direction, lb) ({ \
2284 + cfe_flushcache(CFE_CACHE_FLUSH_D); \
2285 + PHYSADDR((ulong)(va)); \
2286 +})
2287 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2288 + do {} while (0)
2289 +
2290 +/* shared (dma-able) memory access macros */
2291 +#define R_SM(r) *(r)
2292 +#define W_SM(r, v) (*(r) = (v))
2293 +#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
2294 +
2295 +/* generic packet structure */
2296 +#define LBUFSZ 4096
2297 +#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
2298 +struct lbuf {
2299 + struct lbuf *next; /* pointer to next lbuf if in a chain */
2300 + struct lbuf *link; /* pointer to next lbuf if in a list */
2301 + uchar *head; /* start of buffer */
2302 + uchar *end; /* end of buffer */
2303 + uchar *data; /* start of data */
2304 + uchar *tail; /* end of data */
2305 + uint len; /* nbytes of data */
2306 + void *cookie; /* generic cookie */
2307 +};
2308 +
2309 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2310 +#define PKTBUFSZ 2048
2311 +
2312 +/* packet primitives */
2313 +#define PKTGET(osh, len, send) ((void*)osl_pktget((len)))
2314 +#define PKTFREE(osh, lb, send) osl_pktfree((struct lbuf*)(lb))
2315 +#define PKTDATA(osh, lb) (((struct lbuf*)(lb))->data)
2316 +#define PKTLEN(osh, lb) (((struct lbuf*)(lb))->len)
2317 +#define PKTHEADROOM(osh, lb) (PKTDATA(osh,lb)-(((struct lbuf*)(lb))->head))
2318 +#define PKTTAILROOM(osh, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
2319 +#define PKTNEXT(osh, lb) (((struct lbuf*)(lb))->next)
2320 +#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
2321 +#define PKTSETLEN(osh, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
2322 +#define PKTPUSH(osh, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
2323 +#define PKTPULL(osh, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
2324 +#define PKTDUP(osh, lb) osl_pktdup((struct lbuf*)(lb))
2325 +#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
2326 +#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
2327 +#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
2328 +#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
2329 +#define PKTPRIO(lb) (0)
2330 +#define PKTSETPRIO(lb, x) do {} while (0)
2331 +extern struct lbuf *osl_pktget(uint len);
2332 +extern void osl_pktfree(struct lbuf *lb);
2333 +extern void osl_pktsetlen(struct lbuf *lb, uint len);
2334 +extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
2335 +extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
2336 +extern struct lbuf *osl_pktdup(struct lbuf *lb);
2337 +extern int osl_error(int bcmerror);
2338 +
2339 +#endif /* _cfe_osl_h_ */
2340 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h linux.dev/arch/mips/bcm947xx/include/epivers.h
2341 --- linux.old/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
2342 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h 2005-11-07 22:51:38.776726000 +0100
2343 @@ -0,0 +1,69 @@
2344 +/*
2345 + * Copyright 2005, Broadcom Corporation
2346 + * All Rights Reserved.
2347 + *
2348 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2349 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2350 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2351 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2352 + *
2353 + * $Id$
2354 + *
2355 +*/
2356 +
2357 +#ifndef _epivers_h_
2358 +#define _epivers_h_
2359 +
2360 +#ifdef linux
2361 +#include <linux/config.h>
2362 +#endif
2363 +
2364 +/* Vendor Name, ASCII, 32 chars max */
2365 +#ifdef COMPANYNAME
2366 +#define HPNA_VENDOR COMPANYNAME
2367 +#else
2368 +#define HPNA_VENDOR "Broadcom Corporation"
2369 +#endif
2370 +
2371 +/* Driver Date, ASCII, 32 chars max */
2372 +#define HPNA_DRV_BUILD_DATE __DATE__
2373 +
2374 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2375 +#define HPNA_HW_MFG_DATE "Not Specified"
2376 +
2377 +/* See documentation for Device Type values, 32 values max */
2378 +#ifndef HPNA_DEV_TYPE
2379 +
2380 +#if defined(CONFIG_BRCM_VJ)
2381 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2382 +
2383 +#elif defined(CONFIG_BCRM_93725)
2384 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2385 +
2386 +#else
2387 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2388 +
2389 +#endif
2390 +
2391 +#endif /* !HPNA_DEV_TYPE */
2392 +
2393 +
2394 +#define EPI_MAJOR_VERSION 3
2395 +
2396 +#define EPI_MINOR_VERSION 130
2397 +
2398 +#define EPI_RC_NUMBER 20
2399 +
2400 +#define EPI_INCREMENTAL_NUMBER 0
2401 +
2402 +#define EPI_BUILD_NUMBER 0
2403 +
2404 +#define EPI_VERSION 3,130,20,0
2405 +
2406 +#define EPI_VERSION_NUM 0x03821400
2407 +
2408 +/* Driver Version String, ASCII, 32 chars max */
2409 +#define EPI_VERSION_STR "3.130.20.0"
2410 +#define EPI_ROUTER_VERSION_STR "3.131.20.0"
2411 +
2412 +#endif /* _epivers_h_ */
2413 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h.in linux.dev/arch/mips/bcm947xx/include/epivers.h.in
2414 --- linux.old/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
2415 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h.in 2005-11-07 21:57:07.849586000 +0100
2416 @@ -0,0 +1,69 @@
2417 +/*
2418 + * Copyright 2005, Broadcom Corporation
2419 + * All Rights Reserved.
2420 + *
2421 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2422 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2423 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2424 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2425 + *
2426 + * $Id$
2427 + *
2428 +*/
2429 +
2430 +#ifndef _epivers_h_
2431 +#define _epivers_h_
2432 +
2433 +#ifdef linux
2434 +#include <linux/config.h>
2435 +#endif
2436 +
2437 +/* Vendor Name, ASCII, 32 chars max */
2438 +#ifdef COMPANYNAME
2439 +#define HPNA_VENDOR COMPANYNAME
2440 +#else
2441 +#define HPNA_VENDOR "Broadcom Corporation"
2442 +#endif
2443 +
2444 +/* Driver Date, ASCII, 32 chars max */
2445 +#define HPNA_DRV_BUILD_DATE __DATE__
2446 +
2447 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2448 +#define HPNA_HW_MFG_DATE "Not Specified"
2449 +
2450 +/* See documentation for Device Type values, 32 values max */
2451 +#ifndef HPNA_DEV_TYPE
2452 +
2453 +#if defined(CONFIG_BRCM_VJ)
2454 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2455 +
2456 +#elif defined(CONFIG_BCRM_93725)
2457 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2458 +
2459 +#else
2460 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2461 +
2462 +#endif
2463 +
2464 +#endif /* !HPNA_DEV_TYPE */
2465 +
2466 +
2467 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
2468 +
2469 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
2470 +
2471 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
2472 +
2473 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
2474 +
2475 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
2476 +
2477 +#define EPI_VERSION @EPI_VERSION@
2478 +
2479 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
2480 +
2481 +/* Driver Version String, ASCII, 32 chars max */
2482 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
2483 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
2484 +
2485 +#endif /* _epivers_h_ */
2486 diff -urN linux.old/arch/mips/bcm947xx/include/etsockio.h linux.dev/arch/mips/bcm947xx/include/etsockio.h
2487 --- linux.old/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
2488 +++ linux.dev/arch/mips/bcm947xx/include/etsockio.h 2005-11-07 21:57:07.861586750 +0100
2489 @@ -0,0 +1,59 @@
2490 +/*
2491 + * Driver-specific socket ioctls
2492 + * used by BSD, Linux, and PSOS
2493 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
2494 + *
2495 + * Copyright 2005, Broadcom Corporation
2496 + * All Rights Reserved.
2497 + *
2498 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2499 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2500 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2501 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2502 + *
2503 + * $Id$
2504 + */
2505 +
2506 +#ifndef _etsockio_h_
2507 +#define _etsockio_h_
2508 +
2509 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
2510 +
2511 +
2512 +#if defined(linux)
2513 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
2514 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
2515 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
2516 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
2517 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
2518 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
2519 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
2520 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
2521 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
2522 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
2523 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
2524 +#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
2525 +
2526 +#else /* !linux */
2527 +
2528 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
2529 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
2530 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
2531 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
2532 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
2533 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
2534 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
2535 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
2536 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
2537 +
2538 +#endif
2539 +
2540 +/* arg to SIOCTXGEN */
2541 +struct txg {
2542 + uint32 num; /* number of frames to send */
2543 + uint32 delay; /* delay in microseconds between sending each */
2544 + uint32 size; /* size of ether frame to send */
2545 + uchar buf[1514]; /* starting ether frame data */
2546 +};
2547 +
2548 +#endif
2549 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
2550 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
2551 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-11-07 21:57:07.861586750 +0100
2552 @@ -0,0 +1,188 @@
2553 +/*
2554 + * flash.h: Common definitions for flash access.
2555 + *
2556 + * Copyright 2005, Broadcom Corporation
2557 + * All Rights Reserved.
2558 + *
2559 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2560 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2561 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2562 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2563 + *
2564 + * $Id$
2565 + */
2566 +
2567 +/* Types of flashes we know about */
2568 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
2569 +
2570 +/* Commands to write/erase the flases */
2571 +typedef struct _flash_cmds{
2572 + flash_type_t type;
2573 + bool need_unlock;
2574 + uint16 pre_erase;
2575 + uint16 erase_block;
2576 + uint16 erase_chip;
2577 + uint16 write_word;
2578 + uint16 write_buf;
2579 + uint16 clear_csr;
2580 + uint16 read_csr;
2581 + uint16 read_id;
2582 + uint16 confirm;
2583 + uint16 read_array;
2584 +} flash_cmds_t;
2585 +
2586 +#define UNLOCK_CMD_WORDS 2
2587 +
2588 +typedef struct _unlock_cmd {
2589 + uint addr[UNLOCK_CMD_WORDS];
2590 + uint16 cmd[UNLOCK_CMD_WORDS];
2591 +} unlock_cmd_t;
2592 +
2593 +/* Flash descriptors */
2594 +typedef struct _flash_desc {
2595 + uint16 mfgid; /* Manufacturer Id */
2596 + uint16 devid; /* Device Id */
2597 + uint size; /* Total size in bytes */
2598 + uint width; /* Device width in bytes */
2599 + flash_type_t type; /* Device type old, S, J */
2600 + uint bsize; /* Block size */
2601 + uint nb; /* Number of blocks */
2602 + uint ff; /* First full block */
2603 + uint lf; /* Last full block */
2604 + uint nsub; /* Number of subblocks */
2605 + uint *subblocks; /* Offsets for subblocks */
2606 + char *desc; /* Description */
2607 +} flash_desc_t;
2608 +
2609 +
2610 +#ifdef DECLARE_FLASHES
2611 +flash_cmds_t sflash_cmd_t =
2612 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2613 +
2614 +flash_cmds_t flash_cmds[] = {
2615 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
2616 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
2617 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
2618 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2619 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2620 + { 0 }
2621 +};
2622 +
2623 +unlock_cmd_t unlock_cmd_amd = {
2624 +#ifdef MIPSEB
2625 +/* addr: */ { 0x0aa8, 0x0556},
2626 +#else
2627 +/* addr: */ { 0x0aaa, 0x0554},
2628 +#endif
2629 +/* data: */ { 0xaa, 0x55}
2630 +};
2631 +
2632 +unlock_cmd_t unlock_cmd_sst = {
2633 +#ifdef MIPSEB
2634 +/* addr: */ { 0xaaa8, 0x5556},
2635 +#else
2636 +/* addr: */ { 0xaaaa, 0x5554},
2637 +#endif
2638 +/* data: */ { 0xaa, 0x55}
2639 +};
2640 +
2641 +#define AMD_CMD 0xaaa
2642 +#define SST_CMD 0xaaaa
2643 +
2644 +/* intel unlock block cmds */
2645 +#define INTEL_UNLOCK1 0x60
2646 +#define INTEL_UNLOCK2 0xD0
2647 +
2648 +/* Just eight blocks of 8KB byte each */
2649 +
2650 +uint blk8x8k[] = { 0x00000000,
2651 + 0x00002000,
2652 + 0x00004000,
2653 + 0x00006000,
2654 + 0x00008000,
2655 + 0x0000a000,
2656 + 0x0000c000,
2657 + 0x0000e000,
2658 + 0x00010000
2659 +};
2660 +
2661 +/* Funky AMD arrangement for 29xx800's */
2662 +uint amd800[] = { 0x00000000, /* 16KB */
2663 + 0x00004000, /* 32KB */
2664 + 0x0000c000, /* 8KB */
2665 + 0x0000e000, /* 8KB */
2666 + 0x00010000, /* 8KB */
2667 + 0x00012000, /* 8KB */
2668 + 0x00014000, /* 32KB */
2669 + 0x0001c000, /* 16KB */
2670 + 0x00020000
2671 +};
2672 +
2673 +/* AMD arrangement for 29xx160's */
2674 +uint amd4112[] = { 0x00000000, /* 32KB */
2675 + 0x00008000, /* 8KB */
2676 + 0x0000a000, /* 8KB */
2677 + 0x0000c000, /* 16KB */
2678 + 0x00010000
2679 +};
2680 +uint amd2114[] = { 0x00000000, /* 16KB */
2681 + 0x00004000, /* 8KB */
2682 + 0x00006000, /* 8KB */
2683 + 0x00008000, /* 32KB */
2684 + 0x00010000
2685 +};
2686 +
2687 +
2688 +flash_desc_t sflash_desc =
2689 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
2690 +
2691 +flash_desc_t flashes[] = {
2692 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
2693 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
2694 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
2695 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
2696 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
2697 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
2698 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
2699 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
2700 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
2701 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
2702 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
2703 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
2704 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
2705 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
2706 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
2707 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
2708 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
2709 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
2710 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
2711 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
2712 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
2713 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
2714 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
2715 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
2716 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
2717 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
2718 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
2719 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
2720 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
2721 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
2722 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2723 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2724 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
2725 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
2726 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
2727 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
2728 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2729 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2730 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
2731 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
2732 +};
2733 +
2734 +#else
2735 +
2736 +extern flash_cmds_t flash_cmds[];
2737 +extern unlock_cmd_t unlock_cmd;
2738 +extern flash_desc_t flashes[];
2739 +
2740 +#endif
2741 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
2742 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
2743 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-11-07 21:57:07.861586750 +0100
2744 @@ -0,0 +1,27 @@
2745 +/*
2746 + * BCM47XX FLASH driver interface
2747 + *
2748 + * Copyright 2005, Broadcom Corporation
2749 + * All Rights Reserved.
2750 + *
2751 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2752 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2753 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2754 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2755 + * $Id$
2756 + */
2757 +
2758 +#ifndef _flashutl_h_
2759 +#define _flashutl_h_
2760 +
2761 +
2762 +#ifndef _LANGUAGE_ASSEMBLY
2763 +
2764 +int sysFlashInit(char *flash_str);
2765 +int sysFlashRead(uint off, uchar *dst, uint bytes);
2766 +int sysFlashWrite(uint off, uchar *src, uint bytes);
2767 +void nvWrite(unsigned short *data, unsigned int len);
2768 +
2769 +#endif /* _LANGUAGE_ASSEMBLY */
2770 +
2771 +#endif /* _flashutl_h_ */
2772 diff -urN linux.old/arch/mips/bcm947xx/include/hnddma.h linux.dev/arch/mips/bcm947xx/include/hnddma.h
2773 --- linux.old/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
2774 +++ linux.dev/arch/mips/bcm947xx/include/hnddma.h 2005-11-07 22:51:38.776726000 +0100
2775 @@ -0,0 +1,71 @@
2776 +/*
2777 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
2778 + * This supports the following chips: BCM42xx, 44xx, 47xx .
2779 + *
2780 + * Copyright 2005, Broadcom Corporation
2781 + * All Rights Reserved.
2782 + *
2783 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2784 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2785 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2786 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2787 + * $Id$
2788 + */
2789 +
2790 +#ifndef _hnddma_h_
2791 +#define _hnddma_h_
2792 +
2793 +/* export structure */
2794 +typedef volatile struct {
2795 + /* rx error counters */
2796 + uint rxgiants; /* rx giant frames */
2797 + uint rxnobuf; /* rx out of dma descriptors */
2798 + /* tx error counters */
2799 + uint txnobuf; /* tx out of dma descriptors */
2800 +} hnddma_t;
2801 +
2802 +#ifndef di_t
2803 +#define di_t void
2804 +#endif
2805 +
2806 +#ifndef osl_t
2807 +#define osl_t void
2808 +#endif
2809 +
2810 +/* externs */
2811 +extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
2812 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
2813 +extern void dma_detach(di_t *di);
2814 +extern void dma_txreset(di_t *di);
2815 +extern void dma_rxreset(di_t *di);
2816 +extern void dma_txinit(di_t *di);
2817 +extern bool dma_txenabled(di_t *di);
2818 +extern void dma_rxinit(di_t *di);
2819 +extern void dma_rxenable(di_t *di);
2820 +extern bool dma_rxenabled(di_t *di);
2821 +extern void dma_txsuspend(di_t *di);
2822 +extern void dma_txresume(di_t *di);
2823 +extern bool dma_txsuspended(di_t *di);
2824 +extern bool dma_txsuspendedidle(di_t *di);
2825 +extern bool dma_txstopped(di_t *di);
2826 +extern bool dma_rxstopped(di_t *di);
2827 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
2828 +extern void dma_fifoloopbackenable(di_t *di);
2829 +extern void *dma_rx(di_t *di);
2830 +extern void dma_rxfill(di_t *di);
2831 +extern void dma_txreclaim(di_t *di, bool forceall);
2832 +extern void dma_rxreclaim(di_t *di);
2833 +extern uintptr dma_getvar(di_t *di, char *name);
2834 +extern void *dma_getnexttxp(di_t *di, bool forceall);
2835 +extern void *dma_peeknexttxp(di_t *di);
2836 +extern void *dma_getnextrxp(di_t *di, bool forceall);
2837 +extern void dma_txblock(di_t *di);
2838 +extern void dma_txunblock(di_t *di);
2839 +extern uint dma_txactive(di_t *di);
2840 +extern void dma_txrotate(di_t *di);
2841 +
2842 +extern void dma_rxpiomode(dma32regs_t *);
2843 +extern void dma_txpioloopback(dma32regs_t *);
2844 +
2845 +
2846 +#endif /* _hnddma_h_ */
2847 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
2848 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
2849 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-11-07 21:57:07.861586750 +0100
2850 @@ -0,0 +1,16 @@
2851 +/*
2852 + * Alternate include file for HND sbmips.h since CFE also ships with
2853 + * a sbmips.h.
2854 + *
2855 + * Copyright 2005, Broadcom Corporation
2856 + * All Rights Reserved.
2857 + *
2858 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2859 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2860 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2861 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2862 + *
2863 + * $Id$
2864 + */
2865 +
2866 +#include "sbmips.h"
2867 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
2868 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
2869 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-11-07 22:51:38.776726000 +0100
2870 @@ -0,0 +1,371 @@
2871 +/*
2872 + * Linux OS Independent Layer
2873 + *
2874 + * Copyright 2005, Broadcom Corporation
2875 + * All Rights Reserved.
2876 + *
2877 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2878 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2879 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2880 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2881 + *
2882 + * $Id$
2883 + */
2884 +
2885 +#ifndef _linux_osl_h_
2886 +#define _linux_osl_h_
2887 +
2888 +#include <typedefs.h>
2889 +
2890 +/* use current 2.4.x calling conventions */
2891 +#include <linuxver.h>
2892 +
2893 +/* assert and panic */
2894 +#ifdef __GNUC__
2895 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
2896 +#if GCC_VERSION > 30100
2897 +#define ASSERT(exp) do {} while (0)
2898 +#else
2899 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
2900 +#define ASSERT(exp)
2901 +#endif
2902 +#endif
2903 +
2904 +/* microsecond delay */
2905 +#define OSL_DELAY(usec) osl_delay(usec)
2906 +extern void osl_delay(uint usec);
2907 +
2908 +/* PCMCIA attribute space access macros */
2909 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2910 +struct pcmcia_dev {
2911 + dev_link_t link; /* PCMCIA device pointer */
2912 + dev_node_t node; /* PCMCIA node structure */
2913 + void *base; /* Mapped attribute memory window */
2914 + size_t size; /* Size of window */
2915 + void *drv; /* Driver data */
2916 +};
2917 +#endif
2918 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2919 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
2920 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2921 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
2922 +extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
2923 +extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
2924 +
2925 +/* PCI configuration space access macros */
2926 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
2927 + osl_pci_read_config((osh), (offset), (size))
2928 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
2929 + osl_pci_write_config((osh), (offset), (size), (val))
2930 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
2931 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
2932 +
2933 +/* PCI device bus # and slot # */
2934 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
2935 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
2936 +extern uint osl_pci_bus(osl_t *osh);
2937 +extern uint osl_pci_slot(osl_t *osh);
2938 +
2939 +/* OSL initialization */
2940 +extern osl_t *osl_attach(void *pdev);
2941 +extern void osl_detach(osl_t *osh);
2942 +
2943 +/* host/bus architecture-specific byte swap */
2944 +#define BUS_SWAP32(v) (v)
2945 +
2946 +/* general purpose memory allocation */
2947 +
2948 +#if defined(BCMDBG_MEM)
2949 +
2950 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
2951 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
2952 +#define MALLOCED(osh) osl_malloced((osh))
2953 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
2954 +extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
2955 +extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
2956 +extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
2957 +
2958 +#else
2959 +
2960 +#define MALLOC(osh, size) osl_malloc((osh), (size))
2961 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
2962 +#define MALLOCED(osh) osl_malloced((osh))
2963 +
2964 +#endif /* BCMDBG_MEM */
2965 +
2966 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
2967 +
2968 +extern void *osl_malloc(osl_t *osh, uint size);
2969 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
2970 +extern uint osl_malloced(osl_t *osh);
2971 +extern uint osl_malloc_failed(osl_t *osh);
2972 +
2973 +/* allocate/free shared (dma-able) consistent memory */
2974 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
2975 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2976 + osl_dma_alloc_consistent((osh), (size), (pap))
2977 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2978 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
2979 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
2980 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
2981 +
2982 +/* map/unmap direction */
2983 +#define DMA_TX 1
2984 +#define DMA_RX 2
2985 +
2986 +/* map/unmap shared (dma-able) memory */
2987 +#define DMA_MAP(osh, va, size, direction, p) \
2988 + osl_dma_map((osh), (va), (size), (direction))
2989 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2990 + osl_dma_unmap((osh), (pa), (size), (direction))
2991 +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
2992 +extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
2993 +
2994 +/* register access macros */
2995 +#if defined(BCMJTAG)
2996 +#include <bcmjtag.h>
2997 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
2998 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
2999 +#endif
3000 +
3001 +/*
3002 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
3003 + * Macros expand to calls to functions defined in linux_osl.c .
3004 + */
3005 +#ifndef BINOSL
3006 +
3007 +/* string library, kernel mode */
3008 +#define printf(fmt, args...) printk(fmt, ## args)
3009 +#include <linux/kernel.h>
3010 +#include <linux/string.h>
3011 +
3012 +/* register access macros */
3013 +#if !defined(BCMJTAG)
3014 +#ifndef IL_BIGENDIAN
3015 +#define R_REG(r) ( \
3016 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
3017 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
3018 + readl((volatile uint32*)(r)) \
3019 +)
3020 +#define W_REG(r, v) do { \
3021 + switch (sizeof(*(r))) { \
3022 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
3023 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
3024 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3025 + } \
3026 +} while (0)
3027 +#else /* IL_BIGENDIAN */
3028 +#define R_REG(r) ({ \
3029 + __typeof(*(r)) __osl_v; \
3030 + switch (sizeof(*(r))) { \
3031 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
3032 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
3033 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
3034 + } \
3035 + __osl_v; \
3036 +})
3037 +#define W_REG(r, v) do { \
3038 + switch (sizeof(*(r))) { \
3039 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
3040 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
3041 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3042 + } \
3043 +} while (0)
3044 +#endif
3045 +#endif
3046 +
3047 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3048 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3049 +
3050 +/* bcopy, bcmp, and bzero */
3051 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3052 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3053 +#define bzero(b, len) memset((b), '\0', (len))
3054 +
3055 +/* uncached virtual address */
3056 +#ifdef mips
3057 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
3058 +#include <asm/addrspace.h>
3059 +#else
3060 +#define OSL_UNCACHED(va) (va)
3061 +#endif
3062 +
3063 +/* get processor cycle count */
3064 +#if defined(mips)
3065 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
3066 +#elif defined(__i386__)
3067 +#define OSL_GETCYCLES(x) rdtscl((x))
3068 +#else
3069 +#define OSL_GETCYCLES(x) ((x) = 0)
3070 +#endif
3071 +
3072 +/* dereference an address that may cause a bus exception */
3073 +#ifdef mips
3074 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
3075 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
3076 +#else
3077 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
3078 +#include <asm/paccess.h>
3079 +#endif
3080 +#else
3081 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
3082 +#endif
3083 +
3084 +/* map/unmap physical to virtual I/O */
3085 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
3086 +#define REG_UNMAP(va) iounmap((void *)(va))
3087 +
3088 +/* shared (dma-able) memory access macros */
3089 +#define R_SM(r) *(r)
3090 +#define W_SM(r, v) (*(r) = (v))
3091 +#define BZERO_SM(r, len) memset((r), '\0', (len))
3092 +
3093 +/* packet primitives */
3094 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3095 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3096 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
3097 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
3098 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
3099 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
3100 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
3101 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
3102 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
3103 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
3104 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
3105 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
3106 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
3107 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
3108 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
3109 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
3110 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
3111 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
3112 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3113 +extern void osl_pktfree(void *skb);
3114 +
3115 +#else /* BINOSL */
3116 +
3117 +/* string library */
3118 +#ifndef LINUX_OSL
3119 +#undef printf
3120 +#define printf(fmt, args...) osl_printf((fmt), ## args)
3121 +#undef sprintf
3122 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
3123 +#undef strcmp
3124 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
3125 +#undef strncmp
3126 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
3127 +#undef strlen
3128 +#define strlen(s) osl_strlen((s))
3129 +#undef strcpy
3130 +#define strcpy(d, s) osl_strcpy((d), (s))
3131 +#undef strncpy
3132 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
3133 +#endif
3134 +extern int osl_printf(const char *format, ...);
3135 +extern int osl_sprintf(char *buf, const char *format, ...);
3136 +extern int osl_strcmp(const char *s1, const char *s2);
3137 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
3138 +extern int osl_strlen(const char *s);
3139 +extern char* osl_strcpy(char *d, const char *s);
3140 +extern char* osl_strncpy(char *d, const char *s, uint n);
3141 +
3142 +/* register access macros */
3143 +#if !defined(BCMJTAG)
3144 +#define R_REG(r) ( \
3145 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
3146 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
3147 + osl_readl((volatile uint32*)(r)) \
3148 +)
3149 +#define W_REG(r, v) do { \
3150 + switch (sizeof(*(r))) { \
3151 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
3152 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
3153 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
3154 + } \
3155 +} while (0)
3156 +#endif
3157 +
3158 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3159 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3160 +extern uint8 osl_readb(volatile uint8 *r);
3161 +extern uint16 osl_readw(volatile uint16 *r);
3162 +extern uint32 osl_readl(volatile uint32 *r);
3163 +extern void osl_writeb(uint8 v, volatile uint8 *r);
3164 +extern void osl_writew(uint16 v, volatile uint16 *r);
3165 +extern void osl_writel(uint32 v, volatile uint32 *r);
3166 +
3167 +/* bcopy, bcmp, and bzero */
3168 +extern void bcopy(const void *src, void *dst, int len);
3169 +extern int bcmp(const void *b1, const void *b2, int len);
3170 +extern void bzero(void *b, int len);
3171 +
3172 +/* uncached virtual address */
3173 +#define OSL_UNCACHED(va) osl_uncached((va))
3174 +extern void *osl_uncached(void *va);
3175 +
3176 +/* get processor cycle count */
3177 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
3178 +extern uint osl_getcycles(void);
3179 +
3180 +/* dereference an address that may target abort */
3181 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
3182 +extern int osl_busprobe(uint32 *val, uint32 addr);
3183 +
3184 +/* map/unmap physical to virtual */
3185 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
3186 +#define REG_UNMAP(va) osl_reg_unmap((va))
3187 +extern void *osl_reg_map(uint32 pa, uint size);
3188 +extern void osl_reg_unmap(void *va);
3189 +
3190 +/* shared (dma-able) memory access macros */
3191 +#define R_SM(r) *(r)
3192 +#define W_SM(r, v) (*(r) = (v))
3193 +#define BZERO_SM(r, len) bzero((r), (len))
3194 +
3195 +/* packet primitives */
3196 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3197 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3198 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
3199 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
3200 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
3201 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
3202 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
3203 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
3204 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
3205 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
3206 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
3207 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
3208 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
3209 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
3210 +#define PKTLINK(skb) osl_pktlink((skb))
3211 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
3212 +#define PKTPRIO(skb) osl_pktprio((skb))
3213 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
3214 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3215 +extern void osl_pktfree(void *skb);
3216 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
3217 +extern uint osl_pktlen(osl_t *osh, void *skb);
3218 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
3219 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
3220 +extern void *osl_pktnext(osl_t *osh, void *skb);
3221 +extern void osl_pktsetnext(void *skb, void *x);
3222 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
3223 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
3224 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
3225 +extern void *osl_pktdup(osl_t *osh, void *skb);
3226 +extern void *osl_pktcookie(void *skb);
3227 +extern void osl_pktsetcookie(void *skb, void *x);
3228 +extern void *osl_pktlink(void *skb);
3229 +extern void osl_pktsetlink(void *skb, void *x);
3230 +extern uint osl_pktprio(void *skb);
3231 +extern void osl_pktsetprio(void *skb, uint x);
3232 +
3233 +#endif /* BINOSL */
3234 +
3235 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3236 +extern int osl_error(int bcmerror);
3237 +
3238 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
3239 +#define PKTBUFSZ 2048
3240 +
3241 +#endif /* _linux_osl_h_ */
3242 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
3243 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
3244 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-11-07 22:51:38.780726250 +0100
3245 @@ -0,0 +1,411 @@
3246 +/*
3247 + * Linux-specific abstractions to gain some independence from linux kernel versions.
3248 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
3249 + *
3250 + * Copyright 2005, Broadcom Corporation
3251 + * All Rights Reserved.
3252 + *
3253 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3254 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3255 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3256 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3257 + *
3258 + * $Id$
3259 + */
3260 +
3261 +#ifndef _linuxver_h_
3262 +#define _linuxver_h_
3263 +
3264 +#include <linux/config.h>
3265 +#include <linux/version.h>
3266 +
3267 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
3268 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
3269 +#ifdef __UNDEF_NO_VERSION__
3270 +#undef __NO_VERSION__
3271 +#else
3272 +#define __NO_VERSION__
3273 +#endif
3274 +#endif
3275 +
3276 +#if defined(MODULE) && defined(MODVERSIONS)
3277 +#include <linux/modversions.h>
3278 +#endif
3279 +
3280 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
3281 +#include <linux/moduleparam.h>
3282 +#endif
3283 +
3284 +
3285 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3286 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
3287 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
3288 +#endif
3289 +
3290 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
3291 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
3292 +#include <linux/malloc.h>
3293 +#else
3294 +#include <linux/slab.h>
3295 +#endif
3296 +
3297 +#include <linux/types.h>
3298 +#include <linux/init.h>
3299 +#include <linux/mm.h>
3300 +#include <linux/string.h>
3301 +#include <linux/pci.h>
3302 +#include <linux/interrupt.h>
3303 +#include <linux/netdevice.h>
3304 +#include <asm/io.h>
3305 +
3306 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
3307 +#include <linux/workqueue.h>
3308 +#else
3309 +#include <linux/tqueue.h>
3310 +#ifndef work_struct
3311 +#define work_struct tq_struct
3312 +#endif
3313 +#ifndef INIT_WORK
3314 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
3315 +#endif
3316 +#ifndef schedule_work
3317 +#define schedule_work(_work) schedule_task((_work))
3318 +#endif
3319 +#ifndef flush_scheduled_work
3320 +#define flush_scheduled_work() flush_scheduled_tasks()
3321 +#endif
3322 +#endif
3323 +
3324 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3325 +/* Some distributions have their own 2.6.x compatibility layers */
3326 +#ifndef IRQ_NONE
3327 +typedef void irqreturn_t;
3328 +#define IRQ_NONE
3329 +#define IRQ_HANDLED
3330 +#define IRQ_RETVAL(x)
3331 +#endif
3332 +#else
3333 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
3334 +#endif
3335 +
3336 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
3337 +
3338 +#include <pcmcia/version.h>
3339 +#include <pcmcia/cs_types.h>
3340 +#include <pcmcia/cs.h>
3341 +#include <pcmcia/cistpl.h>
3342 +#include <pcmcia/cisreg.h>
3343 +#include <pcmcia/ds.h>
3344 +
3345 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
3346 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
3347 + * does this, but it's not in 2.4 so we do our own for now. */
3348 +static inline void
3349 +cs_error(client_handle_t handle, int func, int ret)
3350 +{
3351 + error_info_t err = { func, ret };
3352 + CardServices(ReportError, handle, &err);
3353 +}
3354 +#endif
3355 +
3356 +#endif /* CONFIG_PCMCIA */
3357 +
3358 +#ifndef __exit
3359 +#define __exit
3360 +#endif
3361 +#ifndef __devexit
3362 +#define __devexit
3363 +#endif
3364 +#ifndef __devinit
3365 +#define __devinit __init
3366 +#endif
3367 +#ifndef __devinitdata
3368 +#define __devinitdata
3369 +#endif
3370 +#ifndef __devexit_p
3371 +#define __devexit_p(x) x
3372 +#endif
3373 +
3374 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
3375 +
3376 +#define pci_get_drvdata(dev) (dev)->sysdata
3377 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
3378 +
3379 +/*
3380 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
3381 + */
3382 +
3383 +struct pci_device_id {
3384 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
3385 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
3386 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
3387 + unsigned long driver_data; /* Data private to the driver */
3388 +};
3389 +
3390 +struct pci_driver {
3391 + struct list_head node;
3392 + char *name;
3393 + const struct pci_device_id *id_table; /* NULL if wants all devices */
3394 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
3395 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
3396 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
3397 + void (*resume)(struct pci_dev *dev); /* Device woken up */
3398 +};
3399 +
3400 +#define MODULE_DEVICE_TABLE(type, name)
3401 +#define PCI_ANY_ID (~0)
3402 +
3403 +/* compatpci.c */
3404 +#define pci_module_init pci_register_driver
3405 +extern int pci_register_driver(struct pci_driver *drv);
3406 +extern void pci_unregister_driver(struct pci_driver *drv);
3407 +
3408 +#endif /* PCI registration */
3409 +
3410 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
3411 +#ifdef MODULE
3412 +#define module_init(x) int init_module(void) { return x(); }
3413 +#define module_exit(x) void cleanup_module(void) { x(); }
3414 +#else
3415 +#define module_init(x) __initcall(x);
3416 +#define module_exit(x) __exitcall(x);
3417 +#endif
3418 +#endif
3419 +
3420 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
3421 +#define list_for_each(pos, head) \
3422 + for (pos = (head)->next; pos != (head); pos = pos->next)
3423 +#endif
3424 +
3425 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
3426 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
3427 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
3428 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
3429 +#endif
3430 +
3431 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
3432 +#define pci_enable_device(dev) do { } while (0)
3433 +#endif
3434 +
3435 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
3436 +#define net_device device
3437 +#endif
3438 +
3439 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
3440 +
3441 +/*
3442 + * DMA mapping
3443 + *
3444 + * See linux/Documentation/DMA-mapping.txt
3445 + */
3446 +
3447 +#ifndef PCI_DMA_TODEVICE
3448 +#define PCI_DMA_TODEVICE 1
3449 +#define PCI_DMA_FROMDEVICE 2
3450 +#endif
3451 +
3452 +typedef u32 dma_addr_t;
3453 +
3454 +/* Pure 2^n version of get_order */
3455 +static inline int get_order(unsigned long size)
3456 +{
3457 + int order;
3458 +
3459 + size = (size-1) >> (PAGE_SHIFT-1);
3460 + order = -1;
3461 + do {
3462 + size >>= 1;
3463 + order++;
3464 + } while (size);
3465 + return order;
3466 +}
3467 +
3468 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
3469 + dma_addr_t *dma_handle)
3470 +{
3471 + void *ret;
3472 + int gfp = GFP_ATOMIC | GFP_DMA;
3473 +
3474 + ret = (void *)__get_free_pages(gfp, get_order(size));
3475 +
3476 + if (ret != NULL) {
3477 + memset(ret, 0, size);
3478 + *dma_handle = virt_to_bus(ret);
3479 + }
3480 + return ret;
3481 +}
3482 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
3483 + void *vaddr, dma_addr_t dma_handle)
3484 +{
3485 + free_pages((unsigned long)vaddr, get_order(size));
3486 +}
3487 +#ifdef ILSIM
3488 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
3489 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
3490 +#else
3491 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
3492 +#define pci_unmap_single(cookie, address, size, dir)
3493 +#endif
3494 +
3495 +#endif /* DMA mapping */
3496 +
3497 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
3498 +
3499 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
3500 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
3501 +
3502 +/* pcmcia-cs provides its own netdevice compatibility layer */
3503 +#ifndef _COMPAT_NETDEVICE_H
3504 +
3505 +/*
3506 + * SoftNet
3507 + *
3508 + * For pre-softnet kernels we need to tell the upper layer not to
3509 + * re-enter start_xmit() while we are in there. However softnet
3510 + * guarantees not to enter while we are in there so there is no need
3511 + * to do the netif_stop_queue() dance unless the transmit queue really
3512 + * gets stuck. This should also improve performance according to tests
3513 + * done by Aman Singla.
3514 + */
3515 +
3516 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
3517 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
3518 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
3519 +
3520 +static inline void netif_start_queue(struct net_device *dev)
3521 +{
3522 + dev->tbusy = 0;
3523 + dev->interrupt = 0;
3524 + dev->start = 1;
3525 +}
3526 +
3527 +#define netif_queue_stopped(dev) (dev)->tbusy
3528 +#define netif_running(dev) (dev)->start
3529 +
3530 +#endif /* _COMPAT_NETDEVICE_H */
3531 +
3532 +#define netif_device_attach(dev) netif_start_queue(dev)
3533 +#define netif_device_detach(dev) netif_stop_queue(dev)
3534 +
3535 +/* 2.4.x renamed bottom halves to tasklets */
3536 +#define tasklet_struct tq_struct
3537 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
3538 +{
3539 + queue_task(tasklet, &tq_immediate);
3540 + mark_bh(IMMEDIATE_BH);
3541 +}
3542 +
3543 +static inline void tasklet_init(struct tasklet_struct *tasklet,
3544 + void (*func)(unsigned long),
3545 + unsigned long data)
3546 +{
3547 + tasklet->next = NULL;
3548 + tasklet->sync = 0;
3549 + tasklet->routine = (void (*)(void *))func;
3550 + tasklet->data = (void *)data;
3551 +}
3552 +#define tasklet_kill(tasklet) {do{} while(0);}
3553 +
3554 +/* 2.4.x introduced del_timer_sync() */
3555 +#define del_timer_sync(timer) del_timer(timer)
3556 +
3557 +#else
3558 +
3559 +#define netif_down(dev)
3560 +
3561 +#endif /* SoftNet */
3562 +
3563 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
3564 +
3565 +/*
3566 + * Emit code to initialise a tq_struct's routine and data pointers
3567 + */
3568 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
3569 + do { \
3570 + (_tq)->routine = _routine; \
3571 + (_tq)->data = _data; \
3572 + } while (0)
3573 +
3574 +/*
3575 + * Emit code to initialise all of a tq_struct
3576 + */
3577 +#define INIT_TQUEUE(_tq, _routine, _data) \
3578 + do { \
3579 + INIT_LIST_HEAD(&(_tq)->list); \
3580 + (_tq)->sync = 0; \
3581 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
3582 + } while (0)
3583 +
3584 +#endif
3585 +
3586 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
3587 +
3588 +/* Power management related routines */
3589 +
3590 +static inline int
3591 +pci_save_state(struct pci_dev *dev, u32 *buffer)
3592 +{
3593 + int i;
3594 + if (buffer) {
3595 + for (i = 0; i < 16; i++)
3596 + pci_read_config_dword(dev, i * 4,&buffer[i]);
3597 + }
3598 + return 0;
3599 +}
3600 +
3601 +static inline int
3602 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
3603 +{
3604 + int i;
3605 +
3606 + if (buffer) {
3607 + for (i = 0; i < 16; i++)
3608 + pci_write_config_dword(dev,i * 4, buffer[i]);
3609 + }
3610 + /*
3611 + * otherwise, write the context information we know from bootup.
3612 + * This works around a problem where warm-booting from Windows
3613 + * combined with a D3(hot)->D0 transition causes PCI config
3614 + * header data to be forgotten.
3615 + */
3616 + else {
3617 + for (i = 0; i < 6; i ++)
3618 + pci_write_config_dword(dev,
3619 + PCI_BASE_ADDRESS_0 + (i * 4),
3620 + pci_resource_start(dev, i));
3621 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3622 + }
3623 + return 0;
3624 +}
3625 +
3626 +#endif /* PCI power management */
3627 +
3628 +/* Old cp0 access macros deprecated in 2.4.19 */
3629 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
3630 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
3631 +#endif
3632 +
3633 +/* Module refcount handled internally in 2.6.x */
3634 +#ifndef SET_MODULE_OWNER
3635 +#define SET_MODULE_OWNER(dev) do {} while (0)
3636 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
3637 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
3638 +#else
3639 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
3640 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
3641 +#endif
3642 +
3643 +#ifndef SET_NETDEV_DEV
3644 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
3645 +#endif
3646 +
3647 +#ifndef HAVE_FREE_NETDEV
3648 +#define free_netdev(dev) kfree(dev)
3649 +#endif
3650 +
3651 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3652 +/* struct packet_type redefined in 2.6.x */
3653 +#define af_packet_priv data
3654 +#endif
3655 +
3656 +#endif /* _linuxver_h_ */
3657 diff -urN linux.old/arch/mips/bcm947xx/include/min_osl.h linux.dev/arch/mips/bcm947xx/include/min_osl.h
3658 --- linux.old/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
3659 +++ linux.dev/arch/mips/bcm947xx/include/min_osl.h 2005-11-07 22:51:38.780726250 +0100
3660 @@ -0,0 +1,126 @@
3661 +/*
3662 + * HND Minimal OS Abstraction Layer.
3663 + *
3664 + * Copyright 2005, Broadcom Corporation
3665 + * All Rights Reserved.
3666 + *
3667 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3668 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3669 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3670 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3671 + *
3672 + * $Id$
3673 + */
3674 +
3675 +#ifndef _min_osl_h_
3676 +#define _min_osl_h_
3677 +
3678 +#include <typedefs.h>
3679 +#include <sbconfig.h>
3680 +#include <mipsinc.h>
3681 +
3682 +/* Cache support */
3683 +extern void caches_on(void);
3684 +extern void blast_dcache(void);
3685 +extern void blast_icache(void);
3686 +
3687 +/* uart output */
3688 +extern void putc(int c);
3689 +
3690 +/* lib functions */
3691 +extern int printf(const char *fmt, ...);
3692 +extern int sprintf(char *buf, const char *fmt, ...);
3693 +extern int strcmp(const char *s1, const char *s2);
3694 +extern int strncmp(const char *s1, const char *s2, uint n);
3695 +extern char *strcpy(char *dest, const char *src);
3696 +extern char *strncpy(char *dest, const char *src, uint n);
3697 +extern uint strlen(const char *s);
3698 +extern char *strchr(const char *str,int c);
3699 +extern char *strrchr(const char *str, int c);
3700 +extern char *strcat(char *d, const char *s);
3701 +extern void *memset(void *dest, int c, uint n);
3702 +extern void *memcpy(void *dest, const void *src, uint n);
3703 +extern int memcmp(const void *s1, const void *s2, uint n);
3704 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3705 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3706 +#define bzero(b, len) memset((b), '\0', (len))
3707 +
3708 +/* assert & debugging */
3709 +#define ASSERT(exp) do {} while (0)
3710 +
3711 +/* PCMCIA attribute space access macros */
3712 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3713 + ASSERT(0)
3714 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3715 + ASSERT(0)
3716 +
3717 +/* PCI configuration space access macros */
3718 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
3719 + (offset == 8 ? 0 : 0xffffffff)
3720 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
3721 + do {} while (0)
3722 +
3723 +/* PCI device bus # and slot # */
3724 +#define OSL_PCI_BUS(osh) (0)
3725 +#define OSL_PCI_SLOT(osh) (0)
3726 +
3727 +/* register access macros */
3728 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
3729 +#define rreg32(r) (*(volatile uint32*)(r))
3730 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
3731 +#define rreg16(r) (*(volatile uint16*)(r))
3732 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
3733 +#define rreg8(r) (*(volatile uint8*)(r))
3734 +#define R_REG(r) ({ \
3735 + __typeof(*(r)) __osl_v; \
3736 + switch (sizeof(*(r))) { \
3737 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
3738 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
3739 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
3740 + } \
3741 + __osl_v; \
3742 +})
3743 +#define W_REG(r, v) do { \
3744 + switch (sizeof(*(r))) { \
3745 + case sizeof(uint8): wreg8((r), (v)); break; \
3746 + case sizeof(uint16): wreg16((r), (v)); break; \
3747 + case sizeof(uint32): wreg32((r), (v)); break; \
3748 + } \
3749 +} while (0)
3750 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3751 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3752 +
3753 +/* general purpose memory allocation */
3754 +#define MALLOC(osh, size) malloc(size)
3755 +#define MFREE(osh, addr, size) free(addr)
3756 +#define MALLOCED(osh) 0
3757 +#define MALLOC_FAILED(osh) 0
3758 +#define MALLOC_DUMP(osh, buf, sz)
3759 +extern int free(void *ptr);
3760 +extern void *malloc(uint size);
3761 +
3762 +/* uncached virtual address */
3763 +#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
3764 +
3765 +/* host/bus architecture-specific address byte swap */
3766 +#define BUS_SWAP32(v) (v)
3767 +
3768 +/* microsecond delay */
3769 +#define OSL_DELAY(usec) udelay(usec)
3770 +extern void udelay(uint32 usec);
3771 +
3772 +/* map/unmap physical to virtual I/O */
3773 +#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
3774 +#define REG_UNMAP(va) do {} while (0)
3775 +
3776 +/* dereference an address that may cause a bus exception */
3777 +#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
3778 +
3779 +/* Misc stubs */
3780 +#define osl_attach(pdev) ((osl_t*)pdev)
3781 +#define osl_detach(osh)
3782 +extern void *osl_init(void);
3783 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3784 +extern int osl_error(int);
3785 +
3786 +#endif /* _min_osl_h_ */
3787 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
3788 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
3789 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-11-07 22:51:38.780726250 +0100
3790 @@ -0,0 +1,552 @@
3791 +/*
3792 + * HND Run Time Environment for standalone MIPS programs.
3793 + *
3794 + * Copyright 2005, Broadcom Corporation
3795 + * All Rights Reserved.
3796 + *
3797 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3798 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3799 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3800 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3801 + *
3802 + * $Id$
3803 + */
3804 +
3805 +#ifndef _MISPINC_H
3806 +#define _MISPINC_H
3807 +
3808 +
3809 +/* MIPS defines */
3810 +
3811 +#ifdef _LANGUAGE_ASSEMBLY
3812 +
3813 +/*
3814 + * Symbolic register names for 32 bit ABI
3815 + */
3816 +#define zero $0 /* wired zero */
3817 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
3818 +#define v0 $2 /* return value */
3819 +#define v1 $3
3820 +#define a0 $4 /* argument registers */
3821 +#define a1 $5
3822 +#define a2 $6
3823 +#define a3 $7
3824 +#define t0 $8 /* caller saved */
3825 +#define t1 $9
3826 +#define t2 $10
3827 +#define t3 $11
3828 +#define t4 $12
3829 +#define t5 $13
3830 +#define t6 $14
3831 +#define t7 $15
3832 +#define s0 $16 /* callee saved */
3833 +#define s1 $17
3834 +#define s2 $18
3835 +#define s3 $19
3836 +#define s4 $20
3837 +#define s5 $21
3838 +#define s6 $22
3839 +#define s7 $23
3840 +#define t8 $24 /* caller saved */
3841 +#define t9 $25
3842 +#define jp $25 /* PIC jump register */
3843 +#define k0 $26 /* kernel scratch */
3844 +#define k1 $27
3845 +#define gp $28 /* global pointer */
3846 +#define sp $29 /* stack pointer */
3847 +#define fp $30 /* frame pointer */
3848 +#define s8 $30 /* same like fp! */
3849 +#define ra $31 /* return address */
3850 +
3851 +
3852 +/*
3853 + * CP0 Registers
3854 + */
3855 +
3856 +#define C0_INX $0
3857 +#define C0_RAND $1
3858 +#define C0_TLBLO0 $2
3859 +#define C0_TLBLO C0_TLBLO0
3860 +#define C0_TLBLO1 $3
3861 +#define C0_CTEXT $4
3862 +#define C0_PGMASK $5
3863 +#define C0_WIRED $6
3864 +#define C0_BADVADDR $8
3865 +#define C0_COUNT $9
3866 +#define C0_TLBHI $10
3867 +#define C0_COMPARE $11
3868 +#define C0_SR $12
3869 +#define C0_STATUS C0_SR
3870 +#define C0_CAUSE $13
3871 +#define C0_EPC $14
3872 +#define C0_PRID $15
3873 +#define C0_CONFIG $16
3874 +#define C0_LLADDR $17
3875 +#define C0_WATCHLO $18
3876 +#define C0_WATCHHI $19
3877 +#define C0_XCTEXT $20
3878 +#define C0_DIAGNOSTIC $22
3879 +#define C0_BROADCOM C0_DIAGNOSTIC
3880 +#define C0_PERFORMANCE $25
3881 +#define C0_ECC $26
3882 +#define C0_CACHEERR $27
3883 +#define C0_TAGLO $28
3884 +#define C0_TAGHI $29
3885 +#define C0_ERREPC $30
3886 +#define C0_DESAVE $31
3887 +
3888 +/*
3889 + * LEAF - declare leaf routine
3890 + */
3891 +#define LEAF(symbol) \
3892 + .globl symbol; \
3893 + .align 2; \
3894 + .type symbol,@function; \
3895 + .ent symbol,0; \
3896 +symbol: .frame sp,0,ra
3897 +
3898 +/*
3899 + * END - mark end of function
3900 + */
3901 +#define END(function) \
3902 + .end function; \
3903 + .size function,.-function
3904 +
3905 +#define _ULCAST_
3906 +
3907 +#else
3908 +
3909 +/*
3910 + * The following macros are especially useful for __asm__
3911 + * inline assembler.
3912 + */
3913 +#ifndef __STR
3914 +#define __STR(x) #x
3915 +#endif
3916 +#ifndef STR
3917 +#define STR(x) __STR(x)
3918 +#endif
3919 +
3920 +#define _ULCAST_ (unsigned long)
3921 +
3922 +
3923 +/*
3924 + * CP0 Registers
3925 + */
3926 +
3927 +#define C0_INX 0 /* CP0: TLB Index */
3928 +#define C0_RAND 1 /* CP0: TLB Random */
3929 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
3930 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
3931 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
3932 +#define C0_CTEXT 4 /* CP0: Context */
3933 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
3934 +#define C0_WIRED 6 /* CP0: TLB Wired */
3935 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
3936 +#define C0_COUNT 9 /* CP0: Count */
3937 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
3938 +#define C0_COMPARE 11 /* CP0: Compare */
3939 +#define C0_SR 12 /* CP0: Processor Status */
3940 +#define C0_STATUS C0_SR /* CP0: Processor Status */
3941 +#define C0_CAUSE 13 /* CP0: Exception Cause */
3942 +#define C0_EPC 14 /* CP0: Exception PC */
3943 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
3944 +#define C0_CONFIG 16 /* CP0: Config */
3945 +#define C0_LLADDR 17 /* CP0: LLAddr */
3946 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
3947 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
3948 +#define C0_XCTEXT 20 /* CP0: XContext */
3949 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
3950 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
3951 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
3952 +#define C0_ECC 26 /* CP0: ECC */
3953 +#define C0_CACHEERR 27 /* CP0: CacheErr */
3954 +#define C0_TAGLO 28 /* CP0: TagLo */
3955 +#define C0_TAGHI 29 /* CP0: TagHi */
3956 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
3957 +#define C0_DESAVE 31 /* CP0: DebugSave */
3958 +
3959 +#endif /* _LANGUAGE_ASSEMBLY */
3960 +
3961 +/*
3962 + * Memory segments (32bit kernel mode addresses)
3963 + */
3964 +#undef KUSEG
3965 +#undef KSEG0
3966 +#undef KSEG1
3967 +#undef KSEG2
3968 +#undef KSEG3
3969 +#define KUSEG 0x00000000
3970 +#define KSEG0 0x80000000
3971 +#define KSEG1 0xa0000000
3972 +#define KSEG2 0xc0000000
3973 +#define KSEG3 0xe0000000
3974 +#define PHYSADDR_MASK 0x1fffffff
3975 +
3976 +/*
3977 + * Map an address to a certain kernel segment
3978 + */
3979 +#undef PHYSADDR
3980 +#undef KSEG0ADDR
3981 +#undef KSEG1ADDR
3982 +#undef KSEG2ADDR
3983 +#undef KSEG3ADDR
3984 +
3985 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
3986 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
3987 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
3988 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
3989 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
3990 +
3991 +
3992 +#ifndef Index_Invalidate_I
3993 +/*
3994 + * Cache Operations
3995 + */
3996 +#define Index_Invalidate_I 0x00
3997 +#define Index_Writeback_Inv_D 0x01
3998 +#define Index_Invalidate_SI 0x02
3999 +#define Index_Writeback_Inv_SD 0x03
4000 +#define Index_Load_Tag_I 0x04
4001 +#define Index_Load_Tag_D 0x05
4002 +#define Index_Load_Tag_SI 0x06
4003 +#define Index_Load_Tag_SD 0x07