add missing copyright info
[openwrt/svn-archive/archive.git] / openwrt / target / linux / package / switch / src / switch-adm.c
1 /*
2 * ADMTEK Adm6996 switch configuration module
3 *
4 * Copyright (C) 2005 Felix Fietkau <nbd@nbd.name>
5 *
6 * Partially based on Broadcom Home Networking Division 10/100 Mbit/s
7 * Ethernet Device Driver (from Montavista 2.4.20_mvl31 Kernel).
8 * Copyright (C) 2004 Broadcom Corporation
9 *
10 * adm_rreg function from adm6996
11 * Copyright (C) 2004 Nikki Chumakov <nikki@gattaca.ru>
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA.
27 */
28
29 #include <linux/config.h>
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <linux/if.h>
33 #include <linux/if_arp.h>
34 #include <linux/sockios.h>
35 #include <linux/delay.h>
36 #include <asm/uaccess.h>
37
38 #include "switch-core.h"
39 #include "gpio.h"
40
41 #define DRIVER_NAME "adm6996"
42 #define DRIVER_VERSION "0.01"
43
44 static int eecs = 0;
45 static int eesk = 0;
46 static int eedi = 0;
47 static int eerc = 0;
48 static int force = 0;
49
50 MODULE_AUTHOR("Felix Fietkau <openwrt@nbd.name>");
51 MODULE_LICENSE("GPL");
52 MODULE_PARM(eecs, "i");
53 MODULE_PARM(eesk, "i");
54 MODULE_PARM(eedi, "i");
55 MODULE_PARM(eerc, "i");
56 MODULE_PARM(force, "i");
57
58 /* Minimum timing constants */
59 #define EECK_EDGE_TIME 3 /* 3us - max(adm 2.5us, 93c 1us) */
60 #define EEDI_SETUP_TIME 1 /* 1us - max(adm 10ns, 93c 400ns) */
61 #define EECS_SETUP_TIME 1 /* 1us - max(adm no, 93c 200ns) */
62
63 /* Handy macros for writing fixed length values */
64 #define adm_write8(cs, b) { __u8 val = (__u8) (b); adm_write(cs, &val, sizeof(val)*8); }
65 #define adm_write16(cs, w) { __u16 val = hton16(w); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
66 #define adm_write32(cs, i) { uint32 val = hton32(i); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
67
68 #define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
69
70 #if defined(BCMGPIO2) || defined(BCMGPIO)
71 extern char *nvram_get(char *name);
72
73 /* Return gpio pin number assigned to the named pin */
74 /*
75 * Variable should be in format:
76 *
77 * gpio<N>=pin_name
78 *
79 * 'def_pin' is returned if there is no such variable found.
80 */
81 static unsigned int getgpiopin(char *pin_name, unsigned int def_pin)
82 {
83 char name[] = "gpioXXXX";
84 char *val;
85 unsigned int pin;
86
87 /* Go thru all possibilities till a match in pin name */
88 for (pin = 0; pin < 16; pin ++) {
89 sprintf(name, "gpio%d", pin);
90 val = nvram_get(name);
91 if (val && !strcmp(val, pin_name))
92 return pin;
93 }
94 return def_pin;
95 }
96 #endif
97
98
99 static void adm_write(int cs, char *buf, unsigned int bits)
100 {
101 int i, len = (bits + 7) / 8;
102 __u8 mask;
103
104 gpioout(eecs, (cs ? eecs : 0));
105 udelay(EECK_EDGE_TIME);
106
107 /* Byte assemble from MSB to LSB */
108 for (i = 0; i < len; i++) {
109 /* Bit bang from MSB to LSB */
110 for (mask = 0x80; mask && bits > 0; mask >>= 1, bits --) {
111 /* Clock low */
112 gpioout(eesk, 0);
113 udelay(EECK_EDGE_TIME);
114
115 /* Output on rising edge */
116 gpioout(eedi, ((mask & buf[i]) ? eedi : 0));
117 udelay(EEDI_SETUP_TIME);
118
119 /* Clock high */
120 gpioout(eesk, eesk);
121 udelay(EECK_EDGE_TIME);
122 }
123 }
124
125 /* Clock low */
126 gpioout(eesk, 0);
127 udelay(EECK_EDGE_TIME);
128
129 if (cs)
130 gpioout(eecs, 0);
131 }
132
133
134 static void adm_read(int cs, char *buf, unsigned int bits)
135 {
136 int i, len = (bits + 7) / 8;
137 __u8 mask;
138
139 gpioout(eecs, (cs ? eecs : 0));
140 udelay(EECK_EDGE_TIME);
141
142 /* Byte assemble from MSB to LSB */
143 for (i = 0; i < len; i++) {
144 __u8 byte;
145
146 /* Bit bang from MSB to LSB */
147 for (mask = 0x80, byte = 0; mask && bits > 0; mask >>= 1, bits --) {
148 __u8 gp;
149
150 /* Clock low */
151 gpioout(eesk, 0);
152 udelay(EECK_EDGE_TIME);
153
154 /* Input on rising edge */
155 gp = gpioin();
156 if (gp & eedi)
157 byte |= mask;
158
159 /* Clock high */
160 gpioout(eesk, eesk);
161 udelay(EECK_EDGE_TIME);
162 }
163
164 *buf++ = byte;
165 }
166
167 /* Clock low */
168 gpioout(eesk, 0);
169 udelay(EECK_EDGE_TIME);
170
171 if (cs)
172 gpioout(eecs, 0);
173 }
174
175
176 /* Enable outputs with specified value to the chip */
177 static void adm_enout(__u8 pins, __u8 val)
178 {
179 /* Prepare GPIO output value */
180 gpioout(pins, val);
181
182 /* Enable GPIO outputs */
183 gpioouten(pins, pins);
184 udelay(EECK_EDGE_TIME);
185 }
186
187
188 /* Disable outputs to the chip */
189 static void adm_disout(__u8 pins)
190 {
191 /* Disable GPIO outputs */
192 gpioouten(pins, 0);
193 udelay(EECK_EDGE_TIME);
194 }
195
196
197 /* Advance clock(s) */
198 static void adm_adclk(int clocks)
199 {
200 int i;
201 for (i = 0; i < clocks; i++) {
202 /* Clock high */
203 gpioout(eesk, eesk);
204 udelay(EECK_EDGE_TIME);
205
206 /* Clock low */
207 gpioout(eesk, 0);
208 udelay(EECK_EDGE_TIME);
209 }
210 }
211
212 static __u32 adm_rreg(__u8 table, __u8 addr)
213 {
214 /* cmd: 01 10 T DD R RRRRRR */
215 __u8 bits[6] = {
216 0xFF, 0xFF, 0xFF, 0xFF,
217 (0x06 << 4) | ((table & 0x01) << 3 | (addr&64)>>6),
218 ((addr&62)<<2)
219 };
220
221 __u8 rbits[4];
222
223 /* Enable GPIO outputs with all pins to 0 */
224 adm_enout((__u8)(eecs | eesk | eedi), 0);
225
226 adm_write(0, bits, 46);
227 adm_disout((__u8)(eedi));
228 adm_adclk(2);
229 adm_read (0, rbits, 32);
230
231 /* Extra clock(s) required per datasheet */
232 adm_adclk(2);
233
234 /* Disable GPIO outputs */
235 adm_disout((__u8)(eecs | eesk));
236
237 if (!table) /* EEPROM has 16-bit registers, but pumps out two registers in one request */
238 return (addr & 0x01 ? (rbits[0]<<8) | rbits[1] : (rbits[2]<<8) | (rbits[3]));
239 else
240 return (rbits[0]<<24) | (rbits[1]<<16) | (rbits[2]<<8) | rbits[3];
241 }
242
243
244
245 /* Write chip configuration register */
246 /* Follow 93c66 timing and chip's min EEPROM timing requirement */
247 void
248 adm_wreg(__u8 addr, __u16 val)
249 {
250 /* cmd(27bits): sb(1) + opc(01) + addr(bbbbbbbb) + data(bbbbbbbbbbbbbbbb) */
251 __u8 bits[4] = {
252 (0x05 << 5) | (addr >> 3),
253 (addr << 5) | (__u8)(val >> 11),
254 (__u8)(val >> 3),
255 (__u8)(val << 5)
256 };
257
258 /* Enable GPIO outputs with all pins to 0 */
259 adm_enout((__u8)(eecs | eesk | eedi), 0);
260
261 /* Write cmd. Total 27 bits */
262 adm_write(1, bits, 27);
263
264 /* Extra clock(s) required per datasheet */
265 adm_adclk(2);
266
267 /* Disable GPIO outputs */
268 adm_disout((__u8)(eecs | eesk | eedi));
269 }
270
271
272 /* Port configuration registers */
273 static int port_conf[] = { 0x01, 0x03, 0x05, 0x07, 0x08, 0x09 };
274
275 /* Bits in VLAN port mapping */
276 static int vlan_ports[] = { 1 << 0, 1 << 2, 1 << 4, 1 << 6, 1 << 7, 1 << 8 };
277
278 static int handle_vlan_port_read(void *driver, char *buf, int nr)
279 {
280 int ports, i, c, len = 0;
281
282 if ((nr < 0) || (nr > 15))
283 return 0;
284
285 /* Get VLAN port map */
286 ports = adm_rreg(0, 0x13 + nr);
287
288 for (i = 0; i <= 5; i++) {
289 if (ports & vlan_ports[i]) {
290 c = adm_rreg(0, port_conf[i]);
291
292 len += sprintf(buf + len, "%d", i);
293 if (c & (1 << 4)) {
294 buf[len++] = 't';
295 if (((c & (0xf << 10)) >> 10) == nr)
296 buf[len++] = '*';
297 } else if (i == 5)
298 buf[len++] = 'u';
299
300 buf[len++] = '\t';
301 }
302 }
303 len += sprintf(buf + len, "\n");
304
305 return len;
306 }
307
308 static int handle_vlan_port_write(void *driver, char *buf, int nr)
309 {
310 int i, cfg, ports;
311 switch_driver *d = (switch_driver *) driver;
312 switch_vlan_config *c = switch_parse_vlan(d, buf);
313
314 if (c == NULL)
315 return -1;
316
317 ports = adm_rreg(0, 0x13 + nr);
318 for (i = 0; i < d->ports; i++) {
319 if (c->port & (1 << i)) {
320 ports |= vlan_ports[i];
321
322 cfg = adm_rreg(0, port_conf[i]);
323
324 /* Tagging */
325 if (c->untag & (1 << i))
326 cfg &= ~(1 << 4);
327 else
328 cfg |= (1 << 4);
329
330 if ((c->untag | c->pvid) & (1 << i)) {
331 cfg = (cfg & ~(0xf << 10)) | (nr << 10);
332 }
333
334 adm_wreg(port_conf[i], (__u16) cfg);
335 } else {
336 ports &= ~(vlan_ports[i]);
337 }
338 }
339 adm_wreg(0x13 + nr, (__u16) ports);
340
341 return 0;
342 }
343
344 static int handle_port_enable_read(void *driver, char *buf, int nr)
345 {
346 return sprintf(buf, "%d\n", ((adm_rreg(0, port_conf[nr]) & (1 << 5)) ? 0 : 1));
347 }
348
349 static int handle_port_enable_write(void *driver, char *buf, int nr)
350 {
351 int reg = adm_rreg(0, port_conf[nr]);
352
353 if (buf[0] == '0')
354 reg |= (1 << 5);
355 else if (buf[0] == '1')
356 reg &= ~(1 << 5);
357 else return -1;
358
359 adm_wreg(port_conf[nr], (__u16) reg);
360 return 0;
361 }
362
363 static int handle_port_media_read(void *driver, char *buf, int nr)
364 {
365 int len;
366 int media = 0;
367 int reg = adm_rreg(0, port_conf[nr]);
368
369 if (reg & (1 << 1))
370 media |= SWITCH_MEDIA_AUTO;
371 if (reg & (1 << 2))
372 media |= SWITCH_MEDIA_100;
373 if (reg & (1 << 3))
374 media |= SWITCH_MEDIA_FD;
375
376 len = switch_print_media(buf, media);
377 return len + sprintf(buf + len, "\n");
378 }
379
380 static int handle_port_media_write(void *driver, char *buf, int nr)
381 {
382 int media = switch_parse_media(buf);
383 int reg = adm_rreg(0, port_conf[nr]);
384
385 if (media < 0)
386 return -1;
387
388 reg &= ~((1 << 1) | (1 << 2) | (1 << 3));
389 if (media & SWITCH_MEDIA_AUTO)
390 reg |= 1 << 1;
391 if (media & SWITCH_MEDIA_100)
392 reg |= 1 << 2;
393 if (media & SWITCH_MEDIA_FD)
394 reg |= 1 << 3;
395
396 adm_wreg(port_conf[nr], reg);
397
398 return 0;
399 }
400
401 static int handle_vlan_enable_read(void *driver, char *buf, int nr)
402 {
403 return sprintf(buf, "%d\n", ((adm_rreg(0, 0x11) & (1 << 5)) ? 1 : 0));
404 }
405
406 static int handle_vlan_enable_write(void *driver, char *buf, int nr)
407 {
408 int reg = adm_rreg(0, 0x11);
409
410 if (buf[0] == '1')
411 reg |= (1 << 5);
412 else if (buf[0] == '0')
413 reg &= ~(1 << 5);
414 else return -1;
415
416 adm_wreg(0x11, (__u16) reg);
417 return 0;
418 }
419
420 static int handle_reset(void *driver, char *buf, int nr)
421 {
422 int i;
423 u32 cfg;
424
425 /*
426 * Reset sequence: RC high->low(100ms)->high(30ms)
427 *
428 * WAR: Certain boards don't have the correct power on
429 * reset logic therefore we must explicitly perform the
430 * sequence in software.
431 */
432 if (eerc) {
433 /* Keep RC high for at least 20ms */
434 adm_enout(eerc, eerc);
435 for (i = 0; i < 20; i ++)
436 udelay(1000);
437 /* Keep RC low for at least 100ms */
438 adm_enout(eerc, 0);
439 for (i = 0; i < 100; i++)
440 udelay(1000);
441 /* Set default configuration */
442 adm_enout((__u8)(eesk | eedi), eesk);
443 /* Keep RC high for at least 30ms */
444 adm_enout(eerc, eerc);
445 for (i = 0; i < 30; i++)
446 udelay(1000);
447 /* Leave RC high and disable GPIO outputs */
448 adm_disout((__u8)(eecs | eesk | eedi));
449
450 }
451
452 /* set up initial configuration for cpu port */
453 cfg = (0x8000 | /* Auto MDIX */
454 (0xf << 10) | /* PVID */
455 (1 << 4) | /* Tagging */
456 0xf); /* full duplex, 100Mbps, auto neg, flow ctrl */
457 adm_wreg(port_conf[5], cfg);
458
459 /* vlan mode select register (0x11): vlan on, mac clone */
460 adm_wreg(0x11, 0xff30);
461
462 return 0;
463 }
464
465 static int handle_registers(void *driver, char *buf, int nr)
466 {
467 int i, len = 0;
468
469 for (i = 0; i <= 0x33; i++) {
470 len += sprintf(buf + len, "0x%02x: 0x%04x\n", i, adm_rreg(0, i));
471 }
472
473 return len;
474 }
475
476 static int handle_counters(void *driver, char *buf, int nr)
477 {
478 int i, len = 0;
479
480 for (i = 0; i <= 0x3c; i++) {
481 len += sprintf(buf + len, "0x%02x: 0x%08x\n", i, adm_rreg(1, i));
482 }
483
484 return len;
485 }
486
487 static int detect_adm()
488 {
489 int ret = 0;
490
491 #if defined(BCMGPIO2) || defined(BCMGPIO)
492 int boardflags = atoi(nvram_get("boardflags"));
493
494 if ((boardflags & 0x80) || force) {
495 ret = 1;
496
497 eecs = getgpiopin("adm_eecs", 2);
498 eesk = getgpiopin("adm_eesk", 3);
499 eedi = getgpiopin("adm_eedi", 4);
500 eerc = getgpiopin("adm_rc", 0);
501
502 } else if ((strcmp(nvram_get("boardtype") ?: "", "bcm94710dev") == 0) &&
503 (strncmp(nvram_get("boardnum") ?: "", "42", 2) == 0)) {
504 /* WRT54G v1.1 hack */
505 eecs = 2;
506 eesk = 3;
507 eedi = 5;
508
509 ret = 1;
510 } else
511 printk("BFL_ENETADM not set in boardflags. Use force=1 to ignore.\n");
512
513 if (eecs)
514 eecs = (1 << eecs);
515 if (eesk)
516 eesk = (1 << eesk);
517 if (eedi)
518 eedi = (1 << eedi);
519 if (eerc)
520 eerc = (1 << eerc);
521 #else
522 ret = 1;
523 #endif
524
525 return ret;
526 }
527
528 static int __init adm_init()
529 {
530 switch_config cfg[] = {
531 {"registers", handle_registers, NULL},
532 {"counters", handle_counters, NULL},
533 {"reset", NULL, handle_reset},
534 {"enable_vlan", handle_vlan_enable_read, handle_vlan_enable_write},
535 {NULL, NULL, NULL}
536 };
537 switch_config port[] = {
538 {"enable", handle_port_enable_read, handle_port_enable_write},
539 {"media", handle_port_media_read, handle_port_media_write},
540 {NULL, NULL, NULL}
541 };
542 switch_config vlan[] = {
543 {"ports", handle_vlan_port_read, handle_vlan_port_write},
544 {NULL, NULL, NULL}
545 };
546 switch_driver driver = {
547 name: DRIVER_NAME,
548 version: DRIVER_VERSION,
549 interface: "eth0",
550 ports: 6,
551 cpuport: 5,
552 vlans: 16,
553 driver_handlers: cfg,
554 port_handlers: port,
555 vlan_handlers: vlan,
556 };
557
558 if (!detect_adm())
559 return -ENODEV;
560
561 return switch_register_driver(&driver);
562 }
563
564 static void __exit adm_exit()
565 {
566 switch_unregister_driver(DRIVER_NAME);
567 }
568
569
570 module_init(adm_init);
571 module_exit(adm_exit);