sync kmod-switch with whiterussian
[openwrt/svn-archive/archive.git] / openwrt / target / linux / package / switch / src / switch-adm.c
1 /*
2 * ADMTEK Adm6996 switch configuration module
3 *
4 * Copyright (C) 2005 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * 02110-1301, USA.
20 */
21
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/if.h>
26 #include <linux/if_arp.h>
27 #include <linux/sockios.h>
28 #include <linux/delay.h>
29 #include <asm/uaccess.h>
30
31 #include "switch-core.h"
32 #include "gpio.h"
33
34 #define DRIVER_NAME "adm6996"
35 #define DRIVER_VERSION "0.01"
36
37 static int eecs = 0;
38 static int eesk = 0;
39 static int eedi = 0;
40 static int eerc = 0;
41 static int force = 0;
42
43 MODULE_AUTHOR("Felix Fietkau <openwrt@nbd.name>");
44 MODULE_LICENSE("GPL");
45 MODULE_PARM(eecs, "i");
46 MODULE_PARM(eesk, "i");
47 MODULE_PARM(eedi, "i");
48 MODULE_PARM(eerc, "i");
49 MODULE_PARM(force, "i");
50
51 /* Minimum timing constants */
52 #define EECK_EDGE_TIME 3 /* 3us - max(adm 2.5us, 93c 1us) */
53 #define EEDI_SETUP_TIME 1 /* 1us - max(adm 10ns, 93c 400ns) */
54 #define EECS_SETUP_TIME 1 /* 1us - max(adm no, 93c 200ns) */
55
56 /* Handy macros for writing fixed length values */
57 #define adm_write8(cs, b) { __u8 val = (__u8) (b); adm_write(cs, &val, sizeof(val)*8); }
58 #define adm_write16(cs, w) { __u16 val = hton16(w); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
59 #define adm_write32(cs, i) { uint32 val = hton32(i); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
60
61 #define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
62
63 #if defined(BCMGPIO2) || defined(BCMGPIO)
64 extern char *nvram_get(char *name);
65
66 /* Return gpio pin number assigned to the named pin */
67 /*
68 * Variable should be in format:
69 *
70 * gpio<N>=pin_name
71 *
72 * 'def_pin' is returned if there is no such variable found.
73 */
74 static unsigned int getgpiopin(char *pin_name, unsigned int def_pin)
75 {
76 char name[] = "gpioXXXX";
77 char *val;
78 unsigned int pin;
79
80 /* Go thru all possibilities till a match in pin name */
81 for (pin = 0; pin < 16; pin ++) {
82 sprintf(name, "gpio%d", pin);
83 val = nvram_get(name);
84 if (val && !strcmp(val, pin_name))
85 return pin;
86 }
87 return def_pin;
88 }
89 #endif
90
91
92 static void adm_write(int cs, char *buf, unsigned int bits)
93 {
94 int i, len = (bits + 7) / 8;
95 __u8 mask;
96
97 gpioout(eecs, (cs ? eecs : 0));
98 udelay(EECK_EDGE_TIME);
99
100 /* Byte assemble from MSB to LSB */
101 for (i = 0; i < len; i++) {
102 /* Bit bang from MSB to LSB */
103 for (mask = 0x80; mask && bits > 0; mask >>= 1, bits --) {
104 /* Clock low */
105 gpioout(eesk, 0);
106 udelay(EECK_EDGE_TIME);
107
108 /* Output on rising edge */
109 gpioout(eedi, ((mask & buf[i]) ? eedi : 0));
110 udelay(EEDI_SETUP_TIME);
111
112 /* Clock high */
113 gpioout(eesk, eesk);
114 udelay(EECK_EDGE_TIME);
115 }
116 }
117
118 /* Clock low */
119 gpioout(eesk, 0);
120 udelay(EECK_EDGE_TIME);
121
122 if (cs)
123 gpioout(eecs, 0);
124 }
125
126
127 static void adm_read(int cs, char *buf, unsigned int bits)
128 {
129 int i, len = (bits + 7) / 8;
130 __u8 mask;
131
132 gpioout(eecs, (cs ? eecs : 0));
133 udelay(EECK_EDGE_TIME);
134
135 /* Byte assemble from MSB to LSB */
136 for (i = 0; i < len; i++) {
137 __u8 byte;
138
139 /* Bit bang from MSB to LSB */
140 for (mask = 0x80, byte = 0; mask && bits > 0; mask >>= 1, bits --) {
141 __u8 gp;
142
143 /* Clock low */
144 gpioout(eesk, 0);
145 udelay(EECK_EDGE_TIME);
146
147 /* Input on rising edge */
148 gp = gpioin();
149 if (gp & eedi)
150 byte |= mask;
151
152 /* Clock high */
153 gpioout(eesk, eesk);
154 udelay(EECK_EDGE_TIME);
155 }
156
157 *buf++ = byte;
158 }
159
160 /* Clock low */
161 gpioout(eesk, 0);
162 udelay(EECK_EDGE_TIME);
163
164 if (cs)
165 gpioout(eecs, 0);
166 }
167
168
169 /* Enable outputs with specified value to the chip */
170 static void adm_enout(__u8 pins, __u8 val)
171 {
172 /* Prepare GPIO output value */
173 gpioout(pins, val);
174
175 /* Enable GPIO outputs */
176 gpioouten(pins, pins);
177 udelay(EECK_EDGE_TIME);
178 }
179
180
181 /* Disable outputs to the chip */
182 static void adm_disout(__u8 pins)
183 {
184 /* Disable GPIO outputs */
185 gpioouten(pins, 0);
186 udelay(EECK_EDGE_TIME);
187 }
188
189
190 /* Advance clock(s) */
191 static void adm_adclk(int clocks)
192 {
193 int i;
194 for (i = 0; i < clocks; i++) {
195 /* Clock high */
196 gpioout(eesk, eesk);
197 udelay(EECK_EDGE_TIME);
198
199 /* Clock low */
200 gpioout(eesk, 0);
201 udelay(EECK_EDGE_TIME);
202 }
203 }
204
205 static __u32 adm_rreg(__u8 table, __u8 addr)
206 {
207 /* cmd: 01 10 T DD R RRRRRR */
208 __u8 bits[6] = {
209 0xFF, 0xFF, 0xFF, 0xFF,
210 (0x06 << 4) | ((table & 0x01) << 3 | (addr&64)>>6),
211 ((addr&62)<<2)
212 };
213
214 __u8 rbits[4];
215
216 /* Enable GPIO outputs with all pins to 0 */
217 adm_enout((__u8)(eecs | eesk | eedi), 0);
218
219 adm_write(0, bits, 46);
220 adm_disout((__u8)(eedi));
221 adm_adclk(2);
222 adm_read (0, rbits, 32);
223
224 /* Extra clock(s) required per datasheet */
225 adm_adclk(2);
226
227 /* Disable GPIO outputs */
228 adm_disout((__u8)(eecs | eesk));
229
230 if (!table) /* EEPROM has 16-bit registers, but pumps out two registers in one request */
231 return (addr & 0x01 ? (rbits[0]<<8) | rbits[1] : (rbits[2]<<8) | (rbits[3]));
232 else
233 return (rbits[0]<<24) | (rbits[1]<<16) | (rbits[2]<<8) | rbits[3];
234 }
235
236
237
238 /* Write chip configuration register */
239 /* Follow 93c66 timing and chip's min EEPROM timing requirement */
240 void
241 adm_wreg(__u8 addr, __u16 val)
242 {
243 /* cmd(27bits): sb(1) + opc(01) + addr(bbbbbbbb) + data(bbbbbbbbbbbbbbbb) */
244 __u8 bits[4] = {
245 (0x05 << 5) | (addr >> 3),
246 (addr << 5) | (__u8)(val >> 11),
247 (__u8)(val >> 3),
248 (__u8)(val << 5)
249 };
250
251 /* Enable GPIO outputs with all pins to 0 */
252 adm_enout((__u8)(eecs | eesk | eedi), 0);
253
254 /* Write cmd. Total 27 bits */
255 adm_write(1, bits, 27);
256
257 /* Extra clock(s) required per datasheet */
258 adm_adclk(2);
259
260 /* Disable GPIO outputs */
261 adm_disout((__u8)(eecs | eesk | eedi));
262 }
263
264
265 /* Port configuration registers */
266 static int port_conf[] = { 0x01, 0x03, 0x05, 0x07, 0x08, 0x09 };
267
268 /* Bits in VLAN port mapping */
269 static int vlan_ports[] = { 1 << 0, 1 << 2, 1 << 4, 1 << 6, 1 << 7, 1 << 8 };
270
271 static int handle_vlan_port_read(void *driver, char *buf, int nr)
272 {
273 int ports, i, c, len = 0;
274
275 if ((nr < 0) || (nr > 15))
276 return 0;
277
278 /* Get VLAN port map */
279 ports = adm_rreg(0, 0x13 + nr);
280
281 for (i = 0; i <= 5; i++) {
282 if (ports & vlan_ports[i]) {
283 c = adm_rreg(0, port_conf[i]);
284
285 len += sprintf(buf + len, "%d", i);
286 if (c & (1 << 4)) {
287 buf[len++] = 't';
288 if (((c & (0xf << 10)) >> 10) == nr)
289 buf[len++] = '*';
290 } else if (i == 5)
291 buf[len++] = 'u';
292
293 buf[len++] = '\t';
294 }
295 }
296 len += sprintf(buf + len, "\n");
297
298 return len;
299 }
300
301 static int handle_vlan_port_write(void *driver, char *buf, int nr)
302 {
303 int i, cfg, ports;
304 switch_driver *d = (switch_driver *) driver;
305 switch_vlan_config *c = switch_parse_vlan(d, buf);
306
307 if (c == NULL)
308 return -1;
309
310 ports = adm_rreg(0, 0x13 + nr);
311 for (i = 0; i < d->ports; i++) {
312 if (c->port & (1 << i)) {
313 ports |= vlan_ports[i];
314
315 cfg = adm_rreg(0, port_conf[i]);
316
317 /* Tagging */
318 if (c->untag & (1 << i))
319 cfg &= ~(1 << 4);
320 else
321 cfg |= (1 << 4);
322
323 if ((c->untag | c->pvid) & (1 << i)) {
324 cfg = (cfg & ~(0xf << 10)) | (nr << 10);
325 }
326
327 adm_wreg(port_conf[i], (__u16) cfg);
328 } else {
329 ports &= ~(vlan_ports[i]);
330 }
331 }
332 adm_wreg(0x13 + nr, (__u16) ports);
333
334 return 0;
335 }
336
337 static int handle_port_enable_read(void *driver, char *buf, int nr)
338 {
339 return sprintf(buf, "%d\n", ((adm_rreg(0, port_conf[nr]) & (1 << 5)) ? 0 : 1));
340 }
341
342 static int handle_port_enable_write(void *driver, char *buf, int nr)
343 {
344 int reg = adm_rreg(0, port_conf[nr]);
345
346 if (buf[0] == '0')
347 reg |= (1 << 5);
348 else if (buf[0] == '1')
349 reg &= ~(1 << 5);
350 else return -1;
351
352 adm_wreg(port_conf[nr], (__u16) reg);
353 return 0;
354 }
355
356 static int handle_port_media_read(void *driver, char *buf, int nr)
357 {
358 int len;
359 int media = 0;
360 int reg = adm_rreg(0, port_conf[nr]);
361
362 if (reg & (1 << 1))
363 media |= SWITCH_MEDIA_AUTO;
364 if (reg & (1 << 2))
365 media |= SWITCH_MEDIA_100;
366 if (reg & (1 << 3))
367 media |= SWITCH_MEDIA_FD;
368
369 len = switch_print_media(buf, media);
370 return len + sprintf(buf + len, "\n");
371 }
372
373 static int handle_port_media_write(void *driver, char *buf, int nr)
374 {
375 int media = switch_parse_media(buf);
376 int reg = adm_rreg(0, port_conf[nr]);
377
378 if (media < 0)
379 return -1;
380
381 reg &= ~((1 << 1) | (1 << 2) | (1 << 3));
382 if (media & SWITCH_MEDIA_AUTO)
383 reg |= 1 << 1;
384 if (media & SWITCH_MEDIA_100)
385 reg |= 1 << 2;
386 if (media & SWITCH_MEDIA_FD)
387 reg |= 1 << 3;
388
389 adm_wreg(port_conf[nr], reg);
390
391 return 0;
392 }
393
394 static int handle_vlan_enable_read(void *driver, char *buf, int nr)
395 {
396 return sprintf(buf, "%d\n", ((adm_rreg(0, 0x11) & (1 << 5)) ? 1 : 0));
397 }
398
399 static int handle_vlan_enable_write(void *driver, char *buf, int nr)
400 {
401 int reg = adm_rreg(0, 0x11);
402
403 if (buf[0] == '1')
404 reg |= (1 << 5);
405 else if (buf[0] == '0')
406 reg &= ~(1 << 5);
407 else return -1;
408
409 adm_wreg(0x11, (__u16) reg);
410 return 0;
411 }
412
413 static int handle_reset(void *driver, char *buf, int nr)
414 {
415 int i;
416 u32 cfg;
417
418 /*
419 * Reset sequence: RC high->low(100ms)->high(30ms)
420 *
421 * WAR: Certain boards don't have the correct power on
422 * reset logic therefore we must explicitly perform the
423 * sequence in software.
424 */
425 if (eerc) {
426 /* Keep RC high for at least 20ms */
427 adm_enout(eerc, eerc);
428 for (i = 0; i < 20; i ++)
429 udelay(1000);
430 /* Keep RC low for at least 100ms */
431 adm_enout(eerc, 0);
432 for (i = 0; i < 100; i++)
433 udelay(1000);
434 /* Set default configuration */
435 adm_enout((__u8)(eesk | eedi), eesk);
436 /* Keep RC high for at least 30ms */
437 adm_enout(eerc, eerc);
438 for (i = 0; i < 30; i++)
439 udelay(1000);
440 /* Leave RC high and disable GPIO outputs */
441 adm_disout((__u8)(eecs | eesk | eedi));
442
443 }
444
445 /* set up initial configuration for cpu port */
446 cfg = (0x8000 | /* Auto MDIX */
447 (0xf << 10) | /* PVID */
448 (1 << 4) | /* Tagging */
449 0xf); /* full duplex, 100Mbps, auto neg, flow ctrl */
450 adm_wreg(port_conf[5], cfg);
451
452 /* vlan mode select register (0x11): vlan on, mac clone */
453 adm_wreg(0x11, 0xff30);
454
455 return 0;
456 }
457
458 static int handle_registers(void *driver, char *buf, int nr)
459 {
460 int i, len = 0;
461
462 for (i = 0; i <= 0x33; i++) {
463 len += sprintf(buf + len, "0x%02x: 0x%04x\n", i, adm_rreg(0, i));
464 }
465
466 return len;
467 }
468
469 static int handle_counters(void *driver, char *buf, int nr)
470 {
471 int i, len = 0;
472
473 for (i = 0; i <= 0x3c; i++) {
474 len += sprintf(buf + len, "0x%02x: 0x%08x\n", i, adm_rreg(1, i));
475 }
476
477 return len;
478 }
479
480 static int detect_adm()
481 {
482 int ret = 0;
483
484 #if defined(BCMGPIO2) || defined(BCMGPIO)
485 int boardflags = atoi(nvram_get("boardflags"));
486
487 if ((boardflags & 0x80) || force) {
488 ret = 1;
489
490 eecs = getgpiopin("adm_eecs", 2);
491 eesk = getgpiopin("adm_eesk", 3);
492 eedi = getgpiopin("adm_eedi", 4);
493 eerc = getgpiopin("adm_rc", 0);
494
495 } else if ((strcmp(nvram_get("boardtype") ?: "", "bcm94710dev") == 0) &&
496 (strncmp(nvram_get("boardnum") ?: "", "42", 2) == 0)) {
497 /* WRT54G v1.1 hack */
498 eecs = 2;
499 eesk = 3;
500 eedi = 5;
501
502 ret = 1;
503 } else
504 printk("BFL_ENETADM not set in boardflags. Use force=1 to ignore.\n");
505
506 if (eecs)
507 eecs = (1 << eecs);
508 if (eesk)
509 eesk = (1 << eesk);
510 if (eedi)
511 eedi = (1 << eedi);
512 if (eerc)
513 eerc = (1 << eerc);
514 #else
515 ret = 1;
516 #endif
517
518 return ret;
519 }
520
521 static int __init adm_init()
522 {
523 switch_config cfg[] = {
524 {"registers", handle_registers, NULL},
525 {"counters", handle_counters, NULL},
526 {"reset", NULL, handle_reset},
527 {"enable_vlan", handle_vlan_enable_read, handle_vlan_enable_write},
528 {NULL, NULL, NULL}
529 };
530 switch_config port[] = {
531 {"enable", handle_port_enable_read, handle_port_enable_write},
532 {"media", handle_port_media_read, handle_port_media_write},
533 {NULL, NULL, NULL}
534 };
535 switch_config vlan[] = {
536 {"ports", handle_vlan_port_read, handle_vlan_port_write},
537 {NULL, NULL, NULL}
538 };
539 switch_driver driver = {
540 name: DRIVER_NAME,
541 version: DRIVER_VERSION,
542 interface: "eth0",
543 ports: 6,
544 cpuport: 5,
545 vlans: 16,
546 driver_handlers: cfg,
547 port_handlers: port,
548 vlan_handlers: vlan,
549 };
550
551 if (!detect_adm())
552 return -ENODEV;
553
554 return switch_register_driver(&driver);
555 }
556
557 static void __exit adm_exit()
558 {
559 switch_unregister_driver(DRIVER_NAME);
560 }
561
562
563 module_init(adm_init);
564 module_exit(adm_exit);