add the new ath9k driver (loads successfully on an AR9160 card, but still seems to...
[openwrt/svn-archive/archive.git] / package / ath9k / src / drivers / net / wireless / ath9k / hw.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18
19 #include "ath9k.h"
20 #include "hw.h"
21 #include "reg.h"
22 #include "phy.h"
23 #include "initvals.h"
24
25 static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
26 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains);
27 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
28 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
29 u_int8_t numChains);
30 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
31 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
32 u_int8_t numChains);
33
34 static const u_int8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
35 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
36
37 static const struct hal_percal_data iq_cal_multi_sample = {
38 IQ_MISMATCH_CAL,
39 MAX_CAL_SAMPLES,
40 PER_MIN_LOG_COUNT,
41 ath9k_hw_iqcal_collect,
42 ath9k_hw_iqcalibrate
43 };
44 static const struct hal_percal_data iq_cal_single_sample = {
45 IQ_MISMATCH_CAL,
46 MIN_CAL_SAMPLES,
47 PER_MAX_LOG_COUNT,
48 ath9k_hw_iqcal_collect,
49 ath9k_hw_iqcalibrate
50 };
51 static const struct hal_percal_data adc_gain_cal_multi_sample = {
52 ADC_GAIN_CAL,
53 MAX_CAL_SAMPLES,
54 PER_MIN_LOG_COUNT,
55 ath9k_hw_adc_gaincal_collect,
56 ath9k_hw_adc_gaincal_calibrate
57 };
58 static const struct hal_percal_data adc_gain_cal_single_sample = {
59 ADC_GAIN_CAL,
60 MIN_CAL_SAMPLES,
61 PER_MAX_LOG_COUNT,
62 ath9k_hw_adc_gaincal_collect,
63 ath9k_hw_adc_gaincal_calibrate
64 };
65 static const struct hal_percal_data adc_dc_cal_multi_sample = {
66 ADC_DC_CAL,
67 MAX_CAL_SAMPLES,
68 PER_MIN_LOG_COUNT,
69 ath9k_hw_adc_dccal_collect,
70 ath9k_hw_adc_dccal_calibrate
71 };
72 static const struct hal_percal_data adc_dc_cal_single_sample = {
73 ADC_DC_CAL,
74 MIN_CAL_SAMPLES,
75 PER_MAX_LOG_COUNT,
76 ath9k_hw_adc_dccal_collect,
77 ath9k_hw_adc_dccal_calibrate
78 };
79 static const struct hal_percal_data adc_init_dc_cal = {
80 ADC_DC_INIT_CAL,
81 MIN_CAL_SAMPLES,
82 INIT_LOG_COUNT,
83 ath9k_hw_adc_dccal_collect,
84 ath9k_hw_adc_dccal_calibrate
85 };
86
87 static const struct ath_hal ar5416hal = {
88 AR5416_MAGIC,
89 0,
90 0,
91 NULL,
92 NULL,
93 CTRY_DEFAULT,
94 0,
95 0,
96 0,
97 0,
98 0,
99 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
101 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
102 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
103 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
104 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
105 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
106 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
107 },
108 };
109
110 static struct hal_rate_table ar5416_11a_table = {
111 8,
112 {0},
113 {
114 {AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
115 {AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
116 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
117 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
118 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
119 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
120 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
121 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
122 },
123 };
124
125 static struct hal_rate_table ar5416_11b_table = {
126 4,
127 {0},
128 {
129 {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
130 {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
131 {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
132 {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
133 },
134 };
135
136 static struct hal_rate_table ar5416_11g_table = {
137 12,
138 {0},
139 {
140 {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
141 {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
142 {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
143 {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
144
145 {AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
146 {AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
147 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
148 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
149 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
150 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
151 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
152 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
153 },
154 };
155
156 static struct hal_rate_table ar5416_11ng_table = {
157 28,
158 {0},
159 {
160 {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
161 {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
162 {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
163 {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
164
165 {AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
166 {AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
167 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
168 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
169 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
170 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
171 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
172 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
173 {AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 4},
174 {AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 6},
175 {AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 6},
176 {AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 8},
177 {AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 8},
178 {AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 8},
179 {AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 8},
180 {AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 8},
181 {AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 4},
182 {AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 6},
183 {AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
184 {AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
185 {AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
186 {AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
187 {AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
188 {AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
189 },
190 };
191
192 static struct hal_rate_table ar5416_11na_table = {
193 24,
194 {0},
195 {
196 {AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
197 {AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
198 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
199 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
200 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
201 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
202 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
203 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
204 {AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 0},
205 {AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 2},
206 {AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 2},
207 {AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 4},
208 {AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 4},
209 {AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 4},
210 {AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 4},
211 {AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 4},
212 {AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 0},
213 {AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 2},
214 {AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
215 {AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
216 {AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
217 {AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
218 {AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
219 {AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
220 },
221 };
222
223 static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
224 const struct hal_channel *chan)
225 {
226 if (IS_CHAN_CCK(chan))
227 return WIRELESS_MODE_11b;
228 if (IS_CHAN_G(chan))
229 return WIRELESS_MODE_11g;
230 return WIRELESS_MODE_11a;
231 }
232
233 static enum hal_bool ath9k_hw_wait(struct ath_hal *ah,
234 u_int reg,
235 u_int32_t mask,
236 u_int32_t val)
237 {
238 int i;
239
240 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
241 if ((REG_READ(ah, reg) & mask) == val)
242 return AH_TRUE;
243
244 udelay(AH_TIME_QUANTUM);
245 }
246 HDPRINTF(ah, HAL_DBG_PHY_IO,
247 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
248 __func__, reg, REG_READ(ah, reg), mask, val);
249 return AH_FALSE;
250 }
251
252 static enum hal_bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
253 u_int16_t *data)
254 {
255 (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
256
257 if (!ath9k_hw_wait(ah,
258 AR_EEPROM_STATUS_DATA,
259 AR_EEPROM_STATUS_DATA_BUSY |
260 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
261 return AH_FALSE;
262 }
263
264 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
265 AR_EEPROM_STATUS_DATA_VAL);
266
267 return AH_TRUE;
268 }
269
270 static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
271 {
272 struct ath_hal_5416 *ahp = AH5416(ah);
273
274 ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
275
276 if (!ahp->ah_cal_mem) {
277 HDPRINTF(ah, HAL_DBG_EEPROM,
278 "%s: cannot remap eeprom region \n", __func__);
279 return HAL_EIO;
280 }
281
282 return HAL_OK;
283 }
284
285 static enum hal_bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
286 u_int16_t *data)
287 {
288 struct ath_hal_5416 *ahp = AH5416(ah);
289
290 *data = ioread16(ahp->ah_cal_mem + off);
291 return AH_TRUE;
292 }
293
294 static void ath9k_hw_read_revisions(struct ath_hal *ah)
295 {
296 u_int32_t val;
297
298 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
299
300 if (val == 0xFF) {
301 val = REG_READ(ah, AR_SREV);
302
303 ah->ah_macVersion =
304 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
305
306 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
307 ah->ah_isPciExpress =
308 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
309
310 } else {
311 if (!AR_SREV_9100(ah))
312 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
313
314 ah->ah_macRev = val & AR_SREV_REVISION;
315
316 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
317 ah->ah_isPciExpress = AH_TRUE;
318 }
319 }
320
321 u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n)
322 {
323 u_int32_t retval;
324 int i;
325
326 for (i = 0, retval = 0; i < n; i++) {
327 retval = (retval << 1) | (val & 1);
328 val >>= 1;
329 }
330 return retval;
331 }
332
333 static void ath9k_hw_set_defaults(struct ath_hal *ah)
334 {
335 int i;
336
337 ah->ah_config.ath_hal_dma_beacon_response_time = 2;
338 ah->ah_config.ath_hal_sw_beacon_response_time = 10;
339 ah->ah_config.ath_hal_additional_swba_backoff = 0;
340 ah->ah_config.ath_hal_6mb_ack = 0x0;
341 ah->ah_config.ath_hal_cwmIgnoreExtCCA = 0;
342 ah->ah_config.ath_hal_pciePowerSaveEnable = 0;
343 ah->ah_config.ath_hal_pcieL1SKPEnable = 0;
344 ah->ah_config.ath_hal_pcieClockReq = 0;
345 ah->ah_config.ath_hal_pciePowerReset = 0x100;
346 ah->ah_config.ath_hal_pcieRestore = 0;
347 ah->ah_config.ath_hal_pcieWaen = 0;
348 ah->ah_config.ath_hal_analogShiftReg = 1;
349 ah->ah_config.ath_hal_htEnable = 1;
350 ah->ah_config.ath_hal_ofdmTrigLow = 200;
351 ah->ah_config.ath_hal_ofdmTrigHigh = 500;
352 ah->ah_config.ath_hal_cckTrigHigh = 200;
353 ah->ah_config.ath_hal_cckTrigLow = 100;
354 ah->ah_config.ath_hal_enableANI = 0;
355 ah->ah_config.ath_hal_noiseImmunityLvl = 4;
356 ah->ah_config.ath_hal_ofdmWeakSigDet = 1;
357 ah->ah_config.ath_hal_cckWeakSigThr = 0;
358 ah->ah_config.ath_hal_spurImmunityLvl = 2;
359 ah->ah_config.ath_hal_firStepLvl = 0;
360 ah->ah_config.ath_hal_rssiThrHigh = 40;
361 ah->ah_config.ath_hal_rssiThrLow = 7;
362 ah->ah_config.ath_hal_diversityControl = 0;
363 ah->ah_config.ath_hal_antennaSwitchSwap = 0;
364
365 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
366 ah->ah_config.ath_hal_spurChans[i][0] = AR_NO_SPUR;
367 ah->ah_config.ath_hal_spurChans[i][1] = AR_NO_SPUR;
368 }
369
370 ah->ah_config.ath_hal_intrMitigation = 0;
371 ah->ah_config.ath_hal_debug = 0;
372 }
373
374 static inline void ath9k_hw_override_ini(struct ath_hal *ah,
375 struct hal_channel *chan)
376 {
377 if (!AR_SREV_5416_V20_OR_LATER(ah)
378 || AR_SREV_9280_10_OR_LATER(ah))
379 return;
380
381 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
382 }
383
384 static inline void ath9k_hw_init_bb(struct ath_hal *ah,
385 struct hal_channel *chan)
386 {
387 u_int32_t synthDelay;
388
389 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
390 if (IS_CHAN_CCK(chan))
391 synthDelay = (4 * synthDelay) / 22;
392 else
393 synthDelay /= 10;
394
395 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
396
397 udelay(synthDelay + BASE_ACTIVATE_DELAY);
398 }
399
400 static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
401 enum hal_opmode opmode)
402 {
403 struct ath_hal_5416 *ahp = AH5416(ah);
404
405 ahp->ah_maskReg = AR_IMR_TXERR |
406 AR_IMR_TXURN |
407 AR_IMR_RXERR |
408 AR_IMR_RXORN |
409 AR_IMR_BCNMISC;
410
411 if (ahp->ah_intrMitigation)
412 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
413 else
414 ahp->ah_maskReg |= AR_IMR_RXOK;
415
416 ahp->ah_maskReg |= AR_IMR_TXOK;
417
418 if (opmode == HAL_M_HOSTAP)
419 ahp->ah_maskReg |= AR_IMR_MIB;
420
421 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
422 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
423
424 if (!AR_SREV_9100(ah)) {
425 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
426 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
427 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
428 }
429 }
430
431 static inline void ath9k_hw_init_qos(struct ath_hal *ah)
432 {
433 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
434 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
435
436 REG_WRITE(ah, AR_QOS_NO_ACK,
437 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
438 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
439 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
440
441 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
442 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
443 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
444 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
445 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
446 }
447
448 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
449 u_int reg,
450 u_int32_t mask,
451 u_int32_t shift,
452 u_int32_t val)
453 {
454 u_int32_t regVal;
455
456 regVal = REG_READ(ah, reg) & ~mask;
457 regVal |= (val << shift) & mask;
458
459 REG_WRITE(ah, reg, regVal);
460
461 if (ah->ah_config.ath_hal_analogShiftReg)
462 udelay(100);
463
464 return;
465 }
466
467 static u_int8_t ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
468 enum hal_freq_band freq_band)
469 {
470 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
471 struct modal_eep_header *pModal =
472 &(eep->modalHeader[HAL_FREQ_BAND_2GHZ == freq_band]);
473 struct base_eep_header *pBase = &eep->baseEepHeader;
474 u_int8_t num_ant_config;
475
476 num_ant_config = 1;
477
478 if (pBase->version >= 0x0E0D)
479 if (pModal->useAnt1)
480 num_ant_config += 1;
481
482 return num_ant_config;
483 }
484
485 static enum hal_status
486 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
487 struct hal_channel_internal *chan,
488 u_int8_t index,
489 u_int16_t *config)
490 {
491 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
492 struct modal_eep_header *pModal =
493 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
494 struct base_eep_header *pBase = &eep->baseEepHeader;
495
496 switch (index) {
497 case 0:
498 *config = pModal->antCtrlCommon & 0xFFFF;
499 return HAL_OK;
500 case 1:
501 if (pBase->version >= 0x0E0D) {
502 if (pModal->useAnt1) {
503 *config =
504 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
505 return HAL_OK;
506 }
507 }
508 break;
509 default:
510 break;
511 }
512
513 return HAL_EINVAL;
514 }
515
516 static inline enum hal_bool ath9k_hw_nvram_read(struct ath_hal *ah,
517 u_int off,
518 u_int16_t *data)
519 {
520 if (ath9k_hw_use_flash(ah))
521 return ath9k_hw_flash_read(ah, off, data);
522 else
523 return ath9k_hw_eeprom_read(ah, off, data);
524 }
525
526 static inline enum hal_bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
527 {
528 struct ath_hal_5416 *ahp = AH5416(ah);
529 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
530 u_int16_t *eep_data;
531 int addr, ar5416_eep_start_loc = 0;
532
533 if (!ath9k_hw_use_flash(ah)) {
534 HDPRINTF(ah, HAL_DBG_EEPROM,
535 "%s: Reading from EEPROM, not flash\n", __func__);
536 ar5416_eep_start_loc = 256;
537 }
538 if (AR_SREV_9100(ah))
539 ar5416_eep_start_loc = 256;
540
541 eep_data = (u_int16_t *) eep;
542 for (addr = 0;
543 addr < sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
544 addr++) {
545 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
546 eep_data)) {
547 HDPRINTF(ah, HAL_DBG_EEPROM,
548 "%s: Unable to read eeprom region \n",
549 __func__);
550 return AH_FALSE;
551 }
552 eep_data++;
553 }
554 return AH_TRUE;
555 }
556
557 /* XXX: Clean me up, make me more legible */
558 static enum hal_bool
559 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
560 struct hal_channel_internal *chan)
561 {
562 struct modal_eep_header *pModal;
563 int i, regChainOffset;
564 struct ath_hal_5416 *ahp = AH5416(ah);
565 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
566 u_int8_t txRxAttenLocal;
567 u_int16_t ant_config;
568
569 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
570
571 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
572
573 ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config);
574 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
575
576 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
577 if (AR_SREV_9280(ah)) {
578 if (i >= 2)
579 break;
580 }
581
582 if (AR_SREV_5416_V20_OR_LATER(ah) &&
583 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
584 && (i != 0))
585 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
586 else
587 regChainOffset = i * 0x1000;
588
589 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
590 pModal->antCtrlChain[i]);
591
592 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
593 (REG_READ(ah,
594 AR_PHY_TIMING_CTRL4(0) +
595 regChainOffset) &
596 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
597 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
598 SM(pModal->iqCalICh[i],
599 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
600 SM(pModal->iqCalQCh[i],
601 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
602
603 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
604 if ((eep->baseEepHeader.version &
605 AR5416_EEP_VER_MINOR_MASK) >= AR5416_EEP_MINOR_VER_3) {
606 txRxAttenLocal = pModal->txRxAttenCh[i];
607 if (AR_SREV_9280_10_OR_LATER(ah)) {
608 OS_REG_RMW_FIELD(ah,
609 AR_PHY_GAIN_2GHZ +
610 regChainOffset,
611 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
612 pModal->
613 bswMargin[i]);
614 OS_REG_RMW_FIELD(ah,
615 AR_PHY_GAIN_2GHZ +
616 regChainOffset,
617 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
618 pModal->
619 bswAtten[i]);
620 OS_REG_RMW_FIELD(ah,
621 AR_PHY_GAIN_2GHZ +
622 regChainOffset,
623 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
624 pModal->
625 xatten2Margin[i]);
626 OS_REG_RMW_FIELD(ah,
627 AR_PHY_GAIN_2GHZ +
628 regChainOffset,
629 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
630 pModal->
631 xatten2Db[i]);
632 } else {
633 REG_WRITE(ah,
634 AR_PHY_GAIN_2GHZ +
635 regChainOffset,
636 (REG_READ(ah,
637 AR_PHY_GAIN_2GHZ +
638 regChainOffset) &
639 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
640 | SM(pModal->
641 bswMargin[i],
642 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
643 REG_WRITE(ah,
644 AR_PHY_GAIN_2GHZ +
645 regChainOffset,
646 (REG_READ(ah,
647 AR_PHY_GAIN_2GHZ +
648 regChainOffset) &
649 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
650 | SM(pModal->bswAtten[i],
651 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
652 }
653 }
654 if (AR_SREV_9280_10_OR_LATER(ah)) {
655 OS_REG_RMW_FIELD(ah,
656 AR_PHY_RXGAIN +
657 regChainOffset,
658 AR9280_PHY_RXGAIN_TXRX_ATTEN,
659 txRxAttenLocal);
660 OS_REG_RMW_FIELD(ah,
661 AR_PHY_RXGAIN +
662 regChainOffset,
663 AR9280_PHY_RXGAIN_TXRX_MARGIN,
664 pModal->rxTxMarginCh[i]);
665 } else {
666 REG_WRITE(ah,
667 AR_PHY_RXGAIN + regChainOffset,
668 (REG_READ(ah,
669 AR_PHY_RXGAIN +
670 regChainOffset) &
671 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
672 SM(txRxAttenLocal,
673 AR_PHY_RXGAIN_TXRX_ATTEN));
674 REG_WRITE(ah,
675 AR_PHY_GAIN_2GHZ +
676 regChainOffset,
677 (REG_READ(ah,
678 AR_PHY_GAIN_2GHZ +
679 regChainOffset) &
680 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
681 SM(pModal->rxTxMarginCh[i],
682 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
683 }
684 }
685 }
686
687 if (AR_SREV_9280_10_OR_LATER(ah)) {
688 if (IS_CHAN_2GHZ(chan)) {
689 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
690 AR_AN_RF2G1_CH0_OB,
691 AR_AN_RF2G1_CH0_OB_S,
692 pModal->ob);
693 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
694 AR_AN_RF2G1_CH0_DB,
695 AR_AN_RF2G1_CH0_DB_S,
696 pModal->db);
697 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
698 AR_AN_RF2G1_CH1_OB,
699 AR_AN_RF2G1_CH1_OB_S,
700 pModal->ob_ch1);
701 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
702 AR_AN_RF2G1_CH1_DB,
703 AR_AN_RF2G1_CH1_DB_S,
704 pModal->db_ch1);
705 } else {
706 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
707 AR_AN_RF5G1_CH0_OB5,
708 AR_AN_RF5G1_CH0_OB5_S,
709 pModal->ob);
710 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
711 AR_AN_RF5G1_CH0_DB5,
712 AR_AN_RF5G1_CH0_DB5_S,
713 pModal->db);
714 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
715 AR_AN_RF5G1_CH1_OB5,
716 AR_AN_RF5G1_CH1_OB5_S,
717 pModal->ob_ch1);
718 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
719 AR_AN_RF5G1_CH1_DB5,
720 AR_AN_RF5G1_CH1_DB5_S,
721 pModal->db_ch1);
722 }
723 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
724 AR_AN_TOP2_XPABIAS_LVL,
725 AR_AN_TOP2_XPABIAS_LVL_S,
726 pModal->xpaBiasLvl);
727 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
728 AR_AN_TOP2_LOCALBIAS,
729 AR_AN_TOP2_LOCALBIAS_S,
730 pModal->local_bias);
731 HDPRINTF(NULL, HAL_DBG_UNMASKABLE, "ForceXPAon: %d\n",
732 pModal->force_xpaon);
733 OS_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
734 pModal->force_xpaon);
735 }
736
737 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
738 pModal->switchSettling);
739 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
740 pModal->adcDesiredSize);
741
742 if (!AR_SREV_9280_10_OR_LATER(ah))
743 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
744 AR_PHY_DESIRED_SZ_PGA,
745 pModal->pgaDesiredSize);
746
747 REG_WRITE(ah, AR_PHY_RF_CTL4,
748 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
749 | SM(pModal->txEndToXpaOff,
750 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
751 | SM(pModal->txFrameToXpaOn,
752 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
753 | SM(pModal->txFrameToXpaOn,
754 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
755
756 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
757 pModal->txEndToRxOn);
758 if (AR_SREV_9280_10_OR_LATER(ah)) {
759 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
760 pModal->thresh62);
761 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
762 AR_PHY_EXT_CCA0_THRESH62,
763 pModal->thresh62);
764 } else {
765 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
766 pModal->thresh62);
767 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
768 AR_PHY_EXT_CCA_THRESH62,
769 pModal->thresh62);
770 }
771
772 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
773 AR5416_EEP_MINOR_VER_2) {
774 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
775 AR_PHY_TX_END_DATA_START,
776 pModal->txFrameToDataStart);
777 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
778 pModal->txFrameToPaOn);
779 }
780
781 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
782 AR5416_EEP_MINOR_VER_3) {
783 if (IS_CHAN_HT40(chan))
784 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
785 AR_PHY_SETTLING_SWITCH,
786 pModal->swSettleHt40);
787 }
788
789 return AH_TRUE;
790 }
791
792 static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
793 {
794 u_int32_t sum = 0, el;
795 u_int16_t *eepdata;
796 int i;
797 struct ath_hal_5416 *ahp = AH5416(ah);
798 enum hal_bool need_swap = AH_FALSE;
799 struct ar5416_eeprom *eep =
800 (struct ar5416_eeprom *) &ahp->ah_eeprom;
801
802 if (!ath9k_hw_use_flash(ah)) {
803 u_int16_t magic, magic2;
804 int addr;
805
806 if (ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
807 &magic)) {
808 HDPRINTF(ah, HAL_DBG_EEPROM,
809 "%s: Reading Magic # failed\n", __func__);
810 return AH_FALSE;
811 }
812 HDPRINTF(ah, HAL_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
813 __func__, magic);
814
815 if (magic != AR5416_EEPROM_MAGIC) {
816 magic2 = swab16(magic);
817
818 if (magic2 == AR5416_EEPROM_MAGIC) {
819 need_swap = AH_TRUE;
820 eepdata = (u_int16_t *) (&ahp->ah_eeprom);
821
822 for (addr = 0;
823 addr <
824 sizeof(struct ar5416_eeprom) /
825 sizeof(u_int16_t); addr++) {
826 u_int16_t temp;
827
828 temp = swab16(*eepdata);
829 *eepdata = temp;
830 eepdata++;
831
832 HDPRINTF(ah, HAL_DBG_EEPROM_DUMP,
833 "0x%04X ", *eepdata);
834 if (((addr + 1) % 6) == 0)
835 HDPRINTF(ah,
836 HAL_DBG_EEPROM_DUMP,
837 "\n");
838 }
839 } else {
840 HDPRINTF(ah, HAL_DBG_EEPROM,
841 "Invalid EEPROM Magic. "
842 "endianness missmatch.\n");
843 return HAL_EEBADSUM;
844 }
845 }
846 }
847 HDPRINTF(ah, HAL_DBG_EEPROM, "need_swap = %s.\n",
848 need_swap ? "True" : "False");
849
850 if (need_swap)
851 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
852 else
853 el = ahp->ah_eeprom.baseEepHeader.length;
854
855 eepdata = (u_int16_t *) (&ahp->ah_eeprom);
856 for (i = 0; i <
857 min(el, sizeof(struct ar5416_eeprom)) / sizeof(u_int16_t); i++)
858 sum ^= *eepdata++;
859
860 if (need_swap) {
861 u_int32_t integer, j;
862 u_int16_t word;
863
864 HDPRINTF(ah, HAL_DBG_EEPROM,
865 "EEPROM Endianness is not native.. Changing \n");
866
867 word = swab16(eep->baseEepHeader.length);
868 eep->baseEepHeader.length = word;
869
870 word = swab16(eep->baseEepHeader.checksum);
871 eep->baseEepHeader.checksum = word;
872
873 word = swab16(eep->baseEepHeader.version);
874 eep->baseEepHeader.version = word;
875
876 word = swab16(eep->baseEepHeader.regDmn[0]);
877 eep->baseEepHeader.regDmn[0] = word;
878
879 word = swab16(eep->baseEepHeader.regDmn[1]);
880 eep->baseEepHeader.regDmn[1] = word;
881
882 word = swab16(eep->baseEepHeader.rfSilent);
883 eep->baseEepHeader.rfSilent = word;
884
885 word = swab16(eep->baseEepHeader.blueToothOptions);
886 eep->baseEepHeader.blueToothOptions = word;
887
888 word = swab16(eep->baseEepHeader.deviceCap);
889 eep->baseEepHeader.deviceCap = word;
890
891 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
892 struct modal_eep_header *pModal =
893 &eep->modalHeader[j];
894 integer = swab32(pModal->antCtrlCommon);
895 pModal->antCtrlCommon = integer;
896
897 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
898 integer = swab32(pModal->antCtrlChain[i]);
899 pModal->antCtrlChain[i] = integer;
900 }
901
902 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
903 word = swab16(pModal->spurChans[i].spurChan);
904 pModal->spurChans[i].spurChan = word;
905 }
906 }
907 }
908
909 if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
910 ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
911 HDPRINTF(ah, HAL_DBG_EEPROM,
912 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
913 sum, ar5416_get_eep_ver(ahp));
914 return HAL_EEBADSUM;
915 }
916
917 return HAL_OK;
918 }
919
920 static enum hal_bool ath9k_hw_chip_test(struct ath_hal *ah)
921 {
922 u_int32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
923 u_int32_t regHold[2];
924 u_int32_t patternData[4] = { 0x55555555,
925 0xaaaaaaaa,
926 0x66666666,
927 0x99999999 };
928 int i, j;
929
930 for (i = 0; i < 2; i++) {
931 u_int32_t addr = regAddr[i];
932 u_int32_t wrData, rdData;
933
934 regHold[i] = REG_READ(ah, addr);
935 for (j = 0; j < 0x100; j++) {
936 wrData = (j << 16) | j;
937 REG_WRITE(ah, addr, wrData);
938 rdData = REG_READ(ah, addr);
939 if (rdData != wrData) {
940 HDPRINTF(ah, HAL_DBG_REG_IO,
941 "%s: address test failed "
942 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
943 __func__, addr, wrData, rdData);
944 return AH_FALSE;
945 }
946 }
947 for (j = 0; j < 4; j++) {
948 wrData = patternData[j];
949 REG_WRITE(ah, addr, wrData);
950 rdData = REG_READ(ah, addr);
951 if (wrData != rdData) {
952 HDPRINTF(ah, HAL_DBG_REG_IO,
953 "%s: address test failed "
954 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
955 __func__, addr, wrData, rdData);
956 return AH_FALSE;
957 }
958 }
959 REG_WRITE(ah, regAddr[i], regHold[i]);
960 }
961 udelay(100);
962 return AH_TRUE;
963 }
964
965 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah)
966 {
967 u_int32_t bits = REG_READ(ah, AR_RX_FILTER);
968 u_int32_t phybits = REG_READ(ah, AR_PHY_ERR);
969
970 if (phybits & AR_PHY_ERR_RADAR)
971 bits |= HAL_RX_FILTER_PHYRADAR;
972 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
973 bits |= HAL_RX_FILTER_PHYERR;
974 return bits;
975 }
976
977 void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits)
978 {
979 u_int32_t phybits;
980
981 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
982 phybits = 0;
983 if (bits & HAL_RX_FILTER_PHYRADAR)
984 phybits |= AR_PHY_ERR_RADAR;
985 if (bits & HAL_RX_FILTER_PHYERR)
986 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
987 REG_WRITE(ah, AR_PHY_ERR, phybits);
988
989 if (phybits)
990 REG_WRITE(ah, AR_RXCFG,
991 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
992 else
993 REG_WRITE(ah, AR_RXCFG,
994 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
995 }
996
997 enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
998 enum hal_capability_type type,
999 u_int32_t capability,
1000 u_int32_t setting,
1001 enum hal_status *status)
1002 {
1003 struct ath_hal_5416 *ahp = AH5416(ah);
1004 u_int32_t v;
1005
1006 switch (type) {
1007 case HAL_CAP_TKIP_MIC:
1008 if (setting)
1009 ahp->ah_staId1Defaults |=
1010 AR_STA_ID1_CRPT_MIC_ENABLE;
1011 else
1012 ahp->ah_staId1Defaults &=
1013 ~AR_STA_ID1_CRPT_MIC_ENABLE;
1014 return AH_TRUE;
1015 case HAL_CAP_DIVERSITY:
1016 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1017 if (setting)
1018 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1019 else
1020 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1021 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1022 return AH_TRUE;
1023 case HAL_CAP_MCAST_KEYSRCH:
1024 if (setting)
1025 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1026 else
1027 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1028 return AH_TRUE;
1029 case HAL_CAP_TSF_ADJUST:
1030 if (setting)
1031 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1032 else
1033 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1034 return AH_TRUE;
1035 default:
1036 return AH_FALSE;
1037 }
1038 }
1039
1040 void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1041 {
1042 u_int32_t val[ATH9K_NUM_DMA_DEBUG_REGS];
1043 int qcuOffset = 0, dcuOffset = 0;
1044 u_int32_t *qcuBase = &val[0], *dcuBase = &val[4];
1045 int i;
1046
1047 REG_WRITE(ah, AR_MACMISC,
1048 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1049 (AR_MACMISC_MISC_OBS_BUS_1 <<
1050 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1051
1052 HDPRINTF(ah, HAL_DBG_REG_IO, "Raw DMA Debug values:\n");
1053 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
1054 if (i % 4 == 0)
1055 HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
1056
1057 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1058 HDPRINTF(ah, HAL_DBG_REG_IO, "%d: %08x ", i, val[i]);
1059 }
1060
1061 HDPRINTF(ah, HAL_DBG_REG_IO, "\n\n");
1062 HDPRINTF(ah, HAL_DBG_REG_IO,
1063 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1064
1065 for (i = 0; i < ATH9K_NUM_QUEUES;
1066 i++, qcuOffset += 4, dcuOffset += 5) {
1067 if (i == 8) {
1068 qcuOffset = 0;
1069 qcuBase++;
1070 }
1071
1072 if (i == 6) {
1073 dcuOffset = 0;
1074 dcuBase++;
1075 }
1076
1077 HDPRINTF(ah, HAL_DBG_REG_IO,
1078 "%2d %2x %1x %2x %2x\n",
1079 i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1080 (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1081 3),
1082 val[2] & (0x7 << (i * 3)) >> (i * 3),
1083 (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1084 }
1085
1086 HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
1087 HDPRINTF(ah, HAL_DBG_REG_IO,
1088 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1089 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1090 HDPRINTF(ah, HAL_DBG_REG_IO,
1091 "qcu_complete state: %2x dcu_complete state: %2x\n",
1092 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1093 HDPRINTF(ah, HAL_DBG_REG_IO,
1094 "dcu_arb state: %2x dcu_fp state: %2x\n",
1095 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1096 HDPRINTF(ah, HAL_DBG_REG_IO,
1097 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1098 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1099 HDPRINTF(ah, HAL_DBG_REG_IO,
1100 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1101 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1102 HDPRINTF(ah, HAL_DBG_REG_IO,
1103 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1104 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1105
1106 HDPRINTF(ah, HAL_DBG_REG_IO, "pcu observe 0x%x \n",
1107 REG_READ(ah, AR_OBS_BUS_1));
1108 HDPRINTF(ah, HAL_DBG_REG_IO, "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1109 }
1110
1111 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1112 u_int32_t *rxc_pcnt,
1113 u_int32_t *rxf_pcnt,
1114 u_int32_t *txf_pcnt)
1115 {
1116 static u_int32_t cycles, rx_clear, rx_frame, tx_frame;
1117 u_int32_t good = 1;
1118
1119 u_int32_t rc = REG_READ(ah, AR_RCCNT);
1120 u_int32_t rf = REG_READ(ah, AR_RFCNT);
1121 u_int32_t tf = REG_READ(ah, AR_TFCNT);
1122 u_int32_t cc = REG_READ(ah, AR_CCCNT);
1123
1124 if (cycles == 0 || cycles > cc) {
1125 HDPRINTF(ah, HAL_DBG_CHANNEL,
1126 "%s: cycle counter wrap. ExtBusy = 0\n",
1127 __func__);
1128 good = 0;
1129 } else {
1130 u_int32_t cc_d = cc - cycles;
1131 u_int32_t rc_d = rc - rx_clear;
1132 u_int32_t rf_d = rf - rx_frame;
1133 u_int32_t tf_d = tf - tx_frame;
1134
1135 if (cc_d != 0) {
1136 *rxc_pcnt = rc_d * 100 / cc_d;
1137 *rxf_pcnt = rf_d * 100 / cc_d;
1138 *txf_pcnt = tf_d * 100 / cc_d;
1139 } else {
1140 good = 0;
1141 }
1142 }
1143
1144 cycles = cc;
1145 rx_frame = rf;
1146 rx_clear = rc;
1147 tx_frame = tf;
1148
1149 return good;
1150 }
1151
1152 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode)
1153 {
1154 u_int32_t macmode;
1155
1156 if (mode == HAL_HT_MACMODE_2040 &&
1157 !ah->ah_config.ath_hal_cwmIgnoreExtCCA)
1158 macmode = AR_2040_JOINED_RX_CLEAR;
1159 else
1160 macmode = 0;
1161
1162 REG_WRITE(ah, AR_2040_MODE, macmode);
1163 }
1164
1165 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1166 {
1167 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1168 }
1169
1170
1171 static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid, void *sc,
1172 void __iomem *mem,
1173 enum hal_status *status)
1174 {
1175 static const u_int8_t defbssidmask[ETH_ALEN] =
1176 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1177 struct ath_hal_5416 *ahp;
1178 struct ath_hal *ah;
1179
1180 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1181 if (ahp == NULL) {
1182 HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
1183 "%s: cannot allocate memory for state block\n",
1184 __func__);
1185 *status = HAL_ENOMEM;
1186 return NULL;
1187 }
1188
1189 ah = &ahp->ah;
1190
1191 memcpy(&ahp->ah, &ar5416hal, sizeof(struct ath_hal));
1192
1193 ah->ah_sc = sc;
1194 ah->ah_sh = mem;
1195
1196 ah->ah_devid = devid;
1197 ah->ah_subvendorid = 0;
1198
1199 ah->ah_flags = 0;
1200 if ((devid == AR5416_AR9100_DEVID))
1201 ah->ah_macVersion = AR_SREV_VERSION_9100;
1202 if (!AR_SREV_9100(ah))
1203 ah->ah_flags = AH_USE_EEPROM;
1204
1205 ah->ah_powerLimit = MAX_RATE_POWER;
1206 ah->ah_tpScale = HAL_TP_SCALE_MAX;
1207
1208 ahp->ah_atimWindow = 0;
1209 ahp->ah_diversityControl = ah->ah_config.ath_hal_diversityControl;
1210 ahp->ah_antennaSwitchSwap =
1211 ah->ah_config.ath_hal_antennaSwitchSwap;
1212
1213 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1214 ahp->ah_beaconInterval = 100;
1215 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
1216 ahp->ah_slottime = (u_int) -1;
1217 ahp->ah_acktimeout = (u_int) -1;
1218 ahp->ah_ctstimeout = (u_int) -1;
1219 ahp->ah_globaltxtimeout = (u_int) -1;
1220 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
1221
1222 ahp->ah_gBeaconRate = 0;
1223
1224 return ahp;
1225 }
1226
1227 static enum hal_status ath9k_hw_eeprom_attach(struct ath_hal *ah)
1228 {
1229 enum hal_status status;
1230
1231 if (ath9k_hw_use_flash(ah))
1232 ath9k_hw_flash_map(ah);
1233
1234 if (!ath9k_hw_fill_eeprom(ah))
1235 return HAL_EIO;
1236
1237 status = ath9k_hw_check_eeprom(ah);
1238
1239 return status;
1240 }
1241
1242 u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1243 enum eeprom_param param)
1244 {
1245 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1246 struct modal_eep_header *pModal = eep->modalHeader;
1247 struct base_eep_header *pBase = &eep->baseEepHeader;
1248
1249 switch (param) {
1250 case EEP_NFTHRESH_5:
1251 return -pModal[0].noiseFloorThreshCh[0];
1252 case EEP_NFTHRESH_2:
1253 return -pModal[1].noiseFloorThreshCh[0];
1254 case AR_EEPROM_MAC(0):
1255 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1256 case AR_EEPROM_MAC(1):
1257 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1258 case AR_EEPROM_MAC(2):
1259 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1260 case EEP_REG_0:
1261 return pBase->regDmn[0];
1262 case EEP_REG_1:
1263 return pBase->regDmn[1];
1264 case EEP_OP_CAP:
1265 return pBase->deviceCap;
1266 case EEP_OP_MODE:
1267 return pBase->opCapFlags;
1268 case EEP_RF_SILENT:
1269 return pBase->rfSilent;
1270 case EEP_OB_5:
1271 return pModal[0].ob;
1272 case EEP_DB_5:
1273 return pModal[0].db;
1274 case EEP_OB_2:
1275 return pModal[1].ob;
1276 case EEP_DB_2:
1277 return pModal[1].db;
1278 case EEP_MINOR_REV:
1279 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1280 case EEP_TX_MASK:
1281 return pBase->txMask;
1282 case EEP_RX_MASK:
1283 return pBase->rxMask;
1284 default:
1285 return 0;
1286 }
1287 }
1288
1289 static inline int ath9k_hw_get_radiorev(struct ath_hal *ah)
1290 {
1291 u_int32_t val;
1292 int i;
1293
1294 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1295 for (i = 0; i < 8; i++)
1296 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1297 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1298 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1299 return ath9k_hw_reverse_bits(val, 8);
1300 }
1301
1302 static inline enum hal_status ath9k_hw_init_macaddr(struct ath_hal *ah)
1303 {
1304 u_int32_t sum;
1305 int i;
1306 u_int16_t eeval;
1307 struct ath_hal_5416 *ahp = AH5416(ah);
1308 DECLARE_MAC_BUF(mac);
1309
1310 sum = 0;
1311 for (i = 0; i < 3; i++) {
1312 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1313 sum += eeval;
1314 ahp->ah_macaddr[2 * i] = eeval >> 8;
1315 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1316 }
1317 if (sum == 0 || sum == 0xffff * 3) {
1318 HDPRINTF(ah, HAL_DBG_EEPROM,
1319 "%s: mac address read failed: %s\n", __func__,
1320 print_mac(mac, ahp->ah_macaddr));
1321 return HAL_EEBADMAC;
1322 }
1323
1324 return HAL_OK;
1325 }
1326
1327 static inline int16_t ath9k_hw_interpolate(u_int16_t target,
1328 u_int16_t srcLeft,
1329 u_int16_t srcRight,
1330 int16_t targetLeft,
1331 int16_t targetRight)
1332 {
1333 int16_t rv;
1334
1335 if (srcRight == srcLeft) {
1336 rv = targetLeft;
1337 } else {
1338 rv = (int16_t) (((target - srcLeft) * targetRight +
1339 (srcRight - target) * targetLeft) /
1340 (srcRight - srcLeft));
1341 }
1342 return rv;
1343 }
1344
1345 static inline u_int16_t ath9k_hw_fbin2freq(u_int8_t fbin,
1346 enum hal_bool is2GHz)
1347 {
1348
1349 if (fbin == AR5416_BCHAN_UNUSED)
1350 return fbin;
1351
1352 return (u_int16_t) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1353 }
1354
1355 static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1356 u_int16_t i,
1357 enum hal_bool is2GHz)
1358 {
1359 struct ath_hal_5416 *ahp = AH5416(ah);
1360 struct ar5416_eeprom *eep =
1361 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1362 u_int16_t spur_val = AR_NO_SPUR;
1363
1364 HDPRINTF(ah, HAL_DBG_ANI,
1365 "Getting spur idx %d is2Ghz. %d val %x\n",
1366 i, is2GHz, ah->ah_config.ath_hal_spurChans[i][is2GHz]);
1367
1368 switch (ah->ah_config.ath_hal_spurMode) {
1369 case SPUR_DISABLE:
1370 break;
1371 case SPUR_ENABLE_IOCTL:
1372 spur_val = ah->ah_config.ath_hal_spurChans[i][is2GHz];
1373 HDPRINTF(ah, HAL_DBG_ANI,
1374 "Getting spur val from new loc. %d\n", spur_val);
1375 break;
1376 case SPUR_ENABLE_EEPROM:
1377 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1378 break;
1379
1380 }
1381 return spur_val;
1382 }
1383
1384 static inline enum hal_status ath9k_hw_rfattach(struct ath_hal *ah)
1385 {
1386 enum hal_bool rfStatus = AH_FALSE;
1387 enum hal_status ecode = HAL_OK;
1388
1389 rfStatus = ath9k_hw_init_rf(ah, &ecode);
1390 if (!rfStatus) {
1391 HDPRINTF(ah, HAL_DBG_RESET,
1392 "%s: RF setup failed, status %u\n", __func__,
1393 ecode);
1394 return ecode;
1395 }
1396
1397 return HAL_OK;
1398 }
1399
1400 static enum hal_status ath9k_hw_rf_claim(struct ath_hal *ah)
1401 {
1402 u_int32_t val;
1403
1404 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1405
1406 val = ath9k_hw_get_radiorev(ah);
1407 switch (val & AR_RADIO_SREV_MAJOR) {
1408 case 0:
1409 val = AR_RAD5133_SREV_MAJOR;
1410 break;
1411 case AR_RAD5133_SREV_MAJOR:
1412 case AR_RAD5122_SREV_MAJOR:
1413 case AR_RAD2133_SREV_MAJOR:
1414 case AR_RAD2122_SREV_MAJOR:
1415 break;
1416 default:
1417 HDPRINTF(ah, HAL_DBG_CHANNEL,
1418 "%s: 5G Radio Chip Rev 0x%02X is not "
1419 "supported by this driver\n",
1420 __func__, ah->ah_analog5GhzRev);
1421 return HAL_ENOTSUPP;
1422 }
1423
1424 ah->ah_analog5GhzRev = val;
1425
1426 return HAL_OK;
1427 }
1428
1429 static inline void ath9k_hw_init_pll(struct ath_hal *ah,
1430 struct hal_channel *chan)
1431 {
1432 u_int32_t pll;
1433
1434 if (AR_SREV_9100(ah)) {
1435 if (chan && IS_CHAN_5GHZ(chan))
1436 pll = 0x1450;
1437 else
1438 pll = 0x1458;
1439 } else {
1440 if (AR_SREV_9280_10_OR_LATER(ah)) {
1441 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1442
1443 if (chan && IS_CHAN_HALF_RATE(chan))
1444 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1445 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1446 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1447
1448 if (chan && IS_CHAN_5GHZ(chan)) {
1449 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1450
1451
1452 if (AR_SREV_9280_20(ah)) {
1453 if (((chan->channel % 20) == 0)
1454 || ((chan->channel % 10) == 0))
1455 pll = 0x2850;
1456 else
1457 pll = 0x142c;
1458 }
1459 } else {
1460 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1461 }
1462
1463 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1464
1465 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1466
1467 if (chan && IS_CHAN_HALF_RATE(chan))
1468 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1469 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1470 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1471
1472 if (chan && IS_CHAN_5GHZ(chan))
1473 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1474 else
1475 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1476 } else {
1477 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1478
1479 if (chan && IS_CHAN_HALF_RATE(chan))
1480 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1481 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1482 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1483
1484 if (chan && IS_CHAN_5GHZ(chan))
1485 pll |= SM(0xa, AR_RTC_PLL_DIV);
1486 else
1487 pll |= SM(0xb, AR_RTC_PLL_DIV);
1488 }
1489 }
1490 REG_WRITE(ah, (u_int16_t) (AR_RTC_PLL_CONTROL), pll);
1491
1492 udelay(RTC_PLL_SETTLE_DELAY);
1493
1494 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1495 }
1496
1497 static void ath9k_hw_set_regs(struct ath_hal *ah, struct hal_channel *chan,
1498 enum hal_ht_macmode macmode)
1499 {
1500 u_int32_t phymode;
1501 struct ath_hal_5416 *ahp = AH5416(ah);
1502
1503 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1504 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1505
1506 if (IS_CHAN_HT40(chan)) {
1507 phymode |= AR_PHY_FC_DYN2040_EN;
1508
1509 if (chan->channelFlags & CHANNEL_HT40PLUS)
1510 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1511
1512 if (ahp->ah_extprotspacing == HAL_HT_EXTPROTSPACING_25)
1513 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1514 }
1515 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1516
1517 ath9k_hw_set11nmac2040(ah, macmode);
1518
1519 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1520 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1521 }
1522
1523 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1524 {
1525 u_int32_t val;
1526
1527 val = REG_READ(ah, AR_STA_ID1);
1528 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1529 switch (opmode) {
1530 case HAL_M_HOSTAP:
1531 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1532 | AR_STA_ID1_KSRCH_MODE);
1533 OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1534 break;
1535 case HAL_M_IBSS:
1536 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1537 | AR_STA_ID1_KSRCH_MODE);
1538 OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1539 break;
1540 case HAL_M_STA:
1541 case HAL_M_MONITOR:
1542 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1543 break;
1544 }
1545 }
1546
1547 static inline void
1548 ath9k_hw_set_rfmode(struct ath_hal *ah, struct hal_channel *chan)
1549 {
1550 u_int32_t rfMode = 0;
1551
1552 if (chan == NULL)
1553 return;
1554
1555 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1556 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1557
1558 if (!AR_SREV_9280_10_OR_LATER(ah))
1559 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1560 AR_PHY_MODE_RF2GHZ;
1561
1562 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1563 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1564
1565 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1566 }
1567
1568 static enum hal_bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1569 {
1570 u_int32_t rst_flags;
1571 u_int32_t tmpReg;
1572
1573 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1574 AR_RTC_FORCE_WAKE_ON_INT);
1575
1576 if (AR_SREV_9100(ah)) {
1577 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1578 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1579 } else {
1580 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1581 if (tmpReg &
1582 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1583 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1584 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1585 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1586 } else {
1587 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1588 }
1589
1590 rst_flags = AR_RTC_RC_MAC_WARM;
1591 if (type == HAL_RESET_COLD)
1592 rst_flags |= AR_RTC_RC_MAC_COLD;
1593 }
1594
1595 REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), rst_flags);
1596 udelay(50);
1597
1598 REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), 0);
1599 if (!ath9k_hw_wait(ah, (u_int16_t) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1600 HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC stuck in MAC reset\n",
1601 __func__);
1602 return AH_FALSE;
1603 }
1604
1605 if (!AR_SREV_9100(ah))
1606 REG_WRITE(ah, AR_RC, 0);
1607
1608 ath9k_hw_init_pll(ah, NULL);
1609
1610 if (AR_SREV_9100(ah))
1611 udelay(50);
1612
1613 return AH_TRUE;
1614 }
1615
1616 static inline enum hal_bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1617 {
1618 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1619 AR_RTC_FORCE_WAKE_ON_INT);
1620
1621 REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 0);
1622 REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 1);
1623
1624 if (!ath9k_hw_wait(ah,
1625 AR_RTC_STATUS,
1626 AR_RTC_STATUS_M,
1627 AR_RTC_STATUS_ON)) {
1628 HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC not waking up\n",
1629 __func__);
1630 return AH_FALSE;
1631 }
1632
1633 ath9k_hw_read_revisions(ah);
1634
1635 return ath9k_hw_set_reset(ah, HAL_RESET_WARM);
1636 }
1637
1638 static enum hal_bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1639 u_int32_t type)
1640 {
1641 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1642 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1643
1644 switch (type) {
1645 case HAL_RESET_POWER_ON:
1646 return ath9k_hw_set_reset_power_on(ah);
1647 break;
1648 case HAL_RESET_WARM:
1649 case HAL_RESET_COLD:
1650 return ath9k_hw_set_reset(ah, type);
1651 break;
1652 default:
1653 return AH_FALSE;
1654 }
1655 }
1656
1657 static inline struct hal_channel_internal *ath9k_hw_check_chan(
1658 struct ath_hal *ah, struct hal_channel *chan)
1659 {
1660 if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
1661 HDPRINTF(ah, HAL_DBG_CHANNEL,
1662 "%s: invalid channel %u/0x%x; not marked as "
1663 "2GHz or 5GHz\n", __func__, chan->channel,
1664 chan->channelFlags);
1665 return NULL;
1666 }
1667
1668 if ((IS(chan, CHANNEL_OFDM)
1669 ^ IS(chan, CHANNEL_CCK)
1670 ^ IS(chan, CHANNEL_HT20)
1671 ^ IS(chan, CHANNEL_HT40PLUS)
1672 ^ IS(chan, CHANNEL_HT40MINUS)) == 0) {
1673 HDPRINTF(ah, HAL_DBG_CHANNEL,
1674 "%s: invalid channel %u/0x%x; not marked as "
1675 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1676 __func__, chan->channel, chan->channelFlags);
1677 return NULL;
1678 }
1679
1680 return ath9k_regd_check_channel(ah, chan);
1681 }
1682
1683 static inline enum hal_bool
1684 ath9k_hw_get_lower_upper_index(u_int8_t target,
1685 u_int8_t *pList,
1686 u_int16_t listSize,
1687 u_int16_t *indexL,
1688 u_int16_t *indexR)
1689 {
1690 u_int16_t i;
1691
1692 if (target <= pList[0]) {
1693 *indexL = *indexR = 0;
1694 return AH_TRUE;
1695 }
1696 if (target >= pList[listSize - 1]) {
1697 *indexL = *indexR = (u_int16_t) (listSize - 1);
1698 return AH_TRUE;
1699 }
1700
1701 for (i = 0; i < listSize - 1; i++) {
1702 if (pList[i] == target) {
1703 *indexL = *indexR = i;
1704 return AH_TRUE;
1705 }
1706 if (target < pList[i + 1]) {
1707 *indexL = i;
1708 *indexR = (u_int16_t) (i + 1);
1709 return AH_FALSE;
1710 }
1711 }
1712 return AH_FALSE;
1713 }
1714
1715 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1716 {
1717 int16_t nfval;
1718 int16_t sort[HAL_NF_CAL_HIST_MAX];
1719 int i, j;
1720
1721 for (i = 0; i < HAL_NF_CAL_HIST_MAX; i++)
1722 sort[i] = nfCalBuffer[i];
1723
1724 for (i = 0; i < HAL_NF_CAL_HIST_MAX - 1; i++) {
1725 for (j = 1; j < HAL_NF_CAL_HIST_MAX - i; j++) {
1726 if (sort[j] > sort[j - 1]) {
1727 nfval = sort[j];
1728 sort[j] = sort[j - 1];
1729 sort[j - 1] = nfval;
1730 }
1731 }
1732 }
1733 nfval = sort[(HAL_NF_CAL_HIST_MAX - 1) >> 1];
1734
1735 return nfval;
1736 }
1737
1738 static void ath9k_hw_update_nfcal_hist_buffer(struct hal_nfcal_hist *h,
1739 int16_t *nfarray)
1740 {
1741 int i;
1742
1743 for (i = 0; i < NUM_NF_READINGS; i++) {
1744 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1745
1746 if (++h[i].currIndex >= HAL_NF_CAL_HIST_MAX)
1747 h[i].currIndex = 0;
1748
1749 if (h[i].invalidNFcount > 0) {
1750 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1751 || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1752 h[i].invalidNFcount = HAL_NF_CAL_HIST_MAX;
1753 } else {
1754 h[i].invalidNFcount--;
1755 h[i].privNF = nfarray[i];
1756 }
1757 } else {
1758 h[i].privNF =
1759 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1760 }
1761 }
1762 return;
1763 }
1764
1765 static void ar5416GetNoiseFloor(struct ath_hal *ah,
1766 int16_t nfarray[NUM_NF_READINGS])
1767 {
1768 int16_t nf;
1769
1770 if (AR_SREV_9280_10_OR_LATER(ah))
1771 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1772 else
1773 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1774
1775 if (nf & 0x100)
1776 nf = 0 - ((nf ^ 0x1ff) + 1);
1777 HDPRINTF(ah, HAL_DBG_CALIBRATE,
1778 "NF calibrated [ctl] [chain 0] is %d\n", nf);
1779 nfarray[0] = nf;
1780
1781 if (AR_SREV_9280_10_OR_LATER(ah))
1782 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1783 AR9280_PHY_CH1_MINCCA_PWR);
1784 else
1785 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1786 AR_PHY_CH1_MINCCA_PWR);
1787
1788 if (nf & 0x100)
1789 nf = 0 - ((nf ^ 0x1ff) + 1);
1790 HDPRINTF(ah, HAL_DBG_NF_CAL,
1791 "NF calibrated [ctl] [chain 1] is %d\n", nf);
1792 nfarray[1] = nf;
1793
1794 if (!AR_SREV_9280(ah)) {
1795 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1796 AR_PHY_CH2_MINCCA_PWR);
1797 if (nf & 0x100)
1798 nf = 0 - ((nf ^ 0x1ff) + 1);
1799 HDPRINTF(ah, HAL_DBG_NF_CAL,
1800 "NF calibrated [ctl] [chain 2] is %d\n", nf);
1801 nfarray[2] = nf;
1802 }
1803
1804 if (AR_SREV_9280_10_OR_LATER(ah))
1805 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1806 AR9280_PHY_EXT_MINCCA_PWR);
1807 else
1808 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1809 AR_PHY_EXT_MINCCA_PWR);
1810
1811 if (nf & 0x100)
1812 nf = 0 - ((nf ^ 0x1ff) + 1);
1813 HDPRINTF(ah, HAL_DBG_NF_CAL,
1814 "NF calibrated [ext] [chain 0] is %d\n", nf);
1815 nfarray[3] = nf;
1816
1817 if (AR_SREV_9280_10_OR_LATER(ah))
1818 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1819 AR9280_PHY_CH1_EXT_MINCCA_PWR);
1820 else
1821 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1822 AR_PHY_CH1_EXT_MINCCA_PWR);
1823
1824 if (nf & 0x100)
1825 nf = 0 - ((nf ^ 0x1ff) + 1);
1826 HDPRINTF(ah, HAL_DBG_CALIBRATE,
1827 "NF calibrated [ext] [chain 1] is %d\n", nf);
1828 nfarray[4] = nf;
1829
1830 if (!AR_SREV_9280(ah)) {
1831 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1832 AR_PHY_CH2_EXT_MINCCA_PWR);
1833 if (nf & 0x100)
1834 nf = 0 - ((nf ^ 0x1ff) + 1);
1835 HDPRINTF(ah, HAL_DBG_NF_CAL,
1836 "NF calibrated [ext] [chain 2] is %d\n", nf);
1837 nfarray[5] = nf;
1838 }
1839 }
1840
1841 static enum hal_bool
1842 getNoiseFloorThresh(struct ath_hal *ah,
1843 const struct hal_channel_internal *chan,
1844 int16_t *nft)
1845 {
1846 struct ath_hal_5416 *ahp = AH5416(ah);
1847
1848 switch (chan->channelFlags & CHANNEL_ALL) {
1849 case CHANNEL_A:
1850 case CHANNEL_A_HT20:
1851 case CHANNEL_A_HT40PLUS:
1852 case CHANNEL_A_HT40MINUS:
1853 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5);
1854 break;
1855 case CHANNEL_B:
1856 case CHANNEL_G:
1857 case CHANNEL_G_HT20:
1858 case CHANNEL_G_HT40PLUS:
1859 case CHANNEL_G_HT40MINUS:
1860 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1861 break;
1862 default:
1863 HDPRINTF(ah, HAL_DBG_CHANNEL,
1864 "%s: invalid channel flags 0x%x\n", __func__,
1865 chan->channelFlags);
1866 return AH_FALSE;
1867 }
1868 return AH_TRUE;
1869 }
1870
1871 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1872 {
1873 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1874 AR_PHY_AGC_CONTROL_ENABLE_NF);
1875 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1876 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1877 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1878 }
1879
1880 static void
1881 ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
1882 {
1883 struct hal_nfcal_hist *h;
1884 int i, j;
1885 int32_t val;
1886 const u_int32_t ar5416_cca_regs[6] = {
1887 AR_PHY_CCA,
1888 AR_PHY_CH1_CCA,
1889 AR_PHY_CH2_CCA,
1890 AR_PHY_EXT_CCA,
1891 AR_PHY_CH1_EXT_CCA,
1892 AR_PHY_CH2_EXT_CCA
1893 };
1894 u_int8_t chainmask;
1895
1896 if (AR_SREV_9280(ah))
1897 chainmask = 0x1B;
1898 else
1899 chainmask = 0x3F;
1900
1901 #ifdef ATH_NF_PER_CHAN
1902 h = chan->nfCalHist;
1903 #else
1904 h = ah->nfCalHist;
1905 #endif
1906
1907 for (i = 0; i < NUM_NF_READINGS; i++) {
1908 if (chainmask & (1 << i)) {
1909 val = REG_READ(ah, ar5416_cca_regs[i]);
1910 val &= 0xFFFFFE00;
1911 val |= (((u_int32_t) (h[i].privNF) << 1) & 0x1ff);
1912 REG_WRITE(ah, ar5416_cca_regs[i], val);
1913 }
1914 }
1915
1916 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1917 AR_PHY_AGC_CONTROL_ENABLE_NF);
1918 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1919 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1920 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1921
1922 for (j = 0; j < 1000; j++) {
1923 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1924 AR_PHY_AGC_CONTROL_NF) == 0)
1925 break;
1926 udelay(10);
1927 }
1928
1929 for (i = 0; i < NUM_NF_READINGS; i++) {
1930 if (chainmask & (1 << i)) {
1931 val = REG_READ(ah, ar5416_cca_regs[i]);
1932 val &= 0xFFFFFE00;
1933 val |= (((u_int32_t) (-50) << 1) & 0x1ff);
1934 REG_WRITE(ah, ar5416_cca_regs[i], val);
1935 }
1936 }
1937 }
1938
1939 static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1940 struct hal_channel_internal *chan)
1941 {
1942 int16_t nf, nfThresh;
1943 int16_t nfarray[NUM_NF_READINGS] = { 0 };
1944 struct hal_nfcal_hist *h;
1945 u_int8_t chainmask;
1946
1947 if (AR_SREV_9280(ah))
1948 chainmask = 0x1B;
1949 else
1950 chainmask = 0x3F;
1951
1952 chan->channelFlags &= (~CHANNEL_CW_INT);
1953 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1954 HDPRINTF(ah, HAL_DBG_CALIBRATE,
1955 "%s: NF did not complete in calibration window\n",
1956 __func__);
1957 nf = 0;
1958 chan->rawNoiseFloor = nf;
1959 return chan->rawNoiseFloor;
1960 } else {
1961 ar5416GetNoiseFloor(ah, nfarray);
1962 nf = nfarray[0];
1963 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1964 && nf > nfThresh) {
1965 HDPRINTF(ah, HAL_DBG_CALIBRATE,
1966 "%s: noise floor failed detected; "
1967 "detected %d, threshold %d\n", __func__,
1968 nf, nfThresh);
1969 chan->channelFlags |= CHANNEL_CW_INT;
1970 }
1971 }
1972
1973 #ifdef ATH_NF_PER_CHAN
1974 h = chan->nfCalHist;
1975 #else
1976 h = ah->nfCalHist;
1977 #endif
1978
1979 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1980 chan->rawNoiseFloor = h[0].privNF;
1981
1982 return chan->rawNoiseFloor;
1983 }
1984
1985 static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1986 struct hal_mib_stats *stats)
1987 {
1988 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1989 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1990 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1991 stats->rts_good += REG_READ(ah, AR_RTS_OK);
1992 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1993 }
1994
1995 static void ath9k_enable_mib_counters(struct ath_hal *ah)
1996 {
1997 struct ath_hal_5416 *ahp = AH5416(ah);
1998
1999 HDPRINTF(ah, HAL_DBG_ANI, "Enable mib counters\n");
2000
2001 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2002
2003 REG_WRITE(ah, AR_FILT_OFDM, 0);
2004 REG_WRITE(ah, AR_FILT_CCK, 0);
2005 REG_WRITE(ah, AR_MIBC,
2006 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
2007 & 0x0f);
2008 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2009 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2010 }
2011
2012 static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2013 {
2014 struct ath_hal_5416 *ahp = AH5416(ah);
2015
2016 HDPRINTF(ah, HAL_DBG_ANI, "Disabling MIB counters\n");
2017
2018 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2019
2020 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2021
2022 REG_WRITE(ah, AR_FILT_OFDM, 0);
2023 REG_WRITE(ah, AR_FILT_CCK, 0);
2024 }
2025
2026 static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2027 struct hal_channel_internal *chan)
2028 {
2029 struct ath_hal_5416 *ahp = AH5416(ah);
2030 int i;
2031
2032 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2033 if (ahp->ah_ani[i].c.channel == chan->channel)
2034 return i;
2035 if (ahp->ah_ani[i].c.channel == 0) {
2036 ahp->ah_ani[i].c.channel = chan->channel;
2037 ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2038 return i;
2039 }
2040 }
2041
2042 HDPRINTF(ah, HAL_DBG_ANI,
2043 "No more channel states left. Using channel 0\n");
2044 return 0;
2045 }
2046
2047 static void ath9k_hw_ani_attach(struct ath_hal *ah)
2048 {
2049 struct ath_hal_5416 *ahp = AH5416(ah);
2050 int i;
2051
2052 ahp->ah_hasHwPhyCounters = 1;
2053
2054 memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2055 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2056 ahp->ah_ani[i].ofdmTrigHigh = HAL_ANI_OFDM_TRIG_HIGH;
2057 ahp->ah_ani[i].ofdmTrigLow = HAL_ANI_OFDM_TRIG_LOW;
2058 ahp->ah_ani[i].cckTrigHigh = HAL_ANI_CCK_TRIG_HIGH;
2059 ahp->ah_ani[i].cckTrigLow = HAL_ANI_CCK_TRIG_LOW;
2060 ahp->ah_ani[i].rssiThrHigh = HAL_ANI_RSSI_THR_HIGH;
2061 ahp->ah_ani[i].rssiThrLow = HAL_ANI_RSSI_THR_LOW;
2062 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2063 !HAL_ANI_USE_OFDM_WEAK_SIG;
2064 ahp->ah_ani[i].cckWeakSigThreshold =
2065 HAL_ANI_CCK_WEAK_SIG_THR;
2066 ahp->ah_ani[i].spurImmunityLevel = HAL_ANI_SPUR_IMMUNE_LVL;
2067 ahp->ah_ani[i].firstepLevel = HAL_ANI_FIRSTEP_LVL;
2068 if (ahp->ah_hasHwPhyCounters) {
2069 ahp->ah_ani[i].ofdmPhyErrBase =
2070 AR_PHY_COUNTMAX - HAL_ANI_OFDM_TRIG_HIGH;
2071 ahp->ah_ani[i].cckPhyErrBase =
2072 AR_PHY_COUNTMAX - HAL_ANI_CCK_TRIG_HIGH;
2073 }
2074 }
2075 if (ahp->ah_hasHwPhyCounters) {
2076 HDPRINTF(ah, HAL_DBG_ANI, "Setting OfdmErrBase = 0x%08x\n",
2077 ahp->ah_ani[0].ofdmPhyErrBase);
2078 HDPRINTF(ah, HAL_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2079 ahp->ah_ani[0].cckPhyErrBase);
2080
2081 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2082 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2083 ath9k_enable_mib_counters(ah);
2084 }
2085 ahp->ah_aniPeriod = HAL_ANI_PERIOD;
2086 if (ah->ah_config.ath_hal_enableANI)
2087 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2088 }
2089
2090 static inline void ath9k_hw_ani_setup(struct ath_hal *ah)
2091 {
2092 struct ath_hal_5416 *ahp = AH5416(ah);
2093 int i;
2094
2095 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
2096 const int coarseHigh[] = { -14, -14, -14, -14, -12 };
2097 const int coarseLow[] = { -64, -64, -64, -64, -70 };
2098 const int firpwr[] = { -78, -78, -78, -78, -80 };
2099
2100 for (i = 0; i < 5; i++) {
2101 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
2102 ahp->ah_coarseHigh[i] = coarseHigh[i];
2103 ahp->ah_coarseLow[i] = coarseLow[i];
2104 ahp->ah_firpwr[i] = firpwr[i];
2105 }
2106 }
2107
2108 static void ath9k_hw_ani_detach(struct ath_hal *ah)
2109 {
2110 struct ath_hal_5416 *ahp = AH5416(ah);
2111
2112 HDPRINTF(ah, HAL_DBG_ANI, "Detaching Ani\n");
2113 if (ahp->ah_hasHwPhyCounters) {
2114 ath9k_hw_disable_mib_counters(ah);
2115 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2116 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2117 }
2118 }
2119
2120
2121 static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
2122 enum hal_ani_cmd cmd, int param)
2123 {
2124 struct ath_hal_5416 *ahp = AH5416(ah);
2125 struct ar5416AniState *aniState = ahp->ah_curani;
2126
2127 switch (cmd & ahp->ah_ani_function) {
2128 case HAL_ANI_NOISE_IMMUNITY_LEVEL:{
2129 u_int level = param;
2130
2131 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2132 HDPRINTF(ah, HAL_DBG_ANI,
2133 "%s: level out of range (%u > %u)\n",
2134 __func__, level,
2135 (unsigned) ARRAY_SIZE(ahp->
2136 ah_totalSizeDesired));
2137 return AH_FALSE;
2138 }
2139
2140 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2141 AR_PHY_DESIRED_SZ_TOT_DES,
2142 ahp->ah_totalSizeDesired[level]);
2143 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2144 AR_PHY_AGC_CTL1_COARSE_LOW,
2145 ahp->ah_coarseLow[level]);
2146 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2147 AR_PHY_AGC_CTL1_COARSE_HIGH,
2148 ahp->ah_coarseHigh[level]);
2149 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2150 AR_PHY_FIND_SIG_FIRPWR,
2151 ahp->ah_firpwr[level]);
2152
2153 if (level > aniState->noiseImmunityLevel)
2154 ahp->ah_stats.ast_ani_niup++;
2155 else if (level < aniState->noiseImmunityLevel)
2156 ahp->ah_stats.ast_ani_nidown++;
2157 aniState->noiseImmunityLevel = level;
2158 break;
2159 }
2160 case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2161 const int m1ThreshLow[] = { 127, 50 };
2162 const int m2ThreshLow[] = { 127, 40 };
2163 const int m1Thresh[] = { 127, 0x4d };
2164 const int m2Thresh[] = { 127, 0x40 };
2165 const int m2CountThr[] = { 31, 16 };
2166 const int m2CountThrLow[] = { 63, 48 };
2167 u_int on = param ? 1 : 0;
2168
2169 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2170 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2171 m1ThreshLow[on]);
2172 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2173 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2174 m2ThreshLow[on]);
2175 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2176 AR_PHY_SFCORR_M1_THRESH,
2177 m1Thresh[on]);
2178 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2179 AR_PHY_SFCORR_M2_THRESH,
2180 m2Thresh[on]);
2181 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2182 AR_PHY_SFCORR_M2COUNT_THR,
2183 m2CountThr[on]);
2184 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2185 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2186 m2CountThrLow[on]);
2187
2188 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2189 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2190 m1ThreshLow[on]);
2191 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2192 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2193 m2ThreshLow[on]);
2194 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2195 AR_PHY_SFCORR_EXT_M1_THRESH,
2196 m1Thresh[on]);
2197 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2198 AR_PHY_SFCORR_EXT_M2_THRESH,
2199 m2Thresh[on]);
2200
2201 if (on)
2202 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2203 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2204 else
2205 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2206 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2207
2208 if (!on != aniState->ofdmWeakSigDetectOff) {
2209 if (on)
2210 ahp->ah_stats.ast_ani_ofdmon++;
2211 else
2212 ahp->ah_stats.ast_ani_ofdmoff++;
2213 aniState->ofdmWeakSigDetectOff = !on;
2214 }
2215 break;
2216 }
2217 case HAL_ANI_CCK_WEAK_SIGNAL_THR:{
2218 const int weakSigThrCck[] = { 8, 6 };
2219 u_int high = param ? 1 : 0;
2220
2221 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2222 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2223 weakSigThrCck[high]);
2224 if (high != aniState->cckWeakSigThreshold) {
2225 if (high)
2226 ahp->ah_stats.ast_ani_cckhigh++;
2227 else
2228 ahp->ah_stats.ast_ani_ccklow++;
2229 aniState->cckWeakSigThreshold = high;
2230 }
2231 break;
2232 }
2233 case HAL_ANI_FIRSTEP_LEVEL:{
2234 const int firstep[] = { 0, 4, 8 };
2235 u_int level = param;
2236
2237 if (level >= ARRAY_SIZE(firstep)) {
2238 HDPRINTF(ah, HAL_DBG_ANI,
2239 "%s: level out of range (%u > %u)\n",
2240 __func__, level,
2241 (unsigned) ARRAY_SIZE(firstep));
2242 return AH_FALSE;
2243 }
2244 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2245 AR_PHY_FIND_SIG_FIRSTEP,
2246 firstep[level]);
2247 if (level > aniState->firstepLevel)
2248 ahp->ah_stats.ast_ani_stepup++;
2249 else if (level < aniState->firstepLevel)
2250 ahp->ah_stats.ast_ani_stepdown++;
2251 aniState->firstepLevel = level;
2252 break;
2253 }
2254 case HAL_ANI_SPUR_IMMUNITY_LEVEL:{
2255 const int cycpwrThr1[] =
2256 { 2, 4, 6, 8, 10, 12, 14, 16 };
2257 u_int level = param;
2258
2259 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2260 HDPRINTF(ah, HAL_DBG_ANI,
2261 "%s: level out of range (%u > %u)\n",
2262 __func__, level,
2263 (unsigned)
2264 ARRAY_SIZE(cycpwrThr1));
2265 return AH_FALSE;
2266 }
2267 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2268 AR_PHY_TIMING5_CYCPWR_THR1,
2269 cycpwrThr1[level]);
2270 if (level > aniState->spurImmunityLevel)
2271 ahp->ah_stats.ast_ani_spurup++;
2272 else if (level < aniState->spurImmunityLevel)
2273 ahp->ah_stats.ast_ani_spurdown++;
2274 aniState->spurImmunityLevel = level;
2275 break;
2276 }
2277 case HAL_ANI_PRESENT:
2278 break;
2279 default:
2280 HDPRINTF(ah, HAL_DBG_ANI, "%s: invalid cmd %u\n", __func__,
2281 cmd);
2282 return AH_FALSE;
2283 }
2284
2285 HDPRINTF(ah, HAL_DBG_ANI, "%s: ANI parameters:\n", __func__);
2286 HDPRINTF(ah, HAL_DBG_ANI,
2287 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2288 "ofdmWeakSigDetectOff=%d\n",
2289 aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2290 !aniState->ofdmWeakSigDetectOff);
2291 HDPRINTF(ah, HAL_DBG_ANI,
2292 "cckWeakSigThreshold=%d, "
2293 "firstepLevel=%d, listenTime=%d\n",
2294 aniState->cckWeakSigThreshold, aniState->firstepLevel,
2295 aniState->listenTime);
2296 HDPRINTF(ah, HAL_DBG_ANI,
2297 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2298 aniState->cycleCount, aniState->ofdmPhyErrCount,
2299 aniState->cckPhyErrCount);
2300 return AH_TRUE;
2301 }
2302
2303 static void ath9k_ani_restart(struct ath_hal *ah)
2304 {
2305 struct ath_hal_5416 *ahp = AH5416(ah);
2306 struct ar5416AniState *aniState;
2307
2308 if (!DO_ANI(ah))
2309 return;
2310
2311 aniState = ahp->ah_curani;
2312
2313 aniState->listenTime = 0;
2314 if (ahp->ah_hasHwPhyCounters) {
2315 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2316 aniState->ofdmPhyErrBase = 0;
2317 HDPRINTF(ah, HAL_DBG_ANI,
2318 "OFDM Trigger is too high for hw counters\n");
2319 } else {
2320 aniState->ofdmPhyErrBase =
2321 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2322 }
2323 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2324 aniState->cckPhyErrBase = 0;
2325 HDPRINTF(ah, HAL_DBG_ANI,
2326 "CCK Trigger is too high for hw counters\n");
2327 } else {
2328 aniState->cckPhyErrBase =
2329 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2330 }
2331 HDPRINTF(ah, HAL_DBG_ANI,
2332 "%s: Writing ofdmbase=%u cckbase=%u\n",
2333 __func__, aniState->ofdmPhyErrBase,
2334 aniState->cckPhyErrBase);
2335 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2336 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2337 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2338 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2339
2340 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2341 }
2342 aniState->ofdmPhyErrCount = 0;
2343 aniState->cckPhyErrCount = 0;
2344 }
2345
2346 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2347 {
2348 struct ath_hal_5416 *ahp = AH5416(ah);
2349 struct hal_channel_internal *chan = ah->ah_curchan;
2350 struct ar5416AniState *aniState;
2351 enum wireless_mode mode;
2352 int32_t rssi;
2353
2354 if (!DO_ANI(ah))
2355 return;
2356
2357 aniState = ahp->ah_curani;
2358
2359 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2360 if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2361 aniState->noiseImmunityLevel +
2362 1) == AH_TRUE) {
2363 return;
2364 }
2365 }
2366
2367 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2368 if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
2369 aniState->spurImmunityLevel +
2370 1) == AH_TRUE) {
2371 return;
2372 }
2373 }
2374
2375 if (ah->ah_opmode == HAL_M_HOSTAP) {
2376 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2377 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2378 aniState->firstepLevel + 1);
2379 }
2380 return;
2381 }
2382 rssi = BEACON_RSSI(ahp);
2383 if (rssi > aniState->rssiThrHigh) {
2384 if (!aniState->ofdmWeakSigDetectOff) {
2385 if (ath9k_hw_ani_control(ah,
2386 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2387 AH_FALSE) == AH_TRUE) {
2388 ath9k_hw_ani_control(ah,
2389 HAL_ANI_SPUR_IMMUNITY_LEVEL,
2390 0);
2391 return;
2392 }
2393 }
2394 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2395 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2396 aniState->firstepLevel + 1);
2397 return;
2398 }
2399 } else if (rssi > aniState->rssiThrLow) {
2400 if (aniState->ofdmWeakSigDetectOff)
2401 ath9k_hw_ani_control(ah,
2402 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2403 AH_TRUE);
2404 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2405 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2406 aniState->firstepLevel + 1);
2407 return;
2408 } else {
2409 mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
2410 if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
2411 if (!aniState->ofdmWeakSigDetectOff)
2412 ath9k_hw_ani_control(ah,
2413 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2414 AH_FALSE);
2415 if (aniState->firstepLevel > 0)
2416 ath9k_hw_ani_control(ah,
2417 HAL_ANI_FIRSTEP_LEVEL,
2418 0);
2419 return;
2420 }
2421 }
2422 }
2423
2424 static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2425 {
2426 struct ath_hal_5416 *ahp = AH5416(ah);
2427 struct hal_channel_internal *chan = ah->ah_curchan;
2428 struct ar5416AniState *aniState;
2429 enum wireless_mode mode;
2430 int32_t rssi;
2431
2432 if (!DO_ANI(ah))
2433 return;
2434
2435 aniState = ahp->ah_curani;
2436 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2437 if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2438 aniState->noiseImmunityLevel +
2439 1) == AH_TRUE) {
2440 return;
2441 }
2442 }
2443 if (ah->ah_opmode == HAL_M_HOSTAP) {
2444 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2445 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2446 aniState->firstepLevel + 1);
2447 }
2448 return;
2449 }
2450 rssi = BEACON_RSSI(ahp);
2451 if (rssi > aniState->rssiThrLow) {
2452 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2453 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2454 aniState->firstepLevel + 1);
2455 } else {
2456 mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
2457 if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
2458 if (aniState->firstepLevel > 0)
2459 ath9k_hw_ani_control(ah,
2460 HAL_ANI_FIRSTEP_LEVEL,
2461 0);
2462 }
2463 }
2464 }
2465
2466 static void ath9k_ani_reset(struct ath_hal *ah)
2467 {
2468 struct ath_hal_5416 *ahp = AH5416(ah);
2469 struct ar5416AniState *aniState;
2470 struct hal_channel_internal *chan = ah->ah_curchan;
2471 int index;
2472
2473 if (!DO_ANI(ah))
2474 return;
2475
2476 index = ath9k_hw_get_ani_channel_idx(ah, chan);
2477 aniState = &ahp->ah_ani[index];
2478 ahp->ah_curani = aniState;
2479
2480 if (DO_ANI(ah) && ah->ah_opmode != HAL_M_STA
2481 && ah->ah_opmode != HAL_M_IBSS) {
2482 HDPRINTF(ah, HAL_DBG_ANI,
2483 "%s: Reset ANI state opmode %u\n", __func__,
2484 ah->ah_opmode);
2485 ahp->ah_stats.ast_ani_reset++;
2486 ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
2487 ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
2488 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
2489 ath9k_hw_ani_control(ah,
2490 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2491 !HAL_ANI_USE_OFDM_WEAK_SIG);
2492 ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
2493 HAL_ANI_CCK_WEAK_SIG_THR);
2494 ath9k_hw_setrxfilter(ah,
2495 ath9k_hw_getrxfilter(ah) |
2496 HAL_RX_FILTER_PHYERR);
2497 if (ah->ah_opmode == HAL_M_HOSTAP) {
2498 ahp->ah_curani->ofdmTrigHigh =
2499 ah->ah_config.ath_hal_ofdmTrigHigh;
2500 ahp->ah_curani->ofdmTrigLow =
2501 ah->ah_config.ath_hal_ofdmTrigLow;
2502 ahp->ah_curani->cckTrigHigh =
2503 ah->ah_config.ath_hal_cckTrigHigh;
2504 ahp->ah_curani->cckTrigLow =
2505 ah->ah_config.ath_hal_cckTrigLow;
2506 }
2507 ath9k_ani_restart(ah);
2508 return;
2509 }
2510
2511 if (aniState->noiseImmunityLevel != 0)
2512 ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2513 aniState->noiseImmunityLevel);
2514 if (aniState->spurImmunityLevel != 0)
2515 ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
2516 aniState->spurImmunityLevel);
2517 if (aniState->ofdmWeakSigDetectOff)
2518 ath9k_hw_ani_control(ah,
2519 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2520 !aniState->ofdmWeakSigDetectOff);
2521 if (aniState->cckWeakSigThreshold)
2522 ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
2523 aniState->cckWeakSigThreshold);
2524 if (aniState->firstepLevel != 0)
2525 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2526 aniState->firstepLevel);
2527 if (ahp->ah_hasHwPhyCounters) {
2528 ath9k_hw_setrxfilter(ah,
2529 ath9k_hw_getrxfilter(ah) &
2530 ~HAL_RX_FILTER_PHYERR);
2531 ath9k_ani_restart(ah);
2532 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2533 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2534
2535 } else {
2536 ath9k_ani_restart(ah);
2537 ath9k_hw_setrxfilter(ah,
2538 ath9k_hw_getrxfilter(ah) |
2539 HAL_RX_FILTER_PHYERR);
2540 }
2541 }
2542
2543 void ath9k_hw_procmibevent(struct ath_hal *ah,
2544 const struct hal_node_stats *stats)
2545 {
2546 struct ath_hal_5416 *ahp = AH5416(ah);
2547 u_int32_t phyCnt1, phyCnt2;
2548
2549 HDPRINTF(ah, HAL_DBG_ANI, "Processing Mib Intr\n");
2550
2551 REG_WRITE(ah, AR_FILT_OFDM, 0);
2552 REG_WRITE(ah, AR_FILT_CCK, 0);
2553 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2554 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2555
2556 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2557 ahp->ah_stats.ast_nodestats = *stats;
2558
2559 if (!DO_ANI(ah))
2560 return;
2561
2562 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2563 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2564 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2565 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2566 struct ar5416AniState *aniState = ahp->ah_curani;
2567 u_int32_t ofdmPhyErrCnt, cckPhyErrCnt;
2568
2569 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2570 ahp->ah_stats.ast_ani_ofdmerrs +=
2571 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2572 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2573
2574 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2575 ahp->ah_stats.ast_ani_cckerrs +=
2576 cckPhyErrCnt - aniState->cckPhyErrCount;
2577 aniState->cckPhyErrCount = cckPhyErrCnt;
2578
2579 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2580 ath9k_hw_ani_ofdm_err_trigger(ah);
2581 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2582 ath9k_hw_ani_cck_err_trigger(ah);
2583
2584 ath9k_ani_restart(ah);
2585 }
2586 }
2587
2588 static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2589 {
2590 struct ath_hal_5416 *ahp = AH5416(ah);
2591 struct ar5416AniState *aniState;
2592 int32_t rssi;
2593
2594 aniState = ahp->ah_curani;
2595
2596 if (ah->ah_opmode == HAL_M_HOSTAP) {
2597 if (aniState->firstepLevel > 0) {
2598 if (ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2599 aniState->firstepLevel -
2600 1) == AH_TRUE) {
2601 return;
2602 }
2603 }
2604 } else {
2605 rssi = BEACON_RSSI(ahp);
2606 if (rssi > aniState->rssiThrHigh) {
2607
2608 } else if (rssi > aniState->rssiThrLow) {
2609 if (aniState->ofdmWeakSigDetectOff) {
2610 if (ath9k_hw_ani_control(ah,
2611 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2612 AH_TRUE) ==
2613 AH_TRUE) {
2614 return;
2615 }
2616 }
2617 if (aniState->firstepLevel > 0) {
2618 if (ath9k_hw_ani_control
2619 (ah, HAL_ANI_FIRSTEP_LEVEL,
2620 aniState->firstepLevel - 1) ==
2621 AH_TRUE) {
2622 return;
2623 }
2624 }
2625 } else {
2626 if (aniState->firstepLevel > 0) {
2627 if (ath9k_hw_ani_control
2628 (ah, HAL_ANI_FIRSTEP_LEVEL,
2629 aniState->firstepLevel - 1) ==
2630 AH_TRUE) {
2631 return;
2632 }
2633 }
2634 }
2635 }
2636
2637 if (aniState->spurImmunityLevel > 0) {
2638 if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
2639 aniState->spurImmunityLevel -
2640 1) == AH_TRUE) {
2641 return;
2642 }
2643 }
2644
2645 if (aniState->noiseImmunityLevel > 0) {
2646 ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2647 aniState->noiseImmunityLevel - 1);
2648 return;
2649 }
2650 }
2651
2652 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2653 {
2654 struct ath_hal_5416 *ahp = AH5416(ah);
2655 struct ar5416AniState *aniState;
2656 u_int32_t txFrameCount, rxFrameCount, cycleCount;
2657 int32_t listenTime;
2658
2659 txFrameCount = REG_READ(ah, AR_TFCNT);
2660 rxFrameCount = REG_READ(ah, AR_RFCNT);
2661 cycleCount = REG_READ(ah, AR_CCCNT);
2662
2663 aniState = ahp->ah_curani;
2664 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2665
2666 listenTime = 0;
2667 ahp->ah_stats.ast_ani_lzero++;
2668 } else {
2669 int32_t ccdelta = cycleCount - aniState->cycleCount;
2670 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2671 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2672 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2673 }
2674 aniState->cycleCount = cycleCount;
2675 aniState->txFrameCount = txFrameCount;
2676 aniState->rxFrameCount = rxFrameCount;
2677
2678 return listenTime;
2679 }
2680
2681 void ath9k_hw_ani_monitor(struct ath_hal *ah,
2682 const struct hal_node_stats *stats,
2683 struct hal_channel *chan)
2684 {