add the new ath9k driver (loads successfully on an AR9160 card, but still seems to...
[openwrt/svn-archive/archive.git] / package / ath9k / src / drivers / net / wireless / ath9k / hw.h
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22
23 struct ar5416_desc {
24 u_int32_t ds_link;
25 u_int32_t ds_data;
26 u_int32_t ds_ctl0;
27 u_int32_t ds_ctl1;
28 union {
29 struct {
30 u_int32_t ctl2;
31 u_int32_t ctl3;
32 u_int32_t ctl4;
33 u_int32_t ctl5;
34 u_int32_t ctl6;
35 u_int32_t ctl7;
36 u_int32_t ctl8;
37 u_int32_t ctl9;
38 u_int32_t ctl10;
39 u_int32_t ctl11;
40 u_int32_t status0;
41 u_int32_t status1;
42 u_int32_t status2;
43 u_int32_t status3;
44 u_int32_t status4;
45 u_int32_t status5;
46 u_int32_t status6;
47 u_int32_t status7;
48 u_int32_t status8;
49 u_int32_t status9;
50 } tx;
51 struct {
52 u_int32_t status0;
53 u_int32_t status1;
54 u_int32_t status2;
55 u_int32_t status3;
56 u_int32_t status4;
57 u_int32_t status5;
58 u_int32_t status6;
59 u_int32_t status7;
60 u_int32_t status8;
61 } rx;
62 } u;
63 } __packed;
64
65 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
66 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
67
68 #define ds_ctl2 u.tx.ctl2
69 #define ds_ctl3 u.tx.ctl3
70 #define ds_ctl4 u.tx.ctl4
71 #define ds_ctl5 u.tx.ctl5
72 #define ds_ctl6 u.tx.ctl6
73 #define ds_ctl7 u.tx.ctl7
74 #define ds_ctl8 u.tx.ctl8
75 #define ds_ctl9 u.tx.ctl9
76 #define ds_ctl10 u.tx.ctl10
77 #define ds_ctl11 u.tx.ctl11
78
79 #define ds_txstatus0 u.tx.status0
80 #define ds_txstatus1 u.tx.status1
81 #define ds_txstatus2 u.tx.status2
82 #define ds_txstatus3 u.tx.status3
83 #define ds_txstatus4 u.tx.status4
84 #define ds_txstatus5 u.tx.status5
85 #define ds_txstatus6 u.tx.status6
86 #define ds_txstatus7 u.tx.status7
87 #define ds_txstatus8 u.tx.status8
88 #define ds_txstatus9 u.tx.status9
89
90 #define ds_rxstatus0 u.rx.status0
91 #define ds_rxstatus1 u.rx.status1
92 #define ds_rxstatus2 u.rx.status2
93 #define ds_rxstatus3 u.rx.status3
94 #define ds_rxstatus4 u.rx.status4
95 #define ds_rxstatus5 u.rx.status5
96 #define ds_rxstatus6 u.rx.status6
97 #define ds_rxstatus7 u.rx.status7
98 #define ds_rxstatus8 u.rx.status8
99
100 #define AR_FrameLen 0x00000fff
101 #define AR_VirtMoreFrag 0x00001000
102 #define AR_TxCtlRsvd00 0x0000e000
103 #define AR_XmitPower 0x003f0000
104 #define AR_XmitPower_S 16
105 #define AR_RTSEnable 0x00400000
106 #define AR_VEOL 0x00800000
107 #define AR_ClrDestMask 0x01000000
108 #define AR_TxCtlRsvd01 0x1e000000
109 #define AR_TxIntrReq 0x20000000
110 #define AR_DestIdxValid 0x40000000
111 #define AR_CTSEnable 0x80000000
112
113 #define AR_BufLen 0x00000fff
114 #define AR_TxMore 0x00001000
115 #define AR_DestIdx 0x000fe000
116 #define AR_DestIdx_S 13
117 #define AR_FrameType 0x00f00000
118 #define AR_FrameType_S 20
119 #define AR_NoAck 0x01000000
120 #define AR_InsertTS 0x02000000
121 #define AR_CorruptFCS 0x04000000
122 #define AR_ExtOnly 0x08000000
123 #define AR_ExtAndCtl 0x10000000
124 #define AR_MoreAggr 0x20000000
125 #define AR_IsAggr 0x40000000
126
127 #define AR_BurstDur 0x00007fff
128 #define AR_BurstDur_S 0
129 #define AR_DurUpdateEna 0x00008000
130 #define AR_XmitDataTries0 0x000f0000
131 #define AR_XmitDataTries0_S 16
132 #define AR_XmitDataTries1 0x00f00000
133 #define AR_XmitDataTries1_S 20
134 #define AR_XmitDataTries2 0x0f000000
135 #define AR_XmitDataTries2_S 24
136 #define AR_XmitDataTries3 0xf0000000
137 #define AR_XmitDataTries3_S 28
138
139 #define AR_XmitRate0 0x000000ff
140 #define AR_XmitRate0_S 0
141 #define AR_XmitRate1 0x0000ff00
142 #define AR_XmitRate1_S 8
143 #define AR_XmitRate2 0x00ff0000
144 #define AR_XmitRate2_S 16
145 #define AR_XmitRate3 0xff000000
146 #define AR_XmitRate3_S 24
147
148 #define AR_PacketDur0 0x00007fff
149 #define AR_PacketDur0_S 0
150 #define AR_RTSCTSQual0 0x00008000
151 #define AR_PacketDur1 0x7fff0000
152 #define AR_PacketDur1_S 16
153 #define AR_RTSCTSQual1 0x80000000
154
155 #define AR_PacketDur2 0x00007fff
156 #define AR_PacketDur2_S 0
157 #define AR_RTSCTSQual2 0x00008000
158 #define AR_PacketDur3 0x7fff0000
159 #define AR_PacketDur3_S 16
160 #define AR_RTSCTSQual3 0x80000000
161
162 #define AR_AggrLen 0x0000ffff
163 #define AR_AggrLen_S 0
164 #define AR_TxCtlRsvd60 0x00030000
165 #define AR_PadDelim 0x03fc0000
166 #define AR_PadDelim_S 18
167 #define AR_EncrType 0x0c000000
168 #define AR_EncrType_S 26
169 #define AR_TxCtlRsvd61 0xf0000000
170
171 #define AR_2040_0 0x00000001
172 #define AR_GI0 0x00000002
173 #define AR_ChainSel0 0x0000001c
174 #define AR_ChainSel0_S 2
175 #define AR_2040_1 0x00000020
176 #define AR_GI1 0x00000040
177 #define AR_ChainSel1 0x00000380
178 #define AR_ChainSel1_S 7
179 #define AR_2040_2 0x00000400
180 #define AR_GI2 0x00000800
181 #define AR_ChainSel2 0x00007000
182 #define AR_ChainSel2_S 12
183 #define AR_2040_3 0x00008000
184 #define AR_GI3 0x00010000
185 #define AR_ChainSel3 0x000e0000
186 #define AR_ChainSel3_S 17
187 #define AR_RTSCTSRate 0x0ff00000
188 #define AR_RTSCTSRate_S 20
189 #define AR_TxCtlRsvd70 0xf0000000
190
191 #define AR_TxRSSIAnt00 0x000000ff
192 #define AR_TxRSSIAnt00_S 0
193 #define AR_TxRSSIAnt01 0x0000ff00
194 #define AR_TxRSSIAnt01_S 8
195 #define AR_TxRSSIAnt02 0x00ff0000
196 #define AR_TxRSSIAnt02_S 16
197 #define AR_TxStatusRsvd00 0x3f000000
198 #define AR_TxBaStatus 0x40000000
199 #define AR_TxStatusRsvd01 0x80000000
200
201 #define AR_FrmXmitOK 0x00000001
202 #define AR_ExcessiveRetries 0x00000002
203 #define AR_FIFOUnderrun 0x00000004
204 #define AR_Filtered 0x00000008
205 #define AR_RTSFailCnt 0x000000f0
206 #define AR_RTSFailCnt_S 4
207 #define AR_DataFailCnt 0x00000f00
208 #define AR_DataFailCnt_S 8
209 #define AR_VirtRetryCnt 0x0000f000
210 #define AR_VirtRetryCnt_S 12
211 #define AR_TxDelimUnderrun 0x00010000
212 #define AR_TxDataUnderrun 0x00020000
213 #define AR_DescCfgErr 0x00040000
214 #define AR_TxTimerExpired 0x00080000
215 #define AR_TxStatusRsvd10 0xfff00000
216
217 #define AR_SendTimestamp ds_txstatus2
218 #define AR_BaBitmapLow ds_txstatus3
219 #define AR_BaBitmapHigh ds_txstatus4
220
221 #define AR_TxRSSIAnt10 0x000000ff
222 #define AR_TxRSSIAnt10_S 0
223 #define AR_TxRSSIAnt11 0x0000ff00
224 #define AR_TxRSSIAnt11_S 8
225 #define AR_TxRSSIAnt12 0x00ff0000
226 #define AR_TxRSSIAnt12_S 16
227 #define AR_TxRSSICombined 0xff000000
228 #define AR_TxRSSICombined_S 24
229
230 #define AR_TxEVM0 ds_txstatus5
231 #define AR_TxEVM1 ds_txstatus6
232 #define AR_TxEVM2 ds_txstatus7
233
234 #define AR_TxDone 0x00000001
235 #define AR_SeqNum 0x00001ffe
236 #define AR_SeqNum_S 1
237 #define AR_TxStatusRsvd80 0x0001e000
238 #define AR_TxOpExceeded 0x00020000
239 #define AR_TxStatusRsvd81 0x001c0000
240 #define AR_FinalTxIdx 0x00600000
241 #define AR_FinalTxIdx_S 21
242 #define AR_TxStatusRsvd82 0x01800000
243 #define AR_PowerMgmt 0x02000000
244 #define AR_TxStatusRsvd83 0xfc000000
245
246 #define AR_RxCTLRsvd00 0xffffffff
247
248 #define AR_BufLen 0x00000fff
249 #define AR_RxCtlRsvd00 0x00001000
250 #define AR_RxIntrReq 0x00002000
251 #define AR_RxCtlRsvd01 0xffffc000
252
253 #define AR_RxRSSIAnt00 0x000000ff
254 #define AR_RxRSSIAnt00_S 0
255 #define AR_RxRSSIAnt01 0x0000ff00
256 #define AR_RxRSSIAnt01_S 8
257 #define AR_RxRSSIAnt02 0x00ff0000
258 #define AR_RxRSSIAnt02_S 16
259 #define AR_RxRate 0xff000000
260 #define AR_RxRate_S 24
261 #define AR_RxStatusRsvd00 0xff000000
262
263 #define AR_DataLen 0x00000fff
264 #define AR_RxMore 0x00001000
265 #define AR_NumDelim 0x003fc000
266 #define AR_NumDelim_S 14
267 #define AR_RxStatusRsvd10 0xff800000
268
269 #define AR_RcvTimestamp ds_rxstatus2
270
271 #define AR_GI 0x00000001
272 #define AR_2040 0x00000002
273 #define AR_Parallel40 0x00000004
274 #define AR_Parallel40_S 2
275 #define AR_RxStatusRsvd30 0x000000f8
276 #define AR_RxAntenna 0xffffff00
277 #define AR_RxAntenna_S 8
278
279 #define AR_RxRSSIAnt10 0x000000ff
280 #define AR_RxRSSIAnt10_S 0
281 #define AR_RxRSSIAnt11 0x0000ff00
282 #define AR_RxRSSIAnt11_S 8
283 #define AR_RxRSSIAnt12 0x00ff0000
284 #define AR_RxRSSIAnt12_S 16
285 #define AR_RxRSSICombined 0xff000000
286 #define AR_RxRSSICombined_S 24
287
288 #define AR_RxEVM0 ds_rxstatus4
289 #define AR_RxEVM1 ds_rxstatus5
290 #define AR_RxEVM2 ds_rxstatus6
291
292 #define AR_RxDone 0x00000001
293 #define AR_RxFrameOK 0x00000002
294 #define AR_CRCErr 0x00000004
295 #define AR_DecryptCRCErr 0x00000008
296 #define AR_PHYErr 0x00000010
297 #define AR_MichaelErr 0x00000020
298 #define AR_PreDelimCRCErr 0x00000040
299 #define AR_RxStatusRsvd70 0x00000080
300 #define AR_RxKeyIdxValid 0x00000100
301 #define AR_KeyIdx 0x0000fe00
302 #define AR_KeyIdx_S 9
303 #define AR_PHYErrCode 0x0000ff00
304 #define AR_PHYErrCode_S 8
305 #define AR_RxMoreAggr 0x00010000
306 #define AR_RxAggr 0x00020000
307 #define AR_PostDelimCRCErr 0x00040000
308 #define AR_RxStatusRsvd71 0x3ff80000
309 #define AR_DecryptBusyErr 0x40000000
310 #define AR_KeyMiss 0x80000000
311
312 #define AR5416_MAGIC 0x19641014
313
314 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
315 MS(ads->ds_rxstatus0, AR_RxRate) : \
316 (ads->ds_rxstatus3 >> 2) & 0xFF)
317 #define RXSTATUS_DUPLICATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
318 MS(ads->ds_rxstatus3, AR_Parallel40) : \
319 (ads->ds_rxstatus3 >> 10) & 0x1)
320
321 #define set11nTries(_series, _index) \
322 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
323
324 #define set11nRate(_series, _index) \
325 (SM((_series)[_index].Rate, AR_XmitRate##_index))
326
327 #define set11nPktDurRTSCTS(_series, _index) \
328 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
329 ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ? \
330 AR_RTSCTSQual##_index : 0))
331
332 #define set11nRateFlags(_series, _index) \
333 (((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? \
334 AR_2040_##_index : 0) \
335 |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? \
336 AR_GI##_index : 0) \
337 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
338
339 #define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100)
340
341 #define INIT_CONFIG_STATUS 0x00000000
342 #define INIT_RSSI_THR 0x00000700
343 #define INIT_BCON_CNTRL_REG 0x00000000
344
345 #define MIN_TX_FIFO_THRESHOLD 0x1
346 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
347 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
348
349 #define NUM_CORNER_FIX_BITS_2133 7
350 #define CCK_OFDM_GAIN_DELTA 15
351
352 struct ar5416AniState {
353 struct hal_channel c;
354 u_int8_t noiseImmunityLevel;
355 u_int8_t spurImmunityLevel;
356 u_int8_t firstepLevel;
357 u_int8_t ofdmWeakSigDetectOff;
358 u_int8_t cckWeakSigThreshold;
359 u_int32_t listenTime;
360 u_int32_t ofdmTrigHigh;
361 u_int32_t ofdmTrigLow;
362 int32_t cckTrigHigh;
363 int32_t cckTrigLow;
364 int32_t rssiThrLow;
365 int32_t rssiThrHigh;
366 u_int32_t noiseFloor;
367 u_int32_t txFrameCount;
368 u_int32_t rxFrameCount;
369 u_int32_t cycleCount;
370 u_int32_t ofdmPhyErrCount;
371 u_int32_t cckPhyErrCount;
372 u_int32_t ofdmPhyErrBase;
373 u_int32_t cckPhyErrBase;
374 int16_t pktRssi[2];
375 int16_t ofdmErrRssi[2];
376 int16_t cckErrRssi[2];
377 };
378
379 #define HAL_PROCESS_ANI 0x00000001
380 #define HAL_RADAR_EN 0x80000000
381 #define HAL_AR_EN 0x40000000
382
383 #define DO_ANI(ah) \
384 ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
385
386 struct ar5416Stats {
387 u_int32_t ast_ani_niup;
388 u_int32_t ast_ani_nidown;
389 u_int32_t ast_ani_spurup;
390 u_int32_t ast_ani_spurdown;
391 u_int32_t ast_ani_ofdmon;
392 u_int32_t ast_ani_ofdmoff;
393 u_int32_t ast_ani_cckhigh;
394 u_int32_t ast_ani_ccklow;
395 u_int32_t ast_ani_stepup;
396 u_int32_t ast_ani_stepdown;
397 u_int32_t ast_ani_ofdmerrs;
398 u_int32_t ast_ani_cckerrs;
399 u_int32_t ast_ani_reset;
400 u_int32_t ast_ani_lzero;
401 u_int32_t ast_ani_lneg;
402 struct hal_mib_stats ast_mibstats;
403 struct hal_node_stats ast_nodestats;
404 };
405
406 #define AR5416_OPFLAGS_11A 0x01
407 #define AR5416_OPFLAGS_11G 0x02
408 #define AR5416_OPFLAGS_N_5G_HT40 0x04
409 #define AR5416_OPFLAGS_N_2G_HT40 0x08
410 #define AR5416_OPFLAGS_N_5G_HT20 0x10
411 #define AR5416_OPFLAGS_N_2G_HT20 0x20
412
413 #define EEP_RFSILENT_ENABLED 0x0001
414 #define EEP_RFSILENT_ENABLED_S 0
415 #define EEP_RFSILENT_POLARITY 0x0002
416 #define EEP_RFSILENT_POLARITY_S 1
417 #define EEP_RFSILENT_GPIO_SEL 0x001c
418 #define EEP_RFSILENT_GPIO_SEL_S 2
419
420 #define AR5416_EEP_NO_BACK_VER 0x1
421 #define AR5416_EEP_VER 0xE
422 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
423 #define AR5416_EEP_MINOR_VER_2 0x2
424 #define AR5416_EEP_MINOR_VER_3 0x3
425 #define AR5416_EEP_MINOR_VER_7 0x7
426 #define AR5416_EEP_MINOR_VER_9 0x9
427
428 #define AR5416_EEP_START_LOC 256
429 #define AR5416_NUM_5G_CAL_PIERS 8
430 #define AR5416_NUM_2G_CAL_PIERS 4
431 #define AR5416_NUM_5G_20_TARGET_POWERS 8
432 #define AR5416_NUM_5G_40_TARGET_POWERS 8
433 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
434 #define AR5416_NUM_2G_20_TARGET_POWERS 4
435 #define AR5416_NUM_2G_40_TARGET_POWERS 4
436 #define AR5416_NUM_CTLS 24
437 #define AR5416_NUM_BAND_EDGES 8
438 #define AR5416_NUM_PD_GAINS 4
439 #define AR5416_PD_GAINS_IN_MASK 4
440 #define AR5416_PD_GAIN_ICEPTS 5
441 #define AR5416_EEPROM_MODAL_SPURS 5
442 #define AR5416_MAX_RATE_POWER 63
443 #define AR5416_NUM_PDADC_VALUES 128
444 #define AR5416_NUM_RATES 16
445 #define AR5416_BCHAN_UNUSED 0xFF
446 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
447 #define AR5416_EEPMISC_BIG_ENDIAN 0x01
448 #define AR5416_MAX_CHAINS 3
449 #define AR5416_ANT_16S 25
450
451 #define AR5416_NUM_ANT_CHAIN_FIELDS 7
452 #define AR5416_NUM_ANT_COMMON_FIELDS 4
453 #define AR5416_SIZE_ANT_CHAIN_FIELD 3
454 #define AR5416_SIZE_ANT_COMMON_FIELD 4
455 #define AR5416_ANT_CHAIN_MASK 0x7
456 #define AR5416_ANT_COMMON_MASK 0xf
457 #define AR5416_CHAIN_0_IDX 0
458 #define AR5416_CHAIN_1_IDX 1
459 #define AR5416_CHAIN_2_IDX 2
460
461 #define AR5416_PWR_TABLE_OFFSET -5
462 #define AR5416_LEGACY_CHAINMASK 1
463
464 enum eeprom_param {
465 EEP_NFTHRESH_5,
466 EEP_NFTHRESH_2,
467 EEP_MAC_MSW,
468 EEP_MAC_MID,
469 EEP_MAC_LSW,
470 EEP_REG_0,
471 EEP_REG_1,
472 EEP_OP_CAP,
473 EEP_OP_MODE,
474 EEP_RF_SILENT,
475 EEP_OB_5,
476 EEP_DB_5,
477 EEP_OB_2,
478 EEP_DB_2,
479 EEP_MINOR_REV,
480 EEP_TX_MASK,
481 EEP_RX_MASK,
482 };
483
484 enum ar5416_rates {
485 rate6mb, rate9mb, rate12mb, rate18mb,
486 rate24mb, rate36mb, rate48mb, rate54mb,
487 rate1l, rate2l, rate2s, rate5_5l,
488 rate5_5s, rate11l, rate11s, rateXr,
489 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
490 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
491 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
492 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
493 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
494 Ar5416RateSize
495 };
496
497 struct base_eep_header {
498 u_int16_t length;
499 u_int16_t checksum;
500 u_int16_t version;
501 u_int8_t opCapFlags;
502 u_int8_t eepMisc;
503 u_int16_t regDmn[2];
504 u_int8_t macAddr[6];
505 u_int8_t rxMask;
506 u_int8_t txMask;
507 u_int16_t rfSilent;
508 u_int16_t blueToothOptions;
509 u_int16_t deviceCap;
510 u_int32_t binBuildNumber;
511 u_int8_t deviceType;
512 u_int8_t pwdclkind;
513 u_int8_t futureBase[32];
514 } __packed;
515
516 struct spur_chan {
517 u_int16_t spurChan;
518 u_int8_t spurRangeLow;
519 u_int8_t spurRangeHigh;
520 } __packed;
521
522 struct modal_eep_header {
523 u_int32_t antCtrlChain[AR5416_MAX_CHAINS];
524 u_int32_t antCtrlCommon;
525 u_int8_t antennaGainCh[AR5416_MAX_CHAINS];
526 u_int8_t switchSettling;
527 u_int8_t txRxAttenCh[AR5416_MAX_CHAINS];
528 u_int8_t rxTxMarginCh[AR5416_MAX_CHAINS];
529 u_int8_t adcDesiredSize;
530 u_int8_t pgaDesiredSize;
531 u_int8_t xlnaGainCh[AR5416_MAX_CHAINS];
532 u_int8_t txEndToXpaOff;
533 u_int8_t txEndToRxOn;
534 u_int8_t txFrameToXpaOn;
535 u_int8_t thresh62;
536 u_int8_t noiseFloorThreshCh[AR5416_MAX_CHAINS];
537 u_int8_t xpdGain;
538 u_int8_t xpd;
539 u_int8_t iqCalICh[AR5416_MAX_CHAINS];
540 u_int8_t iqCalQCh[AR5416_MAX_CHAINS];
541 u_int8_t pdGainOverlap;
542 u_int8_t ob;
543 u_int8_t db;
544 u_int8_t xpaBiasLvl;
545 u_int8_t pwrDecreaseFor2Chain;
546 u_int8_t pwrDecreaseFor3Chain;
547 u_int8_t txFrameToDataStart;
548 u_int8_t txFrameToPaOn;
549 u_int8_t ht40PowerIncForPdadc;
550 u_int8_t bswAtten[AR5416_MAX_CHAINS];
551 u_int8_t bswMargin[AR5416_MAX_CHAINS];
552 u_int8_t swSettleHt40;
553 u_int8_t xatten2Db[AR5416_MAX_CHAINS];
554 u_int8_t xatten2Margin[AR5416_MAX_CHAINS];
555 u_int8_t ob_ch1;
556 u_int8_t db_ch1;
557 u_int8_t useAnt1:1,
558 force_xpaon:1,
559 local_bias:1,
560 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
561 u_int8_t futureModalar9280;
562 u_int16_t xpaBiasLvlFreq[3];
563 u_int8_t futureModal[6];
564
565 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
566 } __packed;
567
568 struct cal_data_per_freq {
569 u_int8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
570 u_int8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
571 } __packed;
572
573 struct cal_target_power_leg {
574 u_int8_t bChannel;
575 u_int8_t tPow2x[4];
576 } __packed;
577
578 struct cal_target_power_ht {
579 u_int8_t bChannel;
580 u_int8_t tPow2x[8];
581 } __packed;
582
583 #ifdef __BIG_ENDIAN_BITFIELD
584 struct cal_ctl_edges {
585 u_int8_t bChannel;
586 u_int8_t flag:2, tPower:6;
587 } __packed;
588 #else
589 struct cal_ctl_edges {
590 u_int8_t bChannel;
591 u_int8_t tPower:6, flag:2;
592 } __packed;
593 #endif
594
595 struct cal_ctl_data {
596 struct cal_ctl_edges
597 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
598 } __packed;
599
600 struct ar5416_eeprom {
601 struct base_eep_header baseEepHeader;
602 u_int8_t custData[64];
603 struct modal_eep_header modalHeader[2];
604 u_int8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
605 u_int8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
606 struct cal_data_per_freq
607 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
608 struct cal_data_per_freq
609 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
610 struct cal_target_power_leg
611 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
612 struct cal_target_power_ht
613 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
614 struct cal_target_power_ht
615 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
616 struct cal_target_power_leg
617 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
618 struct cal_target_power_leg
619 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
620 struct cal_target_power_ht
621 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
622 struct cal_target_power_ht
623 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
624 u_int8_t ctlIndex[AR5416_NUM_CTLS];
625 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
626 u_int8_t padding;
627 } __packed;
628
629 struct ar5416IniArray {
630 u_int32_t *ia_array;
631 u_int32_t ia_rows;
632 u_int32_t ia_columns;
633 };
634
635 #define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
636 (iniarray)->ia_array = (u_int32_t *)(array); \
637 (iniarray)->ia_rows = (rows); \
638 (iniarray)->ia_columns = (columns); \
639 } while (0)
640
641 #define INI_RA(iniarray, row, column) \
642 (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)])
643
644 #define INIT_CAL(_perCal) do { \
645 (_perCal)->calState = CAL_WAITING; \
646 (_perCal)->calNext = NULL; \
647 } while (0)
648
649 #define INSERT_CAL(_ahp, _perCal) \
650 do { \
651 if ((_ahp)->ah_cal_list_last == NULL) { \
652 (_ahp)->ah_cal_list = \
653 (_ahp)->ah_cal_list_last = (_perCal); \
654 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
655 } else { \
656 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
657 (_ahp)->ah_cal_list_last = (_perCal); \
658 (_perCal)->calNext = (_ahp)->ah_cal_list; \
659 } \
660 } while (0)
661
662 enum hal_cal_types {
663 ADC_DC_INIT_CAL = 0x1,
664 ADC_GAIN_CAL = 0x2,
665 ADC_DC_CAL = 0x4,
666 IQ_MISMATCH_CAL = 0x8
667 };
668
669 enum hal_cal_state {
670 CAL_INACTIVE,
671 CAL_WAITING,
672 CAL_RUNNING,
673 CAL_DONE
674 };
675
676 #define MIN_CAL_SAMPLES 1
677 #define MAX_CAL_SAMPLES 64
678 #define INIT_LOG_COUNT 5
679 #define PER_MIN_LOG_COUNT 2
680 #define PER_MAX_LOG_COUNT 10
681
682 struct hal_percal_data {
683 enum hal_cal_types calType;
684 u_int32_t calNumSamples;
685 u_int32_t calCountMax;
686 void (*calCollect) (struct ath_hal *);
687 void (*calPostProc) (struct ath_hal *, u_int8_t);
688 };
689
690 struct hal_cal_list {
691 const struct hal_percal_data *calData;
692 enum hal_cal_state calState;
693 struct hal_cal_list *calNext;
694 };
695
696 struct ath_hal_5416 {
697 struct ath_hal ah;
698 struct ar5416_eeprom ah_eeprom;
699 u_int8_t ah_macaddr[ETH_ALEN];
700 u_int8_t ah_bssid[ETH_ALEN];
701 u_int8_t ah_bssidmask[ETH_ALEN];
702 u_int16_t ah_assocId;
703 int16_t ah_curchanRadIndex;
704 u_int32_t ah_maskReg;
705 struct ar5416Stats ah_stats;
706 u_int32_t ah_txDescMask;
707 u_int32_t ah_txOkInterruptMask;
708 u_int32_t ah_txErrInterruptMask;
709 u_int32_t ah_txDescInterruptMask;
710 u_int32_t ah_txEolInterruptMask;
711 u_int32_t ah_txUrnInterruptMask;
712 struct hal_tx_queue_info ah_txq[HAL_NUM_TX_QUEUES];
713 enum hal_power_mode ah_powerMode;
714 enum hal_bool ah_chipFullSleep;
715 u_int32_t ah_atimWindow;
716 enum hal_ant_setting ah_diversityControl;
717 u_int16_t ah_antennaSwitchSwap;
718 enum hal_cal_types ah_suppCals;
719 struct hal_cal_list ah_iqCalData;
720 struct hal_cal_list ah_adcGainCalData;
721 struct hal_cal_list ah_adcDcCalInitData;
722 struct hal_cal_list ah_adcDcCalData;
723 struct hal_cal_list *ah_cal_list;
724 struct hal_cal_list *ah_cal_list_last;
725 struct hal_cal_list *ah_cal_list_curr;
726 #define ah_totalPowerMeasI ah_Meas0.unsign
727 #define ah_totalPowerMeasQ ah_Meas1.unsign
728 #define ah_totalIqCorrMeas ah_Meas2.sign
729 #define ah_totalAdcIOddPhase ah_Meas0.unsign
730 #define ah_totalAdcIEvenPhase ah_Meas1.unsign
731 #define ah_totalAdcQOddPhase ah_Meas2.unsign
732 #define ah_totalAdcQEvenPhase ah_Meas3.unsign
733 #define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign
734 #define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign
735 #define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign
736 #define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign
737 union {
738 u_int32_t unsign[AR5416_MAX_CHAINS];
739 int32_t sign[AR5416_MAX_CHAINS];
740 } ah_Meas0;
741 union {
742 u_int32_t unsign[AR5416_MAX_CHAINS];
743 int32_t sign[AR5416_MAX_CHAINS];
744 } ah_Meas1;
745 union {
746 u_int32_t unsign[AR5416_MAX_CHAINS];
747 int32_t sign[AR5416_MAX_CHAINS];
748 } ah_Meas2;
749 union {
750 u_int32_t unsign[AR5416_MAX_CHAINS];
751 int32_t sign[AR5416_MAX_CHAINS];
752 } ah_Meas3;
753 u_int16_t ah_CalSamples;
754 u_int32_t ah_tx6PowerInHalfDbm;
755 u_int32_t ah_staId1Defaults;
756 u_int32_t ah_miscMode;
757 enum hal_bool ah_tpcEnabled;
758 u_int32_t ah_beaconInterval;
759 enum {
760 AUTO_32KHZ,
761 USE_32KHZ,
762 DONT_USE_32KHZ,
763 } ah_enable32kHzClock;
764 u_int32_t *ah_analogBank0Data;
765 u_int32_t *ah_analogBank1Data;
766 u_int32_t *ah_analogBank2Data;
767 u_int32_t *ah_analogBank3Data;
768 u_int32_t *ah_analogBank6Data;
769 u_int32_t *ah_analogBank6TPCData;
770 u_int32_t *ah_analogBank7Data;
771 u_int32_t *ah_addac5416_21;
772 u_int32_t *ah_bank6Temp;
773 u_int32_t ah_ofdmTxPower;
774 int16_t ah_txPowerIndexOffset;
775 u_int ah_slottime;
776 u_int ah_acktimeout;
777 u_int ah_ctstimeout;
778 u_int ah_globaltxtimeout;
779 u_int8_t ah_gBeaconRate;
780 u_int32_t ah_gpioSelect;
781 u_int32_t ah_polarity;
782 u_int32_t ah_gpioBit;
783 enum hal_bool ah_eepEnabled;
784 u_int32_t ah_procPhyErr;
785 enum hal_bool ah_hasHwPhyCounters;
786 u_int32_t ah_aniPeriod;
787 struct ar5416AniState *ah_curani;
788 struct ar5416AniState ah_ani[255];
789 int ah_totalSizeDesired[5];
790 int ah_coarseHigh[5];
791 int ah_coarseLow[5];
792 int ah_firpwr[5];
793 u_int16_t ah_ratesArray[16];
794 u_int32_t ah_intrTxqs;
795 enum hal_bool ah_intrMitigation;
796 u_int32_t ah_cycleCount;
797 u_int32_t ah_ctlBusy;
798 u_int32_t ah_extBusy;
799 enum hal_ht_extprotspacing ah_extprotspacing;
800 u_int8_t ah_txchainmask;
801 u_int8_t ah_rxchainmask;
802 int ah_hwp;
803 void __iomem *ah_cal_mem;
804 enum hal_ani_cmd ah_ani_function;
805 struct ar5416IniArray ah_iniModes;
806 struct ar5416IniArray ah_iniCommon;
807 struct ar5416IniArray ah_iniBank0;
808 struct ar5416IniArray ah_iniBB_RfGain;
809 struct ar5416IniArray ah_iniBank1;
810 struct ar5416IniArray ah_iniBank2;
811 struct ar5416IniArray ah_iniBank3;
812 struct ar5416IniArray ah_iniBank6;
813 struct ar5416IniArray ah_iniBank6TPC;
814 struct ar5416IniArray ah_iniBank7;
815 struct ar5416IniArray ah_iniAddac;
816 struct ar5416IniArray ah_iniPcieSerdes;
817 struct ar5416IniArray ah_iniModesAdditional;
818 };
819 #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
820
821 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
822
823 #define IS_5416_EMU(ah) \
824 ((ah->ah_devid == AR5416_DEVID_EMU) || \
825 (ah->ah_devid == AR5416_DEVID_EMU_PCIE))
826
827 #define ar5416RfDetach(ah) do { \
828 if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \
829 AH5416(ah)->ah_rfHal.rfDetach(ah); \
830 } while (0)
831
832 #define ath9k_hw_use_flash(_ah) \
833 (!(_ah->ah_flags & AH_USE_EEPROM))
834
835
836 #define DO_DELAY(x) do { \
837 if ((++(x) % 64) == 0) \
838 udelay(1); \
839 } while (0)
840
841 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
842 int r; \
843 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
844 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
845 INI_RA((iniarray), r, (column))); \
846 DO_DELAY(regWr); \
847 } \
848 } while (0)
849
850 #define BASE_ACTIVATE_DELAY 100
851 #define RTC_PLL_SETTLE_DELAY 1000
852 #define COEF_SCALE_S 24
853 #define HT40_CHANNEL_CENTER_SHIFT 10
854
855 #define ar5416CheckOpMode(_opmode) \
856 ((_opmode == HAL_M_STA) || (_opmode == HAL_M_IBSS) || \
857 (_opmode == HAL_M_HOSTAP) || (_opmode == HAL_M_MONITOR))
858
859 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
860
861 #define AR5416_EEPROM_S 2
862 #define AR5416_EEPROM_OFFSET 0x2000
863 #define AR5416_EEPROM_START_ADDR \
864 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
865 #define AR5416_EEPROM_MAX 0xae0
866 #define ar5416_get_eep_ver(_ahp) \
867 (((_ahp)->ah_eeprom.baseEepHeader.version >> 12) & 0xF)
868 #define ar5416_get_eep_rev(_ahp) \
869 (((_ahp)->ah_eeprom.baseEepHeader.version) & 0xFFF)
870 #define ar5416_get_ntxchains(_txchainmask) \
871 (((_txchainmask >> 2) & 1) + \
872 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
873
874 #define IS_EEP_MINOR_V3(_ahp) \
875 (ath9k_hw_get_eeprom((_ahp), EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_3)
876
877 #define FIXED_CCA_THRESHOLD 15
878
879 #ifdef __BIG_ENDIAN
880 #define AR5416_EEPROM_MAGIC 0x5aa5
881 #else
882 #define AR5416_EEPROM_MAGIC 0xa55a
883 #endif
884
885 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
886
887 #define ATH9K_ANTENNA0_CHAINMASK 0x1
888 #define ATH9K_ANTENNA1_CHAINMASK 0x2
889
890 #define ATH9K_NUM_DMA_DEBUG_REGS 8
891 #define ATH9K_NUM_QUEUES 10
892
893 #define HAL_NOISE_IMMUNE_MAX 4
894 #define HAL_SPUR_IMMUNE_MAX 7
895 #define HAL_FIRST_STEP_MAX 2
896
897 #define HAL_ANI_OFDM_TRIG_HIGH 500
898 #define HAL_ANI_OFDM_TRIG_LOW 200
899 #define HAL_ANI_CCK_TRIG_HIGH 200
900 #define HAL_ANI_CCK_TRIG_LOW 100
901 #define HAL_ANI_NOISE_IMMUNE_LVL 4
902 #define HAL_ANI_USE_OFDM_WEAK_SIG AH_TRUE
903 #define HAL_ANI_CCK_WEAK_SIG_THR AH_FALSE
904 #define HAL_ANI_SPUR_IMMUNE_LVL 7
905 #define HAL_ANI_FIRSTEP_LVL 0
906 #define HAL_ANI_RSSI_THR_HIGH 40
907 #define HAL_ANI_RSSI_THR_LOW 7
908 #define HAL_ANI_PERIOD 100
909
910 #define AR_GPIOD_MASK 0x00001FFF
911 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
912
913 #define MAX_ANALOG_START 319
914
915 #define HAL_EP_RND(x, mul) \
916 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
917 #define BEACON_RSSI(ahp) \
918 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
919 HAL_RSSI_EP_MULTIPLIER)
920
921 #define ah_mibStats ah_stats.ast_mibstats
922
923 #define AH_TIMEOUT 100000
924 #define AH_TIME_QUANTUM 10
925
926 #define IS(_c, _f) (((_c)->channelFlags & _f) || 0)
927
928 #define AR_KEYTABLE_SIZE 128
929 #define POWER_UP_TIME 200000
930
931 #define EXT_ADDITIVE (0x8000)
932 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
933 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
934 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
935
936 #define SUB_NUM_CTL_MODES_AT_5G_40 2
937 #define SUB_NUM_CTL_MODES_AT_2G_40 3
938 #define SPUR_RSSI_THRESH 40
939
940 #define TU_TO_USEC(_tu) ((_tu) << 10)
941
942 #define CAB_TIMEOUT_VAL 10
943 #define BEACON_TIMEOUT_VAL 10
944 #define MIN_BEACON_TIMEOUT_VAL 1
945 #define SLEEP_SLOP 3
946
947 #define CCK_SIFS_TIME 10
948 #define CCK_PREAMBLE_BITS 144
949 #define CCK_PLCP_BITS 48
950
951 #define OFDM_SIFS_TIME 16
952 #define OFDM_PREAMBLE_TIME 20
953 #define OFDM_PLCP_BITS 22
954 #define OFDM_SYMBOL_TIME 4
955
956 #define OFDM_SIFS_TIME_HALF 32
957 #define OFDM_PREAMBLE_TIME_HALF 40
958 #define OFDM_PLCP_BITS_HALF 22
959 #define OFDM_SYMBOL_TIME_HALF 8
960
961 #define OFDM_SIFS_TIME_QUARTER 64
962 #define OFDM_PREAMBLE_TIME_QUARTER 80
963 #define OFDM_PLCP_BITS_QUARTER 22
964 #define OFDM_SYMBOL_TIME_QUARTER 16
965
966 u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
967 enum eeprom_param param);
968
969 #endif