add the new ath9k driver (loads successfully on an AR9160 card, but still seems to...
[openwrt/svn-archive/archive.git] / package / ath9k / src / drivers / net / wireless / ath9k / phy.h
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef PHY_H
18 #define PHY_H
19
20 enum hal_bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
21 struct hal_channel_internal
22 *chan);
23 enum hal_bool ath9k_hw_set_channel(struct ath_hal *ah,
24 struct hal_channel_internal *chan);
25 void ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex,
26 u_int freqIndex, int regWrites);
27 enum hal_bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
28 struct hal_channel_internal *chan,
29 u_int16_t modesIndex);
30 void ath9k_hw_decrease_chain_power(struct ath_hal *ah,
31 struct hal_channel *chan);
32 enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah,
33 enum hal_status *status);
34
35 #define AR_PHY_BASE 0x9800
36 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
37
38 #define AR_PHY_TEST 0x9800
39 #define PHY_AGC_CLR 0x10000000
40 #define RFSILENT_BB 0x00002000
41
42 #define AR_PHY_TURBO 0x9804
43 #define AR_PHY_FC_TURBO_MODE 0x00000001
44 #define AR_PHY_FC_TURBO_SHORT 0x00000002
45 #define AR_PHY_FC_DYN2040_EN 0x00000004
46 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
47 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
48 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
49 #define AR_PHY_FC_HT_EN 0x00000040
50 #define AR_PHY_FC_SHORT_GI_40 0x00000080
51 #define AR_PHY_FC_WALSH 0x00000100
52 #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
53
54 #define AR_PHY_TIMING2 0x9810
55 #define AR_PHY_TIMING3 0x9814
56 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
57 #define AR_PHY_TIMING3_DSC_MAN_S 17
58 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000
59 #define AR_PHY_TIMING3_DSC_EXP_S 13
60
61 #define AR_PHY_CHIP_ID 0x9818
62 #define AR_PHY_CHIP_ID_REV_0 0x80
63 #define AR_PHY_CHIP_ID_REV_1 0x81
64 #define AR_PHY_CHIP_ID_9160_REV_0 0xb0
65
66 #define AR_PHY_ACTIVE 0x981C
67 #define AR_PHY_ACTIVE_EN 0x00000001
68 #define AR_PHY_ACTIVE_DIS 0x00000000
69
70 #define AR_PHY_RF_CTL2 0x9824
71 #define AR_PHY_TX_END_DATA_START 0x000000FF
72 #define AR_PHY_TX_END_DATA_START_S 0
73 #define AR_PHY_TX_END_PA_ON 0x0000FF00
74 #define AR_PHY_TX_END_PA_ON_S 8
75
76 #define AR_PHY_RF_CTL3 0x9828
77 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
78 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16
79
80 #define AR_PHY_ADC_CTL 0x982C
81 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
82 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
83 #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
84 #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
85 #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
86 #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
87 #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
88
89 #define AR_PHY_ADC_SERIAL_CTL 0x9830
90 #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
91 #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
92
93 #define AR_PHY_RF_CTL4 0x9834
94 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
95 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
96 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
97 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
98 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
99 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
100 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
101 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
102
103 #define AR_PHY_SETTLING 0x9844
104 #define AR_PHY_SETTLING_SWITCH 0x00003F80
105 #define AR_PHY_SETTLING_SWITCH_S 7
106
107 #define AR_PHY_RXGAIN 0x9848
108 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
109 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
110 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
111 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
112 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
113 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
114 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
115 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
116
117 #define AR_PHY_DESIRED_SZ 0x9850
118 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF
119 #define AR_PHY_DESIRED_SZ_ADC_S 0
120 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
121 #define AR_PHY_DESIRED_SZ_PGA_S 8
122 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
123 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
124
125 #define AR_PHY_FIND_SIG 0x9858
126 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
127 #define AR_PHY_FIND_SIG_FIRSTEP_S 12
128 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
129 #define AR_PHY_FIND_SIG_FIRPWR_S 18
130
131 #define AR_PHY_AGC_CTL1 0x985C
132 #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
133 #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
134 #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
135 #define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
136
137 #define AR_PHY_AGC_CONTROL 0x9860
138 #define AR_PHY_AGC_CONTROL_CAL 0x00000001
139 #define AR_PHY_AGC_CONTROL_NF 0x00000002
140 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
141 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
142 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
143
144 #define AR_PHY_CCA 0x9864
145 #define AR_PHY_MINCCA_PWR 0x0FF80000
146 #define AR_PHY_MINCCA_PWR_S 19
147 #define AR_PHY_CCA_THRESH62 0x0007F000
148 #define AR_PHY_CCA_THRESH62_S 12
149 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
150 #define AR9280_PHY_MINCCA_PWR_S 20
151 #define AR9280_PHY_CCA_THRESH62 0x000FF000
152 #define AR9280_PHY_CCA_THRESH62_S 12
153
154 #define AR_PHY_SFCORR_LOW 0x986C
155 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
156 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
157 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
158 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
159 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
160 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
161 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
162
163 #define AR_PHY_SFCORR 0x9868
164 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
165 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
166 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
167 #define AR_PHY_SFCORR_M1_THRESH_S 17
168 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
169 #define AR_PHY_SFCORR_M2_THRESH_S 24
170
171 #define AR_PHY_SLEEP_CTR_CONTROL 0x9870
172 #define AR_PHY_SLEEP_CTR_LIMIT 0x9874
173 #define AR_PHY_SYNTH_CONTROL 0x9874
174 #define AR_PHY_SLEEP_SCAL 0x9878
175
176 #define AR_PHY_PLL_CTL 0x987c
177 #define AR_PHY_PLL_CTL_40 0xaa
178 #define AR_PHY_PLL_CTL_40_5413 0x04
179 #define AR_PHY_PLL_CTL_44 0xab
180 #define AR_PHY_PLL_CTL_44_2133 0xeb
181 #define AR_PHY_PLL_CTL_40_2133 0xea
182
183 #define AR_PHY_RX_DELAY 0x9914
184 #define AR_PHY_SEARCH_START_DELAY 0x9918
185 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF
186
187 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
188 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
189 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
190 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
191 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
192 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
193 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
194 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
195 #define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
196
197 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
198 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
199 #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
200 #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
201
202 #define AR_PHY_TIMING5 0x9924
203 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
204 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1
205
206 #define AR_PHY_POWER_TX_RATE1 0x9934
207 #define AR_PHY_POWER_TX_RATE2 0x9938
208 #define AR_PHY_POWER_TX_RATE_MAX 0x993c
209 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
210
211 #define AR_PHY_FRAME_CTL 0x9944
212 #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
213 #define AR_PHY_FRAME_CTL_TX_CLIP_S 3
214
215 #define AR_PHY_TXPWRADJ 0x994C
216 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
217 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
218 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
219 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
220
221 #define AR_PHY_RADAR_EXT 0x9940
222 #define AR_PHY_RADAR_EXT_ENA 0x00004000
223
224 #define AR_PHY_RADAR_0 0x9954
225 #define AR_PHY_RADAR_0_ENA 0x00000001
226 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000
227 #define AR_PHY_RADAR_0_INBAND 0x0000003e
228 #define AR_PHY_RADAR_0_INBAND_S 1
229 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0
230 #define AR_PHY_RADAR_0_PRSSI_S 6
231 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000
232 #define AR_PHY_RADAR_0_HEIGHT_S 12
233 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000
234 #define AR_PHY_RADAR_0_RRSSI_S 18
235 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000
236 #define AR_PHY_RADAR_0_FIRPWR_S 24
237
238 #define AR_PHY_RADAR_1 0x9958
239 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
240 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000
241 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
242 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
243 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
244 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
245 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
246 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
247 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
248 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF
249 #define AR_PHY_RADAR_1_MAXLEN_S 0
250
251 #define AR_PHY_SWITCH_CHAIN_0 0x9960
252 #define AR_PHY_SWITCH_COM 0x9964
253
254 #define AR_PHY_SIGMA_DELTA 0x996C
255 #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
256 #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
257 #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
258 #define AR_PHY_SIGMA_DELTA_FILT2_S 3
259 #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
260 #define AR_PHY_SIGMA_DELTA_FILT1_S 8
261 #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
262 #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
263
264 #define AR_PHY_RESTART 0x9970
265 #define AR_PHY_RESTART_DIV_GC 0x001C0000
266 #define AR_PHY_RESTART_DIV_GC_S 18
267
268 #define AR_PHY_RFBUS_REQ 0x997C
269 #define AR_PHY_RFBUS_REQ_EN 0x00000001
270
271 #define AR_PHY_TIMING7 0x9980
272 #define AR_PHY_TIMING8 0x9984
273 #define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
274 #define AR_PHY_TIMING8_PILOT_MASK_2_S 0
275
276 #define AR_PHY_BIN_MASK2_1 0x9988
277 #define AR_PHY_BIN_MASK2_2 0x998c
278 #define AR_PHY_BIN_MASK2_3 0x9990
279 #define AR_PHY_BIN_MASK2_4 0x9994
280
281 #define AR_PHY_BIN_MASK_1 0x9900
282 #define AR_PHY_BIN_MASK_2 0x9904
283 #define AR_PHY_BIN_MASK_3 0x9908
284
285 #define AR_PHY_MASK_CTL 0x990c
286
287 #define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
288 #define AR_PHY_BIN_MASK2_4_MASK_4_S 0
289
290 #define AR_PHY_TIMING9 0x9998
291 #define AR_PHY_TIMING10 0x999c
292 #define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
293 #define AR_PHY_TIMING10_PILOT_MASK_2_S 0
294
295 #define AR_PHY_TIMING11 0x99a0
296 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
297 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
298 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
299 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
300 #define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
301 #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
302
303 #define AR_PHY_RX_CHAINMASK 0x99a4
304 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
305 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
306 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
307 #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
308
309 #define AR_PHY_EXT_CCA0 0x99b8
310 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
311 #define AR_PHY_EXT_CCA0_THRESH62_S 0
312
313 #define AR_PHY_EXT_CCA 0x99bc
314 #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
315 #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
316 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
317 #define AR_PHY_EXT_CCA_THRESH62_S 16
318 #define AR_PHY_EXT_MINCCA_PWR 0xFF800000
319 #define AR_PHY_EXT_MINCCA_PWR_S 23
320 #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
321 #define AR9280_PHY_EXT_MINCCA_PWR_S 16
322
323 #define AR_PHY_SFCORR_EXT 0x99c0
324 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
325 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
326 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
327 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
328 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
329 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
330 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
331 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
332 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
333
334 #define AR_PHY_HALFGI 0x99D0
335 #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
336 #define AR_PHY_HALFGI_DSC_MAN_S 4
337 #define AR_PHY_HALFGI_DSC_EXP 0x0000000F
338 #define AR_PHY_HALFGI_DSC_EXP_S 0
339
340 #define AR_PHY_CHAN_INFO_MEMORY 0x99DC
341 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
342
343 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
344
345 #define AR_PHY_M_SLEEP 0x99f0
346 #define AR_PHY_REFCLKDLY 0x99f4
347 #define AR_PHY_REFCLKPD 0x99f8
348
349 #define AR_PHY_CALMODE 0x99f0
350
351 #define AR_PHY_CALMODE_IQ 0x00000000
352 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001
353 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
354 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
355
356 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
357 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
358 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
359 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
360
361 #define AR_PHY_CURRENT_RSSI 0x9c1c
362 #define AR9280_PHY_CURRENT_RSSI 0x9c3c
363
364 #define AR_PHY_RFBUS_GRANT 0x9C20
365 #define AR_PHY_RFBUS_GRANT_EN 0x00000001
366
367 #define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
368 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
369
370 #define AR_PHY_CHAN_INFO_GAIN 0x9CFC
371
372 #define AR_PHY_MODE 0xA200
373 #define AR_PHY_MODE_AR2133 0x08
374 #define AR_PHY_MODE_AR5111 0x00
375 #define AR_PHY_MODE_AR5112 0x08
376 #define AR_PHY_MODE_DYNAMIC 0x04
377 #define AR_PHY_MODE_RF2GHZ 0x02
378 #define AR_PHY_MODE_RF5GHZ 0x00
379 #define AR_PHY_MODE_CCK 0x01
380 #define AR_PHY_MODE_OFDM 0x00
381 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
382
383 #define AR_PHY_CCK_TX_CTRL 0xA204
384 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
385
386 #define AR_PHY_CCK_DETECT 0xA208
387 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
388 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
389 /* [12:6] settling time for antenna switch */
390 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
391 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
392 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
393
394 #define AR_PHY_GAIN_2GHZ 0xA20C
395 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
396 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
397 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
398 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
399 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
400 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
401
402 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
403 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
404 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
405 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
406 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
407 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
408 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
409 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
410
411 #define AR_PHY_CCK_RXCTRL4 0xA21C
412 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
413 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
414
415 #define AR_PHY_DAG_CTRLCCK 0xA228
416 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
417 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
418 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
419
420 #define AR_PHY_FORCE_CLKEN_CCK 0xA22C
421 #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
422
423 #define AR_PHY_POWER_TX_RATE3 0xA234
424 #define AR_PHY_POWER_TX_RATE4 0xA238
425
426 #define AR_PHY_SCRM_SEQ_XR 0xA23C
427 #define AR_PHY_HEADER_DETECT_XR 0xA240
428 #define AR_PHY_CHIRP_DETECTED_XR 0xA244
429 #define AR_PHY_BLUETOOTH 0xA254
430
431 #define AR_PHY_TPCRG1 0xA258
432 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
433 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
434
435 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
436 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16
437 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
438 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18
439 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
440 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20
441
442 #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
443 #define AR_PHY_MASK2_M_31_45 0xa3a4
444 #define AR_PHY_MASK2_M_16_30 0xa3a8
445 #define AR_PHY_MASK2_M_00_15 0xa3ac
446 #define AR_PHY_MASK2_P_15_01 0xa3b8
447 #define AR_PHY_MASK2_P_30_16 0xa3bc
448 #define AR_PHY_MASK2_P_45_31 0xa3c0
449 #define AR_PHY_MASK2_P_61_45 0xa3c4
450 #define AR_PHY_SPUR_REG 0x994c
451
452 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
453 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
454
455 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
456 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
457 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
458 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
459 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
460 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
461
462 #define AR_PHY_PILOT_MASK_01_30 0xa3b0
463 #define AR_PHY_PILOT_MASK_31_60 0xa3b4
464
465 #define AR_PHY_CHANNEL_MASK_01_30 0x99d4
466 #define AR_PHY_CHANNEL_MASK_31_60 0x99d8
467
468 #define AR_PHY_ANALOG_SWAP 0xa268
469 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
470
471 #define AR_PHY_TPCRG5 0xA26C
472 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
473 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
474 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
475 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
476 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
477 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
478 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
479 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
480 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
481 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
482
483 #define AR_PHY_POWER_TX_RATE5 0xA38C
484 #define AR_PHY_POWER_TX_RATE6 0xA390
485
486 #define AR_PHY_CAL_CHAINMASK 0xA39C
487
488 #define AR_PHY_POWER_TX_SUB 0xA3C8
489 #define AR_PHY_POWER_TX_RATE7 0xA3CC
490 #define AR_PHY_POWER_TX_RATE8 0xA3D0
491 #define AR_PHY_POWER_TX_RATE9 0xA3D4
492
493 #define AR_PHY_XPA_CFG 0xA3D8
494 #define AR_PHY_FORCE_XPA_CFG 0x000000001
495 #define AR_PHY_FORCE_XPA_CFG_S 0
496
497 #define AR_PHY_CH1_CCA 0xa864
498 #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
499 #define AR_PHY_CH1_MINCCA_PWR_S 19
500 #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
501 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
502
503 #define AR_PHY_CH2_CCA 0xb864
504 #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
505 #define AR_PHY_CH2_MINCCA_PWR_S 19
506
507 #define AR_PHY_CH1_EXT_CCA 0xa9bc
508 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
509 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
510 #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
511 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
512
513 #define AR_PHY_CH2_EXT_CCA 0xb9bc
514 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
515 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
516
517 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
518 int r; \
519 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
520 REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
521 HDPRINTF(ah, HAL_DBG_CHANNEL, \
522 "RF 0x%x V 0x%x\n", \
523 INI_RA((iniarray), r, 0), (regData)[r]); \
524 DO_DELAY(regWr); \
525 } \
526 } while (0)
527
528 #define ATH9K_KEY_XOR 0xaa
529
530 #define ATH9K_IS_MIC_ENABLED(ah) \
531 (AH5416(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
532
533 #define ANTSWAP_AB 0x0001
534 #define REDUCE_CHAIN_0 0x00000050
535 #define REDUCE_CHAIN_1 0x00000051
536
537 #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
538 int i; \
539 for (i = 0; i < (_iniarray)->ia_rows; i++) \
540 (_bank)[i] = INI_RA((_iniarray), i, _col);; \
541 } while (0)
542
543 #endif