add the new ath9k driver (loads successfully on an AR9160 card, but still seems to...
[openwrt/svn-archive/archive.git] / package / ath9k / src / drivers / net / wireless / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 /*
18 * Implementation of transmit path.
19 */
20
21 #include "core.h"
22
23 #define BITS_PER_BYTE 8
24 #define OFDM_PLCP_BITS 22
25 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
27 #define L_STF 8
28 #define L_LTF 8
29 #define L_SIG 4
30 #define HT_SIG 8
31 #define HT_STF 4
32 #define HT_LTF(_ns) (4 * (_ns))
33 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
37
38 #define OFDM_SIFS_TIME 16
39
40 static u_int32_t bits_per_symbol[][2] = {
41 /* 20MHz 40MHz */
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
58 };
59
60 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
61
62 /*
63 * Insert a chain of ath_buf (descriptors) on a multicast txq
64 * but do NOT start tx DMA on this queue.
65 * NB: must be called with txq lock held
66 */
67
68 static void ath_tx_mcastqaddbuf(struct ath_softc *sc,
69 struct ath_txq *txq,
70 struct list_head *head)
71 {
72 struct ath_hal *ah = sc->sc_ah;
73 struct ath_buf *bf;
74
75 if (list_empty(head))
76 return;
77
78 /*
79 * Insert the frame on the outbound list and
80 * pass it on to the hardware.
81 */
82 bf = list_first_entry(head, struct ath_buf, list);
83
84 /*
85 * The CAB queue is started from the SWBA handler since
86 * frames only go out on DTIM and to avoid possible races.
87 */
88 ath9k_hw_set_interrupts(ah, 0);
89
90 /*
91 * If there is anything in the mcastq, we want to set
92 * the "more data" bit in the last item in the queue to
93 * indicate that there is "more data". It makes sense to add
94 * it here since you are *always* going to have
95 * more data when adding to this queue, no matter where
96 * you call from.
97 */
98
99 if (txq->axq_depth) {
100 struct ath_buf *lbf;
101 struct ieee80211_hdr *hdr;
102
103 /*
104 * Add the "more data flag" to the last frame
105 */
106
107 lbf = list_entry(txq->axq_q.prev, struct ath_buf, list);
108 hdr = (struct ieee80211_hdr *)
109 ((struct sk_buff *)(lbf->bf_mpdu))->data;
110 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
111 }
112
113 /*
114 * Now, concat the frame onto the queue
115 */
116 list_splice_tail_init(head, &txq->axq_q);
117 txq->axq_depth++;
118 txq->axq_totalqueued++;
119 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
120
121 DPRINTF(sc, ATH_DEBUG_TX_PROC,
122 "%s: txq depth = %d\n", __func__, txq->axq_depth);
123 if (txq->axq_link != NULL) {
124 *txq->axq_link = cpu_to_le32(bf->bf_daddr);
125 DPRINTF(sc, ATH_DEBUG_XMIT,
126 "%s: link[%u](%p)=%llx (%p)\n",
127 __func__,
128 txq->axq_qnum, txq->axq_link,
129 ito64(bf->bf_daddr), bf->bf_desc);
130 }
131 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
132 ath9k_hw_set_interrupts(ah, sc->sc_imask);
133 }
134
135 /*
136 * Insert a chain of ath_buf (descriptors) on a txq and
137 * assume the descriptors are already chained together by caller.
138 * NB: must be called with txq lock held
139 */
140
141 static void ath_tx_txqaddbuf(struct ath_softc *sc,
142 struct ath_txq *txq, struct list_head *head)
143 {
144 struct ath_hal *ah = sc->sc_ah;
145 struct ath_buf *bf;
146 /*
147 * Insert the frame on the outbound list and
148 * pass it on to the hardware.
149 */
150
151 if (list_empty(head))
152 return;
153
154 bf = list_first_entry(head, struct ath_buf, list);
155
156 list_splice_tail_init(head, &txq->axq_q);
157 txq->axq_depth++;
158 txq->axq_totalqueued++;
159 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
160
161 DPRINTF(sc, ATH_DEBUG_TX_PROC,
162 "%s: txq depth = %d\n", __func__, txq->axq_depth);
163
164 if (txq->axq_link == NULL) {
165 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
166 DPRINTF(sc, ATH_DEBUG_XMIT,
167 "%s: TXDP[%u] = %llx (%p)\n",
168 __func__, txq->axq_qnum,
169 ito64(bf->bf_daddr), bf->bf_desc);
170 } else {
171 *txq->axq_link = cpu_to_le32(bf->bf_daddr);
172 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
173 __func__,
174 txq->axq_qnum, txq->axq_link,
175 ito64(bf->bf_daddr), bf->bf_desc);
176 }
177 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
178 ath9k_hw_txstart(ah, txq->axq_qnum);
179 }
180
181 /* Get transmit rate index using rate in Kbps */
182
183 static int ath_tx_findindex(const struct hal_rate_table *rt, int rate)
184 {
185 int i;
186 int ndx = 0;
187
188 for (i = 0; i < rt->rateCount; i++) {
189 if (rt->info[i].rateKbps == rate) {
190 ndx = i;
191 break;
192 }
193 }
194
195 return ndx;
196 }
197
198 /* Check if it's okay to send out aggregates */
199
200 static int ath_aggr_query(struct ath_softc *sc,
201 struct ath_node *an, u_int8_t tidno)
202 {
203 struct ath_atx_tid *tid;
204 tid = ATH_AN_2_TID(an, tidno);
205
206 if (tid->addba_exchangecomplete || tid->addba_exchangeinprogress)
207 return 1;
208 else
209 return 0;
210 }
211
212 static enum hal_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
213 {
214 enum hal_pkt_type htype;
215 __le16 fc;
216
217 fc = hdr->frame_control;
218
219 /* Calculate Atheros packet type from IEEE80211 packet header */
220
221 if (ieee80211_is_beacon(fc))
222 htype = HAL_PKT_TYPE_BEACON;
223 else if (ieee80211_is_probe_resp(fc))
224 htype = HAL_PKT_TYPE_PROBE_RESP;
225 else if (ieee80211_is_atim(fc))
226 htype = HAL_PKT_TYPE_ATIM;
227 else if (ieee80211_is_pspoll(fc))
228 htype = HAL_PKT_TYPE_PSPOLL;
229 else
230 htype = HAL_PKT_TYPE_NORMAL;
231
232 return htype;
233 }
234
235 static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl)
236 {
237 struct ieee80211_hdr *hdr;
238 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
239 struct ath_tx_info_priv *tx_info_priv;
240 __le16 fc;
241
242 hdr = (struct ieee80211_hdr *)skb->data;
243 fc = hdr->frame_control;
244 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
245
246 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
247 txctl->use_minrate = 1;
248 txctl->min_rate = tx_info_priv->min_rate;
249 } else if (ieee80211_is_data(fc)) {
250 if (ieee80211_is_nullfunc(fc) ||
251 (tx_info->flags & IEEE80211_TX_CTL_EAPOL_FRAME)) {
252 txctl->use_minrate = 1;
253 txctl->min_rate = tx_info_priv->min_rate;
254 }
255 if (is_multicast_ether_addr(hdr->addr1))
256 txctl->mcast_rate = tx_info_priv->min_rate;
257 }
258
259 }
260
261 /* This function will setup additional txctl information, mostly rate stuff */
262 /* FIXME: seqno, ps */
263 static int ath_tx_prepare(struct ath_softc *sc,
264 struct sk_buff *skb,
265 struct ath_tx_control *txctl)
266 {
267 struct ieee80211_hw *hw = sc->hw;
268 struct ieee80211_hdr *hdr;
269 struct ath_rc_series *rcs;
270 struct ath_txq *txq = NULL;
271 const struct hal_rate_table *rt;
272 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
273 struct ath_tx_info_priv *tx_info_priv;
274 int hdrlen;
275 u_int8_t rix, antenna;
276 __le16 fc;
277 u8 *qc;
278
279 memset(txctl, 0, sizeof(struct ath_tx_control));
280
281 txctl->dev = sc;
282 hdr = (struct ieee80211_hdr *)skb->data;
283 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
284 fc = hdr->frame_control;
285
286 rt = sc->sc_currates;
287 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
288
289 /* Fill misc fields */
290
291 spin_lock_bh(&sc->node_lock);
292 txctl->an = ath_node_get(sc, hdr->addr1);
293 /* create a temp node, if the node is not there already */
294 if (!txctl->an)
295 txctl->an = ath_node_attach(sc, hdr->addr1, 0);
296 spin_unlock_bh(&sc->node_lock);
297
298 if (ieee80211_is_data_qos(fc)) {
299 qc = ieee80211_get_qos_ctl(hdr);
300 txctl->tidno = qc[0] & 0xf;
301 }
302
303 txctl->if_id = 0;
304 txctl->nextfraglen = 0;
305 txctl->frmlen = skb->len + FCS_LEN - (hdrlen & 3);
306 txctl->txpower = MAX_RATE_POWER; /* FIXME */
307
308 /* Fill Key related fields */
309
310 txctl->keytype = HAL_KEY_TYPE_CLEAR;
311 txctl->keyix = HAL_TXKEYIX_INVALID;
312
313 if (!(tx_info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) {
314 txctl->keyix = tx_info->control.hw_key->hw_key_idx;
315 txctl->frmlen += tx_info->control.icv_len;
316
317 if (sc->sc_keytype == HAL_CIPHER_WEP)
318 txctl->keytype = HAL_KEY_TYPE_WEP;
319 else if (sc->sc_keytype == HAL_CIPHER_TKIP)
320 txctl->keytype = HAL_KEY_TYPE_TKIP;
321 else if (sc->sc_keytype == HAL_CIPHER_AES_CCM)
322 txctl->keytype = HAL_KEY_TYPE_AES;
323 }
324
325 /* Fill packet type */
326
327 txctl->atype = get_hal_packet_type(hdr);
328
329 /* Fill qnum */
330
331 txctl->qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
332 txq = &sc->sc_txq[txctl->qnum];
333 spin_lock_bh(&txq->axq_lock);
334
335 /* Try to avoid running out of descriptors */
336 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
337 DPRINTF(sc, ATH_DEBUG_FATAL,
338 "%s: TX queue: %d is full, depth: %d\n",
339 __func__,
340 txctl->qnum,
341 txq->axq_depth);
342 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
343 txq->stopped = 1;
344 spin_unlock_bh(&txq->axq_lock);
345 return -1;
346 }
347
348 spin_unlock_bh(&txq->axq_lock);
349
350 /* Fill rate */
351
352 fill_min_rates(skb, txctl);
353
354 /* Fill flags */
355
356 txctl->flags = HAL_TXDESC_CLRDMASK; /* needed for crypto errors */
357
358 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
359 tx_info->flags |= HAL_TXDESC_NOACK;
360 if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
361 tx_info->flags |= HAL_TXDESC_RTSENA;
362
363 /*
364 * Setup for rate calculations.
365 */
366 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
367 rcs = tx_info_priv->rcs;
368
369 if (ieee80211_is_data(fc) && !txctl->use_minrate) {
370
371 /* Enable HT only for DATA frames and not for EAPOL */
372 txctl->ht = (hw->conf.ht_conf.ht_supported &&
373 (tx_info->flags & IEEE80211_TX_CTL_AMPDU));
374
375 if (is_multicast_ether_addr(hdr->addr1)) {
376 rcs[0].rix = (u_int8_t)
377 ath_tx_findindex(rt, txctl->mcast_rate);
378
379 /*
380 * mcast packets are not re-tried.
381 */
382 rcs[0].tries = 1;
383 }
384 /* For HT capable stations, we save tidno for later use.
385 * We also override seqno set by upper layer with the one
386 * in tx aggregation state.
387 *
388 * First, the fragmentation stat is determined.
389 * If fragmentation is on, the sequence number is
390 * not overridden, since it has been
391 * incremented by the fragmentation routine.
392 */
393 if (likely(!(txctl->flags & HAL_TXDESC_FRAG_IS_ON)) &&
394 txctl->ht && sc->sc_txaggr) {
395 struct ath_atx_tid *tid;
396
397 tid = ATH_AN_2_TID(txctl->an, txctl->tidno);
398
399 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
400 IEEE80211_SEQ_SEQ_SHIFT);
401 txctl->seqno = tid->seq_next;
402 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
403 }
404 } else {
405 /* for management and control frames,
406 * or for NULL and EAPOL frames */
407 if (txctl->min_rate)
408 rcs[0].rix = ath_rate_findrateix(sc, txctl->min_rate);
409 else
410 rcs[0].rix = sc->sc_minrateix;
411 rcs[0].tries = ATH_MGT_TXMAXTRY;
412 }
413 rix = rcs[0].rix;
414
415 /*
416 * Calculate duration. This logically belongs in the 802.11
417 * layer but it lacks sufficient information to calculate it.
418 */
419 if ((txctl->flags & HAL_TXDESC_NOACK) == 0 && !ieee80211_is_ctl(fc)) {
420 u_int16_t dur;
421 /*
422 * XXX not right with fragmentation.
423 */
424 if (sc->sc_flags & ATH_PREAMBLE_SHORT)
425 dur = rt->info[rix].spAckDuration;
426 else
427 dur = rt->info[rix].lpAckDuration;
428
429 if (le16_to_cpu(hdr->frame_control) &
430 IEEE80211_FCTL_MOREFRAGS) {
431 dur += dur; /* Add additional 'SIFS + ACK' */
432
433 /*
434 ** Compute size of next fragment in order to compute
435 ** durations needed to update NAV.
436 ** The last fragment uses the ACK duration only.
437 ** Add time for next fragment.
438 */
439 dur += ath9k_hw_computetxtime(sc->sc_ah, rt,
440 txctl->nextfraglen,
441 rix, sc->sc_flags & ATH_PREAMBLE_SHORT);
442 }
443
444 if (ieee80211_has_morefrags(fc) ||
445 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
446 /*
447 ** Force hardware to use computed duration for next
448 ** fragment by disabling multi-rate retry, which
449 ** updates duration based on the multi-rate
450 ** duration table.
451 */
452 rcs[1].tries = rcs[2].tries = rcs[3].tries = 0;
453 rcs[1].rix = rcs[2].rix = rcs[3].rix = 0;
454 /* reset tries but keep rate index */
455 rcs[0].tries = ATH_TXMAXTRY;
456 }
457
458 hdr->duration_id = cpu_to_le16(dur);
459 }
460
461 /*
462 * Determine if a tx interrupt should be generated for
463 * this descriptor. We take a tx interrupt to reap
464 * descriptors when the h/w hits an EOL condition or
465 * when the descriptor is specifically marked to generate
466 * an interrupt. We periodically mark descriptors in this
467 * way to insure timely replenishing of the supply needed
468 * for sending frames. Defering interrupts reduces system
469 * load and potentially allows more concurrent work to be
470 * done but if done to aggressively can cause senders to
471 * backup.
472 *
473 * NB: use >= to deal with sc_txintrperiod changing
474 * dynamically through sysctl.
475 */
476 spin_lock_bh(&txq->axq_lock);
477 if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) {
478 txctl->flags |= HAL_TXDESC_INTREQ;
479 txq->axq_intrcnt = 0;
480 }
481 spin_unlock_bh(&txq->axq_lock);
482
483 if (is_multicast_ether_addr(hdr->addr1)) {
484 antenna = sc->sc_mcastantenna + 1;
485 sc->sc_mcastantenna = (sc->sc_mcastantenna + 1) & 0x1;
486 } else
487 antenna = sc->sc_txantenna;
488
489 #ifdef USE_LEGACY_HAL
490 txctl->antenna = antenna;
491 #endif
492 return 0;
493 }
494
495 /* To complete a chain of buffers associated a frame */
496
497 static void ath_tx_complete_buf(struct ath_softc *sc,
498 struct ath_buf *bf,
499 struct list_head *bf_q,
500 int txok, int sendbar)
501 {
502 struct sk_buff *skb = bf->bf_mpdu;
503 struct ath_xmit_status tx_status;
504 dma_addr_t *pa;
505
506 /*
507 * Set retry information.
508 * NB: Don't use the information in the descriptor, because the frame
509 * could be software retried.
510 */
511 tx_status.retries = bf->bf_retries;
512 tx_status.flags = 0;
513
514 if (sendbar)
515 tx_status.flags = ATH_TX_BAR;
516
517 if (!txok) {
518 tx_status.flags |= ATH_TX_ERROR;
519
520 if (bf->bf_isxretried)
521 tx_status.flags |= ATH_TX_XRETRY;
522 }
523 /* Unmap this frame */
524 pa = get_dma_mem_context(bf, bf_dmacontext);
525 pci_unmap_single(sc->pdev,
526 *pa,
527 skb->len,
528 PCI_DMA_TODEVICE);
529 /* complete this frame */
530 ath_tx_complete(sc, skb, &tx_status, bf->bf_node);
531
532 /*
533 * Return the list of ath_buf of this mpdu to free queue
534 */
535 spin_lock_bh(&sc->sc_txbuflock);
536 list_splice_tail_init(bf_q, &sc->sc_txbuf);
537 spin_unlock_bh(&sc->sc_txbuflock);
538 }
539
540 /*
541 * queue up a dest/ac pair for tx scheduling
542 * NB: must be called with txq lock held
543 */
544
545 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
546 {
547 struct ath_atx_ac *ac = tid->ac;
548
549 /*
550 * if tid is paused, hold off
551 */
552 if (tid->paused)
553 return;
554
555 /*
556 * add tid to ac atmost once
557 */
558 if (tid->sched)
559 return;
560
561 tid->sched = AH_TRUE;
562 list_add_tail(&tid->list, &ac->tid_q);
563
564 /*
565 * add node ac to txq atmost once
566 */
567 if (ac->sched)
568 return;
569
570 ac->sched = AH_TRUE;
571 list_add_tail(&ac->list, &txq->axq_acq);
572 }
573
574 /* pause a tid */
575
576 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
577 {
578 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
579
580 spin_lock_bh(&txq->axq_lock);
581
582 tid->paused++;
583
584 spin_unlock_bh(&txq->axq_lock);
585 }
586
587 /* resume a tid and schedule aggregate */
588
589 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
590 {
591 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
592
593 ASSERT(tid->paused > 0);
594 spin_lock_bh(&txq->axq_lock);
595
596 tid->paused--;
597
598 if (tid->paused > 0)
599 goto unlock;
600
601 if (list_empty(&tid->buf_q))
602 goto unlock;
603
604 /*
605 * Add this TID to scheduler and try to send out aggregates
606 */
607 ath_tx_queue_tid(txq, tid);
608 ath_txq_schedule(sc, txq);
609 unlock:
610 spin_unlock_bh(&txq->axq_lock);
611 }
612
613 /* Compute the number of bad frames */
614
615 static int ath_tx_num_badfrms(struct ath_softc *sc,
616 struct ath_buf *bf, int txok)
617 {
618 struct ath_node *an = bf->bf_node;
619 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
620 struct ath_buf *bf_last = bf->bf_lastbf;
621 struct ath_desc *ds = bf_last->bf_desc;
622 u_int16_t seq_st = 0;
623 u_int32_t ba[WME_BA_BMP_SIZE >> 5];
624 int ba_index;
625 int nbad = 0;
626 int isaggr = 0;
627
628 if (isnodegone || ds->ds_txstat.ts_flags == HAL_TX_SW_ABORTED)
629 return 0;
630
631 isaggr = bf->bf_isaggr;
632 if (isaggr) {
633 seq_st = ATH_DS_BA_SEQ(ds);
634 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
635 }
636
637 while (bf) {
638 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
639 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
640 nbad++;
641
642 bf = bf->bf_next;
643 }
644
645 return nbad;
646 }
647
648 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
649 {
650 struct sk_buff *skb;
651 struct ieee80211_hdr *hdr;
652
653 bf->bf_isretried = 1;
654 bf->bf_retries++;
655
656 skb = bf->bf_mpdu;
657 hdr = (struct ieee80211_hdr *)skb->data;
658 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
659 }
660
661 /* Update block ack window */
662
663 static void ath_tx_update_baw(struct ath_softc *sc,
664 struct ath_atx_tid *tid, int seqno)
665 {
666 int index, cindex;
667
668 index = ATH_BA_INDEX(tid->seq_start, seqno);
669 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
670
671 tid->tx_buf[cindex] = NULL;
672
673 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
674 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
675 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
676 }
677 }
678
679 /*
680 * ath_pkt_dur - compute packet duration (NB: not NAV)
681 *
682 * rix - rate index
683 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
684 * width - 0 for 20 MHz, 1 for 40 MHz
685 * half_gi - to use 4us v/s 3.6 us for symbol time
686 */
687
688 static u_int32_t ath_pkt_duration(struct ath_softc *sc,
689 u_int8_t rix,
690 struct ath_buf *bf,
691 int width,
692 int half_gi,
693 enum hal_bool shortPreamble)
694 {
695 const struct hal_rate_table *rt = sc->sc_currates;
696 u_int32_t nbits, nsymbits, duration, nsymbols;
697 u_int8_t rc;
698 int streams, pktlen;
699
700 pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_frmlen;
701 rc = rt->info[rix].rateCode;
702
703 /*
704 * for legacy rates, use old function to compute packet duration
705 */
706 if (!IS_HT_RATE(rc))
707 return ath9k_hw_computetxtime(sc->sc_ah,
708 rt,
709 pktlen,
710 rix,
711 shortPreamble);
712 /*
713 * find number of symbols: PLCP + data
714 */
715 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
716 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
717 nsymbols = (nbits + nsymbits - 1) / nsymbits;
718
719 if (!half_gi)
720 duration = SYMBOL_TIME(nsymbols);
721 else
722 duration = SYMBOL_TIME_HALFGI(nsymbols);
723
724 /*
725 * addup duration for legacy/ht training and signal fields
726 */
727 streams = HT_RC_2_STREAMS(rc);
728 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
729 return duration;
730 }
731
732 /* Rate module function to set rate related fields in tx descriptor */
733
734 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
735 {
736 struct ath_hal *ah = sc->sc_ah;
737 const struct hal_rate_table *rt;
738 struct ath_desc *ds = bf->bf_desc;
739 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
740 struct hal_11n_rate_series series[4];
741 int i, flags, rtsctsena = 0, dynamic_mimops = 0;
742 u_int ctsduration = 0;
743 u_int8_t rix = 0, cix, ctsrate = 0;
744 u_int32_t aggr_limit_with_rts = sc->sc_rtsaggrlimit;
745 struct ath_node *an = (struct ath_node *) bf->bf_node;
746
747 /*
748 * get the cix for the lowest valid rix.
749 */
750 rt = sc->sc_currates;
751 for (i = 4; i--;) {
752 if (bf->bf_rcs[i].tries) {
753 rix = bf->bf_rcs[i].rix;
754 break;
755 }
756 }
757 flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
758 cix = rt->info[rix].controlRate;
759
760 /*
761 * If 802.11g protection is enabled, determine whether
762 * to use RTS/CTS or just CTS. Note that this is only
763 * done for OFDM/HT unicast frames.
764 */
765 if (sc->sc_protmode != PROT_M_NONE &&
766 (rt->info[rix].phy == PHY_OFDM ||
767 rt->info[rix].phy == PHY_HT) &&
768 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
769 if (sc->sc_protmode == PROT_M_RTSCTS)
770 flags = HAL_TXDESC_RTSENA;
771 else if (sc->sc_protmode == PROT_M_CTSONLY)
772 flags = HAL_TXDESC_CTSENA;
773
774 cix = rt->info[sc->sc_protrix].controlRate;
775 rtsctsena = 1;
776 }
777
778 /* For 11n, the default behavior is to enable RTS for
779 * hw retried frames. We enable the global flag here and
780 * let rate series flags determine which rates will actually
781 * use RTS.
782 */
783 if (sc->sc_hashtsupport && bf->bf_isdata) {
784 KASSERT(an != NULL, ("an == null"));
785 /*
786 * 802.11g protection not needed, use our default behavior
787 */
788 if (!rtsctsena)
789 flags = HAL_TXDESC_RTSENA;
790 /*
791 * For dynamic MIMO PS, RTS needs to precede the first aggregate
792 * and the second aggregate should have any protection at all.
793 */
794 if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
795 if (!bf->bf_aggrburst) {
796 flags = HAL_TXDESC_RTSENA;
797 dynamic_mimops = 1;
798 } else {
799 flags = 0;
800 }
801 }
802 }
803
804 /*
805 * Set protection if aggregate protection on
806 */
807 if (sc->sc_config.ath_aggr_prot &&
808 (!bf->bf_isaggr || (bf->bf_isaggr && bf->bf_al < 8192))) {
809 flags = HAL_TXDESC_RTSENA;
810 cix = rt->info[sc->sc_protrix].controlRate;
811 rtsctsena = 1;
812 }
813
814 /*
815 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
816 */
817 if (bf->bf_isaggr && (bf->bf_al > aggr_limit_with_rts)) {
818 /*
819 * Ensure that in the case of SM Dynamic power save
820 * while we are bursting the second aggregate the
821 * RTS is cleared.
822 */
823 flags &= ~(HAL_TXDESC_RTSENA);
824 }
825
826 /*
827 * CTS transmit rate is derived from the transmit rate
828 * by looking in the h/w rate table. We must also factor
829 * in whether or not a short preamble is to be used.
830 */
831 /* NB: cix is set above where RTS/CTS is enabled */
832 KASSERT(cix != 0xff, ("cix not setup"));
833 ctsrate = rt->info[cix].rateCode |
834 (bf->bf_shpreamble ? rt->info[cix].shortPreamble : 0);
835
836 /*
837 * Setup HAL rate series
838 */
839 memzero(series, sizeof(struct hal_11n_rate_series) * 4);
840
841 for (i = 0; i < 4; i++) {
842 if (!bf->bf_rcs[i].tries)
843 continue;
844
845 rix = bf->bf_rcs[i].rix;
846
847 series[i].Rate = rt->info[rix].rateCode |
848 (bf->bf_shpreamble ? rt->info[rix].shortPreamble : 0);
849
850 series[i].Tries = bf->bf_rcs[i].tries;
851
852 series[i].RateFlags = (
853 (bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
854 HAL_RATESERIES_RTS_CTS : 0) |
855 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
856 HAL_RATESERIES_2040 : 0) |
857 ((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
858 HAL_RATESERIES_HALFGI : 0);
859
860 series[i].PktDuration = ath_pkt_duration(
861 sc, rix, bf,
862 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
863 (bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG),
864 bf->bf_shpreamble);
865
866 if ((an->an_smmode == ATH_SM_PWRSAV_STATIC) &&
867 (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) == 0) {
868 /*
869 * When sending to an HT node that has enabled static
870 * SM/MIMO power save, send at single stream rates but
871 * use maximum allowed transmit chains per user,
872 * hardware, regulatory, or country limits for
873 * better range.
874 */
875 series[i].ChSel = sc->sc_tx_chainmask;
876 } else {
877 if (bf->bf_ht)
878 series[i].ChSel =
879 ath_chainmask_sel_logic(sc, an);
880 else
881 series[i].ChSel = sc->sc_tx_chainmask;
882 }
883
884 if (rtsctsena)
885 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
886
887 /*
888 * Set RTS for all rates if node is in dynamic powersave
889 * mode and we are using dual stream rates.
890 */
891 if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG))
892 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
893 }
894
895 /*
896 * For non-HT devices, calculate RTS/CTS duration in software
897 * and disable multi-rate retry.
898 */
899 if (flags && !sc->sc_hashtsupport) {
900 /*
901 * Compute the transmit duration based on the frame
902 * size and the size of an ACK frame. We call into the
903 * HAL to do the computation since it depends on the
904 * characteristics of the actual PHY being used.
905 *
906 * NB: CTS is assumed the same size as an ACK so we can
907 * use the precalculated ACK durations.
908 */
909 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */
910 ctsduration += bf->bf_shpreamble ?
911 rt->info[cix].spAckDuration :
912 rt->info[cix].lpAckDuration;
913 }
914
915 ctsduration += series[0].PktDuration;
916
917 if ((bf->bf_flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */
918 ctsduration += bf->bf_shpreamble ?
919 rt->info[rix].spAckDuration :
920 rt->info[rix].lpAckDuration;
921 }
922
923 /*
924 * Disable multi-rate retry when using RTS/CTS by clearing
925 * series 1, 2 and 3.
926 */
927 memzero(&series[1], sizeof(struct hal_11n_rate_series) * 3);
928 }
929
930 /*
931 * set dur_update_en for l-sig computation except for PS-Poll frames
932 */
933 ath9k_hw_set11n_ratescenario(ah, ds, lastds,
934 !bf->bf_ispspoll,
935 ctsrate,
936 ctsduration,
937 series, 4, flags);
938 if (sc->sc_config.ath_aggr_prot && flags)
939 ath9k_hw_set11n_burstduration(ah, ds, 8192);
940 }
941
942 /*
943 * Function to send a normal HT (non-AMPDU) frame
944 * NB: must be called with txq lock held
945 */
946
947 static int ath_tx_send_normal(struct ath_softc *sc,
948 struct ath_txq *txq,
949 struct ath_atx_tid *tid,
950 struct list_head *bf_head)
951 {
952 struct ath_buf *bf;
953 struct sk_buff *skb;
954 struct ieee80211_tx_info *tx_info;
955 struct ath_tx_info_priv *tx_info_priv;
956
957 BUG_ON(list_empty(bf_head));
958
959 bf = list_first_entry(bf_head, struct ath_buf, list);
960 bf->bf_isampdu = 0; /* regular HT frame */
961
962 skb = (struct sk_buff *)bf->bf_mpdu;
963 tx_info = IEEE80211_SKB_CB(skb);
964 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
965 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
966
967 /* update starting sequence number for subsequent ADDBA request */
968 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
969
970 /* Queue to h/w without aggregation */
971 bf->bf_nframes = 1;
972 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
973 ath_buf_set_rate(sc, bf);
974 ath_tx_txqaddbuf(sc, txq, bf_head);
975
976 return 0;
977 }
978
979 /* flush tid's software queue and send frames as non-ampdu's */
980
981 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
982 {
983 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
984 struct ath_buf *bf;
985 struct list_head bf_head;
986 INIT_LIST_HEAD(&bf_head);
987
988 ASSERT(tid->paused > 0);
989 spin_lock_bh(&txq->axq_lock);
990
991 tid->paused--;
992
993 if (tid->paused > 0) {
994 spin_unlock_bh(&txq->axq_lock);
995 return;
996 }
997
998 while (!list_empty(&tid->buf_q)) {
999 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1000 ASSERT(!bf->bf_isretried);
1001 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1002 ath_tx_send_normal(sc, txq, tid, &bf_head);
1003 }
1004
1005 spin_unlock_bh(&txq->axq_lock);
1006 }
1007
1008 /* Completion routine of an aggregate */
1009
1010 static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
1011 struct ath_txq *txq,
1012 struct ath_buf *bf,
1013 struct list_head *bf_q,
1014 int txok)
1015 {
1016 struct ath_node *an = bf->bf_node;
1017 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1018 struct ath_buf *bf_last = bf->bf_lastbf;
1019 struct ath_desc *ds = bf_last->bf_desc;
1020 struct ath_buf *bf_next, *bf_lastq = NULL;
1021 struct list_head bf_head, bf_pending;
1022 u_int16_t seq_st = 0;
1023 u_int32_t ba[WME_BA_BMP_SIZE >> 5];
1024 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
1025 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
1026
1027 isaggr = bf->bf_isaggr;
1028 if (isaggr) {
1029 if (txok) {
1030 if (ATH_DS_TX_BA(ds)) {
1031 /*
1032 * extract starting sequence and
1033 * block-ack bitmap
1034 */
1035 seq_st = ATH_DS_BA_SEQ(ds);
1036 memcpy(ba,
1037 ATH_DS_BA_BITMAP(ds),
1038 WME_BA_BMP_SIZE >> 3);
1039 } else {
1040 memzero(ba, WME_BA_BMP_SIZE >> 3);
1041
1042 /*
1043 * AR5416 can become deaf/mute when BA
1044 * issue happens. Chip needs to be reset.
1045 * But AP code may have sychronization issues
1046 * when perform internal reset in this routine.
1047 * Only enable reset in STA mode for now.
1048 */
1049 if (sc->sc_opmode == HAL_M_STA)
1050 needreset = 1;
1051 }
1052 } else {
1053 memzero(ba, WME_BA_BMP_SIZE >> 3);
1054 }
1055 }
1056
1057 INIT_LIST_HEAD(&bf_pending);
1058 INIT_LIST_HEAD(&bf_head);
1059
1060 while (bf) {
1061 txfail = txpending = 0;
1062 bf_next = bf->bf_next;
1063
1064 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
1065 /* transmit completion, subframe is
1066 * acked by block ack */
1067 } else if (!isaggr && txok) {
1068 /* transmit completion */
1069 } else {
1070
1071 if (!tid->cleanup_inprogress && !isnodegone &&
1072 ds->ds_txstat.ts_flags != HAL_TX_SW_ABORTED) {
1073 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
1074 ath_tx_set_retry(sc, bf);
1075 txpending = 1;
1076 } else {
1077 bf->bf_isxretried = 1;
1078 txfail = 1;
1079 sendbar = 1;
1080 }
1081 } else {
1082 /*
1083 * cleanup in progress, just fail
1084 * the un-acked sub-frames
1085 */
1086 txfail = 1;
1087 }
1088 }
1089 /*
1090 * Remove ath_buf's of this sub-frame from aggregate queue.
1091 */
1092 if (bf_next == NULL) { /* last subframe in the aggregate */
1093 ASSERT(bf->bf_lastfrm == bf_last);
1094
1095 /*
1096 * The last descriptor of the last sub frame could be
1097 * a holding descriptor for h/w. If that's the case,
1098 * bf->bf_lastfrm won't be in the bf_q.
1099 * Make sure we handle bf_q properly here.
1100 */
1101
1102 if (!list_empty(bf_q)) {
1103 bf_lastq = list_entry(bf_q->prev,
1104 struct ath_buf, list);
1105 list_cut_position(&bf_head,
1106 bf_q, &bf_lastq->list);
1107 } else {
1108 /*
1109 * XXX: if the last subframe only has one
1110 * descriptor which is also being used as
1111 * a holding descriptor. Then the ath_buf
1112 * is not in the bf_q at all.
1113 */
1114 INIT_LIST_HEAD(&bf_head);
1115 }
1116 } else {
1117 ASSERT(!list_empty(bf_q));
1118 list_cut_position(&bf_head,
1119 bf_q, &bf->bf_lastfrm->list);
1120 }
1121
1122 if (!txpending) {
1123 /*
1124 * complete the acked-ones/xretried ones; update
1125 * block-ack window
1126 */
1127 spin_lock_bh(&txq->axq_lock);
1128 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1129 spin_unlock_bh(&txq->axq_lock);
1130
1131 /* complete this sub-frame */
1132 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
1133 } else {
1134 /*
1135 * retry the un-acked ones
1136 */
1137 /*
1138 * XXX: if the last descriptor is holding descriptor,
1139 * in order to requeue the frame to software queue, we
1140 * need to allocate a new descriptor and
1141 * copy the content of holding descriptor to it.
1142 */
1143 if (bf->bf_next == NULL &&
1144 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
1145 struct ath_buf *tbf;
1146
1147 /* allocate new descriptor */
1148 spin_lock_bh(&sc->sc_txbuflock);
1149 ASSERT(!list_empty((&sc->sc_txbuf)));
1150 tbf = list_first_entry(&sc->sc_txbuf,
1151 struct ath_buf, list);
1152 list_del(&tbf->list);
1153 spin_unlock_bh(&sc->sc_txbuflock);
1154
1155 ATH_TXBUF_RESET(tbf);
1156
1157 /* copy descriptor content */
1158 tbf->bf_mpdu = bf_last->bf_mpdu;
1159 tbf->bf_node = bf_last->bf_node;
1160 tbf->bf_buf_addr = bf_last->bf_buf_addr;
1161 *(tbf->bf_desc) = *(bf_last->bf_desc);
1162
1163 /* link it to the frame */
1164 if (bf_lastq) {
1165 bf_lastq->bf_desc->ds_link =
1166 tbf->bf_daddr;
1167 bf->bf_lastfrm = tbf;
1168 ath9k_hw_cleartxdesc(sc->sc_ah,
1169 bf->bf_lastfrm->bf_desc);
1170 } else {
1171 tbf->bf_state = bf_last->bf_state;
1172 tbf->bf_lastfrm = tbf;
1173 ath9k_hw_cleartxdesc(sc->sc_ah,
1174 tbf->bf_lastfrm->bf_desc);
1175
1176 /* copy the DMA context */
1177 copy_dma_mem_context(
1178 get_dma_mem_context(tbf,
1179 bf_dmacontext),
1180 get_dma_mem_context(bf_last,
1181 bf_dmacontext));
1182 }
1183 list_add_tail(&tbf->list, &bf_head);
1184 } else {
1185 /*
1186 * Clear descriptor status words for
1187 * software retry
1188 */
1189 ath9k_hw_cleartxdesc(sc->sc_ah,
1190 bf->bf_lastfrm->bf_desc);
1191 }
1192
1193 /*
1194 * Put this buffer to the temporary pending
1195 * queue to retain ordering
1196 */
1197 list_splice_tail_init(&bf_head, &bf_pending);
1198 }
1199
1200 bf = bf_next;
1201 }
1202
1203 /*
1204 * node is already gone. no more assocication
1205 * with the node. the node might have been freed
1206 * any node acces can result in panic.note tid
1207 * is part of the node.
1208 */
1209 if (isnodegone)
1210 return;
1211
1212 if (tid->cleanup_inprogress) {
1213 /* check to see if we're done with cleaning the h/w queue */
1214 spin_lock_bh(&txq->axq_lock);
1215
1216 if (tid->baw_head == tid->baw_tail) {
1217 tid->addba_exchangecomplete = 0;
1218 tid->addba_exchangeattempts = 0;
1219 spin_unlock_bh(&txq->axq_lock);
1220
1221 tid->cleanup_inprogress = AH_FALSE;
1222
1223 /* send buffered frames as singles */
1224 ath_tx_flush_tid(sc, tid);
1225 } else
1226 spin_unlock_bh(&txq->axq_lock);
1227
1228 return;
1229 }
1230
1231 /*
1232 * prepend un-acked frames to the beginning of the pending frame queue
1233 */
1234 if (!list_empty(&bf_pending)) {
1235 spin_lock_bh(&txq->axq_lock);
1236 /* Note: we _prepend_, we _do_not_ at to
1237 * the end of the queue ! */
1238 list_splice(&bf_pending, &tid->buf_q);
1239 ath_tx_queue_tid(txq, tid);
1240 spin_unlock_bh(&txq->axq_lock);
1241 }
1242
1243 if (needreset)
1244 ath_internal_reset(sc);
1245
1246 return;
1247 }
1248
1249 /* Process completed xmit descriptors from the specified queue */
1250
1251 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1252 {
1253 struct ath_hal *ah = sc->sc_ah;
1254 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1255 struct list_head bf_head;
1256 struct ath_desc *ds, *tmp_ds;
1257 struct sk_buff *skb;
1258 struct ieee80211_tx_info *tx_info;
1259 struct ath_tx_info_priv *tx_info_priv;
1260 u_int8_t txant;
1261 int nacked, txok, nbad = 0, isrifs = 0;
1262 enum hal_status status;
1263
1264 DPRINTF(sc, ATH_DEBUG_TX_PROC,
1265 "%s: tx queue %d (%x), link %p\n", __func__,
1266 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1267 txq->axq_link);
1268
1269 nacked = 0;
1270 for (;;) {
1271 spin_lock_bh(&txq->axq_lock);
1272 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
1273 if (list_empty(&txq->axq_q)) {
1274 txq->axq_link = NULL;
1275 txq->axq_linkbuf = NULL;
1276 spin_unlock_bh(&txq->axq_lock);
1277 break;
1278 }
1279 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1280
1281 /*
1282 * There is a race condition that a BH gets scheduled
1283 * after sw writes TxE and before hw re-load the last
1284 * descriptor to get the newly chained one.
1285 * Software must keep the last DONE descriptor as a
1286 * holding descriptor - software does so by marking
1287 * it with the STALE flag.
1288 */
1289 bf_held = NULL;
1290 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1291 bf_held = bf;
1292 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1293 /* FIXME:
1294 * The holding descriptor is the last
1295 * descriptor in queue. It's safe to remove
1296 * the last holding descriptor in BH context.
1297 */
1298 spin_unlock_bh(&txq->axq_lock);
1299 break;
1300 } else {
1301 /* Lets work with the next buffer now */
1302 bf = list_entry(bf_held->list.next,
1303 struct ath_buf, list);
1304 }
1305 }
1306
1307 lastbf = bf->bf_lastbf;
1308 ds = lastbf->bf_desc; /* NB: last decriptor */
1309
1310 status = ath9k_hw_txprocdesc(ah, ds);
1311 if (status == HAL_EINPROGRESS) {
1312 spin_unlock_bh(&txq->axq_lock);
1313 break;
1314 }
1315 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1316 txq->axq_lastdsWithCTS = NULL;
1317 if (ds == txq->axq_gatingds)
1318 txq->axq_gatingds = NULL;
1319
1320 /*
1321 * Remove ath_buf's of the same transmit unit from txq,
1322 * however leave the last descriptor back as the holding
1323 * descriptor for hw.
1324 */
1325 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1326 INIT_LIST_HEAD(&bf_head);
1327
1328 if (!list_is_singular(&lastbf->list))
1329 list_cut_position(&bf_head,
1330 &txq->axq_q, lastbf->list.prev);
1331
1332 txq->axq_depth--;
1333
1334 if (bf->bf_isaggr)
1335 txq->axq_aggr_depth--;
1336
1337 txok = (ds->ds_txstat.ts_status == 0);
1338
1339 spin_unlock_bh(&txq->axq_lock);
1340
1341 if (bf_held) {
1342 list_del(&bf_held->list);
1343 spin_lock_bh(&sc->sc_txbuflock);
1344 list_add_tail(&bf_held->list, &sc->sc_txbuf);
1345 spin_unlock_bh(&sc->sc_txbuflock);
1346 }
1347
1348 if (txok) {
1349 txant = ds->ds_txstat.ts_antenna;
1350 sc->sc_ant_tx[txant]++;
1351 }
1352 if (!bf->bf_isampdu) {
1353 /*
1354 * This frame is sent out as a single frame.
1355 * Use hardware retry status for this frame.
1356 */
1357 bf->bf_retries = ds->ds_txstat.ts_longretry;
1358 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
1359 bf->bf_isxretried = 1;
1360 nbad = 0;
1361 } else {
1362 nbad = ath_tx_num_badfrms(sc, bf, txok);
1363 }
1364 skb = bf->bf_mpdu;
1365 tx_info = IEEE80211_SKB_CB(skb);
1366 tx_info_priv = (struct ath_tx_info_priv *)
1367 tx_info->driver_data[0];
1368 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
1369 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1370 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
1371 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
1372 if (ds->ds_txstat.ts_status == 0)
1373 nacked++;
1374
1375 if (bf->bf_isdata) {
1376 if (isrifs)
1377 tmp_ds = bf->bf_rifslast->bf_desc;
1378 else
1379 tmp_ds = ds;
1380 memcpy(&tx_info_priv->tx,
1381 &tmp_ds->ds_txstat,
1382 sizeof(tx_info_priv->tx));
1383 tx_info_priv->n_frames = bf->bf_nframes;
1384 tx_info_priv->n_bad_frames = nbad;
1385 }
1386 }
1387
1388 /*
1389 * Complete this transmit unit
1390 */
1391 if (bf->bf_isampdu)
1392 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok);
1393 else
1394 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1395
1396 /* Wake up mac80211 queue */
1397
1398 spin_lock_bh(&txq->axq_lock);
1399 if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <=
1400 (ATH_TXBUF - 20)) {
1401 int qnum;
1402 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1403 if (qnum != -1) {
1404 ieee80211_wake_queue(sc->hw, qnum);
1405 txq->stopped = 0;
1406 }
1407
1408 }
1409
1410 /*
1411 * schedule any pending packets if aggregation is enabled
1412 */
1413 if (sc->sc_txaggr)
1414 ath_txq_schedule(sc, txq);
1415 spin_unlock_bh(&txq->axq_lock);
1416 }
1417 return nacked;
1418 }
1419
1420 static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1421 {
1422 struct ath_hal *ah = sc->sc_ah;
1423
1424 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1425 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: tx queue [%u] %x, link %p\n",
1426 __func__, txq->axq_qnum,
1427 ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
1428 }
1429
1430 /* Drain only the data queues */
1431
1432 static void ath_drain_txdataq(struct ath_softc *sc, enum hal_bool retry_tx)
1433 {
1434 struct ath_hal *ah = sc->sc_ah;
1435 int i;
1436 int npend = 0;
1437 enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
1438
1439 /* XXX return value */
1440 if (!sc->sc_invalid) {
1441 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1442 if (ATH_TXQ_SETUP(sc, i)) {
1443 ath_tx_stopdma(sc, &sc->sc_txq[i]);
1444
1445 /* The TxDMA may not really be stopped.
1446 * Double check the hal tx pending count */
1447 npend += ath9k_hw_numtxpending(ah,
1448 sc->sc_txq[i].axq_qnum);
1449 }
1450 }
1451 }
1452
1453 if (npend) {
1454 enum hal_status status;
1455
1456 /* TxDMA not stopped, reset the hal */
1457 DPRINTF(sc, ATH_DEBUG_XMIT,
1458 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
1459
1460 spin_lock_bh(&sc->sc_resetlock);
1461 if (!ath9k_hw_reset(ah, sc->sc_opmode,
1462 &sc->sc_curchan, ht_macmode,
1463 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1464 sc->sc_ht_extprotspacing, AH_TRUE, &status)) {
1465
1466 DPRINTF(sc, ATH_DEBUG_FATAL,
1467 "%s: unable to reset hardware; hal status %u\n",
1468 __func__,
1469 status);
1470 }
1471 spin_unlock_bh(&sc->sc_resetlock);
1472 }
1473
1474 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1475 if (ATH_TXQ_SETUP(sc, i))
1476 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
1477 }
1478 }
1479
1480 /* Add a sub-frame to block ack window */
1481
1482 static void ath_tx_addto_baw(struct ath_softc *sc,
1483 struct ath_atx_tid *tid,
1484 struct ath_buf *bf)
1485 {
1486 int index, cindex;
1487
1488 if (bf->bf_isretried)
1489 return;
1490
1491 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
1492 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1493
1494 ASSERT(tid->tx_buf[cindex] == NULL);
1495 tid->tx_buf[cindex] = bf;
1496
1497 if (index >= ((tid->baw_tail - tid->baw_head) &
1498 (ATH_TID_MAX_BUFS - 1))) {
1499 tid->baw_tail = cindex;
1500 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1501 }
1502 }
1503
1504 /*
1505 * Function to send an A-MPDU
1506 * NB: must be called with txq lock held
1507 */
1508
1509 static int ath_tx_send_ampdu(struct ath_softc *sc,
1510 struct ath_txq *txq,
1511 struct ath_atx_tid *tid,
1512 struct list_head *bf_head,
1513 struct ath_tx_control *txctl)
1514 {
1515 struct ath_buf *bf;
1516 struct sk_buff *skb;
1517 struct ieee80211_tx_info *tx_info;
1518 struct ath_tx_info_priv *tx_info_priv;
1519
1520 BUG_ON(list_empty(bf_head));
1521
1522 bf = list_first_entry(bf_head, struct ath_buf, list);
1523 bf->bf_isampdu = 1;
1524 bf->bf_seqno = txctl->seqno; /* save seqno and tidno in buffer */
1525 bf->bf_tidno = txctl->tidno;
1526
1527 /*
1528 * Do not queue to h/w when any of the following conditions is true:
1529 * - there are pending frames in software queue
1530 * - the TID is currently paused for ADDBA/BAR request
1531 * - seqno is not within block-ack window
1532 * - h/w queue depth exceeds low water mark
1533 */
1534 if (!list_empty(&tid->buf_q) || tid->paused ||
1535 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1536 txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1537 /*
1538 * Add this frame to software queue for scheduling later
1539 * for aggregation.
1540 */
1541 list_splice_tail_init(bf_head, &tid->buf_q);
1542 ath_tx_queue_tid(txq, tid);
1543 return 0;
1544 }
1545
1546 skb = (struct sk_buff *)bf->bf_mpdu;
1547 tx_info = IEEE80211_SKB_CB(skb);
1548 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
1549 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1550
1551 /* Add sub-frame to BAW */
1552 ath_tx_addto_baw(sc, tid, bf);
1553
1554 /* Queue to h/w without aggregation */
1555 bf->bf_nframes = 1;
1556 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
1557 ath_buf_set_rate(sc, bf);
1558 ath_tx_txqaddbuf(sc, txq, bf_head);
1559 return 0;
1560 }
1561
1562 /*
1563 * looks up the rate
1564 * returns aggr limit based on lowest of the rates
1565 */
1566
1567 static u_int32_t ath_lookup_rate(struct ath_softc *sc,
1568 struct ath_buf *bf)
1569 {
1570 const struct hal_rate_table *rt = sc->sc_currates;
1571 struct sk_buff *skb;
1572 struct ieee80211_tx_info *tx_info;
1573 struct ath_tx_info_priv *tx_info_priv;
1574 u_int32_t max_4ms_framelen, frame_length;
1575 u_int16_t aggr_limit, legacy = 0, maxampdu;
1576 int i;
1577
1578
1579 skb = (struct sk_buff *)bf->bf_mpdu;
1580 tx_info = IEEE80211_SKB_CB(skb);
1581 tx_info_priv = (struct ath_tx_info_priv *)
1582 tx_info->driver_data[0];
1583 memcpy(bf->bf_rcs,
1584 tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1585
1586 /*
1587 * Find the lowest frame length among the rate series that will have a
1588 * 4ms transmit duration.
1589 * TODO - TXOP limit needs to be considered.
1590 */
1591 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
1592
1593 for (i = 0; i < 4; i++) {
1594 if (bf->bf_rcs[i].tries) {
1595 frame_length = bf->bf_rcs[i].max_4ms_framelen;
1596
1597 if (rt->info[bf->bf_rcs[i].rix].phy != PHY_HT) {
1598 legacy = 1;
1599 break;
1600 }
1601
1602 max_4ms_framelen = min(max_4ms_framelen, frame_length);
1603 }
1604 }
1605
1606 /*
1607 * limit aggregate size by the minimum rate if rate selected is
1608 * not a probe rate, if rate selected is a probe rate then
1609 * avoid aggregation of this packet.
1610 */
1611 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
1612 return 0;
1613
1614 aggr_limit = min(max_4ms_framelen,
1615 (u_int32_t)ATH_AMPDU_LIMIT_DEFAULT);
1616
1617 /*
1618 * h/w can accept aggregates upto 16 bit lengths (65535).
1619 * The IE, however can hold upto 65536, which shows up here
1620 * as zero. Ignore 65536 since we are constrained by hw.
1621 */
1622 maxampdu = sc->sc_ht_info.maxampdu;
1623 if (maxampdu)
1624 aggr_limit = min(aggr_limit, maxampdu);
1625
1626 return aggr_limit;
1627 }
1628
1629 /*
1630 * returns the number of delimiters to be added to
1631 * meet the minimum required mpdudensity.
1632 * caller should make sure that the rate is HT rate .
1633 */
1634
1635 static int ath_compute_num_delims(struct ath_softc *sc,
1636 struct ath_buf *bf,
1637 u_int16_t frmlen)
1638 {
1639 const struct hal_rate_table *rt = sc->sc_currates;
1640 u_int32_t nsymbits, nsymbols, mpdudensity;
1641 u_int16_t minlen;
1642 u_int8_t rc, flags, rix;
1643 int width, half_gi, ndelim, mindelim;
1644
1645 /* Select standard number of delimiters based on frame length alone */
1646 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
1647
1648 /*
1649 * If encryption enabled, hardware requires some more padding between
1650 * subframes.
1651 * TODO - this could be improved to be dependent on the rate.
1652 * The hardware can keep up at lower rates, but not higher rates
1653 */
1654 if (bf->bf_keytype != HAL_KEY_TYPE_CLEAR)
1655 ndelim += ATH_AGGR_ENCRYPTDELIM;
1656
1657 /*
1658 * Convert desired mpdu density from microeconds to bytes based
1659 * on highest rate in rate series (i.e. first rate) to determine
1660 * required minimum length for subframe. Take into account
1661 * whether high rate is 20 or 40Mhz and half or full GI.
1662 */
1663 mpdudensity = sc->sc_ht_info.mpdudensity;
1664
1665 /*
1666 * If there is no mpdu density restriction, no further calculation
1667 * is needed.
1668 */
1669 if (mpdudensity == 0)
1670 return ndelim;
1671
1672 rix = bf->bf_rcs[0].rix;
1673 flags = bf->bf_rcs[0].flags;
1674 rc = rt->info[rix].rateCode;
1675 width = (flags & ATH_RC_CW40_FLAG) ? 1 : 0;
1676 half_gi = (flags & ATH_RC_SGI_FLAG) ? 1 : 0;
1677
1678 if (half_gi)
1679 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
1680 else
1681 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
1682
1683 if (nsymbols == 0)
1684 nsymbols = 1;
1685
1686 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1687 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
1688
1689 /* Is frame shorter than required minimum length? */
1690 if (frmlen < minlen) {
1691 /* Get the minimum number of delimiters required. */
1692 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
1693 ndelim = max(mindelim, ndelim);
1694 }
1695
1696 return ndelim;
1697 }
1698
1699 /*
1700 * For aggregation from software buffer queue.
1701 * NB: must be called with txq lock held
1702 */
1703
1704 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1705 struct ath_atx_tid *tid,
1706 struct list_head *bf_q,
1707 struct ath_buf **bf_last,
1708 struct aggr_rifs_param *param,
1709 int *prev_frames)
1710 {
1711 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1712 struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
1713 struct list_head bf_head;
1714 int rl = 0, nframes = 0, ndelim;
1715 u_int16_t aggr_limit = 0, al = 0, bpad = 0,
1716 al_delta, h_baw = tid->baw_size / 2;
1717 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
1718 int prev_al = 0, is_ds_rate = 0;
1719 INIT_LIST_HEAD(&bf_head);
1720
1721 BUG_ON(list_empty(&tid->buf_q));
1722
1723 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
1724
1725 do {
1726 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1727
1728 /*
1729 * do not step over block-ack window
1730 */
1731 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
1732 status = ATH_AGGR_BAW_CLOSED;
1733 break;
1734 }
1735
1736 if (!rl) {
1737 aggr_limit = ath_lookup_rate(sc, bf);
1738 rl = 1;
1739 /*
1740 * Is rate dual stream
1741 */
1742 is_ds_rate =
1743 (bf->bf_rcs[0].flags & ATH_RC_DS_FLAG) ? 1 : 0;
1744 }
1745
1746 /*
1747 * do not exceed aggregation limit
1748 */
1749 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
1750
1751 if (nframes && (aggr_limit <
1752 (al + bpad + al_delta + prev_al))) {
1753 status = ATH_AGGR_LIMITED;
1754 break;
1755 }
1756
1757 /*
1758 * do not exceed subframe limit
1759 */
1760 if ((nframes + *prev_frames) >=
1761 min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
1762 status = ATH_AGGR_LIMITED;
1763 break;
1764 }
1765
1766 /*
1767 * add padding for previous frame to aggregation length
1768 */
1769 al += bpad + al_delta;
1770
1771 /*
1772 * Get the delimiters needed to meet the MPDU
1773 * density for this node.
1774 */
1775 ndelim = ath_compute_num_delims(sc, bf_first, bf->bf_frmlen);
1776
1777 bpad = PADBYTES(al_delta) + (ndelim << 2);
1778
1779 bf->bf_next = NULL;
1780 bf->bf_lastfrm->bf_desc->ds_link = 0;
1781
1782 /*
1783 * this packet is part of an aggregate
1784 * - remove all descriptors belonging to this frame from
1785 * software queue
1786 * - add it to block ack window
1787 * - set up descriptors for aggregation
1788 */
1789 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1790 ath_tx_addto_baw(sc, tid, bf);
1791
1792 list_for_each_entry(tbf, &bf_head, list) {
1793 ath9k_hw_set11n_aggr_middle(sc->sc_ah,
1794 tbf->bf_desc, ndelim);
1795 }
1796
1797 /*
1798 * link buffers of this frame to the aggregate
1799 */
1800 list_splice_tail_init(&bf_head, bf_q);
1801 nframes++;
1802
1803 if (bf_prev) {
1804 bf_prev->bf_next = bf;
1805 bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr;
1806 }
1807 bf_prev = bf;
1808
1809 #ifdef AGGR_NOSHORT
1810 /*
1811 * terminate aggregation on a small packet boundary
1812 */
1813 if (bf->bf_frmlen < ATH_AGGR_MINPLEN) {
1814 status = ATH_AGGR_SHORTPKT;
1815 break;
1816 }
1817 #endif
1818 } while (!list_empty(&tid->buf_q));
1819
1820 bf_first->bf_al = al;
1821 bf_first->bf_nframes = nframes;
1822 *bf_last = bf_prev;
1823 return status;
1824 #undef PADBYTES
1825 }
1826
1827 /*
1828 * process pending frames possibly doing a-mpdu aggregation
1829 * NB: must be called with txq lock held
1830 */
1831
1832 static void ath_tx_sched_aggr(struct ath_softc *sc,
1833 struct ath_txq *txq, struct ath_atx_tid *tid)
1834 {
1835 struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL;
1836 enum ATH_AGGR_STATUS status;
1837 struct list_head bf_q;
1838 struct aggr_rifs_param param = {0, 0, 0, 0, NULL};
1839 int prev_frames = 0;
1840
1841 do {
1842 if (list_empty(&tid->buf_q))
1843 return;
1844
1845 INIT_LIST_HEAD(&bf_q);
1846
1847 status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, &param,
1848 &prev_frames);
1849
1850 /*
1851 * no frames picked up to be aggregated; block-ack
1852 * window is not open
1853 */
1854 if (list_empty(&bf_q))
1855 break;
1856
1857 bf = list_first_entry(&bf_q, struct ath_buf, list);
1858 bf_last = list_entry(bf_q.prev, struct ath_buf, list);
1859 bf->bf_lastbf = bf_last;
1860
1861 /*
1862 * if only one frame, send as non-aggregate
1863 */
1864 if (bf->bf_nframes == 1) {
1865 ASSERT(bf->bf_lastfrm == bf_last);
1866
1867 bf->bf_isaggr = 0;
1868 /*
1869 * clear aggr bits for every descriptor
1870 * XXX TODO: is there a way to optimize it?
1871 */
1872 list_for_each_entry(tbf, &bf_q, list) {
1873 ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc);
1874 }
1875
1876 ath_buf_set_rate(sc, bf);
1877 ath_tx_txqaddbuf(sc, txq, &bf_q);
1878 continue;
1879 }
1880
1881 /*
1882 * setup first desc with rate and aggr info
1883 */
1884 bf->bf_isaggr = 1;
1885 ath_buf_set_rate(sc, bf);
1886 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
1887
1888 /*
1889 * anchor last frame of aggregate correctly
1890 */
1891 ASSERT(bf_lastaggr);
1892 ASSERT(bf_lastaggr->bf_lastfrm == bf_last);
1893 tbf = bf_lastaggr;
1894 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1895
1896 /* XXX: We don't enter into this loop, consider removing this */
1897 while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) {
1898 tbf = list_entry(tbf->list.next, struct ath_buf, list);
1899 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1900 }
1901
1902 txq->axq_aggr_depth++;
1903
1904 /*
1905 * Normal aggregate, queue to hardware
1906 */
1907 ath_tx_txqaddbuf(sc, txq, &bf_q);
1908
1909 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1910 status != ATH_AGGR_BAW_CLOSED);
1911 }
1912
1913 /* Called with txq lock held */
1914
1915 static void ath_tid_drain(struct ath_softc *sc,
1916 struct ath_txq *txq,
1917 struct ath_atx_tid *tid,
1918 bool bh_flag)
1919 {
1920 struct ath_buf *bf;
1921 struct list_head bf_head;
1922 INIT_LIST_HEAD(&bf_head);
1923
1924 for (;;) {
1925 if (list_empty(&tid->buf_q))
1926 break;
1927 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1928
1929 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1930
1931 /* update baw for software retried frame */
1932 if (bf->bf_isretried)
1933 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1934
1935 /*
1936 * do not indicate packets while holding txq spinlock.
1937 * unlock is intentional here
1938 */
1939 if (likely(bh_flag))
1940 spin_unlock_bh(&txq->axq_lock);
1941 else
1942 spin_unlock(&txq->axq_lock);
1943
1944 /* complete this sub-frame */
1945 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1946
1947 if (likely(bh_flag))
1948 spin_lock_bh(&txq->axq_lock);
1949 else
1950 spin_lock(&txq->axq_lock);
1951 }
1952
1953 /*
1954 * TODO: For frame(s) that are in the retry state, we will reuse the
1955 * sequence number(s) without setting the retry bit. The
1956 * alternative is to give up on these and BAR the receiver's window
1957 * forward.
1958 */
1959 tid->seq_next = tid->seq_start;
1960 tid->baw_tail = tid->baw_head;
1961 }
1962
1963 /*
1964 * Drain all pending buffers
1965 * NB: must be called with txq lock held
1966 */
1967
1968 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1969 struct ath_txq *txq,
1970 bool bh_flag)
1971 {
1972 struct ath_atx_ac *ac, *ac_tmp;
1973 struct ath_atx_tid *tid, *tid_tmp;
1974
1975 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1976 list_del(&ac->list);
1977 ac->sched = AH_FALSE;
1978 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1979 list_del(&tid->list);
1980 tid->sched = AH_FALSE;
1981 ath_tid_drain(sc, txq, tid, bh_flag);
1982 }
1983 }
1984 }
1985
1986 static int ath_tx_start_dma(struct ath_softc *sc,
1987 struct sk_buff *skb,
1988 struct scatterlist *sg,
1989 u_int32_t n_sg,
1990 struct ath_tx_control *txctl)
1991 {
1992 struct ath_node *an = txctl->an;
1993 struct ath_buf *bf = NULL;
1994 struct list_head bf_head;
1995 struct ath_desc *ds;
1996 struct ath_hal *ah = sc->sc_ah;
1997 struct ath_txq *txq = &sc->sc_txq[txctl->qnum];
1998 struct ath_tx_info_priv *tx_info_priv;
1999 struct ath_rc_series *rcs;
2000 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2001 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2002 __le16 fc = hdr->frame_control;
2003
2004 /* For each sglist entry, allocate an ath_buf for DMA */
2005 INIT_LIST_HEAD(&bf_head);
2006 spin_lock_bh(&sc->sc_txbuflock);
2007 if (unlikely(list_empty(&sc->sc_txbuf))) {
2008 spin_unlock_bh(&sc->sc_txbuflock);
2009 return -ENOMEM;
2010 }
2011
2012 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
2013 list_del(&bf->list);
2014 spin_unlock_bh(&sc->sc_txbuflock);
2015
2016 list_add_tail(&bf->list, &bf_head);
2017
2018 /* set up this buffer */
2019 ATH_TXBUF_RESET(bf);
2020 bf->bf_frmlen = txctl->frmlen;
2021 bf->bf_isdata = ieee80211_is_data(fc);
2022 bf->bf_isbar = ieee80211_is_back_req(fc);
2023 bf->bf_ispspoll = ieee80211_is_pspoll(fc);
2024 bf->bf_flags = txctl->flags;
2025 bf->bf_shpreamble = sc->sc_flags & ATH_PREAMBLE_SHORT;
2026 bf->bf_keytype = txctl->keytype;
2027 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
2028 rcs = tx_info_priv->rcs;
2029 bf->bf_rcs[0] = rcs[0];
2030 bf->bf_rcs[1] = rcs[1];
2031 bf->bf_rcs[2] = rcs[2];
2032 bf->bf_rcs[3] = rcs[3];
2033 bf->bf_node = an;
2034 bf->bf_mpdu = skb;
2035 bf->bf_buf_addr = sg_dma_address(sg);
2036
2037 /* setup descriptor */
2038 ds = bf->bf_desc;
2039 ds->ds_link = 0;
2040 ds->ds_data = bf->bf_buf_addr;
2041
2042 /*
2043 * Save the DMA context in the first ath_buf
2044 */
2045 copy_dma_mem_context(get_dma_mem_context(bf, bf_dmacontext),
2046 get_dma_mem_context(txctl, dmacontext));
2047
2048 /*
2049 * Formulate first tx descriptor with tx controls.
2050 */
2051 ath9k_hw_set11n_txdesc(ah,
2052 ds,
2053 bf->bf_frmlen, /* frame length */
2054 txctl->atype, /* Atheros packet type */
2055 min(txctl->txpower, (u_int16_t)60), /* txpower */
2056 txctl->keyix, /* key cache index */
2057 txctl->keytype, /* key type */
2058 txctl->flags); /* flags */
2059 ath9k_hw_filltxdesc(ah,
2060 ds,
2061 sg_dma_len(sg), /* segment length */
2062 AH_TRUE, /* first segment */
2063 (n_sg == 1) ? AH_TRUE : AH_FALSE, /* last segment */
2064 ds); /* first descriptor */
2065 ath_desc_swap(ds);
2066
2067 bf->bf_lastfrm = bf;
2068 bf->bf_ht = txctl->ht;
2069
2070 spin_lock_bh(&txq->axq_lock);
2071
2072 if (txctl->ht && sc->sc_txaggr) {
2073 struct ath_atx_tid *tid = ATH_AN_2_TID(an, txctl->tidno);
2074 if (ath_aggr_query(sc, an, txctl->tidno)) {
2075 /*
2076 * Try aggregation if it's a unicast data frame
2077 * and the destination is HT capable.
2078 */
2079 ath_tx_send_ampdu(sc, txq, tid, &bf_head, txctl);
2080 } else {
2081 /*
2082 * Send this frame as regular when ADDBA exchange
2083 * is neither complete nor pending.
2084 */
2085 ath_tx_send_normal(sc, txq, tid, &bf_head);
2086 }
2087 } else {
2088 bf->bf_lastbf = bf;
2089 bf->bf_nframes = 1;
2090 ath_buf_set_rate(sc, bf);
2091
2092 if (ieee80211_is_back_req(fc)) {
2093 /* This is required for resuming tid
2094 * during BAR completion */
2095 bf->bf_tidno = txctl->tidno;
2096 }
2097
2098 if (is_multicast_ether_addr(hdr->addr1)) {
2099 struct ath_vap *avp = sc->sc_vaps[txctl->if_id];
2100
2101 /*
2102 * When servicing one or more stations in power-save
2103 * mode (or) if there is some mcast data waiting on
2104 * mcast queue (to prevent out of order delivery of
2105 * mcast,bcast packets) multicast frames must be
2106 * buffered until after the beacon. We use the private
2107 * mcast queue for that.
2108 */
2109 /* XXX? more bit in 802.11 frame header */
2110 spin_lock_bh(&avp->av_mcastq.axq_lock);
2111 if (txctl->ps || avp->av_mcastq.axq_depth)
2112 ath_tx_mcastqaddbuf(sc,
2113 &avp->av_mcastq, &bf_head);
2114 else
2115 ath_tx_txqaddbuf(sc, txq, &bf_head);
2116 spin_unlock_bh(&avp->av_mcastq.axq_lock);
2117 } else
2118 ath_tx_txqaddbuf(sc, txq, &bf_head);
2119 }
2120 spin_unlock_bh(&txq->axq_lock);
2121 return 0;
2122 }
2123
2124 static void xmit_map_sg(struct ath_softc *sc,
2125 struct sk_buff *skb,
2126 dma_addr_t *pa,
2127 struct ath_tx_control *txctl)
2128 {
2129 struct ath_xmit_status tx_status;
2130 struct ath_atx_tid *tid;
2131 struct scatterlist sg;
2132
2133 *pa = pci_map_single(sc->pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
2134
2135 /* setup S/G list */
2136 memset(&sg, 0, sizeof(struct scatterlist));
2137 sg_dma_address(&sg) = *pa;
2138 sg_dma_len(&sg) = skb->len;
2139
2140 if (ath_tx_start_dma(sc, skb, &sg, 1, txctl) != 0) {
2141 /*
2142 * We have to do drop frame here.
2143 */
2144 pci_unmap_single(sc->pdev, *pa, skb->len, PCI_DMA_TODEVICE);
2145
2146 tx_status.retries = 0;
2147 tx_status.flags = ATH_TX_ERROR;
2148
2149 if (txctl->ht && sc->sc_txaggr) {
2150 /* Reclaim the seqno. */
2151 tid = ATH_AN_2_TID((struct ath_node *)
2152 txctl->an, txctl->tidno);
2153 DECR(tid->seq_next, IEEE80211_SEQ_MAX);
2154 }
2155 ath_tx_complete(sc, skb, &tx_status, txctl->an);
2156 }
2157 }
2158
2159 /* Initialize TX queue and h/w */
2160
2161 int ath_tx_init(struct ath_softc *sc, int nbufs)
2162 {
2163 int error = 0;
2164
2165 do {
2166 spin_lock_init(&sc->sc_txbuflock);
2167
2168 /* Setup tx descriptors */
2169 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2170 "tx", nbufs * ATH_FRAG_PER_MSDU, ATH_TXDESC);
2171 if (error != 0) {
2172 DPRINTF(sc, ATH_DEBUG_FATAL,
2173 "%s: failed to allocate tx descriptors: %d\n",
2174 __func__, error);
2175 break;
2176 }
2177
2178 /* XXX allocate beacon state together with vap */
2179 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2180 "beacon", ATH_BCBUF, 1);
2181 if (error != 0) {
2182 DPRINTF(sc, ATH_DEBUG_FATAL,
2183 "%s: failed to allocate "
2184 "beacon descripotrs: %d\n",
2185 __func__, error);
2186 break;
2187 }
2188
2189 } while (0);
2190
2191 if (error != 0)
2192 ath_tx_cleanup(sc);
2193
2194 return error;
2195 }
2196
2197 /* Reclaim all tx queue resources */
2198
2199 int ath_tx_cleanup(struct ath_softc *sc)
2200 {
2201 /* cleanup beacon descriptors */
2202 if (sc->sc_bdma.dd_desc_len != 0)
2203 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2204
2205 /* cleanup tx descriptors */
2206 if (sc->sc_txdma.dd_desc_len != 0)
2207 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2208
2209 return 0;
2210 }
2211
2212 /* Setup a h/w transmit queue */
2213
2214 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2215 {
2216 struct ath_hal *ah = sc->sc_ah;
2217 struct hal_txq_info qi;
2218 int qnum;
2219
2220 memzero(&qi, sizeof(qi));
2221 qi.tqi_subtype = subtype;
2222 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2223 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2224 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2225 qi.tqi_compBuf = 0;
2226
2227 /*
2228 * Enable interrupts only for EOL and DESC conditions.
2229 * We mark tx descriptors to receive a DESC interrupt
2230 * when a tx queue gets deep; otherwise waiting for the
2231 * EOL to reap descriptors. Note that this is done to
2232 * reduce interrupt load and this only defers reaping
2233 * descriptors, never transmitting frames. Aside from
2234 * reducing interrupts this also permits more concurrency.
2235 * The only potential downside is if the tx queue backs
2236 * up in which case the top half of the kernel may backup
2237 * due to a lack of tx descriptors.
2238 *
2239 * The UAPSD queue is an exception, since we take a desc-
2240 * based intr on the EOSP frames.
2241 */
2242 if (qtype == HAL_TX_QUEUE_UAPSD)
2243 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
2244 else
2245 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
2246 TXQ_FLAG_TXDESCINT_ENABLE;
2247 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
2248 if (qnum == -1) {
2249 /*
2250 * NB: don't print a message, this happens
2251 * normally on parts with too few tx queues
2252 */
2253 return NULL;
2254 }
2255 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
2256 DPRINTF(sc, ATH_DEBUG_FATAL,
2257 "%s: hal qnum %u out of range, max %u!\n",
2258 __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
2259 ath9k_hw_releasetxqueue(ah, qnum);
2260 return NULL;
2261 }
2262 if (!ATH_TXQ_SETUP(sc, qnum)) {
2263 struct ath_txq *txq = &sc->sc_txq[qnum];
2264
2265 txq->axq_qnum = qnum;
2266 txq->axq_link = NULL;
2267 INIT_LIST_HEAD(&txq->axq_q);
2268 INIT_LIST_HEAD(&txq->axq_acq);
2269 spin_lock_init(&txq->axq_lock);
2270 txq->axq_depth = 0;
2271 txq->axq_aggr_depth = 0;
2272 txq->axq_totalqueued = 0;
2273 txq->axq_intrcnt = 0;
2274 txq->axq_linkbuf = NULL;
2275 sc->sc_txqsetup |= 1<<qnum;
2276 }
2277 return &sc->sc_txq[qnum];
2278 }
2279
2280 /* Reclaim resources for a setup queue */
2281
2282 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
2283 {
2284 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
2285 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
2286 }
2287
2288 /*
2289 * Setup a hardware data transmit queue for the specified
2290 * access control. The hal may not support all requested
2291 * queues in which case it will return a reference to a
2292 * previously setup queue. We record the mapping from ac's
2293 * to h/w queues for use by ath_tx_start and also track
2294 * the set of h/w queues being used to optimize work in the
2295 * transmit interrupt handler and related routines.
2296 */
2297
2298 int ath_tx_setup(struct ath_softc *sc, int haltype)
2299 {
2300 struct ath_txq *txq;
2301
2302 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2303 DPRINTF(sc, ATH_DEBUG_FATAL,
2304 "%s: HAL AC %u out of range, max %zu!\n",
2305 __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
2306 return 0;
2307 }
2308 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
2309 if (txq != NULL) {
2310 sc->sc_haltype2q[haltype] = txq->axq_qnum;
2311 return 1;
2312 } else
2313 return 0;
2314 }
2315
2316 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
2317 {
2318 int qnum;
2319
2320 switch (qtype) {
2321 case HAL_TX_QUEUE_DATA:
2322 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2323 DPRINTF(sc, ATH_DEBUG_FATAL,
2324 "%s: HAL AC %u out of range, max %zu!\n",
2325 __func__,
2326 haltype, ARRAY_SIZE(sc->sc_haltype2q));
2327 return -1;
2328 }
2329 qnum = sc->sc_haltype2q[haltype];
2330 break;
2331 case HAL_TX_QUEUE_BEACON:
2332 qnum = sc->sc_bhalq;
2333 break;
2334 case HAL_TX_QUEUE_CAB:
2335 qnum = sc->sc_cabq->axq_qnum;
2336 break;
2337 default:
2338 qnum = -1;
2339 }
2340 return qnum;
2341 }
2342
2343 /* Update parameters for a transmit queue */
2344
2345 int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *qi0)
2346 {
2347 struct ath_hal *ah = sc->sc_ah;
2348 int error = 0;
2349 struct hal_txq_info qi;
2350
2351 if (qnum == sc->sc_bhalq) {
2352 /*
2353 * XXX: for beacon queue, we just save the parameter.
2354 * It will be picked up by ath_beaconq_config when
2355 * it's necessary.
2356 */
2357 sc->sc_beacon_qi = *qi0;
2358 return 0;
2359 }
2360
2361 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum);
2362
2363 ath9k_hw_gettxqueueprops(ah, qnum, &qi);
2364 qi.tqi_aifs = qi0->tqi_aifs;
2365 qi.tqi_cwmin = qi0->tqi_cwmin;
2366 qi.tqi_cwmax = qi0->tqi_cwmax;
2367 qi.tqi_burstTime = qi0->tqi_burstTime;
2368 qi.tqi_readyTime = qi0->tqi_readyTime;
2369
2370 if (!ath9k_hw_settxqueueprops(ah, qnum, &qi)) {
2371 DPRINTF(sc, ATH_DEBUG_FATAL,
2372 "%s: unable to update hardware queue %u!\n",
2373 __func__, qnum);
2374 error = -EIO;
2375 } else {
2376 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
2377 }
2378
2379 return error;
2380 }
2381
2382 int ath_cabq_update(struct ath_softc *sc)
2383 {
2384 struct hal_txq_info qi;
2385 int qnum = sc->sc_cabq->axq_qnum;
2386 struct ath_beacon_config conf;
2387
2388 ath9k_hw_gettxqueueprops(sc->sc_ah, qnum, &qi);
2389 /*
2390 * Ensure the readytime % is within the bounds.
2391 */
2392 if (sc->sc_config.cabqReadytime < HAL_READY_TIME_LO_BOUND)
2393 sc->sc_config.cabqReadytime = HAL_READY_TIME_LO_BOUND;
2394 else if (sc->sc_config.cabqReadytime > HAL_READY_TIME_HI_BOUND)
2395 sc->sc_config.cabqReadytime = HAL_READY_TIME_HI_BOUND;
2396
2397 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
2398 qi.tqi_readyTime =
2399 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
2400 ath_txq_update(sc, qnum, &qi);
2401
2402 return 0;
2403 }
2404
2405 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb)
2406 {
2407 struct ath_tx_control txctl;
2408 int error = 0;
2409
2410 error = ath_tx_prepare(sc, skb, &txctl);
2411 if (error == 0)
2412 /*
2413 * Start DMA mapping.
2414 * ath_tx_start_dma() will be called either synchronously
2415 * or asynchrounsly once DMA is complete.
2416 */
2417 xmit_map_sg(sc, skb,
2418 get_dma_mem_context(&txctl, dmacontext),
2419 &txctl);
2420 else
2421 ath_node_put(sc, txctl.an, ATH9K_BH_STATUS_CHANGE);
2422
2423 /* failed packets will be dropped by the caller */
2424 return error;
2425 }
2426
2427 /* Deferred processing of transmit interrupt */
2428
2429 void ath_tx_tasklet(struct ath_softc *sc)
2430 {
2431 u_int64_t tsf = ath9k_hw_gettsf64(sc->sc_ah);
2432 int i, nacked = 0;
2433 u_int32_t qcumask = ((1 << HAL_NUM_TX_QUEUES) - 1);
2434
2435 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2436
2437 /*
2438 * Process each active queue.
2439 */
2440 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
2441 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2442 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
2443 }
2444 if (nacked)
2445 sc->sc_lastrx = tsf;
2446 }
2447
2448 void ath_tx_draintxq(struct ath_softc *sc,
2449 struct ath_txq *txq, enum hal_bool retry_tx)
2450 {
2451 struct ath_buf *bf, *lastbf;
2452 struct list_head bf_head;
2453
2454 INIT_LIST_HEAD(&bf_head);
2455
2456 /*
2457 * NB: this assumes output has been stopped and
2458 * we do not need to block ath_tx_tasklet
2459 */
2460 for (;;) {
2461 spin_lock_bh(&txq->axq_lock);
2462
2463 if (list_empty(&txq->axq_q)) {
2464 txq->axq_link = NULL;
2465 txq->axq_linkbuf = NULL;
2466 spin_unlock_bh(&txq->axq_lock);
2467 break;
2468 }
2469
2470 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2471
2472 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
2473 list_del(&bf->list);
2474 spin_unlock_bh(&txq->axq_lock);
2475
2476 spin_lock_bh(&sc->sc_txbuflock);
2477 list_add_tail(&bf->list, &sc->sc_txbuf);
2478 spin_unlock_bh(&sc->sc_txbuflock);
2479 continue;
2480 }
2481
2482 lastbf = bf->bf_lastbf;
2483 if (!retry_tx)
2484 lastbf->bf_desc->ds_txstat.ts_flags = HAL_TX_SW_ABORTED;
2485
2486 /* remove ath_buf's of the same mpdu from txq */
2487 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
2488 txq->axq_depth--;
2489
2490 spin_unlock_bh(&txq->axq_lock);
2491
2492 if (bf->bf_isampdu)
2493 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0);
2494 else
2495 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2496 }
2497
2498 /* flush any pending frames if aggregation is enabled */
2499 if (sc->sc_txaggr) {
2500 if (!retry_tx) {
2501 spin_lock_bh(&txq->axq_lock);
2502 ath_txq_drain_pending_buffers(sc, txq,
2503 ATH9K_BH_STATUS_CHANGE);
2504 spin_unlock_bh(&txq->axq_lock);
2505 }
2506 }
2507 }
2508
2509 /* Drain the transmit queues and reclaim resources */
2510
2511 void ath_draintxq(struct ath_softc *sc, enum hal_bool retry_tx)
2512 {
2513 /* stop beacon queue. The beacon will be freed when
2514 * we go to INIT state */
2515 if (!sc->sc_invalid) {
2516 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2517 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: beacon queue %x\n", __func__,
2518 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2519 }
2520
2521 ath_drain_txdataq(sc, retry_tx);
2522 }
2523
2524 u_int32_t ath_txq_depth(struct ath_softc *sc, int qnum)
2525 {
2526 return sc->sc_txq[qnum].axq_depth;
2527 }
2528
2529 u_int32_t ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2530 {
2531 return sc->sc_txq[qnum].axq_aggr_depth;
2532 }
2533
2534 /* Check if an ADDBA is required. A valid node must be passed. */
2535 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
2536 struct ath_node *an,
2537 u8 tidno)
2538 {
2539 struct ath_atx_tid *txtid;
2540 DECLARE_MAC_BUF(mac);
2541
2542 if (!sc->sc_txaggr)
2543 return AGGR_NOT_REQUIRED;
2544
2545 /* ADDBA exchange must be completed before sending aggregates */
2546 txtid = ATH_AN_2_TID(an, tidno);
2547
2548 if (txtid->addba_exchangecomplete)
2549 return AGGR_EXCHANGE_DONE;
2550
2551 if (txtid->cleanup_inprogress)
2552 return AGGR_CLEANUP_PROGRESS;
2553
2554 if (txtid->addba_exchangeinprogress)
2555 return AGGR_EXCHANGE_PROGRESS;
2556
2557 if (!txtid->addba_exchangecomplete) {
2558 if (!txtid->addba_exchangeinprogress &&
2559 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
2560 txtid->addba_exchangeattempts++;
2561 return AGGR_REQUIRED;
2562 }
2563 }
2564
2565 return AGGR_NOT_REQUIRED;
2566 }
2567
2568 /* Start TX aggregation */
2569
2570 int ath_tx_aggr_start(struct ath_softc *sc,
2571 const u8 *addr,
2572 u16 tid,
2573 u16 *ssn)
2574 {
2575 struct ath_atx_tid *txtid;
2576 struct ath_node *an;
2577
2578 spin_lock_bh(&sc->node_lock);
2579 an = ath_node_find(sc, (u8 *) addr);
2580 spin_unlock_bh(&sc->node_lock);
2581
2582 if (!an) {
2583 DPRINTF(sc, ATH_DEBUG_AGGR,
2584 "%s: Node not found to initialize "
2585 "TX aggregation\n", __func__);
2586 return -1;
2587 }
2588
2589 if (sc->sc_txaggr) {
2590 txtid = ATH_AN_2_TID(an, tid);
2591 txtid->addba_exchangeinprogress = 1;
2592 ath_tx_pause_tid(sc, txtid);
2593 }
2594
2595 return 0;
2596 }
2597
2598 /* Stop tx aggregation */
2599
2600 int ath_tx_aggr_stop(struct ath_softc *sc,
2601 const u8 *addr,
2602 u16 tid)
2603 {
2604 struct ath_node *an;
2605
2606 spin_lock_bh(&sc->node_lock);
2607 an = ath_node_find(sc, (u8 *) addr);
2608 spin_unlock_bh(&sc->node_lock);
2609
2610 if (!an) {
2611 DPRINTF(sc, ATH_DEBUG_AGGR,
2612 "%s: TX aggr stop for non-existent node\n", __func__);
2613 return -1;
2614 }
2615
2616 ath_tx_aggr_teardown(sc, an, tid);
2617 return 0;
2618 }
2619
2620 /*
2621 * Performs transmit side cleanup when TID changes from aggregated to
2622 * unaggregated.
2623 * - Pause the TID and mark cleanup in progress
2624 * - Discard all retry frames from the s/w queue.
2625 */
2626
2627 void ath_tx_aggr_teardown(struct ath_softc *sc,
2628 struct ath_node *an, u_int8_t tid)
2629 {
2630 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2631 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
2632 struct ath_buf *bf;
2633 struct list_head bf_head;
2634 INIT_LIST_HEAD(&bf_head);
2635
2636 DPRINTF(sc, ATH_DEBUG_AGGR, "%s: teardown TX aggregation\n", __func__);
2637
2638 if (txtid->cleanup_inprogress) /* cleanup is in progress */
2639 return;
2640
2641 if (!txtid->addba_exchangecomplete) {
2642 txtid->addba_exchangeattempts = 0;
2643 return;
2644 }
2645
2646 /* TID must be paused first */
2647 ath_tx_pause_tid(sc, txtid);
2648
2649 /* drop all software retried frames and mark this TID */
2650 spin_lock_bh(&txq->axq_lock);
2651 while (!list_empty(&txtid->buf_q)) {
2652 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
2653 if (!bf->bf_isretried) {
2654 /*
2655 * NB: it's based on the assumption that
2656 * software retried frame will always stay
2657 * at the head of software queue.
2658 */
2659 break;
2660 }
2661 list_cut_position(&bf_head,
2662 &txtid->buf_q, &bf->bf_lastfrm->list);
2663 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
2664
2665 /* complete this sub-frame */
2666 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2667 }
2668
2669 if (txtid->baw_head != txtid->baw_tail) {
2670 spin_unlock_bh(&txq->axq_lock);
2671 txtid->cleanup_inprogress = AH_TRUE;
2672 } else {
2673 txtid->addba_exchangecomplete = 0;
2674 txtid->addba_exchangeattempts = 0;
2675 spin_unlock_bh(&txq->axq_lock);
2676 ath_tx_flush_tid(sc, txtid);
2677 }
2678 }
2679
2680 /*
2681 * Tx scheduling logic
2682 * NB: must be called with txq lock held
2683 */
2684
2685 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
2686 {
2687 struct ath_atx_ac *ac;
2688 struct ath_atx_tid *tid;
2689
2690 /* nothing to schedule */
2691 if (list_empty(&txq->axq_acq))
2692 return;
2693 /*
2694 * get the first node/ac pair on the queue
2695 */
2696 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
2697 list_del(&ac->list);
2698 ac->sched = AH_FALSE;
2699
2700 /*
2701 * process a single tid per destination
2702 */
2703 do {
2704 /* nothing to schedule */
2705 if (list_empty(&ac->tid_q))
2706 return;
2707
2708 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
2709 list_del(&tid->list);
2710 tid->sched = AH_FALSE;
2711
2712 if (tid->paused) /* check next tid to keep h/w busy */
2713 continue;
2714
2715 if (!(tid->an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) ||
2716 ((txq->axq_depth % 2) == 0)) {
2717 ath_tx_sched_aggr(sc, txq, tid);
2718 }
2719
2720 /*
2721 * add tid to round-robin queue if more frames
2722 * are pending for the tid
2723 */
2724 if (!list_empty(&tid->buf_q))
2725 ath_tx_queue_tid(txq, tid);
2726
2727 /* only schedule one TID at a time */
2728 break;
2729 } while (!list_empty(&ac->tid_q));
2730
2731 /*
2732 * schedule AC if more TIDs need processing
2733 */
2734 if (!list_empty(&ac->tid_q)) {
2735 /*
2736 * add dest ac to txq if not already added
2737 */
2738 if (ac->sched == AH_FALSE) {
2739 ac->sched = AH_TRUE;
2740 list_add_tail(&ac->list, &txq->axq_acq);
2741 }
2742 }
2743 }
2744
2745 /* Initialize per-node transmit state */
2746
2747 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2748 {
2749 if (sc->sc_txaggr) {
2750 struct ath_atx_tid *tid;
2751 struct ath_atx_ac *ac;
2752 int tidno, acno;
2753
2754 sc->sc_ht_info.maxampdu = ATH_AMPDU_LIMIT_DEFAULT;
2755
2756 /*
2757 * Init per tid tx state
2758 */
2759 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2760 tidno < WME_NUM_TID;
2761 tidno++, tid++) {
2762 tid->an = an;
2763 tid->tidno = tidno;
2764 tid->seq_start = tid->seq_next = 0;
2765 tid->baw_size = WME_MAX_BA;
2766 tid->baw_head = tid->baw_tail = 0;
2767 tid->sched = AH_FALSE;
2768 tid->paused = AH_FALSE;
2769 tid->cleanup_inprogress = AH_FALSE;
2770 INIT_LIST_HEAD(&tid->buf_q);
2771
2772 acno = TID_TO_WME_AC(tidno);
2773 tid->ac = &an->an_aggr.tx.ac[acno];
2774
2775 /* ADDBA state */
2776 tid->addba_exchangecomplete = 0;
2777 tid->addba_exchangeinprogress = 0;
2778 tid->addba_exchangeattempts = 0;
2779 }
2780
2781 /*
2782 * Init per ac tx state
2783 */
2784 for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
2785 acno < WME_NUM_AC; acno++, ac++) {
2786 ac->sched = AH_FALSE;
2787 INIT_LIST_HEAD(&ac->tid_q);
2788
2789 switch (acno) {
2790 case WME_AC_BE:
2791 ac->qnum = ath_tx_get_qnum(sc,
2792 HAL_TX_QUEUE_DATA, HAL_WME_AC_BE);
2793 break;
2794 case WME_AC_BK:
2795 ac->qnum = ath_tx_get_qnum(sc,
2796 HAL_TX_QUEUE_DATA, HAL_WME_AC_BK);
2797 break;
2798 case WME_AC_VI:
2799 ac->qnum = ath_tx_get_qnum(sc,
2800 HAL_TX_QUEUE_DATA, HAL_WME_AC_VI);
2801 break;
2802 case WME_AC_VO:
2803 ac->qnum = ath_tx_get_qnum(sc,
2804 HAL_TX_QUEUE_DATA, HAL_WME_AC_VO);
2805 break;
2806 }
2807 }
2808 }
2809 }
2810
2811 /* Cleanupthe pending buffers for the node. */
2812
2813 void ath_tx_node_cleanup(struct ath_softc *sc,
2814 struct ath_node *an, bool bh_flag)
2815 {
2816 int i;
2817 struct ath_atx_ac *ac, *ac_tmp;
2818 struct ath_atx_tid *tid, *tid_tmp;
2819 struct ath_txq *txq;
2820 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
2821 if (ATH_TXQ_SETUP(sc, i)) {
2822 txq = &sc->sc_txq[i];
2823
2824 if (likely(bh_flag))
2825 spin_lock_bh(&txq->axq_lock);
2826 else
2827 spin_lock(&txq->axq_lock);
2828
2829 list_for_each_entry_safe(ac,
2830 ac_tmp, &txq->axq_acq, list) {
2831 tid = list_first_entry(&ac->tid_q,
2832 struct ath_atx_tid, list);
2833 if (tid && tid->an != an)
2834 continue;
2835 list_del(&ac->list);
2836 ac->sched = AH_FALSE;
2837
2838 list_for_each_entry_safe