Upgrade b43 and mac80211.
[openwrt/svn-archive/archive.git] / package / b43 / src / b43.h
1 #ifndef B43_H_
2 #define B43_H_
3
4 #include <linux/kernel.h>
5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/hw_random.h>
8 #include <linux/ssb/ssb.h>
9 #include <net/mac80211.h>
10
11 #include "debugfs.h"
12 #include "leds.h"
13 #include "rfkill.h"
14 #include "lo.h"
15 #include "phy.h"
16
17 #ifdef CONFIG_B43_DEBUG
18 # define B43_DEBUG 1
19 #else
20 # define B43_DEBUG 0
21 #endif
22
23 #define B43_RX_MAX_SSI 60
24
25 /* MMIO offsets */
26 #define B43_MMIO_DMA0_REASON 0x20
27 #define B43_MMIO_DMA0_IRQ_MASK 0x24
28 #define B43_MMIO_DMA1_REASON 0x28
29 #define B43_MMIO_DMA1_IRQ_MASK 0x2C
30 #define B43_MMIO_DMA2_REASON 0x30
31 #define B43_MMIO_DMA2_IRQ_MASK 0x34
32 #define B43_MMIO_DMA3_REASON 0x38
33 #define B43_MMIO_DMA3_IRQ_MASK 0x3C
34 #define B43_MMIO_DMA4_REASON 0x40
35 #define B43_MMIO_DMA4_IRQ_MASK 0x44
36 #define B43_MMIO_DMA5_REASON 0x48
37 #define B43_MMIO_DMA5_IRQ_MASK 0x4C
38 #define B43_MMIO_MACCTL 0x120 /* MAC control */
39 #define B43_MMIO_MACCMD 0x124 /* MAC command */
40 #define B43_MMIO_GEN_IRQ_REASON 0x128
41 #define B43_MMIO_GEN_IRQ_MASK 0x12C
42 #define B43_MMIO_RAM_CONTROL 0x130
43 #define B43_MMIO_RAM_DATA 0x134
44 #define B43_MMIO_PS_STATUS 0x140
45 #define B43_MMIO_RADIO_HWENABLED_HI 0x158
46 #define B43_MMIO_SHM_CONTROL 0x160
47 #define B43_MMIO_SHM_DATA 0x164
48 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166
49 #define B43_MMIO_XMITSTAT_0 0x170
50 #define B43_MMIO_XMITSTAT_1 0x174
51 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
52 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
53 #define B43_MMIO_TSF_CFP_REP 0x188
54 #define B43_MMIO_TSF_CFP_START 0x18C
55 #define B43_MMIO_TSF_CFP_MAXDUR 0x190
56
57 /* 32-bit DMA */
58 #define B43_MMIO_DMA32_BASE0 0x200
59 #define B43_MMIO_DMA32_BASE1 0x220
60 #define B43_MMIO_DMA32_BASE2 0x240
61 #define B43_MMIO_DMA32_BASE3 0x260
62 #define B43_MMIO_DMA32_BASE4 0x280
63 #define B43_MMIO_DMA32_BASE5 0x2A0
64 /* 64-bit DMA */
65 #define B43_MMIO_DMA64_BASE0 0x200
66 #define B43_MMIO_DMA64_BASE1 0x240
67 #define B43_MMIO_DMA64_BASE2 0x280
68 #define B43_MMIO_DMA64_BASE3 0x2C0
69 #define B43_MMIO_DMA64_BASE4 0x300
70 #define B43_MMIO_DMA64_BASE5 0x340
71
72 #define B43_MMIO_PHY_VER 0x3E0
73 #define B43_MMIO_PHY_RADIO 0x3E2
74 #define B43_MMIO_PHY0 0x3E6
75 #define B43_MMIO_ANTENNA 0x3E8
76 #define B43_MMIO_CHANNEL 0x3F0
77 #define B43_MMIO_CHANNEL_EXT 0x3F4
78 #define B43_MMIO_RADIO_CONTROL 0x3F6
79 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8
80 #define B43_MMIO_RADIO_DATA_LOW 0x3FA
81 #define B43_MMIO_PHY_CONTROL 0x3FC
82 #define B43_MMIO_PHY_DATA 0x3FE
83 #define B43_MMIO_MACFILTER_CONTROL 0x420
84 #define B43_MMIO_MACFILTER_DATA 0x422
85 #define B43_MMIO_RCMTA_COUNT 0x43C
86 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A
87 #define B43_MMIO_GPIO_CONTROL 0x49C
88 #define B43_MMIO_GPIO_MASK 0x49E
89 #define B43_MMIO_TSF_CFP_START_LOW 0x604
90 #define B43_MMIO_TSF_CFP_START_HIGH 0x606
91 #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
92 #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
93 #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
94 #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
95 #define B43_MMIO_RNG 0x65A
96 #define B43_MMIO_POWERUP_DELAY 0x6A8
97
98 /* SPROM boardflags_lo values */
99 #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
100 #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
101 #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
102 #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
103 #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
104 #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
105 #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
106 #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */
107 #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */
108 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
109 #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */
110 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
111 #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */
112 #define B43_BFL_HGPA 0x2000 /* had high gain PA */
113 #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
114 #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
115
116 /* GPIO register offset, in both ChipCommon and PCI core. */
117 #define B43_GPIO_CONTROL 0x6c
118
119 /* SHM Routing */
120 enum {
121 B43_SHM_UCODE, /* Microcode memory */
122 B43_SHM_SHARED, /* Shared memory */
123 B43_SHM_SCRATCH, /* Scratch memory */
124 B43_SHM_HW, /* Internal hardware register */
125 B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
126 };
127 /* SHM Routing modifiers */
128 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
129 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
130 #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
131 B43_SHM_AUTOINC_W)
132
133 /* Misc SHM_SHARED offsets */
134 #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
135 #define B43_SHM_SH_PCTLWDPOS 0x0008
136 #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
137 #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
138 #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
139 #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
140 #define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
141 #define B43_SHM_SH_HOSTFHI 0x0060 /* Hostflags for ucode options (high) */
142 #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
143 #define B43_SHM_SH_RADAR 0x0066 /* Radar register */
144 #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
145 #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
146 #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
147 #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
148 #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
149 /* SHM_SHARED TX FIFO variables */
150 #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
151 #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
152 #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
153 #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
154 /* SHM_SHARED background noise */
155 #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
156 #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
157 #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
158 /* SHM_SHARED crypto engine */
159 #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
160 #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
161 #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */
162 #define B43_SHM_SH_TKIPTSCTTAK 0x0318
163 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
164 #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
165 /* SHM_SHARED WME variables */
166 #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
167 #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */
168 #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
169 /* SHM_SHARED powersave mode related */
170 #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */
171 #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
172 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
173 /* SHM_SHARED beacon/AP variables */
174 #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
175 #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
176 #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
177 #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
178 #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */
179 #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */
180 #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
181 #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
182 #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
183 #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */
184 /* SHM_SHARED ACK/CTS control */
185 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
186 /* SHM_SHARED probe response variables */
187 #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
188 #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
189 #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
190 #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
191 #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
192 /* SHM_SHARED rate tables */
193 #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
194 #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
195 #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
196 #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
197 /* SHM_SHARED microcode soft registers */
198 #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
199 #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
200 #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
201 #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */
202 #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
203 #define B43_SHM_SH_UCODESTAT_INVALID 0
204 #define B43_SHM_SH_UCODESTAT_INIT 1
205 #define B43_SHM_SH_UCODESTAT_ACTIVE 2
206 #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
207 #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
208 #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
209 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
210 #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
211
212 /* SHM_SCRATCH offsets */
213 #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
214 #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
215 #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */
216 #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
217 #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
218 #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
219 #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
220 #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
221 #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
222 #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
223
224 /* Hardware Radio Enable masks */
225 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
226 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
227
228 /* HostFlags. See b43_hf_read/write() */
229 #define B43_HF_ANTDIVHELP 0x00000001 /* ucode antenna div helper */
230 #define B43_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
231 #define B43_HF_RXPULLW 0x00000004 /* RX pullup workaround */
232 #define B43_HF_CCKBOOST 0x00000008 /* 4dB CCK power boost (exclusive with OFDM boost) */
233 #define B43_HF_BTCOEX 0x00000010 /* Bluetooth coexistance */
234 #define B43_HF_GDCW 0x00000020 /* G-PHY DV canceller filter bw workaround */
235 #define B43_HF_OFDMPABOOST 0x00000040 /* Enable PA gain boost for OFDM */
236 #define B43_HF_ACPR 0x00000080 /* Disable for Japan, channel 14 */
237 #define B43_HF_EDCF 0x00000100 /* on if WME and MAC suspended */
238 #define B43_HF_TSSIRPSMW 0x00000200 /* TSSI reset PSM ucode workaround */
239 #define B43_HF_DSCRQ 0x00000400 /* Disable slow clock request in ucode */
240 #define B43_HF_ACIW 0x00000800 /* ACI workaround: shift bits by 2 on PHY CRS */
241 #define B43_HF_2060W 0x00001000 /* 2060 radio workaround */
242 #define B43_HF_RADARW 0x00002000 /* Radar workaround */
243 #define B43_HF_USEDEFKEYS 0x00004000 /* Enable use of default keys */
244 #define B43_HF_BT4PRIOCOEX 0x00010000 /* Bluetooth 2-priority coexistance */
245 #define B43_HF_FWKUP 0x00020000 /* Fast wake-up ucode */
246 #define B43_HF_VCORECALC 0x00040000 /* Force VCO recalculation when powering up synthpu */
247 #define B43_HF_PCISCW 0x00080000 /* PCI slow clock workaround */
248 #define B43_HF_4318TSSI 0x00200000 /* 4318 TSSI */
249 #define B43_HF_FBCMCFIFO 0x00400000 /* Flush bcast/mcast FIFO immediately */
250 #define B43_HF_HWPCTL 0x00800000 /* Enable hardwarre power control */
251 #define B43_HF_BTCOEXALT 0x01000000 /* Bluetooth coexistance in alternate pins */
252 #define B43_HF_TXBTCHECK 0x02000000 /* Bluetooth check during transmission */
253 #define B43_HF_SKCFPUP 0x04000000 /* Skip CFP update */
254
255 /* MacFilter offsets. */
256 #define B43_MACFILTER_SELF 0x0000
257 #define B43_MACFILTER_BSSID 0x0003
258
259 /* PowerControl */
260 #define B43_PCTL_IN 0xB0
261 #define B43_PCTL_OUT 0xB4
262 #define B43_PCTL_OUTENABLE 0xB8
263 #define B43_PCTL_XTAL_POWERUP 0x40
264 #define B43_PCTL_PLL_POWERDOWN 0x80
265
266 /* PowerControl Clock Modes */
267 #define B43_PCTL_CLK_FAST 0x00
268 #define B43_PCTL_CLK_SLOW 0x01
269 #define B43_PCTL_CLK_DYNAMIC 0x02
270
271 #define B43_PCTL_FORCE_SLOW 0x0800
272 #define B43_PCTL_FORCE_PLL 0x1000
273 #define B43_PCTL_DYN_XTAL 0x2000
274
275 /* PHYVersioning */
276 #define B43_PHYTYPE_A 0x00
277 #define B43_PHYTYPE_B 0x01
278 #define B43_PHYTYPE_G 0x02
279 #define B43_PHYTYPE_N 0x04
280 #define B43_PHYTYPE_LP 0x05
281
282 /* PHYRegisters */
283 #define B43_PHY_ILT_A_CTRL 0x0072
284 #define B43_PHY_ILT_A_DATA1 0x0073
285 #define B43_PHY_ILT_A_DATA2 0x0074
286 #define B43_PHY_G_LO_CONTROL 0x0810
287 #define B43_PHY_ILT_G_CTRL 0x0472
288 #define B43_PHY_ILT_G_DATA1 0x0473
289 #define B43_PHY_ILT_G_DATA2 0x0474
290 #define B43_PHY_A_PCTL 0x007B
291 #define B43_PHY_G_PCTL 0x0029
292 #define B43_PHY_A_CRS 0x0029
293 #define B43_PHY_RADIO_BITFIELD 0x0401
294 #define B43_PHY_G_CRS 0x0429
295 #define B43_PHY_NRSSILT_CTRL 0x0803
296 #define B43_PHY_NRSSILT_DATA 0x0804
297
298 /* RadioRegisters */
299 #define B43_RADIOCTL_ID 0x01
300
301 /* MAC Control bitfield */
302 #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
303 #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
304 #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
305 #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
306 #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
307 #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
308 #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
309 #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
310 #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */
311 #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
312 #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */
313 #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
314 #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
315 #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
316 #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
317 #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
318 #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
319 #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
320 #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */
321 #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
322 #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
323 #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
324 #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
325 #define B43_MACCTL_GMODE 0x80000000 /* G Mode */
326
327 /* MAC Command bitfield */
328 #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
329 #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
330 #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
331 #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
332 #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
333
334 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
335 #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
336 #define B43_TMSLOW_PHYCLKSPEED 0x00C00000 /* PHY clock speed mask (N-PHY only) */
337 #define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x00000000 /* 40 MHz PHY */
338 #define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x00400000 /* 80 MHz PHY */
339 #define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x00800000 /* 160 MHz PHY */
340 #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */
341 #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
342 #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
343 #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
344
345 /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
346 #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */
347 #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
348 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */
349 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */
350
351 /* Generic-Interrupt reasons. */
352 #define B43_IRQ_MAC_SUSPENDED 0x00000001
353 #define B43_IRQ_BEACON 0x00000002
354 #define B43_IRQ_TBTT_INDI 0x00000004
355 #define B43_IRQ_BEACON_TX_OK 0x00000008
356 #define B43_IRQ_BEACON_CANCEL 0x00000010
357 #define B43_IRQ_ATIM_END 0x00000020
358 #define B43_IRQ_PMQ 0x00000040
359 #define B43_IRQ_PIO_WORKAROUND 0x00000100
360 #define B43_IRQ_MAC_TXERR 0x00000200
361 #define B43_IRQ_PHY_TXERR 0x00000800
362 #define B43_IRQ_PMEVENT 0x00001000
363 #define B43_IRQ_TIMER0 0x00002000
364 #define B43_IRQ_TIMER1 0x00004000
365 #define B43_IRQ_DMA 0x00008000
366 #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
367 #define B43_IRQ_CCA_MEASURE_OK 0x00020000
368 #define B43_IRQ_NOISESAMPLE_OK 0x00040000
369 #define B43_IRQ_UCODE_DEBUG 0x08000000
370 #define B43_IRQ_RFKILL 0x10000000
371 #define B43_IRQ_TX_OK 0x20000000
372 #define B43_IRQ_PHY_G_CHANGED 0x40000000
373 #define B43_IRQ_TIMEOUT 0x80000000
374
375 #define B43_IRQ_ALL 0xFFFFFFFF
376 #define B43_IRQ_MASKTEMPLATE (B43_IRQ_MAC_SUSPENDED | \
377 B43_IRQ_BEACON | \
378 B43_IRQ_TBTT_INDI | \
379 B43_IRQ_ATIM_END | \
380 B43_IRQ_PMQ | \
381 B43_IRQ_MAC_TXERR | \
382 B43_IRQ_PHY_TXERR | \
383 B43_IRQ_DMA | \
384 B43_IRQ_TXFIFO_FLUSH_OK | \
385 B43_IRQ_NOISESAMPLE_OK | \
386 B43_IRQ_UCODE_DEBUG | \
387 B43_IRQ_RFKILL | \
388 B43_IRQ_TX_OK)
389
390 /* Device specific rate values.
391 * The actual values defined here are (rate_in_mbps * 2).
392 * Some code depends on this. Don't change it. */
393 #define B43_CCK_RATE_1MB 0x02
394 #define B43_CCK_RATE_2MB 0x04
395 #define B43_CCK_RATE_5MB 0x0B
396 #define B43_CCK_RATE_11MB 0x16
397 #define B43_OFDM_RATE_6MB 0x0C
398 #define B43_OFDM_RATE_9MB 0x12
399 #define B43_OFDM_RATE_12MB 0x18
400 #define B43_OFDM_RATE_18MB 0x24
401 #define B43_OFDM_RATE_24MB 0x30
402 #define B43_OFDM_RATE_36MB 0x48
403 #define B43_OFDM_RATE_48MB 0x60
404 #define B43_OFDM_RATE_54MB 0x6C
405 /* Convert a b43 rate value to a rate in 100kbps */
406 #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
407
408 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7
409 #define B43_DEFAULT_LONG_RETRY_LIMIT 4
410
411 #define B43_PHY_TX_BADNESS_LIMIT 1000
412
413 /* Max size of a security key */
414 #define B43_SEC_KEYSIZE 16
415 /* Security algorithms. */
416 enum {
417 B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
418 B43_SEC_ALGO_WEP40,
419 B43_SEC_ALGO_TKIP,
420 B43_SEC_ALGO_AES,
421 B43_SEC_ALGO_WEP104,
422 B43_SEC_ALGO_AES_LEGACY,
423 };
424
425 struct b43_dmaring;
426 struct b43_pioqueue;
427
428 /* The firmware file header */
429 #define B43_FW_TYPE_UCODE 'u'
430 #define B43_FW_TYPE_PCM 'p'
431 #define B43_FW_TYPE_IV 'i'
432 struct b43_fw_header {
433 /* File type */
434 u8 type;
435 /* File format version */
436 u8 ver;
437 u8 __padding[2];
438 /* Size of the data. For ucode and PCM this is in bytes.
439 * For IV this is number-of-ivs. */
440 __be32 size;
441 } __attribute__((__packed__));
442
443 /* Initial Value file format */
444 #define B43_IV_OFFSET_MASK 0x7FFF
445 #define B43_IV_32BIT 0x8000
446 struct b43_iv {
447 __be16 offset_size;
448 union {
449 __be16 d16;
450 __be32 d32;
451 } data __attribute__((__packed__));
452 } __attribute__((__packed__));
453
454
455 #define B43_PHYMODE(phytype) (1 << (phytype))
456 #define B43_PHYMODE_A B43_PHYMODE(B43_PHYTYPE_A)
457 #define B43_PHYMODE_B B43_PHYMODE(B43_PHYTYPE_B)
458 #define B43_PHYMODE_G B43_PHYMODE(B43_PHYTYPE_G)
459
460 struct b43_phy {
461 /* Possible PHYMODEs on this PHY */
462 u8 possible_phymodes;
463 /* GMODE bit enabled? */
464 bool gmode;
465
466 /* Analog Type */
467 u8 analog;
468 /* B43_PHYTYPE_ */
469 u8 type;
470 /* PHY revision number. */
471 u8 rev;
472
473 /* Radio versioning */
474 u16 radio_manuf; /* Radio manufacturer */
475 u16 radio_ver; /* Radio version */
476 u8 radio_rev; /* Radio revision */
477
478 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
479
480 /* ACI (adjacent channel interference) flags. */
481 bool aci_enable;
482 bool aci_wlan_automatic;
483 bool aci_hw_rssi;
484
485 /* Radio switched on/off */
486 bool radio_on;
487 struct {
488 /* Values saved when turning the radio off.
489 * They are needed when turning it on again. */
490 bool valid;
491 u16 rfover;
492 u16 rfoverval;
493 } radio_off_context;
494
495 u16 minlowsig[2];
496 u16 minlowsigpos[2];
497
498 /* TSSI to dBm table in use */
499 const s8 *tssi2dbm;
500 /* Target idle TSSI */
501 int tgt_idle_tssi;
502 /* Current idle TSSI */
503 int cur_idle_tssi;
504
505 /* LocalOscillator control values. */
506 struct b43_txpower_lo_control *lo_control;
507 /* Values from b43_calc_loopback_gain() */
508 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
509 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
510 s16 lna_lod_gain; /* LNA lod */
511 s16 lna_gain; /* LNA */
512 s16 pga_gain; /* PGA */
513
514 /* Desired TX power level (in dBm).
515 * This is set by the user and adjusted in b43_phy_xmitpower(). */
516 u8 power_level;
517 /* A-PHY TX Power control value. */
518 u16 txpwr_offset;
519
520 /* Current TX power level attenuation control values */
521 struct b43_bbatt bbatt;
522 struct b43_rfatt rfatt;
523 u8 tx_control; /* B43_TXCTL_XXX */
524
525 /* Hardware Power Control enabled? */
526 bool hardware_power_control;
527
528 /* Current Interference Mitigation mode */
529 int interfmode;
530 /* Stack of saved values from the Interference Mitigation code.
531 * Each value in the stack is layed out as follows:
532 * bit 0-11: offset
533 * bit 12-15: register ID
534 * bit 16-32: value
535 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
536 */
537 #define B43_INTERFSTACK_SIZE 26
538 u32 interfstack[B43_INTERFSTACK_SIZE]; //FIXME: use a data structure
539
540 /* Saved values from the NRSSI Slope calculation */
541 s16 nrssi[2];
542 s32 nrssislope;
543 /* In memory nrssi lookup table. */
544 s8 nrssi_lt[64];
545
546 /* current channel */
547 u8 channel;
548
549 u16 lofcal;
550
551 u16 initval; //FIXME rename?
552
553 /* PHY TX errors counter. */
554 atomic_t txerr_cnt;
555
556 /* The device does address auto increment for the OFDM tables.
557 * We cache the previously used address here and omit the address
558 * write on the next table access, if possible. */
559 u16 ofdmtab_addr; /* The address currently set in hardware. */
560 enum { /* The last data flow direction. */
561 B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
562 B43_OFDMTAB_DIRECTION_READ,
563 B43_OFDMTAB_DIRECTION_WRITE,
564 } ofdmtab_addr_direction;
565
566 #if B43_DEBUG
567 /* Manual TX-power control enabled? */
568 bool manual_txpower_control;
569 /* PHY registers locked by b43_phy_lock()? */
570 bool phy_locked;
571 #endif /* B43_DEBUG */
572 };
573
574 /* Data structures for DMA transmission, per 80211 core. */
575 struct b43_dma {
576 struct b43_dmaring *tx_ring0;
577 struct b43_dmaring *tx_ring1;
578 struct b43_dmaring *tx_ring2;
579 struct b43_dmaring *tx_ring3;
580 struct b43_dmaring *tx_ring4;
581 struct b43_dmaring *tx_ring5;
582
583 struct b43_dmaring *rx_ring0;
584 struct b43_dmaring *rx_ring3; /* only available on core.rev < 5 */
585 };
586
587 /* Context information for a noise calculation (Link Quality). */
588 struct b43_noise_calculation {
589 u8 channel_at_start;
590 bool calculation_running;
591 u8 nr_samples;
592 s8 samples[8][4];
593 };
594
595 struct b43_stats {
596 u8 link_noise;
597 /* Store the last TX/RX times here for updating the leds. */
598 unsigned long last_tx;
599 unsigned long last_rx;
600 };
601
602 struct b43_key {
603 /* If keyconf is NULL, this key is disabled.
604 * keyconf is a cookie. Don't derefenrence it outside of the set_key
605 * path, because b43 doesn't own it. */
606 struct ieee80211_key_conf *keyconf;
607 u8 algorithm;
608 };
609
610 struct b43_wldev;
611
612 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
613 struct b43_wl {
614 /* Pointer to the active wireless device on this chip */
615 struct b43_wldev *current_dev;
616 /* Pointer to the ieee80211 hardware data structure */
617 struct ieee80211_hw *hw;
618
619 struct mutex mutex;
620 spinlock_t irq_lock;
621 /* Lock for LEDs access. */
622 spinlock_t leds_lock;
623 /* Lock for SHM access. */
624 spinlock_t shm_lock;
625
626 /* We can only have one operating interface (802.11 core)
627 * at a time. General information about this interface follows.
628 */
629
630 struct ieee80211_vif *vif;
631 /* The MAC address of the operating interface. */
632 u8 mac_addr[ETH_ALEN];
633 /* Current BSSID */
634 u8 bssid[ETH_ALEN];
635 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
636 int if_type;
637 /* Is the card operating in AP, STA or IBSS mode? */
638 bool operating;
639 /* filter flags */
640 unsigned int filter_flags;
641 /* Stats about the wireless interface */
642 struct ieee80211_low_level_stats ieee_stats;
643
644 struct hwrng rng;
645 u8 rng_initialized;
646 char rng_name[30 + 1];
647
648 /* The RF-kill button */
649 struct b43_rfkill rfkill;
650
651 /* List of all wireless devices on this chip */
652 struct list_head devlist;
653 u8 nr_devs;
654
655 bool radiotap_enabled;
656
657 /* The beacon we are currently using (AP or IBSS mode).
658 * This beacon stuff is protected by the irq_lock. */
659 struct sk_buff *current_beacon;
660 bool beacon0_uploaded;
661 bool beacon1_uploaded;
662 };
663
664 /* In-memory representation of a cached microcode file. */
665 struct b43_firmware_file {
666 const char *filename;
667 const struct firmware *data;
668 };
669
670 /* Pointers to the firmware data and meta information about it. */
671 struct b43_firmware {
672 /* Microcode */
673 struct b43_firmware_file ucode;
674 /* PCM code */
675 struct b43_firmware_file pcm;
676 /* Initial MMIO values for the firmware */
677 struct b43_firmware_file initvals;
678 /* Initial MMIO values for the firmware, band-specific */
679 struct b43_firmware_file initvals_band;
680
681 /* Firmware revision */
682 u16 rev;
683 /* Firmware patchlevel */
684 u16 patch;
685 };
686
687 /* Device (802.11 core) initialization status. */
688 enum {
689 B43_STAT_UNINIT = 0, /* Uninitialized. */
690 B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */
691 B43_STAT_STARTED = 2, /* Up and running. */
692 };
693 #define b43_status(wldev) atomic_read(&(wldev)->__init_status)
694 #define b43_set_status(wldev, stat) do { \
695 atomic_set(&(wldev)->__init_status, (stat)); \
696 smp_wmb(); \
697 } while (0)
698
699 /* XXX--- HOW LOCKING WORKS IN B43 ---XXX
700 *
701 * You should always acquire both, wl->mutex and wl->irq_lock unless:
702 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
703 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
704 * and packet TX path (and _ONLY_ there.)
705 */
706
707 /* Data structure for one wireless device (802.11 core) */
708 struct b43_wldev {
709 struct ssb_device *dev;
710 struct b43_wl *wl;
711
712 /* The device initialization status.
713 * Use b43_status() to query. */
714 atomic_t __init_status;
715 /* Saved init status for handling suspend. */
716 int suspend_init_status;
717
718 bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */
719 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */
720 bool short_slot; /* TRUE, if short slot timing is enabled. */
721 bool radio_hw_enable; /* saved state of radio hardware enabled state */
722
723 /* PHY/Radio device. */
724 struct b43_phy phy;
725
726 /* DMA engines. */
727 struct b43_dma dma;
728
729 /* Various statistics about the physical device. */
730 struct b43_stats stats;
731
732 /* The device LEDs. */
733 struct b43_led led_tx;
734 struct b43_led led_rx;
735 struct b43_led led_assoc;
736 struct b43_led led_radio;
737
738 /* Reason code of the last interrupt. */
739 u32 irq_reason;
740 u32 dma_reason[6];
741 /* saved irq enable/disable state bitfield. */
742 u32 irq_savedstate;
743 /* Link Quality calculation context. */
744 struct b43_noise_calculation noisecalc;
745 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
746 int mac_suspended;
747
748 /* Interrupt Service Routine tasklet (bottom-half) */
749 struct tasklet_struct isr_tasklet;
750
751 /* Periodic tasks */
752 struct delayed_work periodic_work;
753 unsigned int periodic_state;
754
755 struct work_struct restart_work;
756
757 /* encryption/decryption */
758 u16 ktp; /* Key table pointer */
759 u8 max_nr_keys;
760 struct b43_key key[58];
761
762 /* Firmware data */
763 struct b43_firmware fw;
764
765 /* Devicelist in struct b43_wl (all 802.11 cores) */
766 struct list_head list;
767
768 /* Debugging stuff follows. */
769 #ifdef CONFIG_B43_DEBUG
770 struct b43_dfsentry *dfsentry;
771 #endif
772 };
773
774 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
775 {
776 return hw->priv;
777 }
778
779 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
780 {
781 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
782 return ssb_get_drvdata(ssb_dev);
783 }
784
785 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
786 static inline int b43_is_mode(struct b43_wl *wl, int type)
787 {
788 return (wl->operating && wl->if_type == type);
789 }
790
791 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
792 {
793 return ssb_read16(dev->dev, offset);
794 }
795
796 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
797 {
798 ssb_write16(dev->dev, offset, value);
799 }
800
801 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
802 {
803 return ssb_read32(dev->dev, offset);
804 }
805
806 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
807 {
808 ssb_write32(dev->dev, offset, value);
809 }
810
811 /* Message printing */
812 void b43info(struct b43_wl *wl, const char *fmt, ...)
813 __attribute__ ((format(printf, 2, 3)));
814 void b43err(struct b43_wl *wl, const char *fmt, ...)
815 __attribute__ ((format(printf, 2, 3)));
816 void b43warn(struct b43_wl *wl, const char *fmt, ...)
817 __attribute__ ((format(printf, 2, 3)));
818 #if B43_DEBUG
819 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
820 __attribute__ ((format(printf, 2, 3)));
821 #else /* DEBUG */
822 # define b43dbg(wl, fmt...) do { /* nothing */ } while (0)
823 #endif /* DEBUG */
824
825 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
826 * This _also_ evaluates the arg with debugging disabled. */
827 #if B43_DEBUG
828 # define B43_WARN_ON(x) WARN_ON(x)
829 #else
830 static inline bool __b43_warn_on_dummy(bool x) { return x; }
831 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
832 #endif
833
834 /** Limit a value between two limits */
835 #ifdef limit_value
836 # undef limit_value
837 #endif
838 #define limit_value(value, min, max) \
839 ({ \
840 typeof(value) __value = (value); \
841 typeof(value) __min = (min); \
842 typeof(value) __max = (max); \
843 if (__value < __min) \
844 __value = __min; \
845 else if (__value > __max) \
846 __value = __max; \
847 __value; \
848 })
849
850 /* Convert an integer to a Q5.2 value */
851 #define INT_TO_Q52(i) ((i) << 2)
852 /* Convert a Q5.2 value to an integer (precision loss!) */
853 #define Q52_TO_INT(q52) ((q52) >> 2)
854 /* Macros for printing a value in Q5.2 format */
855 #define Q52_FMT "%u.%u"
856 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
857
858 #endif /* B43_H_ */