9f8175c25a8a2785887e930a23613eed10282c30
[openwrt/svn-archive/archive.git] / package / b43 / src / main.c
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
43
44 #include "b43.h"
45 #include "main.h"
46 #include "debugfs.h"
47 #include "phy.h"
48 #include "dma.h"
49 #include "pio.h"
50 #include "sysfs.h"
51 #include "xmit.h"
52 #include "lo.h"
53 #include "pcmcia.h"
54
55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
56 MODULE_AUTHOR("Martin Langer");
57 MODULE_AUTHOR("Stefano Brivio");
58 MODULE_AUTHOR("Michael Buesch");
59 MODULE_LICENSE("GPL");
60
61 extern char *nvram_get(char *name);
62
63 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
64 static int modparam_pio;
65 module_param_named(pio, modparam_pio, int, 0444);
66 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
67 #elif defined(CONFIG_B43_DMA)
68 # define modparam_pio 0
69 #elif defined(CONFIG_B43_PIO)
70 # define modparam_pio 1
71 #endif
72
73 static int modparam_bad_frames_preempt;
74 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
75 MODULE_PARM_DESC(bad_frames_preempt,
76 "enable(1) / disable(0) Bad Frames Preemption");
77
78 static int modparam_short_retry = B43_DEFAULT_SHORT_RETRY_LIMIT;
79 module_param_named(short_retry, modparam_short_retry, int, 0444);
80 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
81
82 static int modparam_long_retry = B43_DEFAULT_LONG_RETRY_LIMIT;
83 module_param_named(long_retry, modparam_long_retry, int, 0444);
84 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
85
86 static char modparam_fwpostfix[16];
87 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
88 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
89
90 static int modparam_hwpctl;
91 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
92 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
93
94 static int modparam_nohwcrypt;
95 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
96 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
97
98 static const struct ssb_device_id b43_ssb_tbl[] = {
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
104 SSB_DEVTABLE_END
105 };
106
107 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
108
109 static const struct pci_device_id b43_pci_bridge_tbl[] = {
110 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4311) },
111 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
112 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
113 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
114 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
115 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
116 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
117 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
118 { 0, },
119 };
120 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
121
122 static struct pci_driver b43_pci_bridge_driver = {
123 .name = "b43-pci-bridge",
124 .id_table = b43_pci_bridge_tbl,
125 };
126 /* Channel and ratetables are shared for all devices.
127 * They can't be const, because ieee80211 puts some precalculated
128 * data in there. This data is the same for all devices, so we don't
129 * get concurrency issues */
130 #define RATETAB_ENT(_rateid, _flags) \
131 { \
132 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
133 .val = (_rateid), \
134 .val2 = (_rateid), \
135 .flags = (_flags), \
136 }
137 static struct ieee80211_rate __b43_ratetable[] = {
138 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
139 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
140 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
141 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
142 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
143 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
144 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
145 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
146 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
147 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
148 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
149 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
150 };
151
152 #define b43_a_ratetable (__b43_ratetable + 4)
153 #define b43_a_ratetable_size 8
154 #define b43_b_ratetable (__b43_ratetable + 0)
155 #define b43_b_ratetable_size 4
156 #define b43_g_ratetable (__b43_ratetable + 0)
157 #define b43_g_ratetable_size 12
158
159 #define CHANTAB_ENT(_chanid, _freq) \
160 { \
161 .chan = (_chanid), \
162 .freq = (_freq), \
163 .val = (_chanid), \
164 .flag = IEEE80211_CHAN_W_SCAN | \
165 IEEE80211_CHAN_W_ACTIVE_SCAN | \
166 IEEE80211_CHAN_W_IBSS, \
167 .power_level = 0xFF, \
168 .antenna_max = 0xFF, \
169 }
170 static struct ieee80211_channel b43_bg_chantable[] = {
171 CHANTAB_ENT(1, 2412),
172 CHANTAB_ENT(2, 2417),
173 CHANTAB_ENT(3, 2422),
174 CHANTAB_ENT(4, 2427),
175 CHANTAB_ENT(5, 2432),
176 CHANTAB_ENT(6, 2437),
177 CHANTAB_ENT(7, 2442),
178 CHANTAB_ENT(8, 2447),
179 CHANTAB_ENT(9, 2452),
180 CHANTAB_ENT(10, 2457),
181 CHANTAB_ENT(11, 2462),
182 CHANTAB_ENT(12, 2467),
183 CHANTAB_ENT(13, 2472),
184 CHANTAB_ENT(14, 2484),
185 };
186
187 #define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable)
188 static struct ieee80211_channel b43_a_chantable[] = {
189 CHANTAB_ENT(36, 5180),
190 CHANTAB_ENT(40, 5200),
191 CHANTAB_ENT(44, 5220),
192 CHANTAB_ENT(48, 5240),
193 CHANTAB_ENT(52, 5260),
194 CHANTAB_ENT(56, 5280),
195 CHANTAB_ENT(60, 5300),
196 CHANTAB_ENT(64, 5320),
197 CHANTAB_ENT(149, 5745),
198 CHANTAB_ENT(153, 5765),
199 CHANTAB_ENT(157, 5785),
200 CHANTAB_ENT(161, 5805),
201 CHANTAB_ENT(165, 5825),
202 };
203
204 #define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable)
205
206 static void b43_wireless_core_exit(struct b43_wldev *dev);
207 static int b43_wireless_core_init(struct b43_wldev *dev);
208 static void b43_wireless_core_stop(struct b43_wldev *dev);
209 static int b43_wireless_core_start(struct b43_wldev *dev);
210
211 static int b43_ratelimit(struct b43_wl *wl)
212 {
213 if (!wl || !wl->current_dev)
214 return 1;
215 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
216 return 1;
217 /* We are up and running.
218 * Ratelimit the messages to avoid DoS over the net. */
219 return net_ratelimit();
220 }
221
222 void b43info(struct b43_wl *wl, const char *fmt, ...)
223 {
224 va_list args;
225
226 if (!b43_ratelimit(wl))
227 return;
228 va_start(args, fmt);
229 printk(KERN_INFO "b43-%s: ",
230 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
231 vprintk(fmt, args);
232 va_end(args);
233 }
234
235 void b43err(struct b43_wl *wl, const char *fmt, ...)
236 {
237 va_list args;
238
239 if (!b43_ratelimit(wl))
240 return;
241 va_start(args, fmt);
242 printk(KERN_ERR "b43-%s ERROR: ",
243 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
244 vprintk(fmt, args);
245 va_end(args);
246 }
247
248 void b43warn(struct b43_wl *wl, const char *fmt, ...)
249 {
250 va_list args;
251
252 if (!b43_ratelimit(wl))
253 return;
254 va_start(args, fmt);
255 printk(KERN_WARNING "b43-%s warning: ",
256 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
257 vprintk(fmt, args);
258 va_end(args);
259 }
260
261 #if B43_DEBUG
262 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
263 {
264 va_list args;
265
266 va_start(args, fmt);
267 printk(KERN_DEBUG "b43-%s debug: ",
268 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
269 vprintk(fmt, args);
270 va_end(args);
271 }
272 #endif /* DEBUG */
273
274 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
275 {
276 u32 macctl;
277
278 B43_WARN_ON(offset % 4 != 0);
279
280 macctl = b43_read32(dev, B43_MMIO_MACCTL);
281 if (macctl & B43_MACCTL_BE)
282 val = swab32(val);
283
284 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
285 mmiowb();
286 b43_write32(dev, B43_MMIO_RAM_DATA, val);
287 }
288
289 static inline
290 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
291 {
292 u32 control;
293
294 /* "offset" is the WORD offset. */
295
296 control = routing;
297 control <<= 16;
298 control |= offset;
299 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
300 }
301
302 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
303 {
304 u32 ret;
305
306 if (routing == B43_SHM_SHARED) {
307 B43_WARN_ON(offset & 0x0001);
308 if (offset & 0x0003) {
309 /* Unaligned access */
310 b43_shm_control_word(dev, routing, offset >> 2);
311 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
312 ret <<= 16;
313 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
314 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
315
316 return ret;
317 }
318 offset >>= 2;
319 }
320 b43_shm_control_word(dev, routing, offset);
321 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
322
323 return ret;
324 }
325
326 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
327 {
328 u16 ret;
329
330 if (routing == B43_SHM_SHARED) {
331 B43_WARN_ON(offset & 0x0001);
332 if (offset & 0x0003) {
333 /* Unaligned access */
334 b43_shm_control_word(dev, routing, offset >> 2);
335 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
336
337 return ret;
338 }
339 offset >>= 2;
340 }
341 b43_shm_control_word(dev, routing, offset);
342 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
343
344 return ret;
345 }
346
347 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
348 {
349 if (routing == B43_SHM_SHARED) {
350 B43_WARN_ON(offset & 0x0001);
351 if (offset & 0x0003) {
352 /* Unaligned access */
353 b43_shm_control_word(dev, routing, offset >> 2);
354 mmiowb();
355 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
356 (value >> 16) & 0xffff);
357 mmiowb();
358 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
359 mmiowb();
360 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
361 return;
362 }
363 offset >>= 2;
364 }
365 b43_shm_control_word(dev, routing, offset);
366 mmiowb();
367 b43_write32(dev, B43_MMIO_SHM_DATA, value);
368 }
369
370 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
371 {
372 if (routing == B43_SHM_SHARED) {
373 B43_WARN_ON(offset & 0x0001);
374 if (offset & 0x0003) {
375 /* Unaligned access */
376 b43_shm_control_word(dev, routing, offset >> 2);
377 mmiowb();
378 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
379 return;
380 }
381 offset >>= 2;
382 }
383 b43_shm_control_word(dev, routing, offset);
384 mmiowb();
385 b43_write16(dev, B43_MMIO_SHM_DATA, value);
386 }
387
388 /* Read HostFlags */
389 u32 b43_hf_read(struct b43_wldev * dev)
390 {
391 u32 ret;
392
393 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
394 ret <<= 16;
395 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
396
397 return ret;
398 }
399
400 /* Write HostFlags */
401 void b43_hf_write(struct b43_wldev *dev, u32 value)
402 {
403 b43_shm_write16(dev, B43_SHM_SHARED,
404 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
405 b43_shm_write16(dev, B43_SHM_SHARED,
406 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
407 }
408
409 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
410 {
411 /* We need to be careful. As we read the TSF from multiple
412 * registers, we should take care of register overflows.
413 * In theory, the whole tsf read process should be atomic.
414 * We try to be atomic here, by restaring the read process,
415 * if any of the high registers changed (overflew).
416 */
417 if (dev->dev->id.revision >= 3) {
418 u32 low, high, high2;
419
420 do {
421 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
422 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
423 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
424 } while (unlikely(high != high2));
425
426 *tsf = high;
427 *tsf <<= 32;
428 *tsf |= low;
429 } else {
430 u64 tmp;
431 u16 v0, v1, v2, v3;
432 u16 test1, test2, test3;
433
434 do {
435 v3 = b43_read16(dev, B43_MMIO_TSF_3);
436 v2 = b43_read16(dev, B43_MMIO_TSF_2);
437 v1 = b43_read16(dev, B43_MMIO_TSF_1);
438 v0 = b43_read16(dev, B43_MMIO_TSF_0);
439
440 test3 = b43_read16(dev, B43_MMIO_TSF_3);
441 test2 = b43_read16(dev, B43_MMIO_TSF_2);
442 test1 = b43_read16(dev, B43_MMIO_TSF_1);
443 } while (v3 != test3 || v2 != test2 || v1 != test1);
444
445 *tsf = v3;
446 *tsf <<= 48;
447 tmp = v2;
448 tmp <<= 32;
449 *tsf |= tmp;
450 tmp = v1;
451 tmp <<= 16;
452 *tsf |= tmp;
453 *tsf |= v0;
454 }
455 }
456
457 static void b43_time_lock(struct b43_wldev *dev)
458 {
459 u32 macctl;
460
461 macctl = b43_read32(dev, B43_MMIO_MACCTL);
462 macctl |= B43_MACCTL_TBTTHOLD;
463 b43_write32(dev, B43_MMIO_MACCTL, macctl);
464 /* Commit the write */
465 b43_read32(dev, B43_MMIO_MACCTL);
466 }
467
468 static void b43_time_unlock(struct b43_wldev *dev)
469 {
470 u32 macctl;
471
472 macctl = b43_read32(dev, B43_MMIO_MACCTL);
473 macctl &= ~B43_MACCTL_TBTTHOLD;
474 b43_write32(dev, B43_MMIO_MACCTL, macctl);
475 /* Commit the write */
476 b43_read32(dev, B43_MMIO_MACCTL);
477 }
478
479 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
480 {
481 /* Be careful with the in-progress timer.
482 * First zero out the low register, so we have a full
483 * register-overflow duration to complete the operation.
484 */
485 if (dev->dev->id.revision >= 3) {
486 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
487 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
488
489 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
490 mmiowb();
491 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
492 mmiowb();
493 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
494 } else {
495 u16 v0 = (tsf & 0x000000000000FFFFULL);
496 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
497 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
498 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
499
500 b43_write16(dev, B43_MMIO_TSF_0, 0);
501 mmiowb();
502 b43_write16(dev, B43_MMIO_TSF_3, v3);
503 mmiowb();
504 b43_write16(dev, B43_MMIO_TSF_2, v2);
505 mmiowb();
506 b43_write16(dev, B43_MMIO_TSF_1, v1);
507 mmiowb();
508 b43_write16(dev, B43_MMIO_TSF_0, v0);
509 }
510 }
511
512 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
513 {
514 b43_time_lock(dev);
515 b43_tsf_write_locked(dev, tsf);
516 b43_time_unlock(dev);
517 }
518
519 static
520 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
521 {
522 static const u8 zero_addr[ETH_ALEN] = { 0 };
523 u16 data;
524
525 if (!mac)
526 mac = zero_addr;
527
528 offset |= 0x0020;
529 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
530
531 data = mac[0];
532 data |= mac[1] << 8;
533 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
534 data = mac[2];
535 data |= mac[3] << 8;
536 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
537 data = mac[4];
538 data |= mac[5] << 8;
539 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
540 }
541
542 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
543 {
544 const u8 *mac;
545 const u8 *bssid;
546 u8 mac_bssid[ETH_ALEN * 2];
547 int i;
548 u32 tmp;
549
550 bssid = dev->wl->bssid;
551 mac = dev->wl->mac_addr;
552
553 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
554
555 memcpy(mac_bssid, mac, ETH_ALEN);
556 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
557
558 /* Write our MAC address and BSSID to template ram */
559 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
560 tmp = (u32) (mac_bssid[i + 0]);
561 tmp |= (u32) (mac_bssid[i + 1]) << 8;
562 tmp |= (u32) (mac_bssid[i + 2]) << 16;
563 tmp |= (u32) (mac_bssid[i + 3]) << 24;
564 b43_ram_write(dev, 0x20 + i, tmp);
565 }
566 }
567
568 static void b43_upload_card_macaddress(struct b43_wldev *dev)
569 {
570 b43_write_mac_bssid_templates(dev);
571 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
572 }
573
574 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
575 {
576 /* slot_time is in usec. */
577 if (dev->phy.type != B43_PHYTYPE_G)
578 return;
579 b43_write16(dev, 0x684, 510 + slot_time);
580 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
581 }
582
583 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
584 {
585 b43_set_slot_time(dev, 9);
586 dev->short_slot = 1;
587 }
588
589 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
590 {
591 b43_set_slot_time(dev, 20);
592 dev->short_slot = 0;
593 }
594
595 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
596 * Returns the _previously_ enabled IRQ mask.
597 */
598 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
599 {
600 u32 old_mask;
601
602 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
603 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
604
605 return old_mask;
606 }
607
608 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
609 * Returns the _previously_ enabled IRQ mask.
610 */
611 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
612 {
613 u32 old_mask;
614
615 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
616 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
617
618 return old_mask;
619 }
620
621 /* Synchronize IRQ top- and bottom-half.
622 * IRQs must be masked before calling this.
623 * This must not be called with the irq_lock held.
624 */
625 static void b43_synchronize_irq(struct b43_wldev *dev)
626 {
627 synchronize_irq(dev->dev->irq);
628 tasklet_kill(&dev->isr_tasklet);
629 }
630
631 /* DummyTransmission function, as documented on
632 * http://bcm-specs.sipsolutions.net/DummyTransmission
633 */
634 void b43_dummy_transmission(struct b43_wldev *dev)
635 {
636 struct b43_phy *phy = &dev->phy;
637 unsigned int i, max_loop;
638 u16 value;
639 u32 buffer[5] = {
640 0x00000000,
641 0x00D40000,
642 0x00000000,
643 0x01000000,
644 0x00000000,
645 };
646
647 switch (phy->type) {
648 case B43_PHYTYPE_A:
649 max_loop = 0x1E;
650 buffer[0] = 0x000201CC;
651 break;
652 case B43_PHYTYPE_B:
653 case B43_PHYTYPE_G:
654 max_loop = 0xFA;
655 buffer[0] = 0x000B846E;
656 break;
657 default:
658 B43_WARN_ON(1);
659 return;
660 }
661
662 for (i = 0; i < 5; i++)
663 b43_ram_write(dev, i * 4, buffer[i]);
664
665 /* Commit writes */
666 b43_read32(dev, B43_MMIO_MACCTL);
667
668 b43_write16(dev, 0x0568, 0x0000);
669 b43_write16(dev, 0x07C0, 0x0000);
670 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
671 b43_write16(dev, 0x050C, value);
672 b43_write16(dev, 0x0508, 0x0000);
673 b43_write16(dev, 0x050A, 0x0000);
674 b43_write16(dev, 0x054C, 0x0000);
675 b43_write16(dev, 0x056A, 0x0014);
676 b43_write16(dev, 0x0568, 0x0826);
677 b43_write16(dev, 0x0500, 0x0000);
678 b43_write16(dev, 0x0502, 0x0030);
679
680 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
681 b43_radio_write16(dev, 0x0051, 0x0017);
682 for (i = 0x00; i < max_loop; i++) {
683 value = b43_read16(dev, 0x050E);
684 if (value & 0x0080)
685 break;
686 udelay(10);
687 }
688 for (i = 0x00; i < 0x0A; i++) {
689 value = b43_read16(dev, 0x050E);
690 if (value & 0x0400)
691 break;
692 udelay(10);
693 }
694 for (i = 0x00; i < 0x0A; i++) {
695 value = b43_read16(dev, 0x0690);
696 if (!(value & 0x0100))
697 break;
698 udelay(10);
699 }
700 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
701 b43_radio_write16(dev, 0x0051, 0x0037);
702 }
703
704 static void key_write(struct b43_wldev *dev,
705 u8 index, u8 algorithm, const u8 * key)
706 {
707 unsigned int i;
708 u32 offset;
709 u16 value;
710 u16 kidx;
711
712 /* Key index/algo block */
713 kidx = b43_kidx_to_fw(dev, index);
714 value = ((kidx << 4) | algorithm);
715 b43_shm_write16(dev, B43_SHM_SHARED,
716 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
717
718 /* Write the key to the Key Table Pointer offset */
719 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
720 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
721 value = key[i];
722 value |= (u16) (key[i + 1]) << 8;
723 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
724 }
725 }
726
727 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
728 {
729 u32 addrtmp[2] = { 0, 0, };
730 u8 per_sta_keys_start = 8;
731
732 if (b43_new_kidx_api(dev))
733 per_sta_keys_start = 4;
734
735 B43_WARN_ON(index < per_sta_keys_start);
736 /* We have two default TX keys and possibly two default RX keys.
737 * Physical mac 0 is mapped to physical key 4 or 8, depending
738 * on the firmware version.
739 * So we must adjust the index here.
740 */
741 index -= per_sta_keys_start;
742
743 if (addr) {
744 addrtmp[0] = addr[0];
745 addrtmp[0] |= ((u32) (addr[1]) << 8);
746 addrtmp[0] |= ((u32) (addr[2]) << 16);
747 addrtmp[0] |= ((u32) (addr[3]) << 24);
748 addrtmp[1] = addr[4];
749 addrtmp[1] |= ((u32) (addr[5]) << 8);
750 }
751
752 if (dev->dev->id.revision >= 5) {
753 /* Receive match transmitter address mechanism */
754 b43_shm_write32(dev, B43_SHM_RCMTA,
755 (index * 2) + 0, addrtmp[0]);
756 b43_shm_write16(dev, B43_SHM_RCMTA,
757 (index * 2) + 1, addrtmp[1]);
758 } else {
759 /* RXE (Receive Engine) and
760 * PSM (Programmable State Machine) mechanism
761 */
762 if (index < 8) {
763 /* TODO write to RCM 16, 19, 22 and 25 */
764 } else {
765 b43_shm_write32(dev, B43_SHM_SHARED,
766 B43_SHM_SH_PSM + (index * 6) + 0,
767 addrtmp[0]);
768 b43_shm_write16(dev, B43_SHM_SHARED,
769 B43_SHM_SH_PSM + (index * 6) + 4,
770 addrtmp[1]);
771 }
772 }
773 }
774
775 static void do_key_write(struct b43_wldev *dev,
776 u8 index, u8 algorithm,
777 const u8 * key, size_t key_len, const u8 * mac_addr)
778 {
779 u8 buf[B43_SEC_KEYSIZE] = { 0, };
780 u8 per_sta_keys_start = 8;
781
782 if (b43_new_kidx_api(dev))
783 per_sta_keys_start = 4;
784
785 B43_WARN_ON(index >= dev->max_nr_keys);
786 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
787
788 if (index >= per_sta_keys_start)
789 keymac_write(dev, index, NULL); /* First zero out mac. */
790 if (key)
791 memcpy(buf, key, key_len);
792 key_write(dev, index, algorithm, buf);
793 if (index >= per_sta_keys_start)
794 keymac_write(dev, index, mac_addr);
795
796 dev->key[index].algorithm = algorithm;
797 }
798
799 static int b43_key_write(struct b43_wldev *dev,
800 int index, u8 algorithm,
801 const u8 * key, size_t key_len,
802 const u8 * mac_addr,
803 struct ieee80211_key_conf *keyconf)
804 {
805 int i;
806 int sta_keys_start;
807
808 if (key_len > B43_SEC_KEYSIZE)
809 return -EINVAL;
810 for (i = 0; i < dev->max_nr_keys; i++) {
811 /* Check that we don't already have this key. */
812 B43_WARN_ON(dev->key[i].keyconf == keyconf);
813 }
814 if (index < 0) {
815 /* Either pairwise key or address is 00:00:00:00:00:00
816 * for transmit-only keys. Search the index. */
817 if (b43_new_kidx_api(dev))
818 sta_keys_start = 4;
819 else
820 sta_keys_start = 8;
821 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
822 if (!dev->key[i].keyconf) {
823 /* found empty */
824 index = i;
825 break;
826 }
827 }
828 if (index < 0) {
829 b43err(dev->wl, "Out of hardware key memory\n");
830 return -ENOSPC;
831 }
832 } else
833 B43_WARN_ON(index > 3);
834
835 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
836 if ((index <= 3) && !b43_new_kidx_api(dev)) {
837 /* Default RX key */
838 B43_WARN_ON(mac_addr);
839 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
840 }
841 keyconf->hw_key_idx = index;
842 dev->key[index].keyconf = keyconf;
843
844 return 0;
845 }
846
847 static int b43_key_clear(struct b43_wldev *dev, int index)
848 {
849 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
850 return -EINVAL;
851 do_key_write(dev, index, B43_SEC_ALGO_NONE,
852 NULL, B43_SEC_KEYSIZE, NULL);
853 if ((index <= 3) && !b43_new_kidx_api(dev)) {
854 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
855 NULL, B43_SEC_KEYSIZE, NULL);
856 }
857 dev->key[index].keyconf = NULL;
858
859 return 0;
860 }
861
862 static void b43_clear_keys(struct b43_wldev *dev)
863 {
864 int i;
865
866 for (i = 0; i < dev->max_nr_keys; i++)
867 b43_key_clear(dev, i);
868 }
869
870 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
871 {
872 u32 macctl;
873 u16 ucstat;
874 bool hwps;
875 bool awake;
876 int i;
877
878 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
879 (ps_flags & B43_PS_DISABLED));
880 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
881
882 if (ps_flags & B43_PS_ENABLED) {
883 hwps = 1;
884 } else if (ps_flags & B43_PS_DISABLED) {
885 hwps = 0;
886 } else {
887 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
888 // and thus is not an AP and we are associated, set bit 25
889 }
890 if (ps_flags & B43_PS_AWAKE) {
891 awake = 1;
892 } else if (ps_flags & B43_PS_ASLEEP) {
893 awake = 0;
894 } else {
895 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
896 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
897 // successful, set bit26
898 }
899
900 /* FIXME: For now we force awake-on and hwps-off */
901 hwps = 0;
902 awake = 1;
903
904 macctl = b43_read32(dev, B43_MMIO_MACCTL);
905 if (hwps)
906 macctl |= B43_MACCTL_HWPS;
907 else
908 macctl &= ~B43_MACCTL_HWPS;
909 if (awake)
910 macctl |= B43_MACCTL_AWAKE;
911 else
912 macctl &= ~B43_MACCTL_AWAKE;
913 b43_write32(dev, B43_MMIO_MACCTL, macctl);
914 /* Commit write */
915 b43_read32(dev, B43_MMIO_MACCTL);
916 if (awake && dev->dev->id.revision >= 5) {
917 /* Wait for the microcode to wake up. */
918 for (i = 0; i < 100; i++) {
919 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
920 B43_SHM_SH_UCODESTAT);
921 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
922 break;
923 udelay(10);
924 }
925 }
926 }
927
928 /* Turn the Analog ON/OFF */
929 static void b43_switch_analog(struct b43_wldev *dev, int on)
930 {
931 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
932 }
933
934 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
935 {
936 u32 tmslow;
937 u32 macctl;
938
939 flags |= B43_TMSLOW_PHYCLKEN;
940 flags |= B43_TMSLOW_PHYRESET;
941 ssb_device_enable(dev->dev, flags);
942 msleep(2); /* Wait for the PLL to turn on. */
943
944 /* Now take the PHY out of Reset again */
945 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
946 tmslow |= SSB_TMSLOW_FGC;
947 tmslow &= ~B43_TMSLOW_PHYRESET;
948 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
949 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
950 msleep(1);
951 tmslow &= ~SSB_TMSLOW_FGC;
952 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
953 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
954 msleep(1);
955
956 /* Turn Analog ON */
957 b43_switch_analog(dev, 1);
958
959 macctl = b43_read32(dev, B43_MMIO_MACCTL);
960 macctl &= ~B43_MACCTL_GMODE;
961 if (flags & B43_TMSLOW_GMODE)
962 macctl |= B43_MACCTL_GMODE;
963 macctl |= B43_MACCTL_IHR_ENABLED;
964 b43_write32(dev, B43_MMIO_MACCTL, macctl);
965 }
966
967 static void handle_irq_transmit_status(struct b43_wldev *dev)
968 {
969 u32 v0, v1;
970 u16 tmp;
971 struct b43_txstatus stat;
972
973 while (1) {
974 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
975 if (!(v0 & 0x00000001))
976 break;
977 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
978
979 stat.cookie = (v0 >> 16);
980 stat.seq = (v1 & 0x0000FFFF);
981 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
982 tmp = (v0 & 0x0000FFFF);
983 stat.frame_count = ((tmp & 0xF000) >> 12);
984 stat.rts_count = ((tmp & 0x0F00) >> 8);
985 stat.supp_reason = ((tmp & 0x001C) >> 2);
986 stat.pm_indicated = !!(tmp & 0x0080);
987 stat.intermediate = !!(tmp & 0x0040);
988 stat.for_ampdu = !!(tmp & 0x0020);
989 stat.acked = !!(tmp & 0x0002);
990
991 b43_handle_txstatus(dev, &stat);
992 }
993 }
994
995 static void drain_txstatus_queue(struct b43_wldev *dev)
996 {
997 u32 dummy;
998
999 if (dev->dev->id.revision < 5)
1000 return;
1001 /* Read all entries from the microcode TXstatus FIFO
1002 * and throw them away.
1003 */
1004 while (1) {
1005 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1006 if (!(dummy & 0x00000001))
1007 break;
1008 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1009 }
1010 }
1011
1012 static u32 b43_jssi_read(struct b43_wldev *dev)
1013 {
1014 u32 val = 0;
1015
1016 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1017 val <<= 16;
1018 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1019
1020 return val;
1021 }
1022
1023 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1024 {
1025 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1026 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1027 }
1028
1029 static void b43_generate_noise_sample(struct b43_wldev *dev)
1030 {
1031 b43_jssi_write(dev, 0x7F7F7F7F);
1032 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1033 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1034 | (1 << 4));
1035 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1036 }
1037
1038 static void b43_calculate_link_quality(struct b43_wldev *dev)
1039 {
1040 /* Top half of Link Quality calculation. */
1041
1042 if (dev->noisecalc.calculation_running)
1043 return;
1044 dev->noisecalc.channel_at_start = dev->phy.channel;
1045 dev->noisecalc.calculation_running = 1;
1046 dev->noisecalc.nr_samples = 0;
1047
1048 b43_generate_noise_sample(dev);
1049 }
1050
1051 static void handle_irq_noise(struct b43_wldev *dev)
1052 {
1053 struct b43_phy *phy = &dev->phy;
1054 u16 tmp;
1055 u8 noise[4];
1056 u8 i, j;
1057 s32 average;
1058
1059 /* Bottom half of Link Quality calculation. */
1060
1061 B43_WARN_ON(!dev->noisecalc.calculation_running);
1062 if (dev->noisecalc.channel_at_start != phy->channel)
1063 goto drop_calculation;
1064 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1065 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1066 noise[2] == 0x7F || noise[3] == 0x7F)
1067 goto generate_new;
1068
1069 /* Get the noise samples. */
1070 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1071 i = dev->noisecalc.nr_samples;
1072 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1073 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1074 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1075 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1076 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1077 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1078 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1079 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1080 dev->noisecalc.nr_samples++;
1081 if (dev->noisecalc.nr_samples == 8) {
1082 /* Calculate the Link Quality by the noise samples. */
1083 average = 0;
1084 for (i = 0; i < 8; i++) {
1085 for (j = 0; j < 4; j++)
1086 average += dev->noisecalc.samples[i][j];
1087 }
1088 average /= (8 * 4);
1089 average *= 125;
1090 average += 64;
1091 average /= 128;
1092 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1093 tmp = (tmp / 128) & 0x1F;
1094 if (tmp >= 8)
1095 average += 2;
1096 else
1097 average -= 25;
1098 if (tmp == 8)
1099 average -= 72;
1100 else
1101 average -= 48;
1102
1103 dev->stats.link_noise = average;
1104 drop_calculation:
1105 dev->noisecalc.calculation_running = 0;
1106 return;
1107 }
1108 generate_new:
1109 b43_generate_noise_sample(dev);
1110 }
1111
1112 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1113 {
1114 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1115 ///TODO: PS TBTT
1116 } else {
1117 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1118 b43_power_saving_ctl_bits(dev, 0);
1119 }
1120 dev->reg124_set_0x4 = 0;
1121 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1122 dev->reg124_set_0x4 = 1;
1123 }
1124
1125 static void handle_irq_atim_end(struct b43_wldev *dev)
1126 {
1127 if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1128 return;
1129 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1130 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1131 | 0x4);
1132 }
1133
1134 static void handle_irq_pmq(struct b43_wldev *dev)
1135 {
1136 u32 tmp;
1137
1138 //TODO: AP mode.
1139
1140 while (1) {
1141 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1142 if (!(tmp & 0x00000008))
1143 break;
1144 }
1145 /* 16bit write is odd, but correct. */
1146 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1147 }
1148
1149 static void b43_write_template_common(struct b43_wldev *dev,
1150 const u8 * data, u16 size,
1151 u16 ram_offset,
1152 u16 shm_size_offset, u8 rate)
1153 {
1154 u32 i, tmp;
1155 struct b43_plcp_hdr4 plcp;
1156
1157 plcp.data = 0;
1158 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1159 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1160 ram_offset += sizeof(u32);
1161 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1162 * So leave the first two bytes of the next write blank.
1163 */
1164 tmp = (u32) (data[0]) << 16;
1165 tmp |= (u32) (data[1]) << 24;
1166 b43_ram_write(dev, ram_offset, tmp);
1167 ram_offset += sizeof(u32);
1168 for (i = 2; i < size; i += sizeof(u32)) {
1169 tmp = (u32) (data[i + 0]);
1170 if (i + 1 < size)
1171 tmp |= (u32) (data[i + 1]) << 8;
1172 if (i + 2 < size)
1173 tmp |= (u32) (data[i + 2]) << 16;
1174 if (i + 3 < size)
1175 tmp |= (u32) (data[i + 3]) << 24;
1176 b43_ram_write(dev, ram_offset + i - 2, tmp);
1177 }
1178 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1179 size + sizeof(struct b43_plcp_hdr6));
1180 }
1181
1182 static void b43_write_beacon_template(struct b43_wldev *dev,
1183 u16 ram_offset,
1184 u16 shm_size_offset, u8 rate)
1185 {
1186 int len;
1187 const u8 *data;
1188
1189 B43_WARN_ON(!dev->cached_beacon);
1190 len = min((size_t) dev->cached_beacon->len,
1191 0x200 - sizeof(struct b43_plcp_hdr6));
1192 data = (const u8 *)(dev->cached_beacon->data);
1193 b43_write_template_common(dev, data,
1194 len, ram_offset, shm_size_offset, rate);
1195 }
1196
1197 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1198 u16 shm_offset, u16 size, u8 rate)
1199 {
1200 struct b43_plcp_hdr4 plcp;
1201 u32 tmp;
1202 __le16 dur;
1203
1204 plcp.data = 0;
1205 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1206 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1207 dev->wl->if_id, size,
1208 B43_RATE_TO_BASE100KBPS(rate));
1209 /* Write PLCP in two parts and timing for packet transfer */
1210 tmp = le32_to_cpu(plcp.data);
1211 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1212 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1213 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1214 }
1215
1216 /* Instead of using custom probe response template, this function
1217 * just patches custom beacon template by:
1218 * 1) Changing packet type
1219 * 2) Patching duration field
1220 * 3) Stripping TIM
1221 */
1222 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1223 u16 * dest_size, u8 rate)
1224 {
1225 const u8 *src_data;
1226 u8 *dest_data;
1227 u16 src_size, elem_size, src_pos, dest_pos;
1228 __le16 dur;
1229 struct ieee80211_hdr *hdr;
1230
1231 B43_WARN_ON(!dev->cached_beacon);
1232 src_size = dev->cached_beacon->len;
1233 src_data = (const u8 *)dev->cached_beacon->data;
1234
1235 if (unlikely(src_size < 0x24)) {
1236 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1237 return NULL;
1238 }
1239
1240 dest_data = kmalloc(src_size, GFP_ATOMIC);
1241 if (unlikely(!dest_data))
1242 return NULL;
1243
1244 /* 0x24 is offset of first variable-len Information-Element
1245 * in beacon frame.
1246 */
1247 memcpy(dest_data, src_data, 0x24);
1248 src_pos = dest_pos = 0x24;
1249 for (; src_pos < src_size - 2; src_pos += elem_size) {
1250 elem_size = src_data[src_pos + 1] + 2;
1251 if (src_data[src_pos] != 0x05) { /* TIM */
1252 memcpy(dest_data + dest_pos, src_data + src_pos,
1253 elem_size);
1254 dest_pos += elem_size;
1255 }
1256 }
1257 *dest_size = dest_pos;
1258 hdr = (struct ieee80211_hdr *)dest_data;
1259
1260 /* Set the frame control. */
1261 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1262 IEEE80211_STYPE_PROBE_RESP);
1263 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1264 dev->wl->if_id, *dest_size,
1265 B43_RATE_TO_BASE100KBPS(rate));
1266 hdr->duration_id = dur;
1267
1268 return dest_data;
1269 }
1270
1271 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1272 u16 ram_offset,
1273 u16 shm_size_offset, u8 rate)
1274 {
1275 u8 *probe_resp_data;
1276 u16 size;
1277
1278 B43_WARN_ON(!dev->cached_beacon);
1279 size = dev->cached_beacon->len;
1280 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1281 if (unlikely(!probe_resp_data))
1282 return;
1283
1284 /* Looks like PLCP headers plus packet timings are stored for
1285 * all possible basic rates
1286 */
1287 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1288 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1289 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1290 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1291
1292 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1293 b43_write_template_common(dev, probe_resp_data,
1294 size, ram_offset, shm_size_offset, rate);
1295 kfree(probe_resp_data);
1296 }
1297
1298 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1299 struct sk_buff *beacon)
1300 {
1301 if (dev->cached_beacon)
1302 kfree_skb(dev->cached_beacon);
1303 dev->cached_beacon = beacon;
1304
1305 return 0;
1306 }
1307
1308 static void b43_update_templates(struct b43_wldev *dev)
1309 {
1310 u32 status;
1311
1312 B43_WARN_ON(!dev->cached_beacon);
1313
1314 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1315 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1316 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1317
1318 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1319 status |= 0x03;
1320 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1321 }
1322
1323 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1324 {
1325 int err;
1326
1327 err = b43_refresh_cached_beacon(dev, beacon);
1328 if (unlikely(err))
1329 return;
1330 b43_update_templates(dev);
1331 }
1332
1333 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1334 {
1335 u32 tmp;
1336 u16 i, len;
1337
1338 len = min((u16) ssid_len, (u16) 0x100);
1339 for (i = 0; i < len; i += sizeof(u32)) {
1340 tmp = (u32) (ssid[i + 0]);
1341 if (i + 1 < len)
1342 tmp |= (u32) (ssid[i + 1]) << 8;
1343 if (i + 2 < len)
1344 tmp |= (u32) (ssid[i + 2]) << 16;
1345 if (i + 3 < len)
1346 tmp |= (u32) (ssid[i + 3]) << 24;
1347 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1348 }
1349 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1350 }
1351
1352 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1353 {
1354 b43_time_lock(dev);
1355 if (dev->dev->id.revision >= 3) {
1356 b43_write32(dev, 0x188, (beacon_int << 16));
1357 } else {
1358 b43_write16(dev, 0x606, (beacon_int >> 6));
1359 b43_write16(dev, 0x610, beacon_int);
1360 }
1361 b43_time_unlock(dev);
1362 }
1363
1364 static void handle_irq_beacon(struct b43_wldev *dev)
1365 {
1366 u32 status;
1367
1368 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1369 return;
1370
1371 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1372 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1373
1374 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1375 /* ACK beacon IRQ. */
1376 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1377 dev->irq_savedstate |= B43_IRQ_BEACON;
1378 if (dev->cached_beacon)
1379 kfree_skb(dev->cached_beacon);
1380 dev->cached_beacon = NULL;
1381 return;
1382 }
1383 if (!(status & 0x1)) {
1384 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1385 status |= 0x1;
1386 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1387 }
1388 if (!(status & 0x2)) {
1389 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1390 status |= 0x2;
1391 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1392 }
1393 }
1394
1395 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1396 {
1397 //TODO
1398 }
1399
1400 /* Interrupt handler bottom-half */
1401 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1402 {
1403 u32 reason;
1404 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1405 u32 merged_dma_reason = 0;
1406 int i;
1407 unsigned long flags;
1408
1409 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1410
1411 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1412
1413 reason = dev->irq_reason;
1414 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1415 dma_reason[i] = dev->dma_reason[i];
1416 merged_dma_reason |= dma_reason[i];
1417 }
1418
1419 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1420 b43err(dev->wl, "MAC transmission error\n");
1421
1422 if (unlikely(reason & B43_IRQ_PHY_TXERR))
1423 b43err(dev->wl, "PHY transmission error\n");
1424
1425 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1426 B43_DMAIRQ_NONFATALMASK))) {
1427 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1428 b43err(dev->wl, "Fatal DMA error: "
1429 "0x%08X, 0x%08X, 0x%08X, "
1430 "0x%08X, 0x%08X, 0x%08X\n",
1431 dma_reason[0], dma_reason[1],
1432 dma_reason[2], dma_reason[3],
1433 dma_reason[4], dma_reason[5]);
1434 b43_controller_restart(dev, "DMA error");
1435 mmiowb();
1436 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1437 return;
1438 }
1439 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1440 b43err(dev->wl, "DMA error: "
1441 "0x%08X, 0x%08X, 0x%08X, "
1442 "0x%08X, 0x%08X, 0x%08X\n",
1443 dma_reason[0], dma_reason[1],
1444 dma_reason[2], dma_reason[3],
1445 dma_reason[4], dma_reason[5]);
1446 }
1447 }
1448
1449 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1450 handle_irq_ucode_debug(dev);
1451 if (reason & B43_IRQ_TBTT_INDI)
1452 handle_irq_tbtt_indication(dev);
1453 if (reason & B43_IRQ_ATIM_END)
1454 handle_irq_atim_end(dev);
1455 if (reason & B43_IRQ_BEACON)
1456 handle_irq_beacon(dev);
1457 if (reason & B43_IRQ_PMQ)
1458 handle_irq_pmq(dev);
1459 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1460 ;/* TODO */
1461 if (reason & B43_IRQ_NOISESAMPLE_OK)
1462 handle_irq_noise(dev);
1463
1464 /* Check the DMA reason registers for received data. */
1465 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1466 if (b43_using_pio(dev))
1467 b43_pio_rx(dev->pio.queue0);
1468 else
1469 b43_dma_rx(dev->dma.rx_ring0);
1470 }
1471 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1472 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1473 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1474 if (b43_using_pio(dev))
1475 b43_pio_rx(dev->pio.queue3);
1476 else
1477 b43_dma_rx(dev->dma.rx_ring3);
1478 }
1479 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1480 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1481
1482 if (reason & B43_IRQ_TX_OK)
1483 handle_irq_transmit_status(dev);
1484
1485 b43_interrupt_enable(dev, dev->irq_savedstate);
1486 mmiowb();
1487 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1488 }
1489
1490 static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1491 {
1492 u16 rxctl;
1493
1494 rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1495 if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1496 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1497 else
1498 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1499 }
1500
1501 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1502 {
1503 if (b43_using_pio(dev) &&
1504 (dev->dev->id.revision < 3) &&
1505 (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1506 /* Apply a PIO specific workaround to the dma_reasons */
1507 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1508 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1509 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1510 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1511 }
1512
1513 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1514
1515 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1516 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1517 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1518 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1519 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1520 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1521 }
1522
1523 /* Interrupt handler top-half */
1524 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1525 {
1526 irqreturn_t ret = IRQ_NONE;
1527 struct b43_wldev *dev = dev_id;
1528 u32 reason;
1529
1530 if (!dev)
1531 return IRQ_NONE;
1532
1533 spin_lock(&dev->wl->irq_lock);
1534
1535 if (b43_status(dev) < B43_STAT_STARTED)
1536 goto out;
1537 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1538 if (reason == 0xffffffff) /* shared IRQ */
1539 goto out;
1540 ret = IRQ_HANDLED;
1541 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1542 if (!reason)
1543 goto out;
1544
1545 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1546 & 0x0001DC00;
1547 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1548 & 0x0000DC00;
1549 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1550 & 0x0000DC00;
1551 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1552 & 0x0001DC00;
1553 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1554 & 0x0000DC00;
1555 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1556 & 0x0000DC00;
1557
1558 b43_interrupt_ack(dev, reason);
1559 /* disable all IRQs. They are enabled again in the bottom half. */
1560 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1561 /* save the reason code and call our bottom half. */
1562 dev->irq_reason = reason;
1563 tasklet_schedule(&dev->isr_tasklet);
1564 out:
1565 mmiowb();
1566 spin_unlock(&dev->wl->irq_lock);
1567
1568 return ret;
1569 }
1570
1571 static void b43_release_firmware(struct b43_wldev *dev)
1572 {
1573 release_firmware(dev->fw.ucode);
1574 dev->fw.ucode = NULL;
1575 release_firmware(dev->fw.pcm);
1576 dev->fw.pcm = NULL;
1577 release_firmware(dev->fw.initvals);
1578 dev->fw.initvals = NULL;
1579 release_firmware(dev->fw.initvals_band);
1580 dev->fw.initvals_band = NULL;
1581 }
1582
1583 static void b43_print_fw_helptext(struct b43_wl *wl)
1584 {
1585 b43err(wl, "You must go to "
1586 "http://linuxwireless.org/en/users/Drivers/bcm43xx#devicefirmware "
1587 "and download the correct firmware (version 4).\n");
1588 }
1589
1590 static int do_request_fw(struct b43_wldev *dev,
1591 const char *name,
1592 const struct firmware **fw)
1593 {
1594 char path[sizeof(modparam_fwpostfix) + 32];
1595 struct b43_fw_header *hdr;
1596 u32 size;
1597 int err;
1598
1599 if (!name)
1600 return 0;
1601
1602 snprintf(path, ARRAY_SIZE(path),
1603 "b43%s/%s.fw",
1604 modparam_fwpostfix, name);
1605 err = request_firmware(fw, path, dev->dev->dev);
1606 if (err) {
1607 b43err(dev->wl, "Firmware file \"%s\" not found "
1608 "or load failed.\n", path);
1609 return err;
1610 }
1611 if ((*fw)->size < sizeof(struct b43_fw_header))
1612 goto err_format;
1613 hdr = (struct b43_fw_header *)((*fw)->data);
1614 switch (hdr->type) {
1615 case B43_FW_TYPE_UCODE:
1616 case B43_FW_TYPE_PCM:
1617 size = be32_to_cpu(hdr->size);
1618 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1619 goto err_format;
1620 /* fallthrough */
1621 case B43_FW_TYPE_IV:
1622 if (hdr->ver != 1)
1623 goto err_format;
1624 break;
1625 default:
1626 goto err_format;
1627 }
1628
1629 return err;
1630
1631 err_format:
1632 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1633 return -EPROTO;
1634 }
1635
1636 static int b43_request_firmware(struct b43_wldev *dev)
1637 {
1638 struct b43_firmware *fw = &dev->fw;
1639 const u8 rev = dev->dev->id.revision;
1640 const char *filename;
1641 u32 tmshigh;
1642 int err;
1643
1644 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1645 if (!fw->ucode) {
1646 if ((rev >= 5) && (rev <= 10))
1647 filename = "ucode5";
1648 else if ((rev >= 11) && (rev <= 12))
1649 filename = "ucode11";
1650 else if (rev >= 13)
1651 filename = "ucode13";
1652 else
1653 goto err_no_ucode;
1654 err = do_request_fw(dev, filename, &fw->ucode);
1655 if (err)
1656 goto err_load;
1657 }
1658 if (!fw->pcm) {
1659 if ((rev >= 5) && (rev <= 10))
1660 filename = "pcm5";
1661 else if (rev >= 11)
1662 filename = NULL;
1663 else
1664 goto err_no_pcm;
1665 err = do_request_fw(dev, filename, &fw->pcm);
1666 if (err)
1667 goto err_load;
1668 }
1669 if (!fw->initvals) {
1670 switch (dev->phy.type) {
1671 case B43_PHYTYPE_A:
1672 if ((rev >= 5) && (rev <= 10)) {
1673 if (tmshigh & B43_TMSHIGH_GPHY)
1674 filename = "a0g1initvals5";
1675 else
1676 filename = "a0g0initvals5";
1677 } else
1678 goto err_no_initvals;
1679 break;
1680 case B43_PHYTYPE_G:
1681 if ((rev >= 5) && (rev <= 10))
1682 filename = "b0g0initvals5";
1683 else if (rev >= 13)
1684 filename = "lp0initvals13";
1685 else
1686 goto err_no_initvals;
1687 break;
1688 default:
1689 goto err_no_initvals;
1690 }
1691 err = do_request_fw(dev, filename, &fw->initvals);
1692 if (err)
1693 goto err_load;
1694 }
1695 if (!fw->initvals_band) {
1696 switch (dev->phy.type) {
1697 case B43_PHYTYPE_A:
1698 if ((rev >= 5) && (rev <= 10)) {
1699 if (tmshigh & B43_TMSHIGH_GPHY)
1700 filename = "a0g1bsinitvals5";
1701 else
1702 filename = "a0g0bsinitvals5";
1703 } else if (rev >= 11)
1704 filename = NULL;
1705 else
1706 goto err_no_initvals;
1707 break;
1708 case B43_PHYTYPE_G:
1709 if ((rev >= 5) && (rev <= 10))
1710 filename = "b0g0bsinitvals5";
1711 else if (rev >= 11)
1712 filename = NULL;
1713 else
1714 goto err_no_initvals;
1715 break;
1716 default:
1717 goto err_no_initvals;
1718 }
1719 err = do_request_fw(dev, filename, &fw->initvals_band);
1720 if (err)
1721 goto err_load;
1722 }
1723
1724 return 0;
1725
1726 err_load:
1727 b43_print_fw_helptext(dev->wl);
1728 goto error;
1729
1730 err_no_ucode:
1731 err = -ENODEV;
1732 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1733 goto error;
1734
1735 err_no_pcm:
1736 err = -ENODEV;
1737 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1738 goto error;
1739
1740 err_no_initvals:
1741 err = -ENODEV;
1742 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1743 "core rev %u\n", dev->phy.type, rev);
1744 goto error;
1745
1746 error:
1747 b43_release_firmware(dev);
1748 return err;
1749 }
1750
1751 static int b43_upload_microcode(struct b43_wldev *dev)
1752 {
1753 const size_t hdr_len = sizeof(struct b43_fw_header);
1754 const __be32 *data;
1755 unsigned int i, len;
1756 u16 fwrev, fwpatch, fwdate, fwtime;
1757 u32 tmp;
1758 int err = 0;
1759
1760 /* Upload Microcode. */
1761 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1762 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1763 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1764 for (i = 0; i < len; i++) {
1765 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1766 udelay(10);
1767 }
1768
1769 if (dev->fw.pcm) {
1770 /* Upload PCM data. */
1771 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1772 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1773 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1774 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1775 /* No need for autoinc bit in SHM_HW */
1776 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1777 for (i = 0; i < len; i++) {
1778 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1779 udelay(10);
1780 }
1781 }
1782
1783 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1784 b43_write32(dev, B43_MMIO_MACCTL,
1785 B43_MACCTL_PSM_RUN |
1786 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1787
1788 /* Wait for the microcode to load and respond */
1789 i = 0;
1790 while (1) {
1791 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1792 if (tmp == B43_IRQ_MAC_SUSPENDED)
1793 break;
1794 i++;
1795 if (i >= 50) {
1796 b43err(dev->wl, "Microcode not responding\n");
1797 b43_print_fw_helptext(dev->wl);
1798 err = -ENODEV;
1799 goto out;
1800 }
1801 udelay(10);
1802 }
1803 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1804
1805 /* Get and check the revisions. */
1806 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1807 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1808 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1809 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1810
1811 if (fwrev <= 0x128) {
1812 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1813 "binary drivers older than version 4.x is unsupported. "
1814 "You must upgrade your firmware files.\n");
1815 b43_print_fw_helptext(dev->wl);
1816 b43_write32(dev, B43_MMIO_MACCTL, 0);
1817 err = -EOPNOTSUPP;
1818 goto out;
1819 }
1820 b43dbg(dev->wl, "Loading firmware version %u.%u "
1821 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1822 fwrev, fwpatch,
1823 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1824 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1825
1826 dev->fw.rev = fwrev;
1827 dev->fw.patch = fwpatch;
1828
1829 out:
1830 return err;
1831 }
1832
1833 static int b43_write_initvals(struct b43_wldev *dev,
1834 const struct b43_iv *ivals,
1835 size_t count,
1836 size_t array_size)
1837 {
1838 const struct b43_iv *iv;
1839 u16 offset;
1840 size_t i;
1841 bool bit32;
1842
1843 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1844 iv = ivals;
1845 for (i = 0; i < count; i++) {
1846 if (array_size < sizeof(iv->offset_size))
1847 goto err_format;
1848 array_size -= sizeof(iv->offset_size);
1849 offset = be16_to_cpu(iv->offset_size);
1850 bit32 = !!(offset & B43_IV_32BIT);
1851 offset &= B43_IV_OFFSET_MASK;
1852 if (offset >= 0x1000)
1853 goto err_format;
1854 if (bit32) {
1855 u32 value;
1856
1857 if (array_size < sizeof(iv->data.d32))
1858 goto err_format;
1859 array_size -= sizeof(iv->data.d32);
1860
1861 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1862 b43_write32(dev, offset, value);
1863
1864 iv = (const struct b43_iv *)((const uint8_t *)iv +
1865 sizeof(__be16) +
1866 sizeof(__be32));
1867 } else {
1868 u16 value;
1869
1870 if (array_size < sizeof(iv->data.d16))
1871 goto err_format;
1872 array_size -= sizeof(iv->data.d16);
1873
1874 value = be16_to_cpu(iv->data.d16);
1875 b43_write16(dev, offset, value);
1876
1877 iv = (const struct b43_iv *)((const uint8_t *)iv +
1878 sizeof(__be16) +
1879 sizeof(__be16));
1880 }
1881 }
1882 if (array_size)
1883 goto err_format;
1884
1885 return 0;
1886
1887 err_format:
1888 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1889 b43_print_fw_helptext(dev->wl);
1890
1891 return -EPROTO;
1892 }
1893
1894 static int b43_upload_initvals(struct b43_wldev *dev)
1895 {
1896 const size_t hdr_len = sizeof(struct b43_fw_header);
1897 const struct b43_fw_header *hdr;
1898 struct b43_firmware *fw = &dev->fw;
1899 const struct b43_iv *ivals;
1900 size_t count;
1901 int err;
1902
1903 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1904 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1905 count = be32_to_cpu(hdr->size);
1906 err = b43_write_initvals(dev, ivals, count,
1907 fw->initvals->size - hdr_len);
1908 if (err)
1909 goto out;
1910 if (fw->initvals_band) {
1911 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1912 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1913 count = be32_to_cpu(hdr->size);
1914 err = b43_write_initvals(dev, ivals, count,
1915 fw->initvals_band->size - hdr_len);
1916 if (err)
1917 goto out;
1918 }
1919 out:
1920
1921 return err;
1922 }
1923
1924 /* Initialize the GPIOs
1925 * http://bcm-specs.sipsolutions.net/GPIO
1926 */
1927 static int b43_gpio_init(struct b43_wldev *dev)
1928 {
1929 struct ssb_bus *bus = dev->dev->bus;
1930 struct ssb_device *gpiodev, *pcidev = NULL;
1931 u32 mask, set;
1932
1933 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1934 & ~B43_MACCTL_GPOUTSMSK);
1935
1936 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1937 | 0x000F);
1938
1939 mask = 0x0000001F;
1940 set = 0x0000000F;
1941 if (dev->dev->bus->chip_id == 0x4301) {
1942 mask |= 0x0060;
1943 set |= 0x0060;
1944 }
1945 if (0 /* FIXME: conditional unknown */ ) {
1946 b43_write16(dev, B43_MMIO_GPIO_MASK,
1947 b43_read16(dev, B43_MMIO_GPIO_MASK)
1948 | 0x0100);
1949 mask |= 0x0180;
1950 set |= 0x0180;
1951 }
1952 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) {
1953 b43_write16(dev, B43_MMIO_GPIO_MASK,
1954 b43_read16(dev, B43_MMIO_GPIO_MASK)
1955 | 0x0200);
1956 mask |= 0x0200;
1957 set |= 0x0200;
1958 }
1959 if (dev->dev->id.revision >= 2)
1960 mask |= 0x0010; /* FIXME: This is redundant. */
1961
1962 #ifdef CONFIG_SSB_DRIVER_PCICORE
1963 pcidev = bus->pcicore.dev;
1964 #endif
1965 gpiodev = bus->chipco.dev ? : pcidev;
1966 if (!gpiodev)
1967 return 0;
1968 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1969 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1970 & mask) | set);
1971
1972 return 0;
1973 }
1974
1975 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1976 static void b43_gpio_cleanup(struct b43_wldev *dev)
1977 {
1978 struct ssb_bus *bus = dev->dev->bus;
1979 struct ssb_device *gpiodev, *pcidev = NULL;
1980
1981 #ifdef CONFIG_SSB_DRIVER_PCICORE
1982 pcidev = bus->pcicore.dev;
1983 #endif
1984 gpiodev = bus->chipco.dev ? : pcidev;
1985 if (!gpiodev)
1986 return;
1987 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1988 }
1989
1990 /* http://bcm-specs.sipsolutions.net/EnableMac */
1991 void b43_mac_enable(struct b43_wldev *dev)
1992 {
1993 dev->mac_suspended--;
1994 B43_WARN_ON(dev->mac_suspended < 0);
1995 B43_WARN_ON(irqs_disabled());
1996 if (dev->mac_suspended == 0) {
1997 b43_write32(dev, B43_MMIO_MACCTL,
1998 b43_read32(dev, B43_MMIO_MACCTL)
1999 | B43_MACCTL_ENABLED);
2000 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2001 B43_IRQ_MAC_SUSPENDED);
2002 /* Commit writes */
2003 b43_read32(dev, B43_MMIO_MACCTL);
2004 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2005 b43_power_saving_ctl_bits(dev, 0);
2006
2007 /* Re-enable IRQs. */
2008 spin_lock_irq(&dev->wl->irq_lock);
2009 b43_interrupt_enable(dev, dev->irq_savedstate);
2010 spin_unlock_irq(&dev->wl->irq_lock);
2011 }
2012 }
2013
2014 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2015 void b43_mac_suspend(struct b43_wldev *dev)
2016 {
2017 int i;
2018 u32 tmp;
2019
2020 might_sleep();
2021 B43_WARN_ON(irqs_disabled());
2022 B43_WARN_ON(dev->mac_suspended < 0);
2023
2024 if (dev->mac_suspended == 0) {
2025 /* Mask IRQs before suspending MAC. Otherwise
2026 * the MAC stays busy and won't suspend. */
2027 spin_lock_irq(&dev->wl->irq_lock);
2028 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2029 spin_unlock_irq(&dev->wl->irq_lock);
2030 b43_synchronize_irq(dev);
2031 dev->irq_savedstate = tmp;
2032
2033 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2034 b43_write32(dev, B43_MMIO_MACCTL,
2035 b43_read32(dev, B43_MMIO_MACCTL)
2036 & ~B43_MACCTL_ENABLED);
2037 /* force pci to flush the write */
2038 b43_read32(dev, B43_MMIO_MACCTL);
2039 for (i = 40; i; i--) {
2040 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2041 if (tmp & B43_IRQ_MAC_SUSPENDED)
2042 goto out;
2043 msleep(1);
2044 }
2045 b43err(dev->wl, "MAC suspend failed\n");
2046 }
2047 out:
2048 dev->mac_suspended++;
2049 }
2050
2051 static void b43_adjust_opmode(struct b43_wldev *dev)
2052 {
2053 struct b43_wl *wl = dev->wl;
2054 u32 ctl;
2055 u16 cfp_pretbtt;
2056
2057 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2058 /* Reset status to STA infrastructure mode. */
2059 ctl &= ~B43_MACCTL_AP;
2060 ctl &= ~B43_MACCTL_KEEP_CTL;
2061 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2062 ctl &= ~B43_MACCTL_KEEP_BAD;
2063 ctl &= ~B43_MACCTL_PROMISC;
2064 ctl &= ~B43_MACCTL_BEACPROMISC;
2065 ctl |= B43_MACCTL_INFRA;
2066
2067 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2068 ctl |= B43_MACCTL_AP;
2069 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2070 ctl &= ~B43_MACCTL_INFRA;
2071
2072 if (wl->filter_flags & FIF_CONTROL)
2073 ctl |= B43_MACCTL_KEEP_CTL;
2074 if (wl->filter_flags & FIF_FCSFAIL)
2075 ctl |= B43_MACCTL_KEEP_BAD;
2076 if (wl->filter_flags & FIF_PLCPFAIL)
2077 ctl |= B43_MACCTL_KEEP_BADPLCP;
2078 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2079 ctl |= B43_MACCTL_PROMISC;
2080 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2081 ctl |= B43_MACCTL_BEACPROMISC;
2082
2083 /* Workaround: On old hardware the HW-MAC-address-filter
2084 * doesn't work properly, so always run promisc in filter
2085 * it in software. */
2086 if (dev->dev->id.revision <= 4)
2087 ctl |= B43_MACCTL_PROMISC;
2088
2089 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2090
2091 cfp_pretbtt = 2;
2092 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2093 if (dev->dev->bus->chip_id == 0x4306 &&
2094 dev->dev->bus->chip_rev == 3)
2095 cfp_pretbtt = 100;
2096 else
2097 cfp_pretbtt = 50;
2098 }
2099 b43_write16(dev, 0x612, cfp_pretbtt);
2100 }
2101
2102 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2103 {
2104 u16 offset;
2105
2106 if (is_ofdm) {
2107 offset = 0x480;
2108 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2109 } else {
2110 offset = 0x4C0;
2111 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2112 }
2113 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2114 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2115 }
2116
2117 static void b43_rate_memory_init(struct b43_wldev *dev)
2118 {
2119 switch (dev->phy.type) {
2120 case B43_PHYTYPE_A:
2121 case B43_PHYTYPE_G:
2122 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2123 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2124 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2125 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2126 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2127 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2128 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2129 if (dev->phy.type == B43_PHYTYPE_A)
2130 break;
2131 /* fallthrough */
2132 case B43_PHYTYPE_B:
2133 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2134 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2135 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2136 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2137 break;
2138 default:
2139 B43_WARN_ON(1);
2140 }
2141 }
2142
2143 /* Set the TX-Antenna for management frames sent by firmware. */
2144 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2145 {
2146 u16 ant = 0;
2147 u16 tmp;
2148
2149 switch (antenna) {
2150 case B43_ANTENNA0:
2151 ant |= B43_TX4_PHY_ANT0;
2152 break;
2153 case B43_ANTENNA1:
2154 ant |= B43_TX4_PHY_ANT1;
2155 break;
2156 case B43_ANTENNA_AUTO:
2157 ant |= B43_TX4_PHY_ANTLAST;
2158 break;
2159 default:
2160 B43_WARN_ON(1);
2161 }
2162
2163 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2164
2165 /* For Beacons */
2166 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2167 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2168 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2169 /* For ACK/CTS */
2170 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2171 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2172 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2173 /* For Probe Resposes */
2174 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2175 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2176 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2177 }
2178
2179 /* This is the opposite of b43_chip_init() */
2180 static void b43_chip_exit(struct b43_wldev *dev)
2181 {
2182 b43_radio_turn_off(dev, 1);
2183 b43_leds_exit(dev);
2184 b43_gpio_cleanup(dev);
2185 /* firmware is released later */
2186 }
2187
2188 /* Initialize the chip
2189 * http://bcm-specs.sipsolutions.net/ChipInit
2190 */
2191 static int b43_chip_init(struct b43_wldev *dev)
2192 {
2193 struct b43_phy *phy = &dev->phy;
2194 int err, tmp;
2195 u32 value32;
2196 u16 value16;
2197
2198 b43_write32(dev, B43_MMIO_MACCTL,
2199 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2200
2201 err = b43_request_firmware(dev);
2202 if (err)
2203 goto out;
2204 err = b43_upload_microcode(dev);
2205 if (err)
2206 goto out; /* firmware is released later */
2207
2208 err = b43_gpio_init(dev);
2209 if (err)
2210 goto out; /* firmware is released later */
2211 b43_leds_init(dev);
2212
2213 err = b43_upload_initvals(dev);
2214 if (err)
2215 goto err_leds_exit;
2216 b43_radio_turn_on(dev);
2217
2218 b43_write16(dev, 0x03E6, 0x0000);
2219 err = b43_phy_init(dev);
2220 if (err)
2221 goto err_radio_off;
2222
2223 /* Select initial Interference Mitigation. */
2224 tmp = phy->interfmode;
2225 phy->interfmode = B43_INTERFMODE_NONE;
2226 b43_radio_set_interference_mitigation(dev, tmp);
2227
2228 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2229 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2230
2231 if (phy->type == B43_PHYTYPE_B) {
2232 value16 = b43_read16(dev, 0x005E);
2233 value16 |= 0x0004;
2234 b43_write16(dev, 0x005E, value16);
2235 }
2236 b43_write32(dev, 0x0100, 0x01000000);
2237 if (dev->dev->id.revision < 5)
2238 b43_write32(dev, 0x010C, 0x01000000);
2239
2240 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2241 & ~B43_MACCTL_INFRA);
2242 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2243 | B43_MACCTL_INFRA);
2244
2245 if (b43_using_pio(dev)) {
2246 b43_write32(dev, 0x0210, 0x00000100);
2247 b43_write32(dev, 0x0230, 0x00000100);
2248 b43_write32(dev, 0x0250, 0x00000100);
2249 b43_write32(dev, 0x0270, 0x00000100);
2250 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2251 }
2252
2253 /* Probe Response Timeout value */
2254 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2255 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2256
2257 /* Initially set the wireless operation mode. */
2258 b43_adjust_opmode(dev);
2259
2260 if (dev->dev->id.revision < 3) {
2261 b43_write16(dev, 0x060E, 0x0000);
2262 b43_write16(dev, 0x0610, 0x8000);
2263 b43_write16(dev, 0x0604, 0x0000);
2264 b43_write16(dev, 0x0606, 0x0200);
2265 } else {
2266 b43_write32(dev, 0x0188, 0x80000000);
2267 b43_write32(dev, 0x018C, 0x02000000);
2268 }
2269 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2270 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2271 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2272 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2273 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2274 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2275 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2276
2277 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2278 value32 |= 0x00100000;
2279 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2280
2281 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2282 dev->dev->bus->chipco.fast_pwrup_delay);
2283
2284 err = 0;
2285 b43dbg(dev->wl, "Chip initialized\n");
2286 out:
2287 return err;
2288
2289 err_radio_off:
2290 b43_radio_turn_off(dev, 1);
2291 err_leds_exit:
2292 b43_leds_exit(dev);
2293 b43_gpio_cleanup(dev);
2294 return err;
2295 }
2296
2297 static void b43_periodic_every120sec(struct b43_wldev *dev)
2298 {
2299 struct b43_phy *phy = &dev->phy;
2300
2301 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2302 return;
2303
2304 b43_mac_suspend(dev);
2305 b43_lo_g_measure(dev);
2306 b43_mac_enable(dev);
2307 if (b43_has_hardware_pctl(phy))
2308 b43_lo_g_ctl_mark_all_unused(dev);
2309 }
2310
2311 static void b43_periodic_every60sec(struct b43_wldev *dev)
2312 {
2313 struct b43_phy *phy = &dev->phy;
2314
2315 if (!b43_has_hardware_pctl(phy))
2316 b43_lo_g_ctl_mark_all_unused(dev);
2317 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
2318 b43_mac_suspend(dev);
2319 b43_calc_nrssi_slope(dev);
2320 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2321 u8 old_chan = phy->channel;
2322
2323 /* VCO Calibration */
2324 if (old_chan >= 8)
2325 b43_radio_selectchannel(dev, 1, 0);
2326 else
2327 b43_radio_selectchannel(dev, 13, 0);
2328 b43_radio_selectchannel(dev, old_chan, 0);
2329 }
2330 b43_mac_enable(dev);
2331 }
2332 }
2333
2334 static void b43_periodic_every30sec(struct b43_wldev *dev)
2335 {
2336 /* Update device statistics. */
2337 b43_calculate_link_quality(dev);
2338 }
2339
2340 static void b43_periodic_every15sec(struct b43_wldev *dev)
2341 {
2342 struct b43_phy *phy = &dev->phy;
2343
2344 if (phy->type == B43_PHYTYPE_G) {
2345 //TODO: update_aci_moving_average
2346 if (phy->aci_enable && phy->aci_wlan_automatic) {
2347 b43_mac_suspend(dev);
2348 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2349 if (0 /*TODO: bunch of conditions */ ) {
2350 b43_radio_set_interference_mitigation
2351 (dev, B43_INTERFMODE_MANUALWLAN);
2352 }
2353 } else if (1 /*TODO*/) {
2354 /*
2355 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2356 b43_radio_set_interference_mitigation(dev,
2357 B43_INTERFMODE_NONE);
2358 }
2359 */
2360 }
2361 b43_mac_enable(dev);
2362 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2363 phy->rev == 1) {
2364 //TODO: implement rev1 workaround
2365 }
2366 }
2367 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2368 //TODO for APHY (temperature?)
2369 }
2370
2371 static void do_periodic_work(struct b43_wldev *dev)
2372 {
2373 unsigned int state;
2374
2375 state = dev->periodic_state;
2376 if (state % 8 == 0)
2377 b43_periodic_every120sec(dev);
2378 if (state % 4 == 0)
2379 b43_periodic_every60sec(dev);
2380 if (state % 2 == 0)
2381 b43_periodic_every30sec(dev);
2382 b43_periodic_every15sec(dev);
2383 }
2384
2385 /* Periodic work locking policy:
2386 * The whole periodic work handler is protected by
2387 * wl->mutex. If another lock is needed somewhere in the
2388 * pwork callchain, it's aquired in-place, where it's needed.
2389 */
2390 static void b43_periodic_work_handler(struct work_struct *work)
2391 {
2392 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2393 periodic_work.work);
2394 struct b43_wl *wl = dev->wl;
2395 unsigned long delay;
2396
2397 mutex_lock(&wl->mutex);
2398
2399 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2400 goto out;
2401 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2402 goto out_requeue;
2403
2404 do_periodic_work(dev);
2405
2406 dev->periodic_state++;
2407 out_requeue:
2408 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2409 delay = msecs_to_jiffies(50);
2410 else
2411 delay = round_jiffies_relative(HZ * 15);
2412 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2413 out:
2414 mutex_unlock(&wl->mutex);
2415 }
2416
2417 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2418 {
2419 struct delayed_work *work = &dev->periodic_work;
2420
2421 dev->periodic_state = 0;
2422 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2423 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2424 }
2425
2426 /* Validate access to the chip (SHM) */
2427 static int b43_validate_chipaccess(struct b43_wldev *dev)
2428 {
2429 u32 value;
2430 u32 shm_backup;
2431
2432 shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2433 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2434 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2435 goto error;
2436 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2437 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2438 goto error;
2439 b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2440
2441 value = b43_read32(dev, B43_MMIO_MACCTL);
2442 if ((value | B43_MACCTL_GMODE) !=
2443 (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2444 goto error;
2445
2446 value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2447 if (value)
2448 goto error;
2449
2450 return 0;
2451 error:
2452 b43err(dev->wl, "Failed to validate the chipaccess\n");
2453 return -ENODEV;
2454 }
2455
2456 static void b43_security_init(struct b43_wldev *dev)
2457 {
2458 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2459 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2460 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2461 /* KTP is a word address, but we address SHM bytewise.
2462 * So multiply by two.
2463 */
2464 dev->ktp *= 2;
2465 if (dev->dev->id.revision >= 5) {
2466 /* Number of RCMTA address slots */
2467 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2468 }
2469 b43_clear_keys(dev);
2470 }
2471
2472 static int b43_rng_read(struct hwrng *rng, u32 * data)
2473 {
2474 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2475 unsigned long flags;
2476
2477 /* Don't take wl->mutex here, as it could deadlock with
2478 * hwrng internal locking. It's not needed to take
2479 * wl->mutex here, anyway. */
2480
2481 spin_lock_irqsave(&wl->irq_lock, flags);
2482 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2483 spin_unlock_irqrestore(&wl->irq_lock, flags);
2484
2485 return (sizeof(u16));
2486 }
2487
2488 static void b43_rng_exit(struct b43_wl *wl)
2489 {
2490 if (wl->rng_initialized)
2491 hwrng_unregister(&wl->rng);
2492 }
2493
2494 static int b43_rng_init(struct b43_wl *wl)
2495 {
2496 int err;
2497
2498 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2499 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2500 wl->rng.name = wl->rng_name;
2501 wl->rng.data_read = b43_rng_read;
2502 wl->rng.priv = (unsigned long)wl;
2503 wl->rng_initialized = 1;
2504 err = hwrng_register(&wl->rng);
2505 if (err) {
2506 wl->rng_initialized = 0;
2507 b43err(wl, "Failed to register the random "
2508 "number generator (%d)\n", err);
2509 }
2510
2511 return err;
2512 }
2513
2514 static int b43_tx(struct ieee80211_hw *hw,
2515 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2516 {
2517 struct b43_wl *wl = hw_to_b43_wl(hw);
2518 struct b43_wldev *dev = wl->current_dev;
2519 int err = -ENODEV;
2520 unsigned long flags;
2521
2522 if (unlikely(!dev))
2523 goto out;
2524 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2525 goto out;
2526 /* DMA-TX is done without a global lock. */
2527 if (b43_using_pio(dev)) {
2528 spin_lock_irqsave(&wl->irq_lock, flags);
2529 err = b43_pio_tx(dev, skb, ctl);
2530 spin_unlock_irqrestore(&wl->irq_lock, flags);
2531 } else
2532 err = b43_dma_tx(dev, skb, ctl);
2533 out:
2534 if (unlikely(err))
2535 return NETDEV_TX_BUSY;
2536 return NETDEV_TX_OK;
2537 }
2538
2539 static int b43_conf_tx(struct ieee80211_hw *hw,
2540 int queue,
2541 const struct ieee80211_tx_queue_params *params)
2542 {
2543 return 0;
2544 }
2545
2546 static int b43_get_tx_stats(struct ieee80211_hw *hw,
2547 struct ieee80211_tx_queue_stats *stats)
2548 {
2549 struct b43_wl *wl = hw_to_b43_wl(hw);
2550 struct b43_wldev *dev = wl->current_dev;
2551 unsigned long flags;
2552 int err = -ENODEV;
2553
2554 if (!dev)
2555 goto out;
2556 spin_lock_irqsave(&wl->irq_lock, flags);
2557 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2558 if (b43_using_pio(dev))
2559 b43_pio_get_tx_stats(dev, stats);
2560 else
2561 b43_dma_get_tx_stats(dev, stats);
2562 err = 0;
2563 }
2564 spin_unlock_irqrestore(&wl->irq_lock, flags);
2565 out:
2566 return err;
2567 }
2568
2569 static int b43_get_stats(struct ieee80211_hw *hw,
2570 struct ieee80211_low_level_stats *stats)
2571 {
2572 struct b43_wl *wl = hw_to_b43_wl(hw);
2573 unsigned long flags;
2574
2575 spin_lock_irqsave(&wl->irq_lock, flags);
2576 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2577 spin_unlock_irqrestore(&wl->irq_lock, flags);
2578
2579 return 0;
2580 }
2581
2582 static const char *phymode_to_string(unsigned int phymode)
2583 {
2584 switch (phymode) {
2585 case B43_PHYMODE_A:
2586 return "A";
2587 case B43_PHYMODE_B:
2588 return "B";
2589 case B43_PHYMODE_G:
2590 return "G";
2591 default:
2592 B43_WARN_ON(1);
2593 }
2594 return "";
2595 }
2596
2597 static int find_wldev_for_phymode(struct b43_wl *wl,
2598 unsigned int phymode,
2599 struct b43_wldev **dev, bool * gmode)
2600 {
2601 struct b43_wldev *d;
2602
2603 list_for_each_entry(d, &wl->devlist, list) {
2604 if (d->phy.possible_phymodes & phymode) {
2605 /* Ok, this device supports the PHY-mode.
2606 * Now figure out how the gmode bit has to be
2607 * set to support it. */
2608 if (phymode == B43_PHYMODE_A)
2609 *gmode = 0;
2610 else
2611 *gmode = 1;
2612 *dev = d;
2613
2614 return 0;
2615 }
2616 }
2617
2618 return -ESRCH;
2619 }
2620
2621 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2622 {
2623 struct ssb_device *sdev = dev->dev;
2624 u32 tmslow;
2625
2626 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2627 tmslow &= ~B43_TMSLOW_GMODE;
2628 tmslow |= B43_TMSLOW_PHYRESET;
2629 tmslow |= SSB_TMSLOW_FGC;
2630 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2631 msleep(1);
2632
2633 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2634 tmslow &= ~SSB_TMSLOW_FGC;
2635 tmslow |= B43_TMSLOW_PHYRESET;
2636 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2637 msleep(1);
2638 }
2639
2640 /* Expects wl->mutex locked */
2641 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2642 {
2643 struct b43_wldev *up_dev;
2644 struct b43_wldev *down_dev;
2645 int err;
2646 bool gmode = 0;
2647 int prev_status;
2648
2649 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2650 if (err) {
2651 b43err(wl, "Could not find a device for %s-PHY mode\n",
2652 phymode_to_string(new_mode));
2653 return err;
2654 }
2655 if ((up_dev == wl->current_dev) &&
2656 (!!wl->current_dev->phy.gmode == !!gmode)) {
2657 /* This device is already running. */
2658 return 0;
2659 }
2660 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2661 phymode_to_string(new_mode));
2662 down_dev = wl->current_dev;
2663
2664 prev_status = b43_status(down_dev);
2665 /* Shutdown the currently running core. */
2666 if (prev_status >= B43_STAT_STARTED)
2667 b43_wireless_core_stop(down_dev);
2668 if (prev_status >= B43_STAT_INITIALIZED)
2669 b43_wireless_core_exit(down_dev);
2670
2671 if (down_dev != up_dev) {
2672 /* We switch to a different core, so we put PHY into
2673 * RESET on the old core. */
2674 b43_put_phy_into_reset(down_dev);
2675 }
2676
2677 /* Now start the new core. */
2678 up_dev->phy.gmode = gmode;
2679 if (prev_status >= B43_STAT_INITIALIZED) {
2680 err = b43_wireless_core_init(up_dev);
2681 if (err) {
2682 b43err(wl, "Fatal: Could not initialize device for "
2683 "newly selected %s-PHY mode\n",
2684 phymode_to_string(new_mode));
2685 goto init_failure;
2686 }
2687 }
2688 if (prev_status >= B43_STAT_STARTED) {
2689 err = b43_wireless_core_start(up_dev);
2690 if (err) {
2691 b43err(wl, "Fatal: Coult not start device for "
2692 "newly selected %s-PHY mode\n",
2693 phymode_to_string(new_mode));
2694 b43_wireless_core_exit(up_dev);
2695 goto init_failure;
2696 }
2697 }
2698 B43_WARN_ON(b43_status(up_dev) != prev_status);
2699
2700 wl->current_dev = up_dev;
2701
2702 return 0;
2703 init_failure:
2704 /* Whoops, failed to init the new core. No core is operating now. */
2705 wl->current_dev = NULL;
2706 return err;
2707 }
2708
2709 static int b43_antenna_from_ieee80211(u8 antenna)
2710 {
2711 switch (antenna) {
2712 case 0: /* default/diversity */
2713 return B43_ANTENNA_DEFAULT;
2714 case 1: /* Antenna 0 */
2715 return B43_ANTENNA0;
2716 case 2: /* Antenna 1 */
2717 return B43_ANTENNA1;
2718 default:
2719 return B43_ANTENNA_DEFAULT;
2720 }
2721 }
2722
2723 static int b43_dev_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2724 {
2725 struct b43_wl *wl = hw_to_b43_wl(hw);
2726 struct b43_wldev *dev;
2727 struct b43_phy *phy;
2728 unsigned long flags;
2729 unsigned int new_phymode = 0xFFFF;
2730 int antenna_tx;
2731 int antenna_rx;
2732 int err = 0;
2733 u32 savedirqs;
2734
2735 antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
2736 antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
2737
2738 mutex_lock(&wl->mutex);
2739
2740 /* Switch the PHY mode (if necessary). */
2741 switch (conf->phymode) {
2742 case MODE_IEEE80211A:
2743 new_phymode = B43_PHYMODE_A;
2744 break;
2745 case MODE_IEEE80211B:
2746 new_phymode = B43_PHYMODE_B;
2747 break;
2748 case MODE_IEEE80211G:
2749 new_phymode = B43_PHYMODE_G;
2750 break;
2751 default:
2752 B43_WARN_ON(1);
2753 }
2754 err = b43_switch_phymode(wl, new_phymode);
2755 if (err)
2756 goto out_unlock_mutex;
2757 dev = wl->current_dev;
2758 phy = &dev->phy;
2759
2760 /* Disable IRQs while reconfiguring the device.
2761 * This makes it possible to drop the spinlock throughout
2762 * the reconfiguration process. */
2763 spin_lock_irqsave(&wl->irq_lock, flags);
2764 if (b43_status(dev) < B43_STAT_STARTED) {
2765 spin_unlock_irqrestore(&wl->irq_lock, flags);
2766 goto out_unlock_mutex;
2767 }
2768 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2769 spin_unlock_irqrestore(&wl->irq_lock, flags);
2770 b43_synchronize_irq(dev);
2771
2772 /* Switch to the requested channel.
2773 * The firmware takes care of races with the TX handler. */
2774 if (conf->channel_val != phy->channel)
2775 b43_radio_selectchannel(dev, conf->channel_val, 0);
2776
2777 /* Enable/Disable ShortSlot timing. */
2778 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2779 dev->short_slot) {
2780 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2781 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2782 b43_short_slot_timing_enable(dev);
2783 else
2784 b43_short_slot_timing_disable(dev);
2785 }
2786
2787 /* Adjust the desired TX power level. */
2788 if (conf->power_level != 0) {
2789 if (conf->power_level != phy->power_level) {
2790 phy->power_level = conf->power_level;
2791 b43_phy_xmitpower(dev);
2792 }
2793 }
2794
2795 /* Antennas for RX and management frame TX. */
2796 b43_mgmtframe_txantenna(dev, antenna_tx);
2797 b43_set_rx_antenna(dev, antenna_rx);
2798
2799 /* Update templates for AP mode. */
2800 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2801 b43_set_beacon_int(dev, conf->beacon_int);
2802
2803 if (!!conf->radio_enabled != phy->radio_on) {
2804 if (conf->radio_enabled) {
2805 b43_radio_turn_on(dev);
2806 b43info(dev->wl, "Radio turned on by software\n");
2807 if (!dev->radio_hw_enable) {
2808 b43info(dev->wl, "The hardware RF-kill button "
2809 "still turns the radio physically off. "
2810 "Press the button to turn it on.\n");
2811 }
2812 } else {
2813 b43_radio_turn_off(dev, 0);
2814 b43info(dev->wl, "Radio turned off by software\n");
2815 }
2816 }
2817
2818 spin_lock_irqsave(&wl->irq_lock, flags);
2819 b43_interrupt_enable(dev, savedirqs);
2820 mmiowb();
2821 spin_unlock_irqrestore(&wl->irq_lock, flags);
2822 out_unlock_mutex:
2823 mutex_unlock(&wl->mutex);
2824
2825 return err;
2826 }
2827
2828 static int b43_dev_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2829 const u8 *local_addr, const u8 *addr,
2830 struct ieee80211_key_conf *key)
2831 {
2832 struct b43_wl *wl = hw_to_b43_wl(hw);
2833 struct b43_wldev *dev = wl->current_dev;
2834 unsigned long flags;
2835 u8 algorithm;
2836 u8 index;
2837 int err = -EINVAL;
2838
2839 if (modparam_nohwcrypt)
2840 return -ENOSPC; /* User disabled HW-crypto */
2841
2842 if (!dev)
2843 return -ENODEV;
2844 switch (key->alg) {
2845 case ALG_WEP:
2846 if (key->keylen == 5)
2847 algorithm = B43_SEC_ALGO_WEP40;
2848 else
2849 algorithm = B43_SEC_ALGO_WEP104;
2850 break;
2851 case ALG_TKIP:
2852 algorithm = B43_SEC_ALGO_TKIP;
2853 break;
2854 case ALG_CCMP:
2855 algorithm = B43_SEC_ALGO_AES;
2856 break;
2857 default:
2858 B43_WARN_ON(1);
2859 goto out;
2860 }
2861
2862 index = (u8) (key->keyidx);
2863 if (index > 3)
2864 goto out;
2865
2866 mutex_lock(&wl->mutex);
2867 spin_lock_irqsave(&wl->irq_lock, flags);
2868
2869 if (b43_status(dev) < B43_STAT_INITIALIZED) {
2870 err = -ENODEV;
2871 goto out_unlock;
2872 }
2873
2874 switch (cmd) {
2875 case SET_KEY:
2876 if (algorithm == B43_SEC_ALGO_TKIP) {
2877 /* FIXME: No TKIP hardware encryption for now. */
2878 err = -EOPNOTSUPP;
2879 goto out_unlock;
2880 }
2881
2882 if (is_broadcast_ether_addr(addr)) {
2883 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2884 err = b43_key_write(dev, index, algorithm,
2885 key->key, key->keylen, NULL, key);
2886 } else {
2887 /*
2888 * either pairwise key or address is 00:00:00:00:00:00
2889 * for transmit-only keys
2890 */
2891 err = b43_key_write(dev, -1, algorithm,
2892 key->key, key->keylen, addr, key);
2893 }
2894 if (err)
2895 goto out_unlock;
2896
2897 if (algorithm == B43_SEC_ALGO_WEP40 ||
2898 algorithm == B43_SEC_ALGO_WEP104) {
2899 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2900 } else {
2901 b43_hf_write(dev,
2902 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2903 }
2904 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2905 break;
2906 case DISABLE_KEY: {
2907 err = b43_key_clear(dev, key->hw_key_idx);
2908 if (err)
2909 goto out_unlock;
2910 break;
2911 }
2912 default:
2913 B43_WARN_ON(1);
2914 }
2915 out_unlock:
2916 spin_unlock_irqrestore(&wl->irq_lock, flags);
2917 mutex_unlock(&wl->mutex);
2918 out:
2919 if (!err) {
2920 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2921 "mac: " MAC_FMT "\n",
2922 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2923 MAC_ARG(addr));
2924 }
2925 return err;
2926 }
2927
2928 static void b43_configure_filter(struct ieee80211_hw *hw,
2929 unsigned int changed, unsigned int *fflags,
2930 int mc_count, struct dev_addr_list *mc_list)
2931 {
2932 struct b43_wl *wl = hw_to_b43_wl(hw);
2933 struct b43_wldev *dev = wl->current_dev;
2934 unsigned long flags;
2935
2936 if (!dev) {
2937 *fflags = 0;
2938 return;
2939 }
2940
2941 spin_lock_irqsave(&wl->irq_lock, flags);
2942 *fflags &= FIF_PROMISC_IN_BSS |
2943 FIF_ALLMULTI |
2944 FIF_FCSFAIL |
2945 FIF_PLCPFAIL |
2946 FIF_CONTROL |
2947 FIF_OTHER_BSS |
2948 FIF_BCN_PRBRESP_PROMISC;
2949
2950 changed &= FIF_PROMISC_IN_BSS |
2951 FIF_ALLMULTI |
2952 FIF_FCSFAIL |
2953 FIF_PLCPFAIL |
2954 FIF_CONTROL |
2955 FIF_OTHER_BSS |
2956 FIF_BCN_PRBRESP_PROMISC;
2957
2958 wl->filter_flags = *fflags;
2959
2960 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2961 b43_adjust_opmode(dev);
2962 spin_unlock_irqrestore(&wl->irq_lock, flags);
2963 }
2964
2965 static int b43_config_interface(struct ieee80211_hw *hw,
2966 int if_id, struct ieee80211_if_conf *conf)
2967 {
2968 struct b43_wl *wl = hw_to_b43_wl(hw);
2969 struct b43_wldev *dev = wl->current_dev;
2970 unsigned long flags;
2971
2972 if (!dev)
2973 return -ENODEV;
2974 mutex_lock(&wl->mutex);
2975 spin_lock_irqsave(&wl->irq_lock, flags);
2976 B43_WARN_ON(wl->if_id != if_id);
2977 if (conf->bssid)
2978 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2979 else
2980 memset(wl->bssid, 0, ETH_ALEN);
2981 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2982 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2983 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2984 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2985 if (conf->beacon)
2986 b43_refresh_templates(dev, conf->beacon);
2987 }
2988 b43_write_mac_bssid_templates(dev);
2989 }
2990 spin_unlock_irqrestore(&wl->irq_lock, flags);
2991 mutex_unlock(&wl->mutex);
2992
2993 return 0;
2994 }
2995
2996 /* Locking: wl->mutex */
2997 static void b43_wireless_core_stop(struct b43_wldev *dev)
2998 {
2999 struct b43_wl *wl = dev->wl;
3000 unsigned long flags;
3001
3002 if (b43_status(dev) < B43_STAT_STARTED)
3003 return;
3004 b43_set_status(dev, B43_STAT_INITIALIZED);
3005
3006 mutex_unlock(&wl->mutex);
3007 /* Must unlock as it would otherwise deadlock. No races here.
3008 * Cancel the possibly running self-rearming periodic work. */
3009 cancel_delayed_work_sync(&dev->periodic_work);
3010 mutex_lock(&wl->mutex);
3011
3012 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3013
3014 /* Disable and sync interrupts. */
3015 spin_lock_irqsave(&wl->irq_lock, flags);
3016 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3017 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3018 spin_unlock_irqrestore(&wl->irq_lock, flags);
3019 b43_synchronize_irq(dev);
3020
3021 b43_mac_suspend(dev);
3022 free_irq(dev->dev->irq, dev);
3023 b43dbg(wl, "Wireless interface stopped\n");
3024 }
3025
3026 /* Locking: wl->mutex */
3027 static int b43_wireless_core_start(struct b43_wldev *dev)
3028 {
3029 int err;
3030
3031 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3032
3033 drain_txstatus_queue(dev);
3034 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3035 IRQF_SHARED, KBUILD_MODNAME, dev);
3036 if (err) {
3037 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3038 goto out;
3039 }
3040
3041 /* We are ready to run. */
3042 b43_set_status(dev, B43_STAT_STARTED);
3043
3044 /* Start data flow (TX/RX). */
3045 b43_mac_enable(dev);
3046 b43_interrupt_enable(dev, dev->irq_savedstate);
3047 ieee80211_start_queues(dev->wl->hw);
3048
3049 /* Start maintainance work */
3050 b43_periodic_tasks_setup(dev);
3051
3052 b43dbg(dev->wl, "Wireless interface started\n");
3053 out:
3054 return err;
3055 }
3056
3057 /* Get PHY and RADIO versioning numbers */
3058 static int b43_phy_versioning(struct b43_wldev *dev)
3059 {
3060 struct b43_phy *phy = &dev->phy;
3061 u32 tmp;
3062 u8 analog_type;
3063 u8 phy_type;
3064 u8 phy_rev;
3065 u16 radio_manuf;
3066 u16 radio_ver;
3067 u16 radio_rev;
3068 int unsupported = 0;
3069
3070 /* Get PHY versioning */
3071 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3072 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3073 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3074 phy_rev = (tmp & B43_PHYVER_VERSION);
3075 switch (phy_type) {
3076 case B43_PHYTYPE_A:
3077 if (phy_rev >= 4)
3078 unsupported = 1;
3079 break;
3080 case B43_PHYTYPE_B:
3081 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3082 && phy_rev != 7)
3083 unsupported = 1;
3084 break;
3085 case B43_PHYTYPE_G:
3086 if (phy_rev > 8)
3087 unsupported = 1;
3088 break;
3089 default:
3090 unsupported = 1;
3091 };
3092 if (unsupported) {
3093 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3094 "(Analog %u, Type %u, Revision %u)\n",
3095 analog_type, phy_type, phy_rev);
3096 return -EOPNOTSUPP;
3097 }
3098 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3099 analog_type, phy_type, phy_rev);
3100
3101 /* Get RADIO versioning */
3102 if (dev->dev->bus->chip_id == 0x4317) {
3103 if (dev->dev->bus->chip_rev == 0)
3104 tmp = 0x3205017F;
3105 else if (dev->dev->bus->chip_rev == 1)
3106 tmp = 0x4205017F;
3107 else
3108 tmp = 0x5205017F;
3109 } else {
3110 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3111 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3112 tmp <<= 16;
3113 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3114 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3115 }
3116 radio_manuf = (tmp & 0x00000FFF);
3117 radio_ver = (tmp & 0x0FFFF000) >> 12;
3118 radio_rev = (tmp & 0xF0000000) >> 28;
3119 switch (phy_type) {
3120 case B43_PHYTYPE_A:
3121 if (radio_ver != 0x2060)
3122 unsupported = 1;
3123 if (radio_rev != 1)
3124 unsupported = 1;
3125 if (radio_manuf != 0x17F)
3126 unsupported = 1;
3127 break;
3128 case B43_PHYTYPE_B:
3129 if ((radio_ver & 0xFFF0) != 0x2050)
3130 unsupported = 1;
3131 break;
3132 case B43_PHYTYPE_G:
3133 if (radio_ver != 0x2050)
3134 unsupported = 1;
3135 break;
3136 default:
3137 B43_WARN_ON(1);
3138 }
3139 if (unsupported) {
3140 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3141 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3142 radio_manuf, radio_ver, radio_rev);
3143 return -EOPNOTSUPP;
3144 }
3145 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3146 radio_manuf, radio_ver, radio_rev);
3147
3148 phy->radio_manuf = radio_manuf;
3149 phy->radio_ver = radio_ver;
3150 phy->radio_rev = radio_rev;
3151
3152 phy->analog = analog_type;
3153 phy->type = phy_type;
3154 phy->rev = phy_rev;
3155
3156 return 0;
3157 }
3158
3159 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3160 struct b43_phy *phy)
3161 {
3162 struct b43_txpower_lo_control *lo;
3163 int i;
3164
3165 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3166 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3167
3168 /* Flags */
3169 phy->locked = 0;
3170
3171 phy->aci_enable = 0;
3172 phy->aci_wlan_automatic = 0;
3173 phy->aci_hw_rssi = 0;
3174
3175 phy->radio_off_context.valid = 0;
3176
3177 lo = phy->lo_control;
3178 if (lo) {
3179 memset(lo, 0, sizeof(*(phy->lo_control)));
3180 lo->rebuild = 1;
3181 lo->tx_bias = 0xFF;
3182 }
3183 phy->max_lb_gain = 0;
3184 phy->trsw_rx_gain = 0;
3185 phy->txpwr_offset = 0;
3186
3187 /* NRSSI */
3188 phy->nrssislope = 0;
3189 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3190 phy->nrssi[i] = -1000;
3191 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3192 phy->nrssi_lt[i] = i;
3193
3194 phy->lofcal = 0xFFFF;
3195 phy->initval = 0xFFFF;
3196
3197 spin_lock_init(&phy->lock);
3198 phy->interfmode = B43_INTERFMODE_NONE;
3199 phy->channel = 0xFF;
3200
3201 phy->hardware_power_control = !!modparam_hwpctl;
3202 }
3203
3204 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3205 {
3206 /* Flags */
3207 dev->reg124_set_0x4 = 0;
3208 /* Assume the radio is enabled. If it's not enabled, the state will
3209 * immediately get fixed on the first periodic work run. */
3210 dev->radio_hw_enable = 1;
3211
3212 /* Stats */
3213 memset(&dev->stats, 0, sizeof(dev->stats));
3214
3215 setup_struct_phy_for_init(dev, &dev->phy);
3216
3217 /* IRQ related flags */
3218 dev->irq_reason = 0;
3219 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3220 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3221
3222 dev->mac_suspended = 1;
3223
3224 /* Noise calculation context */
3225 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3226 }
3227
3228 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3229 {
3230 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3231 u32 hf;
3232
3233 if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST))
3234 return;
3235 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3236 return;
3237
3238 hf = b43_hf_read(dev);
3239 if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD)
3240 hf |= B43_HF_BTCOEXALT;
3241 else
3242 hf |= B43_HF_BTCOEX;
3243 b43_hf_write(dev, hf);
3244 //TODO
3245 }
3246
3247 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3248 { //TODO
3249 }
3250
3251 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3252 {
3253 #ifdef CONFIG_SSB_DRIVER_PCICORE
3254 struct ssb_bus *bus = dev->dev->bus;
3255 u32 tmp;
3256
3257 if (bus->pcicore.dev &&
3258 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3259 bus->pcicore.dev->id.revision <= 5) {
3260 /* IMCFGLO timeouts workaround. */
3261 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3262 tmp &= ~SSB_IMCFGLO_REQTO;
3263 tmp &= ~SSB_IMCFGLO_SERTO;
3264 switch (bus->bustype) {
3265 case SSB_BUSTYPE_PCI:
3266 case SSB_BUSTYPE_PCMCIA:
3267 tmp |= 0x32;
3268 break;
3269 case SSB_BUSTYPE_SSB:
3270 tmp |= 0x53;
3271 break;
3272 }
3273 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3274 }
3275 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3276 }
3277
3278 /* Shutdown a wireless core */
3279 /* Locking: wl->mutex */
3280 static void b43_wireless_core_exit(struct b43_wldev *dev)
3281 {
3282 struct b43_phy *phy = &dev->phy;
3283
3284 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3285 if (b43_status(dev) != B43_STAT_INITIALIZED)
3286 return;
3287 b43_set_status(dev, B43_STAT_UNINIT);
3288
3289 mutex_unlock(&dev->wl->mutex);
3290 b43_rfkill_exit(dev);
3291 mutex_lock(&dev->wl->mutex);
3292
3293 b43_rng_exit(dev->wl);
3294 b43_pio_free(dev);
3295 b43_dma_free(dev);
3296 b43_chip_exit(dev);
3297 b43_radio_turn_off(dev, 1);
3298 b43_switch_analog(dev, 0);
3299 if (phy->dyn_tssi_tbl)
3300 kfree(phy->tssi2dbm);
3301 kfree(phy->lo_control);
3302 phy->lo_control = NULL;
3303 ssb_device_disable(dev->dev, 0);
3304 ssb_bus_may_powerdown(dev->dev->bus);
3305 }
3306
3307 /* Initialize a wireless core */
3308 static int b43_wireless_core_init(struct b43_wldev *dev)
3309 {
3310 struct b43_wl *wl = dev->wl;
3311 struct ssb_bus *bus = dev->dev->bus;
3312 struct ssb_sprom *sprom = &bus->sprom;
3313 struct b43_phy *phy = &dev->phy;
3314 int err;
3315 u32 hf, tmp;
3316
3317 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3318
3319 err = ssb_bus_powerup(bus, 0);
3320 if (err)
3321 goto out;
3322 if (!ssb_device_is_enabled(dev->dev)) {
3323 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3324 b43_wireless_core_reset(dev, tmp);
3325 }
3326
3327 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3328 phy->lo_control =
3329 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3330 if (!phy->lo_control) {
3331 err = -ENOMEM;
3332 goto err_busdown;
3333 }
3334 }
3335 setup_struct_wldev_for_init(dev);
3336
3337 err = b43_phy_init_tssi2dbm_table(dev);
3338 if (err)
3339 goto err_kfree_lo_control;
3340
3341 /* Enable IRQ routing to this device. */
3342 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3343
3344 b43_imcfglo_timeouts_workaround(dev);
3345 b43_bluetooth_coext_disable(dev);
3346 b43_phy_early_init(dev);
3347 err = b43_chip_init(dev);
3348 if (err)
3349 goto err_kfree_tssitbl;
3350 b43_shm_write16(dev, B43_SHM_SHARED,
3351 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3352 hf = b43_hf_read(dev);
3353 if (phy->type == B43_PHYTYPE_G) {
3354 hf |= B43_HF_SYMW;
3355 if (phy->rev == 1)
3356 hf |= B43_HF_GDCW;
3357 if (sprom->r1.boardflags_lo & B43_BFL_PACTRL)
3358 hf |= B43_HF_OFDMPABOOST;
3359 } else if (phy->type == B43_PHYTYPE_B) {
3360 hf |= B43_HF_SYMW;
3361 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3362 hf &= ~B43_HF_GDCW;
3363 }
3364 b43_hf_write(dev, hf);
3365
3366 /* Short/Long Retry Limit.
3367 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3368 * the chip-internal counter.
3369 */
3370 tmp = limit_value(modparam_short_retry, 0, 0xF);
3371 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, tmp);
3372 tmp = limit_value(modparam_long_retry, 0, 0xF);
3373 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, tmp);
3374
3375 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3376 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3377
3378 /* Disable sending probe responses from firmware.
3379 * Setting the MaxTime to one usec will always trigger
3380 * a timeout, so we never send any probe resp.
3381 * A timeout of zero is infinite. */
3382 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3383
3384 b43_rate_memory_init(dev);
3385
3386 /* Minimum Contention Window */
3387 if (phy->type == B43_PHYTYPE_B) {
3388 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3389 } else {
3390 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3391 }
3392 /* Maximum Contention Window */
3393 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3394
3395 do {
3396 if (b43_using_pio(dev)) {
3397 err = b43_pio_init(dev);
3398 } else {
3399 err = b43_dma_init(dev);
3400 if (!err)