uboot-lantiq: update to v2013.10
[openwrt/svn-archive/archive.git] / package / boot / uboot-lantiq / patches / 0015-MIPS-lantiq-add-support-for-Lantiq-XWAY-ARX100-SoC-f.patch
1 From 4953294aa8f8b9023e6b5f7f39059706c72d916c Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Sun, 9 Dec 2012 17:54:56 +0100
4 Subject: MIPS: lantiq: add support for Lantiq XWAY ARX100 SoC family
5
6 Signed-off-by: Luka Perkov <luka@openwrt.org>
7 Signed-off-by: John Crispin <blogic@openwrt.org>
8 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9
10 diff --git a/arch/mips/cpu/mips32/arx100/Makefile b/arch/mips/cpu/mips32/arx100/Makefile
11 new file mode 100644
12 index 0000000..98f5f73
13 --- /dev/null
14 +++ b/arch/mips/cpu/mips32/arx100/Makefile
15 @@ -0,0 +1,31 @@
16 +#
17 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
18 +#
19 +# SPDX-License-Identifier: GPL-2.0+
20 +#
21 +
22 +include $(TOPDIR)/config.mk
23 +
24 +LIB = $(obj)lib$(SOC).o
25 +
26 +COBJS-y += cgu.o chipid.o ebu.o mem.o pmu.o rcu.o
27 +SOBJS-y += cgu_init.o mem_init.o
28 +
29 +COBJS := $(COBJS-y)
30 +SOBJS := $(SOBJS-y)
31 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
32 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
33 +
34 +all: $(LIB)
35 +
36 +$(LIB): $(obj).depend $(OBJS)
37 + $(call cmd_link_o_target, $(OBJS))
38 +
39 +#########################################################################
40 +
41 +# defines $(obj).depend target
42 +include $(SRCTREE)/rules.mk
43 +
44 +sinclude $(obj).depend
45 +
46 +#########################################################################
47 diff --git a/arch/mips/cpu/mips32/arx100/cgu.c b/arch/mips/cpu/mips32/arx100/cgu.c
48 new file mode 100644
49 index 0000000..6e71ee7
50 --- /dev/null
51 +++ b/arch/mips/cpu/mips32/arx100/cgu.c
52 @@ -0,0 +1,109 @@
53 +/*
54 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
55 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
56 + *
57 + * SPDX-License-Identifier: GPL-2.0+
58 + */
59 +
60 +#include <common.h>
61 +#include <asm/arch/soc.h>
62 +#include <asm/lantiq/clk.h>
63 +#include <asm/lantiq/io.h>
64 +
65 +#define CGU_SYS_DDR_SEL (1 << 0)
66 +#define CGU_SYS_CPU_SEL (1 << 2)
67 +#define CGU_SYS_SYS_SHIFT 3
68 +#define CGU_SYS_SYS_MASK (0x3 << CGU_SYS_SYS_SHIFT)
69 +#define CGU_SYS_FPI_SEL (1 << 6)
70 +#define CGU_SYS_PPE_SEL (1 << 7)
71 +
72 +struct ltq_cgu_regs {
73 + u32 rsvd0;
74 + __be32 pll0_cfg; /* PLL0 config */
75 + __be32 pll1_cfg; /* PLL1 config */
76 + u32 rsvd2;
77 + __be32 sys; /* System clock */
78 + __be32 update; /* CGU update control */
79 + __be32 if_clk; /* Interface clock */
80 + u32 rsvd3;
81 + __be32 smd; /* SDRAM Memory Control */
82 + u32 rsvd4;
83 + __be32 ct1_sr; /* CT status 1 */
84 + __be32 ct_kval; /* CT K value */
85 + __be32 pcm_cr; /* PCM control */
86 +};
87 +
88 +static struct ltq_cgu_regs *ltq_cgu_regs =
89 + (struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE);
90 +
91 +static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift)
92 +{
93 + return (ltq_readl(&ltq_cgu_regs->sys) & mask) >> shift;
94 +}
95 +
96 +static unsigned long ltq_get_system_clock(void)
97 +{
98 + u32 sys_sel;
99 + unsigned long clk;
100 +
101 + sys_sel = ltq_cgu_sys_readl(CGU_SYS_SYS_MASK, CGU_SYS_SYS_SHIFT);
102 +
103 + switch (sys_sel) {
104 + case 0:
105 + clk = CLOCK_333_MHZ;
106 + break;
107 + case 2:
108 + clk = CLOCK_393_MHZ;
109 + break;
110 + default:
111 + clk = 0;
112 + break;
113 + }
114 +
115 + return clk;
116 +}
117 +
118 +unsigned long ltq_get_io_region_clock(void)
119 +{
120 + u32 ddr_sel;
121 + unsigned long clk;
122 +
123 + ddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL);
124 +
125 + if (ddr_sel)
126 + clk = ltq_get_system_clock() / 3;
127 + else
128 + clk = ltq_get_system_clock() / 2;
129 +
130 + return clk;
131 +}
132 +
133 +unsigned long ltq_get_cpu_clock(void)
134 +{
135 + u32 cpu_sel;
136 + unsigned long clk;
137 +
138 + cpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL);
139 +
140 + if (cpu_sel)
141 + clk = ltq_get_io_region_clock();
142 + else
143 + clk = ltq_get_system_clock();
144 +
145 + return clk;
146 +}
147 +
148 +unsigned long ltq_get_bus_clock(void)
149 +{
150 + u32 fpi_sel;
151 + unsigned long clk;
152 +
153 + fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);
154 +
155 + if (fpi_sel)
156 + clk = ltq_get_io_region_clock() / 2;
157 + else
158 + clk = ltq_get_io_region_clock();
159 +
160 + return clk;
161 +}
162 diff --git a/arch/mips/cpu/mips32/arx100/cgu_init.S b/arch/mips/cpu/mips32/arx100/cgu_init.S
163 new file mode 100644
164 index 0000000..ed70cb2
165 --- /dev/null
166 +++ b/arch/mips/cpu/mips32/arx100/cgu_init.S
167 @@ -0,0 +1,105 @@
168 +/*
169 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
170 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
171 + *
172 + * SPDX-License-Identifier: GPL-2.0+
173 + */
174 +
175 +#include <config.h>
176 +#include <asm/asm.h>
177 +#include <asm/regdef.h>
178 +#include <asm/addrspace.h>
179 +#include <asm/arch/soc.h>
180 +
181 +/* CGU module register */
182 +#define CGU_PLL0_CFG 0x0004 /* PLL0 config */
183 +#define CGU_PLL1_CFG 0x0008 /* PLL1 config */
184 +#define CGU_SYS 0x0010 /* System clock */
185 +#define CGU_UPDATE 0x0014 /* Clock update control */
186 +
187 +/* Valid SYS.PPE_SEL values */
188 +#define CGU_SYS_PPESEL_SHIFT 7
189 +#define CGU_SYS_PPESEL_250_MHZ (0x1 << CGU_SYS_PPESEL_SHIFT)
190 +
191 +/* Valid SYS.SYS_SEL values */
192 +#define CGU_SYS_SYSSEL_SHIFT 3
193 +#define CGU_SYS_SYSSEL_PLL0_333_MHZ (0x0 << CGU_SYS_SYSSEL_SHIFT)
194 +#define CGU_SYS_SYSSEL_PLL1_393_MHZ (0x2 << CGU_SYS_SYSSEL_SHIFT)
195 +
196 +/* Valid SYS.CPU_SEL values */
197 +#define CGU_SYS_CPUSEL_SHIFT 2
198 +#define CGU_SYS_CPUSEL_EQUAL_SYSCLK (0x0 << CGU_SYS_CPUSEL_SHIFT)
199 +#define CGU_SYS_CPUSEL_EQUAL_DDRCLK (0x1 << CGU_SYS_CPUSEL_SHIFT)
200 +
201 +/* Valid SYS.DDR_SEL values */
202 +#define CGU_SYS_DDRSEL_HALF_SYSCLK 0x0
203 +#define CGU_SYS_DDRSEL_THIRD_SYSCLK 0x1
204 +
205 +#define CGU_UPDATE_UPD 0x1
206 +
207 +#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_393_DDR_197)
208 +#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ
209 +#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL1_393_MHZ
210 +#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_SYSCLK
211 +#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_HALF_SYSCLK
212 +#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_197_DDR_197)
213 +#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ
214 +#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL1_393_MHZ
215 +#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_DDRCLK
216 +#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_HALF_SYSCLK
217 +#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_333_DDR_167)
218 +#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ
219 +#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL0_333_MHZ
220 +#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_SYSCLK
221 +#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_HALF_SYSCLK
222 +#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_167_DDR_167)
223 +#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ
224 +#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL0_333_MHZ
225 +#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_DDRCLK
226 +#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_HALF_SYSCLK
227 +#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_131_DDR_131)
228 +#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ
229 +#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL1_393_MHZ
230 +#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_DDRCLK
231 +#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_THIRD_SYSCLK
232 +#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_111_DDR_111)
233 +#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ
234 +#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL0_333_MHZ
235 +#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_DDRCLK
236 +#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_THIRD_SYSCLK
237 +#else
238 +#error "Invalid system clock configuration!"
239 +#endif
240 +
241 +/* Build register values */
242 +#define CGU_SYS_VALUE (CGU_SYS_PPESEL_CONFIG | \
243 + CGU_SYS_SYSSEL_CONFIG | \
244 + CGU_SYS_CPUSEL_CONFIG | \
245 + CGU_SYS_DDRSEL_CONFIG)
246 +
247 + .set noreorder
248 +
249 +LEAF(ltq_cgu_init)
250 + /* Load current CGU register value */
251 + li t0, (LTQ_CGU_BASE | KSEG1)
252 + lw t1, CGU_SYS(t0)
253 +
254 + /* Load target CGU register values */
255 + li t2, CGU_SYS_VALUE
256 +
257 + /* Only update registers if values differ */
258 + beq t1, t2, finished
259 + nop
260 +
261 + /* Store target register values */
262 + sw t2, CGU_SYS(t0)
263 +
264 + /* Trigger CGU update */
265 + li t1, CGU_UPDATE_UPD
266 + sw t1, CGU_UPDATE(t0)
267 +
268 +finished:
269 + jr ra
270 + nop
271 +
272 + END(ltq_cgu_init)
273 diff --git a/arch/mips/cpu/mips32/arx100/chipid.c b/arch/mips/cpu/mips32/arx100/chipid.c
274 new file mode 100644
275 index 0000000..e97d7ef
276 --- /dev/null
277 +++ b/arch/mips/cpu/mips32/arx100/chipid.c
278 @@ -0,0 +1,60 @@
279 +/*
280 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
281 + *
282 + * SPDX-License-Identifier: GPL-2.0+
283 + */
284 +
285 +#include <common.h>
286 +#include <asm/lantiq/io.h>
287 +#include <asm/lantiq/chipid.h>
288 +#include <asm/arch/soc.h>
289 +
290 +#define LTQ_CHIPID_VERSION_SHIFT 28
291 +#define LTQ_CHIPID_VERSION_MASK (0xF << LTQ_CHIPID_VERSION_SHIFT)
292 +#define LTQ_CHIPID_PNUM_SHIFT 12
293 +#define LTQ_CHIPID_PNUM_MASK (0xFFFF << LTQ_CHIPID_PNUM_SHIFT)
294 +
295 +struct ltq_chipid_regs {
296 + u32 manid; /* Manufacturer identification */
297 + u32 chipid; /* Chip identification */
298 +};
299 +
300 +static struct ltq_chipid_regs *ltq_chipid_regs =
301 + (struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE);
302 +
303 +unsigned int ltq_chip_version_get(void)
304 +{
305 + u32 chipid;
306 +
307 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
308 +
309 + return (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT;
310 +}
311 +
312 +unsigned int ltq_chip_partnum_get(void)
313 +{
314 + u32 chipid;
315 +
316 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
317 +
318 + return (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT;
319 +}
320 +
321 +const char *ltq_chip_partnum_str(void)
322 +{
323 + enum ltq_chip_partnum partnum = ltq_chip_partnum_get();
324 +
325 + switch (partnum) {
326 + case LTQ_SOC_ARX188:
327 + return "ARX188";
328 + case LTQ_SOC_ARX186:
329 + case LTQ_SOC_ARX186_2:
330 + return "ARX186";
331 + case LTQ_SOC_ARX182:
332 + return "ARX182";
333 + default:
334 + printf("Unknown partnum: %x\n", partnum);
335 + }
336 +
337 + return "";
338 +}
339 diff --git a/arch/mips/cpu/mips32/arx100/config.mk b/arch/mips/cpu/mips32/arx100/config.mk
340 new file mode 100644
341 index 0000000..442156a
342 --- /dev/null
343 +++ b/arch/mips/cpu/mips32/arx100/config.mk
344 @@ -0,0 +1,30 @@
345 +#
346 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
347 +#
348 +# SPDX-License-Identifier: GPL-2.0+
349 +#
350 +
351 +PF_CPPFLAGS_XRX := $(call cc-option,-mtune=34kc,)
352 +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_XRX)
353 +
354 +ifdef CONFIG_SPL_BUILD
355 +PF_ABICALLS := -mno-abicalls
356 +PF_PIC := -fno-pic
357 +PF_PIE :=
358 +USE_PRIVATE_LIBGCC := yes
359 +endif
360 +
361 +LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o
362 +
363 +ifndef CONFIG_SPL_BUILD
364 +ifdef CONFIG_SYS_BOOT_SFSPL
365 +ALL-y += $(obj)u-boot.ltq.sfspl
366 +ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl
367 +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.sfspl
368 +endif
369 +ifdef CONFIG_SYS_BOOT_NORSPL
370 +ALL-y += $(obj)u-boot.ltq.norspl
371 +ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl
372 +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl
373 +endif
374 +endif
375 diff --git a/arch/mips/cpu/mips32/arx100/ebu.c b/arch/mips/cpu/mips32/arx100/ebu.c
376 new file mode 100644
377 index 0000000..4ab3cf1
378 --- /dev/null
379 +++ b/arch/mips/cpu/mips32/arx100/ebu.c
380 @@ -0,0 +1,111 @@
381 +/*
382 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
383 + *
384 + * SPDX-License-Identifier: GPL-2.0+
385 + */
386 +
387 +#include <common.h>
388 +#include <asm/arch/soc.h>
389 +#include <asm/lantiq/io.h>
390 +
391 +#define EBU_ADDRSEL_MASK(mask) ((mask & 0xf) << 4)
392 +#define EBU_ADDRSEL_REGEN (1 << 0)
393 +
394 +#define EBU_CON_WRDIS (1 << 31)
395 +#define EBU_CON_AGEN_DEMUX (0x0 << 24)
396 +#define EBU_CON_AGEN_MUX (0x2 << 24)
397 +#define EBU_CON_SETUP (1 << 22)
398 +#define EBU_CON_WAIT_DIS (0x0 << 20)
399 +#define EBU_CON_WAIT_ASYNC (0x1 << 20)
400 +#define EBU_CON_WAIT_SYNC (0x2 << 20)
401 +#define EBU_CON_WINV (1 << 19)
402 +#define EBU_CON_PW_8BIT (0x0 << 16)
403 +#define EBU_CON_PW_16BIT (0x1 << 16)
404 +#define EBU_CON_ALEC(cycles) ((cycles & 0x3) << 14)
405 +#define EBU_CON_BCGEN_CS (0x0 << 12)
406 +#define EBU_CON_BCGEN_INTEL (0x1 << 12)
407 +#define EBU_CON_BCGEN_MOTOROLA (0x2 << 12)
408 +#define EBU_CON_WAITWRC(cycles) ((cycles & 0x7) << 8)
409 +#define EBU_CON_WAITRDC(cycles) ((cycles & 0x3) << 6)
410 +#define EBU_CON_HOLDC(cycles) ((cycles & 0x3) << 4)
411 +#define EBU_CON_RECOVC(cycles) ((cycles & 0x3) << 2)
412 +#define EBU_CON_CMULT_1 0x0
413 +#define EBU_CON_CMULT_4 0x1
414 +#define EBU_CON_CMULT_8 0x2
415 +#define EBU_CON_CMULT_16 0x3
416 +
417 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
418 +#define ebu_region0_enable 1
419 +#else
420 +#define ebu_region0_enable 0
421 +#endif
422 +
423 +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
424 +#define ebu_region1_enable 1
425 +#else
426 +#define ebu_region1_enable 0
427 +#endif
428 +
429 +struct ltq_ebu_regs {
430 + u32 clc;
431 + u32 rsvd0;
432 + u32 id;
433 + u32 rsvd1;
434 + u32 con;
435 + u32 rsvd2[3];
436 + u32 addr_sel_0;
437 + u32 addr_sel_1;
438 + u32 addr_sel_2;
439 + u32 addr_sel_3;
440 + u32 rsvd3[12];
441 + u32 con_0;
442 + u32 con_1;
443 + u32 con_2;
444 + u32 con_3;
445 +};
446 +
447 +static struct ltq_ebu_regs *ltq_ebu_regs =
448 + (struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE);
449 +
450 +void ltq_ebu_init(void)
451 +{
452 + if (ebu_region0_enable) {
453 + /*
454 + * Map EBU region 0 to range 0x10000000-0x13ffffff and enable
455 + * region control. This supports up to 32 MiB NOR flash in
456 + * bank 0.
457 + */
458 + ltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |
459 + EBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN);
460 +
461 + ltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |
462 + EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
463 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
464 + EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |
465 + EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |
466 + EBU_CON_CMULT_16);
467 + } else
468 + ltq_clrbits(&ltq_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN);
469 +
470 + if (ebu_region1_enable) {
471 + /*
472 + * Map EBU region 1 to range 0x14000000-0x13ffffff and enable
473 + * region control. This supports NAND flash in bank 1.
474 + */
475 + ltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |
476 + EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);
477 +
478 + ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
479 + EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |
480 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
481 + EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |
482 + EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |
483 + EBU_CON_CMULT_4);
484 + } else
485 + ltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);
486 +}
487 +
488 +void *flash_swap_addr(unsigned long addr)
489 +{
490 + return (void *)(addr ^ 2);
491 +}
492 diff --git a/arch/mips/cpu/mips32/arx100/mem.c b/arch/mips/cpu/mips32/arx100/mem.c
493 new file mode 100644
494 index 0000000..1fba7cd
495 --- /dev/null
496 +++ b/arch/mips/cpu/mips32/arx100/mem.c
497 @@ -0,0 +1,30 @@
498 +/*
499 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
500 + *
501 + * SPDX-License-Identifier: GPL-2.0+
502 + */
503 +
504 +#include <common.h>
505 +#include <asm/arch/soc.h>
506 +#include <asm/lantiq/io.h>
507 +
508 +static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE);
509 +
510 +static inline u32 ltq_mc_dc_read(u32 index)
511 +{
512 + return ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_DC_OFFSET(index));
513 +}
514 +
515 +phys_size_t initdram(int board_type)
516 +{
517 + u32 col, row, dc04, dc19, dc20;
518 +
519 + dc04 = ltq_mc_dc_read(4);
520 + dc19 = ltq_mc_dc_read(19);
521 + dc20 = ltq_mc_dc_read(20);
522 +
523 + row = (dc04 & 0xF) - ((dc19 & 0x700) >> 8);
524 + col = ((dc04 & 0xF00) >> 8) - (dc20 & 0x7);
525 +
526 + return (1 << (row + col)) * 4 * 2;
527 +}
528 diff --git a/arch/mips/cpu/mips32/arx100/mem_init.S b/arch/mips/cpu/mips32/arx100/mem_init.S
529 new file mode 100644
530 index 0000000..5d70842
531 --- /dev/null
532 +++ b/arch/mips/cpu/mips32/arx100/mem_init.S
533 @@ -0,0 +1,114 @@
534 +/*
535 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
536 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
537 + *
538 + * SPDX-License-Identifier: GPL-2.0+
539 + */
540 +
541 +#include <config.h>
542 +#include <asm/asm.h>
543 +#include <asm/regdef.h>
544 +#include <asm/addrspace.h>
545 +#include <asm/arch/soc.h>
546 +
547 +/* Must be configured in BOARDDIR */
548 +#include <ddr_settings.h>
549 +
550 +#define LTQ_MC_GEN_ERRCAUSE 0x0010
551 +#define LTQ_MC_GEN_ERRADDR 0x0020
552 +#define LTQ_MC_GEN_CON 0x0060
553 +#define LTQ_MC_GEN_STAT 0x0070
554 +#define LTQ_MC_GEN_CON_SRAM_DDR_ENABLE 0xD
555 +#define LTQ_MC_GEN_STAT_DLCK_PWRON 0xC
556 +
557 +#define LTQ_MC_DDR_DC03_MC_START 0x100
558 +
559 + /* Store given value in MC DDR CCRx register */
560 + .macro dc_sw num, val
561 + li t2, \val
562 + sw t2, LTQ_MC_DDR_DC_OFFSET(\num)(t1)
563 + .endm
564 +
565 +LEAF(ltq_mem_init)
566 + /* Load MC General and MC DDR module base */
567 + li t0, (LTQ_MC_GEN_BASE | KSEG1)
568 + li t1, (LTQ_MC_DDR_BASE | KSEG1)
569 +
570 + /* Clear access error log registers */
571 + sw zero, LTQ_MC_GEN_ERRCAUSE(t0)
572 + sw zero, LTQ_MC_GEN_ERRADDR(t0)
573 +
574 + /* Enable DDR and SRAM module in memory controller */
575 + li t2, LTQ_MC_GEN_CON_SRAM_DDR_ENABLE
576 + sw t2, LTQ_MC_GEN_CON(t0)
577 +
578 + /* Clear start bit of DDR memory controller */
579 + sw zero, LTQ_MC_DDR_DC_OFFSET(3)(t1)
580 +
581 + /* Init memory controller registers with values ddr_settings.h */
582 + dc_sw 0, MC_DC00_VALUE
583 + dc_sw 1, MC_DC01_VALUE
584 + dc_sw 2, MC_DC02_VALUE
585 + dc_sw 4, MC_DC04_VALUE
586 + dc_sw 5, MC_DC05_VALUE
587 + dc_sw 6, MC_DC06_VALUE
588 + dc_sw 7, MC_DC07_VALUE
589 + dc_sw 8, MC_DC08_VALUE
590 + dc_sw 9, MC_DC09_VALUE
591 +
592 + dc_sw 10, MC_DC10_VALUE
593 + dc_sw 11, MC_DC11_VALUE
594 + dc_sw 12, MC_DC12_VALUE
595 + dc_sw 13, MC_DC13_VALUE
596 + dc_sw 14, MC_DC14_VALUE
597 + dc_sw 15, MC_DC15_VALUE
598 + dc_sw 16, MC_DC16_VALUE
599 + dc_sw 17, MC_DC17_VALUE
600 + dc_sw 18, MC_DC18_VALUE
601 + dc_sw 19, MC_DC19_VALUE
602 +
603 + dc_sw 20, MC_DC20_VALUE
604 + dc_sw 21, MC_DC21_VALUE
605 + dc_sw 22, MC_DC22_VALUE
606 + dc_sw 23, MC_DC23_VALUE
607 + dc_sw 24, MC_DC24_VALUE
608 + dc_sw 25, MC_DC25_VALUE
609 + dc_sw 26, MC_DC26_VALUE
610 + dc_sw 27, MC_DC27_VALUE
611 + dc_sw 28, MC_DC28_VALUE
612 + dc_sw 29, MC_DC29_VALUE
613 +
614 + dc_sw 30, MC_DC30_VALUE
615 + dc_sw 31, MC_DC31_VALUE
616 + dc_sw 32, MC_DC32_VALUE
617 + dc_sw 33, MC_DC33_VALUE
618 + dc_sw 34, MC_DC34_VALUE
619 + dc_sw 35, MC_DC35_VALUE
620 + dc_sw 36, MC_DC36_VALUE
621 + dc_sw 37, MC_DC37_VALUE
622 + dc_sw 38, MC_DC38_VALUE
623 + dc_sw 39, MC_DC39_VALUE
624 +
625 + dc_sw 40, MC_DC40_VALUE
626 + dc_sw 41, MC_DC41_VALUE
627 + dc_sw 42, MC_DC42_VALUE
628 + dc_sw 43, MC_DC43_VALUE
629 + dc_sw 44, MC_DC44_VALUE
630 + dc_sw 45, MC_DC45_VALUE
631 + dc_sw 46, MC_DC46_VALUE
632 +
633 + /* Set start bit of DDR memory controller */
634 + li t2, LTQ_MC_DDR_DC03_MC_START
635 + sw t2, LTQ_MC_DDR_DC_OFFSET(3)(t1)
636 +
637 + /* Wait until DLL has locked and core is ready for data transfers */
638 +wait_ready:
639 + lw t2, LTQ_MC_GEN_STAT(t0)
640 + li t3, LTQ_MC_GEN_STAT_DLCK_PWRON
641 + and t2, t3
642 + bne t2, t3, wait_ready
643 +
644 +finished:
645 + jr ra
646 +
647 + END(ltq_mem_init)
648 diff --git a/arch/mips/cpu/mips32/arx100/pmu.c b/arch/mips/cpu/mips32/arx100/pmu.c
649 new file mode 100644
650 index 0000000..d2afe96
651 --- /dev/null
652 +++ b/arch/mips/cpu/mips32/arx100/pmu.c
653 @@ -0,0 +1,120 @@
654 +/*
655 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
656 + *
657 + * SPDX-License-Identifier: GPL-2.0+
658 + */
659 +
660 +#include <common.h>
661 +#include <asm/lantiq/io.h>
662 +#include <asm/lantiq/pm.h>
663 +#include <asm/arch/soc.h>
664 +
665 +#define LTQ_PMU_PWDCR_RESERVED 0xE00C200C
666 +
667 +#define LTQ_PMU_PWDCR_SWITCH (1 << 28)
668 +#define LTQ_PMU_PWDCR_USB1 (1 << 27)
669 +#define LTQ_PMU_PWDCR_USB1_PHY (1 << 26)
670 +#define LTQ_PMU_PWDCR_TDM (1 << 25)
671 +#define LTQ_PMU_PWDCR_DDR_MEM (1 << 24)
672 +#define LTQ_PMU_PWDCR_PPE_DP (1 << 23)
673 +#define LTQ_PMU_PWDCR_PPE_EMA (1 << 22)
674 +#define LTQ_PMU_PWDCR_PPE_TC (1 << 21)
675 +#define LTQ_PMU_PWDCR_DEU (1 << 20)
676 +#define LTQ_PMU_PWDCR_UART1 (1 << 17)
677 +#define LTQ_PMU_PWDCR_SDIO (1 << 16)
678 +#define LTQ_PMU_PWDCR_AHB (1 << 15)
679 +#define LTQ_PMU_PWDCR_FPI0 (1 << 14)
680 +#define LTQ_PMU_PWDCR_GPTC (1 << 12)
681 +#define LTQ_PMU_PWDCR_LEDC (1 << 11)
682 +#define LTQ_PMU_PWDCR_EBU (1 << 10)
683 +#define LTQ_PMU_PWDCR_DSL (1 << 9)
684 +#define LTQ_PMU_PWDCR_SPI (1 << 8)
685 +#define LTQ_PMU_PWDCR_UART0 (1 << 7)
686 +#define LTQ_PMU_PWDCR_USB (1 << 6)
687 +#define LTQ_PMU_PWDCR_DMA (1 << 5)
688 +#define LTQ_PMU_PWDCR_PCI (1 << 4)
689 +#define LTQ_PMU_PWDCR_FPI1 (1 << 1)
690 +#define LTQ_PMU_PWDCR_USB0_PHY (1 << 0)
691 +
692 +struct ltq_pmu_regs {
693 + u32 rsvd0[7];
694 + __be32 pwdcr;
695 + __be32 sr;
696 +};
697 +
698 +static struct ltq_pmu_regs *ltq_pmu_regs =
699 + (struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE);
700 +
701 +u32 ltq_pm_map(enum ltq_pm_modules module)
702 +{
703 + u32 val;
704 +
705 + switch (module) {
706 + case LTQ_PM_CORE:
707 + val = LTQ_PMU_PWDCR_DDR_MEM | LTQ_PMU_PWDCR_UART1 |
708 + LTQ_PMU_PWDCR_FPI0 | LTQ_PMU_PWDCR_LEDC |
709 + LTQ_PMU_PWDCR_EBU;
710 + break;
711 + case LTQ_PM_DMA:
712 + val = LTQ_PMU_PWDCR_DMA;
713 + break;
714 + case LTQ_PM_ETH:
715 + val = LTQ_PMU_PWDCR_SWITCH | LTQ_PMU_PWDCR_PPE_DP |
716 + LTQ_PMU_PWDCR_PPE_EMA | LTQ_PMU_PWDCR_PPE_TC;
717 + break;
718 + case LTQ_PM_SPI:
719 + val = LTQ_PMU_PWDCR_SPI;
720 + break;
721 + default:
722 + val = 0;
723 + break;
724 + }
725 +
726 + return val;
727 +}
728 +
729 +int ltq_pm_enable(enum ltq_pm_modules module)
730 +{
731 + const unsigned long timeout = 1000;
732 + unsigned long timebase;
733 + u32 sr, val;
734 +
735 + val = ltq_pm_map(module);
736 + if (unlikely(!val))
737 + return 1;
738 +
739 + ltq_clrbits(&ltq_pmu_regs->pwdcr, val);
740 +
741 + timebase = get_timer(0);
742 +
743 + do {
744 + sr = ltq_readl(&ltq_pmu_regs->sr);
745 + if (~sr & val)
746 + return 0;
747 + } while (get_timer(timebase) < timeout);
748 +
749 + return 1;
750 +}
751 +
752 +int ltq_pm_disable(enum ltq_pm_modules module)
753 +{
754 + u32 val;
755 +
756 + val = ltq_pm_map(module);
757 + if (unlikely(!val))
758 + return 1;
759 +
760 + ltq_setbits(&ltq_pmu_regs->pwdcr, val);
761 +
762 + return 0;
763 +}
764 +
765 +void ltq_pmu_init(void)
766 +{
767 + u32 set, clr;
768 +
769 + clr = ltq_pm_map(LTQ_PM_CORE);
770 + set = ~(LTQ_PMU_PWDCR_RESERVED | clr);
771 +
772 + ltq_clrsetbits(&ltq_pmu_regs->pwdcr, clr, set);
773 +}
774 diff --git a/arch/mips/cpu/mips32/arx100/rcu.c b/arch/mips/cpu/mips32/arx100/rcu.c
775 new file mode 100644
776 index 0000000..4ff6935
777 --- /dev/null
778 +++ b/arch/mips/cpu/mips32/arx100/rcu.c
779 @@ -0,0 +1,130 @@
780 +/*
781 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
782 + *
783 + * SPDX-License-Identifier: GPL-2.0+
784 + */
785 +
786 +#include <common.h>
787 +#include <asm/lantiq/io.h>
788 +#include <asm/lantiq/reset.h>
789 +#include <asm/lantiq/cpu.h>
790 +#include <asm/arch/soc.h>
791 +
792 +#define LTQ_RCU_RD_SRST (1 << 30) /* Global SW Reset */
793 +#define LTQ_RCU_RD_USB1 (1 << 28) /* USB1 MAC and PHY */
794 +#define LTQ_RCU_RD_REG25_PD (1 << 26) /* Power down 2.5V regulator */
795 +#define LTQ_RCU_RD_PPE_ATM_TC (1 << 22) /* PPE ATM TC */
796 +#define LTQ_RCU_RD_ETHSW (1 << 21) /* Ethernet switch */
797 +#define LTQ_RCU_RD_DSP_DEN (1 << 20) /* Enable DSP JTAG */
798 +#define LTQ_RCU_RD_TDM (1 << 19) /* TDM module interface */
799 +#define LTQ_RCU_RD_MC (1 << 14) /* Memory Controller */
800 +#define LTQ_RCU_RD_PCI (1 << 13) /* PCI core */
801 +#define LTQ_RCU_RD_SDIO (1 << 10) /* SDIO core */
802 +#define LTQ_RCU_RD_DMA (1 << 9) /* DMA core */
803 +#define LTQ_RCU_RD_PPE (1 << 8) /* PPE core */
804 +#define LTQ_RCU_RD_ARC_DFE (1 << 7) /* ARC/DFE core */
805 +#define LTQ_RCU_RD_AHB (1 << 6) /* AHB bus */
806 +#define LTQ_RCU_RD_USB (1 << 4) /* USB and Phy core */
807 +#define LTQ_RCU_RD_FPI (1 << 2) /* FPI bus */
808 +#define LTQ_RCU_RD_CPU0 (1 << 1) /* CPU0 subsystem */
809 +#define LTQ_RCU_RD_HRST (1 << 0) /* HW reset via HRST pin */
810 +
811 +#define LTQ_RCU_STAT_BOOT_SHIFT 17
812 +#define LTQ_RCU_STAT_BOOT_MASK (0xf << LTQ_RCU_STAT_BOOT_SHIFT)
813 +
814 +struct ltq_rcu_regs {
815 + u32 rsvd0[4];
816 + __be32 req; /* Reset request */
817 + __be32 stat; /* Reset status */
818 + __be32 usb0_cfg; /* USB0 config */
819 + u32 rsvd1[2];
820 + __be32 pci_rdy; /* PCI boot ready */
821 + __be32 ppe_conf; /* PPE config */
822 + u32 rsvd2;
823 + __be32 usb1_cfg; /* USB1 config */
824 +};
825 +
826 +static struct ltq_rcu_regs *ltq_rcu_regs =
827 + (struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE);
828 +
829 +u32 ltq_reset_map(enum ltq_reset_modules module)
830 +{
831 + u32 val;
832 +
833 + switch (module) {
834 + case LTQ_RESET_CORE:
835 + case LTQ_RESET_SOFT:
836 + val = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU0;
837 + break;
838 + case LTQ_RESET_DMA:
839 + val = LTQ_RCU_RD_DMA;
840 + break;
841 + case LTQ_RESET_ETH:
842 + val = LTQ_RCU_RD_PPE | LTQ_RCU_RD_ETHSW;
843 + break;
844 + case LTQ_RESET_HARD:
845 + val = LTQ_RCU_RD_HRST;
846 + break;
847 + default:
848 + val = 0;
849 + break;
850 + }
851 +
852 + return val;
853 +}
854 +
855 +int ltq_reset_activate(enum ltq_reset_modules module)
856 +{
857 + u32 val;
858 +
859 + val = ltq_reset_map(module);
860 + if (unlikely(!val))
861 + return 1;
862 +
863 + ltq_setbits(&ltq_rcu_regs->req, val);
864 +
865 + return 0;
866 +}
867 +
868 +int ltq_reset_deactivate(enum ltq_reset_modules module)
869 +{
870 + u32 val;
871 +
872 + val = ltq_reset_map(module);
873 + if (unlikely(!val))
874 + return 1;
875 +
876 + ltq_clrbits(&ltq_rcu_regs->req, val);
877 +
878 + return 0;
879 +}
880 +
881 +enum ltq_boot_select ltq_boot_select(void)
882 +{
883 + u32 stat;
884 + unsigned int bootstrap;
885 +
886 + stat = ltq_readl(&ltq_rcu_regs->stat);
887 + bootstrap = (stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT;
888 +
889 + switch (bootstrap) {
890 + case 0:
891 + return BOOT_NOR_NO_BOOTROM;
892 + case 1:
893 + return BOOT_RGMII0;
894 + case 2:
895 + return BOOT_NOR;
896 + case 3:
897 + return BOOT_MII0;
898 + case 5:
899 + return BOOT_RMII0;
900 + case 6:
901 + return BOOT_PCI;
902 + case 8:
903 + return BOOT_UART;
904 + case 10:
905 + return BOOT_SPI;
906 + default:
907 + return BOOT_UNKNOWN;
908 + }
909 +}
910 diff --git a/arch/mips/cpu/mips32/lantiq-common/cpu.c b/arch/mips/cpu/mips32/lantiq-common/cpu.c
911 index 4a7acdf..aa37b35 100644
912 --- a/arch/mips/cpu/mips32/lantiq-common/cpu.c
913 +++ b/arch/mips/cpu/mips32/lantiq-common/cpu.c
914 @@ -20,6 +20,7 @@ static const char ltq_bootsel_strings[][16] = {
915 "PCI",
916 "MII0",
917 "RMII0",
918 + "RGMII0",
919 "RGMII1",
920 "unknown",
921 };
922 diff --git a/arch/mips/cpu/mips32/lantiq-common/start.S b/arch/mips/cpu/mips32/lantiq-common/start.S
923 index 481d739..fc8276e 100644
924 --- a/arch/mips/cpu/mips32/lantiq-common/start.S
925 +++ b/arch/mips/cpu/mips32/lantiq-common/start.S
926 @@ -64,6 +64,11 @@
927 #define STATUS_LANTIQ (STATUS_MIPS24K | STATUS_MIPS32_64)
928 #endif
929
930 +#ifdef CONFIG_SOC_XWAY_ARX100
931 +#define CONFIG0_LANTIQ (CONFIG0_MIPS34K | CONFIG0_MIPS32_64)
932 +#define STATUS_LANTIQ (STATUS_MIPS34K | STATUS_MIPS32_64)
933 +#endif
934 +
935 #ifdef CONFIG_SOC_XWAY_VRX200
936 #define CONFIG0_LANTIQ (CONFIG0_MIPS34K | CONFIG0_MIPS32_64)
937 #define STATUS_LANTIQ (STATUS_MIPS34K | STATUS_MIPS32_64)
938 diff --git a/arch/mips/include/asm/arch-arx100/config.h b/arch/mips/include/asm/arch-arx100/config.h
939 new file mode 100644
940 index 0000000..1a6c9bc
941 --- /dev/null
942 +++ b/arch/mips/include/asm/arch-arx100/config.h
943 @@ -0,0 +1,175 @@
944 +/*
945 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
946 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
947 + *
948 + * SPDX-License-Identifier: GPL-2.0+
949 + *
950 + * Common board configuration for Lantiq XWAY ARX100 family
951 + *
952 + * Use following defines in your board config to enable specific features
953 + * and drivers for this SoC:
954 + *
955 + * CONFIG_LTQ_SUPPORT_UART
956 + * - support the Danube ASC/UART interface and console
957 + *
958 + * CONFIG_LTQ_SUPPORT_NOR_FLASH
959 + * - support a parallel NOR flash via the CFI interface in flash bank 0
960 + *
961 + * CONFIG_LTQ_SUPPORT_ETHERNET
962 + * - support the Danube ETOP and MAC interface
963 + *
964 + * CONFIG_LTQ_SUPPORT_SPI_FLASH
965 + * - support the Danube SPI interface and serial flash drivers
966 + * - specific SPI flash drivers must be configured separately
967 + */
968 +
969 +#ifndef __ARX100_CONFIG_H__
970 +#define __ARX100_CONFIG_H__
971 +
972 +/* CPU and SoC type */
973 +#define CONFIG_SOC_LANTIQ
974 +#define CONFIG_SOC_XWAY_ARX100
975 +
976 +/* Cache configuration */
977 +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
978 +#define CONFIG_SYS_DCACHE_SIZE (16 * 1024)
979 +#define CONFIG_SYS_ICACHE_SIZE (32 * 1024)
980 +#define CONFIG_SYS_CACHELINE_SIZE 32
981 +#define CONFIG_SYS_MIPS_CACHE_EXT_INIT
982 +
983 +/*
984 + * Supported clock modes
985 + * PLL0: rational PLL running at 500 MHz
986 + * PLL1: fractional PLL running at 393.219 MHz
987 + */
988 +#define LTQ_CLK_CPU_393_DDR_197 0
989 +#define LTQ_CLK_CPU_197_DDR_197 1
990 +#define LTQ_CLK_CPU_333_DDR_167 2
991 +#define LTQ_CLK_CPU_167_DDR_167 3
992 +#define LTQ_CLK_CPU_131_DDR_131 4
993 +#define LTQ_CLK_CPU_111_DDR_111 5
994 +
995 +/* CPU speed */
996 +#define CONFIG_SYS_CLOCK_MODE LTQ_CLK_CPU_333_DDR_167
997 +#define CONFIG_SYS_MIPS_TIMER_FREQ 166666667
998 +#define CONFIG_SYS_HZ 1000
999 +
1000 +/* RAM */
1001 +#define CONFIG_NR_DRAM_BANKS 1
1002 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
1003 +#define CONFIG_SYS_SDRAM_BASE_UC 0xa0000000
1004 +#define CONFIG_SYS_MEMTEST_START 0x81000000
1005 +#define CONFIG_SYS_MEMTEST_END 0x82000000
1006 +#define CONFIG_SYS_LOAD_ADDR 0x81000000
1007 +#define CONFIG_SYS_INIT_SP_OFFSET (32 * 1024)
1008 +
1009 +/* SRAM */
1010 +#define CONFIG_SYS_SRAM_BASE 0xBE1A0000
1011 +#define CONFIG_SYS_SRAM_SIZE 0x10000
1012 +
1013 +/* ASC/UART driver and console */
1014 +#define CONFIG_LANTIQ_SERIAL
1015 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
1016 +
1017 +/* GPIO */
1018 +#define CONFIG_LANTIQ_GPIO
1019 +#define CONFIG_LTQ_GPIO_MAX_BANKS 3
1020 +#define CONFIG_LTQ_HAS_GPIO_BANK3
1021 +
1022 +/* FLASH driver */
1023 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
1024 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
1025 +#define CONFIG_SYS_MAX_FLASH_SECT 256
1026 +#define CONFIG_SYS_FLASH_BASE 0xB0000000
1027 +#define CONFIG_FLASH_16BIT
1028 +#define CONFIG_SYS_FLASH_CFI
1029 +#define CONFIG_FLASH_CFI_DRIVER
1030 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
1031 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
1032 +#define CONFIG_FLASH_SHOW_PROGRESS 50
1033 +#define CONFIG_SYS_FLASH_PROTECTION
1034 +#define CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP
1035 +
1036 +#define CONFIG_CMD_FLASH
1037 +#else
1038 +#define CONFIG_SYS_NO_FLASH
1039 +#endif /* CONFIG_NOR_FLASH */
1040 +
1041 +#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)
1042 +#define CONFIG_LANTIQ_SPI
1043 +#define CONFIG_SPI_FLASH
1044 +
1045 +#define CONFIG_CMD_SF
1046 +#define CONFIG_CMD_SPI
1047 +#endif
1048 +
1049 +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
1050 +#define CONFIG_NAND_LANTIQ
1051 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
1052 +#define CONFIG_SYS_NAND_BASE 0xB4000000
1053 +
1054 +#define CONFIG_CMD_NAND
1055 +#endif
1056 +
1057 +#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)
1058 +#define CONFIG_LANTIQ_DMA
1059 +#define CONFIG_LANTIQ_ARX100_SWITCH
1060 +
1061 +#define CONFIG_PHYLIB
1062 +#define CONFIG_MII
1063 +#define CONFIG_UDP_CHECKSUM
1064 +
1065 +#define CONFIG_CMD_MII
1066 +#define CONFIG_CMD_NET
1067 +#endif
1068 +
1069 +#define CONFIG_SPL_MAX_SIZE (32 * 1024)
1070 +#define CONFIG_SPL_BSS_MAX_SIZE (8 * 1024)
1071 +#define CONFIG_SPL_STACK_MAX_SIZE (8 * 1024)
1072 +#define CONFIG_SPL_MALLOC_MAX_SIZE (32 * 1024)
1073 +#define CONFIG_SPL_STACK_BSS_IN_SRAM
1074 +
1075 +#if defined(CONFIG_SPL_STACK_BSS_IN_SRAM)
1076 +#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SRAM_BASE + \
1077 + CONFIG_SPL_MAX_SIZE + \
1078 + CONFIG_SPL_STACK_MAX_SIZE - 1)
1079 +#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1)
1080 +#define CONFIG_SPL_MALLOC_BASE (CONFIG_SYS_SDRAM_BASE + \
1081 + CONFIG_SYS_INIT_SP_OFFSET)
1082 +#else
1083 +#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SDRAM_BASE + \
1084 + CONFIG_SYS_INIT_SP_OFFSET + \
1085 + CONFIG_SPL_STACK_MAX_SIZE - 1)
1086 +#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1)
1087 +#define CONFIG_SPL_MALLOC_BASE (CONFIG_SPL_BSS_BASE + \
1088 + CONFIG_SPL_BSS_MAX_SIZE)
1089 +#endif
1090 +
1091 +#if defined(CONFIG_SYS_BOOT_RAM)
1092 +#define CONFIG_SYS_TEXT_BASE 0xA0100000
1093 +#define CONFIG_SKIP_LOWLEVEL_INIT
1094 +#define CONFIG_SYS_DISABLE_CACHE
1095 +#endif
1096 +
1097 +#if defined(CONFIG_SYS_BOOT_NOR)
1098 +#define CONFIG_SYS_TEXT_BASE 0xB0000000
1099 +#endif
1100 +
1101 +#if defined(CONFIG_SYS_BOOT_SFSPL) || defined(CONFIG_SYS_BOOT_NANDSPL)
1102 +#define CONFIG_SYS_TEXT_BASE 0x80100000
1103 +#define CONFIG_SPL_TEXT_BASE 0xBE1A0000
1104 +#endif
1105 +
1106 +#if defined(CONFIG_SYS_BOOT_NORSPL)
1107 +#define CONFIG_SYS_TEXT_BASE 0x80100000
1108 +#define CONFIG_SPL_TEXT_BASE 0xB0000000
1109 +#endif
1110 +
1111 +#if defined(CONFIG_SYS_BOOT_NOR) || defined(CONFIG_SYS_BOOT_NORSPL)
1112 +#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x688C688C
1113 +#define CONFIG_XWAY_SWAP_BYTES
1114 +#endif
1115 +
1116 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
1117 +
1118 +#endif /* __ARX100_CONFIG_H__ */
1119 diff --git a/arch/mips/include/asm/arch-arx100/gpio.h b/arch/mips/include/asm/arch-arx100/gpio.h
1120 new file mode 100644
1121 index 0000000..f6b6409
1122 --- /dev/null
1123 +++ b/arch/mips/include/asm/arch-arx100/gpio.h
1124 @@ -0,0 +1,12 @@
1125 +/*
1126 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1127 + *
1128 + * SPDX-License-Identifier: GPL-2.0+
1129 + */
1130 +
1131 +#ifndef __ARX100_GPIO_H__
1132 +#define __ARX100_GPIO_H__
1133 +
1134 +#include <asm/lantiq/gpio.h>
1135 +
1136 +#endif /* __ARX100_GPIO_H__ */
1137 diff --git a/arch/mips/include/asm/arch-arx100/nand.h b/arch/mips/include/asm/arch-arx100/nand.h
1138 new file mode 100644
1139 index 0000000..231b68f
1140 --- /dev/null
1141 +++ b/arch/mips/include/asm/arch-arx100/nand.h
1142 @@ -0,0 +1,13 @@
1143 +/*
1144 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1145 + *
1146 + * SPDX-License-Identifier: GPL-2.0+
1147 + */
1148 +
1149 +#ifndef __VRX200_NAND_H__
1150 +#define __VRX200_NAND_H__
1151 +
1152 +struct nand_chip;
1153 +int ltq_nand_init(struct nand_chip *nand);
1154 +
1155 +#endif /* __VRX200_NAND_H__ */
1156 diff --git a/arch/mips/include/asm/arch-arx100/soc.h b/arch/mips/include/asm/arch-arx100/soc.h
1157 new file mode 100644
1158 index 0000000..3ccaf3f
1159 --- /dev/null
1160 +++ b/arch/mips/include/asm/arch-arx100/soc.h
1161 @@ -0,0 +1,37 @@
1162 +/*
1163 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
1164 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1165 + *
1166 + * SPDX-License-Identifier: GPL-2.0+
1167 + */
1168 +
1169 +#ifndef __ARX100_SOC_H__
1170 +#define __ARX100_SOC_H__
1171 +
1172 +#define LTQ_ASC0_BASE 0x1E100400
1173 +#define LTQ_SPI_BASE 0x1E100800
1174 +#define LTQ_GPIO_BASE 0x1E100B00
1175 +#define LTQ_SSIO_BASE 0x1E100BB0
1176 +#define LTQ_ASC1_BASE 0x1E100C00
1177 +#define LTQ_DMA_BASE 0x1E104100
1178 +
1179 +#define LTQ_EBU_BASE 0x1E105300
1180 +#define LTQ_EBU_REGION0_BASE 0x10000000
1181 +#define LTQ_EBU_REGION1_BASE 0x14000000
1182 +#define LTQ_EBU_NAND_BASE (LTQ_EBU_BASE + 0xB0)
1183 +
1184 +#define LTQ_PPE_BASE 0x1E180000
1185 +#define LTQ_SWITCH_BASE 0x1E108000
1186 +
1187 +#define LTQ_PMU_BASE 0x1F102000
1188 +#define LTQ_CGU_BASE 0x1F103000
1189 +#define LTQ_MPS_BASE 0x1F107000
1190 +#define LTQ_CHIPID_BASE (LTQ_MPS_BASE + 0x340)
1191 +#define LTQ_RCU_BASE 0x1F203000
1192 +
1193 +#define LTQ_MC_GEN_BASE 0x1F800000
1194 +#define LTQ_MC_SDR_BASE 0x1F800200
1195 +#define LTQ_MC_DDR_BASE 0x1F801000
1196 +#define LTQ_MC_DDR_DC_OFFSET(x) (x * 0x10)
1197 +
1198 +#endif /* __ARX100_SOC_H__ */
1199 diff --git a/arch/mips/include/asm/lantiq/chipid.h b/arch/mips/include/asm/lantiq/chipid.h
1200 index c9921b0..19adf97 100644
1201 --- a/arch/mips/include/asm/lantiq/chipid.h
1202 +++ b/arch/mips/include/asm/lantiq/chipid.h
1203 @@ -15,6 +15,10 @@ enum ltq_chip_partnum {
1204 LTQ_SOC_DANUBE = 0x0129,
1205 LTQ_SOC_DANUBE_S = 0x012B,
1206 LTQ_SOC_TWINPASS = 0x012D,
1207 + LTQ_SOC_ARX188 = 0x016C, /* ARX188 */
1208 + LTQ_SOC_ARX186 = 0x016D, /* ARX186 v1.1 */
1209 + LTQ_SOC_ARX186_2 = 0x016E, /* ARX186 v1.2 */
1210 + LTQ_SOC_ARX182 = 0x016F, /* ARX182 */
1211 LTQ_SOC_VRX288 = 0x01C0, /* VRX288 v1.1 */
1212 LTQ_SOC_VRX268 = 0x01C2, /* VRX268 v1.1 */
1213 LTQ_SOC_GRX288 = 0x01C9, /* GRX288 v1.1 */
1214 @@ -38,6 +42,38 @@ static inline int ltq_soc_is_danube(void)
1215 }
1216 #endif
1217
1218 +#ifdef CONFIG_SOC_XWAY_ARX100
1219 +static inline int ltq_soc_is_arx100(void)
1220 +{
1221 + return 1;
1222 +}
1223 +
1224 +static inline int ltq_soc_is_arx100_v1(void)
1225 +{
1226 + return ltq_chip_version_get() == 1;
1227 +}
1228 +
1229 +static inline int ltq_soc_is_arx100_v2(void)
1230 +{
1231 + return ltq_chip_version_get() == 2;
1232 +}
1233 +#else
1234 +static inline int ltq_soc_is_arx100(void)
1235 +{
1236 + return 0;
1237 +}
1238 +
1239 +static inline int ltq_soc_is_arx100_v1(void)
1240 +{
1241 + return 0;
1242 +}
1243 +
1244 +static inline int ltq_soc_is_arx100_v2(void)
1245 +{
1246 + return 0;
1247 +}
1248 +#endif
1249 +
1250 #ifdef CONFIG_SOC_XWAY_VRX200
1251 static inline int ltq_soc_is_vrx200(void)
1252 {
1253 diff --git a/arch/mips/include/asm/lantiq/clk.h b/arch/mips/include/asm/lantiq/clk.h
1254 index e13f000..5aea603 100644
1255 --- a/arch/mips/include/asm/lantiq/clk.h
1256 +++ b/arch/mips/include/asm/lantiq/clk.h
1257 @@ -13,9 +13,10 @@ enum ltq_clk {
1258 CLOCK_83_MHZ = 83333333,
1259 CLOCK_111_MHZ = 111111111,
1260 CLOCK_125_MHZ = 125000000,
1261 + CLOCK_131_MHZ = 131073000,
1262 CLOCK_133_MHZ = 133333333,
1263 CLOCK_166_MHZ = 166666667,
1264 - CLOCK_197_MHZ = 197000000,
1265 + CLOCK_197_MHZ = 196609500,
1266 CLOCK_333_MHZ = 333333333,
1267 CLOCK_393_MHZ = 393219000,
1268 CLOCK_500_MHZ = 500000000,
1269 diff --git a/arch/mips/include/asm/lantiq/cpu.h b/arch/mips/include/asm/lantiq/cpu.h
1270 index b3a504e..e3b0312 100644
1271 --- a/arch/mips/include/asm/lantiq/cpu.h
1272 +++ b/arch/mips/include/asm/lantiq/cpu.h
1273 @@ -17,6 +17,7 @@ enum ltq_boot_select {
1274 BOOT_PCI,
1275 BOOT_MII0,
1276 BOOT_RMII0,
1277 + BOOT_RGMII0,
1278 BOOT_RGMII1,
1279 BOOT_UNKNOWN,
1280 };
1281 --
1282 1.8.3.2
1283