uboot-lantiq: update to v2013.10
[openwrt/svn-archive/archive.git] / package / boot / uboot-lantiq / patches / 0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch
1 From 37a95ae4ba75407a26862ece6f48fa68aa6c5c78 Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Sat, 2 Mar 2013 23:34:00 +0100
4 Subject: MIPS: add board support for AVM FritzBox 3370
5
6 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
7
8 diff --git a/board/avm/fb3370/Makefile b/board/avm/fb3370/Makefile
9 new file mode 100644
10 index 0000000..e3d621e
11 --- /dev/null
12 +++ b/board/avm/fb3370/Makefile
13 @@ -0,0 +1,28 @@
14 +#
15 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
16 +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
17 +#
18 +# SPDX-License-Identifier: GPL-2.0+
19 +#
20 +
21 +include $(TOPDIR)/config.mk
22 +
23 +LIB = $(obj)lib$(BOARD).o
24 +
25 +COBJS = $(BOARD).o
26 +
27 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
28 +OBJS := $(addprefix $(obj),$(COBJS))
29 +SOBJS := $(addprefix $(obj),$(SOBJS))
30 +
31 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
32 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
33 +
34 +#########################################################################
35 +
36 +# defines $(obj).depend target
37 +include $(SRCTREE)/rules.mk
38 +
39 +sinclude $(obj).depend
40 +
41 +#########################################################################
42 diff --git a/board/avm/fb3370/config.mk b/board/avm/fb3370/config.mk
43 new file mode 100644
44 index 0000000..4dcfd05
45 --- /dev/null
46 +++ b/board/avm/fb3370/config.mk
47 @@ -0,0 +1,7 @@
48 +#
49 +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
50 +#
51 +# SPDX-License-Identifier: GPL-2.0+
52 +#
53 +
54 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
55 diff --git a/board/avm/fb3370/ddr_settings.h b/board/avm/fb3370/ddr_settings.h
56 new file mode 100644
57 index 0000000..307c084
58 --- /dev/null
59 +++ b/board/avm/fb3370/ddr_settings.h
60 @@ -0,0 +1,69 @@
61 +/*
62 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
63 + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
64 + *
65 + * SPDX-License-Identifier: GPL-2.0+
66 + */
67 +
68 +#define MC_CCR00_VALUE 0x101
69 +#define MC_CCR01_VALUE 0x1000100
70 +#define MC_CCR02_VALUE 0x1010000
71 +#define MC_CCR03_VALUE 0x101
72 +#define MC_CCR04_VALUE 0x1000000
73 +#define MC_CCR05_VALUE 0x1000101
74 +#define MC_CCR06_VALUE 0x1000100
75 +#define MC_CCR07_VALUE 0x1010000
76 +#define MC_CCR08_VALUE 0x1000101
77 +#define MC_CCR09_VALUE 0x0
78 +#define MC_CCR10_VALUE 0x2000100
79 +#define MC_CCR11_VALUE 0x2000300
80 +#define MC_CCR12_VALUE 0x30000
81 +#define MC_CCR13_VALUE 0x202
82 +#define MC_CCR14_VALUE 0x7080A0F
83 +#define MC_CCR15_VALUE 0x2040F
84 +#define MC_CCR16_VALUE 0x40000
85 +#define MC_CCR17_VALUE 0x70102
86 +#define MC_CCR18_VALUE 0x4020002
87 +#define MC_CCR19_VALUE 0x30302
88 +#define MC_CCR20_VALUE 0x8000700
89 +#define MC_CCR21_VALUE 0x40F020A
90 +#define MC_CCR22_VALUE 0x0
91 +#define MC_CCR23_VALUE 0xC020000
92 +#define MC_CCR24_VALUE 0x4401B04
93 +#define MC_CCR25_VALUE 0x0
94 +#define MC_CCR26_VALUE 0x0
95 +#define MC_CCR27_VALUE 0x6420000
96 +#define MC_CCR28_VALUE 0x0
97 +#define MC_CCR29_VALUE 0x0
98 +#define MC_CCR30_VALUE 0x798
99 +#define MC_CCR31_VALUE 0x0
100 +#define MC_CCR32_VALUE 0x0
101 +#define MC_CCR33_VALUE 0x650000
102 +#define MC_CCR34_VALUE 0x200C8
103 +#define MC_CCR35_VALUE 0x1D445D
104 +#define MC_CCR36_VALUE 0xC8
105 +#define MC_CCR37_VALUE 0xC351
106 +#define MC_CCR38_VALUE 0x0
107 +#define MC_CCR39_VALUE 0x141F04
108 +#define MC_CCR40_VALUE 0x142704
109 +#define MC_CCR41_VALUE 0x141B42
110 +#define MC_CCR42_VALUE 0x141B42
111 +#define MC_CCR43_VALUE 0x566504
112 +#define MC_CCR44_VALUE 0x566504
113 +#define MC_CCR45_VALUE 0x565F17
114 +#define MC_CCR46_VALUE 0x565F17
115 +#define MC_CCR47_VALUE 0x0
116 +#define MC_CCR48_VALUE 0x0
117 +#define MC_CCR49_VALUE 0x0
118 +#define MC_CCR50_VALUE 0x0
119 +#define MC_CCR51_VALUE 0x0
120 +#define MC_CCR52_VALUE 0x133
121 +#define MC_CCR53_VALUE 0xF3014B27
122 +#define MC_CCR54_VALUE 0xF3014B27
123 +#define MC_CCR55_VALUE 0xF3014B27
124 +#define MC_CCR56_VALUE 0xF3014B27
125 +#define MC_CCR57_VALUE 0x7800301
126 +#define MC_CCR58_VALUE 0x7800301
127 +#define MC_CCR59_VALUE 0x7800301
128 +#define MC_CCR60_VALUE 0x7800301
129 +#define MC_CCR61_VALUE 0x4
130 diff --git a/board/avm/fb3370/fb3370.c b/board/avm/fb3370/fb3370.c
131 new file mode 100644
132 index 0000000..ff44c68
133 --- /dev/null
134 +++ b/board/avm/fb3370/fb3370.c
135 @@ -0,0 +1,138 @@
136 +/*
137 + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
138 + *
139 + * SPDX-License-Identifier: GPL-2.0+
140 + */
141 +
142 +#include <common.h>
143 +#include <spi.h>
144 +#include <asm/gpio.h>
145 +#include <asm/lantiq/eth.h>
146 +#include <asm/lantiq/chipid.h>
147 +#include <asm/lantiq/cpu.h>
148 +#include <asm/arch/gphy.h>
149 +
150 +#if defined(CONFIG_SPL_BUILD)
151 +#define do_gpio_init 1
152 +#define do_pll_init 1
153 +#define do_dcdc_init 0
154 +#elif defined(CONFIG_SYS_BOOT_RAM)
155 +#define do_gpio_init 1
156 +#define do_pll_init 0
157 +#define do_dcdc_init 1
158 +#elif defined(CONFIG_SYS_BOOT_NOR)
159 +#define do_gpio_init 1
160 +#define do_pll_init 1
161 +#define do_dcdc_init 1
162 +#else
163 +#define do_gpio_init 0
164 +#define do_pll_init 0
165 +#define do_dcdc_init 1
166 +#endif
167 +
168 +static void gpio_init(void)
169 +{
170 + /* SPI CS 0.4 to serial flash */
171 + gpio_direction_output(10, 1);
172 +
173 + /* EBU.FL_CS1 as output for NAND CE */
174 + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
175 + /* EBU.FL_A23 as output for NAND CLE */
176 + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
177 + /* EBU.FL_A24 as output for NAND ALE */
178 + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
179 + /* GPIO 3.0 as input for NAND Ready Busy */
180 + gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
181 + /* GPIO 3.1 as output for NAND Read */
182 + gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
183 +}
184 +
185 +int board_early_init_f(void)
186 +{
187 + if (do_gpio_init)
188 + gpio_init();
189 +
190 + if (do_pll_init)
191 + ltq_pll_init();
192 +
193 + if (do_dcdc_init)
194 + ltq_dcdc_init(0x7F);
195 +
196 + return 0;
197 +}
198 +
199 +int checkboard(void)
200 +{
201 + puts("Board: " CONFIG_BOARD_NAME "\n");
202 + ltq_chip_print_info();
203 +
204 + return 0;
205 +}
206 +
207 +static const struct ltq_eth_port_config eth_port_config[] = {
208 + /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
209 + { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
210 + /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
211 + { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
212 + /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
213 + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
214 + /* GMAC3: unused */
215 + { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
216 + /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
217 + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
218 + /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
219 + { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
220 +};
221 +
222 +static const struct ltq_eth_board_config eth_board_config = {
223 + .ports = eth_port_config,
224 + .num_ports = ARRAY_SIZE(eth_port_config),
225 +};
226 +
227 +int board_eth_init(bd_t * bis)
228 +{
229 + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
230 + const ulong fw_addr = 0x80FF0000;
231 +
232 + ltq_gphy_phy11g_a1x_load(fw_addr);
233 +
234 + ltq_cgu_gphy_clk_src(clk);
235 +
236 + ltq_rcu_gphy_boot(0, fw_addr);
237 + ltq_rcu_gphy_boot(1, fw_addr);
238 +
239 + return ltq_eth_initialize(&eth_board_config);
240 +}
241 +
242 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
243 +{
244 + if (bus)
245 + return 0;
246 +
247 + if (cs == 4)
248 + return 1;
249 +
250 + return 0;
251 +}
252 +
253 +void spi_cs_activate(struct spi_slave *slave)
254 +{
255 + switch (slave->cs) {
256 + case 4:
257 + gpio_set_value(10, 0);
258 + break;
259 + default:
260 + break;
261 + }
262 +}
263 +
264 +void spi_cs_deactivate(struct spi_slave *slave)
265 +{
266 + switch (slave->cs) {
267 + case 4:
268 + gpio_set_value(10, 1);
269 + break;
270 + default:
271 + break;
272 + }
273 +}
274 diff --git a/boards.cfg b/boards.cfg
275 index 9f407b8..ea5c4f9 100644
276 --- a/boards.cfg
277 +++ b/boards.cfg
278 @@ -517,6 +517,9 @@ Active mips mips32 incaip - incaip
279 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
280 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
281 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
282 +Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
283 +Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
284 +Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
285 Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
286 Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
287 Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
288 diff --git a/include/configs/fb3370.h b/include/configs/fb3370.h
289 new file mode 100644
290 index 0000000..8ae1373
291 --- /dev/null
292 +++ b/include/configs/fb3370.h
293 @@ -0,0 +1,78 @@
294 +/*
295 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
296 + *
297 + * SPDX-License-Identifier: GPL-2.0+
298 + */
299 +
300 +#ifndef __CONFIG_H
301 +#define __CONFIG_H
302 +
303 +#define CONFIG_MACH_TYPE "FB3370"
304 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
305 +#define CONFIG_BOARD_NAME "AVM FritzBox 3370"
306 +
307 +/* Configure SoC */
308 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
309 +
310 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
311 +
312 +#define CONFIG_LTQ_SUPPORT_SPI_FLASH
313 +#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
314 +
315 +#define CONFIG_LTQ_SUPPORT_NAND_FLASH
316 +
317 +#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
318 +#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
319 +#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
320 +
321 +#define CONFIG_SPL_SPI_BUS 0
322 +#define CONFIG_SPL_SPI_CS 4
323 +#define CONFIG_SPL_SPI_MAX_HZ 25000000
324 +#define CONFIG_SPL_SPI_MODE 0
325 +
326 +#define CONFIG_SYS_DRAM_PROBE
327 +
328 +/* Environment */
329 +#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
330 +#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
331 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
332 +#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
333 +
334 +#if defined(CONFIG_SYS_BOOT_SFSPL)
335 +#define CONFIG_ENV_IS_IN_SPI_FLASH
336 +#define CONFIG_ENV_OVERWRITE
337 +#define CONFIG_ENV_OFFSET (192 * 1024)
338 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
339 +#else
340 +#define CONFIG_ENV_IS_NOWHERE
341 +#endif
342 +
343 +#define CONFIG_ENV_SIZE (8 * 1024)
344 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
345 +
346 +#if defined(CONFIG_SYS_BOOT_EVA)
347 +#define CONFIG_SYS_TEXT_BASE 0x80100000
348 +#define CONFIG_SKIP_LOWLEVEL_INIT
349 +#endif
350 +
351 +/* Console */
352 +#define CONFIG_LTQ_ADVANCED_CONSOLE
353 +#define CONFIG_BAUDRATE 115200
354 +#define CONFIG_CONSOLE_ASC 1
355 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
356 +
357 +/* Pull in default board configs for Lantiq XWAY VRX200 */
358 +#include <asm/lantiq/config.h>
359 +#include <asm/arch/config.h>
360 +
361 +/* Pull in default OpenWrt configs for Lantiq SoC */
362 +#include "openwrt-lantiq-common.h"
363 +
364 +#define CONFIG_ENV_UPDATE_UBOOT_SF \
365 + "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
366 +
367 +#define CONFIG_EXTRA_ENV_SETTINGS \
368 + CONFIG_ENV_LANTIQ_DEFAULTS \
369 + CONFIG_ENV_UPDATE_UBOOT_SF
370 +
371 +#endif /* __CONFIG_H */
372 --
373 1.8.3.2
374