uboot-lantiq: update to v2013.10
[openwrt/svn-archive/archive.git] / package / boot / uboot-lantiq / patches / 0031-MIPS-add-board-support-for-ZTE-ZXHN-H367N.patch
1 From 0597056e2ba19ea783ef5c3d14c75c4722740e48 Mon Sep 17 00:00:00 2001
2 From: Luka Perkov <luka@openwrt.org>
3 Date: Sun, 10 Mar 2013 17:59:56 +0100
4 Subject: MIPS: add board support for ZTE ZXHN H367N
5
6 Signed-off-by: Luka Perkov <luka@openwrt.org>
7
8 diff --git a/board/zte/zxhnh367n/Makefile b/board/zte/zxhnh367n/Makefile
9 new file mode 100644
10 index 0000000..3a547c2
11 --- /dev/null
12 +++ b/board/zte/zxhnh367n/Makefile
13 @@ -0,0 +1,27 @@
14 +#
15 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
16 +#
17 +# SPDX-License-Identifier: GPL-2.0+
18 +#
19 +
20 +include $(TOPDIR)/config.mk
21 +
22 +LIB = $(obj)lib$(BOARD).o
23 +
24 +COBJS = $(BOARD).o
25 +
26 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
27 +OBJS := $(addprefix $(obj),$(COBJS))
28 +SOBJS := $(addprefix $(obj),$(SOBJS))
29 +
30 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
31 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
32 +
33 +#########################################################################
34 +
35 +# defines $(obj).depend target
36 +include $(SRCTREE)/rules.mk
37 +
38 +sinclude $(obj).depend
39 +
40 +#########################################################################
41 diff --git a/board/zte/zxhnh367n/config.mk b/board/zte/zxhnh367n/config.mk
42 new file mode 100644
43 index 0000000..9d33739
44 --- /dev/null
45 +++ b/board/zte/zxhnh367n/config.mk
46 @@ -0,0 +1,7 @@
47 +#
48 +# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
49 +#
50 +# SPDX-License-Identifier: GPL-2.0+
51 +#
52 +
53 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
54 diff --git a/board/zte/zxhnh367n/ddr_settings.h b/board/zte/zxhnh367n/ddr_settings.h
55 new file mode 100644
56 index 0000000..b3f81de
57 --- /dev/null
58 +++ b/board/zte/zxhnh367n/ddr_settings.h
59 @@ -0,0 +1,70 @@
60 +/*
61 + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
62 + *
63 + * The values have been extracted from original ZTE U-Boot.
64 + *
65 + * SPDX-License-Identifier: GPL-2.0+
66 + */
67 +
68 +#define MC_CCR00_VALUE 0x101
69 +#define MC_CCR01_VALUE 0x1000101
70 +#define MC_CCR02_VALUE 0x1010000
71 +#define MC_CCR03_VALUE 0x100
72 +#define MC_CCR04_VALUE 0x1000000
73 +#define MC_CCR05_VALUE 0x1000101
74 +#define MC_CCR06_VALUE 0x1000100
75 +#define MC_CCR07_VALUE 0x1010000
76 +#define MC_CCR08_VALUE 0x1000101
77 +#define MC_CCR09_VALUE 0x0
78 +#define MC_CCR10_VALUE 0x2000100
79 +#define MC_CCR11_VALUE 0x2000401
80 +#define MC_CCR12_VALUE 0x30000
81 +#define MC_CCR13_VALUE 0x202
82 +#define MC_CCR14_VALUE 0x7080A0F
83 +#define MC_CCR15_VALUE 0x2040F
84 +#define MC_CCR16_VALUE 0x40000
85 +#define MC_CCR17_VALUE 0x70102
86 +#define MC_CCR18_VALUE 0x4020002
87 +#define MC_CCR19_VALUE 0x30302
88 +#define MC_CCR20_VALUE 0x8000700
89 +#define MC_CCR21_VALUE 0x40F020A
90 +#define MC_CCR22_VALUE 0x0
91 +#define MC_CCR23_VALUE 0xC020000
92 +#define MC_CCR24_VALUE 0x4401B04
93 +#define MC_CCR25_VALUE 0x0
94 +#define MC_CCR26_VALUE 0x0
95 +#define MC_CCR27_VALUE 0x6420000
96 +#define MC_CCR28_VALUE 0x0
97 +#define MC_CCR29_VALUE 0x0
98 +#define MC_CCR30_VALUE 0x798
99 +#define MC_CCR31_VALUE 0x0
100 +#define MC_CCR32_VALUE 0x0
101 +#define MC_CCR33_VALUE 0x650000
102 +#define MC_CCR34_VALUE 0x200C8
103 +#define MC_CCR35_VALUE 0x1D445D
104 +#define MC_CCR36_VALUE 0xC8
105 +#define MC_CCR37_VALUE 0xC351
106 +#define MC_CCR38_VALUE 0x0
107 +#define MC_CCR39_VALUE 0x141F04
108 +#define MC_CCR40_VALUE 0x142704
109 +#define MC_CCR41_VALUE 0x141B42
110 +#define MC_CCR42_VALUE 0x141B42
111 +#define MC_CCR43_VALUE 0x566504
112 +#define MC_CCR44_VALUE 0x566504
113 +#define MC_CCR45_VALUE 0x565F17
114 +#define MC_CCR46_VALUE 0x565F17
115 +#define MC_CCR47_VALUE 0x0
116 +#define MC_CCR48_VALUE 0x0
117 +#define MC_CCR49_VALUE 0x0
118 +#define MC_CCR50_VALUE 0x0
119 +#define MC_CCR51_VALUE 0x0
120 +#define MC_CCR52_VALUE 0x133
121 +#define MC_CCR53_VALUE 0xF3014B27
122 +#define MC_CCR54_VALUE 0xF3014B27
123 +#define MC_CCR55_VALUE 0xF3014B27
124 +#define MC_CCR56_VALUE 0xF3014B27
125 +#define MC_CCR57_VALUE 0x7800301
126 +#define MC_CCR58_VALUE 0x7800301
127 +#define MC_CCR59_VALUE 0x7800301
128 +#define MC_CCR60_VALUE 0x7800301
129 +#define MC_CCR61_VALUE 0x4
130 diff --git a/board/zte/zxhnh367n/zxhnh367n.c b/board/zte/zxhnh367n/zxhnh367n.c
131 new file mode 100644
132 index 0000000..f64f105
133 --- /dev/null
134 +++ b/board/zte/zxhnh367n/zxhnh367n.c
135 @@ -0,0 +1,97 @@
136 +/*
137 + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
138 + *
139 + * SPDX-License-Identifier: GPL-2.0+
140 + */
141 +
142 +#include <common.h>
143 +#include <asm/gpio.h>
144 +#include <asm/lantiq/eth.h>
145 +#include <asm/lantiq/chipid.h>
146 +#include <asm/lantiq/cpu.h>
147 +#include <asm/arch/gphy.h>
148 +
149 +#if defined(CONFIG_SPL_BUILD)
150 +#define do_gpio_init 1
151 +#define do_pll_init 1
152 +#define do_dcdc_init 0
153 +#elif defined(CONFIG_SYS_BOOT_RAM)
154 +#define do_gpio_init 1
155 +#define do_pll_init 0
156 +#define do_dcdc_init 1
157 +#else
158 +#define do_gpio_init 0
159 +#define do_pll_init 0
160 +#define do_dcdc_init 1
161 +#endif
162 +
163 +static void gpio_init(void)
164 +{
165 + /* EBU.FL_CS1 as output for NAND CE */
166 + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
167 + /* EBU.FL_A23 as output for NAND CLE */
168 + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
169 + /* EBU.FL_A24 as output for NAND ALE */
170 + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
171 + /* GPIO 3.0 as input for NAND Ready Busy */
172 + gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
173 + /* GPIO 3.1 as output for NAND Read */
174 + gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
175 +}
176 +
177 +int board_early_init_f(void)
178 +{
179 + if (do_gpio_init)
180 + gpio_init();
181 +
182 + if (do_pll_init)
183 + ltq_pll_init();
184 +
185 + if (do_dcdc_init)
186 + ltq_dcdc_init(0x7F);
187 +
188 + return 0;
189 +}
190 +
191 +int checkboard(void)
192 +{
193 + puts("Board: " CONFIG_BOARD_NAME "\n");
194 + ltq_chip_print_info();
195 +
196 + return 0;
197 +}
198 +
199 +static const struct ltq_eth_port_config eth_port_config[] = {
200 + /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
201 + { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
202 + /* GMAC1: unused */
203 + { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
204 + /* GMAC2: internal GPHY0 with 10/100 firmware for LAN port 1 */
205 + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
206 + /* GMAC3: internal GPHY0 with 10/100 firmware for LAN port 2 */
207 + { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
208 + /* GMAC4: internal GPHY1 with 10/100 firmware for LAN port 3 */
209 + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
210 + /* GMAC5: internal GPHY1 with 10/100 firmware for LAN port 4 */
211 + { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
212 +};
213 +
214 +static const struct ltq_eth_board_config eth_board_config = {
215 + .ports = eth_port_config,
216 + .num_ports = ARRAY_SIZE(eth_port_config),
217 +};
218 +
219 +int board_eth_init(bd_t * bis)
220 +{
221 + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
222 + const ulong fw_addr = 0x80FF0000;
223 +
224 + ltq_gphy_phy22f_a2x_load(fw_addr);
225 +
226 + ltq_cgu_gphy_clk_src(clk);
227 +
228 + ltq_rcu_gphy_boot(0, fw_addr);
229 + ltq_rcu_gphy_boot(1, fw_addr);
230 +
231 + return ltq_eth_initialize(&eth_board_config);
232 +}
233 diff --git a/boards.cfg b/boards.cfg
234 index 2163cdb..4b18a26 100644
235 --- a/boards.cfg
236 +++ b/boards.cfg
237 @@ -527,6 +527,9 @@ Active mips mips32 vrx200 lantiq easy80920
238 Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
239 Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
240 Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
241 +Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_nandspl zxhnh367n:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org>
242 +Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_ram zxhnh367n:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
243 +Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_zte zxhnh367n:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org>
244 Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
245 Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
246 Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
247 diff --git a/include/configs/zxhnh367n.h b/include/configs/zxhnh367n.h
248 new file mode 100644
249 index 0000000..55d2e2a
250 --- /dev/null
251 +++ b/include/configs/zxhnh367n.h
252 @@ -0,0 +1,72 @@
253 +/*
254 + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
255 + *
256 + * SPDX-License-Identifier: GPL-2.0+
257 + */
258 +
259 +#ifndef __CONFIG_H
260 +#define __CONFIG_H
261 +
262 +#define CONFIG_MACH_TYPE "ZXHN H367N"
263 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
264 +#define CONFIG_BOARD_NAME "ZTE ZXHN H367N"
265 +
266 +/* Configure SoC */
267 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
268 +
269 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
270 +
271 +#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a NAND flash */
272 +
273 +#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
274 +#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
275 +#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
276 +
277 +#define CONFIG_SYS_NAND_PAGE_COUNT 128
278 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
279 +#define CONFIG_SYS_NAND_OOBSIZE 64
280 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
281 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
282 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000
283 +
284 +#define CONFIG_SYS_DRAM_PROBE
285 +
286 +/* Environment */
287 +#if defined(CONFIG_SYS_BOOT_NANDSPL)
288 +#define CONFIG_ENV_IS_IN_NAND
289 +#define CONFIG_ENV_OVERWRITE
290 +#define CONFIG_ENV_OFFSET (256 * 1024)
291 +#define CONFIG_ENV_SECT_SIZE (256 * 1024)
292 +#else
293 +#define CONFIG_ENV_IS_NOWHERE
294 +#endif
295 +
296 +#define CONFIG_ENV_SIZE (8 * 1024)
297 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
298 +
299 +#if defined(CONFIG_SYS_BOOT_ZTE)
300 +#define CONFIG_SYS_TEXT_BASE 0x80800000
301 +#define CONFIG_SKIP_LOWLEVEL_INIT
302 +#endif
303 +
304 +/* Console */
305 +#define CONFIG_LTQ_ADVANCED_CONSOLE
306 +#define CONFIG_BAUDRATE 115200
307 +#define CONFIG_CONSOLE_ASC 1
308 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
309 +
310 +/* Pull in default board configs for Lantiq XWAY VRX200 */
311 +#include <asm/lantiq/config.h>
312 +#include <asm/arch/config.h>
313 +
314 +/* Pull in default OpenWrt configs for Lantiq SoC */
315 +#include "openwrt-lantiq-common.h"
316 +
317 +#define CONFIG_ENV_UPDATE_UBOOT_NAND \
318 + "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
319 +
320 +#define CONFIG_EXTRA_ENV_SETTINGS \
321 + CONFIG_ENV_LANTIQ_DEFAULTS \
322 + CONFIG_ENV_UPDATE_UBOOT_NAND
323 +
324 +#endif /* __CONFIG_H */
325 --
326 1.8.3.2
327