uboot-lantiq: update to v2013.10
[openwrt/svn-archive/archive.git] / package / boot / uboot-lantiq / patches / 0033-MIPS-add-board-support-for-ZyXEL-P-661HNU-Fx.patch
1 From a18f994f373db4467a4680f83ead997c8122908e Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Wed, 22 May 2013 17:48:08 +0200
4 Subject: MIPS: add board support for ZyXEL P-661HNU-Fx
5
6 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
7
8 diff --git a/board/zyxel/p661hnufx/Makefile b/board/zyxel/p661hnufx/Makefile
9 new file mode 100644
10 index 0000000..3a547c2
11 --- /dev/null
12 +++ b/board/zyxel/p661hnufx/Makefile
13 @@ -0,0 +1,27 @@
14 +#
15 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
16 +#
17 +# SPDX-License-Identifier: GPL-2.0+
18 +#
19 +
20 +include $(TOPDIR)/config.mk
21 +
22 +LIB = $(obj)lib$(BOARD).o
23 +
24 +COBJS = $(BOARD).o
25 +
26 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
27 +OBJS := $(addprefix $(obj),$(COBJS))
28 +SOBJS := $(addprefix $(obj),$(SOBJS))
29 +
30 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
31 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
32 +
33 +#########################################################################
34 +
35 +# defines $(obj).depend target
36 +include $(SRCTREE)/rules.mk
37 +
38 +sinclude $(obj).depend
39 +
40 +#########################################################################
41 diff --git a/board/zyxel/p661hnufx/config.mk b/board/zyxel/p661hnufx/config.mk
42 new file mode 100644
43 index 0000000..9d33739
44 --- /dev/null
45 +++ b/board/zyxel/p661hnufx/config.mk
46 @@ -0,0 +1,7 @@
47 +#
48 +# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
49 +#
50 +# SPDX-License-Identifier: GPL-2.0+
51 +#
52 +
53 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
54 diff --git a/board/zyxel/p661hnufx/ddr_settings.h b/board/zyxel/p661hnufx/ddr_settings.h
55 new file mode 100644
56 index 0000000..83693b8
57 --- /dev/null
58 +++ b/board/zyxel/p661hnufx/ddr_settings.h
59 @@ -0,0 +1,55 @@
60 +/*
61 + * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
62 + *
63 + * The values have been extracted from original ZyXEL U-Boot.
64 + *
65 + * SPDX-License-Identifier: GPL-2.0+
66 + */
67 +
68 +#define MC_DC00_VALUE 0x1B1B
69 +#define MC_DC01_VALUE 0x0
70 +#define MC_DC02_VALUE 0x0
71 +#define MC_DC03_VALUE 0x0
72 +#define MC_DC04_VALUE 0x0
73 +#define MC_DC05_VALUE 0x200
74 +#define MC_DC06_VALUE 0x307
75 +#define MC_DC07_VALUE 0x303
76 +#define MC_DC08_VALUE 0x103
77 +#define MC_DC09_VALUE 0x80B
78 +#define MC_DC10_VALUE 0x203
79 +#define MC_DC11_VALUE 0xE02
80 +#define MC_DC12_VALUE 0x2C8
81 +#define MC_DC13_VALUE 0x1
82 +#define MC_DC14_VALUE 0x0
83 +#define MC_DC15_VALUE 0x100
84 +#define MC_DC16_VALUE 0xC800
85 +#define MC_DC17_VALUE 0xF
86 +#define MC_DC18_VALUE 0x301
87 +#define MC_DC19_VALUE 0x200
88 +#define MC_DC20_VALUE 0xA04
89 +#define MC_DC21_VALUE 0x1600
90 +#define MC_DC22_VALUE 0x1616
91 +#define MC_DC23_VALUE 0x0
92 +#define MC_DC24_VALUE 0x5D
93 +#define MC_DC25_VALUE 0x0
94 +#define MC_DC26_VALUE 0x0
95 +#define MC_DC27_VALUE 0x0
96 +#define MC_DC28_VALUE 0x5FB
97 +#define MC_DC29_VALUE 0x35DF
98 +#define MC_DC30_VALUE 0x99E9
99 +#define MC_DC31_VALUE 0x0
100 +#define MC_DC32_VALUE 0x0
101 +#define MC_DC33_VALUE 0x0
102 +#define MC_DC34_VALUE 0x0
103 +#define MC_DC35_VALUE 0x0
104 +#define MC_DC36_VALUE 0x0
105 +#define MC_DC37_VALUE 0x0
106 +#define MC_DC38_VALUE 0x0
107 +#define MC_DC39_VALUE 0x0
108 +#define MC_DC40_VALUE 0x0
109 +#define MC_DC41_VALUE 0x0
110 +#define MC_DC42_VALUE 0x0
111 +#define MC_DC43_VALUE 0x0
112 +#define MC_DC44_VALUE 0x0
113 +#define MC_DC45_VALUE 0x600
114 +#define MC_DC46_VALUE 0x0
115 diff --git a/board/zyxel/p661hnufx/p661hnufx.c b/board/zyxel/p661hnufx/p661hnufx.c
116 new file mode 100644
117 index 0000000..dfaca51
118 --- /dev/null
119 +++ b/board/zyxel/p661hnufx/p661hnufx.c
120 @@ -0,0 +1,102 @@
121 +/*
122 + * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
123 + *
124 + * SPDX-License-Identifier: GPL-2.0+
125 + */
126 +
127 +#include <common.h>
128 +#include <switch.h>
129 +#include <spi.h>
130 +#include <asm/gpio.h>
131 +#include <asm/lantiq/eth.h>
132 +#include <asm/lantiq/reset.h>
133 +#include <asm/lantiq/chipid.h>
134 +
135 +static void gpio_init(void)
136 +{
137 + /* SPI CS 0.4 to serial flash */
138 + gpio_direction_output(10, 1);
139 +}
140 +
141 +int board_early_init_f(void)
142 +{
143 + gpio_init();
144 +
145 + return 0;
146 +}
147 +
148 +int checkboard(void)
149 +{
150 + puts("Board: " CONFIG_BOARD_NAME "\n");
151 + ltq_chip_print_info();
152 +
153 + return 0;
154 +}
155 +
156 +static const struct ltq_eth_port_config eth_port_config[] = {
157 + /* MAC0: Lantiq Tantos switch */
158 + { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
159 + /* MAC1: unused */
160 + { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
161 +};
162 +
163 +static const struct ltq_eth_board_config eth_board_config = {
164 + .ports = eth_port_config,
165 + .num_ports = ARRAY_SIZE(eth_port_config),
166 +};
167 +
168 +int board_eth_init(bd_t *bis)
169 +{
170 + return ltq_eth_initialize(&eth_board_config);
171 +}
172 +
173 +static struct switch_device psb697x_dev = {
174 + .name = "psb697x",
175 + .cpu_port = 5,
176 + .port_mask = 0xF,
177 +};
178 +
179 +int board_switch_init(void)
180 +{
181 + printf("%s\n", __func__);
182 +
183 +#if 0
184 + ltq_reset_once(LTQ_RESET_HARD, 200000);
185 + __udelay(50000);
186 +#endif
187 +
188 + return switch_device_register(&psb697x_dev);
189 +}
190 +
191 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
192 +{
193 + if (bus)
194 + return 0;
195 +
196 + if (cs == 4)
197 + return 1;
198 +
199 + return 0;
200 +}
201 +
202 +void spi_cs_activate(struct spi_slave *slave)
203 +{
204 + switch (slave->cs) {
205 + case 4:
206 + gpio_set_value(10, 0);
207 + break;
208 + default:
209 + break;
210 + }
211 +}
212 +
213 +void spi_cs_deactivate(struct spi_slave *slave)
214 +{
215 + switch (slave->cs) {
216 + case 4:
217 + gpio_set_value(10, 1);
218 + break;
219 + default:
220 + break;
221 + }
222 +}
223 diff --git a/boards.cfg b/boards.cfg
224 index 4362856..e505203 100644
225 --- a/boards.cfg
226 +++ b/boards.cfg
227 @@ -499,6 +499,9 @@ Active mips mips32 - micronas vct
228 Active mips mips32 arx100 zte zxv10h201l zxv10h201l_nor zxv10h201l:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
229 Active mips mips32 arx100 zte zxv10h201l zxv10h201l_ram zxv10h201l:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
230 Active mips mips32 arx100 zte zxv10h201l zxv10h201l_zte zxv10h201l:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org>
231 +Active mips mips32 arx100 zyxel p661hnufx p661hnufx_ram p661hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
232 +Active mips mips32 arx100 zyxel p661hnufx p661hnufx_sfspl p661hnufx:SYS_BOOT_SFSPL Luka Perkov <luka@openwrt.org>
233 +Active mips mips32 arx100 zyxel p661hnufx p661hnufx_zyxel p661hnufx:SYS_BOOT_ZYXEL Luka Perkov <luka@openwrt.org>
234 Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se>
235 Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se>
236 Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se>
237 diff --git a/include/configs/p661hnufx.h b/include/configs/p661hnufx.h
238 new file mode 100644
239 index 0000000..85e3e1e
240 --- /dev/null
241 +++ b/include/configs/p661hnufx.h
242 @@ -0,0 +1,79 @@
243 +/*
244 + * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
245 + *
246 + * SPDX-License-Identifier: GPL-2.0+
247 + */
248 +
249 +#ifndef __CONFIG_H
250 +#define __CONFIG_H
251 +
252 +#define CONFIG_MACH_TYPE "P-661HNU-Fx"
253 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
254 +#define CONFIG_BOARD_NAME "ZyXEL P-661HNU-Fx"
255 +
256 +/* Configure SoC */
257 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
258 +
259 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
260 +
261 +#define CONFIG_LTQ_SUPPORT_SPI_FLASH
262 +#define CONFIG_SPI_FLASH_MACRONIX /* Supports Macronix serial flash */
263 +#define CONFIG_SPI_FLASH_4BYTE_MODE
264 +
265 +#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
266 +#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
267 +#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
268 +
269 +#define CONFIG_SPL_SPI_BUS 0
270 +#define CONFIG_SPL_SPI_CS 4
271 +#define CONFIG_SPL_SPI_MAX_HZ 25000000
272 +#define CONFIG_SPL_SPI_MODE 0
273 +
274 +/* Switch devices */
275 +#define CONFIG_SWITCH_MULTI
276 +#define CONFIG_SWITCH_PSB697X
277 +
278 +/* Environment */
279 +#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
280 +#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
281 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
282 +#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
283 +
284 +#if defined(CONFIG_SYS_BOOT_SFSPL)
285 +#define CONFIG_ENV_IS_IN_SPI_FLASH
286 +#define CONFIG_ENV_OVERWRITE
287 +#define CONFIG_ENV_OFFSET (512 * 1024)
288 +#define CONFIG_ENV_SECT_SIZE (256 * 1024)
289 +#else
290 +#define CONFIG_ENV_IS_NOWHERE
291 +#endif
292 +
293 +#define CONFIG_ENV_SIZE (8 * 1024)
294 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
295 +
296 +#if defined(CONFIG_SYS_BOOT_ZYXEL)
297 +#define CONFIG_SYS_TEXT_BASE 0x80800000
298 +#define CONFIG_SKIP_LOWLEVEL_INIT
299 +#endif
300 +
301 +/* Console */
302 +#define CONFIG_LTQ_ADVANCED_CONSOLE
303 +#define CONFIG_BAUDRATE 115200
304 +#define CONFIG_CONSOLE_ASC 1
305 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
306 +
307 +/* Pull in default board configs for Lantiq XWAY Danube */
308 +#include <asm/lantiq/config.h>
309 +#include <asm/arch/config.h>
310 +
311 +/* Pull in default OpenWrt configs for Lantiq SoC */
312 +#include "openwrt-lantiq-common.h"
313 +
314 +#define CONFIG_ENV_UPDATE_UBOOT_SF \
315 + "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
316 +
317 +#define CONFIG_EXTRA_ENV_SETTINGS \
318 + CONFIG_ENV_LANTIQ_DEFAULTS \
319 + CONFIG_ENV_UPDATE_UBOOT_SF
320 +
321 +#endif /* __CONFIG_H */
322 --
323 1.8.3.2
324