adds lantiq packages/drivers
[openwrt/svn-archive/archive.git] / package / ltq-dsl / src / ifxmips_atm_fw_regs_common.h
1 #ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
2 #define IFXMIPS_ATM_FW_REGS_COMMON_H
3
4
5
6 #if defined(CONFIG_DANUBE)
7 #include "ifxmips_atm_fw_regs_danube.h"
8 #elif defined(CONFIG_AMAZON_SE)
9 #include "ifxmips_atm_fw_regs_amazon_se.h"
10 #elif defined(CONFIG_AR9)
11 #include "ifxmips_atm_fw_regs_ar9.h"
12 #elif defined(CONFIG_VR9)
13 #include "ifxmips_atm_fw_regs_vr9.h"
14 #else
15 #error Platform is not specified!
16 #endif
17
18
19
20 /*
21 * PPE ATM Cell Header
22 */
23 #if defined(__BIG_ENDIAN)
24 struct uni_cell_header {
25 unsigned int gfc :4;
26 unsigned int vpi :8;
27 unsigned int vci :16;
28 unsigned int pti :3;
29 unsigned int clp :1;
30 };
31 #else
32 struct uni_cell_header {
33 unsigned int clp :1;
34 unsigned int pti :3;
35 unsigned int vci :16;
36 unsigned int vpi :8;
37 unsigned int gfc :4;
38 };
39 #endif // defined(__BIG_ENDIAN)
40
41 /*
42 * Inband Header and Trailer
43 */
44 #if defined(__BIG_ENDIAN)
45 struct rx_inband_trailer {
46 /* 0 - 3h */
47 unsigned int uu :8;
48 unsigned int cpi :8;
49 unsigned int stw_res1:4;
50 unsigned int stw_clp :1;
51 unsigned int stw_ec :1;
52 unsigned int stw_uu :1;
53 unsigned int stw_cpi :1;
54 unsigned int stw_ovz :1;
55 unsigned int stw_mfl :1;
56 unsigned int stw_usz :1;
57 unsigned int stw_crc :1;
58 unsigned int stw_il :1;
59 unsigned int stw_ra :1;
60 unsigned int stw_res2:2;
61 /* 4 - 7h */
62 unsigned int gfc :4;
63 unsigned int vpi :8;
64 unsigned int vci :16;
65 unsigned int pti :3;
66 unsigned int clp :1;
67 };
68
69 struct tx_inband_header {
70 /* 0 - 3h */
71 unsigned int gfc :4;
72 unsigned int vpi :8;
73 unsigned int vci :16;
74 unsigned int pti :3;
75 unsigned int clp :1;
76 /* 4 - 7h */
77 unsigned int uu :8;
78 unsigned int cpi :8;
79 unsigned int pad :8;
80 unsigned int res1 :8;
81 };
82 #else
83 struct rx_inband_trailer {
84 /* 0 - 3h */
85 unsigned int stw_res2:2;
86 unsigned int stw_ra :1;
87 unsigned int stw_il :1;
88 unsigned int stw_crc :1;
89 unsigned int stw_usz :1;
90 unsigned int stw_mfl :1;
91 unsigned int stw_ovz :1;
92 unsigned int stw_cpi :1;
93 unsigned int stw_uu :1;
94 unsigned int stw_ec :1;
95 unsigned int stw_clp :1;
96 unsigned int stw_res1:4;
97 unsigned int cpi :8;
98 unsigned int uu :8;
99 /* 4 - 7h */
100 unsigned int clp :1;
101 unsigned int pti :3;
102 unsigned int vci :16;
103 unsigned int vpi :8;
104 unsigned int gfc :4;
105 };
106
107 struct tx_inband_header {
108 /* 0 - 3h */
109 unsigned int clp :1;
110 unsigned int pti :3;
111 unsigned int vci :16;
112 unsigned int vpi :8;
113 unsigned int gfc :4;
114 /* 4 - 7h */
115 unsigned int res1 :8;
116 unsigned int pad :8;
117 unsigned int cpi :8;
118 unsigned int uu :8;
119 };
120 #endif // defined(__BIG_ENDIAN)
121
122 /*
123 * MIB Table Maintained by Firmware
124 */
125 struct wan_mib_table {
126 u32 res1;
127 u32 wrx_drophtu_cell;
128 u32 wrx_dropdes_pdu;
129 u32 wrx_correct_pdu;
130 u32 wrx_err_pdu;
131 u32 wrx_dropdes_cell;
132 u32 wrx_correct_cell;
133 u32 wrx_err_cell;
134 u32 wrx_total_byte;
135 u32 res2;
136 u32 wtx_total_pdu;
137 u32 wtx_total_cell;
138 u32 wtx_total_byte;
139 };
140
141 /*
142 * Host-PPE Communication Data Structure
143 */
144
145 #if defined(__BIG_ENDIAN)
146 struct wrx_queue_config {
147 /* 0h */
148 unsigned int res2 :27;
149 unsigned int dmach :4;
150 unsigned int errdp :1;
151 /* 1h */
152 unsigned int oversize :16;
153 unsigned int undersize :16;
154 /* 2h */
155 unsigned int res1 :16;
156 unsigned int mfs :16;
157 /* 3h */
158 unsigned int uumask :8;
159 unsigned int cpimask :8;
160 unsigned int uuexp :8;
161 unsigned int cpiexp :8;
162 };
163
164 struct wtx_port_config {
165 unsigned int res1 :27;
166 unsigned int qid :4;
167 unsigned int qsben :1;
168 };
169
170 struct wtx_queue_config {
171 unsigned int res1 :25;
172 unsigned int sbid :1;
173 unsigned int res2 :3;
174 unsigned int type :2;
175 unsigned int qsben :1;
176 };
177
178 struct wrx_dma_channel_config {
179 /* 0h */
180 unsigned int res1 :1;
181 unsigned int mode :2;
182 unsigned int rlcfg :1;
183 unsigned int desba :28;
184 /* 1h */
185 unsigned int chrl :16;
186 unsigned int clp1th :16;
187 /* 2h */
188 unsigned int deslen :16;
189 unsigned int vlddes :16;
190 };
191
192 struct wtx_dma_channel_config {
193 /* 0h */
194 unsigned int res2 :1;
195 unsigned int mode :2;
196 unsigned int res3 :1;
197 unsigned int desba :28;
198 /* 1h */
199 unsigned int res1 :32;
200 /* 2h */
201 unsigned int deslen :16;
202 unsigned int vlddes :16;
203 };
204
205 struct htu_entry {
206 unsigned int res1 :1;
207 unsigned int clp :1;
208 unsigned int pid :2;
209 unsigned int vpi :8;
210 unsigned int vci :16;
211 unsigned int pti :3;
212 unsigned int vld :1;
213 };
214
215 struct htu_mask {
216 unsigned int set :1;
217 unsigned int clp :1;
218 unsigned int pid_mask :2;
219 unsigned int vpi_mask :8;
220 unsigned int vci_mask :16;
221 unsigned int pti_mask :3;
222 unsigned int clear :1;
223 };
224
225 struct htu_result {
226 unsigned int res1 :12;
227 unsigned int cellid :4;
228 unsigned int res2 :5;
229 unsigned int type :1;
230 unsigned int ven :1;
231 unsigned int res3 :5;
232 unsigned int qid :4;
233 };
234
235 struct rx_descriptor {
236 /* 0 - 3h */
237 unsigned int own :1;
238 unsigned int c :1;
239 unsigned int sop :1;
240 unsigned int eop :1;
241 unsigned int res1 :3;
242 unsigned int byteoff :2;
243 unsigned int res2 :2;
244 unsigned int id :4;
245 unsigned int err :1;
246 unsigned int datalen :16;
247 /* 4 - 7h */
248 unsigned int res3 :4;
249 unsigned int dataptr :28;
250 };
251
252 struct tx_descriptor {
253 /* 0 - 3h */
254 unsigned int own :1;
255 unsigned int c :1;
256 unsigned int sop :1;
257 unsigned int eop :1;
258 unsigned int byteoff :5;
259 unsigned int res1 :5;
260 unsigned int iscell :1;
261 unsigned int clp :1;
262 unsigned int datalen :16;
263 /* 4 - 7h */
264 unsigned int res2 :4;
265 unsigned int dataptr :28;
266 };
267 #else
268 struct wrx_queue_config {
269 /* 0h */
270 unsigned int errdp :1;
271 unsigned int dmach :4;
272 unsigned int res2 :27;
273 /* 1h */
274 unsigned int undersize :16;
275 unsigned int oversize :16;
276 /* 2h */
277 unsigned int mfs :16;
278 unsigned int res1 :16;
279 /* 3h */
280 unsigned int cpiexp :8;
281 unsigned int uuexp :8;
282 unsigned int cpimask :8;
283 unsigned int uumask :8;
284 };
285
286 struct wtx_port_config {
287 unsigned int qsben :1;
288 unsigned int qid :4;
289 unsigned int res1 :27;
290 };
291
292 struct wtx_queue_config {
293 unsigned int qsben :1;
294 unsigned int type :2;
295 unsigned int res2 :3;
296 unsigned int sbid :1;
297 unsigned int res1 :25;
298 };
299
300 struct wrx_dma_channel_config
301 {
302 /* 0h */
303 unsigned int desba :28;
304 unsigned int rlcfg :1;
305 unsigned int mode :2;
306 unsigned int res1 :1;
307 /* 1h */
308 unsigned int clp1th :16;
309 unsigned int chrl :16;
310 /* 2h */
311 unsigned int vlddes :16;
312 unsigned int deslen :16;
313 };
314
315 struct wtx_dma_channel_config {
316 /* 0h */
317 unsigned int desba :28;
318 unsigned int res3 :1;
319 unsigned int mode :2;
320 unsigned int res2 :1;
321 /* 1h */
322 unsigned int res1 :32;
323 /* 2h */
324 unsigned int vlddes :16;
325 unsigned int deslen :16;
326 };
327
328 struct rx_descriptor {
329 /* 4 - 7h */
330 unsigned int dataptr :28;
331 unsigned int res3 :4;
332 /* 0 - 3h */
333 unsigned int datalen :16;
334 unsigned int err :1;
335 unsigned int id :4;
336 unsigned int res2 :2;
337 unsigned int byteoff :2;
338 unsigned int res1 :3;
339 unsigned int eop :1;
340 unsigned int sop :1;
341 unsigned int c :1;
342 unsigned int own :1;
343 };
344
345 struct tx_descriptor {
346 /* 4 - 7h */
347 unsigned int dataptr :28;
348 unsigned int res2 :4;
349 /* 0 - 3h */
350 unsigned int datalen :16;
351 unsigned int clp :1;
352 unsigned int iscell :1;
353 unsigned int res1 :5;
354 unsigned int byteoff :5;
355 unsigned int eop :1;
356 unsigned int sop :1;
357 unsigned int c :1;
358 unsigned int own :1;
359 };
360 #endif // defined(__BIG_ENDIAN)
361
362
363
364 #endif // IFXMIPS_ATM_FW_REGS_COMMON_H