5a4a9033c923b9d9d05fbc6d3759036860a81d48
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 300-ar9300_support.patch
1 --- a/drivers/net/wireless/ath/ath9k/Makefile
2 +++ b/drivers/net/wireless/ath/ath9k/Makefile
3 @@ -13,16 +13,26 @@ ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
4
5 obj-$(CONFIG_ATH9K) += ath9k.o
6
7 -ath9k_hw-y:= hw.o \
8 +ath9k_hw-y:= \
9 + ar9002_hw.o \
10 + ar9003_hw.o \
11 + hw.o \
12 + ar9003_phy.o \
13 + ar9002_phy.o \
14 + ar5008_phy.o \
15 + ar9002_calib.o \
16 + ar9003_calib.o \
17 + calib.o \
18 eeprom.o \
19 eeprom_def.o \
20 eeprom_4k.o \
21 eeprom_9287.o \
22 - calib.o \
23 ani.o \
24 - phy.o \
25 btcoex.o \
26 mac.o \
27 + ar9002_mac.o \
28 + ar9003_mac.o \
29 + ar9003_eeprom.o
30
31 obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
32
33 --- a/drivers/net/wireless/ath/ath9k/ani.c
34 +++ b/drivers/net/wireless/ath/ath9k/ani.c
35 @@ -15,6 +15,7 @@
36 */
37
38 #include "hw.h"
39 +#include "hw-ops.h"
40
41 static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
42 struct ath9k_channel *chan)
43 @@ -37,190 +38,6 @@ static int ath9k_hw_get_ani_channel_idx(
44 return 0;
45 }
46
47 -static bool ath9k_hw_ani_control(struct ath_hw *ah,
48 - enum ath9k_ani_cmd cmd, int param)
49 -{
50 - struct ar5416AniState *aniState = ah->curani;
51 - struct ath_common *common = ath9k_hw_common(ah);
52 -
53 - switch (cmd & ah->ani_function) {
54 - case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
55 - u32 level = param;
56 -
57 - if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
58 - ath_print(common, ATH_DBG_ANI,
59 - "level out of range (%u > %u)\n",
60 - level,
61 - (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
62 - return false;
63 - }
64 -
65 - REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
66 - AR_PHY_DESIRED_SZ_TOT_DES,
67 - ah->totalSizeDesired[level]);
68 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
69 - AR_PHY_AGC_CTL1_COARSE_LOW,
70 - ah->coarse_low[level]);
71 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
72 - AR_PHY_AGC_CTL1_COARSE_HIGH,
73 - ah->coarse_high[level]);
74 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
75 - AR_PHY_FIND_SIG_FIRPWR,
76 - ah->firpwr[level]);
77 -
78 - if (level > aniState->noiseImmunityLevel)
79 - ah->stats.ast_ani_niup++;
80 - else if (level < aniState->noiseImmunityLevel)
81 - ah->stats.ast_ani_nidown++;
82 - aniState->noiseImmunityLevel = level;
83 - break;
84 - }
85 - case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
86 - const int m1ThreshLow[] = { 127, 50 };
87 - const int m2ThreshLow[] = { 127, 40 };
88 - const int m1Thresh[] = { 127, 0x4d };
89 - const int m2Thresh[] = { 127, 0x40 };
90 - const int m2CountThr[] = { 31, 16 };
91 - const int m2CountThrLow[] = { 63, 48 };
92 - u32 on = param ? 1 : 0;
93 -
94 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
95 - AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
96 - m1ThreshLow[on]);
97 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
98 - AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
99 - m2ThreshLow[on]);
100 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
101 - AR_PHY_SFCORR_M1_THRESH,
102 - m1Thresh[on]);
103 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
104 - AR_PHY_SFCORR_M2_THRESH,
105 - m2Thresh[on]);
106 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
107 - AR_PHY_SFCORR_M2COUNT_THR,
108 - m2CountThr[on]);
109 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
110 - AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
111 - m2CountThrLow[on]);
112 -
113 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
114 - AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
115 - m1ThreshLow[on]);
116 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
117 - AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
118 - m2ThreshLow[on]);
119 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
120 - AR_PHY_SFCORR_EXT_M1_THRESH,
121 - m1Thresh[on]);
122 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
123 - AR_PHY_SFCORR_EXT_M2_THRESH,
124 - m2Thresh[on]);
125 -
126 - if (on)
127 - REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
128 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
129 - else
130 - REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
131 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
132 -
133 - if (!on != aniState->ofdmWeakSigDetectOff) {
134 - if (on)
135 - ah->stats.ast_ani_ofdmon++;
136 - else
137 - ah->stats.ast_ani_ofdmoff++;
138 - aniState->ofdmWeakSigDetectOff = !on;
139 - }
140 - break;
141 - }
142 - case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
143 - const int weakSigThrCck[] = { 8, 6 };
144 - u32 high = param ? 1 : 0;
145 -
146 - REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
147 - AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
148 - weakSigThrCck[high]);
149 - if (high != aniState->cckWeakSigThreshold) {
150 - if (high)
151 - ah->stats.ast_ani_cckhigh++;
152 - else
153 - ah->stats.ast_ani_ccklow++;
154 - aniState->cckWeakSigThreshold = high;
155 - }
156 - break;
157 - }
158 - case ATH9K_ANI_FIRSTEP_LEVEL:{
159 - const int firstep[] = { 0, 4, 8 };
160 - u32 level = param;
161 -
162 - if (level >= ARRAY_SIZE(firstep)) {
163 - ath_print(common, ATH_DBG_ANI,
164 - "level out of range (%u > %u)\n",
165 - level,
166 - (unsigned) ARRAY_SIZE(firstep));
167 - return false;
168 - }
169 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
170 - AR_PHY_FIND_SIG_FIRSTEP,
171 - firstep[level]);
172 - if (level > aniState->firstepLevel)
173 - ah->stats.ast_ani_stepup++;
174 - else if (level < aniState->firstepLevel)
175 - ah->stats.ast_ani_stepdown++;
176 - aniState->firstepLevel = level;
177 - break;
178 - }
179 - case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
180 - const int cycpwrThr1[] =
181 - { 2, 4, 6, 8, 10, 12, 14, 16 };
182 - u32 level = param;
183 -
184 - if (level >= ARRAY_SIZE(cycpwrThr1)) {
185 - ath_print(common, ATH_DBG_ANI,
186 - "level out of range (%u > %u)\n",
187 - level,
188 - (unsigned) ARRAY_SIZE(cycpwrThr1));
189 - return false;
190 - }
191 - REG_RMW_FIELD(ah, AR_PHY_TIMING5,
192 - AR_PHY_TIMING5_CYCPWR_THR1,
193 - cycpwrThr1[level]);
194 - if (level > aniState->spurImmunityLevel)
195 - ah->stats.ast_ani_spurup++;
196 - else if (level < aniState->spurImmunityLevel)
197 - ah->stats.ast_ani_spurdown++;
198 - aniState->spurImmunityLevel = level;
199 - break;
200 - }
201 - case ATH9K_ANI_PRESENT:
202 - break;
203 - default:
204 - ath_print(common, ATH_DBG_ANI,
205 - "invalid cmd %u\n", cmd);
206 - return false;
207 - }
208 -
209 - ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
210 - ath_print(common, ATH_DBG_ANI,
211 - "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
212 - "ofdmWeakSigDetectOff=%d\n",
213 - aniState->noiseImmunityLevel,
214 - aniState->spurImmunityLevel,
215 - !aniState->ofdmWeakSigDetectOff);
216 - ath_print(common, ATH_DBG_ANI,
217 - "cckWeakSigThreshold=%d, "
218 - "firstepLevel=%d, listenTime=%d\n",
219 - aniState->cckWeakSigThreshold,
220 - aniState->firstepLevel,
221 - aniState->listenTime);
222 - ath_print(common, ATH_DBG_ANI,
223 - "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
224 - aniState->cycleCount,
225 - aniState->ofdmPhyErrCount,
226 - aniState->cckPhyErrCount);
227 -
228 - return true;
229 -}
230 -
231 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
232 struct ath9k_mib_stats *stats)
233 {
234 --- /dev/null
235 +++ b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
236 @@ -0,0 +1,742 @@
237 +/*
238 + * Copyright (c) 2008-2009 Atheros Communications Inc.
239 + *
240 + * Permission to use, copy, modify, and/or distribute this software for any
241 + * purpose with or without fee is hereby granted, provided that the above
242 + * copyright notice and this permission notice appear in all copies.
243 + *
244 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
245 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
246 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
247 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
248 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
249 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
250 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
251 + */
252 +
253 +#ifndef INITVALS_AR5008_H
254 +#define INITVALS_AR5008_H
255 +
256 +static const u32 ar5416Modes[][6] = {
257 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
258 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
259 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
260 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
261 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
262 + { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
263 + { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
264 + { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
265 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
266 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
267 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
268 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
269 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
270 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
271 + { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
272 + { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
273 + { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
274 + { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
275 + { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
276 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
277 + { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
278 + { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
279 + { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
280 + { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
281 + { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
282 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
283 + { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 },
284 + { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b },
285 + { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
286 + { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
287 + { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
288 + { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
289 + { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
290 + { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
291 + { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
292 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
293 + { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
294 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
295 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
296 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
297 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
298 + { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
299 + { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
300 + { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
301 + { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
302 + { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
303 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
304 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
305 + { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
306 + { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
307 + { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
308 + { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
309 + { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
310 + { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
311 + { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
312 + { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
313 + { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
314 + { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
315 + { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
316 + { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
317 + { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
318 + { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
319 + { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
320 +};
321 +
322 +static const u32 ar5416Common[][2] = {
323 + { 0x0000000c, 0x00000000 },
324 + { 0x00000030, 0x00020015 },
325 + { 0x00000034, 0x00000005 },
326 + { 0x00000040, 0x00000000 },
327 + { 0x00000044, 0x00000008 },
328 + { 0x00000048, 0x00000008 },
329 + { 0x0000004c, 0x00000010 },
330 + { 0x00000050, 0x00000000 },
331 + { 0x00000054, 0x0000001f },
332 + { 0x00000800, 0x00000000 },
333 + { 0x00000804, 0x00000000 },
334 + { 0x00000808, 0x00000000 },
335 + { 0x0000080c, 0x00000000 },
336 + { 0x00000810, 0x00000000 },
337 + { 0x00000814, 0x00000000 },
338 + { 0x00000818, 0x00000000 },
339 + { 0x0000081c, 0x00000000 },
340 + { 0x00000820, 0x00000000 },
341 + { 0x00000824, 0x00000000 },
342 + { 0x00001040, 0x002ffc0f },
343 + { 0x00001044, 0x002ffc0f },
344 + { 0x00001048, 0x002ffc0f },
345 + { 0x0000104c, 0x002ffc0f },
346 + { 0x00001050, 0x002ffc0f },
347 + { 0x00001054, 0x002ffc0f },
348 + { 0x00001058, 0x002ffc0f },
349 + { 0x0000105c, 0x002ffc0f },
350 + { 0x00001060, 0x002ffc0f },
351 + { 0x00001064, 0x002ffc0f },
352 + { 0x00001230, 0x00000000 },
353 + { 0x00001270, 0x00000000 },
354 + { 0x00001038, 0x00000000 },
355 + { 0x00001078, 0x00000000 },
356 + { 0x000010b8, 0x00000000 },
357 + { 0x000010f8, 0x00000000 },
358 + { 0x00001138, 0x00000000 },
359 + { 0x00001178, 0x00000000 },
360 + { 0x000011b8, 0x00000000 },
361 + { 0x000011f8, 0x00000000 },
362 + { 0x00001238, 0x00000000 },
363 + { 0x00001278, 0x00000000 },
364 + { 0x000012b8, 0x00000000 },
365 + { 0x000012f8, 0x00000000 },
366 + { 0x00001338, 0x00000000 },
367 + { 0x00001378, 0x00000000 },
368 + { 0x000013b8, 0x00000000 },
369 + { 0x000013f8, 0x00000000 },
370 + { 0x00001438, 0x00000000 },
371 + { 0x00001478, 0x00000000 },
372 + { 0x000014b8, 0x00000000 },
373 + { 0x000014f8, 0x00000000 },
374 + { 0x00001538, 0x00000000 },
375 + { 0x00001578, 0x00000000 },
376 + { 0x000015b8, 0x00000000 },
377 + { 0x000015f8, 0x00000000 },
378 + { 0x00001638, 0x00000000 },
379 + { 0x00001678, 0x00000000 },
380 + { 0x000016b8, 0x00000000 },
381 + { 0x000016f8, 0x00000000 },
382 + { 0x00001738, 0x00000000 },
383 + { 0x00001778, 0x00000000 },
384 + { 0x000017b8, 0x00000000 },
385 + { 0x000017f8, 0x00000000 },
386 + { 0x0000103c, 0x00000000 },
387 + { 0x0000107c, 0x00000000 },
388 + { 0x000010bc, 0x00000000 },
389 + { 0x000010fc, 0x00000000 },
390 + { 0x0000113c, 0x00000000 },
391 + { 0x0000117c, 0x00000000 },
392 + { 0x000011bc, 0x00000000 },
393 + { 0x000011fc, 0x00000000 },
394 + { 0x0000123c, 0x00000000 },
395 + { 0x0000127c, 0x00000000 },
396 + { 0x000012bc, 0x00000000 },
397 + { 0x000012fc, 0x00000000 },
398 + { 0x0000133c, 0x00000000 },
399 + { 0x0000137c, 0x00000000 },
400 + { 0x000013bc, 0x00000000 },
401 + { 0x000013fc, 0x00000000 },
402 + { 0x0000143c, 0x00000000 },
403 + { 0x0000147c, 0x00000000 },
404 + { 0x00004030, 0x00000002 },
405 + { 0x0000403c, 0x00000002 },
406 + { 0x00007010, 0x00000000 },
407 + { 0x00007038, 0x000004c2 },
408 + { 0x00008004, 0x00000000 },
409 + { 0x00008008, 0x00000000 },
410 + { 0x0000800c, 0x00000000 },
411 + { 0x00008018, 0x00000700 },
412 + { 0x00008020, 0x00000000 },
413 + { 0x00008038, 0x00000000 },
414 + { 0x0000803c, 0x00000000 },
415 + { 0x00008048, 0x40000000 },
416 + { 0x00008054, 0x00000000 },
417 + { 0x00008058, 0x00000000 },
418 + { 0x0000805c, 0x000fc78f },
419 + { 0x00008060, 0x0000000f },
420 + { 0x00008064, 0x00000000 },
421 + { 0x000080c0, 0x2a82301a },
422 + { 0x000080c4, 0x05dc01e0 },
423 + { 0x000080c8, 0x1f402710 },
424 + { 0x000080cc, 0x01f40000 },
425 + { 0x000080d0, 0x00001e00 },
426 + { 0x000080d4, 0x00000000 },
427 + { 0x000080d8, 0x00400000 },
428 + { 0x000080e0, 0xffffffff },
429 + { 0x000080e4, 0x0000ffff },
430 + { 0x000080e8, 0x003f3f3f },
431 + { 0x000080ec, 0x00000000 },
432 + { 0x000080f0, 0x00000000 },
433 + { 0x000080f4, 0x00000000 },
434 + { 0x000080f8, 0x00000000 },
435 + { 0x000080fc, 0x00020000 },
436 + { 0x00008100, 0x00020000 },
437 + { 0x00008104, 0x00000001 },
438 + { 0x00008108, 0x00000052 },
439 + { 0x0000810c, 0x00000000 },
440 + { 0x00008110, 0x00000168 },
441 + { 0x00008118, 0x000100aa },
442 + { 0x0000811c, 0x00003210 },
443 + { 0x00008124, 0x00000000 },
444 + { 0x00008128, 0x00000000 },
445 + { 0x0000812c, 0x00000000 },
446 + { 0x00008130, 0x00000000 },
447 + { 0x00008134, 0x00000000 },
448 + { 0x00008138, 0x00000000 },
449 + { 0x0000813c, 0x00000000 },
450 + { 0x00008144, 0xffffffff },
451 + { 0x00008168, 0x00000000 },
452 + { 0x0000816c, 0x00000000 },
453 + { 0x00008170, 0x32143320 },
454 + { 0x00008174, 0xfaa4fa50 },
455 + { 0x00008178, 0x00000100 },
456 + { 0x0000817c, 0x00000000 },
457 + { 0x000081c4, 0x00000000 },
458 + { 0x000081ec, 0x00000000 },
459 + { 0x000081f0, 0x00000000 },
460 + { 0x000081f4, 0x00000000 },
461 + { 0x000081f8, 0x00000000 },
462 + { 0x000081fc, 0x00000000 },
463 + { 0x00008200, 0x00000000 },
464 + { 0x00008204, 0x00000000 },
465 + { 0x00008208, 0x00000000 },
466 + { 0x0000820c, 0x00000000 },
467 + { 0x00008210, 0x00000000 },
468 + { 0x00008214, 0x00000000 },
469 + { 0x00008218, 0x00000000 },
470 + { 0x0000821c, 0x00000000 },
471 + { 0x00008220, 0x00000000 },
472 + { 0x00008224, 0x00000000 },
473 + { 0x00008228, 0x00000000 },
474 + { 0x0000822c, 0x00000000 },
475 + { 0x00008230, 0x00000000 },
476 + { 0x00008234, 0x00000000 },
477 + { 0x00008238, 0x00000000 },
478 + { 0x0000823c, 0x00000000 },
479 + { 0x00008240, 0x00100000 },
480 + { 0x00008244, 0x0010f400 },
481 + { 0x00008248, 0x00000100 },
482 + { 0x0000824c, 0x0001e800 },
483 + { 0x00008250, 0x00000000 },
484 + { 0x00008254, 0x00000000 },
485 + { 0x00008258, 0x00000000 },
486 + { 0x0000825c, 0x400000ff },
487 + { 0x00008260, 0x00080922 },
488 + { 0x00008264, 0xa8000010 },
489 + { 0x00008270, 0x00000000 },
490 + { 0x00008274, 0x40000000 },
491 + { 0x00008278, 0x003e4180 },
492 + { 0x0000827c, 0x00000000 },
493 + { 0x00008284, 0x0000002c },
494 + { 0x00008288, 0x0000002c },
495 + { 0x0000828c, 0x00000000 },
496 + { 0x00008294, 0x00000000 },
497 + { 0x00008298, 0x00000000 },
498 + { 0x00008300, 0x00000000 },
499 + { 0x00008304, 0x00000000 },
500 + { 0x00008308, 0x00000000 },
501 + { 0x0000830c, 0x00000000 },
502 + { 0x00008310, 0x00000000 },
503 + { 0x00008314, 0x00000000 },
504 + { 0x00008318, 0x00000000 },
505 + { 0x00008328, 0x00000000 },
506 + { 0x0000832c, 0x00000007 },
507 + { 0x00008330, 0x00000302 },
508 + { 0x00008334, 0x00000e00 },
509 + { 0x00008338, 0x00070000 },
510 + { 0x0000833c, 0x00000000 },
511 + { 0x00008340, 0x000107ff },
512 + { 0x00009808, 0x00000000 },
513 + { 0x0000980c, 0xad848e19 },
514 + { 0x00009810, 0x7d14e000 },
515 + { 0x00009814, 0x9c0a9f6b },
516 + { 0x0000981c, 0x00000000 },
517 + { 0x0000982c, 0x0000a000 },
518 + { 0x00009830, 0x00000000 },
519 + { 0x0000983c, 0x00200400 },
520 + { 0x00009840, 0x206a002e },
521 + { 0x0000984c, 0x1284233c },
522 + { 0x00009854, 0x00000859 },
523 + { 0x00009900, 0x00000000 },
524 + { 0x00009904, 0x00000000 },
525 + { 0x00009908, 0x00000000 },
526 + { 0x0000990c, 0x00000000 },
527 + { 0x0000991c, 0x10000fff },
528 + { 0x00009920, 0x05100000 },
529 + { 0x0000a920, 0x05100000 },
530 + { 0x0000b920, 0x05100000 },
531 + { 0x00009928, 0x00000001 },
532 + { 0x0000992c, 0x00000004 },
533 + { 0x00009934, 0x1e1f2022 },
534 + { 0x00009938, 0x0a0b0c0d },
535 + { 0x0000993c, 0x00000000 },
536 + { 0x00009948, 0x9280b212 },
537 + { 0x0000994c, 0x00020028 },
538 + { 0x00009954, 0x5d50e188 },
539 + { 0x00009958, 0x00081fff },
540 + { 0x0000c95c, 0x004b6a8e },
541 + { 0x0000c968, 0x000003ce },
542 + { 0x00009970, 0x190fb515 },
543 + { 0x00009974, 0x00000000 },
544 + { 0x00009978, 0x00000001 },
545 + { 0x0000997c, 0x00000000 },
546 + { 0x00009980, 0x00000000 },
547 + { 0x00009984, 0x00000000 },
548 + { 0x00009988, 0x00000000 },
549 + { 0x0000998c, 0x00000000 },
550 + { 0x00009990, 0x00000000 },
551 + { 0x00009994, 0x00000000 },
552 + { 0x00009998, 0x00000000 },
553 + { 0x0000999c, 0x00000000 },
554 + { 0x000099a0, 0x00000000 },
555 + { 0x000099a4, 0x00000001 },
556 + { 0x000099a8, 0x001fff00 },
557 + { 0x000099ac, 0x00000000 },
558 + { 0x000099b0, 0x03051000 },
559 + { 0x000099dc, 0x00000000 },
560 + { 0x000099e0, 0x00000200 },
561 + { 0x000099e4, 0xaaaaaaaa },
562 + { 0x000099e8, 0x3c466478 },
563 + { 0x000099ec, 0x000000aa },
564 + { 0x000099fc, 0x00001042 },
565 + { 0x00009b00, 0x00000000 },
566 + { 0x00009b04, 0x00000001 },
567 + { 0x00009b08, 0x00000002 },
568 + { 0x00009b0c, 0x00000003 },
569 + { 0x00009b10, 0x00000004 },
570 + { 0x00009b14, 0x00000005 },
571 + { 0x00009b18, 0x00000008 },
572 + { 0x00009b1c, 0x00000009 },
573 + { 0x00009b20, 0x0000000a },
574 + { 0x00009b24, 0x0000000b },
575 + { 0x00009b28, 0x0000000c },
576 + { 0x00009b2c, 0x0000000d },
577 + { 0x00009b30, 0x00000010 },
578 + { 0x00009b34, 0x00000011 },
579 + { 0x00009b38, 0x00000012 },
580 + { 0x00009b3c, 0x00000013 },
581 + { 0x00009b40, 0x00000014 },
582 + { 0x00009b44, 0x00000015 },
583 + { 0x00009b48, 0x00000018 },
584 + { 0x00009b4c, 0x00000019 },
585 + { 0x00009b50, 0x0000001a },
586 + { 0x00009b54, 0x0000001b },
587 + { 0x00009b58, 0x0000001c },
588 + { 0x00009b5c, 0x0000001d },
589 + { 0x00009b60, 0x00000020 },
590 + { 0x00009b64, 0x00000021 },
591 + { 0x00009b68, 0x00000022 },
592 + { 0x00009b6c, 0x00000023 },
593 + { 0x00009b70, 0x00000024 },
594 + { 0x00009b74, 0x00000025 },
595 + { 0x00009b78, 0x00000028 },
596 + { 0x00009b7c, 0x00000029 },
597 + { 0x00009b80, 0x0000002a },
598 + { 0x00009b84, 0x0000002b },
599 + { 0x00009b88, 0x0000002c },
600 + { 0x00009b8c, 0x0000002d },
601 + { 0x00009b90, 0x00000030 },
602 + { 0x00009b94, 0x00000031 },
603 + { 0x00009b98, 0x00000032 },
604 + { 0x00009b9c, 0x00000033 },
605 + { 0x00009ba0, 0x00000034 },
606 + { 0x00009ba4, 0x00000035 },
607 + { 0x00009ba8, 0x00000035 },
608 + { 0x00009bac, 0x00000035 },
609 + { 0x00009bb0, 0x00000035 },
610 + { 0x00009bb4, 0x00000035 },
611 + { 0x00009bb8, 0x00000035 },
612 + { 0x00009bbc, 0x00000035 },
613 + { 0x00009bc0, 0x00000035 },
614 + { 0x00009bc4, 0x00000035 },
615 + { 0x00009bc8, 0x00000035 },
616 + { 0x00009bcc, 0x00000035 },
617 + { 0x00009bd0, 0x00000035 },
618 + { 0x00009bd4, 0x00000035 },
619 + { 0x00009bd8, 0x00000035 },
620 + { 0x00009bdc, 0x00000035 },
621 + { 0x00009be0, 0x00000035 },
622 + { 0x00009be4, 0x00000035 },
623 + { 0x00009be8, 0x00000035 },
624 + { 0x00009bec, 0x00000035 },
625 + { 0x00009bf0, 0x00000035 },
626 + { 0x00009bf4, 0x00000035 },
627 + { 0x00009bf8, 0x00000010 },
628 + { 0x00009bfc, 0x0000001a },
629 + { 0x0000a210, 0x40806333 },
630 + { 0x0000a214, 0x00106c10 },
631 + { 0x0000a218, 0x009c4060 },
632 + { 0x0000a220, 0x018830c6 },
633 + { 0x0000a224, 0x00000400 },
634 + { 0x0000a228, 0x00000bb5 },
635 + { 0x0000a22c, 0x00000011 },
636 + { 0x0000a234, 0x20202020 },
637 + { 0x0000a238, 0x20202020 },
638 + { 0x0000a23c, 0x13c889af },
639 + { 0x0000a240, 0x38490a20 },
640 + { 0x0000a244, 0x00007bb6 },
641 + { 0x0000a248, 0x0fff3ffc },
642 + { 0x0000a24c, 0x00000001 },
643 + { 0x0000a250, 0x0000a000 },
644 + { 0x0000a254, 0x00000000 },
645 + { 0x0000a258, 0x0cc75380 },
646 + { 0x0000a25c, 0x0f0f0f01 },
647 + { 0x0000a260, 0xdfa91f01 },
648 + { 0x0000a268, 0x00000000 },
649 + { 0x0000a26c, 0x0e79e5c6 },
650 + { 0x0000b26c, 0x0e79e5c6 },
651 + { 0x0000c26c, 0x0e79e5c6 },
652 + { 0x0000d270, 0x00820820 },
653 + { 0x0000a278, 0x1ce739ce },
654 + { 0x0000a27c, 0x051701ce },
655 + { 0x0000a338, 0x00000000 },
656 + { 0x0000a33c, 0x00000000 },
657 + { 0x0000a340, 0x00000000 },
658 + { 0x0000a344, 0x00000000 },
659 + { 0x0000a348, 0x3fffffff },
660 + { 0x0000a34c, 0x3fffffff },
661 + { 0x0000a350, 0x3fffffff },
662 + { 0x0000a354, 0x0003ffff },
663 + { 0x0000a358, 0x79a8aa1f },
664 + { 0x0000d35c, 0x07ffffef },
665 + { 0x0000d360, 0x0fffffe7 },
666 + { 0x0000d364, 0x17ffffe5 },
667 + { 0x0000d368, 0x1fffffe4 },
668 + { 0x0000d36c, 0x37ffffe3 },
669 + { 0x0000d370, 0x3fffffe3 },
670 + { 0x0000d374, 0x57ffffe3 },
671 + { 0x0000d378, 0x5fffffe2 },
672 + { 0x0000d37c, 0x7fffffe2 },
673 + { 0x0000d380, 0x7f3c7bba },
674 + { 0x0000d384, 0xf3307ff0 },
675 + { 0x0000a388, 0x08000000 },
676 + { 0x0000a38c, 0x20202020 },
677 + { 0x0000a390, 0x20202020 },
678 + { 0x0000a394, 0x1ce739ce },
679 + { 0x0000a398, 0x000001ce },
680 + { 0x0000a39c, 0x00000001 },
681 + { 0x0000a3a0, 0x00000000 },
682 + { 0x0000a3a4, 0x00000000 },
683 + { 0x0000a3a8, 0x00000000 },
684 + { 0x0000a3ac, 0x00000000 },
685 + { 0x0000a3b0, 0x00000000 },
686 + { 0x0000a3b4, 0x00000000 },
687 + { 0x0000a3b8, 0x00000000 },
688 + { 0x0000a3bc, 0x00000000 },
689 + { 0x0000a3c0, 0x00000000 },
690 + { 0x0000a3c4, 0x00000000 },
691 + { 0x0000a3c8, 0x00000246 },
692 + { 0x0000a3cc, 0x20202020 },
693 + { 0x0000a3d0, 0x20202020 },
694 + { 0x0000a3d4, 0x20202020 },
695 + { 0x0000a3dc, 0x1ce739ce },
696 + { 0x0000a3e0, 0x000001ce },
697 +};
698 +
699 +static const u32 ar5416Bank0[][2] = {
700 + { 0x000098b0, 0x1e5795e5 },
701 + { 0x000098e0, 0x02008020 },
702 +};
703 +
704 +static const u32 ar5416BB_RfGain[][3] = {
705 + { 0x00009a00, 0x00000000, 0x00000000 },
706 + { 0x00009a04, 0x00000040, 0x00000040 },
707 + { 0x00009a08, 0x00000080, 0x00000080 },
708 + { 0x00009a0c, 0x000001a1, 0x00000141 },
709 + { 0x00009a10, 0x000001e1, 0x00000181 },
710 + { 0x00009a14, 0x00000021, 0x000001c1 },
711 + { 0x00009a18, 0x00000061, 0x00000001 },
712 + { 0x00009a1c, 0x00000168, 0x00000041 },
713 + { 0x00009a20, 0x000001a8, 0x000001a8 },
714 + { 0x00009a24, 0x000001e8, 0x000001e8 },
715 + { 0x00009a28, 0x00000028, 0x00000028 },
716 + { 0x00009a2c, 0x00000068, 0x00000068 },
717 + { 0x00009a30, 0x00000189, 0x000000a8 },
718 + { 0x00009a34, 0x000001c9, 0x00000169 },
719 + { 0x00009a38, 0x00000009, 0x000001a9 },
720 + { 0x00009a3c, 0x00000049, 0x000001e9 },
721 + { 0x00009a40, 0x00000089, 0x00000029 },
722 + { 0x00009a44, 0x00000170, 0x00000069 },
723 + { 0x00009a48, 0x000001b0, 0x00000190 },
724 + { 0x00009a4c, 0x000001f0, 0x000001d0 },
725 + { 0x00009a50, 0x00000030, 0x00000010 },
726 + { 0x00009a54, 0x00000070, 0x00000050 },
727 + { 0x00009a58, 0x00000191, 0x00000090 },
728 + { 0x00009a5c, 0x000001d1, 0x00000151 },
729 + { 0x00009a60, 0x00000011, 0x00000191 },
730 + { 0x00009a64, 0x00000051, 0x000001d1 },
731 + { 0x00009a68, 0x00000091, 0x00000011 },
732 + { 0x00009a6c, 0x000001b8, 0x00000051 },
733 + { 0x00009a70, 0x000001f8, 0x00000198 },
734 + { 0x00009a74, 0x00000038, 0x000001d8 },
735 + { 0x00009a78, 0x00000078, 0x00000018 },
736 + { 0x00009a7c, 0x00000199, 0x00000058 },
737 + { 0x00009a80, 0x000001d9, 0x00000098 },
738 + { 0x00009a84, 0x00000019, 0x00000159 },
739 + { 0x00009a88, 0x00000059, 0x00000199 },
740 + { 0x00009a8c, 0x00000099, 0x000001d9 },
741 + { 0x00009a90, 0x000000d9, 0x00000019 },
742 + { 0x00009a94, 0x000000f9, 0x00000059 },
743 + { 0x00009a98, 0x000000f9, 0x00000099 },
744 + { 0x00009a9c, 0x000000f9, 0x000000d9 },
745 + { 0x00009aa0, 0x000000f9, 0x000000f9 },
746 + { 0x00009aa4, 0x000000f9, 0x000000f9 },
747 + { 0x00009aa8, 0x000000f9, 0x000000f9 },
748 + { 0x00009aac, 0x000000f9, 0x000000f9 },
749 + { 0x00009ab0, 0x000000f9, 0x000000f9 },
750 + { 0x00009ab4, 0x000000f9, 0x000000f9 },
751 + { 0x00009ab8, 0x000000f9, 0x000000f9 },
752 + { 0x00009abc, 0x000000f9, 0x000000f9 },
753 + { 0x00009ac0, 0x000000f9, 0x000000f9 },
754 + { 0x00009ac4, 0x000000f9, 0x000000f9 },
755 + { 0x00009ac8, 0x000000f9, 0x000000f9 },
756 + { 0x00009acc, 0x000000f9, 0x000000f9 },
757 + { 0x00009ad0, 0x000000f9, 0x000000f9 },
758 + { 0x00009ad4, 0x000000f9, 0x000000f9 },
759 + { 0x00009ad8, 0x000000f9, 0x000000f9 },
760 + { 0x00009adc, 0x000000f9, 0x000000f9 },
761 + { 0x00009ae0, 0x000000f9, 0x000000f9 },
762 + { 0x00009ae4, 0x000000f9, 0x000000f9 },
763 + { 0x00009ae8, 0x000000f9, 0x000000f9 },
764 + { 0x00009aec, 0x000000f9, 0x000000f9 },
765 + { 0x00009af0, 0x000000f9, 0x000000f9 },
766 + { 0x00009af4, 0x000000f9, 0x000000f9 },
767 + { 0x00009af8, 0x000000f9, 0x000000f9 },
768 + { 0x00009afc, 0x000000f9, 0x000000f9 },
769 +};
770 +
771 +static const u32 ar5416Bank1[][2] = {
772 + { 0x000098b0, 0x02108421 },
773 + { 0x000098ec, 0x00000008 },
774 +};
775 +
776 +static const u32 ar5416Bank2[][2] = {
777 + { 0x000098b0, 0x0e73ff17 },
778 + { 0x000098e0, 0x00000420 },
779 +};
780 +
781 +static const u32 ar5416Bank3[][3] = {
782 + { 0x000098f0, 0x01400018, 0x01c00018 },
783 +};
784 +
785 +static const u32 ar5416Bank6[][3] = {
786 +
787 + { 0x0000989c, 0x00000000, 0x00000000 },
788 + { 0x0000989c, 0x00000000, 0x00000000 },
789 + { 0x0000989c, 0x00000000, 0x00000000 },
790 + { 0x0000989c, 0x00e00000, 0x00e00000 },
791 + { 0x0000989c, 0x005e0000, 0x005e0000 },
792 + { 0x0000989c, 0x00120000, 0x00120000 },
793 + { 0x0000989c, 0x00620000, 0x00620000 },
794 + { 0x0000989c, 0x00020000, 0x00020000 },
795 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
796 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
797 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
798 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
799 + { 0x0000989c, 0x005f0000, 0x005f0000 },
800 + { 0x0000989c, 0x00870000, 0x00870000 },
801 + { 0x0000989c, 0x00f90000, 0x00f90000 },
802 + { 0x0000989c, 0x007b0000, 0x007b0000 },
803 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
804 + { 0x0000989c, 0x00f50000, 0x00f50000 },
805 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
806 + { 0x0000989c, 0x00110000, 0x00110000 },
807 + { 0x0000989c, 0x006100a8, 0x006100a8 },
808 + { 0x0000989c, 0x004210a2, 0x004210a2 },
809 + { 0x0000989c, 0x0014008f, 0x0014008f },
810 + { 0x0000989c, 0x00c40003, 0x00c40003 },
811 + { 0x0000989c, 0x003000f2, 0x003000f2 },
812 + { 0x0000989c, 0x00440016, 0x00440016 },
813 + { 0x0000989c, 0x00410040, 0x00410040 },
814 + { 0x0000989c, 0x0001805e, 0x0001805e },
815 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
816 + { 0x0000989c, 0x000000f1, 0x000000f1 },
817 + { 0x0000989c, 0x00002081, 0x00002081 },
818 + { 0x0000989c, 0x000000d4, 0x000000d4 },
819 + { 0x000098d0, 0x0000000f, 0x0010000f },
820 +};
821 +
822 +static const u32 ar5416Bank6TPC[][3] = {
823 + { 0x0000989c, 0x00000000, 0x00000000 },
824 + { 0x0000989c, 0x00000000, 0x00000000 },
825 + { 0x0000989c, 0x00000000, 0x00000000 },
826 + { 0x0000989c, 0x00e00000, 0x00e00000 },
827 + { 0x0000989c, 0x005e0000, 0x005e0000 },
828 + { 0x0000989c, 0x00120000, 0x00120000 },
829 + { 0x0000989c, 0x00620000, 0x00620000 },
830 + { 0x0000989c, 0x00020000, 0x00020000 },
831 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
832 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
833 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
834 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
835 + { 0x0000989c, 0x005f0000, 0x005f0000 },
836 + { 0x0000989c, 0x00870000, 0x00870000 },
837 + { 0x0000989c, 0x00f90000, 0x00f90000 },
838 + { 0x0000989c, 0x007b0000, 0x007b0000 },
839 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
840 + { 0x0000989c, 0x00f50000, 0x00f50000 },
841 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
842 + { 0x0000989c, 0x00110000, 0x00110000 },
843 + { 0x0000989c, 0x006100a8, 0x006100a8 },
844 + { 0x0000989c, 0x00423022, 0x00423022 },
845 + { 0x0000989c, 0x201400df, 0x201400df },
846 + { 0x0000989c, 0x00c40002, 0x00c40002 },
847 + { 0x0000989c, 0x003000f2, 0x003000f2 },
848 + { 0x0000989c, 0x00440016, 0x00440016 },
849 + { 0x0000989c, 0x00410040, 0x00410040 },
850 + { 0x0000989c, 0x0001805e, 0x0001805e },
851 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
852 + { 0x0000989c, 0x000000e1, 0x000000e1 },
853 + { 0x0000989c, 0x00007081, 0x00007081 },
854 + { 0x0000989c, 0x000000d4, 0x000000d4 },
855 + { 0x000098d0, 0x0000000f, 0x0010000f },
856 +};
857 +
858 +static const u32 ar5416Bank7[][2] = {
859 + { 0x0000989c, 0x00000500 },
860 + { 0x0000989c, 0x00000800 },
861 + { 0x000098cc, 0x0000000e },
862 +};
863 +
864 +static const u32 ar5416Addac[][2] = {
865 + {0x0000989c, 0x00000000 },
866 + {0x0000989c, 0x00000003 },
867 + {0x0000989c, 0x00000000 },
868 + {0x0000989c, 0x0000000c },
869 + {0x0000989c, 0x00000000 },
870 + {0x0000989c, 0x00000030 },
871 + {0x0000989c, 0x00000000 },
872 + {0x0000989c, 0x00000000 },
873 + {0x0000989c, 0x00000000 },
874 + {0x0000989c, 0x00000000 },
875 + {0x0000989c, 0x00000000 },
876 + {0x0000989c, 0x00000000 },
877 + {0x0000989c, 0x00000000 },
878 + {0x0000989c, 0x00000000 },
879 + {0x0000989c, 0x00000000 },
880 + {0x0000989c, 0x00000000 },
881 + {0x0000989c, 0x00000000 },
882 + {0x0000989c, 0x00000000 },
883 + {0x0000989c, 0x00000060 },
884 + {0x0000989c, 0x00000000 },
885 + {0x0000989c, 0x00000000 },
886 + {0x0000989c, 0x00000000 },
887 + {0x0000989c, 0x00000000 },
888 + {0x0000989c, 0x00000000 },
889 + {0x0000989c, 0x00000000 },
890 + {0x0000989c, 0x00000000 },
891 + {0x0000989c, 0x00000000 },
892 + {0x0000989c, 0x00000000 },
893 + {0x0000989c, 0x00000000 },
894 + {0x0000989c, 0x00000000 },
895 + {0x0000989c, 0x00000000 },
896 + {0x0000989c, 0x00000058 },
897 + {0x0000989c, 0x00000000 },
898 + {0x0000989c, 0x00000000 },
899 + {0x0000989c, 0x00000000 },
900 + {0x0000989c, 0x00000000 },
901 + {0x000098cc, 0x00000000 },
902 +};
903 +
904 +static const u32 ar5416Modes_9100[][6] = {
905 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
906 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
907 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
908 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
909 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
910 + { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
911 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
912 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
913 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
914 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
915 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
916 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
917 + { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
918 + { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
919 + { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
920 + { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
921 + { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
922 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },
923 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
924 + { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
925 + { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
926 + { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
927 + { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
928 + { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
929 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
930 + { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },
931 + { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
932 + { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
933 + { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
934 + { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
935 +#ifdef TB243
936 + { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
937 + { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
938 + { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
939 + { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
940 +#else
941 + { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
942 + { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
943 + { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
944 + { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
945 +#endif
946 + { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
947 + { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
948 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
949 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
950 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
951 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
952 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
953 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
954 + { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
955 + { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
956 + { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
957 + { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
958 + { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
959 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
960 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
961 + { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
962 + { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
963 + { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
964 + { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
965 + { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
966 + { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
967 + { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
968 + { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
969 + { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
970 + { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
971 + { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
972 + { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
973 + { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
974 + { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
975 + { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
976 +};
977 +
978 +#endif /* INITVALS_AR5008_H */
979 --- /dev/null
980 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
981 @@ -0,0 +1,1278 @@
982 +/*
983 + * Copyright (c) 2008-2010 Atheros Communications Inc.
984 + *
985 + * Permission to use, copy, modify, and/or distribute this software for any
986 + * purpose with or without fee is hereby granted, provided that the above
987 + * copyright notice and this permission notice appear in all copies.
988 + *
989 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
990 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
991 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
992 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
993 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
994 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
995 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
996 + */
997 +
998 +#include "hw.h"
999 +#include "hw-ops.h"
1000 +#include "../regd.h"
1001 +#include "ar9002_phy.h"
1002 +
1003 +/* All code below is for non single-chip solutions */
1004 +
1005 +/**
1006 + * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
1007 + * @rfbuf:
1008 + * @reg32:
1009 + * @numBits:
1010 + * @firstBit:
1011 + * @column:
1012 + *
1013 + * Performs analog "swizzling" of parameters into their location.
1014 + * Used on external AR2133/AR5133 radios.
1015 + */
1016 +static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
1017 + u32 numBits, u32 firstBit,
1018 + u32 column)
1019 +{
1020 + u32 tmp32, mask, arrayEntry, lastBit;
1021 + int32_t bitPosition, bitsLeft;
1022 +
1023 + tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
1024 + arrayEntry = (firstBit - 1) / 8;
1025 + bitPosition = (firstBit - 1) % 8;
1026 + bitsLeft = numBits;
1027 + while (bitsLeft > 0) {
1028 + lastBit = (bitPosition + bitsLeft > 8) ?
1029 + 8 : bitPosition + bitsLeft;
1030 + mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
1031 + (column * 8);
1032 + rfBuf[arrayEntry] &= ~mask;
1033 + rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
1034 + (column * 8)) & mask;
1035 + bitsLeft -= 8 - bitPosition;
1036 + tmp32 = tmp32 >> (8 - bitPosition);
1037 + bitPosition = 0;
1038 + arrayEntry++;
1039 + }
1040 +}
1041 +
1042 +/*
1043 + * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
1044 + * rf_pwd_icsyndiv.
1045 + *
1046 + * Theoretical Rules:
1047 + * if 2 GHz band
1048 + * if forceBiasAuto
1049 + * if synth_freq < 2412
1050 + * bias = 0
1051 + * else if 2412 <= synth_freq <= 2422
1052 + * bias = 1
1053 + * else // synth_freq > 2422
1054 + * bias = 2
1055 + * else if forceBias > 0
1056 + * bias = forceBias & 7
1057 + * else
1058 + * no change, use value from ini file
1059 + * else
1060 + * no change, invalid band
1061 + *
1062 + * 1st Mod:
1063 + * 2422 also uses value of 2
1064 + * <approved>
1065 + *
1066 + * 2nd Mod:
1067 + * Less than 2412 uses value of 0, 2412 and above uses value of 2
1068 + */
1069 +static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
1070 +{
1071 + struct ath_common *common = ath9k_hw_common(ah);
1072 + u32 tmp_reg;
1073 + int reg_writes = 0;
1074 + u32 new_bias = 0;
1075 +
1076 + if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
1077 + return;
1078 + }
1079 +
1080 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1081 +
1082 + if (synth_freq < 2412)
1083 + new_bias = 0;
1084 + else if (synth_freq < 2422)
1085 + new_bias = 1;
1086 + else
1087 + new_bias = 2;
1088 +
1089 + /* pre-reverse this field */
1090 + tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
1091 +
1092 + ath_print(common, ATH_DBG_CONFIG,
1093 + "Force rf_pwd_icsyndiv to %1d on %4d\n",
1094 + new_bias, synth_freq);
1095 +
1096 + /* swizzle rf_pwd_icsyndiv */
1097 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
1098 +
1099 + /* write Bank 6 with new params */
1100 + REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
1101 +}
1102 +
1103 +/**
1104 + * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
1105 + * @ah: atheros hardware stucture
1106 + * @chan:
1107 + *
1108 + * For the external AR2133/AR5133 radios, takes the MHz channel value and set
1109 + * the channel value. Assumes writes enabled to analog bus and bank6 register
1110 + * cache in ah->analogBank6Data.
1111 + */
1112 +static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
1113 +{
1114 + struct ath_common *common = ath9k_hw_common(ah);
1115 + u32 channelSel = 0;
1116 + u32 bModeSynth = 0;
1117 + u32 aModeRefSel = 0;
1118 + u32 reg32 = 0;
1119 + u16 freq;
1120 + struct chan_centers centers;
1121 +
1122 + ath9k_hw_get_channel_centers(ah, chan, &centers);
1123 + freq = centers.synth_center;
1124 +
1125 + if (freq < 4800) {
1126 + u32 txctl;
1127 +
1128 + if (((freq - 2192) % 5) == 0) {
1129 + channelSel = ((freq - 672) * 2 - 3040) / 10;
1130 + bModeSynth = 0;
1131 + } else if (((freq - 2224) % 5) == 0) {
1132 + channelSel = ((freq - 704) * 2 - 3040) / 10;
1133 + bModeSynth = 1;
1134 + } else {
1135 + ath_print(common, ATH_DBG_FATAL,
1136 + "Invalid channel %u MHz\n", freq);
1137 + return -EINVAL;
1138 + }
1139 +
1140 + channelSel = (channelSel << 2) & 0xff;
1141 + channelSel = ath9k_hw_reverse_bits(channelSel, 8);
1142 +
1143 + txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
1144 + if (freq == 2484) {
1145 +
1146 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1147 + txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
1148 + } else {
1149 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1150 + txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
1151 + }
1152 +
1153 + } else if ((freq % 20) == 0 && freq >= 5120) {
1154 + channelSel =
1155 + ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
1156 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1157 + } else if ((freq % 10) == 0) {
1158 + channelSel =
1159 + ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
1160 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1161 + aModeRefSel = ath9k_hw_reverse_bits(2, 2);
1162 + else
1163 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1164 + } else if ((freq % 5) == 0) {
1165 + channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
1166 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1167 + } else {
1168 + ath_print(common, ATH_DBG_FATAL,
1169 + "Invalid channel %u MHz\n", freq);
1170 + return -EINVAL;
1171 + }
1172 +
1173 + ar5008_hw_force_bias(ah, freq);
1174 +
1175 + reg32 =
1176 + (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
1177 + (1 << 5) | 0x1;
1178 +
1179 + REG_WRITE(ah, AR_PHY(0x37), reg32);
1180 +
1181 + ah->curchan = chan;
1182 + ah->curchan_rad_index = -1;
1183 +
1184 + return 0;
1185 +}
1186 +
1187 +/**
1188 + * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
1189 + * @ah: atheros hardware structure
1190 + * @chan:
1191 + *
1192 + * For non single-chip solutions. Converts to baseband spur frequency given the
1193 + * input channel frequency and compute register settings below.
1194 + */
1195 +static void ar5008_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1196 +{
1197 + int bb_spur = AR_NO_SPUR;
1198 + int bin, cur_bin;
1199 + int spur_freq_sd;
1200 + int spur_delta_phase;
1201 + int denominator;
1202 + int upper, lower, cur_vit_mask;
1203 + int tmp, new;
1204 + int i;
1205 + int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1206 + AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1207 + };
1208 + int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1209 + AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1210 + };
1211 + int inc[4] = { 0, 100, 0, 0 };
1212 +
1213 + int8_t mask_m[123];
1214 + int8_t mask_p[123];
1215 + int8_t mask_amt;
1216 + int tmp_mask;
1217 + int cur_bb_spur;
1218 + bool is2GHz = IS_CHAN_2GHZ(chan);
1219 +
1220 + memset(&mask_m, 0, sizeof(int8_t) * 123);
1221 + memset(&mask_p, 0, sizeof(int8_t) * 123);
1222 +
1223 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1224 + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1225 + if (AR_NO_SPUR == cur_bb_spur)
1226 + break;
1227 + cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1228 + if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1229 + bb_spur = cur_bb_spur;
1230 + break;
1231 + }
1232 + }
1233 +
1234 + if (AR_NO_SPUR == bb_spur)
1235 + return;
1236 +
1237 + bin = bb_spur * 32;
1238 +
1239 + tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1240 + new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1241 + AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1242 + AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1243 + AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1244 +
1245 + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
1246 +
1247 + new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1248 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1249 + AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1250 + AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1251 + SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1252 + REG_WRITE(ah, AR_PHY_SPUR_REG, new);
1253 +
1254 + spur_delta_phase = ((bb_spur * 524288) / 100) &
1255 + AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1256 +
1257 + denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
1258 + spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
1259 +
1260 + new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1261 + SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1262 + SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1263 + REG_WRITE(ah, AR_PHY_TIMING11, new);
1264 +
1265 + cur_bin = -6000;
1266 + upper = bin + 100;
1267 + lower = bin - 100;
1268 +
1269 + for (i = 0; i < 4; i++) {
1270 + int pilot_mask = 0;
1271 + int chan_mask = 0;
1272 + int bp = 0;
1273 + for (bp = 0; bp < 30; bp++) {
1274 + if ((cur_bin > lower) && (cur_bin < upper)) {
1275 + pilot_mask = pilot_mask | 0x1 << bp;
1276 + chan_mask = chan_mask | 0x1 << bp;
1277 + }
1278 + cur_bin += 100;
1279 + }
1280 + cur_bin += inc[i];
1281 + REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1282 + REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1283 + }
1284 +
1285 + cur_vit_mask = 6100;
1286 + upper = bin + 120;
1287 + lower = bin - 120;
1288 +
1289 + for (i = 0; i < 123; i++) {
1290 + if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1291 +
1292 + /* workaround for gcc bug #37014 */
1293 + volatile int tmp_v = abs(cur_vit_mask - bin);
1294 +
1295 + if (tmp_v < 75)
1296 + mask_amt = 1;
1297 + else
1298 + mask_amt = 0;
1299 + if (cur_vit_mask < 0)
1300 + mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1301 + else
1302 + mask_p[cur_vit_mask / 100] = mask_amt;
1303 + }
1304 + cur_vit_mask -= 100;
1305 + }
1306 +
1307 + tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1308 + | (mask_m[48] << 26) | (mask_m[49] << 24)
1309 + | (mask_m[50] << 22) | (mask_m[51] << 20)
1310 + | (mask_m[52] << 18) | (mask_m[53] << 16)
1311 + | (mask_m[54] << 14) | (mask_m[55] << 12)
1312 + | (mask_m[56] << 10) | (mask_m[57] << 8)
1313 + | (mask_m[58] << 6) | (mask_m[59] << 4)
1314 + | (mask_m[60] << 2) | (mask_m[61] << 0);
1315 + REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1316 + REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1317 +
1318 + tmp_mask = (mask_m[31] << 28)
1319 + | (mask_m[32] << 26) | (mask_m[33] << 24)
1320 + | (mask_m[34] << 22) | (mask_m[35] << 20)
1321 + | (mask_m[36] << 18) | (mask_m[37] << 16)
1322 + | (mask_m[48] << 14) | (mask_m[39] << 12)
1323 + | (mask_m[40] << 10) | (mask_m[41] << 8)
1324 + | (mask_m[42] << 6) | (mask_m[43] << 4)
1325 + | (mask_m[44] << 2) | (mask_m[45] << 0);
1326 + REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1327 + REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1328 +
1329 + tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1330 + | (mask_m[18] << 26) | (mask_m[18] << 24)
1331 + | (mask_m[20] << 22) | (mask_m[20] << 20)
1332 + | (mask_m[22] << 18) | (mask_m[22] << 16)
1333 + | (mask_m[24] << 14) | (mask_m[24] << 12)
1334 + | (mask_m[25] << 10) | (mask_m[26] << 8)
1335 + | (mask_m[27] << 6) | (mask_m[28] << 4)
1336 + | (mask_m[29] << 2) | (mask_m[30] << 0);
1337 + REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1338 + REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1339 +
1340 + tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1341 + | (mask_m[2] << 26) | (mask_m[3] << 24)
1342 + | (mask_m[4] << 22) | (mask_m[5] << 20)
1343 + | (mask_m[6] << 18) | (mask_m[7] << 16)
1344 + | (mask_m[8] << 14) | (mask_m[9] << 12)
1345 + | (mask_m[10] << 10) | (mask_m[11] << 8)
1346 + | (mask_m[12] << 6) | (mask_m[13] << 4)
1347 + | (mask_m[14] << 2) | (mask_m[15] << 0);
1348 + REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1349 + REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1350 +
1351 + tmp_mask = (mask_p[15] << 28)
1352 + | (mask_p[14] << 26) | (mask_p[13] << 24)
1353 + | (mask_p[12] << 22) | (mask_p[11] << 20)
1354 + | (mask_p[10] << 18) | (mask_p[9] << 16)
1355 + | (mask_p[8] << 14) | (mask_p[7] << 12)
1356 + | (mask_p[6] << 10) | (mask_p[5] << 8)
1357 + | (mask_p[4] << 6) | (mask_p[3] << 4)
1358 + | (mask_p[2] << 2) | (mask_p[1] << 0);
1359 + REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1360 + REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1361 +
1362 + tmp_mask = (mask_p[30] << 28)
1363 + | (mask_p[29] << 26) | (mask_p[28] << 24)
1364 + | (mask_p[27] << 22) | (mask_p[26] << 20)
1365 + | (mask_p[25] << 18) | (mask_p[24] << 16)
1366 + | (mask_p[23] << 14) | (mask_p[22] << 12)
1367 + | (mask_p[21] << 10) | (mask_p[20] << 8)
1368 + | (mask_p[19] << 6) | (mask_p[18] << 4)
1369 + | (mask_p[17] << 2) | (mask_p[16] << 0);
1370 + REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1371 + REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1372 +
1373 + tmp_mask = (mask_p[45] << 28)
1374 + | (mask_p[44] << 26) | (mask_p[43] << 24)
1375 + | (mask_p[42] << 22) | (mask_p[41] << 20)
1376 + | (mask_p[40] << 18) | (mask_p[39] << 16)
1377 + | (mask_p[38] << 14) | (mask_p[37] << 12)
1378 + | (mask_p[36] << 10) | (mask_p[35] << 8)
1379 + | (mask_p[34] << 6) | (mask_p[33] << 4)
1380 + | (mask_p[32] << 2) | (mask_p[31] << 0);
1381 + REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1382 + REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1383 +
1384 + tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1385 + | (mask_p[59] << 26) | (mask_p[58] << 24)
1386 + | (mask_p[57] << 22) | (mask_p[56] << 20)
1387 + | (mask_p[55] << 18) | (mask_p[54] << 16)
1388 + | (mask_p[53] << 14) | (mask_p[52] << 12)
1389 + | (mask_p[51] << 10) | (mask_p[50] << 8)
1390 + | (mask_p[49] << 6) | (mask_p[48] << 4)
1391 + | (mask_p[47] << 2) | (mask_p[46] << 0);
1392 + REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1393 + REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1394 +}
1395 +
1396 +/**
1397 + * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
1398 + * @ah: atheros hardware structure
1399 + *
1400 + * Only required for older devices with external AR2133/AR5133 radios.
1401 + */
1402 +static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
1403 +{
1404 +#define ATH_ALLOC_BANK(bank, size) do { \
1405 + bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
1406 + if (!bank) { \
1407 + ath_print(common, ATH_DBG_FATAL, \
1408 + "Cannot allocate RF banks\n"); \
1409 + return -ENOMEM; \
1410 + } \
1411 + } while (0);
1412 +
1413 + struct ath_common *common = ath9k_hw_common(ah);
1414 +
1415 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1416 +
1417 + ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
1418 + ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
1419 + ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
1420 + ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
1421 + ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
1422 + ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
1423 + ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
1424 + ATH_ALLOC_BANK(ah->addac5416_21,
1425 + ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
1426 + ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
1427 +
1428 + return 0;
1429 +#undef ATH_ALLOC_BANK
1430 +}
1431 +
1432 +
1433 +/**
1434 + * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
1435 + * @ah: atheros hardware struture
1436 + * For the external AR2133/AR5133 radios banks.
1437 + */
1438 +static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
1439 +{
1440 +#define ATH_FREE_BANK(bank) do { \
1441 + kfree(bank); \
1442 + bank = NULL; \
1443 + } while (0);
1444 +
1445 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1446 +
1447 + ATH_FREE_BANK(ah->analogBank0Data);
1448 + ATH_FREE_BANK(ah->analogBank1Data);
1449 + ATH_FREE_BANK(ah->analogBank2Data);
1450 + ATH_FREE_BANK(ah->analogBank3Data);
1451 + ATH_FREE_BANK(ah->analogBank6Data);
1452 + ATH_FREE_BANK(ah->analogBank6TPCData);
1453 + ATH_FREE_BANK(ah->analogBank7Data);
1454 + ATH_FREE_BANK(ah->addac5416_21);
1455 + ATH_FREE_BANK(ah->bank6Temp);
1456 +
1457 +#undef ATH_FREE_BANK
1458 +}
1459 +
1460 +/* *
1461 + * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
1462 + * @ah: atheros hardware structure
1463 + * @chan:
1464 + * @modesIndex:
1465 + *
1466 + * Used for the external AR2133/AR5133 radios.
1467 + *
1468 + * Reads the EEPROM header info from the device structure and programs
1469 + * all rf registers. This routine requires access to the analog
1470 + * rf device. This is not required for single-chip devices.
1471 + */
1472 +static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
1473 + struct ath9k_channel *chan,
1474 + u16 modesIndex)
1475 +{
1476 + u32 eepMinorRev;
1477 + u32 ob5GHz = 0, db5GHz = 0;
1478 + u32 ob2GHz = 0, db2GHz = 0;
1479 + int regWrites = 0;
1480 +
1481 + /*
1482 + * Software does not need to program bank data
1483 + * for single chip devices, that is AR9280 or anything
1484 + * after that.
1485 + */
1486 + if (AR_SREV_9280_10_OR_LATER(ah))
1487 + return true;
1488 +
1489 + /* Setup rf parameters */
1490 + eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
1491 +
1492 + /* Setup Bank 0 Write */
1493 + RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
1494 +
1495 + /* Setup Bank 1 Write */
1496 + RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
1497 +
1498 + /* Setup Bank 2 Write */
1499 + RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
1500 +
1501 + /* Setup Bank 6 Write */
1502 + RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
1503 + modesIndex);
1504 + {
1505 + int i;
1506 + for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
1507 + ah->analogBank6Data[i] =
1508 + INI_RA(&ah->iniBank6TPC, i, modesIndex);
1509 + }
1510 + }
1511 +
1512 + /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
1513 + if (eepMinorRev >= 2) {
1514 + if (IS_CHAN_2GHZ(chan)) {
1515 + ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
1516 + db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
1517 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1518 + ob2GHz, 3, 197, 0);
1519 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1520 + db2GHz, 3, 194, 0);
1521 + } else {
1522 + ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
1523 + db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
1524 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1525 + ob5GHz, 3, 203, 0);
1526 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1527 + db5GHz, 3, 200, 0);
1528 + }
1529 + }
1530 +
1531 + /* Setup Bank 7 Setup */
1532 + RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
1533 +
1534 + /* Write Analog registers */
1535 + REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
1536 + regWrites);
1537 + REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
1538 + regWrites);
1539 + REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
1540 + regWrites);
1541 + REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
1542 + regWrites);
1543 + REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
1544 + regWrites);
1545 + REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
1546 + regWrites);
1547 +
1548 + return true;
1549 +}
1550 +
1551 +static void ar5008_hw_init_bb(struct ath_hw *ah,
1552 + struct ath9k_channel *chan)
1553 +{
1554 + u32 synthDelay;
1555 +
1556 + synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1557 + if (IS_CHAN_B(chan))
1558 + synthDelay = (4 * synthDelay) / 22;
1559 + else
1560 + synthDelay /= 10;
1561 +
1562 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1563 +
1564 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
1565 +}
1566 +
1567 +static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
1568 +{
1569 + int rx_chainmask, tx_chainmask;
1570 +
1571 + rx_chainmask = ah->rxchainmask;
1572 + tx_chainmask = ah->txchainmask;
1573 +
1574 + switch (rx_chainmask) {
1575 + case 0x5:
1576 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1577 + AR_PHY_SWAP_ALT_CHAIN);
1578 + case 0x3:
1579 + if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1580 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1581 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1582 + break;
1583 + }
1584 + case 0x1:
1585 + case 0x2:
1586 + case 0x7:
1587 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1588 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1589 + break;
1590 + default:
1591 + break;
1592 + }
1593 +
1594 + REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1595 + if (tx_chainmask == 0x5) {
1596 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1597 + AR_PHY_SWAP_ALT_CHAIN);
1598 + }
1599 + if (AR_SREV_9100(ah))
1600 + REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1601 + REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1602 +}
1603 +
1604 +static void ar5008_hw_override_ini(struct ath_hw *ah,
1605 + struct ath9k_channel *chan)
1606 +{
1607 + u32 val;
1608 +
1609 + /*
1610 + * Set the RX_ABORT and RX_DIS and clear if off only after
1611 + * RXE is set for MAC. This prevents frames with corrupted
1612 + * descriptor status.
1613 + */
1614 + REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1615 +
1616 + if (AR_SREV_9280_10_OR_LATER(ah)) {
1617 + val = REG_READ(ah, AR_PCU_MISC_MODE2);
1618 +
1619 + if (!AR_SREV_9271(ah))
1620 + val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1621 +
1622 + if (AR_SREV_9287_10_OR_LATER(ah))
1623 + val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1624 +
1625 + REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1626 + }
1627 +
1628 + if (!AR_SREV_5416_20_OR_LATER(ah) ||
1629 + AR_SREV_9280_10_OR_LATER(ah))
1630 + return;
1631 + /*
1632 + * Disable BB clock gating
1633 + * Necessary to avoid issues on AR5416 2.0
1634 + */
1635 + REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1636 +
1637 + /*
1638 + * Disable RIFS search on some chips to avoid baseband
1639 + * hang issues.
1640 + */
1641 + if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1642 + val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1643 + val &= ~AR_PHY_RIFS_INIT_DELAY;
1644 + REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1645 + }
1646 +}
1647 +
1648 +static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
1649 + struct ath9k_channel *chan)
1650 +{
1651 + u32 phymode;
1652 + u32 enableDacFifo = 0;
1653 +
1654 + if (AR_SREV_9285_10_OR_LATER(ah))
1655 + enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1656 + AR_PHY_FC_ENABLE_DAC_FIFO);
1657 +
1658 + phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1659 + | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1660 +
1661 + if (IS_CHAN_HT40(chan)) {
1662 + phymode |= AR_PHY_FC_DYN2040_EN;
1663 +
1664 + if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1665 + (chan->chanmode == CHANNEL_G_HT40PLUS))
1666 + phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1667 +
1668 + }
1669 + REG_WRITE(ah, AR_PHY_TURBO, phymode);
1670 +
1671 + ath9k_hw_set11nmac2040(ah);
1672 +
1673 + REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1674 + REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1675 +}
1676 +
1677 +
1678 +static int ar5008_hw_process_ini(struct ath_hw *ah,
1679 + struct ath9k_channel *chan)
1680 +{
1681 + struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1682 + int i, regWrites = 0;
1683 + struct ieee80211_channel *channel = chan->chan;
1684 + u32 modesIndex, freqIndex;
1685 +
1686 + switch (chan->chanmode) {
1687 + case CHANNEL_A:
1688 + case CHANNEL_A_HT20:
1689 + modesIndex = 1;
1690 + freqIndex = 1;
1691 + break;
1692 + case CHANNEL_A_HT40PLUS:
1693 + case CHANNEL_A_HT40MINUS:
1694 + modesIndex = 2;
1695 + freqIndex = 1;
1696 + break;
1697 + case CHANNEL_G:
1698 + case CHANNEL_G_HT20:
1699 + case CHANNEL_B:
1700 + modesIndex = 4;
1701 + freqIndex = 2;
1702 + break;
1703 + case CHANNEL_G_HT40PLUS:
1704 + case CHANNEL_G_HT40MINUS:
1705 + modesIndex = 3;
1706 + freqIndex = 2;
1707 + break;
1708 +
1709 + default:
1710 + return -EINVAL;
1711 + }
1712 +
1713 + if (AR_SREV_9287_12_OR_LATER(ah)) {
1714 + /* Enable ASYNC FIFO */
1715 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1716 + AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1717 + REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1718 + REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1719 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1720 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1721 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1722 + }
1723 +
1724 + /* Set correct baseband to analog shift setting to access analog chips */
1725 + REG_WRITE(ah, AR_PHY(0), 0x00000007);
1726 +
1727 + /* Write ADDAC shifts */
1728 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1729 + ah->eep_ops->set_addac(ah, chan);
1730 +
1731 + if (AR_SREV_5416_22_OR_LATER(ah)) {
1732 + REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1733 + } else {
1734 + struct ar5416IniArray temp;
1735 + u32 addacSize =
1736 + sizeof(u32) * ah->iniAddac.ia_rows *
1737 + ah->iniAddac.ia_columns;
1738 +
1739 + /* For AR5416 2.0/2.1 */
1740 + memcpy(ah->addac5416_21,
1741 + ah->iniAddac.ia_array, addacSize);
1742 +
1743 + /* override CLKDRV value at [row, column] = [31, 1] */
1744 + (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1745 +
1746 + temp.ia_array = ah->addac5416_21;
1747 + temp.ia_columns = ah->iniAddac.ia_columns;
1748 + temp.ia_rows = ah->iniAddac.ia_rows;
1749 + REG_WRITE_ARRAY(&temp, 1, regWrites);
1750 + }
1751 +
1752 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1753 +
1754 + for (i = 0; i < ah->iniModes.ia_rows; i++) {
1755 + u32 reg = INI_RA(&ah->iniModes, i, 0);
1756 + u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1757 +
1758 + if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1759 + val &= ~AR_AN_TOP2_PWDCLKIND;
1760 +
1761 + REG_WRITE(ah, reg, val);
1762 +
1763 + if (reg >= 0x7800 && reg < 0x78a0
1764 + && ah->config.analog_shiftreg) {
1765 + udelay(100);
1766 + }
1767 +
1768 + DO_DELAY(regWrites);
1769 + }
1770 +
1771 + if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1772 + REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1773 +
1774 + if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1775 + AR_SREV_9287_10_OR_LATER(ah))
1776 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1777 +
1778 + if (AR_SREV_9271_10(ah))
1779 + REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1780 + modesIndex, regWrites);
1781 +
1782 + /* Write common array parameters */
1783 + for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1784 + u32 reg = INI_RA(&ah->iniCommon, i, 0);
1785 + u32 val = INI_RA(&ah->iniCommon, i, 1);
1786 +
1787 + REG_WRITE(ah, reg, val);
1788 +
1789 + if (reg >= 0x7800 && reg < 0x78a0
1790 + && ah->config.analog_shiftreg) {
1791 + udelay(100);
1792 + }
1793 +
1794 + DO_DELAY(regWrites);
1795 + }
1796 +
1797 + if (AR_SREV_9271(ah)) {
1798 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1799 + REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1800 + modesIndex, regWrites);
1801 + else
1802 + REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1803 + modesIndex, regWrites);
1804 + }
1805 +
1806 + REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
1807 +
1808 + if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1809 + REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1810 + regWrites);
1811 + }
1812 +
1813 + ar5008_hw_override_ini(ah, chan);
1814 + ar5008_hw_set_channel_regs(ah, chan);
1815 + ar5008_hw_init_chain_masks(ah);
1816 + ath9k_olc_init(ah);
1817 +
1818 + /* Set TX power */
1819 + ah->eep_ops->set_txpower(ah, chan,
1820 + ath9k_regd_get_ctl(regulatory, chan),
1821 + channel->max_antenna_gain * 2,
1822 + channel->max_power * 2,
1823 + min((u32) MAX_RATE_POWER,
1824 + (u32) regulatory->power_limit));
1825 +
1826 + /* Write analog registers */
1827 + if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1828 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1829 + "ar5416SetRfRegs failed\n");
1830 + return -EIO;
1831 + }
1832 +
1833 + return 0;
1834 +}
1835 +
1836 +static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1837 +{
1838 + u32 rfMode = 0;
1839 +
1840 + if (chan == NULL)
1841 + return;
1842 +
1843 + rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1844 + ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1845 +
1846 + if (!AR_SREV_9280_10_OR_LATER(ah))
1847 + rfMode |= (IS_CHAN_5GHZ(chan)) ?
1848 + AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1849 +
1850 + if ((AR_SREV_9280_20(ah) || AR_SREV_9300_20_OR_LATER(ah))
1851 + && IS_CHAN_A_5MHZ_SPACED(chan))
1852 + rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1853 +
1854 + REG_WRITE(ah, AR_PHY_MODE, rfMode);
1855 +}
1856 +
1857 +static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
1858 +{
1859 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1860 +}
1861 +
1862 +static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
1863 + struct ath9k_channel *chan)
1864 +{
1865 + u32 coef_scaled, ds_coef_exp, ds_coef_man;
1866 + u32 clockMhzScaled = 0x64000000;
1867 + struct chan_centers centers;
1868 +
1869 + if (IS_CHAN_HALF_RATE(chan))
1870 + clockMhzScaled = clockMhzScaled >> 1;
1871 + else if (IS_CHAN_QUARTER_RATE(chan))
1872 + clockMhzScaled = clockMhzScaled >> 2;
1873 +
1874 + ath9k_hw_get_channel_centers(ah, chan, &centers);
1875 + coef_scaled = clockMhzScaled / centers.synth_center;
1876 +
1877 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1878 + &ds_coef_exp);
1879 +
1880 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1881 + AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1882 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1883 + AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1884 +
1885 + coef_scaled = (9 * coef_scaled) / 10;
1886 +
1887 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1888 + &ds_coef_exp);
1889 +
1890 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1891 + AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1892 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1893 + AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1894 +}
1895 +
1896 +static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
1897 +{
1898 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1899 + return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1900 + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
1901 +}
1902 +
1903 +static void ar5008_hw_rfbus_done(struct ath_hw *ah)
1904 +{
1905 + u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1906 + if (IS_CHAN_B(ah->curchan))
1907 + synthDelay = (4 * synthDelay) / 22;
1908 + else
1909 + synthDelay /= 10;
1910 +
1911 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
1912 +
1913 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1914 +}
1915 +
1916 +static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
1917 +{
1918 + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1919 + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1920 +
1921 + REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1922 + AR_GPIO_INPUT_MUX2_RFSILENT);
1923 +
1924 + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1925 + REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1926 +}
1927 +
1928 +static void ar5008_restore_chainmask(struct ath_hw *ah)
1929 +{
1930 + int rx_chainmask = ah->rxchainmask;
1931 +
1932 + if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
1933 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1934 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1935 + }
1936 +}
1937 +
1938 +static void ar5008_set_diversity(struct ath_hw *ah, bool value)
1939 +{
1940 + u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1941 + if (value)
1942 + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1943 + else
1944 + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1945 + REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1946 +}
1947 +
1948 +static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
1949 + struct ath9k_channel *chan)
1950 +{
1951 + if (chan && IS_CHAN_5GHZ(chan))
1952 + return 0x1450;
1953 + return 0x1458;
1954 +}
1955 +
1956 +static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1957 + struct ath9k_channel *chan)
1958 +{
1959 + u32 pll;
1960 +
1961 + pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1962 +
1963 + if (chan && IS_CHAN_HALF_RATE(chan))
1964 + pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1965 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
1966 + pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1967 +
1968 + if (chan && IS_CHAN_5GHZ(chan))
1969 + pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1970 + else
1971 + pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1972 +
1973 + return pll;
1974 +}
1975 +
1976 +static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1977 + struct ath9k_channel *chan)
1978 +{
1979 + u32 pll;
1980 +
1981 + pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1982 +
1983 + if (chan && IS_CHAN_HALF_RATE(chan))
1984 + pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1985 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
1986 + pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1987 +
1988 + if (chan && IS_CHAN_5GHZ(chan))
1989 + pll |= SM(0xa, AR_RTC_PLL_DIV);
1990 + else
1991 + pll |= SM(0xb, AR_RTC_PLL_DIV);
1992 +
1993 + return pll;
1994 +}
1995 +
1996 +static bool ar5008_hw_ani_control(struct ath_hw *ah,
1997 + enum ath9k_ani_cmd cmd, int param)
1998 +{
1999 + struct ar5416AniState *aniState = ah->curani;
2000 + struct ath_common *common = ath9k_hw_common(ah);
2001 +
2002 + switch (cmd & ah->ani_function) {
2003 + case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2004 + u32 level = param;
2005 +
2006 + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
2007 + ath_print(common, ATH_DBG_ANI,
2008 + "level out of range (%u > %u)\n",
2009 + level,
2010 + (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
2011 + return false;
2012 + }
2013 +
2014 + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2015 + AR_PHY_DESIRED_SZ_TOT_DES,
2016 + ah->totalSizeDesired[level]);
2017 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2018 + AR_PHY_AGC_CTL1_COARSE_LOW,
2019 + ah->coarse_low[level]);
2020 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2021 + AR_PHY_AGC_CTL1_COARSE_HIGH,
2022 + ah->coarse_high[level]);
2023 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2024 + AR_PHY_FIND_SIG_FIRPWR,
2025 + ah->firpwr[level]);
2026 +
2027 + if (level > aniState->noiseImmunityLevel)
2028 + ah->stats.ast_ani_niup++;
2029 + else if (level < aniState->noiseImmunityLevel)
2030 + ah->stats.ast_ani_nidown++;
2031 + aniState->noiseImmunityLevel = level;
2032 + break;
2033 + }
2034 + case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2035 + const int m1ThreshLow[] = { 127, 50 };
2036 + const int m2ThreshLow[] = { 127, 40 };
2037 + const int m1Thresh[] = { 127, 0x4d };
2038 + const int m2Thresh[] = { 127, 0x40 };
2039 + const int m2CountThr[] = { 31, 16 };
2040 + const int m2CountThrLow[] = { 63, 48 };
2041 + u32 on = param ? 1 : 0;
2042 +
2043 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2044 + AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2045 + m1ThreshLow[on]);
2046 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2047 + AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2048 + m2ThreshLow[on]);
2049 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2050 + AR_PHY_SFCORR_M1_THRESH,
2051 + m1Thresh[on]);
2052 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2053 + AR_PHY_SFCORR_M2_THRESH,
2054 + m2Thresh[on]);
2055 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2056 + AR_PHY_SFCORR_M2COUNT_THR,
2057 + m2CountThr[on]);
2058 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2059 + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2060 + m2CountThrLow[on]);
2061 +
2062 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2063 + AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2064 + m1ThreshLow[on]);
2065 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2066 + AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2067 + m2ThreshLow[on]);
2068 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2069 + AR_PHY_SFCORR_EXT_M1_THRESH,
2070 + m1Thresh[on]);
2071 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2072 + AR_PHY_SFCORR_EXT_M2_THRESH,
2073 + m2Thresh[on]);
2074 +
2075 + if (on)
2076 + REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2077 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2078 + else
2079 + REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2080 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2081 +
2082 + if (!on != aniState->ofdmWeakSigDetectOff) {
2083 + if (on)
2084 + ah->stats.ast_ani_ofdmon++;
2085 + else
2086 + ah->stats.ast_ani_ofdmoff++;
2087 + aniState->ofdmWeakSigDetectOff = !on;
2088 + }
2089 + break;
2090 + }
2091 + case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2092 + const int weakSigThrCck[] = { 8, 6 };
2093 + u32 high = param ? 1 : 0;
2094 +
2095 + REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2096 + AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2097 + weakSigThrCck[high]);
2098 + if (high != aniState->cckWeakSigThreshold) {
2099 + if (high)
2100 + ah->stats.ast_ani_cckhigh++;
2101 + else
2102 + ah->stats.ast_ani_ccklow++;
2103 + aniState->cckWeakSigThreshold = high;
2104 + }
2105 + break;
2106 + }
2107 + case ATH9K_ANI_FIRSTEP_LEVEL:{
2108 + const int firstep[] = { 0, 4, 8 };
2109 + u32 level = param;
2110 +
2111 + if (level >= ARRAY_SIZE(firstep)) {
2112 + ath_print(common, ATH_DBG_ANI,
2113 + "level out of range (%u > %u)\n",
2114 + level,
2115 + (unsigned) ARRAY_SIZE(firstep));
2116 + return false;
2117 + }
2118 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2119 + AR_PHY_FIND_SIG_FIRSTEP,
2120 + firstep[level]);
2121 + if (level > aniState->firstepLevel)
2122 + ah->stats.ast_ani_stepup++;
2123 + else if (level < aniState->firstepLevel)
2124 + ah->stats.ast_ani_stepdown++;
2125 + aniState->firstepLevel = level;
2126 + break;
2127 + }
2128 + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2129 + const int cycpwrThr1[] =
2130 + { 2, 4, 6, 8, 10, 12, 14, 16 };
2131 + u32 level = param;
2132 +
2133 + if (level >= ARRAY_SIZE(cycpwrThr1)) {
2134 + ath_print(common, ATH_DBG_ANI,
2135 + "level out of range (%u > %u)\n",
2136 + level,
2137 + (unsigned) ARRAY_SIZE(cycpwrThr1));
2138 + return false;
2139 + }
2140 + REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2141 + AR_PHY_TIMING5_CYCPWR_THR1,
2142 + cycpwrThr1[level]);
2143 + if (level > aniState->spurImmunityLevel)
2144 + ah->stats.ast_ani_spurup++;
2145 + else if (level < aniState->spurImmunityLevel)
2146 + ah->stats.ast_ani_spurdown++;
2147 + aniState->spurImmunityLevel = level;
2148 + break;
2149 + }
2150 + case ATH9K_ANI_PRESENT:
2151 + break;
2152 + default:
2153 + ath_print(common, ATH_DBG_ANI,
2154 + "invalid cmd %u\n", cmd);
2155 + return false;
2156 + }
2157 +
2158 + ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
2159 + ath_print(common, ATH_DBG_ANI,
2160 + "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2161 + "ofdmWeakSigDetectOff=%d\n",
2162 + aniState->noiseImmunityLevel,
2163 + aniState->spurImmunityLevel,
2164 + !aniState->ofdmWeakSigDetectOff);
2165 + ath_print(common, ATH_DBG_ANI,
2166 + "cckWeakSigThreshold=%d, "
2167 + "firstepLevel=%d, listenTime=%d\n",
2168 + aniState->cckWeakSigThreshold,
2169 + aniState->firstepLevel,
2170 + aniState->listenTime);
2171 + ath_print(common, ATH_DBG_ANI,
2172 + "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2173 + aniState->cycleCount,
2174 + aniState->ofdmPhyErrCount,
2175 + aniState->cckPhyErrCount);
2176 +
2177 + return true;
2178 +}
2179 +
2180 +static void ar5008_hw_do_getnf(struct ath_hw *ah,
2181 + int16_t nfarray[NUM_NF_READINGS])
2182 +{
2183 + struct ath_common *common = ath9k_hw_common(ah);
2184 + int16_t nf;
2185 +
2186 + nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
2187 + if (nf & 0x100)
2188 + nf = 0 - ((nf ^ 0x1ff) + 1);
2189 + ath_print(common, ATH_DBG_CALIBRATE,
2190 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
2191 + nfarray[0] = nf;
2192 +
2193 + nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
2194 + if (nf & 0x100)
2195 + nf = 0 - ((nf ^ 0x1ff) + 1);
2196 + ath_print(common, ATH_DBG_CALIBRATE,
2197 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
2198 + nfarray[1] = nf;
2199 +
2200 + nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
2201 + if (nf & 0x100)
2202 + nf = 0 - ((nf ^ 0x1ff) + 1);
2203 + ath_print(common, ATH_DBG_CALIBRATE,
2204 + "NF calibrated [ctl] [chain 2] is %d\n", nf);
2205 + nfarray[2] = nf;
2206 +
2207 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
2208 + if (nf & 0x100)
2209 + nf = 0 - ((nf ^ 0x1ff) + 1);
2210 + ath_print(common, ATH_DBG_CALIBRATE,
2211 + "NF calibrated [ext] [chain 0] is %d\n", nf);
2212 + nfarray[3] = nf;
2213 +
2214 + nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
2215 + if (nf & 0x100)
2216 + nf = 0 - ((nf ^ 0x1ff) + 1);
2217 + ath_print(common, ATH_DBG_CALIBRATE,
2218 + "NF calibrated [ext] [chain 1] is %d\n", nf);
2219 + nfarray[4] = nf;
2220 +
2221 + nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
2222 + if (nf & 0x100)
2223 + nf = 0 - ((nf ^ 0x1ff) + 1);
2224 + ath_print(common, ATH_DBG_CALIBRATE,
2225 + "NF calibrated [ext] [chain 2] is %d\n", nf);
2226 + nfarray[5] = nf;
2227 +}
2228 +
2229 +void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
2230 +{
2231 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
2232 +
2233 + priv_ops->rf_set_freq = ar5008_hw_set_channel;
2234 + priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
2235 +
2236 + priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
2237 + priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
2238 + priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
2239 + priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
2240 + priv_ops->init_bb = ar5008_hw_init_bb;
2241 + priv_ops->process_ini = ar5008_hw_process_ini;
2242 + priv_ops->set_rfmode = ar5008_hw_set_rfmode;
2243 + priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
2244 + priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
2245 + priv_ops->rfbus_req = ar5008_hw_rfbus_req;
2246 + priv_ops->rfbus_done = ar5008_hw_rfbus_done;
2247 + priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
2248 + priv_ops->restore_chainmask = ar5008_restore_chainmask;
2249 + priv_ops->set_diversity = ar5008_set_diversity;
2250 + priv_ops->ani_control = ar5008_hw_ani_control;
2251 + priv_ops->do_getnf = ar5008_hw_do_getnf;
2252 +
2253 + if (AR_SREV_9100(ah))
2254 + priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
2255 + else if (AR_SREV_9160_10_OR_LATER(ah))
2256 + priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
2257 + else
2258 + priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
2259 +}
2260 --- /dev/null
2261 +++ b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
2262 @@ -0,0 +1,1254 @@
2263 +
2264 +static const u32 ar5416Common_9100[][2] = {
2265 + { 0x0000000c, 0x00000000 },
2266 + { 0x00000030, 0x00020015 },
2267 + { 0x00000034, 0x00000005 },
2268 + { 0x00000040, 0x00000000 },
2269 + { 0x00000044, 0x00000008 },
2270 + { 0x00000048, 0x00000008 },
2271 + { 0x0000004c, 0x00000010 },
2272 + { 0x00000050, 0x00000000 },
2273 + { 0x00000054, 0x0000001f },
2274 + { 0x00000800, 0x00000000 },
2275 + { 0x00000804, 0x00000000 },
2276 + { 0x00000808, 0x00000000 },
2277 + { 0x0000080c, 0x00000000 },
2278 + { 0x00000810, 0x00000000 },
2279 + { 0x00000814, 0x00000000 },
2280 + { 0x00000818, 0x00000000 },
2281 + { 0x0000081c, 0x00000000 },
2282 + { 0x00000820, 0x00000000 },
2283 + { 0x00000824, 0x00000000 },
2284 + { 0x00001040, 0x002ffc0f },
2285 + { 0x00001044, 0x002ffc0f },
2286 + { 0x00001048, 0x002ffc0f },
2287 + { 0x0000104c, 0x002ffc0f },
2288 + { 0x00001050, 0x002ffc0f },
2289 + { 0x00001054, 0x002ffc0f },
2290 + { 0x00001058, 0x002ffc0f },
2291 + { 0x0000105c, 0x002ffc0f },
2292 + { 0x00001060, 0x002ffc0f },
2293 + { 0x00001064, 0x002ffc0f },
2294 + { 0x00001230, 0x00000000 },
2295 + { 0x00001270, 0x00000000 },
2296 + { 0x00001038, 0x00000000 },
2297 + { 0x00001078, 0x00000000 },
2298 + { 0x000010b8, 0x00000000 },
2299 + { 0x000010f8, 0x00000000 },
2300 + { 0x00001138, 0x00000000 },
2301 + { 0x00001178, 0x00000000 },
2302 + { 0x000011b8, 0x00000000 },
2303 + { 0x000011f8, 0x00000000 },
2304 + { 0x00001238, 0x00000000 },
2305 + { 0x00001278, 0x00000000 },
2306 + { 0x000012b8, 0x00000000 },
2307 + { 0x000012f8, 0x00000000 },
2308 + { 0x00001338, 0x00000000 },
2309 + { 0x00001378, 0x00000000 },
2310 + { 0x000013b8, 0x00000000 },
2311 + { 0x000013f8, 0x00000000 },
2312 + { 0x00001438, 0x00000000 },
2313 + { 0x00001478, 0x00000000 },
2314 + { 0x000014b8, 0x00000000 },
2315 + { 0x000014f8, 0x00000000 },
2316 + { 0x00001538, 0x00000000 },
2317 + { 0x00001578, 0x00000000 },
2318 + { 0x000015b8, 0x00000000 },
2319 + { 0x000015f8, 0x00000000 },
2320 + { 0x00001638, 0x00000000 },
2321 + { 0x00001678, 0x00000000 },
2322 + { 0x000016b8, 0x00000000 },
2323 + { 0x000016f8, 0x00000000 },
2324 + { 0x00001738, 0x00000000 },
2325 + { 0x00001778, 0x00000000 },
2326 + { 0x000017b8, 0x00000000 },
2327 + { 0x000017f8, 0x00000000 },
2328 + { 0x0000103c, 0x00000000 },
2329 + { 0x0000107c, 0x00000000 },
2330 + { 0x000010bc, 0x00000000 },
2331 + { 0x000010fc, 0x00000000 },
2332 + { 0x0000113c, 0x00000000 },
2333 + { 0x0000117c, 0x00000000 },
2334 + { 0x000011bc, 0x00000000 },
2335 + { 0x000011fc, 0x00000000 },
2336 + { 0x0000123c, 0x00000000 },
2337 + { 0x0000127c, 0x00000000 },
2338 + { 0x000012bc, 0x00000000 },
2339 + { 0x000012fc, 0x00000000 },
2340 + { 0x0000133c, 0x00000000 },
2341 + { 0x0000137c, 0x00000000 },
2342 + { 0x000013bc, 0x00000000 },
2343 + { 0x000013fc, 0x00000000 },
2344 + { 0x0000143c, 0x00000000 },
2345 + { 0x0000147c, 0x00000000 },
2346 + { 0x00020010, 0x00000003 },
2347 + { 0x00020038, 0x000004c2 },
2348 + { 0x00008004, 0x00000000 },
2349 + { 0x00008008, 0x00000000 },
2350 + { 0x0000800c, 0x00000000 },
2351 + { 0x00008018, 0x00000700 },
2352 + { 0x00008020, 0x00000000 },
2353 + { 0x00008038, 0x00000000 },
2354 + { 0x0000803c, 0x00000000 },
2355 + { 0x00008048, 0x40000000 },
2356 + { 0x00008054, 0x00004000 },
2357 + { 0x00008058, 0x00000000 },
2358 + { 0x0000805c, 0x000fc78f },
2359 + { 0x00008060, 0x0000000f },
2360 + { 0x00008064, 0x00000000 },
2361 + { 0x000080c0, 0x2a82301a },
2362 + { 0x000080c4, 0x05dc01e0 },
2363 + { 0x000080c8, 0x1f402710 },
2364 + { 0x000080cc, 0x01f40000 },
2365 + { 0x000080d0, 0x00001e00 },
2366 + { 0x000080d4, 0x00000000 },
2367 + { 0x000080d8, 0x00400000 },
2368 + { 0x000080e0, 0xffffffff },
2369 + { 0x000080e4, 0x0000ffff },
2370 + { 0x000080e8, 0x003f3f3f },
2371 + { 0x000080ec, 0x00000000 },
2372 + { 0x000080f0, 0x00000000 },
2373 + { 0x000080f4, 0x00000000 },
2374 + { 0x000080f8, 0x00000000 },
2375 + { 0x000080fc, 0x00020000 },
2376 + { 0x00008100, 0x00020000 },
2377 + { 0x00008104, 0x00000001 },
2378 + { 0x00008108, 0x00000052 },
2379 + { 0x0000810c, 0x00000000 },
2380 + { 0x00008110, 0x00000168 },
2381 + { 0x00008118, 0x000100aa },
2382 + { 0x0000811c, 0x00003210 },
2383 + { 0x00008120, 0x08f04800 },
2384 + { 0x00008124, 0x00000000 },
2385 + { 0x00008128, 0x00000000 },
2386 + { 0x0000812c, 0x00000000 },
2387 + { 0x00008130, 0x00000000 },
2388 + { 0x00008134, 0x00000000 },
2389 + { 0x00008138, 0x00000000 },
2390 + { 0x0000813c, 0x00000000 },
2391 + { 0x00008144, 0x00000000 },
2392 + { 0x00008168, 0x00000000 },
2393 + { 0x0000816c, 0x00000000 },
2394 + { 0x00008170, 0x32143320 },
2395 + { 0x00008174, 0xfaa4fa50 },
2396 + { 0x00008178, 0x00000100 },
2397 + { 0x0000817c, 0x00000000 },
2398 + { 0x000081c4, 0x00000000 },
2399 + { 0x000081d0, 0x00003210 },
2400 + { 0x000081ec, 0x00000000 },
2401 + { 0x000081f0, 0x00000000 },
2402 + { 0x000081f4, 0x00000000 },
2403 + { 0x000081f8, 0x00000000 },
2404 + { 0x000081fc, 0x00000000 },
2405 + { 0x00008200, 0x00000000 },
2406 + { 0x00008204, 0x00000000 },
2407 + { 0x00008208, 0x00000000 },
2408 + { 0x0000820c, 0x00000000 },
2409 + { 0x00008210, 0x00000000 },
2410 + { 0x00008214, 0x00000000 },
2411 + { 0x00008218, 0x00000000 },
2412 + { 0x0000821c, 0x00000000 },
2413 + { 0x00008220, 0x00000000 },
2414 + { 0x00008224, 0x00000000 },
2415 + { 0x00008228, 0x00000000 },
2416 + { 0x0000822c, 0x00000000 },
2417 + { 0x00008230, 0x00000000 },
2418 + { 0x00008234, 0x00000000 },
2419 + { 0x00008238, 0x00000000 },
2420 + { 0x0000823c, 0x00000000 },
2421 + { 0x00008240, 0x00100000 },
2422 + { 0x00008244, 0x0010f400 },
2423 + { 0x00008248, 0x00000100 },
2424 + { 0x0000824c, 0x0001e800 },
2425 + { 0x00008250, 0x00000000 },
2426 + { 0x00008254, 0x00000000 },
2427 + { 0x00008258, 0x00000000 },
2428 + { 0x0000825c, 0x400000ff },
2429 + { 0x00008260, 0x00080922 },
2430 + { 0x00008270, 0x00000000 },
2431 + { 0x00008274, 0x40000000 },
2432 + { 0x00008278, 0x003e4180 },
2433 + { 0x0000827c, 0x00000000 },
2434 + { 0x00008284, 0x0000002c },
2435 + { 0x00008288, 0x0000002c },
2436 + { 0x0000828c, 0x00000000 },
2437 + { 0x00008294, 0x00000000 },
2438 + { 0x00008298, 0x00000000 },
2439 + { 0x00008300, 0x00000000 },
2440 + { 0x00008304, 0x00000000 },
2441 + { 0x00008308, 0x00000000 },
2442 + { 0x0000830c, 0x00000000 },
2443 + { 0x00008310, 0x00000000 },
2444 + { 0x00008314, 0x00000000 },
2445 + { 0x00008318, 0x00000000 },
2446 + { 0x00008328, 0x00000000 },
2447 + { 0x0000832c, 0x00000007 },
2448 + { 0x00008330, 0x00000302 },
2449 + { 0x00008334, 0x00000e00 },
2450 + { 0x00008338, 0x00000000 },
2451 + { 0x0000833c, 0x00000000 },
2452 + { 0x00008340, 0x000107ff },
2453 + { 0x00009808, 0x00000000 },
2454 + { 0x0000980c, 0xad848e19 },
2455 + { 0x00009810, 0x7d14e000 },
2456 + { 0x00009814, 0x9c0a9f6b },
2457 + { 0x0000981c, 0x00000000 },
2458 + { 0x0000982c, 0x0000a000 },
2459 + { 0x00009830, 0x00000000 },
2460 + { 0x0000983c, 0x00200400 },
2461 + { 0x00009840, 0x206a01ae },
2462 + { 0x0000984c, 0x1284233c },
2463 + { 0x00009854, 0x00000859 },
2464 + { 0x00009900, 0x00000000 },
2465 + { 0x00009904, 0x00000000 },
2466 + { 0x00009908, 0x00000000 },
2467 + { 0x0000990c, 0x00000000 },
2468 + { 0x0000991c, 0x10000fff },
2469 + { 0x00009920, 0x05100000 },
2470 + { 0x0000a920, 0x05100000 },
2471 + { 0x0000b920, 0x05100000 },
2472 + { 0x00009928, 0x00000001 },
2473 + { 0x0000992c, 0x00000004 },
2474 + { 0x00009934, 0x1e1f2022 },
2475 + { 0x00009938, 0x0a0b0c0d },
2476 + { 0x0000993c, 0x00000000 },
2477 + { 0x00009948, 0x9280b212 },
2478 + { 0x0000994c, 0x00020028 },
2479 + { 0x0000c95c, 0x004b6a8e },
2480 + { 0x0000c968, 0x000003ce },
2481 + { 0x00009970, 0x190fb515 },
2482 + { 0x00009974, 0x00000000 },
2483 + { 0x00009978, 0x00000001 },
2484 + { 0x0000997c, 0x00000000 },
2485 + { 0x00009980, 0x00000000 },
2486 + { 0x00009984, 0x00000000 },
2487 + { 0x00009988, 0x00000000 },
2488 + { 0x0000998c, 0x00000000 },
2489 + { 0x00009990, 0x00000000 },
2490 + { 0x00009994, 0x00000000 },
2491 + { 0x00009998, 0x00000000 },
2492 + { 0x0000999c, 0x00000000 },
2493 + { 0x000099a0, 0x00000000 },
2494 + { 0x000099a4, 0x00000001 },
2495 + { 0x000099a8, 0x201fff00 },
2496 + { 0x000099ac, 0x006f0000 },
2497 + { 0x000099b0, 0x03051000 },
2498 + { 0x000099dc, 0x00000000 },
2499 + { 0x000099e0, 0x00000200 },
2500 + { 0x000099e4, 0xaaaaaaaa },
2501 + { 0x000099e8, 0x3c466478 },
2502 + { 0x000099ec, 0x0cc80caa },
2503 + { 0x000099fc, 0x00001042 },
2504 + { 0x00009b00, 0x00000000 },
2505 + { 0x00009b04, 0x00000001 },
2506 + { 0x00009b08, 0x00000002 },
2507 + { 0x00009b0c, 0x00000003 },
2508 + { 0x00009b10, 0x00000004 },
2509 + { 0x00009b14, 0x00000005 },
2510 + { 0x00009b18, 0x00000008 },
2511 + { 0x00009b1c, 0x00000009 },
2512 + { 0x00009b20, 0x0000000a },
2513 + { 0x00009b24, 0x0000000b },
2514 + { 0x00009b28, 0x0000000c },
2515 + { 0x00009b2c, 0x0000000d },
2516 + { 0x00009b30, 0x00000010 },
2517 + { 0x00009b34, 0x00000011 },
2518 + { 0x00009b38, 0x00000012 },
2519 + { 0x00009b3c, 0x00000013 },
2520 + { 0x00009b40, 0x00000014 },
2521 + { 0x00009b44, 0x00000015 },
2522 + { 0x00009b48, 0x00000018 },
2523 + { 0x00009b4c, 0x00000019 },
2524 + { 0x00009b50, 0x0000001a },
2525 + { 0x00009b54, 0x0000001b },
2526 + { 0x00009b58, 0x0000001c },
2527 + { 0x00009b5c, 0x0000001d },
2528 + { 0x00009b60, 0x00000020 },
2529 + { 0x00009b64, 0x00000021 },
2530 + { 0x00009b68, 0x00000022 },
2531 + { 0x00009b6c, 0x00000023 },
2532 + { 0x00009b70, 0x00000024 },
2533 + { 0x00009b74, 0x00000025 },
2534 + { 0x00009b78, 0x00000028 },
2535 + { 0x00009b7c, 0x00000029 },
2536 + { 0x00009b80, 0x0000002a },
2537 + { 0x00009b84, 0x0000002b },
2538 + { 0x00009b88, 0x0000002c },
2539 + { 0x00009b8c, 0x0000002d },
2540 + { 0x00009b90, 0x00000030 },
2541 + { 0x00009b94, 0x00000031 },
2542 + { 0x00009b98, 0x00000032 },
2543 + { 0x00009b9c, 0x00000033 },
2544 + { 0x00009ba0, 0x00000034 },
2545 + { 0x00009ba4, 0x00000035 },
2546 + { 0x00009ba8, 0x00000035 },
2547 + { 0x00009bac, 0x00000035 },
2548 + { 0x00009bb0, 0x00000035 },
2549 + { 0x00009bb4, 0x00000035 },
2550 + { 0x00009bb8, 0x00000035 },
2551 + { 0x00009bbc, 0x00000035 },
2552 + { 0x00009bc0, 0x00000035 },
2553 + { 0x00009bc4, 0x00000035 },
2554 + { 0x00009bc8, 0x00000035 },
2555 + { 0x00009bcc, 0x00000035 },
2556 + { 0x00009bd0, 0x00000035 },
2557 + { 0x00009bd4, 0x00000035 },
2558 + { 0x00009bd8, 0x00000035 },
2559 + { 0x00009bdc, 0x00000035 },
2560 + { 0x00009be0, 0x00000035 },
2561 + { 0x00009be4, 0x00000035 },
2562 + { 0x00009be8, 0x00000035 },
2563 + { 0x00009bec, 0x00000035 },
2564 + { 0x00009bf0, 0x00000035 },
2565 + { 0x00009bf4, 0x00000035 },
2566 + { 0x00009bf8, 0x00000010 },
2567 + { 0x00009bfc, 0x0000001a },
2568 + { 0x0000a210, 0x40806333 },
2569 + { 0x0000a214, 0x00106c10 },
2570 + { 0x0000a218, 0x009c4060 },
2571 + { 0x0000a220, 0x018830c6 },
2572 + { 0x0000a224, 0x00000400 },
2573 + { 0x0000a228, 0x001a0bb5 },
2574 + { 0x0000a22c, 0x00000000 },
2575 + { 0x0000a234, 0x20202020 },
2576 + { 0x0000a238, 0x20202020 },
2577 + { 0x0000a23c, 0x13c889ae },
2578 + { 0x0000a240, 0x38490a20 },
2579 + { 0x0000a244, 0x00007bb6 },
2580 + { 0x0000a248, 0x0fff3ffc },
2581 + { 0x0000a24c, 0x00000001 },
2582 + { 0x0000a250, 0x0000a000 },
2583 + { 0x0000a254, 0x00000000 },
2584 + { 0x0000a258, 0x0cc75380 },
2585 + { 0x0000a25c, 0x0f0f0f01 },
2586 + { 0x0000a260, 0xdfa91f01 },
2587 + { 0x0000a268, 0x00000001 },
2588 + { 0x0000a26c, 0x0ebae9c6 },
2589 + { 0x0000b26c, 0x0ebae9c6 },
2590 + { 0x0000c26c, 0x0ebae9c6 },
2591 + { 0x0000d270, 0x00820820 },
2592 + { 0x0000a278, 0x1ce739ce },
2593 + { 0x0000a27c, 0x050701ce },
2594 + { 0x0000a338, 0x00000000 },
2595 + { 0x0000a33c, 0x00000000 },
2596 + { 0x0000a340, 0x00000000 },
2597 + { 0x0000a344, 0x00000000 },
2598 + { 0x0000a348, 0x3fffffff },
2599 + { 0x0000a34c, 0x3fffffff },
2600 + { 0x0000a350, 0x3fffffff },
2601 + { 0x0000a354, 0x0003ffff },
2602 + { 0x0000a358, 0x79a8aa33 },
2603 + { 0x0000d35c, 0x07ffffef },
2604 + { 0x0000d360, 0x0fffffe7 },
2605 + { 0x0000d364, 0x17ffffe5 },
2606 + { 0x0000d368, 0x1fffffe4 },
2607 + { 0x0000d36c, 0x37ffffe3 },
2608 + { 0x0000d370, 0x3fffffe3 },
2609 + { 0x0000d374, 0x57ffffe3 },
2610 + { 0x0000d378, 0x5fffffe2 },
2611 + { 0x0000d37c, 0x7fffffe2 },
2612 + { 0x0000d380, 0x7f3c7bba },
2613 + { 0x0000d384, 0xf3307ff0 },
2614 + { 0x0000a388, 0x0c000000 },
2615 + { 0x0000a38c, 0x20202020 },
2616 + { 0x0000a390, 0x20202020 },
2617 + { 0x0000a394, 0x1ce739ce },
2618 + { 0x0000a398, 0x000001ce },
2619 + { 0x0000a39c, 0x00000001 },
2620 + { 0x0000a3a0, 0x00000000 },
2621 + { 0x0000a3a4, 0x00000000 },
2622 + { 0x0000a3a8, 0x00000000 },
2623 + { 0x0000a3ac, 0x00000000 },
2624 + { 0x0000a3b0, 0x00000000 },
2625 + { 0x0000a3b4, 0x00000000 },
2626 + { 0x0000a3b8, 0x00000000 },
2627 + { 0x0000a3bc, 0x00000000 },
2628 + { 0x0000a3c0, 0x00000000 },
2629 + { 0x0000a3c4, 0x00000000 },
2630 + { 0x0000a3c8, 0x00000246 },
2631 + { 0x0000a3cc, 0x20202020 },
2632 + { 0x0000a3d0, 0x20202020 },
2633 + { 0x0000a3d4, 0x20202020 },
2634 + { 0x0000a3dc, 0x1ce739ce },
2635 + { 0x0000a3e0, 0x000001ce },
2636 +};
2637 +
2638 +static const u32 ar5416Bank0_9100[][2] = {
2639 + { 0x000098b0, 0x1e5795e5 },
2640 + { 0x000098e0, 0x02008020 },
2641 +};
2642 +
2643 +static const u32 ar5416BB_RfGain_9100[][3] = {
2644 + { 0x00009a00, 0x00000000, 0x00000000 },
2645 + { 0x00009a04, 0x00000040, 0x00000040 },
2646 + { 0x00009a08, 0x00000080, 0x00000080 },
2647 + { 0x00009a0c, 0x000001a1, 0x00000141 },
2648 + { 0x00009a10, 0x000001e1, 0x00000181 },
2649 + { 0x00009a14, 0x00000021, 0x000001c1 },
2650 + { 0x00009a18, 0x00000061, 0x00000001 },
2651 + { 0x00009a1c, 0x00000168, 0x00000041 },
2652 + { 0x00009a20, 0x000001a8, 0x000001a8 },
2653 + { 0x00009a24, 0x000001e8, 0x000001e8 },
2654 + { 0x00009a28, 0x00000028, 0x00000028 },
2655 + { 0x00009a2c, 0x00000068, 0x00000068 },
2656 + { 0x00009a30, 0x00000189, 0x000000a8 },
2657 + { 0x00009a34, 0x000001c9, 0x00000169 },
2658 + { 0x00009a38, 0x00000009, 0x000001a9 },
2659 + { 0x00009a3c, 0x00000049, 0x000001e9 },
2660 + { 0x00009a40, 0x00000089, 0x00000029 },
2661 + { 0x00009a44, 0x00000170, 0x00000069 },
2662 + { 0x00009a48, 0x000001b0, 0x00000190 },
2663 + { 0x00009a4c, 0x000001f0, 0x000001d0 },
2664 + { 0x00009a50, 0x00000030, 0x00000010 },
2665 + { 0x00009a54, 0x00000070, 0x00000050 },
2666 + { 0x00009a58, 0x00000191, 0x00000090 },
2667 + { 0x00009a5c, 0x000001d1, 0x00000151 },
2668 + { 0x00009a60, 0x00000011, 0x00000191 },
2669 + { 0x00009a64, 0x00000051, 0x000001d1 },
2670 + { 0x00009a68, 0x00000091, 0x00000011 },
2671 + { 0x00009a6c, 0x000001b8, 0x00000051 },
2672 + { 0x00009a70, 0x000001f8, 0x00000198 },
2673 + { 0x00009a74, 0x00000038, 0x000001d8 },
2674 + { 0x00009a78, 0x00000078, 0x00000018 },
2675 + { 0x00009a7c, 0x00000199, 0x00000058 },
2676 + { 0x00009a80, 0x000001d9, 0x00000098 },
2677 + { 0x00009a84, 0x00000019, 0x00000159 },
2678 + { 0x00009a88, 0x00000059, 0x00000199 },
2679 + { 0x00009a8c, 0x00000099, 0x000001d9 },
2680 + { 0x00009a90, 0x000000d9, 0x00000019 },
2681 + { 0x00009a94, 0x000000f9, 0x00000059 },
2682 + { 0x00009a98, 0x000000f9, 0x00000099 },
2683 + { 0x00009a9c, 0x000000f9, 0x000000d9 },
2684 + { 0x00009aa0, 0x000000f9, 0x000000f9 },
2685 + { 0x00009aa4, 0x000000f9, 0x000000f9 },
2686 + { 0x00009aa8, 0x000000f9, 0x000000f9 },
2687 + { 0x00009aac, 0x000000f9, 0x000000f9 },
2688 + { 0x00009ab0, 0x000000f9, 0x000000f9 },
2689 + { 0x00009ab4, 0x000000f9, 0x000000f9 },
2690 + { 0x00009ab8, 0x000000f9, 0x000000f9 },
2691 + { 0x00009abc, 0x000000f9, 0x000000f9 },
2692 + { 0x00009ac0, 0x000000f9, 0x000000f9 },
2693 + { 0x00009ac4, 0x000000f9, 0x000000f9 },
2694 + { 0x00009ac8, 0x000000f9, 0x000000f9 },
2695 + { 0x00009acc, 0x000000f9, 0x000000f9 },
2696 + { 0x00009ad0, 0x000000f9, 0x000000f9 },
2697 + { 0x00009ad4, 0x000000f9, 0x000000f9 },
2698 + { 0x00009ad8, 0x000000f9, 0x000000f9 },
2699 + { 0x00009adc, 0x000000f9, 0x000000f9 },
2700 + { 0x00009ae0, 0x000000f9, 0x000000f9 },
2701 + { 0x00009ae4, 0x000000f9, 0x000000f9 },
2702 + { 0x00009ae8, 0x000000f9, 0x000000f9 },
2703 + { 0x00009aec, 0x000000f9, 0x000000f9 },
2704 + { 0x00009af0, 0x000000f9, 0x000000f9 },
2705 + { 0x00009af4, 0x000000f9, 0x000000f9 },
2706 + { 0x00009af8, 0x000000f9, 0x000000f9 },
2707 + { 0x00009afc, 0x000000f9, 0x000000f9 },
2708 +};
2709 +
2710 +static const u32 ar5416Bank1_9100[][2] = {
2711 + { 0x000098b0, 0x02108421},
2712 + { 0x000098ec, 0x00000008},
2713 +};
2714 +
2715 +static const u32 ar5416Bank2_9100[][2] = {
2716 + { 0x000098b0, 0x0e73ff17},
2717 + { 0x000098e0, 0x00000420},
2718 +};
2719 +
2720 +static const u32 ar5416Bank3_9100[][3] = {
2721 + { 0x000098f0, 0x01400018, 0x01c00018 },
2722 +};
2723 +
2724 +static const u32 ar5416Bank6_9100[][3] = {
2725 +
2726 + { 0x0000989c, 0x00000000, 0x00000000 },
2727 + { 0x0000989c, 0x00000000, 0x00000000 },
2728 + { 0x0000989c, 0x00000000, 0x00000000 },
2729 + { 0x0000989c, 0x00e00000, 0x00e00000 },
2730 + { 0x0000989c, 0x005e0000, 0x005e0000 },
2731 + { 0x0000989c, 0x00120000, 0x00120000 },
2732 + { 0x0000989c, 0x00620000, 0x00620000 },
2733 + { 0x0000989c, 0x00020000, 0x00020000 },
2734 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2735 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2736 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2737 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2738 + { 0x0000989c, 0x005f0000, 0x005f0000 },
2739 + { 0x0000989c, 0x00870000, 0x00870000 },
2740 + { 0x0000989c, 0x00f90000, 0x00f90000 },
2741 + { 0x0000989c, 0x007b0000, 0x007b0000 },
2742 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2743 + { 0x0000989c, 0x00f50000, 0x00f50000 },
2744 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
2745 + { 0x0000989c, 0x00110000, 0x00110000 },
2746 + { 0x0000989c, 0x006100a8, 0x006100a8 },
2747 + { 0x0000989c, 0x004210a2, 0x004210a2 },
2748 + { 0x0000989c, 0x0014000f, 0x0014000f },
2749 + { 0x0000989c, 0x00c40002, 0x00c40002 },
2750 + { 0x0000989c, 0x003000f2, 0x003000f2 },
2751 + { 0x0000989c, 0x00440016, 0x00440016 },
2752 + { 0x0000989c, 0x00410040, 0x00410040 },
2753 + { 0x0000989c, 0x000180d6, 0x000180d6 },
2754 + { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
2755 + { 0x0000989c, 0x000000b1, 0x000000b1 },
2756 + { 0x0000989c, 0x00002000, 0x00002000 },
2757 + { 0x0000989c, 0x000000d4, 0x000000d4 },
2758 + { 0x000098d0, 0x0000000f, 0x0010000f },
2759 +};
2760 +
2761 +
2762 +static const u32 ar5416Bank6TPC_9100[][3] = {
2763 +
2764 + { 0x0000989c, 0x00000000, 0x00000000 },
2765 + { 0x0000989c, 0x00000000, 0x00000000 },
2766 + { 0x0000989c, 0x00000000, 0x00000000 },
2767 + { 0x0000989c, 0x00e00000, 0x00e00000 },
2768 + { 0x0000989c, 0x005e0000, 0x005e0000 },
2769 + { 0x0000989c, 0x00120000, 0x00120000 },
2770 + { 0x0000989c, 0x00620000, 0x00620000 },
2771 + { 0x0000989c, 0x00020000, 0x00020000 },
2772 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2773 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2774 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2775 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
2776 + { 0x0000989c, 0x005f0000, 0x005f0000 },
2777 + { 0x0000989c, 0x00870000, 0x00870000 },
2778 + { 0x0000989c, 0x00f90000, 0x00f90000 },
2779 + { 0x0000989c, 0x007b0000, 0x007b0000 },
2780 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2781 + { 0x0000989c, 0x00f50000, 0x00f50000 },
2782 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
2783 + { 0x0000989c, 0x00110000, 0x00110000 },
2784 + { 0x0000989c, 0x006100a8, 0x006100a8 },
2785 + { 0x0000989c, 0x00423022, 0x00423022 },
2786 + { 0x0000989c, 0x2014008f, 0x2014008f },
2787 + { 0x0000989c, 0x00c40002, 0x00c40002 },
2788 + { 0x0000989c, 0x003000f2, 0x003000f2 },
2789 + { 0x0000989c, 0x00440016, 0x00440016 },
2790 + { 0x0000989c, 0x00410040, 0x00410040 },
2791 + { 0x0000989c, 0x0001805e, 0x0001805e },
2792 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
2793 + { 0x0000989c, 0x000000e1, 0x000000e1 },
2794 + { 0x0000989c, 0x00007080, 0x00007080 },
2795 + { 0x0000989c, 0x000000d4, 0x000000d4 },
2796 + { 0x000098d0, 0x0000000f, 0x0010000f },
2797 +};
2798 +
2799 +static const u32 ar5416Bank7_9100[][2] = {
2800 + { 0x0000989c, 0x00000500 },
2801 + { 0x0000989c, 0x00000800 },
2802 + { 0x000098cc, 0x0000000e },
2803 +};
2804 +
2805 +static const u32 ar5416Addac_9100[][2] = {
2806 + {0x0000989c, 0x00000000 },
2807 + {0x0000989c, 0x00000000 },
2808 + {0x0000989c, 0x00000000 },
2809 + {0x0000989c, 0x00000000 },
2810 + {0x0000989c, 0x00000000 },
2811 + {0x0000989c, 0x00000000 },
2812 + {0x0000989c, 0x00000000 },
2813 + {0x0000989c, 0x00000010 },
2814 + {0x0000989c, 0x00000000 },
2815 + {0x0000989c, 0x00000000 },
2816 + {0x0000989c, 0x00000000 },
2817 + {0x0000989c, 0x00000000 },
2818 + {0x0000989c, 0x00000000 },
2819 + {0x0000989c, 0x00000000 },
2820 + {0x0000989c, 0x00000000 },
2821 + {0x0000989c, 0x00000000 },
2822 + {0x0000989c, 0x00000000 },
2823 + {0x0000989c, 0x00000000 },
2824 + {0x0000989c, 0x00000000 },
2825 + {0x0000989c, 0x00000000 },
2826 + {0x0000989c, 0x00000000 },
2827 + {0x0000989c, 0x000000c0 },
2828 + {0x0000989c, 0x00000015 },
2829 + {0x0000989c, 0x00000000 },
2830 + {0x0000989c, 0x00000000 },
2831 + {0x0000989c, 0x00000000 },
2832 + {0x0000989c, 0x00000000 },
2833 + {0x0000989c, 0x00000000 },
2834 + {0x0000989c, 0x00000000 },
2835 + {0x0000989c, 0x00000000 },
2836 + {0x0000989c, 0x00000000 },
2837 + {0x000098cc, 0x00000000 },
2838 +};
2839 +
2840 +static const u32 ar5416Modes_9160[][6] = {
2841 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
2842 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
2843 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
2844 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
2845 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
2846 + { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
2847 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
2848 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
2849 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
2850 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
2851 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
2852 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
2853 + { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
2854 + { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
2855 + { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
2856 + { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
2857 + { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
2858 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
2859 + { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e },
2860 + { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
2861 + { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
2862 + { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
2863 + { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
2864 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
2865 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
2866 + { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
2867 + { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
2868 + { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
2869 + { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
2870 + { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
2871 + { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
2872 + { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
2873 + { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
2874 + { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
2875 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
2876 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
2877 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
2878 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
2879 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2880 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2881 + { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
2882 + { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
2883 + { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
2884 + { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
2885 + { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
2886 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
2887 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
2888 + { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
2889 + { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
2890 + { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
2891 + { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
2892 + { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
2893 + { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
2894 + { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
2895 + { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
2896 + { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
2897 + { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
2898 + { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
2899 + { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
2900 + { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2901 + { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2902 + { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2903 +};
2904 +
2905 +static const u32 ar5416Common_9160[][2] = {
2906 + { 0x0000000c, 0x00000000 },
2907 + { 0x00000030, 0x00020015 },
2908 + { 0x00000034, 0x00000005 },
2909 + { 0x00000040, 0x00000000 },
2910 + { 0x00000044, 0x00000008 },
2911 + { 0x00000048, 0x00000008 },
2912 + { 0x0000004c, 0x00000010 },
2913 + { 0x00000050, 0x00000000 },
2914 + { 0x00000054, 0x0000001f },
2915 + { 0x00000800, 0x00000000 },
2916 + { 0x00000804, 0x00000000 },
2917 + { 0x00000808, 0x00000000 },
2918 + { 0x0000080c, 0x00000000 },
2919 + { 0x00000810, 0x00000000 },
2920 + { 0x00000814, 0x00000000 },
2921 + { 0x00000818, 0x00000000 },
2922 + { 0x0000081c, 0x00000000 },
2923 + { 0x00000820, 0x00000000 },
2924 + { 0x00000824, 0x00000000 },
2925 + { 0x00001040, 0x002ffc0f },
2926 + { 0x00001044, 0x002ffc0f },
2927 + { 0x00001048, 0x002ffc0f },
2928 + { 0x0000104c, 0x002ffc0f },
2929 + { 0x00001050, 0x002ffc0f },
2930 + { 0x00001054, 0x002ffc0f },
2931 + { 0x00001058, 0x002ffc0f },
2932 + { 0x0000105c, 0x002ffc0f },
2933 + { 0x00001060, 0x002ffc0f },
2934 + { 0x00001064, 0x002ffc0f },
2935 + { 0x00001230, 0x00000000 },
2936 + { 0x00001270, 0x00000000 },
2937 + { 0x00001038, 0x00000000 },
2938 + { 0x00001078, 0x00000000 },
2939 + { 0x000010b8, 0x00000000 },
2940 + { 0x000010f8, 0x00000000 },
2941 + { 0x00001138, 0x00000000 },
2942 + { 0x00001178, 0x00000000 },
2943 + { 0x000011b8, 0x00000000 },
2944 + { 0x000011f8, 0x00000000 },
2945 + { 0x00001238, 0x00000000 },
2946 + { 0x00001278, 0x00000000 },
2947 + { 0x000012b8, 0x00000000 },
2948 + { 0x000012f8, 0x00000000 },
2949 + { 0x00001338, 0x00000000 },
2950 + { 0x00001378, 0x00000000 },
2951 + { 0x000013b8, 0x00000000 },
2952 + { 0x000013f8, 0x00000000 },
2953 + { 0x00001438, 0x00000000 },
2954 + { 0x00001478, 0x00000000 },
2955 + { 0x000014b8, 0x00000000 },
2956 + { 0x000014f8, 0x00000000 },
2957 + { 0x00001538, 0x00000000 },
2958 + { 0x00001578, 0x00000000 },
2959 + { 0x000015b8, 0x00000000 },
2960 + { 0x000015f8, 0x00000000 },
2961 + { 0x00001638, 0x00000000 },
2962 + { 0x00001678, 0x00000000 },
2963 + { 0x000016b8, 0x00000000 },
2964 + { 0x000016f8, 0x00000000 },
2965 + { 0x00001738, 0x00000000 },
2966 + { 0x00001778, 0x00000000 },
2967 + { 0x000017b8, 0x00000000 },
2968 + { 0x000017f8, 0x00000000 },
2969 + { 0x0000103c, 0x00000000 },
2970 + { 0x0000107c, 0x00000000 },
2971 + { 0x000010bc, 0x00000000 },
2972 + { 0x000010fc, 0x00000000 },
2973 + { 0x0000113c, 0x00000000 },
2974 + { 0x0000117c, 0x00000000 },
2975 + { 0x000011bc, 0x00000000 },
2976 + { 0x000011fc, 0x00000000 },
2977 + { 0x0000123c, 0x00000000 },
2978 + { 0x0000127c, 0x00000000 },
2979 + { 0x000012bc, 0x00000000 },
2980 + { 0x000012fc, 0x00000000 },
2981 + { 0x0000133c, 0x00000000 },
2982 + { 0x0000137c, 0x00000000 },
2983 + { 0x000013bc, 0x00000000 },
2984 + { 0x000013fc, 0x00000000 },
2985 + { 0x0000143c, 0x00000000 },
2986 + { 0x0000147c, 0x00000000 },
2987 + { 0x00004030, 0x00000002 },
2988 + { 0x0000403c, 0x00000002 },
2989 + { 0x00007010, 0x00000020 },
2990 + { 0x00007038, 0x000004c2 },
2991 + { 0x00008004, 0x00000000 },
2992 + { 0x00008008, 0x00000000 },
2993 + { 0x0000800c, 0x00000000 },
2994 + { 0x00008018, 0x00000700 },
2995 + { 0x00008020, 0x00000000 },
2996 + { 0x00008038, 0x00000000 },
2997 + { 0x0000803c, 0x00000000 },
2998 + { 0x00008048, 0x40000000 },
2999 + { 0x00008054, 0x00000000 },
3000 + { 0x00008058, 0x00000000 },
3001 + { 0x0000805c, 0x000fc78f },
3002 + { 0x00008060, 0x0000000f },
3003 + { 0x00008064, 0x00000000 },
3004 + { 0x000080c0, 0x2a82301a },
3005 + { 0x000080c4, 0x05dc01e0 },
3006 + { 0x000080c8, 0x1f402710 },
3007 + { 0x000080cc, 0x01f40000 },
3008 + { 0x000080d0, 0x00001e00 },
3009 + { 0x000080d4, 0x00000000 },
3010 + { 0x000080d8, 0x00400000 },
3011 + { 0x000080e0, 0xffffffff },
3012 + { 0x000080e4, 0x0000ffff },
3013 + { 0x000080e8, 0x003f3f3f },
3014 + { 0x000080ec, 0x00000000 },
3015 + { 0x000080f0, 0x00000000 },
3016 + { 0x000080f4, 0x00000000 },
3017 + { 0x000080f8, 0x00000000 },
3018 + { 0x000080fc, 0x00020000 },
3019 + { 0x00008100, 0x00020000 },
3020 + { 0x00008104, 0x00000001 },
3021 + { 0x00008108, 0x00000052 },
3022 + { 0x0000810c, 0x00000000 },
3023 + { 0x00008110, 0x00000168 },
3024 + { 0x00008118, 0x000100aa },
3025 + { 0x0000811c, 0x00003210 },
3026 + { 0x00008120, 0x08f04800 },
3027 + { 0x00008124, 0x00000000 },
3028 + { 0x00008128, 0x00000000 },
3029 + { 0x0000812c, 0x00000000 },
3030 + { 0x00008130, 0x00000000 },
3031 + { 0x00008134, 0x00000000 },
3032 + { 0x00008138, 0x00000000 },
3033 + { 0x0000813c, 0x00000000 },
3034 + { 0x00008144, 0xffffffff },
3035 + { 0x00008168, 0x00000000 },
3036 + { 0x0000816c, 0x00000000 },
3037 + { 0x00008170, 0x32143320 },
3038 + { 0x00008174, 0xfaa4fa50 },
3039 + { 0x00008178, 0x00000100 },
3040 + { 0x0000817c, 0x00000000 },
3041 + { 0x000081c4, 0x00000000 },
3042 + { 0x000081d0, 0x00003210 },
3043 + { 0x000081ec, 0x00000000 },
3044 + { 0x000081f0, 0x00000000 },
3045 + { 0x000081f4, 0x00000000 },
3046 + { 0x000081f8, 0x00000000 },
3047 + { 0x000081fc, 0x00000000 },
3048 + { 0x00008200, 0x00000000 },
3049 + { 0x00008204, 0x00000000 },
3050 + { 0x00008208, 0x00000000 },
3051 + { 0x0000820c, 0x00000000 },
3052 + { 0x00008210, 0x00000000 },
3053 + { 0x00008214, 0x00000000 },
3054 + { 0x00008218, 0x00000000 },
3055 + { 0x0000821c, 0x00000000 },
3056 + { 0x00008220, 0x00000000 },
3057 + { 0x00008224, 0x00000000 },
3058 + { 0x00008228, 0x00000000 },
3059 + { 0x0000822c, 0x00000000 },
3060 + { 0x00008230, 0x00000000 },
3061 + { 0x00008234, 0x00000000 },
3062 + { 0x00008238, 0x00000000 },
3063 + { 0x0000823c, 0x00000000 },
3064 + { 0x00008240, 0x00100000 },
3065 + { 0x00008244, 0x0010f400 },
3066 + { 0x00008248, 0x00000100 },
3067 + { 0x0000824c, 0x0001e800 },
3068 + { 0x00008250, 0x00000000 },
3069 + { 0x00008254, 0x00000000 },
3070 + { 0x00008258, 0x00000000 },
3071 + { 0x0000825c, 0x400000ff },
3072 + { 0x00008260, 0x00080922 },
3073 + { 0x00008270, 0x00000000 },
3074 + { 0x00008274, 0x40000000 },
3075 + { 0x00008278, 0x003e4180 },
3076 + { 0x0000827c, 0x00000000 },
3077 + { 0x00008284, 0x0000002c },
3078 + { 0x00008288, 0x0000002c },
3079 + { 0x0000828c, 0x00000000 },
3080 + { 0x00008294, 0x00000000 },
3081 + { 0x00008298, 0x00000000 },
3082 + { 0x00008300, 0x00000000 },
3083 + { 0x00008304, 0x00000000 },
3084 + { 0x00008308, 0x00000000 },
3085 + { 0x0000830c, 0x00000000 },
3086 + { 0x00008310, 0x00000000 },
3087 + { 0x00008314, 0x00000000 },
3088 + { 0x00008318, 0x00000000 },
3089 + { 0x00008328, 0x00000000 },
3090 + { 0x0000832c, 0x00000007 },
3091 + { 0x00008330, 0x00000302 },
3092 + { 0x00008334, 0x00000e00 },
3093 + { 0x00008338, 0x00ff0000 },
3094 + { 0x0000833c, 0x00000000 },
3095 + { 0x00008340, 0x000107ff },
3096 + { 0x00009808, 0x00000000 },
3097 + { 0x0000980c, 0xad848e19 },
3098 + { 0x00009810, 0x7d14e000 },
3099 + { 0x00009814, 0x9c0a9f6b },
3100 + { 0x0000981c, 0x00000000 },
3101 + { 0x0000982c, 0x0000a000 },
3102 + { 0x00009830, 0x00000000 },
3103 + { 0x0000983c, 0x00200400 },
3104 + { 0x00009840, 0x206a01ae },
3105 + { 0x0000984c, 0x1284233c },
3106 + { 0x00009854, 0x00000859 },
3107 + { 0x00009900, 0x00000000 },
3108 + { 0x00009904, 0x00000000 },
3109 + { 0x00009908, 0x00000000 },
3110 + { 0x0000990c, 0x00000000 },
3111 + { 0x0000991c, 0x10000fff },
3112 + { 0x00009920, 0x05100000 },
3113 + { 0x0000a920, 0x05100000 },
3114 + { 0x0000b920, 0x05100000 },
3115 + { 0x00009928, 0x00000001 },
3116 + { 0x0000992c, 0x00000004 },
3117 + { 0x00009934, 0x1e1f2022 },
3118 + { 0x00009938, 0x0a0b0c0d },
3119 + { 0x0000993c, 0x00000000 },
3120 + { 0x00009948, 0x9280b212 },
3121 + { 0x0000994c, 0x00020028 },
3122 + { 0x00009954, 0x5f3ca3de },
3123 + { 0x00009958, 0x2108ecff },
3124 + { 0x00009940, 0x00750604 },
3125 + { 0x0000c95c, 0x004b6a8e },
3126 + { 0x00009970, 0x190fb515 },
3127 + { 0x00009974, 0x00000000 },
3128 + { 0x00009978, 0x00000001 },
3129 + { 0x0000997c, 0x00000000 },
3130 + { 0x00009980, 0x00000000 },
3131 + { 0x00009984, 0x00000000 },
3132 + { 0x00009988, 0x00000000 },
3133 + { 0x0000998c, 0x00000000 },
3134 + { 0x00009990, 0x00000000 },
3135 + { 0x00009994, 0x00000000 },
3136 + { 0x00009998, 0x00000000 },
3137 + { 0x0000999c, 0x00000000 },
3138 + { 0x000099a0, 0x00000000 },
3139 + { 0x000099a4, 0x00000001 },
3140 + { 0x000099a8, 0x201fff00 },
3141 + { 0x000099ac, 0x006f0000 },
3142 + { 0x000099b0, 0x03051000 },
3143 + { 0x000099dc, 0x00000000 },
3144 + { 0x000099e0, 0x00000200 },
3145 + { 0x000099e4, 0xaaaaaaaa },
3146 + { 0x000099e8, 0x3c466478 },
3147 + { 0x000099ec, 0x0cc80caa },
3148 + { 0x000099fc, 0x00001042 },
3149 + { 0x00009b00, 0x00000000 },
3150 + { 0x00009b04, 0x00000001 },
3151 + { 0x00009b08, 0x00000002 },
3152 + { 0x00009b0c, 0x00000003 },
3153 + { 0x00009b10, 0x00000004 },
3154 + { 0x00009b14, 0x00000005 },
3155 + { 0x00009b18, 0x00000008 },
3156 + { 0x00009b1c, 0x00000009 },
3157 + { 0x00009b20, 0x0000000a },
3158 + { 0x00009b24, 0x0000000b },
3159 + { 0x00009b28, 0x0000000c },
3160 + { 0x00009b2c, 0x0000000d },
3161 + { 0x00009b30, 0x00000010 },
3162 + { 0x00009b34, 0x00000011 },
3163 + { 0x00009b38, 0x00000012 },
3164 + { 0x00009b3c, 0x00000013 },
3165 + { 0x00009b40, 0x00000014 },
3166 + { 0x00009b44, 0x00000015 },
3167 + { 0x00009b48, 0x00000018 },
3168 + { 0x00009b4c, 0x00000019 },
3169 + { 0x00009b50, 0x0000001a },
3170 + { 0x00009b54, 0x0000001b },
3171 + { 0x00009b58, 0x0000001c },
3172 + { 0x00009b5c, 0x0000001d },
3173 + { 0x00009b60, 0x00000020 },
3174 + { 0x00009b64, 0x00000021 },
3175 + { 0x00009b68, 0x00000022 },
3176 + { 0x00009b6c, 0x00000023 },
3177 + { 0x00009b70, 0x00000024 },
3178 + { 0x00009b74, 0x00000025 },
3179 + { 0x00009b78, 0x00000028 },
3180 + { 0x00009b7c, 0x00000029 },
3181 + { 0x00009b80, 0x0000002a },
3182 + { 0x00009b84, 0x0000002b },
3183 + { 0x00009b88, 0x0000002c },
3184 + { 0x00009b8c, 0x0000002d },
3185 + { 0x00009b90, 0x00000030 },
3186 + { 0x00009b94, 0x00000031 },
3187 + { 0x00009b98, 0x00000032 },
3188 + { 0x00009b9c, 0x00000033 },
3189 + { 0x00009ba0, 0x00000034 },
3190 + { 0x00009ba4, 0x00000035 },
3191 + { 0x00009ba8, 0x00000035 },
3192 + { 0x00009bac, 0x00000035 },
3193 + { 0x00009bb0, 0x00000035 },
3194 + { 0x00009bb4, 0x00000035 },
3195 + { 0x00009bb8, 0x00000035 },
3196 + { 0x00009bbc, 0x00000035 },
3197 + { 0x00009bc0, 0x00000035 },
3198 + { 0x00009bc4, 0x00000035 },
3199 + { 0x00009bc8, 0x00000035 },
3200 + { 0x00009bcc, 0x00000035 },
3201 + { 0x00009bd0, 0x00000035 },
3202 + { 0x00009bd4, 0x00000035 },
3203 + { 0x00009bd8, 0x00000035 },
3204 + { 0x00009bdc, 0x00000035 },
3205 + { 0x00009be0, 0x00000035 },
3206 + { 0x00009be4, 0x00000035 },
3207 + { 0x00009be8, 0x00000035 },
3208 + { 0x00009bec, 0x00000035 },
3209 + { 0x00009bf0, 0x00000035 },
3210 + { 0x00009bf4, 0x00000035 },
3211 + { 0x00009bf8, 0x00000010 },
3212 + { 0x00009bfc, 0x0000001a },
3213 + { 0x0000a210, 0x40806333 },
3214 + { 0x0000a214, 0x00106c10 },
3215 + { 0x0000a218, 0x009c4060 },
3216 + { 0x0000a220, 0x018830c6 },
3217 + { 0x0000a224, 0x00000400 },
3218 + { 0x0000a228, 0x001a0bb5 },
3219 + { 0x0000a22c, 0x00000000 },
3220 + { 0x0000a234, 0x20202020 },
3221 + { 0x0000a238, 0x20202020 },
3222 + { 0x0000a23c, 0x13c889af },
3223 + { 0x0000a240, 0x38490a20 },
3224 + { 0x0000a244, 0x00007bb6 },
3225 + { 0x0000a248, 0x0fff3ffc },
3226 + { 0x0000a24c, 0x00000001 },
3227 + { 0x0000a250, 0x0000e000 },
3228 + { 0x0000a254, 0x00000000 },
3229 + { 0x0000a258, 0x0cc75380 },
3230 + { 0x0000a25c, 0x0f0f0f01 },
3231 + { 0x0000a260, 0xdfa91f01 },
3232 + { 0x0000a268, 0x00000001 },
3233 + { 0x0000a26c, 0x0ebae9c6 },
3234 + { 0x0000b26c, 0x0ebae9c6 },
3235 + { 0x0000c26c, 0x0ebae9c6 },
3236 + { 0x0000d270, 0x00820820 },
3237 + { 0x0000a278, 0x1ce739ce },
3238 + { 0x0000a27c, 0x050701ce },
3239 + { 0x0000a338, 0x00000000 },
3240 + { 0x0000a33c, 0x00000000 },
3241 + { 0x0000a340, 0x00000000 },
3242 + { 0x0000a344, 0x00000000 },
3243 + { 0x0000a348, 0x3fffffff },
3244 + { 0x0000a34c, 0x3fffffff },
3245 + { 0x0000a350, 0x3fffffff },
3246 + { 0x0000a354, 0x0003ffff },
3247 + { 0x0000a358, 0x79bfaa03 },
3248 + { 0x0000d35c, 0x07ffffef },
3249 + { 0x0000d360, 0x0fffffe7 },
3250 + { 0x0000d364, 0x17ffffe5 },
3251 + { 0x0000d368, 0x1fffffe4 },
3252 + { 0x0000d36c, 0x37ffffe3 },
3253 + { 0x0000d370, 0x3fffffe3 },
3254 + { 0x0000d374, 0x57ffffe3 },
3255 + { 0x0000d378, 0x5fffffe2 },
3256 + { 0x0000d37c, 0x7fffffe2 },
3257 + { 0x0000d380, 0x7f3c7bba },
3258 + { 0x0000d384, 0xf3307ff0 },
3259 + { 0x0000a388, 0x0c000000 },
3260 + { 0x0000a38c, 0x20202020 },
3261 + { 0x0000a390, 0x20202020 },
3262 + { 0x0000a394, 0x1ce739ce },
3263 + { 0x0000a398, 0x000001ce },
3264 + { 0x0000a39c, 0x00000001 },
3265 + { 0x0000a3a0, 0x00000000 },
3266 + { 0x0000a3a4, 0x00000000 },
3267 + { 0x0000a3a8, 0x00000000 },
3268 + { 0x0000a3ac, 0x00000000 },
3269 + { 0x0000a3b0, 0x00000000 },
3270 + { 0x0000a3b4, 0x00000000 },
3271 + { 0x0000a3b8, 0x00000000 },
3272 + { 0x0000a3bc, 0x00000000 },
3273 + { 0x0000a3c0, 0x00000000 },
3274 + { 0x0000a3c4, 0x00000000 },
3275 + { 0x0000a3c8, 0x00000246 },
3276 + { 0x0000a3cc, 0x20202020 },
3277 + { 0x0000a3d0, 0x20202020 },
3278 + { 0x0000a3d4, 0x20202020 },
3279 + { 0x0000a3dc, 0x1ce739ce },
3280 + { 0x0000a3e0, 0x000001ce },
3281 +};
3282 +
3283 +static const u32 ar5416Bank0_9160[][2] = {
3284 + { 0x000098b0, 0x1e5795e5 },
3285 + { 0x000098e0, 0x02008020 },
3286 +};
3287 +
3288 +static const u32 ar5416BB_RfGain_9160[][3] = {
3289 + { 0x00009a00, 0x00000000, 0x00000000 },
3290 + { 0x00009a04, 0x00000040, 0x00000040 },
3291 + { 0x00009a08, 0x00000080, 0x00000080 },
3292 + { 0x00009a0c, 0x000001a1, 0x00000141 },
3293 + { 0x00009a10, 0x000001e1, 0x00000181 },
3294 + { 0x00009a14, 0x00000021, 0x000001c1 },
3295 + { 0x00009a18, 0x00000061, 0x00000001 },
3296 + { 0x00009a1c, 0x00000168, 0x00000041 },
3297 + { 0x00009a20, 0x000001a8, 0x000001a8 },
3298 + { 0x00009a24, 0x000001e8, 0x000001e8 },
3299 + { 0x00009a28, 0x00000028, 0x00000028 },
3300 + { 0x00009a2c, 0x00000068, 0x00000068 },
3301 + { 0x00009a30, 0x00000189, 0x000000a8 },
3302 + { 0x00009a34, 0x000001c9, 0x00000169 },
3303 + { 0x00009a38, 0x00000009, 0x000001a9 },
3304 + { 0x00009a3c, 0x00000049, 0x000001e9 },
3305 + { 0x00009a40, 0x00000089, 0x00000029 },
3306 + { 0x00009a44, 0x00000170, 0x00000069 },
3307 + { 0x00009a48, 0x000001b0, 0x00000190 },
3308 + { 0x00009a4c, 0x000001f0, 0x000001d0 },
3309 + { 0x00009a50, 0x00000030, 0x00000010 },
3310 + { 0x00009a54, 0x00000070, 0x00000050 },
3311 + { 0x00009a58, 0x00000191, 0x00000090 },
3312 + { 0x00009a5c, 0x000001d1, 0x00000151 },
3313 + { 0x00009a60, 0x00000011, 0x00000191 },
3314 + { 0x00009a64, 0x00000051, 0x000001d1 },
3315 + { 0x00009a68, 0x00000091, 0x00000011 },
3316 + { 0x00009a6c, 0x000001b8, 0x00000051 },
3317 + { 0x00009a70, 0x000001f8, 0x00000198 },
3318 + { 0x00009a74, 0x00000038, 0x000001d8 },
3319 + { 0x00009a78, 0x00000078, 0x00000018 },
3320 + { 0x00009a7c, 0x00000199, 0x00000058 },
3321 + { 0x00009a80, 0x000001d9, 0x00000098 },
3322 + { 0x00009a84, 0x00000019, 0x00000159 },
3323 + { 0x00009a88, 0x00000059, 0x00000199 },
3324 + { 0x00009a8c, 0x00000099, 0x000001d9 },
3325 + { 0x00009a90, 0x000000d9, 0x00000019 },
3326 + { 0x00009a94, 0x000000f9, 0x00000059 },
3327 + { 0x00009a98, 0x000000f9, 0x00000099 },
3328 + { 0x00009a9c, 0x000000f9, 0x000000d9 },
3329 + { 0x00009aa0, 0x000000f9, 0x000000f9 },
3330 + { 0x00009aa4, 0x000000f9, 0x000000f9 },
3331 + { 0x00009aa8, 0x000000f9, 0x000000f9 },
3332 + { 0x00009aac, 0x000000f9, 0x000000f9 },
3333 + { 0x00009ab0, 0x000000f9, 0x000000f9 },
3334 + { 0x00009ab4, 0x000000f9, 0x000000f9 },
3335 + { 0x00009ab8, 0x000000f9, 0x000000f9 },
3336 + { 0x00009abc, 0x000000f9, 0x000000f9 },
3337 + { 0x00009ac0, 0x000000f9, 0x000000f9 },
3338 + { 0x00009ac4, 0x000000f9, 0x000000f9 },
3339 + { 0x00009ac8, 0x000000f9, 0x000000f9 },
3340 + { 0x00009acc, 0x000000f9, 0x000000f9 },
3341 + { 0x00009ad0, 0x000000f9, 0x000000f9 },
3342 + { 0x00009ad4, 0x000000f9, 0x000000f9 },
3343 + { 0x00009ad8, 0x000000f9, 0x000000f9 },
3344 + { 0x00009adc, 0x000000f9, 0x000000f9 },
3345 + { 0x00009ae0, 0x000000f9, 0x000000f9 },
3346 + { 0x00009ae4, 0x000000f9, 0x000000f9 },
3347 + { 0x00009ae8, 0x000000f9, 0x000000f9 },
3348 + { 0x00009aec, 0x000000f9, 0x000000f9 },
3349 + { 0x00009af0, 0x000000f9, 0x000000f9 },
3350 + { 0x00009af4, 0x000000f9, 0x000000f9 },
3351 + { 0x00009af8, 0x000000f9, 0x000000f9 },
3352 + { 0x00009afc, 0x000000f9, 0x000000f9 },
3353 +};
3354 +
3355 +static const u32 ar5416Bank1_9160[][2] = {
3356 + { 0x000098b0, 0x02108421 },
3357 + { 0x000098ec, 0x00000008 },
3358 +};
3359 +
3360 +static const u32 ar5416Bank2_9160[][2] = {
3361 + { 0x000098b0, 0x0e73ff17 },
3362 + { 0x000098e0, 0x00000420 },
3363 +};
3364 +
3365 +static const u32 ar5416Bank3_9160[][3] = {
3366 + { 0x000098f0, 0x01400018, 0x01c00018 },
3367 +};
3368 +
3369 +static const u32 ar5416Bank6_9160[][3] = {
3370 + { 0x0000989c, 0x00000000, 0x00000000 },
3371 + { 0x0000989c, 0x00000000, 0x00000000 },
3372 + { 0x0000989c, 0x00000000, 0x00000000 },
3373 + { 0x0000989c, 0x00e00000, 0x00e00000 },
3374 + { 0x0000989c, 0x005e0000, 0x005e0000 },
3375 + { 0x0000989c, 0x00120000, 0x00120000 },
3376 + { 0x0000989c, 0x00620000, 0x00620000 },
3377 + { 0x0000989c, 0x00020000, 0x00020000 },
3378 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3379 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3380 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3381 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
3382 + { 0x0000989c, 0x005f0000, 0x005f0000 },
3383 + { 0x0000989c, 0x00870000, 0x00870000 },
3384 + { 0x0000989c, 0x00f90000, 0x00f90000 },
3385 + { 0x0000989c, 0x007b0000, 0x007b0000 },
3386 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3387 + { 0x0000989c, 0x00f50000, 0x00f50000 },
3388 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
3389 + { 0x0000989c, 0x00110000, 0x00110000 },
3390 + { 0x0000989c, 0x006100a8, 0x006100a8 },
3391 + { 0x0000989c, 0x004210a2, 0x004210a2 },
3392 + { 0x0000989c, 0x0014008f, 0x0014008f },
3393 + { 0x0000989c, 0x00c40003, 0x00c40003 },
3394 + { 0x0000989c, 0x003000f2, 0x003000f2 },
3395 + { 0x0000989c, 0x00440016, 0x00440016 },
3396 + { 0x0000989c, 0x00410040, 0x00410040 },
3397 + { 0x0000989c, 0x0001805e, 0x0001805e },
3398 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
3399 + { 0x0000989c, 0x000000f1, 0x000000f1 },
3400 + { 0x0000989c, 0x00002081, 0x00002081 },
3401 + { 0x0000989c, 0x000000d4, 0x000000d4 },
3402 + { 0x000098d0, 0x0000000f, 0x0010000f },
3403 +};
3404 +
3405 +static const u32 ar5416Bank6TPC_9160[][3] = {
3406 + { 0x0000989c, 0x00000000, 0x00000000 },
3407 + { 0x0000989c, 0x00000000, 0x00000000 },
3408 + { 0x0000989c, 0x00000000, 0x00000000 },
3409 + { 0x0000989c, 0x00e00000, 0x00e00000 },
3410 + { 0x0000989c, 0x005e0000, 0x005e0000 },
3411 + { 0x0000989c, 0x00120000, 0x00120000 },
3412 + { 0x0000989c, 0x00620000, 0x00620000 },
3413 + { 0x0000989c, 0x00020000, 0x00020000 },
3414 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3415 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3416 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3417 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
3418 + { 0x0000989c, 0x005f0000, 0x005f0000 },
3419 + { 0x0000989c, 0x00870000, 0x00870000 },
3420 + { 0x0000989c, 0x00f90000, 0x00f90000 },
3421 + { 0x0000989c, 0x007b0000, 0x007b0000 },
3422 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3423 + { 0x0000989c, 0x00f50000, 0x00f50000 },
3424 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
3425 + { 0x0000989c, 0x00110000, 0x00110000 },
3426 + { 0x0000989c, 0x006100a8, 0x006100a8 },
3427 + { 0x0000989c, 0x00423022, 0x00423022 },
3428 + { 0x0000989c, 0x2014008f, 0x2014008f },
3429 + { 0x0000989c, 0x00c40002, 0x00c40002 },
3430 + { 0x0000989c, 0x003000f2, 0x003000f2 },
3431 + { 0x0000989c, 0x00440016, 0x00440016 },
3432 + { 0x0000989c, 0x00410040, 0x00410040 },
3433 + { 0x0000989c, 0x0001805e, 0x0001805e },
3434 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
3435 + { 0x0000989c, 0x000000e1, 0x000000e1 },
3436 + { 0x0000989c, 0x00007080, 0x00007080 },
3437 + { 0x0000989c, 0x000000d4, 0x000000d4 },
3438 + { 0x000098d0, 0x0000000f, 0x0010000f },
3439 +};
3440 +
3441 +static const u32 ar5416Bank7_9160[][2] = {
3442 + { 0x0000989c, 0x00000500 },
3443 + { 0x0000989c, 0x00000800 },
3444 + { 0x000098cc, 0x0000000e },
3445 +};
3446 +
3447 +static u32 ar5416Addac_9160[][2] = {
3448 + {0x0000989c, 0x00000000 },
3449 + {0x0000989c, 0x00000000 },
3450 + {0x0000989c, 0x00000000 },
3451 + {0x0000989c, 0x00000000 },
3452 + {0x0000989c, 0x00000000 },
3453 + {0x0000989c, 0x00000000 },
3454 + {0x0000989c, 0x000000c0 },
3455 + {0x0000989c, 0x00000018 },
3456 + {0x0000989c, 0x00000004 },
3457 + {0x0000989c, 0x00000000 },
3458 + {0x0000989c, 0x00000000 },
3459 + {0x0000989c, 0x00000000 },
3460 + {0x0000989c, 0x00000000 },
3461 + {0x0000989c, 0x00000000 },
3462 + {0x0000989c, 0x00000000 },
3463 + {0x0000989c, 0x00000000 },
3464 + {0x0000989c, 0x00000000 },
3465 + {0x0000989c, 0x00000000 },
3466 + {0x0000989c, 0x00000000 },
3467 + {0x0000989c, 0x00000000 },
3468 + {0x0000989c, 0x00000000 },
3469 + {0x0000989c, 0x000000c0 },
3470 + {0x0000989c, 0x00000019 },
3471 + {0x0000989c, 0x00000004 },
3472 + {0x0000989c, 0x00000000 },
3473 + {0x0000989c, 0x00000000 },
3474 + {0x0000989c, 0x00000000 },
3475 + {0x0000989c, 0x00000004 },
3476 + {0x0000989c, 0x00000003 },
3477 + {0x0000989c, 0x00000008 },
3478 + {0x0000989c, 0x00000000 },
3479 + {0x000098cc, 0x00000000 },
3480 +};
3481 +
3482 +static u32 ar5416Addac_91601_1[][2] = {
3483 + {0x0000989c, 0x00000000 },
3484 + {0x0000989c, 0x00000000 },
3485 + {0x0000989c, 0x00000000 },
3486 + {0x0000989c, 0x00000000 },
3487 + {0x0000989c, 0x00000000 },
3488 + {0x0000989c, 0x00000000 },
3489 + {0x0000989c, 0x000000c0 },
3490 + {0x0000989c, 0x00000018 },
3491 + {0x0000989c, 0x00000004 },
3492 + {0x0000989c, 0x00000000 },
3493 + {0x0000989c, 0x00000000 },
3494 + {0x0000989c, 0x00000000 },
3495 + {0x0000989c, 0x00000000 },
3496 + {0x0000989c, 0x00000000 },
3497 + {0x0000989c, 0x00000000 },
3498 + {0x0000989c, 0x00000000 },
3499 + {0x0000989c, 0x00000000 },
3500 + {0x0000989c, 0x00000000 },
3501 + {0x0000989c, 0x00000000 },
3502 + {0x0000989c, 0x00000000 },
3503 + {0x0000989c, 0x00000000 },
3504 + {0x0000989c, 0x000000c0 },
3505 + {0x0000989c, 0x00000019 },
3506 + {0x0000989c, 0x00000004 },
3507 + {0x0000989c, 0x00000000 },
3508 + {0x0000989c, 0x00000000 },
3509 + {0x0000989c, 0x00000000 },
3510 + {0x0000989c, 0x00000000 },
3511 + {0x0000989c, 0x00000000 },
3512 + {0x0000989c, 0x00000000 },
3513 + {0x0000989c, 0x00000000 },
3514 + {0x000098cc, 0x00000000 },
3515 +};
3516 +
3517 --- /dev/null
3518 +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
3519 @@ -0,0 +1,988 @@
3520 +/*
3521 + * Copyright (c) 2008-2010 Atheros Communications Inc.
3522 + *
3523 + * Permission to use, copy, modify, and/or distribute this software for any
3524 + * purpose with or without fee is hereby granted, provided that the above
3525 + * copyright notice and this permission notice appear in all copies.
3526 + *
3527 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
3528 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
3529 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
3530 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
3531 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
3532 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
3533 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
3534 + */
3535 +
3536 +#include "hw.h"
3537 +#include "hw-ops.h"
3538 +#include "ar9002_phy.h"
3539 +
3540 +#define AR9285_CLCAL_REDO_THRESH 1
3541 +
3542 +static void ar9002_hw_setup_calibration(struct ath_hw *ah,
3543 + struct ath9k_cal_list *currCal)
3544 +{
3545 + struct ath_common *common = ath9k_hw_common(ah);
3546 +
3547 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
3548 + AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
3549 + currCal->calData->calCountMax);
3550 +
3551 + switch (currCal->calData->calType) {
3552 + case IQ_MISMATCH_CAL:
3553 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
3554 + ath_print(common, ATH_DBG_CALIBRATE,
3555 + "starting IQ Mismatch Calibration\n");
3556 + break;
3557 + case ADC_GAIN_CAL:
3558 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
3559 + ath_print(common, ATH_DBG_CALIBRATE,
3560 + "starting ADC Gain Calibration\n");
3561 + break;
3562 + case ADC_DC_CAL:
3563 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
3564 + ath_print(common, ATH_DBG_CALIBRATE,
3565 + "starting ADC DC Calibration\n");
3566 + break;
3567 + case ADC_DC_INIT_CAL:
3568 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
3569 + ath_print(common, ATH_DBG_CALIBRATE,
3570 + "starting Init ADC DC Calibration\n");
3571 + break;
3572 + case TEMP_COMP_CAL:
3573 + break; /* Not supported */
3574 + }
3575 +
3576 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3577 + AR_PHY_TIMING_CTRL4_DO_CAL);
3578 +}
3579 +
3580 +static bool ar9002_hw_per_calibration(struct ath_hw *ah,
3581 + struct ath9k_channel *ichan,
3582 + u8 rxchainmask,
3583 + struct ath9k_cal_list *currCal)
3584 +{
3585 + bool iscaldone = false;
3586 +
3587 + if (currCal->calState == CAL_RUNNING) {
3588 + if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
3589 + AR_PHY_TIMING_CTRL4_DO_CAL)) {
3590 +
3591 + currCal->calData->calCollect(ah);
3592 + ah->cal_samples++;
3593 +
3594 + if (ah->cal_samples >= currCal->calData->calNumSamples) {
3595 + int i, numChains = 0;
3596 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3597 + if (rxchainmask & (1 << i))
3598 + numChains++;
3599 + }
3600 +
3601 + currCal->calData->calPostProc(ah, numChains);
3602 + ichan->CalValid |= currCal->calData->calType;
3603 + currCal->calState = CAL_DONE;
3604 + iscaldone = true;
3605 + } else {
3606 + ar9002_hw_setup_calibration(ah, currCal);
3607 + }
3608 + }
3609 + } else if (!(ichan->CalValid & currCal->calData->calType)) {
3610 + ath9k_hw_reset_calibration(ah, currCal);
3611 + }
3612 +
3613 + return iscaldone;
3614 +}
3615 +
3616 +/* Assumes you are talking about the currently configured channel */
3617 +static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
3618 + enum ath9k_cal_types calType)
3619 +{
3620 + struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3621 +
3622 + switch (calType & ah->supp_cals) {
3623 + case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
3624 + return true;
3625 + case ADC_GAIN_CAL:
3626 + case ADC_DC_CAL:
3627 + if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
3628 + conf_is_ht20(conf)))
3629 + return true;
3630 + break;
3631 + }
3632 + return false;
3633 +}
3634 +
3635 +static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
3636 +{
3637 + int i;
3638 +
3639 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3640 + ah->totalPowerMeasI[i] +=
3641 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3642 + ah->totalPowerMeasQ[i] +=
3643 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3644 + ah->totalIqCorrMeas[i] +=
3645 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3646 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3647 + "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
3648 + ah->cal_samples, i, ah->totalPowerMeasI[i],
3649 + ah->totalPowerMeasQ[i],
3650 + ah->totalIqCorrMeas[i]);
3651 + }
3652 +}
3653 +
3654 +static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
3655 +{
3656 + int i;
3657 +
3658 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3659 + ah->totalAdcIOddPhase[i] +=
3660 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3661 + ah->totalAdcIEvenPhase[i] +=
3662 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3663 + ah->totalAdcQOddPhase[i] +=
3664 + REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3665 + ah->totalAdcQEvenPhase[i] +=
3666 + REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3667 +
3668 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3669 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3670 + "oddq=0x%08x; evenq=0x%08x;\n",
3671 + ah->cal_samples, i,
3672 + ah->totalAdcIOddPhase[i],
3673 + ah->totalAdcIEvenPhase[i],
3674 + ah->totalAdcQOddPhase[i],
3675 + ah->totalAdcQEvenPhase[i]);
3676 + }
3677 +}
3678 +
3679 +static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
3680 +{
3681 + int i;
3682 +
3683 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3684 + ah->totalAdcDcOffsetIOddPhase[i] +=
3685 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3686 + ah->totalAdcDcOffsetIEvenPhase[i] +=
3687 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3688 + ah->totalAdcDcOffsetQOddPhase[i] +=
3689 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3690 + ah->totalAdcDcOffsetQEvenPhase[i] +=
3691 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3692 +
3693 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3694 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3695 + "oddq=0x%08x; evenq=0x%08x;\n",
3696 + ah->cal_samples, i,
3697 + ah->totalAdcDcOffsetIOddPhase[i],
3698 + ah->totalAdcDcOffsetIEvenPhase[i],
3699 + ah->totalAdcDcOffsetQOddPhase[i],
3700 + ah->totalAdcDcOffsetQEvenPhase[i]);
3701 + }
3702 +}
3703 +
3704 +static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
3705 +{
3706 + struct ath_common *common = ath9k_hw_common(ah);
3707 + u32 powerMeasQ, powerMeasI, iqCorrMeas;
3708 + u32 qCoffDenom, iCoffDenom;
3709 + int32_t qCoff, iCoff;
3710 + int iqCorrNeg, i;
3711 +
3712 + for (i = 0; i < numChains; i++) {
3713 + powerMeasI = ah->totalPowerMeasI[i];
3714 + powerMeasQ = ah->totalPowerMeasQ[i];
3715 + iqCorrMeas = ah->totalIqCorrMeas[i];
3716 +
3717 + ath_print(common, ATH_DBG_CALIBRATE,
3718 + "Starting IQ Cal and Correction for Chain %d\n",
3719 + i);
3720 +
3721 + ath_print(common, ATH_DBG_CALIBRATE,
3722 + "Orignal: Chn %diq_corr_meas = 0x%08x\n",
3723 + i, ah->totalIqCorrMeas[i]);
3724 +
3725 + iqCorrNeg = 0;
3726 +
3727 + if (iqCorrMeas > 0x80000000) {
3728 + iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
3729 + iqCorrNeg = 1;
3730 + }
3731 +
3732 + ath_print(common, ATH_DBG_CALIBRATE,
3733 + "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
3734 + ath_print(common, ATH_DBG_CALIBRATE,
3735 + "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
3736 + ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
3737 + iqCorrNeg);
3738 +
3739 + iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
3740 + qCoffDenom = powerMeasQ / 64;
3741 +
3742 + if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
3743 + (qCoffDenom != 0)) {
3744 + iCoff = iqCorrMeas / iCoffDenom;
3745 + qCoff = powerMeasI / qCoffDenom - 64;
3746 + ath_print(common, ATH_DBG_CALIBRATE,
3747 + "Chn %d iCoff = 0x%08x\n", i, iCoff);
3748 + ath_print(common, ATH_DBG_CALIBRATE,
3749 + "Chn %d qCoff = 0x%08x\n", i, qCoff);
3750 +
3751 + iCoff = iCoff & 0x3f;
3752 + ath_print(common, ATH_DBG_CALIBRATE,
3753 + "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
3754 + if (iqCorrNeg == 0x0)
3755 + iCoff = 0x40 - iCoff;
3756 +
3757 + if (qCoff > 15)
3758 + qCoff = 15;
3759 + else if (qCoff <= -16)
3760 + qCoff = 16;
3761 +
3762 + ath_print(common, ATH_DBG_CALIBRATE,
3763 + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
3764 + i, iCoff, qCoff);
3765 +
3766 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3767 + AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
3768 + iCoff);
3769 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3770 + AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
3771 + qCoff);
3772 + ath_print(common, ATH_DBG_CALIBRATE,
3773 + "IQ Cal and Correction done for Chain %d\n",
3774 + i);
3775 + }
3776 + }
3777 +
3778 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3779 + AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
3780 +}
3781 +
3782 +static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
3783 +{
3784 + struct ath_common *common = ath9k_hw_common(ah);
3785 + u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
3786 + u32 qGainMismatch, iGainMismatch, val, i;
3787 +
3788 + for (i = 0; i < numChains; i++) {
3789 + iOddMeasOffset = ah->totalAdcIOddPhase[i];
3790 + iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
3791 + qOddMeasOffset = ah->totalAdcQOddPhase[i];
3792 + qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
3793 +
3794 + ath_print(common, ATH_DBG_CALIBRATE,
3795 + "Starting ADC Gain Cal for Chain %d\n", i);
3796 +
3797 + ath_print(common, ATH_DBG_CALIBRATE,
3798 + "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
3799 + iOddMeasOffset);
3800 + ath_print(common, ATH_DBG_CALIBRATE,
3801 + "Chn %d pwr_meas_even_i = 0x%08x\n", i,
3802 + iEvenMeasOffset);
3803 + ath_print(common, ATH_DBG_CALIBRATE,
3804 + "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
3805 + qOddMeasOffset);
3806 + ath_print(common, ATH_DBG_CALIBRATE,
3807 + "Chn %d pwr_meas_even_q = 0x%08x\n", i,
3808 + qEvenMeasOffset);
3809 +
3810 + if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
3811 + iGainMismatch =
3812 + ((iEvenMeasOffset * 32) /
3813 + iOddMeasOffset) & 0x3f;
3814 + qGainMismatch =
3815 + ((qOddMeasOffset * 32) /
3816 + qEvenMeasOffset) & 0x3f;
3817 +
3818 + ath_print(common, ATH_DBG_CALIBRATE,
3819 + "Chn %d gain_mismatch_i = 0x%08x\n", i,
3820 + iGainMismatch);
3821 + ath_print(common, ATH_DBG_CALIBRATE,
3822 + "Chn %d gain_mismatch_q = 0x%08x\n", i,
3823 + qGainMismatch);
3824 +
3825 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
3826 + val &= 0xfffff000;
3827 + val |= (qGainMismatch) | (iGainMismatch << 6);
3828 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
3829 +
3830 + ath_print(common, ATH_DBG_CALIBRATE,
3831 + "ADC Gain Cal done for Chain %d\n", i);
3832 + }
3833 + }
3834 +
3835 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
3836 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
3837 + AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
3838 +}
3839 +
3840 +static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
3841 +{
3842 + struct ath_common *common = ath9k_hw_common(ah);
3843 + u32 iOddMeasOffset, iEvenMeasOffset, val, i;
3844 + int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
3845 + const struct ath9k_percal_data *calData =
3846 + ah->cal_list_curr->calData;
3847 + u32 numSamples =
3848 + (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
3849 +
3850 + for (i = 0; i < numChains; i++) {
3851 + iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
3852 + iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
3853 + qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
3854 + qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
3855 +
3856 + ath_print(common, ATH_DBG_CALIBRATE,
3857 + "Starting ADC DC Offset Cal for Chain %d\n", i);
3858 +
3859 + ath_print(common, ATH_DBG_CALIBRATE,
3860 + "Chn %d pwr_meas_odd_i = %d\n", i,
3861 + iOddMeasOffset);
3862 + ath_print(common, ATH_DBG_CALIBRATE,
3863 + "Chn %d pwr_meas_even_i = %d\n", i,
3864 + iEvenMeasOffset);
3865 + ath_print(common, ATH_DBG_CALIBRATE,
3866 + "Chn %d pwr_meas_odd_q = %d\n", i,
3867 + qOddMeasOffset);
3868 + ath_print(common, ATH_DBG_CALIBRATE,
3869 + "Chn %d pwr_meas_even_q = %d\n", i,
3870 + qEvenMeasOffset);
3871 +
3872 + iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
3873 + numSamples) & 0x1ff;
3874 + qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
3875 + numSamples) & 0x1ff;
3876 +
3877 + ath_print(common, ATH_DBG_CALIBRATE,
3878 + "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
3879 + iDcMismatch);
3880 + ath_print(common, ATH_DBG_CALIBRATE,
3881 + "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
3882 + qDcMismatch);
3883 +
3884 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
3885 + val &= 0xc0000fff;
3886 + val |= (qDcMismatch << 12) | (iDcMismatch << 21);
3887 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
3888 +
3889 + ath_print(common, ATH_DBG_CALIBRATE,
3890 + "ADC DC Offset Cal done for Chain %d\n", i);
3891 + }
3892 +
3893 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
3894 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
3895 + AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
3896 +}
3897 +
3898 +static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
3899 +{
3900 + u32 rddata;
3901 + int32_t delta, currPDADC, slope;
3902 +
3903 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
3904 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
3905 +
3906 + if (ah->initPDADC == 0 || currPDADC == 0) {
3907 + /*
3908 + * Zero value indicates that no frames have been transmitted yet,
3909 + * can't do temperature compensation until frames are transmitted.
3910 + */
3911 + return;
3912 + } else {
3913 + slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
3914 +
3915 + if (slope == 0) { /* to avoid divide by zero case */
3916 + delta = 0;
3917 + } else {
3918 + delta = ((currPDADC - ah->initPDADC)*4) / slope;
3919 + }
3920 + REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
3921 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
3922 + REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
3923 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
3924 + }
3925 +}
3926 +
3927 +static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
3928 +{
3929 + u32 rddata, i;
3930 + int delta, currPDADC, regval;
3931 +
3932 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
3933 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
3934 +
3935 + if (ah->initPDADC == 0 || currPDADC == 0)
3936 + return;
3937 +
3938 + if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
3939 + delta = (currPDADC - ah->initPDADC + 4) / 8;
3940 + else
3941 + delta = (currPDADC - ah->initPDADC + 5) / 10;
3942 +
3943 + if (delta != ah->PDADCdelta) {
3944 + ah->PDADCdelta = delta;
3945 + for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
3946 + regval = ah->originalGain[i] - delta;
3947 + if (regval < 0)
3948 + regval = 0;
3949 +
3950 + REG_RMW_FIELD(ah,
3951 + AR_PHY_TX_GAIN_TBL1 + i * 4,
3952 + AR_PHY_TX_GAIN, regval);
3953 + }
3954 + }
3955 +}
3956 +
3957 +static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
3958 +{
3959 + u32 regVal;
3960 + unsigned int i;
3961 + u32 regList [][2] = {
3962 + { 0x786c, 0 },
3963 + { 0x7854, 0 },
3964 + { 0x7820, 0 },
3965 + { 0x7824, 0 },
3966 + { 0x7868, 0 },
3967 + { 0x783c, 0 },
3968 + { 0x7838, 0 } ,
3969 + { 0x7828, 0 } ,
3970 + };
3971 +
3972 + for (i = 0; i < ARRAY_SIZE(regList); i++)
3973 + regList[i][1] = REG_READ(ah, regList[i][0]);
3974 +
3975 + regVal = REG_READ(ah, 0x7834);
3976 + regVal &= (~(0x1));
3977 + REG_WRITE(ah, 0x7834, regVal);
3978 + regVal = REG_READ(ah, 0x9808);
3979 + regVal |= (0x1 << 27);
3980 + REG_WRITE(ah, 0x9808, regVal);
3981 +
3982 + /* 786c,b23,1, pwddac=1 */
3983 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
3984 + /* 7854, b5,1, pdrxtxbb=1 */
3985 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
3986 + /* 7854, b7,1, pdv2i=1 */
3987 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
3988 + /* 7854, b8,1, pddacinterface=1 */
3989 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
3990 + /* 7824,b12,0, offcal=0 */
3991 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
3992 + /* 7838, b1,0, pwddb=0 */
3993 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
3994 + /* 7820,b11,0, enpacal=0 */
3995 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
3996 + /* 7820,b25,1, pdpadrv1=0 */
3997 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
3998 + /* 7820,b24,0, pdpadrv2=0 */
3999 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
4000 + /* 7820,b23,0, pdpaout=0 */
4001 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4002 + /* 783c,b14-16,7, padrvgn2tab_0=7 */
4003 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4004 + /*
4005 + * 7838,b29-31,0, padrvgn1tab_0=0
4006 + * does not matter since we turn it off
4007 + */
4008 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4009 +
4010 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
4011 +
4012 + /* Set:
4013 + * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
4014 + * txon=1,paon=1,oscon=1,synthon_force=1
4015 + */
4016 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4017 + udelay(30);
4018 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
4019 +
4020 + /* find off_6_1; */
4021 + for (i = 6; i > 0; i--) {
4022 + regVal = REG_READ(ah, 0x7834);
4023 + regVal |= (1 << (20 + i));
4024 + REG_WRITE(ah, 0x7834, regVal);
4025 + udelay(1);
4026 + //regVal = REG_READ(ah, 0x7834);
4027 + regVal &= (~(0x1 << (20 + i)));
4028 + regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
4029 + << (20 + i));
4030 + REG_WRITE(ah, 0x7834, regVal);
4031 + }
4032 +
4033 + regVal = (regVal >>20) & 0x7f;
4034 +
4035 + /* Update PA cal info */
4036 + if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
4037 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4038 + ah->pacal_info.max_skipcount =
4039 + 2 * ah->pacal_info.max_skipcount;
4040 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4041 + } else {
4042 + ah->pacal_info.max_skipcount = 1;
4043 + ah->pacal_info.skipcount = 0;
4044 + ah->pacal_info.prev_offset = regVal;
4045 + }
4046 +
4047 + regVal = REG_READ(ah, 0x7834);
4048 + regVal |= 0x1;
4049 + REG_WRITE(ah, 0x7834, regVal);
4050 + regVal = REG_READ(ah, 0x9808);
4051 + regVal &= (~(0x1 << 27));
4052 + REG_WRITE(ah, 0x9808, regVal);
4053 +
4054 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4055 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4056 +}
4057 +
4058 +static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4059 +{
4060 + struct ath_common *common = ath9k_hw_common(ah);
4061 + u32 regVal;
4062 + int i, offset, offs_6_1, offs_0;
4063 + u32 ccomp_org, reg_field;
4064 + u32 regList[][2] = {
4065 + { 0x786c, 0 },
4066 + { 0x7854, 0 },
4067 + { 0x7820, 0 },
4068 + { 0x7824, 0 },
4069 + { 0x7868, 0 },
4070 + { 0x783c, 0 },
4071 + { 0x7838, 0 },
4072 + };
4073 +
4074 + ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
4075 +
4076 + /* PA CAL is not needed for high power solution */
4077 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
4078 + AR5416_EEP_TXGAIN_HIGH_POWER)
4079 + return;
4080 +
4081 + if (AR_SREV_9285_11(ah)) {
4082 + REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
4083 + udelay(10);
4084 + }
4085 +
4086 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4087 + regList[i][1] = REG_READ(ah, regList[i][0]);
4088 +
4089 + regVal = REG_READ(ah, 0x7834);
4090 + regVal &= (~(0x1));
4091 + REG_WRITE(ah, 0x7834, regVal);
4092 + regVal = REG_READ(ah, 0x9808);
4093 + regVal |= (0x1 << 27);
4094 + REG_WRITE(ah, 0x9808, regVal);
4095 +
4096 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
4097 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
4098 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
4099 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
4100 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
4101 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
4102 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
4103 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
4104 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
4105 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4106 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4107 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4108 + ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
4109 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
4110 +
4111 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4112 + udelay(30);
4113 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
4114 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
4115 +
4116 + for (i = 6; i > 0; i--) {
4117 + regVal = REG_READ(ah, 0x7834);
4118 + regVal |= (1 << (19 + i));
4119 + REG_WRITE(ah, 0x7834, regVal);
4120 + udelay(1);
4121 + regVal = REG_READ(ah, 0x7834);
4122 + regVal &= (~(0x1 << (19 + i)));
4123 + reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
4124 + regVal |= (reg_field << (19 + i));
4125 + REG_WRITE(ah, 0x7834, regVal);
4126 + }
4127 +
4128 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
4129 + udelay(1);
4130 + reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
4131 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
4132 + offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
4133 + offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
4134 +
4135 + offset = (offs_6_1<<1) | offs_0;
4136 + offset = offset - 0;
4137 + offs_6_1 = offset>>1;
4138 + offs_0 = offset & 1;
4139 +
4140 + if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
4141 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4142 + ah->pacal_info.max_skipcount =
4143 + 2 * ah->pacal_info.max_skipcount;
4144 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4145 + } else {
4146 + ah->pacal_info.max_skipcount = 1;
4147 + ah->pacal_info.skipcount = 0;
4148 + ah->pacal_info.prev_offset = offset;
4149 + }
4150 +
4151 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
4152 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
4153 +
4154 + regVal = REG_READ(ah, 0x7834);
4155 + regVal |= 0x1;
4156 + REG_WRITE(ah, 0x7834, regVal);
4157 + regVal = REG_READ(ah, 0x9808);
4158 + regVal &= (~(0x1 << 27));
4159 + REG_WRITE(ah, 0x9808, regVal);
4160 +
4161 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4162 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4163 +
4164 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
4165 +
4166 + if (AR_SREV_9285_11(ah))
4167 + REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
4168 +
4169 +}
4170 +
4171 +static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)