mac80211: reorganize patches
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 300-pending_work.patch
1 --- a/drivers/net/wireless/ath/ath5k/mac80211-ops.c
2 +++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
3 @@ -210,8 +210,8 @@ ath5k_config(struct ieee80211_hw *hw, u3
4 }
5
6 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
7 - (ah->power_level != conf->power_level)) {
8 - ah->power_level = conf->power_level;
9 + (ah->ah_txpower.txp_requested != conf->power_level)) {
10 + ah->ah_txpower.txp_requested = conf->power_level;
11
12 /* Half dB steps */
13 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
14 @@ -622,7 +622,7 @@ ath5k_conf_tx(struct ieee80211_hw *hw, s
15 qi.tqi_aifs = params->aifs;
16 qi.tqi_cw_min = params->cw_min;
17 qi.tqi_cw_max = params->cw_max;
18 - qi.tqi_burst_time = params->txop;
19 + qi.tqi_burst_time = params->txop * 32;
20
21 ATH5K_DBG(ah, ATH5K_DEBUG_ANY,
22 "Configure tx [queue %d], "
23 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
24 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
25 @@ -26,106 +26,74 @@
26 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
27 {
28 if (AR_SREV_9271(ah)) {
29 - INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
30 - ARRAY_SIZE(ar9271Modes_9271), 5);
31 - INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
32 - ARRAY_SIZE(ar9271Common_9271), 2);
33 - INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
34 - ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5);
35 + INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
36 + INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
37 + INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
38 return;
39 }
40
41 if (ah->config.pcie_clock_req)
42 INIT_INI_ARRAY(&ah->iniPcieSerdes,
43 - ar9280PciePhy_clkreq_off_L1_9280,
44 - ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
45 + ar9280PciePhy_clkreq_off_L1_9280);
46 else
47 INIT_INI_ARRAY(&ah->iniPcieSerdes,
48 - ar9280PciePhy_clkreq_always_on_L1_9280,
49 - ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
50 + ar9280PciePhy_clkreq_always_on_L1_9280);
51 #ifdef CONFIG_PM_SLEEP
52 INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
53 - ar9280PciePhy_awow,
54 - ARRAY_SIZE(ar9280PciePhy_awow), 2);
55 + ar9280PciePhy_awow);
56 #endif
57
58 if (AR_SREV_9287_11_OR_LATER(ah)) {
59 - INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
60 - ARRAY_SIZE(ar9287Modes_9287_1_1), 5);
61 - INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
62 - ARRAY_SIZE(ar9287Common_9287_1_1), 2);
63 + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
64 + INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
65 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
66 - INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
67 - ARRAY_SIZE(ar9285Modes_9285_1_2), 5);
68 - INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
69 - ARRAY_SIZE(ar9285Common_9285_1_2), 2);
70 + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
71 + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
72 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
73 - INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
74 - ARRAY_SIZE(ar9280Modes_9280_2), 5);
75 - INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
76 - ARRAY_SIZE(ar9280Common_9280_2), 2);
77 + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
78 + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
79
80 INIT_INI_ARRAY(&ah->iniModesFastClock,
81 - ar9280Modes_fast_clock_9280_2,
82 - ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
83 + ar9280Modes_fast_clock_9280_2);
84 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
85 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
86 - ARRAY_SIZE(ar5416Modes_9160), 5);
87 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
88 - ARRAY_SIZE(ar5416Common_9160), 2);
89 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
90 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
91 if (AR_SREV_9160_11(ah)) {
92 INIT_INI_ARRAY(&ah->iniAddac,
93 - ar5416Addac_9160_1_1,
94 - ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
95 + ar5416Addac_9160_1_1);
96 } else {
97 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
98 - ARRAY_SIZE(ar5416Addac_9160), 2);
99 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
100 }
101 } else if (AR_SREV_9100_OR_LATER(ah)) {
102 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
103 - ARRAY_SIZE(ar5416Modes_9100), 5);
104 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
105 - ARRAY_SIZE(ar5416Common_9100), 2);
106 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
107 - ARRAY_SIZE(ar5416Bank6_9100), 3);
108 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
109 - ARRAY_SIZE(ar5416Addac_9100), 2);
110 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
111 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
112 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
113 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
114 } else {
115 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
116 - ARRAY_SIZE(ar5416Modes), 5);
117 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
118 - ARRAY_SIZE(ar5416Common), 2);
119 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
120 - ARRAY_SIZE(ar5416Bank6TPC), 3);
121 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
122 - ARRAY_SIZE(ar5416Addac), 2);
123 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
124 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
125 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
126 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
127 }
128
129 if (!AR_SREV_9280_20_OR_LATER(ah)) {
130 /* Common for AR5416, AR913x, AR9160 */
131 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
132 - ARRAY_SIZE(ar5416BB_RfGain), 3);
133 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
134
135 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
136 - ARRAY_SIZE(ar5416Bank0), 2);
137 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
138 - ARRAY_SIZE(ar5416Bank1), 2);
139 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
140 - ARRAY_SIZE(ar5416Bank2), 2);
141 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
142 - ARRAY_SIZE(ar5416Bank3), 3);
143 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
144 - ARRAY_SIZE(ar5416Bank7), 2);
145 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0);
146 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1);
147 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2);
148 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
149 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
150
151 /* Common for AR5416, AR9160 */
152 if (!AR_SREV_9100(ah))
153 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
154 - ARRAY_SIZE(ar5416Bank6), 3);
155 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
156
157 /* Common for AR913x, AR9160 */
158 if (!AR_SREV_5416(ah))
159 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
160 - ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
161 + INIT_INI_ARRAY(&ah->iniBank6TPC,
162 + ar5416Bank6TPC_9100);
163 }
164
165 /* iniAddac needs to be modified for these chips */
166 @@ -148,13 +116,9 @@ static void ar9002_hw_init_mode_regs(str
167 }
168 if (AR_SREV_9287_11_OR_LATER(ah)) {
169 INIT_INI_ARRAY(&ah->iniCckfirNormal,
170 - ar9287Common_normal_cck_fir_coeff_9287_1_1,
171 - ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
172 - 2);
173 + ar9287Common_normal_cck_fir_coeff_9287_1_1);
174 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
175 - ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
176 - ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
177 - 2);
178 + ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
179 }
180 }
181
182 @@ -168,20 +132,16 @@ static void ar9280_20_hw_init_rxgain_ini
183
184 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
185 INIT_INI_ARRAY(&ah->iniModesRxGain,
186 - ar9280Modes_backoff_13db_rxgain_9280_2,
187 - ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5);
188 + ar9280Modes_backoff_13db_rxgain_9280_2);
189 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
190 INIT_INI_ARRAY(&ah->iniModesRxGain,
191 - ar9280Modes_backoff_23db_rxgain_9280_2,
192 - ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5);
193 + ar9280Modes_backoff_23db_rxgain_9280_2);
194 else
195 INIT_INI_ARRAY(&ah->iniModesRxGain,
196 - ar9280Modes_original_rxgain_9280_2,
197 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
198 + ar9280Modes_original_rxgain_9280_2);
199 } else {
200 INIT_INI_ARRAY(&ah->iniModesRxGain,
201 - ar9280Modes_original_rxgain_9280_2,
202 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
203 + ar9280Modes_original_rxgain_9280_2);
204 }
205 }
206
207 @@ -191,16 +151,13 @@ static void ar9280_20_hw_init_txgain_ini
208 AR5416_EEP_MINOR_VER_19) {
209 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
210 INIT_INI_ARRAY(&ah->iniModesTxGain,
211 - ar9280Modes_high_power_tx_gain_9280_2,
212 - ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5);
213 + ar9280Modes_high_power_tx_gain_9280_2);
214 else
215 INIT_INI_ARRAY(&ah->iniModesTxGain,
216 - ar9280Modes_original_tx_gain_9280_2,
217 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
218 + ar9280Modes_original_tx_gain_9280_2);
219 } else {
220 INIT_INI_ARRAY(&ah->iniModesTxGain,
221 - ar9280Modes_original_tx_gain_9280_2,
222 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
223 + ar9280Modes_original_tx_gain_9280_2);
224 }
225 }
226
227 @@ -208,12 +165,10 @@ static void ar9271_hw_init_txgain_ini(st
228 {
229 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
230 INIT_INI_ARRAY(&ah->iniModesTxGain,
231 - ar9271Modes_high_power_tx_gain_9271,
232 - ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5);
233 + ar9271Modes_high_power_tx_gain_9271);
234 else
235 INIT_INI_ARRAY(&ah->iniModesTxGain,
236 - ar9271Modes_normal_power_tx_gain_9271,
237 - ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5);
238 + ar9271Modes_normal_power_tx_gain_9271);
239 }
240
241 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
242 @@ -222,8 +177,7 @@ static void ar9002_hw_init_mode_gain_reg
243
244 if (AR_SREV_9287_11_OR_LATER(ah))
245 INIT_INI_ARRAY(&ah->iniModesRxGain,
246 - ar9287Modes_rx_gain_9287_1_1,
247 - ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5);
248 + ar9287Modes_rx_gain_9287_1_1);
249 else if (AR_SREV_9280_20(ah))
250 ar9280_20_hw_init_rxgain_ini(ah);
251
252 @@ -231,8 +185,7 @@ static void ar9002_hw_init_mode_gain_reg
253 ar9271_hw_init_txgain_ini(ah, txgain_type);
254 } else if (AR_SREV_9287_11_OR_LATER(ah)) {
255 INIT_INI_ARRAY(&ah->iniModesTxGain,
256 - ar9287Modes_tx_gain_9287_1_1,
257 - ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5);
258 + ar9287Modes_tx_gain_9287_1_1);
259 } else if (AR_SREV_9280_20(ah)) {
260 ar9280_20_hw_init_txgain_ini(ah, txgain_type);
261 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
262 @@ -240,26 +193,18 @@ static void ar9002_hw_init_mode_gain_reg
263 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
264 if (AR_SREV_9285E_20(ah)) {
265 INIT_INI_ARRAY(&ah->iniModesTxGain,
266 - ar9285Modes_XE2_0_high_power,
267 - ARRAY_SIZE(
268 - ar9285Modes_XE2_0_high_power), 5);
269 + ar9285Modes_XE2_0_high_power);
270 } else {
271 INIT_INI_ARRAY(&ah->iniModesTxGain,
272 - ar9285Modes_high_power_tx_gain_9285_1_2,
273 - ARRAY_SIZE(
274 - ar9285Modes_high_power_tx_gain_9285_1_2), 5);
275 + ar9285Modes_high_power_tx_gain_9285_1_2);
276 }
277 } else {
278 if (AR_SREV_9285E_20(ah)) {
279 INIT_INI_ARRAY(&ah->iniModesTxGain,
280 - ar9285Modes_XE2_0_normal_power,
281 - ARRAY_SIZE(
282 - ar9285Modes_XE2_0_normal_power), 5);
283 + ar9285Modes_XE2_0_normal_power);
284 } else {
285 INIT_INI_ARRAY(&ah->iniModesTxGain,
286 - ar9285Modes_original_tx_gain_9285_1_2,
287 - ARRAY_SIZE(
288 - ar9285Modes_original_tx_gain_9285_1_2), 5);
289 + ar9285Modes_original_tx_gain_9285_1_2);
290 }
291 }
292 }
293 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
294 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
295 @@ -131,8 +131,9 @@ static const struct ar9300_eeprom ar9300
296 .thresh62 = 28,
297 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
298 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
299 + .xlna_bias_strength = 0,
300 .futureModal = {
301 - 0, 0, 0, 0, 0, 0, 0, 0,
302 + 0, 0, 0, 0, 0, 0, 0,
303 },
304 },
305 .base_ext1 = {
306 @@ -331,8 +332,9 @@ static const struct ar9300_eeprom ar9300
307 .thresh62 = 28,
308 .papdRateMaskHt20 = LE32(0x0c80c080),
309 .papdRateMaskHt40 = LE32(0x0080c080),
310 + .xlna_bias_strength = 0,
311 .futureModal = {
312 - 0, 0, 0, 0, 0, 0, 0, 0,
313 + 0, 0, 0, 0, 0, 0, 0,
314 },
315 },
316 .base_ext2 = {
317 @@ -704,8 +706,9 @@ static const struct ar9300_eeprom ar9300
318 .thresh62 = 28,
319 .papdRateMaskHt20 = LE32(0x0c80c080),
320 .papdRateMaskHt40 = LE32(0x0080c080),
321 + .xlna_bias_strength = 0,
322 .futureModal = {
323 - 0, 0, 0, 0, 0, 0, 0, 0,
324 + 0, 0, 0, 0, 0, 0, 0,
325 },
326 },
327 .base_ext1 = {
328 @@ -904,8 +907,9 @@ static const struct ar9300_eeprom ar9300
329 .thresh62 = 28,
330 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
331 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
332 + .xlna_bias_strength = 0,
333 .futureModal = {
334 - 0, 0, 0, 0, 0, 0, 0, 0,
335 + 0, 0, 0, 0, 0, 0, 0,
336 },
337 },
338 .base_ext2 = {
339 @@ -1278,8 +1282,9 @@ static const struct ar9300_eeprom ar9300
340 .thresh62 = 28,
341 .papdRateMaskHt20 = LE32(0x0c80c080),
342 .papdRateMaskHt40 = LE32(0x0080c080),
343 + .xlna_bias_strength = 0,
344 .futureModal = {
345 - 0, 0, 0, 0, 0, 0, 0, 0,
346 + 0, 0, 0, 0, 0, 0, 0,
347 },
348 },
349 .base_ext1 = {
350 @@ -1478,8 +1483,9 @@ static const struct ar9300_eeprom ar9300
351 .thresh62 = 28,
352 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
353 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
354 + .xlna_bias_strength = 0,
355 .futureModal = {
356 - 0, 0, 0, 0, 0, 0, 0, 0,
357 + 0, 0, 0, 0, 0, 0, 0,
358 },
359 },
360 .base_ext2 = {
361 @@ -1852,8 +1858,9 @@ static const struct ar9300_eeprom ar9300
362 .thresh62 = 28,
363 .papdRateMaskHt20 = LE32(0x0c80c080),
364 .papdRateMaskHt40 = LE32(0x0080c080),
365 + .xlna_bias_strength = 0,
366 .futureModal = {
367 - 0, 0, 0, 0, 0, 0, 0, 0,
368 + 0, 0, 0, 0, 0, 0, 0,
369 },
370 },
371 .base_ext1 = {
372 @@ -2052,8 +2059,9 @@ static const struct ar9300_eeprom ar9300
373 .thresh62 = 28,
374 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
375 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
376 + .xlna_bias_strength = 0,
377 .futureModal = {
378 - 0, 0, 0, 0, 0, 0, 0, 0,
379 + 0, 0, 0, 0, 0, 0, 0,
380 },
381 },
382 .base_ext2 = {
383 @@ -2425,8 +2433,9 @@ static const struct ar9300_eeprom ar9300
384 .thresh62 = 28,
385 .papdRateMaskHt20 = LE32(0x0c80C080),
386 .papdRateMaskHt40 = LE32(0x0080C080),
387 + .xlna_bias_strength = 0,
388 .futureModal = {
389 - 0, 0, 0, 0, 0, 0, 0, 0,
390 + 0, 0, 0, 0, 0, 0, 0,
391 },
392 },
393 .base_ext1 = {
394 @@ -2625,8 +2634,9 @@ static const struct ar9300_eeprom ar9300
395 .thresh62 = 28,
396 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
397 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
398 + .xlna_bias_strength = 0,
399 .futureModal = {
400 - 0, 0, 0, 0, 0, 0, 0, 0,
401 + 0, 0, 0, 0, 0, 0, 0,
402 },
403 },
404 .base_ext2 = {
405 @@ -2971,14 +2981,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(st
406 return (pBase->txrxMask >> 4) & 0xf;
407 case EEP_RX_MASK:
408 return pBase->txrxMask & 0xf;
409 - case EEP_DRIVE_STRENGTH:
410 -#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
411 - return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
412 - case EEP_INTERNAL_REGULATOR:
413 - /* Bit 4 is internal regulator flag */
414 - return (pBase->featureEnable & 0x10) >> 4;
415 - case EEP_SWREG:
416 - return le32_to_cpu(pBase->swreg);
417 case EEP_PAPRD:
418 return !!(pBase->featureEnable & BIT(5));
419 case EEP_CHAIN_MASK_REDUCE:
420 @@ -2989,8 +2991,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(st
421 return eep->modalHeader5G.antennaGain;
422 case EEP_ANTENNA_GAIN_2G:
423 return eep->modalHeader2G.antennaGain;
424 - case EEP_QUICK_DROP:
425 - return pBase->miscConfiguration & BIT(1);
426 default:
427 return 0;
428 }
429 @@ -3260,10 +3260,20 @@ static int ar9300_eeprom_restore_interna
430 int it;
431 u16 checksum, mchecksum;
432 struct ath_common *common = ath9k_hw_common(ah);
433 + struct ar9300_eeprom *eep;
434 eeprom_read_op read;
435
436 - if (ath9k_hw_use_flash(ah))
437 - return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
438 + if (ath9k_hw_use_flash(ah)) {
439 + u8 txrx;
440 +
441 + ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
442 +
443 + /* check if eeprom contains valid data */
444 + eep = (struct ar9300_eeprom *) mptr;
445 + txrx = eep->baseEepHeader.txrxMask;
446 + if (txrx != 0 && txrx != 0xff)
447 + return 0;
448 + }
449
450 word = kzalloc(2048, GFP_KERNEL);
451 if (!word)
452 @@ -3493,19 +3503,20 @@ static int ath9k_hw_ar9300_get_eeprom_re
453 return 0;
454 }
455
456 -static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
457 +static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
458 + bool is2ghz)
459 {
460 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
461
462 if (is2ghz)
463 - return eep->modalHeader2G.xpaBiasLvl;
464 + return &eep->modalHeader2G;
465 else
466 - return eep->modalHeader5G.xpaBiasLvl;
467 + return &eep->modalHeader5G;
468 }
469
470 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
471 {
472 - int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
473 + int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
474
475 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
476 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
477 @@ -3521,57 +3532,26 @@ static void ar9003_hw_xpa_bias_level_app
478 }
479 }
480
481 -static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
482 +static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
483 {
484 - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
485 - __le16 val;
486 -
487 - if (is_2ghz)
488 - val = eep->modalHeader2G.switchcomspdt;
489 - else
490 - val = eep->modalHeader5G.switchcomspdt;
491 - return le16_to_cpu(val);
492 + return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
493 }
494
495
496 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
497 {
498 - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
499 - __le32 val;
500 -
501 - if (is2ghz)
502 - val = eep->modalHeader2G.antCtrlCommon;
503 - else
504 - val = eep->modalHeader5G.antCtrlCommon;
505 - return le32_to_cpu(val);
506 + return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
507 }
508
509 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
510 {
511 - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
512 - __le32 val;
513 -
514 - if (is2ghz)
515 - val = eep->modalHeader2G.antCtrlCommon2;
516 - else
517 - val = eep->modalHeader5G.antCtrlCommon2;
518 - return le32_to_cpu(val);
519 + return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
520 }
521
522 -static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
523 - int chain,
524 +static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
525 bool is2ghz)
526 {
527 - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
528 - __le16 val = 0;
529 -
530 - if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
531 - if (is2ghz)
532 - val = eep->modalHeader2G.antCtrlChain[chain];
533 - else
534 - val = eep->modalHeader5G.antCtrlChain[chain];
535 - }
536 -
537 + __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
538 return le16_to_cpu(val);
539 }
540
541 @@ -3681,11 +3661,12 @@ static void ar9003_hw_ant_ctrl_apply(str
542
543 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
544 {
545 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
546 + struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
547 int drive_strength;
548 unsigned long reg;
549
550 - drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
551 -
552 + drive_strength = pBase->miscConfiguration & BIT(0);
553 if (!drive_strength)
554 return;
555
556 @@ -3815,11 +3796,11 @@ static bool is_pmu_set(struct ath_hw *ah
557
558 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
559 {
560 - int internal_regulator =
561 - ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
562 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
563 + struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
564 u32 reg_val;
565
566 - if (internal_regulator) {
567 + if (pBase->featureEnable & BIT(4)) {
568 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
569 int reg_pmu_set;
570
571 @@ -3863,11 +3844,11 @@ void ar9003_hw_internal_regulator_apply(
572 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
573 return;
574 } else if (AR_SREV_9462(ah)) {
575 - reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
576 + reg_val = le32_to_cpu(pBase->swreg);
577 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
578 } else {
579 /* Internal regulator is ON. Write swreg register. */
580 - reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
581 + reg_val = le32_to_cpu(pBase->swreg);
582 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
583 REG_READ(ah, AR_RTC_REG_CONTROL1) &
584 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
585 @@ -3909,6 +3890,9 @@ static void ar9003_hw_apply_tuning_caps(
586 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
587 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
588
589 + if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
590 + return;
591 +
592 if (eep->baseEepHeader.featureEnable & 0x40) {
593 tuning_caps_param &= 0x7f;
594 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
595 @@ -3921,10 +3905,11 @@ static void ar9003_hw_apply_tuning_caps(
596 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
597 {
598 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
599 - int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
600 + struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
601 + int quick_drop;
602 s32 t[3], f[3] = {5180, 5500, 5785};
603
604 - if (!quick_drop)
605 + if (!(pBase->miscConfiguration & BIT(1)))
606 return;
607
608 if (freq < 4000)
609 @@ -3938,13 +3923,11 @@ static void ar9003_hw_quick_drop_apply(s
610 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
611 }
612
613 -static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
614 +static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
615 {
616 - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
617 u32 value;
618
619 - value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
620 - eep->modalHeader5G.txEndToXpaOff;
621 + value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
622
623 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
624 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
625 @@ -3952,19 +3935,63 @@ static void ar9003_hw_txend_to_xpa_off_a
626 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
627 }
628
629 +static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
630 +{
631 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
632 + u8 xpa_ctl;
633 +
634 + if (!(eep->baseEepHeader.featureEnable & 0x80))
635 + return;
636 +
637 + if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
638 + return;
639 +
640 + xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
641 + if (is2ghz)
642 + REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
643 + AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
644 + else
645 + REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
646 + AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
647 +}
648 +
649 +static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
650 +{
651 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
652 + u8 bias;
653 +
654 + if (!(eep->baseEepHeader.featureEnable & 0x40))
655 + return;
656 +
657 + if (!AR_SREV_9300(ah))
658 + return;
659 +
660 + bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
661 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
662 + bias & 0x3);
663 + bias >>= 2;
664 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
665 + bias & 0x3);
666 + bias >>= 2;
667 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
668 + bias & 0x3);
669 +}
670 +
671 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
672 struct ath9k_channel *chan)
673 {
674 - ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
675 - ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
676 + bool is2ghz = IS_CHAN_2GHZ(chan);
677 + ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
678 + ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
679 + ar9003_hw_ant_ctrl_apply(ah, is2ghz);
680 ar9003_hw_drive_strength_apply(ah);
681 + ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
682 ar9003_hw_atten_apply(ah, chan);
683 ar9003_hw_quick_drop_apply(ah, chan->channel);
684 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
685 ar9003_hw_internal_regulator_apply(ah);
686 - if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
687 - ar9003_hw_apply_tuning_caps(ah);
688 - ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
689 + ar9003_hw_apply_tuning_caps(ah);
690 + ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
691 }
692
693 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
694 @@ -5100,14 +5127,9 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath
695 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
696 }
697
698 -u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
699 +u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
700 {
701 - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
702 -
703 - if (is_2ghz)
704 - return eep->modalHeader2G.spurChans;
705 - else
706 - return eep->modalHeader5G.spurChans;
707 + return ar9003_modal_header(ah, is2ghz)->spurChans;
708 }
709
710 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
711 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
712 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
713 @@ -231,7 +231,8 @@ struct ar9300_modal_eep_header {
714 __le32 papdRateMaskHt20;
715 __le32 papdRateMaskHt40;
716 __le16 switchcomspdt;
717 - u8 futureModal[8];
718 + u8 xlna_bias_strength;
719 + u8 futureModal[7];
720 } __packed;
721
722 struct ar9300_cal_data_per_freq_op_loop {
723 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
724 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
725 @@ -44,462 +44,310 @@ static void ar9003_hw_init_mode_regs(str
726 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
727 if (AR_SREV_9330_11(ah)) {
728 /* mac */
729 - INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
730 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
731 - ar9331_1p1_mac_core,
732 - ARRAY_SIZE(ar9331_1p1_mac_core), 2);
733 + ar9331_1p1_mac_core);
734 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
735 - ar9331_1p1_mac_postamble,
736 - ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
737 + ar9331_1p1_mac_postamble);
738
739 /* bb */
740 - INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
741 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
742 - ar9331_1p1_baseband_core,
743 - ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
744 + ar9331_1p1_baseband_core);
745 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
746 - ar9331_1p1_baseband_postamble,
747 - ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
748 + ar9331_1p1_baseband_postamble);
749
750 /* radio */
751 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
752 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
753 - ar9331_1p1_radio_core,
754 - ARRAY_SIZE(ar9331_1p1_radio_core), 2);
755 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
756 + ar9331_1p1_radio_core);
757
758 /* soc */
759 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
760 - ar9331_1p1_soc_preamble,
761 - ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
762 - INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
763 + ar9331_1p1_soc_preamble);
764 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
765 - ar9331_1p1_soc_postamble,
766 - ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
767 + ar9331_1p1_soc_postamble);
768
769 /* rx/tx gain */
770 INIT_INI_ARRAY(&ah->iniModesRxGain,
771 - ar9331_common_rx_gain_1p1,
772 - ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
773 + ar9331_common_rx_gain_1p1);
774 INIT_INI_ARRAY(&ah->iniModesTxGain,
775 - ar9331_modes_lowest_ob_db_tx_gain_1p1,
776 - ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
777 - 5);
778 + ar9331_modes_lowest_ob_db_tx_gain_1p1);
779
780 /* additional clock settings */
781 if (ah->is_clk_25mhz)
782 INIT_INI_ARRAY(&ah->iniAdditional,
783 - ar9331_1p1_xtal_25M,
784 - ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
785 + ar9331_1p1_xtal_25M);
786 else
787 INIT_INI_ARRAY(&ah->iniAdditional,
788 - ar9331_1p1_xtal_40M,
789 - ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
790 + ar9331_1p1_xtal_40M);
791 } else if (AR_SREV_9330_12(ah)) {
792 /* mac */
793 - INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
794 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
795 - ar9331_1p2_mac_core,
796 - ARRAY_SIZE(ar9331_1p2_mac_core), 2);
797 + ar9331_1p2_mac_core);
798 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
799 - ar9331_1p2_mac_postamble,
800 - ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
801 + ar9331_1p2_mac_postamble);
802
803 /* bb */
804 - INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
805 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
806 - ar9331_1p2_baseband_core,
807 - ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
808 + ar9331_1p2_baseband_core);
809 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
810 - ar9331_1p2_baseband_postamble,
811 - ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
812 + ar9331_1p2_baseband_postamble);
813
814 /* radio */
815 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
816 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
817 - ar9331_1p2_radio_core,
818 - ARRAY_SIZE(ar9331_1p2_radio_core), 2);
819 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
820 + ar9331_1p2_radio_core);
821
822 /* soc */
823 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
824 - ar9331_1p2_soc_preamble,
825 - ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
826 - INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
827 + ar9331_1p2_soc_preamble);
828 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
829 - ar9331_1p2_soc_postamble,
830 - ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
831 + ar9331_1p2_soc_postamble);
832
833 /* rx/tx gain */
834 INIT_INI_ARRAY(&ah->iniModesRxGain,
835 - ar9331_common_rx_gain_1p2,
836 - ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
837 + ar9331_common_rx_gain_1p2);
838 INIT_INI_ARRAY(&ah->iniModesTxGain,
839 - ar9331_modes_lowest_ob_db_tx_gain_1p2,
840 - ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
841 - 5);
842 + ar9331_modes_lowest_ob_db_tx_gain_1p2);
843
844 /* additional clock settings */
845 if (ah->is_clk_25mhz)
846 INIT_INI_ARRAY(&ah->iniAdditional,
847 - ar9331_1p2_xtal_25M,
848 - ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
849 + ar9331_1p2_xtal_25M);
850 else
851 INIT_INI_ARRAY(&ah->iniAdditional,
852 - ar9331_1p2_xtal_40M,
853 - ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
854 + ar9331_1p2_xtal_40M);
855 } else if (AR_SREV_9340(ah)) {
856 /* mac */
857 - INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
858 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
859 - ar9340_1p0_mac_core,
860 - ARRAY_SIZE(ar9340_1p0_mac_core), 2);
861 + ar9340_1p0_mac_core);
862 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
863 - ar9340_1p0_mac_postamble,
864 - ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
865 + ar9340_1p0_mac_postamble);
866
867 /* bb */
868 - INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
869 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
870 - ar9340_1p0_baseband_core,
871 - ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
872 + ar9340_1p0_baseband_core);
873 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
874 - ar9340_1p0_baseband_postamble,
875 - ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
876 + ar9340_1p0_baseband_postamble);
877
878 /* radio */
879 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
880 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
881 - ar9340_1p0_radio_core,
882 - ARRAY_SIZE(ar9340_1p0_radio_core), 2);
883 + ar9340_1p0_radio_core);
884 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
885 - ar9340_1p0_radio_postamble,
886 - ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
887 + ar9340_1p0_radio_postamble);
888
889 /* soc */
890 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
891 - ar9340_1p0_soc_preamble,
892 - ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
893 - INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
894 + ar9340_1p0_soc_preamble);
895 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
896 - ar9340_1p0_soc_postamble,
897 - ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
898 + ar9340_1p0_soc_postamble);
899
900 /* rx/tx gain */
901 INIT_INI_ARRAY(&ah->iniModesRxGain,
902 - ar9340Common_wo_xlna_rx_gain_table_1p0,
903 - ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
904 - 5);
905 - INIT_INI_ARRAY(&ah->iniModesTxGain,
906 - ar9340Modes_high_ob_db_tx_gain_table_1p0,
907 - ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
908 - 5);
909 + ar9340Common_wo_xlna_rx_gain_table_1p0);
910 + INIT_INI_ARRAY(&ah->iniModesTxGain,
911 + ar9340Modes_high_ob_db_tx_gain_table_1p0);
912
913 INIT_INI_ARRAY(&ah->iniModesFastClock,
914 - ar9340Modes_fast_clock_1p0,
915 - ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
916 - 3);
917 + ar9340Modes_fast_clock_1p0);
918
919 if (!ah->is_clk_25mhz)
920 INIT_INI_ARRAY(&ah->iniAdditional,
921 - ar9340_1p0_radio_core_40M,
922 - ARRAY_SIZE(ar9340_1p0_radio_core_40M),
923 - 2);
924 + ar9340_1p0_radio_core_40M);
925 } else if (AR_SREV_9485_11(ah)) {
926 /* mac */
927 - INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
928 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
929 - ar9485_1_1_mac_core,
930 - ARRAY_SIZE(ar9485_1_1_mac_core), 2);
931 + ar9485_1_1_mac_core);
932 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
933 - ar9485_1_1_mac_postamble,
934 - ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
935 + ar9485_1_1_mac_postamble);
936
937 /* bb */
938 - INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
939 - ARRAY_SIZE(ar9485_1_1), 2);
940 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
941 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
942 - ar9485_1_1_baseband_core,
943 - ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
944 + ar9485_1_1_baseband_core);
945 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
946 - ar9485_1_1_baseband_postamble,
947 - ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
948 + ar9485_1_1_baseband_postamble);
949
950 /* radio */
951 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
952 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
953 - ar9485_1_1_radio_core,
954 - ARRAY_SIZE(ar9485_1_1_radio_core), 2);
955 + ar9485_1_1_radio_core);
956 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
957 - ar9485_1_1_radio_postamble,
958 - ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
959 + ar9485_1_1_radio_postamble);
960
961 /* soc */
962 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
963 - ar9485_1_1_soc_preamble,
964 - ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
965 - INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
966 - INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
967 + ar9485_1_1_soc_preamble);
968
969 /* rx/tx gain */
970 INIT_INI_ARRAY(&ah->iniModesRxGain,
971 - ar9485Common_wo_xlna_rx_gain_1_1,
972 - ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
973 + ar9485Common_wo_xlna_rx_gain_1_1);
974 INIT_INI_ARRAY(&ah->iniModesTxGain,
975 - ar9485_modes_lowest_ob_db_tx_gain_1_1,
976 - ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
977 - 5);
978 + ar9485_modes_lowest_ob_db_tx_gain_1_1);
979
980 /* Load PCIE SERDES settings from INI */
981
982 /* Awake Setting */
983
984 INIT_INI_ARRAY(&ah->iniPcieSerdes,
985 - ar9485_1_1_pcie_phy_clkreq_disable_L1,
986 - ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
987 - 2);
988 + ar9485_1_1_pcie_phy_clkreq_disable_L1);
989
990 /* Sleep Setting */
991
992 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
993 - ar9485_1_1_pcie_phy_clkreq_disable_L1,
994 - ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
995 - 2);
996 + ar9485_1_1_pcie_phy_clkreq_disable_L1);
997 } else if (AR_SREV_9462_20(ah)) {
998
999 - INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
1000 - INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
1001 - ARRAY_SIZE(ar9462_2p0_mac_core), 2);
1002 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
1003 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
1004 - ar9462_2p0_mac_postamble,
1005 - ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
1006 + ar9462_2p0_mac_postamble);
1007
1008 - INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
1009 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
1010 - ar9462_2p0_baseband_core,
1011 - ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
1012 + ar9462_2p0_baseband_core);
1013 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
1014 - ar9462_2p0_baseband_postamble,
1015 - ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
1016 + ar9462_2p0_baseband_postamble);
1017
1018 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
1019 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
1020 - ar9462_2p0_radio_core,
1021 - ARRAY_SIZE(ar9462_2p0_radio_core), 2);
1022 + ar9462_2p0_radio_core);
1023 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
1024 - ar9462_2p0_radio_postamble,
1025 - ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
1026 + ar9462_2p0_radio_postamble);
1027 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
1028 - ar9462_2p0_radio_postamble_sys2ant,
1029 - ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
1030 - 5);
1031 + ar9462_2p0_radio_postamble_sys2ant);
1032
1033 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
1034 - ar9462_2p0_soc_preamble,
1035 - ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
1036 - INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
1037 + ar9462_2p0_soc_preamble);
1038 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
1039 - ar9462_2p0_soc_postamble,
1040 - ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
1041 + ar9462_2p0_soc_postamble);
1042
1043 INIT_INI_ARRAY(&ah->iniModesRxGain,
1044 - ar9462_common_rx_gain_table_2p0,
1045 - ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
1046 + ar9462_common_rx_gain_table_2p0);
1047
1048 /* Awake -> Sleep Setting */
1049 INIT_INI_ARRAY(&ah->iniPcieSerdes,
1050 - PCIE_PLL_ON_CREQ_DIS_L1_2P0,
1051 - ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
1052 - 2);
1053 + PCIE_PLL_ON_CREQ_DIS_L1_2P0);
1054 /* Sleep -> Awake Setting */
1055 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
1056 - PCIE_PLL_ON_CREQ_DIS_L1_2P0,
1057 - ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
1058 - 2);
1059 + PCIE_PLL_ON_CREQ_DIS_L1_2P0);
1060
1061 /* Fast clock modal settings */
1062 INIT_INI_ARRAY(&ah->iniModesFastClock,
1063 - ar9462_modes_fast_clock_2p0,
1064 - ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
1065 + ar9462_modes_fast_clock_2p0);
1066
1067 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
1068 - AR9462_BB_CTX_COEFJ(2p0),
1069 - ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
1070 + AR9462_BB_CTX_COEFJ(2p0));
1071
1072 - INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
1073 - ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
1074 + INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
1075 } else if (AR_SREV_9550(ah)) {
1076 /* mac */
1077 - INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
1078 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
1079 - ar955x_1p0_mac_core,
1080 - ARRAY_SIZE(ar955x_1p0_mac_core), 2);
1081 + ar955x_1p0_mac_core);
1082 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
1083 - ar955x_1p0_mac_postamble,
1084 - ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
1085 + ar955x_1p0_mac_postamble);
1086
1087 /* bb */
1088 - INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
1089 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
1090 - ar955x_1p0_baseband_core,
1091 - ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
1092 + ar955x_1p0_baseband_core);
1093 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
1094 - ar955x_1p0_baseband_postamble,
1095 - ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
1096 + ar955x_1p0_baseband_postamble);
1097
1098 /* radio */
1099 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
1100 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
1101 - ar955x_1p0_radio_core,
1102 - ARRAY_SIZE(ar955x_1p0_radio_core), 2);
1103 + ar955x_1p0_radio_core);
1104 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
1105 - ar955x_1p0_radio_postamble,
1106 - ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
1107 + ar955x_1p0_radio_postamble);
1108
1109 /* soc */
1110 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
1111 - ar955x_1p0_soc_preamble,
1112 - ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
1113 - INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
1114 + ar955x_1p0_soc_preamble);
1115 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
1116 - ar955x_1p0_soc_postamble,
1117 - ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
1118 + ar955x_1p0_soc_postamble);
1119
1120 /* rx/tx gain */
1121 INIT_INI_ARRAY(&ah->iniModesRxGain,
1122 - ar955x_1p0_common_wo_xlna_rx_gain_table,
1123 - ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
1124 - 2);
1125 + ar955x_1p0_common_wo_xlna_rx_gain_table);
1126 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
1127 - ar955x_1p0_common_wo_xlna_rx_gain_bounds,
1128 - ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
1129 - 5);
1130 - INIT_INI_ARRAY(&ah->iniModesTxGain,
1131 - ar955x_1p0_modes_xpa_tx_gain_table,
1132 - ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
1133 - 9);
1134 + ar955x_1p0_common_wo_xlna_rx_gain_bounds);
1135 + INIT_INI_ARRAY(&ah->iniModesTxGain,
1136 + ar955x_1p0_modes_xpa_tx_gain_table);
1137
1138 /* Fast clock modal settings */
1139 INIT_INI_ARRAY(&ah->iniModesFastClock,
1140 - ar955x_1p0_modes_fast_clock,
1141 - ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
1142 + ar955x_1p0_modes_fast_clock);
1143 } else if (AR_SREV_9580(ah)) {
1144 /* mac */
1145 - INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
1146 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
1147 - ar9580_1p0_mac_core,
1148 - ARRAY_SIZE(ar9580_1p0_mac_core), 2);
1149 + ar9580_1p0_mac_core);
1150 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
1151 - ar9580_1p0_mac_postamble,
1152 - ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
1153 + ar9580_1p0_mac_postamble);
1154
1155 /* bb */
1156 - INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
1157 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
1158 - ar9580_1p0_baseband_core,
1159 - ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
1160 + ar9580_1p0_baseband_core);
1161 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
1162 - ar9580_1p0_baseband_postamble,
1163 - ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
1164 + ar9580_1p0_baseband_postamble);
1165
1166 /* radio */
1167 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
1168 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
1169 - ar9580_1p0_radio_core,
1170 - ARRAY_SIZE(ar9580_1p0_radio_core), 2);
1171 + ar9580_1p0_radio_core);
1172 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
1173 - ar9580_1p0_radio_postamble,
1174 - ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
1175 + ar9580_1p0_radio_postamble);
1176
1177 /* soc */
1178 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
1179 - ar9580_1p0_soc_preamble,
1180 - ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
1181 - INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
1182 + ar9580_1p0_soc_preamble);
1183 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
1184 - ar9580_1p0_soc_postamble,
1185 - ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
1186 + ar9580_1p0_soc_postamble);
1187
1188 /* rx/tx gain */
1189 INIT_INI_ARRAY(&ah->iniModesRxGain,
1190 - ar9580_1p0_rx_gain_table,
1191 - ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
1192 + ar9580_1p0_rx_gain_table);
1193 INIT_INI_ARRAY(&ah->iniModesTxGain,
1194 - ar9580_1p0_low_ob_db_tx_gain_table,
1195 - ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
1196 - 5);
1197 + ar9580_1p0_low_ob_db_tx_gain_table);
1198
1199 INIT_INI_ARRAY(&ah->iniModesFastClock,
1200 - ar9580_1p0_modes_fast_clock,
1201 - ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
1202 - 3);
1203 + ar9580_1p0_modes_fast_clock);
1204 } else {
1205 /* mac */
1206 - INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
1207 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
1208 - ar9300_2p2_mac_core,
1209 - ARRAY_SIZE(ar9300_2p2_mac_core), 2);
1210 + ar9300_2p2_mac_core);
1211 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
1212 - ar9300_2p2_mac_postamble,
1213 - ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
1214 + ar9300_2p2_mac_postamble);
1215
1216 /* bb */
1217 - INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
1218 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
1219 - ar9300_2p2_baseband_core,
1220 - ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
1221 + ar9300_2p2_baseband_core);
1222 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
1223 - ar9300_2p2_baseband_postamble,
1224 - ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
1225 + ar9300_2p2_baseband_postamble);
1226
1227 /* radio */
1228 - INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
1229 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
1230 - ar9300_2p2_radio_core,
1231 - ARRAY_SIZE(ar9300_2p2_radio_core), 2);
1232 + ar9300_2p2_radio_core);
1233 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
1234 - ar9300_2p2_radio_postamble,
1235 - ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
1236 + ar9300_2p2_radio_postamble);
1237
1238 /* soc */
1239 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
1240 - ar9300_2p2_soc_preamble,
1241 - ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
1242 - INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
1243 + ar9300_2p2_soc_preamble);
1244 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
1245 - ar9300_2p2_soc_postamble,
1246 - ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
1247 + ar9300_2p2_soc_postamble);
1248
1249 /* rx/tx gain */
1250 INIT_INI_ARRAY(&ah->iniModesRxGain,
1251 - ar9300Common_rx_gain_table_2p2,
1252 - ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
1253 + ar9300Common_rx_gain_table_2p2);
1254 INIT_INI_ARRAY(&ah->iniModesTxGain,
1255 - ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
1256 - ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
1257 - 5);
1258 + ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
1259
1260 /* Load PCIE SERDES settings from INI */
1261
1262 /* Awake Setting */
1263
1264 INIT_INI_ARRAY(&ah->iniPcieSerdes,
1265 - ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
1266 - ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
1267 - 2);
1268 + ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
1269
1270 /* Sleep Setting */
1271
1272 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
1273 - ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
1274 - ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
1275 - 2);
1276 + ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
1277
1278 /* Fast clock modal settings */
1279 INIT_INI_ARRAY(&ah->iniModesFastClock,
1280 - ar9300Modes_fast_clock_2p2,
1281 - ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
1282 - 3);
1283 + ar9300Modes_fast_clock_2p2);
1284 }
1285 }
1286
1287 @@ -507,156 +355,110 @@ static void ar9003_tx_gain_table_mode0(s
1288 {
1289 if (AR_SREV_9330_12(ah))
1290 INIT_INI_ARRAY(&ah->iniModesTxGain,
1291 - ar9331_modes_lowest_ob_db_tx_gain_1p2,
1292 - ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
1293 - 5);
1294 + ar9331_modes_lowest_ob_db_tx_gain_1p2);
1295 else if (AR_SREV_9330_11(ah))
1296 INIT_INI_ARRAY(&ah->iniModesTxGain,
1297 - ar9331_modes_lowest_ob_db_tx_gain_1p1,
1298 - ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
1299 - 5);
1300 + ar9331_modes_lowest_ob_db_tx_gain_1p1);
1301 else if (AR_SREV_9340(ah))
1302 INIT_INI_ARRAY(&ah->iniModesTxGain,
1303 - ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
1304 - ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
1305 - 5);
1306 + ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
1307 else if (AR_SREV_9485_11(ah))
1308 INIT_INI_ARRAY(&ah->iniModesTxGain,
1309 - ar9485_modes_lowest_ob_db_tx_gain_1_1,
1310 - ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
1311 - 5);
1312 + ar9485_modes_lowest_ob_db_tx_gain_1_1);
1313 else if (AR_SREV_9550(ah))
1314 INIT_INI_ARRAY(&ah->iniModesTxGain,
1315 - ar955x_1p0_modes_xpa_tx_gain_table,
1316 - ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
1317 - 9);
1318 + ar955x_1p0_modes_xpa_tx_gain_table);
1319 else if (AR_SREV_9580(ah))
1320 INIT_INI_ARRAY(&ah->iniModesTxGain,
1321 - ar9580_1p0_lowest_ob_db_tx_gain_table,
1322 - ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
1323 - 5);
1324 + ar9580_1p0_lowest_ob_db_tx_gain_table);
1325 else if (AR_SREV_9462_20(ah))
1326 INIT_INI_ARRAY(&ah->iniModesTxGain,
1327 - ar9462_modes_low_ob_db_tx_gain_table_2p0,
1328 - ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
1329 - 5);
1330 + ar9462_modes_low_ob_db_tx_gain_table_2p0);
1331 else
1332 INIT_INI_ARRAY(&ah->iniModesTxGain,
1333 - ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
1334 - ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
1335 - 5);
1336 + ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
1337 }
1338
1339 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
1340 {
1341 if (AR_SREV_9330_12(ah))
1342 INIT_INI_ARRAY(&ah->iniModesTxGain,
1343 - ar9331_modes_high_ob_db_tx_gain_1p2,
1344 - ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
1345 - 5);
1346 + ar9331_modes_high_ob_db_tx_gain_1p2);
1347 else if (AR_SREV_9330_11(ah))
1348 INIT_INI_ARRAY(&ah->iniModesTxGain,
1349 - ar9331_modes_high_ob_db_tx_gain_1p1,
1350 - ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
1351 - 5);
1352 + ar9331_modes_high_ob_db_tx_gain_1p1);
1353 else if (AR_SREV_9340(ah))
1354 INIT_INI_ARRAY(&ah->iniModesTxGain,
1355 - ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
1356 - ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
1357 - 5);
1358 + ar9340Modes_high_ob_db_tx_gain_table_1p0);
1359 else if (AR_SREV_9485_11(ah))
1360 INIT_INI_ARRAY(&ah->iniModesTxGain,
1361 - ar9485Modes_high_ob_db_tx_gain_1_1,
1362 - ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
1363 - 5);
1364 + ar9485Modes_high_ob_db_tx_gain_1_1);
1365 else if (AR_SREV_9580(ah))
1366 INIT_INI_ARRAY(&ah->iniModesTxGain,
1367 - ar9580_1p0_high_ob_db_tx_gain_table,
1368 - ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
1369 - 5);
1370 + ar9580_1p0_high_ob_db_tx_gain_table);
1371 else if (AR_SREV_9550(ah))
1372 INIT_INI_ARRAY(&ah->iniModesTxGain,
1373 - ar955x_1p0_modes_no_xpa_tx_gain_table,
1374 - ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
1375 - 9);
1376 + ar955x_1p0_modes_no_xpa_tx_gain_table);
1377 else if (AR_SREV_9462_20(ah))
1378 INIT_INI_ARRAY(&ah->iniModesTxGain,
1379 - ar9462_modes_high_ob_db_tx_gain_table_2p0,
1380 - ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
1381 - 5);
1382 + ar9462_modes_high_ob_db_tx_gain_table_2p0);
1383 else
1384 INIT_INI_ARRAY(&ah->iniModesTxGain,
1385 - ar9300Modes_high_ob_db_tx_gain_table_2p2,
1386 - ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
1387 - 5);
1388 + ar9300Modes_high_ob_db_tx_gain_table_2p2);
1389 }
1390
1391 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
1392 {
1393 if (AR_SREV_9330_12(ah))
1394 INIT_INI_ARRAY(&ah->iniModesTxGain,
1395 - ar9331_modes_low_ob_db_tx_gain_1p2,
1396 - ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
1397 - 5);
1398 + ar9331_modes_low_ob_db_tx_gain_1p2);
1399 else if (AR_SREV_9330_11(ah))
1400 INIT_INI_ARRAY(&ah->iniModesTxGain,
1401 - ar9331_modes_low_ob_db_tx_gain_1p1,
1402 - ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
1403 - 5);
1404 + ar9331_modes_low_ob_db_tx_gain_1p1);
1405 else if (AR_SREV_9340(ah))
1406 INIT_INI_ARRAY(&ah->iniModesTxGain,
1407 - ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
1408 - ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
1409 - 5);
1410 + ar9340Modes_low_ob_db_tx_gain_table_1p0);
1411 else if (AR_SREV_9485_11(ah))
1412 INIT_INI_ARRAY(&ah->iniModesTxGain,
1413 - ar9485Modes_low_ob_db_tx_gain_1_1,
1414 - ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
1415 - 5);
1416 + ar9485Modes_low_ob_db_tx_gain_1_1);
1417 else if (AR_SREV_9580(ah))
1418 INIT_INI_ARRAY(&ah->iniModesTxGain,
1419 - ar9580_1p0_low_ob_db_tx_gain_table,
1420 - ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
1421 - 5);
1422 + ar9580_1p0_low_ob_db_tx_gain_table);
1423 else
1424 INIT_INI_ARRAY(&ah->iniModesTxGain,
1425 - ar9300Modes_low_ob_db_tx_gain_table_2p2,
1426 - ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
1427 - 5);
1428 + ar9300Modes_low_ob_db_tx_gain_table_2p2);
1429 }
1430
1431 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
1432 {
1433 if (AR_SREV_9330_12(ah))
1434 INIT_INI_ARRAY(&ah->iniModesTxGain,
1435 - ar9331_modes_high_power_tx_gain_1p2,
1436 - ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
1437 - 5);
1438 + ar9331_modes_high_power_tx_gain_1p2);
1439 else if (AR_SREV_9330_11(ah))
1440 INIT_INI_ARRAY(&ah->iniModesTxGain,
1441 - ar9331_modes_high_power_tx_gain_1p1,
1442 - ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
1443 - 5);
1444 + ar9331_modes_high_power_tx_gain_1p1);
1445 else if (AR_SREV_9340(ah))
1446 INIT_INI_ARRAY(&ah->iniModesTxGain,
1447 - ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
1448 - ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
1449 - 5);
1450 + ar9340Modes_high_power_tx_gain_table_1p0);
1451 else if (AR_SREV_9485_11(ah))
1452 INIT_INI_ARRAY(&ah->iniModesTxGain,
1453 - ar9485Modes_high_power_tx_gain_1_1,
1454 - ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
1455 - 5);
1456 + ar9485Modes_high_power_tx_gain_1_1);
1457 else if (AR_SREV_9580(ah))
1458 INIT_INI_ARRAY(&ah->iniModesTxGain,
1459 - ar9580_1p0_high_power_tx_gain_table,
1460 - ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
1461 - 5);
1462 + ar9580_1p0_high_power_tx_gain_table);
1463 else
1464 INIT_INI_ARRAY(&ah->iniModesTxGain,
1465 - ar9300Modes_high_power_tx_gain_table_2p2,
1466 - ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
1467 - 5);
1468 + ar9300Modes_high_power_tx_gain_table_2p2);
1469 +}
1470 +
1471 +static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
1472 +{
1473 + if (AR_SREV_9340(ah))
1474 + INIT_INI_ARRAY(&ah->iniModesTxGain,
1475 + ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
1476 + else if (AR_SREV_9580(ah))
1477 + INIT_INI_ARRAY(&ah->iniModesTxGain,
1478 + ar9580_1p0_mixed_ob_db_tx_gain_table);
1479 }
1480
1481 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
1482 @@ -675,6 +477,9 @@ static void ar9003_tx_gain_table_apply(s
1483 case 3:
1484 ar9003_tx_gain_table_mode3(ah);
1485 break;
1486 + case 4:
1487 + ar9003_tx_gain_table_mode4(ah);
1488 + break;
1489 }
1490 }
1491
1492 @@ -682,104 +487,67 @@ static void ar9003_rx_gain_table_mode0(s
1493 {
1494 if (AR_SREV_9330_12(ah))
1495 INIT_INI_ARRAY(&ah->iniModesRxGain,
1496 - ar9331_common_rx_gain_1p2,
1497 - ARRAY_SIZE(ar9331_common_rx_gain_1p2),
1498 - 2);
1499 + ar9331_common_rx_gain_1p2);
1500 else if (AR_SREV_9330_11(ah))
1501 INIT_INI_ARRAY(&ah->iniModesRxGain,
1502 - ar9331_common_rx_gain_1p1,
1503 - ARRAY_SIZE(ar9331_common_rx_gain_1p1),
1504 - 2);
1505 + ar9331_common_rx_gain_1p1);
1506 else if (AR_SREV_9340(ah))
1507 INIT_INI_ARRAY(&ah->iniModesRxGain,
1508 - ar9340Common_rx_gain_table_1p0,
1509 - ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
1510 - 2);
1511 + ar9340Common_rx_gain_table_1p0);
1512 else if (AR_SREV_9485_11(ah))
1513 INIT_INI_ARRAY(&ah->iniModesRxGain,
1514 - ar9485Common_wo_xlna_rx_gain_1_1,
1515 - ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
1516 - 2);
1517 + ar9485Common_wo_xlna_rx_gain_1_1);
1518 else if (AR_SREV_9550(ah)) {
1519 INIT_INI_ARRAY(&ah->iniModesRxGain,
1520 - ar955x_1p0_common_rx_gain_table,
1521 - ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
1522 - 2);
1523 + ar955x_1p0_common_rx_gain_table);
1524 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
1525 - ar955x_1p0_common_rx_gain_bounds,
1526 - ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
1527 - 5);
1528 + ar955x_1p0_common_rx_gain_bounds);
1529 } else if (AR_SREV_9580(ah))
1530 INIT_INI_ARRAY(&ah->iniModesRxGain,
1531 - ar9580_1p0_rx_gain_table,
1532 - ARRAY_SIZE(ar9580_1p0_rx_gain_table),
1533 - 2);
1534 + ar9580_1p0_rx_gain_table);
1535 else if (AR_SREV_9462_20(ah))
1536 INIT_INI_ARRAY(&ah->iniModesRxGain,
1537 - ar9462_common_rx_gain_table_2p0,
1538 - ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
1539 - 2);
1540 + ar9462_common_rx_gain_table_2p0);
1541 else
1542 INIT_INI_ARRAY(&ah->iniModesRxGain,
1543 - ar9300Common_rx_gain_table_2p2,
1544 - ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
1545 - 2);
1546 + ar9300Common_rx_gain_table_2p2);
1547 }
1548
1549 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
1550 {
1551 if (AR_SREV_9330_12(ah))
1552 INIT_INI_ARRAY(&ah->iniModesRxGain,
1553 - ar9331_common_wo_xlna_rx_gain_1p2,
1554 - ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
1555 - 2);
1556 + ar9331_common_wo_xlna_rx_gain_1p2);
1557 else if (AR_SREV_9330_11(ah))
1558 INIT_INI_ARRAY(&ah->iniModesRxGain,
1559 - ar9331_common_wo_xlna_rx_gain_1p1,
1560 - ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
1561 - 2);
1562 + ar9331_common_wo_xlna_rx_gain_1p1);
1563 else if (AR_SREV_9340(ah))
1564 INIT_INI_ARRAY(&ah->iniModesRxGain,
1565 - ar9340Common_wo_xlna_rx_gain_table_1p0,
1566 - ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
1567 - 2);
1568 + ar9340Common_wo_xlna_rx_gain_table_1p0);
1569 else if (AR_SREV_9485_11(ah))
1570 INIT_INI_ARRAY(&ah->iniModesRxGain,
1571 - ar9485Common_wo_xlna_rx_gain_1_1,
1572 - ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
1573 - 2);
1574 + ar9485Common_wo_xlna_rx_gain_1_1);
1575 else if (AR_SREV_9462_20(ah))
1576 INIT_INI_ARRAY(&ah->iniModesRxGain,
1577 - ar9462_common_wo_xlna_rx_gain_table_2p0,
1578 - ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
1579 - 2);
1580 + ar9462_common_wo_xlna_rx_gain_table_2p0);
1581 else if (AR_SREV_9550(ah)) {
1582 INIT_INI_ARRAY(&ah->iniModesRxGain,
1583 - ar955x_1p0_common_wo_xlna_rx_gain_table,
1584 - ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
1585 - 2);
1586 + ar955x_1p0_common_wo_xlna_rx_gain_table);
1587 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
1588 - ar955x_1p0_common_wo_xlna_rx_gain_bounds,
1589 - ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
1590 - 5);
1591 + ar955x_1p0_common_wo_xlna_rx_gain_bounds);
1592 } else if (AR_SREV_9580(ah))
1593 INIT_INI_ARRAY(&ah->iniModesRxGain,
1594 - ar9580_1p0_wo_xlna_rx_gain_table,
1595 - ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
1596 - 2);
1597 + ar9580_1p0_wo_xlna_rx_gain_table);
1598 else
1599 INIT_INI_ARRAY(&ah->iniModesRxGain,
1600 - ar9300Common_wo_xlna_rx_gain_table_2p2,
1601 - ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
1602 - 2);
1603 + ar9300Common_wo_xlna_rx_gain_table_2p2);
1604 }
1605
1606 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
1607 {
1608 if (AR_SREV_9462_20(ah))
1609 INIT_INI_ARRAY(&ah->iniModesRxGain,
1610 - ar9462_common_mixed_rx_gain_table_2p0,
1611 - ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
1612 + ar9462_common_mixed_rx_gain_table_2p0);
1613 }
1614
1615 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
1616 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
1617 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
1618 @@ -117,8 +117,8 @@ static int ar9003_hw_set_channel(struct
1619 ah->is_clk_25mhz) {
1620 u32 chan_frac;
1621
1622 - channelSel = (freq * 2) / 75;
1623 - chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
1624 + channelSel = freq / 75;
1625 + chan_frac = ((freq % 75) * 0x20000) / 75;
1626 channelSel = (channelSel << 17) | chan_frac;
1627 } else {
1628 channelSel = CHANSEL_5G(freq);
1629 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
1630 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
1631 @@ -625,6 +625,10 @@
1632 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
1633 #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
1634
1635 +#define AR_PHY_65NM_CH0_TXRF3 0x16048
1636 +#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001e
1637 +#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1
1638 +
1639 #define AR_PHY_65NM_CH0_SYNTH4 0x1608c
1640 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT (AR_SREV_9462(ah) ? 0x00000001 : 0x00000002)
1641 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S (AR_SREV_9462(ah) ? 0 : 1)
1642 @@ -633,6 +637,8 @@
1643 #define AR_PHY_65NM_CH0_BIAS2 0x160c4
1644 #define AR_PHY_65NM_CH0_BIAS4 0x160cc
1645 #define AR_PHY_65NM_CH0_RXTX4 0x1610c
1646 +#define AR_PHY_65NM_CH1_RXTX4 0x1650c
1647 +#define AR_PHY_65NM_CH2_RXTX4 0x1690c
1648
1649 #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
1650 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
1651 @@ -876,6 +882,9 @@
1652 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
1653 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
1654
1655 +#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
1656 +#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30
1657 +
1658 /*
1659 * Channel 1 Register Map
1660 */
1661 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
1662 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
1663 @@ -297,6 +297,8 @@ struct ath_tx {
1664 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
1665 struct ath_descdma txdma;
1666 struct ath_txq *txq_map[WME_NUM_AC];
1667 + u32 txq_max_pending[WME_NUM_AC];
1668 + u16 max_aggr_framelen[WME_NUM_AC][4][32];
1669 };
1670
1671 struct ath_rx_edma {
1672 @@ -341,6 +343,7 @@ int ath_tx_init(struct ath_softc *sc, in
1673 void ath_tx_cleanup(struct ath_softc *sc);
1674 int ath_txq_update(struct ath_softc *sc, int qnum,
1675 struct ath9k_tx_queue_info *q);
1676 +void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
1677 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1678 struct ath_tx_control *txctl);
1679 void ath_tx_tasklet(struct ath_softc *sc);
1680 @@ -360,7 +363,7 @@ void ath_tx_aggr_sleep(struct ieee80211_
1681
1682 struct ath_vif {
1683 int av_bslot;
1684 - bool is_bslot_active, primary_sta_vif;
1685 + bool primary_sta_vif;
1686 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
1687 struct ath_buf *av_bcbuf;
1688 };
1689 @@ -386,6 +389,7 @@ struct ath_beacon_config {
1690 u16 dtim_period;
1691 u16 bmiss_timeout;
1692 u8 dtim_count;
1693 + bool enable_beacon;
1694 };
1695
1696 struct ath_beacon {
1697 @@ -397,7 +401,6 @@ struct ath_beacon {
1698
1699 u32 beaconq;
1700 u32 bmisscnt;
1701 - u32 ast_be_xmit;
1702 u32 bc_tstamp;
1703 struct ieee80211_vif *bslot[ATH_BCBUF];
1704 int slottime;
1705 @@ -411,12 +414,14 @@ struct ath_beacon {
1706 bool tx_last;
1707 };
1708
1709 -void ath_beacon_tasklet(unsigned long data);
1710 -void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
1711 -int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
1712 -void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
1713 -int ath_beaconq_config(struct ath_softc *sc);
1714 -void ath_set_beacon(struct ath_softc *sc);
1715 +void ath9k_beacon_tasklet(unsigned long data);
1716 +bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
1717 +void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
1718 + u32 changed);
1719 +void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
1720 +void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
1721 +void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
1722 +void ath9k_set_beacon(struct ath_softc *sc);
1723 void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
1724
1725 /*******************/
1726 @@ -442,9 +447,12 @@ void ath_rx_poll(unsigned long data);
1727 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
1728 void ath_paprd_calibrate(struct work_struct *work);
1729 void ath_ani_calibrate(unsigned long data);
1730 -void ath_start_ani(struct ath_common *common);
1731 +void ath_start_ani(struct ath_softc *sc);
1732 +void ath_stop_ani(struct ath_softc *sc);
1733 +void ath_check_ani(struct ath_softc *sc);
1734 int ath_update_survey_stats(struct ath_softc *sc);
1735 void ath_update_survey_nf(struct ath_softc *sc, int channel);
1736 +void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
1737
1738 /**********/
1739 /* BTCOEX */
1740 @@ -619,7 +627,6 @@ enum sc_op_flags {
1741 SC_OP_INVALID,
1742 SC_OP_BEACONS,
1743 SC_OP_RXFLUSH,
1744 - SC_OP_TSF_RESET,
1745 SC_OP_ANI_RUN,
1746 SC_OP_PRIM_STA_VIF,
1747 SC_OP_HW_RESET,
1748 --- a/drivers/net/wireless/ath/ath9k/beacon.c
1749 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
1750 @@ -30,7 +30,7 @@ static void ath9k_reset_beacon_status(st
1751 * the operating mode of the station (AP or AdHoc). Parameters are AIFS
1752 * settings and channel width min/max
1753 */
1754 -int ath_beaconq_config(struct ath_softc *sc)
1755 +static void ath9k_beaconq_config(struct ath_softc *sc)
1756 {
1757 struct ath_hw *ah = sc->sc_ah;
1758 struct ath_common *common = ath9k_hw_common(ah);
1759 @@ -38,6 +38,7 @@ int ath_beaconq_config(struct ath_softc
1760 struct ath_txq *txq;
1761
1762 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
1763 +
1764 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
1765 /* Always burst out beacon and CAB traffic. */
1766 qi.tqi_aifs = 1;
1767 @@ -56,12 +57,9 @@ int ath_beaconq_config(struct ath_softc
1768 }
1769
1770 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
1771 - ath_err(common,
1772 - "Unable to update h/w beacon queue parameters\n");
1773 - return 0;
1774 + ath_err(common, "Unable to update h/w beacon queue parameters\n");
1775 } else {
1776 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
1777 - return 1;
1778 }
1779 }
1780
1781 @@ -70,7 +68,7 @@ int ath_beaconq_config(struct ath_softc
1782 * up rate codes, and channel flags. Beacons are always sent out at the
1783 * lowest rate, and are not retried.
1784 */
1785 -static void ath_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
1786 +static void ath9k_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
1787 struct ath_buf *bf, int rateidx)
1788 {
1789 struct sk_buff *skb = bf->bf_mpdu;
1790 @@ -81,8 +79,6 @@ static void ath_beacon_setup(struct ath_
1791 u8 chainmask = ah->txchainmask;
1792 u8 rate = 0;
1793
1794 - ath9k_reset_beacon_status(sc);
1795 -
1796 sband = &sc->sbands[common->hw->conf.channel->band];
1797 rate = sband->bitrates[rateidx].hw_value;
1798 if (vif->bss_conf.use_short_preamble)
1799 @@ -111,7 +107,7 @@ static void ath_beacon_setup(struct ath_
1800 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1801 }
1802
1803 -static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1804 +static void ath9k_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1805 {
1806 struct ath_softc *sc = hw->priv;
1807 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1808 @@ -128,28 +124,22 @@ static void ath_tx_cabq(struct ieee80211
1809 }
1810 }
1811
1812 -static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
1813 - struct ieee80211_vif *vif)
1814 +static struct ath_buf *ath9k_beacon_generate(struct ieee80211_hw *hw,
1815 + struct ieee80211_vif *vif)
1816 {
1817 struct ath_softc *sc = hw->priv;
1818 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1819 struct ath_buf *bf;
1820 - struct ath_vif *avp;
1821 + struct ath_vif *avp = (void *)vif->drv_priv;
1822 struct sk_buff *skb;
1823 - struct ath_txq *cabq;
1824 + struct ath_txq *cabq = sc->beacon.cabq;
1825 struct ieee80211_tx_info *info;
1826 + struct ieee80211_mgmt *mgmt_hdr;
1827 int cabq_depth;
1828
1829 - ath9k_reset_beacon_status(sc);
1830 -
1831 - avp = (void *)vif->drv_priv;
1832 - cabq = sc->beacon.cabq;
1833 -
1834 - if ((avp->av_bcbuf == NULL) || !avp->is_bslot_active)
1835 + if (avp->av_bcbuf == NULL)
1836 return NULL;
1837
1838 - /* Release the old beacon first */
1839 -
1840 bf = avp->av_bcbuf;
1841 skb = bf->bf_mpdu;
1842 if (skb) {
1843 @@ -159,14 +149,14 @@ static struct ath_buf *ath_beacon_genera
1844 bf->bf_buf_addr = 0;
1845 }
1846
1847 - /* Get a new beacon from mac80211 */
1848 -
1849 skb = ieee80211_beacon_get(hw, vif);
1850 - bf->bf_mpdu = skb;
1851 if (skb == NULL)
1852 return NULL;
1853 - ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
1854 - avp->tsf_adjust;
1855 +
1856 + bf->bf_mpdu = skb;
1857 +
1858 + mgmt_hdr = (struct ieee80211_mgmt *)skb->data;
1859 + mgmt_hdr->u.beacon.timestamp = avp->tsf_adjust;
1860
1861 info = IEEE80211_SKB_CB(skb);
1862 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1863 @@ -212,61 +202,52 @@ static struct ath_buf *ath_beacon_genera
1864 }
1865 }
1866
1867 - ath_beacon_setup(sc, vif, bf, info->control.rates[0].idx);
1868 + ath9k_beacon_setup(sc, vif, bf, info->control.rates[0].idx);
1869
1870 while (skb) {
1871 - ath_tx_cabq(hw, skb);
1872 + ath9k_tx_cabq(hw, skb);
1873 skb = ieee80211_get_buffered_bc(hw, vif);
1874 }
1875
1876 return bf;
1877 }
1878
1879 -int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif)
1880 +void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif)
1881 {
1882 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1883 - struct ath_vif *avp;
1884 - struct ath_buf *bf;
1885 - struct sk_buff *skb;
1886 - struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1887 - __le64 tstamp;
1888 + struct ath_vif *avp = (void *)vif->drv_priv;
1889 + int slot;
1890
1891 - avp = (void *)vif->drv_priv;
1892 + avp->av_bcbuf = list_first_entry(&sc->beacon.bbuf, struct ath_buf, list);
1893 + list_del(&avp->av_bcbuf->list);
1894
1895 - /* Allocate a beacon descriptor if we haven't done so. */
1896 - if (!avp->av_bcbuf) {
1897 - /* Allocate beacon state for hostap/ibss. We know
1898 - * a buffer is available. */
1899 - avp->av_bcbuf = list_first_entry(&sc->beacon.bbuf,
1900 - struct ath_buf, list);
1901 - list_del(&avp->av_bcbuf->list);
1902 -
1903 - if (ath9k_uses_beacons(vif->type)) {
1904 - int slot;
1905 - /*
1906 - * Assign the vif to a beacon xmit slot. As
1907 - * above, this cannot fail to find one.
1908 - */
1909 - avp->av_bslot = 0;
1910 - for (slot = 0; slot < ATH_BCBUF; slot++)
1911 - if (sc->beacon.bslot[slot] == NULL) {
1912 - avp->av_bslot = slot;
1913 - avp->is_bslot_active = false;
1914 -
1915 - /* NB: keep looking for a double slot */
1916 - if (slot == 0 || !sc->beacon.bslot[slot-1])
1917 - break;
1918 - }
1919 - BUG_ON(sc->beacon.bslot[avp->av_bslot] != NULL);
1920 - sc->beacon.bslot[avp->av_bslot] = vif;
1921 - sc->nbcnvifs++;
1922 + for (slot = 0; slot < ATH_BCBUF; slot++) {
1923 + if (sc->beacon.bslot[slot] == NULL) {
1924 + avp->av_bslot = slot;
1925 + break;
1926 }
1927 }
1928
1929 - /* release the previous beacon frame, if it already exists. */
1930 - bf = avp->av_bcbuf;
1931 - if (bf->bf_mpdu != NULL) {
1932 - skb = bf->bf_mpdu;
1933 + sc->beacon.bslot[avp->av_bslot] = vif;
1934 + sc->nbcnvifs++;
1935 +
1936 + ath_dbg(common, CONFIG, "Added interface at beacon slot: %d\n",
1937 + avp->av_bslot);
1938 +}
1939 +
1940 +void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif)
1941 +{
1942 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1943 + struct ath_vif *avp = (void *)vif->drv_priv;
1944 + struct ath_buf *bf = avp->av_bcbuf;
1945 +
1946 + ath_dbg(common, CONFIG, "Removing interface at beacon slot: %d\n",
1947 + avp->av_bslot);
1948 +
1949 + tasklet_disable(&sc->bcon_tasklet);
1950 +
1951 + if (bf && bf->bf_mpdu) {
1952 + struct sk_buff *skb = bf->bf_mpdu;
1953 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1954 skb->len, DMA_TO_DEVICE);
1955 dev_kfree_skb_any(skb);
1956 @@ -274,99 +255,74 @@ int ath_beacon_alloc(struct ath_softc *s
1957 bf->bf_buf_addr = 0;
1958 }
1959
1960 - /* NB: the beacon data buffer must be 32-bit aligned. */
1961 - skb = ieee80211_beacon_get(sc->hw, vif);
1962 - if (skb == NULL)
1963 - return -ENOMEM;
1964 -
1965 - tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
1966 - sc->beacon.bc_tstamp = (u32) le64_to_cpu(tstamp);
1967 - /* Calculate a TSF adjustment factor required for staggered beacons. */
1968 - if (avp->av_bslot > 0) {
1969 - u64 tsfadjust;
1970 - int intval;
1971 + avp->av_bcbuf = NULL;
1972 + sc->beacon.bslot[avp->av_bslot] = NULL;
1973 + sc->nbcnvifs--;
1974 + list_add_tail(&bf->list, &sc->beacon.bbuf);
1975
1976 - intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
1977 + tasklet_enable(&sc->bcon_tasklet);
1978 +}
1979
1980 - /*
1981 - * Calculate the TSF offset for this beacon slot, i.e., the
1982 - * number of usecs that need to be added to the timestamp field
1983 - * in Beacon and Probe Response frames. Beacon slot 0 is
1984 - * processed at the correct offset, so it does not require TSF
1985 - * adjustment. Other slots are adjusted to get the timestamp
1986 - * close to the TBTT for the BSS.
1987 - */
1988 - tsfadjust = TU_TO_USEC(intval * avp->av_bslot) / ATH_BCBUF;
1989 - avp->tsf_adjust = cpu_to_le64(tsfadjust);
1990 +static int ath9k_beacon_choose_slot(struct ath_softc *sc)
1991 +{
1992 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1993 + struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1994 + u16 intval;
1995 + u32 tsftu;
1996 + u64 tsf;
1997 + int slot;
1998
1999 - ath_dbg(common, BEACON,
2000 - "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
2001 - avp->av_bslot, intval, (unsigned long long)tsfadjust);
2002 + if (sc->sc_ah->opmode != NL80211_IFTYPE_AP) {
2003 + ath_dbg(common, BEACON, "slot 0, tsf: %llu\n",
2004 + ath9k_hw_gettsf64(sc->sc_ah));
2005 + return 0;
2006 + }
2007
2008 - ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
2009 - avp->tsf_adjust;
2010 - } else
2011 - avp->tsf_adjust = cpu_to_le64(0);
2012 + intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
2013 + tsf = ath9k_hw_gettsf64(sc->sc_ah);
2014 + tsf += TU_TO_USEC(sc->sc_ah->config.sw_beacon_response_time);
2015 + tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
2016 + slot = (tsftu % (intval * ATH_BCBUF)) / intval;
2017
2018 - bf->bf_mpdu = skb;
2019 - bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2020 - skb->len, DMA_TO_DEVICE);
2021 - if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2022 - dev_kfree_skb_any(skb);
2023 - bf->bf_mpdu = NULL;
2024 - bf->bf_buf_addr = 0;
2025 - ath_err(common, "dma_mapping_error on beacon alloc\n");
2026 - return -ENOMEM;
2027 - }
2028 - avp->is_bslot_active = true;
2029 + ath_dbg(common, BEACON, "slot: %d tsf: %llu tsftu: %u\n",
2030 + slot, tsf, tsftu / ATH_BCBUF);
2031
2032 - return 0;
2033 + return slot;
2034 }
2035
2036 -void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp)
2037 +void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif)
2038 {
2039 - if (avp->av_bcbuf != NULL) {
2040 - struct ath_buf *bf;
2041 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2042 + struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
2043 + struct ath_vif *avp = (void *)vif->drv_priv;
2044 + u64 tsfadjust;
2045
2046 - avp->is_bslot_active = false;
2047 - if (avp->av_bslot != -1) {
2048 - sc->beacon.bslot[avp->av_bslot] = NULL;
2049 - sc->nbcnvifs--;
2050 - avp->av_bslot = -1;
2051 - }
2052 + if (avp->av_bslot == 0)
2053 + return;
2054
2055 - bf = avp->av_bcbuf;
2056 - if (bf->bf_mpdu != NULL) {
2057 - struct sk_buff *skb = bf->bf_mpdu;
2058 - dma_unmap_single(sc->dev, bf->bf_buf_addr,
2059 - skb->len, DMA_TO_DEVICE);
2060 - dev_kfree_skb_any(skb);
2061 - bf->bf_mpdu = NULL;
2062 - bf->bf_buf_addr = 0;
2063 - }
2064 - list_add_tail(&bf->list, &sc->beacon.bbuf);
2065 + tsfadjust = cur_conf->beacon_interval * avp->av_bslot / ATH_BCBUF;
2066 + avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
2067
2068 - avp->av_bcbuf = NULL;
2069 - }
2070 + ath_dbg(common, CONFIG, "tsfadjust is: %llu for bslot: %d\n",
2071 + (unsigned long long)tsfadjust, avp->av_bslot);
2072 }
2073
2074 -void ath_beacon_tasklet(unsigned long data)
2075 +void ath9k_beacon_tasklet(unsigned long data)
2076 {
2077 struct ath_softc *sc = (struct ath_softc *)data;
2078 - struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
2079 struct ath_hw *ah = sc->sc_ah;
2080 struct ath_common *common = ath9k_hw_common(ah);
2081 struct ath_buf *bf = NULL;
2082 struct ieee80211_vif *vif;
2083 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2084 int slot;
2085 - u32 bfaddr, bc = 0;
2086
2087 - if (work_pending(&sc->hw_reset_work)) {
2088 + if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
2089 ath_dbg(common, RESET,
2090 "reset work is pending, skip beaconing now\n");
2091 return;
2092 }
2093 +
2094 /*
2095 * Check if the previous beacon has gone out. If
2096 * not don't try to post another, skip this period
2097 @@ -390,55 +346,25 @@ void ath_beacon_tasklet(unsigned long da
2098 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
2099 ath_dbg(common, BSTUCK, "beacon is officially stuck\n");
2100 sc->beacon.bmisscnt = 0;
2101 - set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
2102 - ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2103 + ath9k_queue_reset(sc, RESET_TYPE_BEACON_STUCK);
2104 }
2105
2106 return;
2107 }
2108
2109 - /*
2110 - * Generate beacon frames. we are sending frames
2111 - * staggered so calculate the slot for this frame based
2112 - * on the tsf to safeguard against missing an swba.
2113 - */
2114 -
2115 -
2116 - if (ah->opmode == NL80211_IFTYPE_AP) {
2117 - u16 intval;
2118 - u32 tsftu;
2119 - u64 tsf;
2120 -
2121 - intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
2122 - tsf = ath9k_hw_gettsf64(ah);
2123 - tsf += TU_TO_USEC(ah->config.sw_beacon_response_time);
2124 - tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
2125 - slot = (tsftu % (intval * ATH_BCBUF)) / intval;
2126 - vif = sc->beacon.bslot[slot];
2127 -
2128 - ath_dbg(common, BEACON,
2129 - "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
2130 - slot, tsf, tsftu / ATH_BCBUF, intval, vif);
2131 - } else {
2132 - slot = 0;
2133 - vif = sc->beacon.bslot[slot];
2134 - }
2135 + slot = ath9k_beacon_choose_slot(sc);
2136 + vif = sc->beacon.bslot[slot];
2137
2138 + if (!vif || !vif->bss_conf.enable_beacon)
2139 + return;
2140
2141 - bfaddr = 0;
2142 - if (vif) {
2143 - bf = ath_beacon_generate(sc->hw, vif);
2144 - if (bf != NULL) {
2145 - bfaddr = bf->bf_daddr;
2146 - bc = 1;
2147 - }
2148 + bf = ath9k_beacon_generate(sc->hw, vif);
2149 + WARN_ON(!bf);
2150
2151 - if (sc->beacon.bmisscnt != 0) {
2152 - ath_dbg(common, BSTUCK,
2153 - "resume beacon xmit after %u misses\n",
2154 - sc->beacon.bmisscnt);
2155 - sc->beacon.bmisscnt = 0;
2156 - }
2157 + if (sc->beacon.bmisscnt != 0) {
2158 + ath_dbg(common, BSTUCK, "resume beacon xmit after %u misses\n",
2159 + sc->beacon.bmisscnt);
2160 + sc->beacon.bmisscnt = 0;
2161 }
2162
2163 /*
2164 @@ -458,39 +384,37 @@ void ath_beacon_tasklet(unsigned long da
2165 * set to ATH_BCBUF so this check is a noop.
2166 */
2167 if (sc->beacon.updateslot == UPDATE) {
2168 - sc->beacon.updateslot = COMMIT; /* commit next beacon */
2169 + sc->beacon.updateslot = COMMIT;
2170 sc->beacon.slotupdate = slot;
2171 - } else if (sc->beacon.updateslot == COMMIT && sc->beacon.slotupdate == slot) {
2172 + } else if (sc->beacon.updateslot == COMMIT &&
2173 + sc->beacon.slotupdate == slot) {
2174 ah->slottime = sc->beacon.slottime;
2175 ath9k_hw_init_global_settings(ah);
2176 sc->beacon.updateslot = OK;
2177 }
2178 - if (bfaddr != 0) {
2179 +
2180 + if (bf) {
2181 + ath9k_reset_beacon_status(sc);
2182 +
2183 /* NB: cabq traffic should already be queued and primed */
2184 - ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr);
2185 + ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
2186
2187 if (!edma)
2188 ath9k_hw_txstart(ah, sc->beacon.beaconq);
2189 -
2190 - sc->beacon.ast_be_xmit += bc; /* XXX per-vif? */
2191 }
2192 }
2193
2194 -static void ath9k_beacon_init(struct ath_softc *sc,
2195 - u32 next_beacon,
2196 - u32 beacon_period)
2197 +static void ath9k_beacon_init(struct ath_softc *sc, u32 nexttbtt, u32 intval)
2198 {
2199 - if (test_bit(SC_OP_TSF_RESET, &sc->sc_flags)) {
2200 - ath9k_ps_wakeup(sc);
2201 - ath9k_hw_reset_tsf(sc->sc_ah);
2202 - }
2203 -
2204 - ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
2205 + struct ath_hw *ah = sc->sc_ah;
2206
2207 - if (test_bit(SC_OP_TSF_RESET, &sc->sc_flags)) {
2208 - ath9k_ps_restore(sc);
2209 - clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
2210 - }
2211 + ath9k_hw_disable_interrupts(ah);
2212 + ath9k_hw_reset_tsf(ah);
2213 + ath9k_beaconq_config(sc);
2214 + ath9k_hw_beaconinit(ah, nexttbtt, intval);
2215 + sc->beacon.bmisscnt = 0;
2216 + ath9k_hw_set_interrupts(ah);
2217 + ath9k_hw_enable_interrupts(ah);
2218 }
2219
2220 /*
2221 @@ -498,32 +422,27 @@ static void ath9k_beacon_init(struct ath
2222 * burst together. For the former arrange for the SWBA to be delivered for each
2223 * slot. Slots that are not occupied will generate nothing.
2224 */
2225 -static void ath_beacon_config_ap(struct ath_softc *sc,
2226 - struct ath_beacon_config *conf)
2227 +static void ath9k_beacon_config_ap(struct ath_softc *sc,
2228 + struct ath_beacon_config *conf)
2229 {
2230 struct ath_hw *ah = sc->sc_ah;
2231 + struct ath_common *common = ath9k_hw_common(ah);
2232 u32 nexttbtt, intval;
2233
2234 /* NB: the beacon interval is kept internally in TU's */
2235 intval = TU_TO_USEC(conf->beacon_interval);
2236 - intval /= ATH_BCBUF; /* for staggered beacons */
2237 + intval /= ATH_BCBUF;
2238 nexttbtt = intval;
2239
2240 - /*
2241 - * In AP mode we enable the beacon timers and SWBA interrupts to
2242 - * prepare beacon frames.
2243 - */
2244 - ah->imask |= ATH9K_INT_SWBA;
2245 - ath_beaconq_config(sc);
2246 + if (conf->enable_beacon)
2247 + ah->imask |= ATH9K_INT_SWBA;
2248 + else
2249 + ah->imask &= ~ATH9K_INT_SWBA;
2250
2251 - /* Set the computed AP beacon timers */
2252 + ath_dbg(common, BEACON, "AP nexttbtt: %u intval: %u conf_intval: %u\n",
2253 + nexttbtt, intval, conf->beacon_interval);
2254
2255 - ath9k_hw_disable_interrupts(ah);
2256 - set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
2257 ath9k_beacon_init(sc, nexttbtt, intval);
2258 - sc->beacon.bmisscnt = 0;
2259 - ath9k_hw_set_interrupts(ah);
2260 - ath9k_hw_enable_interrupts(ah);
2261 }
2262
2263 /*
2264 @@ -534,8 +453,8 @@ static void ath_beacon_config_ap(struct
2265 * we'll receive a BMISS interrupt when we stop seeing beacons from the AP
2266 * we've associated with.
2267 */
2268 -static void ath_beacon_config_sta(struct ath_softc *sc,
2269 - struct ath_beacon_config *conf)
2270 +static void ath9k_beacon_config_sta(struct ath_softc *sc,
2271 + struct ath_beacon_config *conf)
2272 {
2273 struct ath_hw *ah = sc->sc_ah;
2274 struct ath_common *common = ath9k_hw_common(ah);
2275 @@ -654,8 +573,8 @@ static void ath_beacon_config_sta(struct
2276 ath9k_hw_enable_interrupts(ah);
2277 }
2278
2279 -static void ath_beacon_config_adhoc(struct ath_softc *sc,
2280 - struct ath_beacon_config *conf)
2281 +static void ath9k_beacon_config_adhoc(struct ath_softc *sc,
2282 + struct ath_beacon_config *conf)
2283 {
2284 struct ath_hw *ah = sc->sc_ah;
2285 struct ath_common *common = ath9k_hw_common(ah);
2286 @@ -669,82 +588,53 @@ static void ath_beacon_config_adhoc(stru
2287 tsf = roundup(ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE), intval);
2288 nexttbtt = tsf + intval;
2289
2290 - ath_dbg(common, BEACON, "IBSS nexttbtt %u intval %u (%u)\n",
2291 - nexttbtt, intval, conf->beacon_interval);
2292 -
2293 - /*
2294 - * In IBSS mode enable the beacon timers but only enable SWBA interrupts
2295 - * if we need to manually prepare beacon frames. Otherwise we use a
2296 - * self-linked tx descriptor and let the hardware deal with things.
2297 - */
2298 - ah->imask |= ATH9K_INT_SWBA;
2299 -
2300 - ath_beaconq_config(sc);
2301 + if (conf->enable_beacon)
2302 + ah->imask |= ATH9K_INT_SWBA;
2303 + else
2304 + ah->imask &= ~ATH9K_INT_SWBA;
2305
2306 - /* Set the computed ADHOC beacon timers */
2307 + ath_dbg(common, BEACON, "IBSS nexttbtt: %u intval: %u conf_intval: %u\n",
2308 + nexttbtt, intval, conf->beacon_interval);
2309
2310 - ath9k_hw_disable_interrupts(ah);
2311 ath9k_beacon_init(sc, nexttbtt, intval);
2312 - sc->beacon.bmisscnt = 0;
2313 -
2314 - ath9k_hw_set_interrupts(ah);
2315 - ath9k_hw_enable_interrupts(ah);
2316 }
2317
2318 -static bool ath9k_allow_beacon_config(struct ath_softc *sc,
2319 - struct ieee80211_vif *vif)
2320 +bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
2321 {
2322 - struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
2323 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2324 - struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2325 struct ath_vif *avp = (void *)vif->drv_priv;
2326
2327 - /*
2328 - * Can not have different beacon interval on multiple
2329 - * AP interface case
2330 - */
2331 - if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
2332 - (sc->nbcnvifs > 1) &&
2333 - (vif->type == NL80211_IFTYPE_AP) &&
2334 - (cur_conf->beacon_interval != bss_conf->beacon_int)) {
2335 - ath_dbg(common, CONFIG,
2336 - "Changing beacon interval of multiple AP interfaces !\n");
2337 - return false;
2338 - }
2339 - /*
2340 - * Can not configure station vif's beacon config
2341 - * while on AP opmode
2342 - */
2343 - if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
2344 - (vif->type != NL80211_IFTYPE_AP)) {
2345 - ath_dbg(common, CONFIG,
2346 - "STA vif's beacon not allowed on AP mode\n");
2347 - return false;
2348 + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
2349 + if ((vif->type != NL80211_IFTYPE_AP) ||
2350 + (sc->nbcnvifs > 1)) {
2351 + ath_dbg(common, CONFIG,
2352 + "An AP interface is already present !\n");
2353 + return false;
2354 + }
2355 }
2356 - /*
2357 - * Do not allow beacon config if HW was already configured
2358 - * with another STA vif
2359 - */
2360 - if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
2361 - (vif->type == NL80211_IFTYPE_STATION) &&
2362 - test_bit(SC_OP_BEACONS, &sc->sc_flags) &&
2363 - !avp->primary_sta_vif) {
2364 - ath_dbg(common, CONFIG,
2365 - "Beacon already configured for a station interface\n");
2366 - return false;
2367 +
2368 + if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
2369 + if ((vif->type == NL80211_IFTYPE_STATION) &&
2370 + test_bit(SC_OP_BEACONS, &sc->sc_flags) &&
2371 + !avp->primary_sta_vif) {
2372 + ath_dbg(common, CONFIG,
2373 + "Beacon already configured for a station interface\n");
2374 + return false;
2375 + }
2376 }
2377 +
2378 return true;
2379 }
2380
2381 -void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
2382 +static void ath9k_cache_beacon_config(struct ath_softc *sc,
2383 + struct ieee80211_bss_conf *bss_conf)
2384 {
2385 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2386 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
2387 - struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2388
2389 - if (!ath9k_allow_beacon_config(sc, vif))
2390 - return;
2391 + ath_dbg(common, BEACON,
2392 + "Caching beacon data for BSS: %pM\n", bss_conf->bssid);
2393
2394 - /* Setup the beacon configuration parameters */
2395 cur_conf->beacon_interval = bss_conf->beacon_int;
2396 cur_conf->dtim_period = bss_conf->dtim_period;
2397 cur_conf->listen_interval = 1;
2398 @@ -769,73 +659,59 @@ void ath_beacon_config(struct ath_softc
2399 if (cur_conf->dtim_period == 0)
2400 cur_conf->dtim_period = 1;
2401
2402 - ath_set_beacon(sc);
2403 }
2404
2405 -static bool ath_has_valid_bslot(struct ath_softc *sc)
2406 +void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
2407 + u32 changed)
2408 {
2409 - struct ath_vif *avp;
2410 - int slot;
2411 - bool found = false;
2412 + struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2413 + struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
2414
2415 - for (slot = 0; slot < ATH_BCBUF; slot++) {
2416 - if (sc->beacon.bslot[slot]) {
2417 - avp = (void *)sc->beacon.bslot[slot]->drv_priv;
2418 - if (avp->is_bslot_active) {
2419 - found = true;
2420 - break;
2421 - }
2422 + ath9k_cache_beacon_config(sc, bss_conf);
2423 +
2424 + if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
2425 + ath9k_set_beacon(sc);
2426 + set_bit(SC_OP_BEACONS, &sc->sc_flags);
2427 + } else {
2428 + /*
2429 + * Take care of multiple interfaces when
2430 + * enabling/disabling SWBA.
2431 + */
2432 + if (changed & BSS_CHANGED_BEACON_ENABLED) {
2433 + if (!bss_conf->enable_beacon &&
2434 + (sc->nbcnvifs <= 1))
2435 + cur_conf->enable_beacon = false;
2436 + else if (bss_conf->enable_beacon)
2437 + cur_conf->enable_beacon = true;
2438 }
2439 +
2440 + ath9k_set_beacon(sc);
2441 +
2442 + if (cur_conf->enable_beacon)
2443 + set_bit(SC_OP_BEACONS, &sc->sc_flags);
2444 + else
2445 + clear_bit(SC_OP_BEACONS, &sc->sc_flags);
2446 }
2447 - return found;
2448 }
2449
2450 -
2451 -void ath_set_beacon(struct ath_softc *sc)
2452 +void ath9k_set_beacon(struct ath_softc *sc)
2453 {
2454 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2455 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
2456
2457 switch (sc->sc_ah->opmode) {
2458 case NL80211_IFTYPE_AP:
2459 - if (ath_has_valid_bslot(sc))
2460 - ath_beacon_config_ap(sc, cur_conf);
2461 + ath9k_beacon_config_ap(sc, cur_conf);
2462 break;
2463 case NL80211_IFTYPE_ADHOC:
2464 case NL80211_IFTYPE_MESH_POINT:
2465 - ath_beacon_config_adhoc(sc, cur_conf);
2466 + ath9k_beacon_config_adhoc(sc, cur_conf);
2467 break;
2468 case NL80211_IFTYPE_STATION:
2469 - ath_beacon_config_sta(sc, cur_conf);
2470 + ath9k_beacon_config_sta(sc, cur_conf);
2471 break;
2472 default:
2473 ath_dbg(common, CONFIG, "Unsupported beaconing mode\n");
2474 return;
2475 }
2476 -
2477 - set_bit(SC_OP_BEACONS, &sc->sc_flags);
2478 -}
2479 -
2480 -void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
2481 -{
2482 - struct ath_hw *ah = sc->sc_ah;
2483 -
2484 - if (!ath_has_valid_bslot(sc)) {
2485 - clear_bit(SC_OP_BEACONS, &sc->sc_flags);
2486 - return;
2487 - }
2488 -
2489 - ath9k_ps_wakeup(sc);
2490 - if (status) {
2491 - /* Re-enable beaconing */
2492 - ah->imask |= ATH9K_INT_SWBA;
2493 - ath9k_hw_set_interrupts(ah);
2494 - } else {
2495 - /* Disable SWBA interrupt */
2496 - ah->imask &= ~ATH9K_INT_SWBA;
2497 - ath9k_hw_set_interrupts(ah);
2498 - tasklet_kill(&sc->bcon_tasklet);
2499 - ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
2500 - }
2501 - ath9k_ps_restore(sc);
2502 }
2503 --- a/drivers/net/wireless/ath/ath9k/calib.h
2504 +++ b/drivers/net/wireless/ath/ath9k/calib.h
2505 @@ -30,10 +30,10 @@ struct ar5416IniArray {
2506 u32 ia_columns;
2507 };
2508
2509 -#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
2510 +#define INIT_INI_ARRAY(iniarray, array) do { \
2511 (iniarray)->ia_array = (u32 *)(array); \
2512 - (iniarray)->ia_rows = (rows); \
2513 - (iniarray)->ia_columns = (columns); \
2514 + (iniarray)->ia_rows = ARRAY_SIZE(array); \
2515 + (iniarray)->ia_columns = ARRAY_SIZE(array[0]); \
2516 } while (0)
2517
2518 #define INI_RA(iniarray, row, column) \
2519 --- a/drivers/net/wireless/ath/ath9k/debug.c
2520 +++ b/drivers/net/wireless/ath/ath9k/debug.c
2521 @@ -206,10 +206,9 @@ static ssize_t write_file_disable_ani(st
2522
2523 if (disable_ani) {
2524 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
2525 - del_timer_sync(&common->ani.timer);
2526 + ath_stop_ani(sc);
2527 } else {
2528 - set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
2529 - ath_start_ani(common);
2530 + ath_check_ani(sc);
2531 }
2532
2533 return count;
2534 @@ -1556,6 +1555,14 @@ int ath9k_init_debug(struct ath_hw *ah)
2535 &fops_interrupt);
2536 debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy, sc,
2537 &fops_xmit);
2538 + debugfs_create_u32("qlen_bk", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
2539 + &sc->tx.txq_max_pending[WME_AC_BK]);
2540 + debugfs_create_u32("qlen_be", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
2541 + &sc->tx.txq_max_pending[WME_AC_BE]);
2542 + debugfs_create_u32("qlen_vi", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
2543 + &sc->tx.txq_max_pending[WME_AC_VI]);
2544 + debugfs_create_u32("qlen_vo", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
2545 + &sc->tx.txq_max_pending[WME_AC_VO]);
2546 debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy, sc,
2547 &fops_stations);
2548 debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, sc,
2549 --- a/drivers/net/wireless/ath/ath9k/debug.h
2550 +++ b/drivers/net/wireless/ath/ath9k/debug.h
2551 @@ -32,6 +32,19 @@ struct ath_buf;
2552 #define RESET_STAT_INC(sc, type) do { } while (0)
2553 #endif
2554
2555 +enum ath_reset_type {
2556 + RESET_TYPE_BB_HANG,
2557 + RESET_TYPE_BB_WATCHDOG,
2558 + RESET_TYPE_FATAL_INT,
2559 + RESET_TYPE_TX_ERROR,
2560 + RESET_TYPE_TX_HANG,
2561 + RESET_TYPE_PLL_HANG,
2562 + RESET_TYPE_MAC_HANG,
2563 + RESET_TYPE_BEACON_STUCK,
2564 + RESET_TYPE_MCI,
2565 + __RESET_TYPE_MAX
2566 +};
2567 +
2568 #ifdef CONFIG_ATH9K_DEBUGFS
2569
2570 /**
2571 @@ -209,17 +222,6 @@ struct ath_rx_stats {
2572 u32 rx_frags;
2573 };
2574
2575 -enum ath_reset_type {
2576 - RESET_TYPE_BB_HANG,
2577 - RESET_TYPE_BB_WATCHDOG,
2578 - RESET_TYPE_FATAL_INT,
2579 - RESET_TYPE_TX_ERROR,
2580 - RESET_TYPE_TX_HANG,
2581 - RESET_TYPE_PLL_HANG,
2582 - RESET_TYPE_MAC_HANG,
2583 - __RESET_TYPE_MAX
2584 -};
2585 -
2586 struct ath_stats {
2587 struct ath_interrupt_stats istats;
2588 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
2589 --- a/drivers/net/wireless/ath/ath9k/eeprom.h
2590 +++ b/drivers/net/wireless/ath/ath9k/eeprom.h
2591 @@ -241,16 +241,12 @@ enum eeprom_param {
2592 EEP_TEMPSENSE_SLOPE,
2593 EEP_TEMPSENSE_SLOPE_PAL_ON,
2594 EEP_PWR_TABLE_OFFSET,
2595 - EEP_DRIVE_STRENGTH,
2596 - EEP_INTERNAL_REGULATOR,
2597 - EEP_SWREG,
2598 EEP_PAPRD,
2599 EEP_MODAL_VER,
2600 EEP_ANT_DIV_CTL1,
2601 EEP_CHAIN_MASK_REDUCE,
2602 EEP_ANTENNA_GAIN_2G,
2603 EEP_ANTENNA_GAIN_5G,
2604 - EEP_QUICK_DROP
2605 };
2606
2607 enum ar5416_rates {
2608 --- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
2609 +++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
2610 @@ -1111,7 +1111,7 @@ static int ath9k_htc_add_interface(struc
2611
2612 if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
2613 !test_bit(OP_ANI_RUNNING, &priv->op_flags)) {
2614 - ath9k_hw_set_tsfadjust(priv->ah, 1);
2615 + ath9k_hw_set_tsfadjust(priv->ah, true);
2616 ath9k_htc_start_ani(priv);
2617 }
2618
2619 @@ -1351,7 +1351,7 @@ static int ath9k_htc_conf_tx(struct ieee
2620 qi.tqi_aifs = params->aifs;
2621 qi.tqi_cwmin = params->cw_min;
2622 qi.tqi_cwmax = params->cw_max;
2623 - qi.tqi_burstTime = params->txop;
2624 + qi.tqi_burstTime = params->txop * 32;
2625
2626 qnum = get_hw_qnum(queue, priv->hwq_map);
2627
2628 --- a/drivers/net/wireless/ath/ath9k/hw.c
2629 +++ b/drivers/net/wireless/ath/ath9k/hw.c
2630 @@ -463,9 +463,6 @@ static void ath9k_hw_init_config(struct
2631 ah->config.spurchans[i][1] = AR_NO_SPUR;
2632 }
2633
2634 - /* PAPRD needs some more work to be enabled */
2635 - ah->config.paprd_disable = 1;
2636 -
2637 ah->config.rx_intr_mitigation = true;
2638 ah->config.pcieSerDesWrite = true;
2639
2640 @@ -671,10 +668,6 @@ static int __ath9k_hw_init(struct ath_hw
2641 if (!AR_SREV_9300_20_OR_LATER(ah))
2642 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
2643
2644 - /* disable ANI for 9340 */
2645 - if (AR_SREV_9340(ah))
2646 - ah->config.enable_ani = false;
2647 -
2648 ath9k_hw_init_mode_regs(ah);
2649
2650 if (!ah->is_pciexpress)
2651 @@ -1781,6 +1774,8 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2652 /* Operating channel changed, reset channel calibration data */
2653 memset(caldata, 0, sizeof(*caldata));
2654 ath9k_init_nfcal_hist_buffer(ah, chan);
2655 + } else if (caldata) {
2656 + caldata->paprd_packet_sent = false;
2657 }
2658 ah->noise = ath9k_hw_getchan_noise(ah, chan);
2659
2660 @@ -2505,7 +2500,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw
2661 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2662 pCap->txs_len = sizeof(struct ar9003_txs);
2663 if (!ah->config.paprd_disable &&
2664 - ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2665 + ah->eep_ops->get_eeprom(ah, EEP_PAPRD) &&
2666 + !AR_SREV_9462(ah))
2667 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2668 } else {
2669 pCap->tx_desc_len = sizeof(struct ath_desc);
2670 @@ -2916,9 +2912,9 @@ void ath9k_hw_reset_tsf(struct ath_hw *a
2671 }
2672 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2673
2674 -void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2675 +void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2676 {
2677 - if (setting)
2678 + if (set)
2679 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2680 else
2681 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2682 --- a/drivers/net/wireless/ath/ath9k/hw.h
2683 +++ b/drivers/net/wireless/ath/ath9k/hw.h
2684 @@ -404,6 +404,7 @@ struct ath9k_hw_cal_data {
2685 int8_t iCoff;
2686 int8_t qCoff;
2687 bool rtt_done;
2688 + bool paprd_packet_sent;
2689 bool paprd_done;
2690 bool nfcal_pending;
2691 bool nfcal_interference;
2692 @@ -994,7 +995,7 @@ u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2693 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
2694 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
2695 void ath9k_hw_reset_tsf(struct ath_hw *ah);
2696 -void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
2697 +void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
2698 void ath9k_hw_init_global_settings(struct ath_hw *ah);
2699 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
2700 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
2701 --- a/drivers/net/wireless/ath/ath9k/init.c
2702 +++ b/drivers/net/wireless/ath/ath9k/init.c
2703 @@ -436,6 +436,7 @@ static int ath9k_init_queues(struct ath_
2704 for (i = 0; i < WME_NUM_AC; i++) {
2705 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
2706 sc->tx.txq_map[i]->mac80211_qnum = i;
2707 + sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
2708 }
2709 return 0;
2710 }
2711 @@ -560,7 +561,7 @@ static int ath9k_init_softc(u16 devid, s
2712 spin_lock_init(&sc->debug.samp_lock);
2713 #endif
2714 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
2715 - tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
2716 + tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
2717 (unsigned long)sc);
2718
2719 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
2720 --- a/drivers/net/wireless/ath/ath9k/link.c
2721 +++ b/drivers/net/wireless/ath/ath9k/link.c
2722 @@ -50,8 +50,7 @@ void ath_tx_complete_poll_work(struct wo
2723 if (needreset) {
2724 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET,
2725 "tx hung, resetting the chip\n");
2726 - RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2727 - ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2728 + ath9k_queue_reset(sc, RESET_TYPE_TX_HANG);
2729 return;
2730 }
2731
2732 @@ -69,6 +68,7 @@ void ath_hw_check(struct work_struct *wo
2733 unsigned long flags;
2734 int busy;
2735 u8 is_alive, nbeacon = 1;
2736 + enum ath_reset_type type;
2737
2738 ath9k_ps_wakeup(sc);
2739 is_alive = ath9k_hw_check_alive(sc->sc_ah);
2740 @@ -78,7 +78,7 @@ void ath_hw_check(struct work_struct *wo
2741 else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
2742 ath_dbg(common, RESET,
2743 "DCU stuck is detected. Schedule chip reset\n");
2744 - RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG);
2745 + type = RESET_TYPE_MAC_HANG;
2746 goto sched_reset;
2747 }
2748
2749 @@ -90,7 +90,7 @@ void ath_hw_check(struct work_struct *wo
2750 busy, sc->hw_busy_count + 1);
2751 if (busy >= 99) {
2752 if (++sc->hw_busy_count >= 3) {
2753 - RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
2754 + type = RESET_TYPE_BB_HANG;
2755 goto sched_reset;
2756 }
2757 } else if (busy >= 0) {
2758 @@ -102,7 +102,7 @@ void ath_hw_check(struct work_struct *wo
2759 goto out;
2760
2761 sched_reset:
2762 - ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2763 + ath9k_queue_reset(sc, type);
2764 out:
2765 ath9k_ps_restore(sc);
2766 }
2767 @@ -119,8 +119,7 @@ static bool ath_hw_pll_rx_hang_check(str
2768 count++;
2769 if (count == 3) {
2770 ath_dbg(common, RESET, "PLL WAR, resetting the chip\n");
2771 - RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
2772 - ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2773 + ath9k_queue_reset(sc, RESET_TYPE_PLL_HANG);
2774 count = 0;
2775 return true;
2776 }
2777 @@ -255,8 +254,9 @@ void ath_paprd_calibrate(struct work_str
2778 int chain_ok = 0;
2779 int chain;
2780 int len = 1800;
2781 + int ret;
2782
2783 - if (!caldata)
2784 + if (!caldata || !caldata->paprd_packet_sent || caldata->paprd_done)
2785 return;
2786
2787 ath9k_ps_wakeup(sc);
2788 @@ -283,13 +283,6 @@ void ath_paprd_calibrate(struct work_str
2789 continue;
2790
2791 chain_ok = 0;
2792 -
2793 - ath_dbg(common, CALIBRATE,
2794 - "Sending PAPRD frame for thermal measurement on chain %d\n",
2795 - chain);
2796 - if (!ath_paprd_send_frame(sc, skb, chain))
2797 - goto fail_paprd;
2798 -
2799 ar9003_paprd_setup_gain_table(ah, chain);
2800
2801 ath_dbg(common, CALIBRATE,
2802 @@ -303,7 +296,13 @@ void ath_paprd_calibrate(struct work_str
2803 break;
2804 }
2805
2806 - if (ar9003_paprd_create_curve(ah, caldata, chain)) {
2807 + ret = ar9003_paprd_create_curve(ah, caldata, chain);
2808 + if (ret == -EINPROGRESS) {
2809 + ath_dbg(common, CALIBRATE,
2810 + "PAPRD curve on chain %d needs to be re-trained\n",
2811 + chain);
2812 + break;
2813 + } else if (ret) {
2814 ath_dbg(common, CALIBRATE,
2815 "PAPRD create curve failed on chain %d\n",
2816 chain);
2817 @@ -432,26 +431,69 @@ set_timer:
2818 }
2819 }
2820
2821 -void ath_start_ani(struct ath_common *common)
2822 +void ath_start_ani(struct ath_softc *sc)
2823 {
2824 - struct ath_hw *ah = common->ah;
2825 + struct ath_hw *ah = sc->sc_ah;
2826 + struct ath_common *common = ath9k_hw_common(ah);
2827 unsigned long timestamp = jiffies_to_msecs(jiffies);
2828 - struct ath_softc *sc = (struct ath_softc *) common->priv;
2829
2830 - if (!test_bit(SC_OP_ANI_RUN, &sc->sc_flags))
2831 - return;
2832 -
2833 - if (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
2834 + if (common->disable_ani ||
2835 + !test_bit(SC_OP_ANI_RUN, &sc->sc_flags) ||
2836 + (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
2837 return;
2838
2839 common->ani.longcal_timer = timestamp;
2840 common->ani.shortcal_timer = timestamp;
2841 common->ani.checkani_timer = timestamp;
2842
2843 + ath_dbg(common, ANI, "Starting ANI\n");
2844 mod_timer(&common->ani.timer,
2845 jiffies + msecs_to_jiffies((u32)ah->config.ani_poll_interval));
2846 }
2847
2848 +void ath_stop_ani(struct ath_softc *sc)
2849 +{
2850 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2851 +
2852 + ath_dbg(common, ANI, "Stopping ANI\n");
2853 + del_timer_sync(&common->ani.timer);
2854 +}
2855 +
2856 +void ath_check_ani(struct ath_softc *sc)
2857 +{
2858 + struct ath_hw *ah = sc->sc_ah;
2859 + struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
2860 +
2861 + /*
2862 + * Check for the various conditions in which ANI has to
2863 + * be stopped.
2864 + */
2865 + if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2866 + if (!cur_conf->enable_beacon)
2867 + goto stop_ani;
2868 + } else if (ah->opmode == NL80211_IFTYPE_AP) {
2869 + if (!cur_conf->enable_beacon) {
2870 + /*
2871 + * Disable ANI only when there are no
2872 + * associated stations.
2873 + */
2874 + if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
2875 + goto stop_ani;
2876 + }
2877 + } else if (ah->opmode == NL80211_IFTYPE_STATION) {
2878 + if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
2879 + goto stop_ani;
2880 + }
2881 +
2882 + set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
2883 + ath_start_ani(sc);
2884 + return;
2885 +
2886 +stop_ani:
2887 + clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
2888 + ath_stop_ani(sc);
2889 +}
2890 +
2891 void ath_update_survey_nf(struct ath_softc *sc, int channel)
2892 {
2893 struct ath_hw *ah = sc->sc_ah;
2894 --- a/drivers/net/wireless/ath/ath9k/main.c
2895 +++ b/drivers/net/wireless/ath/ath9k/main.c
2896 @@ -167,8 +167,6 @@ static void ath_cancel_work(struct ath_s
2897
2898 static void ath_restart_work(struct ath_softc *sc)
2899 {
2900 - struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2901 -
2902 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2903
2904 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
2905 @@ -177,21 +175,18 @@ static void ath_restart_work(struct ath_
2906 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
2907
2908 ath_start_rx_poll(sc, 3);
2909 -
2910 - if (!common->disable_ani)
2911 - ath_start_ani(common);
2912 + ath_start_ani(sc);
2913 }
2914
2915 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
2916 {
2917 struct ath_hw *ah = sc->sc_ah;
2918 - struct ath_common *common = ath9k_hw_common(ah);
2919 bool ret = true;
2920
2921 ieee80211_stop_queues(sc->hw);
2922
2923 sc->hw_busy_count = 0;
2924 - del_timer_sync(&common->ani.timer);
2925 + ath_stop_ani(sc);
2926 del_timer_sync(&sc->rx_poll_timer);
2927
2928 ath9k_debug_samp_bb_mac(sc);
2929 @@ -236,7 +231,7 @@ static bool ath_complete_reset(struct at
2930 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
2931 goto work;
2932
2933 - ath_set_beacon(sc);
2934 + ath9k_set_beacon(sc);
2935
2936 if (ah->opmode == NL80211_IFTYPE_STATION &&
2937 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2938 @@ -365,6 +360,7 @@ void ath9k_tasklet(unsigned long data)
2939 struct ath_softc *sc = (struct ath_softc *)data;
2940 struct ath_hw *ah = sc->sc_ah;
2941 struct ath_common *common = ath9k_hw_common(ah);
2942 + enum ath_reset_type type;
2943 unsigned long flags;
2944 u32 status = sc->intrstatus;
2945 u32 rxmask;
2946 @@ -374,18 +370,13 @@ void ath9k_tasklet(unsigned long data)
2947
2948 if ((status & ATH9K_INT_FATAL) ||
2949 (status & ATH9K_INT_BB_WATCHDOG)) {
2950 -#ifdef CONFIG_ATH9K_DEBUGFS
2951 - enum ath_reset_type type;
2952
2953 if (status & ATH9K_INT_FATAL)
2954 type = RESET_TYPE_FATAL_INT;
2955 else
2956 type = RESET_TYPE_BB_WATCHDOG;
2957
2958 - RESET_STAT_INC(sc, type);
2959 -#endif
2960 - set_bit(SC_OP_HW_RESET, &sc->sc_flags);
2961 - ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2962 + ath9k_queue_reset(sc, type);
2963 goto out;
2964 }
2965
2966 @@ -468,8 +459,10 @@ irqreturn_t ath_isr(int irq, void *dev)
2967 if (!ath9k_hw_intrpend(ah))
2968 return IRQ_NONE;
2969
2970 - if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2971 + if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
2972 + ath9k_hw_kill_interrupts(ah);
2973 return IRQ_HANDLED;
2974 + }
2975
2976 /*
2977 * Figure out the reason(s) for the interrupt. Note
2978 @@ -586,6 +579,15 @@ static int ath_reset(struct ath_softc *s
2979 return r;
2980 }
2981
2982 +void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
2983 +{
2984 +#ifdef CONFIG_ATH9K_DEBUGFS
2985 + RESET_STAT_INC(sc, type);
2986 +#endif
2987 + set_bit(SC_OP_HW_RESET, &sc->sc_flags);
2988 + ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2989 +}
2990 +
2991 void ath_reset_work(struct work_struct *work)
2992 {
2993 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
2994 @@ -852,16 +854,6 @@ bool ath9k_uses_beacons(int type)
2995 }
2996 }
2997
2998 -static void ath9k_reclaim_beacon(struct ath_softc *sc,
2999 - struct ieee80211_vif *vif)
3000 -{
3001 - struct ath_vif *avp = (void *)vif->drv_priv;
3002 -
3003 - ath9k_set_beaconing_status(sc, false);
3004 - ath_beacon_return(sc, avp);
3005 - ath9k_set_beaconing_status(sc, true);
3006 -}
3007 -
3008 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
3009 {
3010 struct ath9k_vif_iter_data *iter_data = data;
3011 @@ -929,18 +921,14 @@ static void ath9k_calculate_summary_stat
3012
3013 ath9k_calculate_iter_data(hw, vif, &iter_data);
3014
3015 - /* Set BSSID mask. */
3016 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
3017 ath_hw_setbssidmask(common);
3018
3019 - /* Set op-mode & TSF */
3020 if (iter_data.naps > 0) {
3021 - ath9k_hw_set_tsfadjust(ah, 1);
3022 - set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
3023 + ath9k_hw_set_tsfadjust(ah, true);
3024 ah->opmode = NL80211_IFTYPE_AP;
3025 } else {
3026 - ath9k_hw_set_tsfadjust(ah, 0);
3027 - clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
3028 + ath9k_hw_set_tsfadjust(ah, false);
3029
3030 if (iter_data.nmeshes)
3031 ah->opmode = NL80211_IFTYPE_MESH_POINT;
3032 @@ -952,45 +940,14 @@ static void ath9k_calculate_summary_stat
3033 ah->opmode = NL80211_IFTYPE_STATION;
3034 }
3035
3036 - /*
3037 - * Enable MIB interrupts when there are hardware phy counters.
3038 - */
3039 + ath9k_hw_setopmode(ah);
3040 +
3041 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3042 ah->imask |= ATH9K_INT_TSFOOR;
3043 else
3044 ah->imask &= ~ATH9K_INT_TSFOOR;
3045
3046 ath9k_hw_set_interrupts(ah);
3047 -
3048 - /* Set up ANI */
3049 - if (iter_data.naps > 0) {
3050 - sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
3051 -
3052 - if (!common->disable_ani) {
3053 - set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
3054 - ath_start_ani(common);
3055 - }
3056 -
3057 - } else {
3058 - clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
3059 - del_timer_sync(&common->ani.timer);
3060 - }
3061 -}
3062 -
3063 -/* Called with sc->mutex held, vif counts set up properly. */
3064 -static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
3065 - struct ieee80211_vif *vif)
3066 -{
3067 - struct ath_softc *sc = hw->priv;
3068 -
3069 - ath9k_calculate_summary_state(hw, vif);
3070 -
3071 - if (ath9k_uses_beacons(vif->type)) {
3072 - /* Reserve a beacon slot for the vif */
3073 - ath9k_set_beaconing_status(sc, false);
3074 - ath_beacon_alloc(sc, vif);
3075 - ath9k_set_beaconing_status(sc, true);
3076 - }
3077 }
3078
3079 static int ath9k_add_interface(struct ieee80211_hw *hw,
3080 @@ -1032,7 +989,10 @@ static int ath9k_add_interface(struct ie
3081
3082 sc->nvifs++;
3083
3084 - ath9k_do_vif_add_setup(hw, vif);
3085 + ath9k_calculate_summary_state(hw, vif);
3086 + if (ath9k_uses_beacons(vif->type))
3087 + ath9k_beacon_assign_slot(sc, vif);
3088 +
3089 out:
3090 mutex_unlock(&sc->mutex);
3091 ath9k_ps_restore(sc);
3092 @@ -1049,6 +1009,7 @@ static int ath9k_change_interface(struct
3093 int ret = 0;
3094
3095 ath_dbg(common, CONFIG, "Change Interface\n");
3096 +
3097 mutex_lock(&sc->mutex);
3098 ath9k_ps_wakeup(sc);
3099
3100 @@ -1061,15 +1022,16 @@ static int ath9k_change_interface(struct
3101 }
3102 }
3103
3104 - /* Clean up old vif stuff */
3105 if (ath9k_uses_beacons(vif->type))
3106 - ath9k_reclaim_beacon(sc, vif);
3107 + ath9k_beacon_remove_slot(sc, vif);
3108
3109 - /* Add new settings */
3110 vif->type = new_type;
3111 vif->p2p = p2p;
3112
3113 - ath9k_do_vif_add_setup(hw, vif);
3114 + ath9k_calculate_summary_state(hw, vif);
3115 + if (ath9k_uses_beacons(vif->type))
3116 + ath9k_beacon_assign_slot(sc, vif);
3117 +
3118 out:
3119 ath9k_ps_restore(sc);
3120 mutex_unlock(&sc->mutex);
3121 @@ -1089,9 +1051,8 @@ static void ath9k_remove_interface(struc
3122
3123 sc->nvifs--;
3124
3125 - /* Reclaim beacon resources */
3126 if (ath9k_uses_beacons(vif->type))
3127 - ath9k_reclaim_beacon(sc, vif);
3128 + ath9k_beacon_remove_slot(sc, vif);
3129
3130 ath9k_calculate_summary_state(hw, NULL);
3131
3132 @@ -1388,21 +1349,18 @@ static int ath9k_conf_tx(struct ieee8021
3133 qi.tqi_aifs = params->aifs;
3134 qi.tqi_cwmin = params->cw_min;
3135 qi.tqi_cwmax = params->cw_max;
3136 - qi.tqi_burstTime = params->txop;
3137 + qi.tqi_burstTime = params->txop * 32;
3138
3139 ath_dbg(common, CONFIG,
3140 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3141 queue, txq->axq_qnum, params->aifs, params->cw_min,
3142 params->cw_max, params->txop);
3143
3144 + ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
3145 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
3146 if (ret)
3147 ath_err(common, "TXQ Update failed\n");
3148
3149 - if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
3150 - if (queue == WME_AC_BE && !ret)
3151 - ath_beaconq_config(sc);
3152 -
3153 mutex_unlock(&sc->mutex);
3154 ath9k_ps_restore(sc);
3155
3156 @@ -1471,85 +1429,36 @@ static int ath9k_set_key(struct ieee8021
3157
3158 return ret;
3159 }
3160 -static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
3161 +
3162 +static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
3163 {
3164 struct ath_softc *sc = data;
3165 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
3166 - struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
3167 struct ath_vif *avp = (void *)vif->drv_priv;
3168 + struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
3169 unsigned long flags;
3170 - /*
3171 - * Skip iteration if primary station vif's bss info
3172 - * was not changed
3173 - */
3174 +
3175 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
3176 return;
3177
3178 if (bss_conf->assoc) {
3179 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
3180 avp->primary_sta_vif = true;
3181 +
3182 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3183 common->curaid = bss_conf->aid;
3184 ath9k_hw_write_associd(sc->sc_ah);
3185 - ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
3186 - bss_conf->aid, common->curbssid);
3187 - ath_beacon_config(sc, vif);
3188 - /*
3189 - * Request a re-configuration of Beacon related timers
3190 - * on the receipt of the first Beacon frame (i.e.,
3191 - * after time sync with the AP).
3192 - */
3193 - spin_lock_irqsave(&sc->sc_pm_lock, flags);
3194 - sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
3195 - spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3196
3197 - /* Reset rssi stats */
3198 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
3199 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
3200
3201 - ath_start_rx_poll(sc, 3);
3202 -
3203 - if (!common->disable_ani) {
3204 - set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
3205 - ath_start_ani(common);
3206 - }
3207 -
3208 - }
3209 -}
3210 -
3211 -static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
3212 -{
3213 - struct ath_common *common = ath9k_hw_common(sc->sc_ah);
3214 - struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
3215 - struct ath_vif *avp = (void *)vif->drv_priv;
3216 -
3217 - if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
3218 - return;
3219 -
3220 - /* Reconfigure bss info */
3221 - if (avp->primary_sta_vif && !bss_conf->assoc) {
3222 - ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
3223 - common->curaid, common->curbssid);
3224 - clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
3225 - clear_bit(SC_OP_BEACONS, &sc->sc_flags);
3226 - avp->primary_sta_vif = false;
3227 - memset(common->curbssid, 0, ETH_ALEN);
3228 - common->curaid = 0;
3229 - }
3230 -
3231 - ieee80211_iterate_active_interfaces_atomic(
3232 - sc->hw, ath9k_bss_iter, sc);
3233 + spin_lock_irqsave(&sc->sc_pm_lock, flags);
3234 + sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
3235 + spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3236
3237 - /*
3238 - * None of station vifs are associated.
3239 - * Clear bssid & aid
3240 - */
3241 - if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
3242 - ath9k_hw_write_associd(sc->sc_ah);
3243 - clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
3244 - del_timer_sync(&common->ani.timer);
3245 - del_timer_sync(&sc->rx_poll_timer);
3246 - memset(&sc->caldata, 0, sizeof(sc->caldata));
3247 + ath_dbg(common, CONFIG,
3248 + "Primary Station interface: %pM, BSSID: %pM\n",
3249 + vif->addr, common->curbssid);
3250 }
3251 }
3252
3253 @@ -1558,6 +1467,11 @@ static void ath9k_bss_info_changed(struc
3254 struct ieee80211_bss_conf *bss_conf,
3255 u32 changed)
3256 {
3257 +#define CHECK_ANI \
3258 + (BSS_CHANGED_ASSOC | \
3259 + BSS_CHANGED_IBSS | \
3260 + BSS_CHANGED_BEACON_ENABLED)
3261 +
3262 struct ath_softc *sc = hw->priv;
3263 struct ath_hw *ah = sc->sc_ah;
3264 struct ath_common *common = ath9k_hw_common(ah);
3265 @@ -1568,53 +1482,43 @@ static void ath9k_bss_info_changed(struc
3266 mutex_lock(&sc->mutex);
3267
3268 if (changed & BSS_CHANGED_ASSOC) {
3269 - ath9k_config_bss(sc, vif);
3270 + ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
3271 + bss_conf->bssid, bss_conf->assoc);
3272
3273 - ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
3274 - common->curbssid, common->curaid);
3275 + /*
3276 + * Do not do anything when the opmode is not STATION.
3277 + */
3278 + if (ah->opmode == NL80211_IFTYPE_STATION) {
3279 + if (avp->primary_sta_vif && !bss_conf->assoc) {
3280 + clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
3281 + clear_bit(SC_OP_BEACONS, &sc->sc_flags);
3282 + avp->primary_sta_vif = false;
3283 + }
3284 +
3285 + ieee80211_iterate_active_interfaces_atomic(sc->hw,
3286 + ath9k_bss_assoc_iter, sc);
3287 +
3288 + if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
3289 + memset(common->curbssid, 0, ETH_ALEN);
3290 + common->curaid = 0;
3291 + ath9k_hw_write_associd(sc->sc_ah);
3292 + }
3293 + }
3294 }
3295
3296 if (changed & BSS_CHANGED_IBSS) {
3297 - /* There can be only one vif available */
3298 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3299 common->curaid = bss_conf->aid;
3300 ath9k_hw_write_associd(sc->sc_ah);
3301 -
3302 - if (bss_conf->ibss_joined) {
3303 - sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
3304 -
3305 - if (!common->disable_ani) {
3306 - set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
3307 - ath_start_ani(common);
3308 - }
3309 -
3310 - } else {
3311 - clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
3312 - del_timer_sync(&common->ani.timer);
3313 - del_timer_sync(&sc->rx_poll_timer);
3314 - }
3315 }
3316
3317 - /*
3318 - * In case of AP mode, the HW TSF has to be reset
3319 - * when the beacon interval changes.
3320 - */
3321 - if ((changed & BSS_CHANGED_BEACON_INT) &&
3322 - (vif->type == NL80211_IFTYPE_AP))
3323 - set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
3324 -
3325 - /* Configure beaconing (AP, IBSS, MESH) */
3326 - if (ath9k_uses_beacons(vif->type) &&
3327 - ((changed & BSS_CHANGED_BEACON) ||
3328 - (changed & BSS_CHANGED_BEACON_ENABLED) ||
3329 - (changed & BSS_CHANGED_BEACON_INT))) {
3330 - ath9k_set_beaconing_status(sc, false);
3331 - if (bss_conf->enable_beacon)
3332 - ath_beacon_alloc(sc, vif);
3333 - else
3334 - avp->is_bslot_active = false;
3335 - ath_beacon_config(sc, vif);
3336 - ath9k_set_beaconing_status(sc, true);
3337 + if ((changed & BSS_CHANGED_BEACON) ||
3338 + (changed & BSS_CHANGED_BEACON_ENABLED) ||
3339 + (changed & BSS_CHANGED_BEACON_INT)) {
3340 + if (ah->opmode == NL80211_IFTYPE_AP)
3341 + ath9k_set_tsfadjust(sc, vif);
3342 + if (ath9k_allow_beacon_config(sc, vif))
3343 + ath9k_beacon_config(sc, vif, changed);
3344 }
3345
3346 if (changed & BSS_CHANGED_ERP_SLOT) {
3347 @@ -1636,8 +1540,13 @@ static void ath9k_bss_info_changed(struc
3348 }
3349 }
3350
3351 + if (changed & CHECK_ANI)
3352 + ath_check_ani(sc);
3353 +
3354 mutex_unlock(&sc->mutex);
3355 ath9k_ps_restore(sc);
3356 +
3357 +#undef CHECK_ANI
3358 }
3359
3360 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3361 @@ -1866,10 +1775,11 @@ static int ath9k_tx_last_beacon(struct i
3362 if (!vif)
3363 return 0;
3364
3365 - avp = (void *)vif->drv_priv;
3366 - if (!avp->is_bslot_active)
3367 + if (!vif->bss_conf.enable_beacon)
3368 return 0;
3369
3370 + avp = (void *)vif->drv_priv;
3371 +
3372 if (!sc->beacon.tx_processed && !edma) {
3373 tasklet_disable(&sc->bcon_tasklet);
3374
3375 @@ -1923,12 +1833,29 @@ static u32 fill_chainmask(u32 cap, u32 n
3376 return filled;
3377 }
3378
3379 +static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
3380 +{
3381 + switch (val & 0x7) {
3382 + case 0x1:
3383 + case 0x3:
3384 + case 0x7:
3385 + return true;
3386 + case 0x2:
3387 + return (ah->caps.rx_chainmask == 1);
3388 + default:
3389 + return false;
3390 + }
3391 +}
3392 +
3393 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
3394 {
3395 struct ath_softc *sc = hw->priv;
3396 struct ath_hw *ah = sc->sc_ah;
3397
3398 - if (!rx_ant || !tx_ant)
3399 + if (ah->caps.rx_chainmask != 1)
3400 + rx_ant |= tx_ant;
3401 +
3402 + if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
3403 return -EINVAL;
3404
3405 sc->ant_rx = rx_ant;
3406 --- a/drivers/net/wireless/ath/ath9k/mci.c
3407 +++ b/drivers/net/wireless/ath/ath9k/mci.c
3408 @@ -202,7 +202,7 @@ static void ath_mci_cal_msg(struct ath_s
3409 case MCI_GPM_BT_CAL_REQ:
3410 if (mci_hw->bt_state == MCI_BT_AWAKE) {
3411 ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START);
3412 - ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
3413 + ath9k_queue_reset(sc, RESET_TYPE_MCI);
3414 }
3415 ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
3416 break;
3417 --- a/drivers/net/wireless/ath/ath9k/recv.c
3418 +++ b/drivers/net/wireless/ath/ath9k/recv.c
3419 @@ -553,7 +553,7 @@ static void ath_rx_ps_beacon(struct ath_
3420 sc->ps_flags &= ~PS_BEACON_SYNC;
3421 ath_dbg(common, PS,
3422 "Reconfigure Beacon timers based on timestamp from the AP\n");
3423 - ath_set_beacon(sc);
3424 + ath9k_set_beacon(sc);
3425 }
3426
3427 if (ath_beacon_dtim_pending_cab(skb)) {
3428 @@ -1044,7 +1044,6 @@ int ath_rx_tasklet(struct ath_softc *sc,
3429 struct ieee80211_hw *hw = sc->hw;
3430 struct ieee80211_hdr *hdr;
3431 int retval;
3432 - bool decrypt_error = false;
3433 struct ath_rx_status rs;
3434 enum ath9k_rx_qtype qtype;
3435 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
3436 @@ -1066,6 +1065,7 @@ int ath_rx_tasklet(struct ath_softc *sc,
3437 tsf_lower = tsf & 0xffffffff;
3438
3439 do {
3440 + bool decrypt_error = false;
3441 /* If handling rx interrupt and flush is in progress => exit */
3442 if (test_bit(SC_OP_RXFLUSH, &sc->sc_flags) && (flush == 0))
3443 break;
3444 --- a/drivers/net/wireless/ath/ath9k/xmit.c
3445 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
3446 @@ -29,6 +29,8 @@
3447 #define HT_LTF(_ns) (4 * (_ns))
3448 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
3449 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
3450 +#define TIME_SYMBOLS(t) ((t) >> 2)
3451 +#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
3452 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
3453 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
3454
3455 @@ -74,33 +76,6 @@ enum {
3456 MCS_HT40_SGI,
3457 };
3458
3459 -static int ath_max_4ms_framelen[4][32] = {
3460 - [MCS_HT20] = {
3461 - 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
3462 - 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
3463 - 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
3464 - 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
3465 - },
3466 - [MCS_HT20_SGI] = {
3467 - 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
3468 - 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
3469 - 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
3470 - 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
3471 - },
3472 - [MCS_HT40] = {
3473 - 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
3474 - 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
3475 - 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
3476 - 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
3477 - },
3478 - [MCS_HT40_SGI] = {
3479 - 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
3480 - 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
3481 - 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
3482 - 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
3483 - }
3484 -};
3485 -
3486 /*********************/
3487 /* Aggregation logic */
3488 /*********************/
3489 @@ -614,10 +589,8 @@ static void ath_tx_complete_aggr(struct
3490
3491 rcu_read_unlock();
3492
3493 - if (needreset) {
3494 - RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
3495 - ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
3496 - }
3497 + if (needreset)
3498 + ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
3499 }
3500
3501 static bool ath_lookup_legacy(struct ath_buf *bf)
3502 @@ -650,6 +623,7 @@ static u32 ath_lookup_rate(struct ath_so
3503 struct ieee80211_tx_rate *rates;
3504 u32 max_4ms_framelen, frmlen;
3505 u16 aggr_limit, bt_aggr_limit, legacy = 0;
3506 + int q = tid->ac->txq->mac80211_qnum;
3507 int i;
3508
3509 skb = bf->bf_mpdu;
3510 @@ -658,8 +632,7 @@ static u32 ath_lookup_rate(struct ath_so
3511
3512 /*