26baa49ce1594954d239bbb7bab67de1e1caf6ba
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 302-rt2x00-Implement-support-for-rt2800pci.patch
1 From cdd4310f4631d5a41c2c6ab09bbddb558c26587f Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Wed, 4 Feb 2009 20:43:00 +0100
4 Subject: [PATCH] rt2x00: Implement support for rt2800pci
5
6 Add support for the rt2800pci chipset.
7
8 Includes various patches from Mattias, Mark and Felix.
9
10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
11 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
12 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
13 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
14 ---
15 drivers/net/wireless/rt2x00/Kconfig | 15 +
16 drivers/net/wireless/rt2x00/Makefile | 1 +
17 drivers/net/wireless/rt2x00/rt2800pci.c | 2785 +++++++++++++++++++++++++++++++
18 drivers/net/wireless/rt2x00/rt2800pci.h | 1877 +++++++++++++++++++++
19 drivers/net/wireless/rt2x00/rt2x00.h | 4 +
20 5 files changed, 4682 insertions(+), 0 deletions(-)
21 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
22 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
23
24 --- a/drivers/net/wireless/rt2x00/Makefile
25 +++ b/drivers/net/wireless/rt2x00/Makefile
26 @@ -16,5 +16,6 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
27 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
28 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
29 obj-$(CONFIG_RT61PCI) += rt61pci.o
30 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
31 obj-$(CONFIG_RT2500USB) += rt2500usb.o
32 obj-$(CONFIG_RT73USB) += rt73usb.o
33 --- /dev/null
34 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
35 @@ -0,0 +1,2785 @@
36 +/*
37 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
38 + <http://rt2x00.serialmonkey.com>
39 +
40 + This program is free software; you can redistribute it and/or modify
41 + it under the terms of the GNU General Public License as published by
42 + the Free Software Foundation; either version 2 of the License, or
43 + (at your option) any later version.
44 +
45 + This program is distributed in the hope that it will be useful,
46 + but WITHOUT ANY WARRANTY; without even the implied warranty of
47 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48 + GNU General Public License for more details.
49 +
50 + You should have received a copy of the GNU General Public License
51 + along with this program; if not, write to the
52 + Free Software Foundation, Inc.,
53 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
54 + */
55 +
56 +/*
57 + Module: rt2800pci
58 + Abstract: rt2800pci device specific routines.
59 + Supported chipsets: RT2800E & RT2800ED.
60 + */
61 +
62 +#include <linux/crc-ccitt.h>
63 +#include <linux/delay.h>
64 +#include <linux/etherdevice.h>
65 +#include <linux/init.h>
66 +#include <linux/kernel.h>
67 +#include <linux/module.h>
68 +#include <linux/pci.h>
69 +#include <linux/eeprom_93cx6.h>
70 +
71 +#include "rt2x00.h"
72 +#include "rt2x00pci.h"
73 +#include "rt2800pci.h"
74 +
75 +/*
76 + * Allow hardware encryption to be disabled.
77 + */
78 +static int modparam_nohwcrypt = 0;
79 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
80 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
81 +
82 +/*
83 + * Register access.
84 + * BBP and RF register require indirect register access,
85 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
86 + * These indirect registers work with busy bits,
87 + * and we will try maximal REGISTER_BUSY_COUNT times to access
88 + * the register while taking a REGISTER_BUSY_DELAY us delay
89 + * between each attampt. When the busy bit is still set at that time,
90 + * the access attempt is considered to have failed,
91 + * and we will print an error.
92 + */
93 +#define WAIT_FOR_BBP(__dev, __reg) \
94 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
95 +#define WAIT_FOR_RF(__dev, __reg) \
96 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
97 +#define WAIT_FOR_MCU(__dev, __reg) \
98 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
99 + H2M_MAILBOX_CSR_OWNER, (__reg))
100 +
101 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
102 + const unsigned int word, const u8 value)
103 +{
104 + u32 reg;
105 +
106 + mutex_lock(&rt2x00dev->csr_mutex);
107 +
108 + /*
109 + * Wait until the BBP becomes available, afterwards we
110 + * can safely write the new data into the register.
111 + */
112 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
113 + reg = 0;
114 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
115 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
116 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
117 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
118 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
119 +
120 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
121 + }
122 +
123 + mutex_unlock(&rt2x00dev->csr_mutex);
124 +}
125 +
126 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
127 + const unsigned int word, u8 *value)
128 +{
129 + u32 reg;
130 +
131 + mutex_lock(&rt2x00dev->csr_mutex);
132 +
133 + /*
134 + * Wait until the BBP becomes available, afterwards we
135 + * can safely write the read request into the register.
136 + * After the data has been written, we wait until hardware
137 + * returns the correct value, if at any time the register
138 + * doesn't become available in time, reg will be 0xffffffff
139 + * which means we return 0xff to the caller.
140 + */
141 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
142 + reg = 0;
143 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
144 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
145 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
146 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
147 +
148 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
149 +
150 + WAIT_FOR_BBP(rt2x00dev, &reg);
151 + }
152 +
153 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
154 +
155 + mutex_unlock(&rt2x00dev->csr_mutex);
156 +}
157 +
158 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
159 + const unsigned int word, const u32 value)
160 +{
161 + u32 reg;
162 +
163 + if (!word)
164 + return;
165 +
166 + mutex_lock(&rt2x00dev->csr_mutex);
167 +
168 + /*
169 + * Wait until the RF becomes available, afterwards we
170 + * can safely write the new data into the register.
171 + */
172 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
173 + reg = 0;
174 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
175 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
176 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
177 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
178 +
179 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
180 + rt2x00_rf_write(rt2x00dev, word, value);
181 + }
182 +
183 + mutex_unlock(&rt2x00dev->csr_mutex);
184 +}
185 +
186 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
187 + const u8 command, const u8 token,
188 + const u8 arg0, const u8 arg1)
189 +{
190 + u32 reg;
191 +
192 + mutex_lock(&rt2x00dev->csr_mutex);
193 +
194 + /*
195 + * Wait until the MCU becomes available, afterwards we
196 + * can safely write the new data into the register.
197 + */
198 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
199 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
200 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
201 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
202 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
203 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
204 +
205 + reg = 0;
206 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
207 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
208 + }
209 +
210 + mutex_unlock(&rt2x00dev->csr_mutex);
211 +}
212 +
213 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
214 +{
215 + struct rt2x00_dev *rt2x00dev = eeprom->data;
216 + u32 reg;
217 +
218 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
219 +
220 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
221 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
222 + eeprom->reg_data_clock =
223 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
224 + eeprom->reg_chip_select =
225 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
226 +}
227 +
228 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
229 +{
230 + struct rt2x00_dev *rt2x00dev = eeprom->data;
231 + u32 reg = 0;
232 +
233 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
234 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
235 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
236 + !!eeprom->reg_data_clock);
237 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
238 + !!eeprom->reg_chip_select);
239 +
240 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
241 +}
242 +
243 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
244 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
245 + .owner = THIS_MODULE,
246 + .csr = {
247 + .read = rt2x00pci_register_read,
248 + .write = rt2x00pci_register_write,
249 + .flags = RT2X00DEBUGFS_OFFSET,
250 + .word_base = CSR_REG_BASE,
251 + .word_size = sizeof(u32),
252 + .word_count = CSR_REG_SIZE / sizeof(u32),
253 + },
254 + .eeprom = {
255 + .read = rt2x00_eeprom_read,
256 + .write = rt2x00_eeprom_write,
257 + .word_base = EEPROM_BASE,
258 + .word_size = sizeof(u16),
259 + .word_count = EEPROM_SIZE / sizeof(u16),
260 + },
261 + .bbp = {
262 + .read = rt2800pci_bbp_read,
263 + .write = rt2800pci_bbp_write,
264 + .word_base = BBP_BASE,
265 + .word_size = sizeof(u8),
266 + .word_count = BBP_SIZE / sizeof(u8),
267 + },
268 + .rf = {
269 + .read = rt2x00_rf_read,
270 + .write = rt2800pci_rf_write,
271 + .word_base = RF_BASE,
272 + .word_size = sizeof(u32),
273 + .word_count = RF_SIZE / sizeof(u32),
274 + },
275 +};
276 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
277 +
278 +#ifdef CONFIG_RT2X00_LIB_RFKILL
279 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
280 +{
281 + u32 reg;
282 +
283 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
284 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
285 +}
286 +#else
287 +#define rt2800pci_rfkill_poll NULL
288 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
289 +
290 +#ifdef CONFIG_RT2X00_LIB_LEDS
291 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
292 + enum led_brightness brightness)
293 +{
294 + struct rt2x00_led *led =
295 + container_of(led_cdev, struct rt2x00_led, led_dev);
296 + unsigned int enabled = brightness != LED_OFF;
297 + unsigned int bg_mode =
298 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
299 + unsigned int polarity =
300 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
301 + EEPROM_FREQ_LED_POLARITY);
302 + unsigned int ledmode =
303 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
304 + EEPROM_FREQ_LED_MODE);
305 +
306 + if (led->type == LED_TYPE_RADIO) {
307 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
308 + enabled ? 0x20 : 0);
309 + } else if (led->type == LED_TYPE_ASSOC) {
310 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
311 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
312 + } else if (led->type == LED_TYPE_QUALITY) {
313 + /*
314 + * The brightness is divided into 6 levels (0 - 5),
315 + * The specs tell us the following levels:
316 + * 0, 1 ,3, 7, 15, 31
317 + * to determine the level in a simple way we can simply
318 + * work with bitshifting:
319 + * (1 << level) - 1
320 + */
321 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
322 + (1 << brightness / (LED_FULL / 6)) - 1,
323 + polarity);
324 + }
325 +}
326 +
327 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
328 + unsigned long *delay_on,
329 + unsigned long *delay_off)
330 +{
331 + struct rt2x00_led *led =
332 + container_of(led_cdev, struct rt2x00_led, led_dev);
333 + u32 reg;
334 +
335 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
336 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
337 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
338 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
339 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
340 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
341 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
342 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
343 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
344 +
345 + return 0;
346 +}
347 +
348 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
349 + struct rt2x00_led *led,
350 + enum led_type type)
351 +{
352 + led->rt2x00dev = rt2x00dev;
353 + led->type = type;
354 + led->led_dev.brightness_set = rt2800pci_brightness_set;
355 + led->led_dev.blink_set = rt2800pci_blink_set;
356 + led->flags = LED_INITIALIZED;
357 +}
358 +#endif /* CONFIG_RT2X00_LIB_LEDS */
359 +
360 +/*
361 + * Configuration handlers.
362 + */
363 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
364 + struct rt2x00lib_crypto *crypto,
365 + struct ieee80211_key_conf *key)
366 +{
367 + struct mac_wcid_entry wcid_entry;
368 + struct mac_iveiv_entry iveiv_entry;
369 + u32 offset;
370 + u32 reg;
371 +
372 + offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
373 +
374 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
375 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
376 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
377 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, crypto->cipher);
378 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
379 + (crypto->cmd == SET_KEY) * crypto->bssidx);
380 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
381 + rt2x00pci_register_write(rt2x00dev, offset, reg);
382 +
383 + offset = MAC_IVEIV_ENTRY(crypto->aid);
384 +
385 + memset(&iveiv_entry, 0, sizeof(iveiv_entry));
386 + if ((crypto->cipher == CIPHER_TKIP) ||
387 + (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
388 + (crypto->cipher == CIPHER_AES))
389 + iveiv_entry.iv[3] |= 0x20;
390 + iveiv_entry.iv[3] |= key->keyidx << 6;
391 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
392 + &iveiv_entry, sizeof(iveiv_entry));
393 +
394 + offset = MAC_WCID_ENTRY(crypto->aid);
395 +
396 + memset(&wcid_entry, 0, sizeof(wcid_entry));
397 + if (crypto->cmd == SET_KEY)
398 + memcpy(&wcid_entry, crypto->address, ETH_ALEN);
399 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
400 + &wcid_entry, sizeof(wcid_entry));
401 +}
402 +
403 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
404 + struct rt2x00lib_crypto *crypto,
405 + struct ieee80211_key_conf *key)
406 +{
407 + struct hw_key_entry key_entry;
408 + struct rt2x00_field32 field;
409 + u32 offset;
410 + u32 reg;
411 +
412 + if (crypto->cmd == SET_KEY) {
413 + key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
414 +
415 + memcpy(key_entry.key, crypto->key,
416 + sizeof(key_entry.key));
417 + memcpy(key_entry.tx_mic, crypto->tx_mic,
418 + sizeof(key_entry.tx_mic));
419 + memcpy(key_entry.rx_mic, crypto->rx_mic,
420 + sizeof(key_entry.rx_mic));
421 +
422 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
423 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
424 + &key_entry, sizeof(key_entry));
425 + }
426 +
427 + /*
428 + * The cipher types are stored over multiple registers
429 + * starting with SHARED_KEY_MODE_BASE each word will have
430 + * 32 bits and contains the cipher types for 2 bssidx each.
431 + * Using the correct defines correctly will cause overhead,
432 + * so just calculate the correct offset.
433 + */
434 + field.bit_offset = (4 * key->keyidx);
435 + field.bit_mask = 0x7 << field.bit_offset;
436 +
437 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
438 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
439 + rt2x00_set_field32(&reg, field,
440 + (crypto->cmd == SET_KEY) * crypto->cipher);
441 + rt2x00pci_register_write(rt2x00dev, offset, reg);
442 +
443 + /*
444 + * Update WCID information
445 + */
446 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
447 +
448 + return 0;
449 +}
450 +
451 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
452 + struct rt2x00lib_crypto *crypto,
453 + struct ieee80211_key_conf *key)
454 +{
455 + struct hw_key_entry key_entry;
456 + u32 offset;
457 +
458 + if (crypto->cmd == SET_KEY) {
459 + /*
460 + * 1 pairwise key is possible per AID, this means that the AID
461 + * equals our hw_key_idx.
462 + */
463 + key->hw_key_idx = crypto->aid;
464 +
465 + memcpy(key_entry.key, crypto->key,
466 + sizeof(key_entry.key));
467 + memcpy(key_entry.tx_mic, crypto->tx_mic,
468 + sizeof(key_entry.tx_mic));
469 + memcpy(key_entry.rx_mic, crypto->rx_mic,
470 + sizeof(key_entry.rx_mic));
471 +
472 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
473 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
474 + &key_entry, sizeof(key_entry));
475 + }
476 +
477 + /*
478 + * Update WCID information
479 + */
480 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
481 +
482 + return 0;
483 +}
484 +
485 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
486 + const unsigned int filter_flags)
487 +{
488 + u32 reg;
489 +
490 + /*
491 + * Start configuration steps.
492 + * Note that the version error will always be dropped
493 + * and broadcast frames will always be accepted since
494 + * there is no filter for it at this time.
495 + */
496 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
497 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
498 + !(filter_flags & FIF_FCSFAIL));
499 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
500 + !(filter_flags & FIF_PLCPFAIL));
501 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
502 + !(filter_flags & FIF_PROMISC_IN_BSS));
503 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
504 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
505 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
506 + !(filter_flags & FIF_ALLMULTI));
507 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
508 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
509 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
510 + !(filter_flags & FIF_CONTROL));
511 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
512 + !(filter_flags & FIF_CONTROL));
513 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
514 + !(filter_flags & FIF_CONTROL));
515 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
516 + !(filter_flags & FIF_CONTROL));
517 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
518 + !(filter_flags & FIF_CONTROL));
519 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
520 + !(filter_flags & FIF_CONTROL));
521 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
522 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
523 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
524 + !(filter_flags & FIF_CONTROL));
525 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
526 +}
527 +
528 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
529 + struct rt2x00_intf *intf,
530 + struct rt2x00intf_conf *conf,
531 + const unsigned int flags)
532 +{
533 + unsigned int beacon_base;
534 + u32 reg;
535 +
536 + if (flags & CONFIG_UPDATE_TYPE) {
537 + /*
538 + * Clear current synchronisation setup.
539 + * For the Beacon base registers we only need to clear
540 + * the first byte since that byte contains the VALID and OWNER
541 + * bits which (when set to 0) will invalidate the entire beacon.
542 + */
543 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
544 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
545 +
546 + /*
547 + * Enable synchronisation.
548 + */
549 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
550 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
551 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
552 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
553 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
554 + }
555 +
556 + if (flags & CONFIG_UPDATE_MAC) {
557 + reg = le32_to_cpu(conf->mac[1]);
558 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
559 + conf->mac[1] = cpu_to_le32(reg);
560 +
561 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
562 + conf->mac, sizeof(conf->mac));
563 + }
564 +
565 + if (flags & CONFIG_UPDATE_BSSID) {
566 + reg = le32_to_cpu(conf->bssid[1]);
567 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
568 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
569 + conf->bssid[1] = cpu_to_le32(reg);
570 +
571 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
572 + conf->bssid, sizeof(conf->bssid));
573 + }
574 +}
575 +
576 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
577 + struct rt2x00lib_erp *erp)
578 +{
579 + u32 reg;
580 +
581 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
582 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
583 + DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
584 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
585 +
586 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
587 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
588 + !!erp->short_preamble);
589 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
590 + !!erp->short_preamble);
591 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
592 +
593 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
594 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
595 + erp->cts_protection ? 2 : 0);
596 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
597 +
598 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
599 + erp->basic_rates);
600 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
601 +
602 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
603 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
604 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
605 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
606 +
607 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
608 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
609 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
610 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
611 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
612 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
613 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
614 +}
615 +
616 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
617 + struct antenna_setup *ant)
618 +{
619 + u16 eeprom;
620 + u8 r1;
621 + u8 r3;
622 +
623 + /*
624 + * FIXME: Use requested antenna configuration.
625 + */
626 +
627 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
628 +
629 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
630 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
631 +
632 + /*
633 + * Configure the TX antenna.
634 + */
635 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
636 + case 1:
637 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
638 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
639 + break;
640 + case 2:
641 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 16);
642 + break;
643 + case 3:
644 + /* Do nothing */
645 + break;
646 + }
647 +
648 + /*
649 + * Configure the RX antenna.
650 + */
651 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
652 + case 1:
653 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
654 + break;
655 + case 2:
656 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
657 + break;
658 + case 3:
659 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
660 + break;
661 + }
662 +
663 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
664 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
665 +}
666 +
667 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
668 + struct rt2x00lib_conf *libconf)
669 +{
670 + u16 eeprom;
671 + short lna_gain;
672 +
673 + if (libconf->rf.channel <= 14) {
674 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
675 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
676 + } else if (libconf->rf.channel <= 64) {
677 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
678 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
679 + } else if (libconf->rf.channel <= 128) {
680 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
681 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
682 + } else {
683 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
684 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
685 + }
686 +
687 + rt2x00dev->lna_gain = lna_gain;
688 +}
689 +
690 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
691 + struct rf_channel *rf,
692 + struct channel_info *info)
693 +{
694 + u32 reg;
695 + unsigned int tx_pin;
696 + u16 eeprom;
697 +
698 + tx_pin = 0;
699 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
700 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
701 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
702 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
703 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
704 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
705 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
706 +
707 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
708 +
709 + /*
710 + * Determine antenna settings from EEPROM
711 + */
712 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
713 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
714 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
715 + /* Turn off unused PA or LNA when only 1T or 1R */
716 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
717 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
718 + }
719 +
720 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
721 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
722 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
723 + /* Turn off unused PA or LNA when only 1T or 1R */
724 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
725 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
726 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
727 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
728 +
729 + if (rf->channel > 14) {
730 + /*
731 + * When TX power is below 0, we should increase it by 7 to
732 + * make it a positive value (Minumum value is -7).
733 + * However this means that values between 0 and 7 have
734 + * double meaning, and we should set a 7DBm boost flag.
735 + */
736 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
737 + (info->tx_power1 >= 0));
738 +
739 + if (info->tx_power1 < 0)
740 + info->tx_power1 += 7;
741 +
742 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
743 + TXPOWER_A_TO_DEV(info->tx_power1));
744 +
745 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
746 + (info->tx_power2 >= 0));
747 +
748 + if (info->tx_power2 < 0)
749 + info->tx_power2 += 7;
750 +
751 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
752 + TXPOWER_A_TO_DEV(info->tx_power2));
753 +
754 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
755 + } else {
756 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
757 + TXPOWER_G_TO_DEV(info->tx_power1));
758 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
759 + TXPOWER_G_TO_DEV(info->tx_power2));
760 +
761 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
762 + }
763 +
764 + rt2x00_set_field32(&rf->rf4, RF4_BW40,
765 + test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
766 +
767 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
768 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
769 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
770 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
771 +
772 + udelay(200);
773 +
774 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
775 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
776 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
777 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
778 +
779 + udelay(200);
780 +
781 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
782 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
783 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
784 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
785 +
786 + /*
787 + * Change BBP settings
788 + */
789 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
790 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
791 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
792 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
793 +
794 + if (rf->channel <= 14) {
795 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
796 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
797 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
798 + } else {
799 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
800 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
801 + }
802 +
803 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
804 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
805 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
806 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
807 + } else {
808 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
809 +
810 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
811 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
812 + else
813 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
814 +
815 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
816 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
817 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
818 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
819 + }
820 +
821 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
822 +
823 + msleep(1);
824 +}
825 +
826 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
827 + const int txpower)
828 +{
829 + u32 reg;
830 + u32 value = TXPOWER_G_TO_DEV(txpower);
831 + u8 r1;
832 +
833 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
834 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
835 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
836 +
837 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
838 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
839 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
840 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
841 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
842 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
843 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
844 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
845 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
846 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
847 +
848 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
849 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
850 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
851 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
852 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
853 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
854 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
855 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
856 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
857 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
858 +
859 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
860 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
861 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
862 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
863 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
864 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
865 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
866 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
867 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
868 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
869 +
870 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
871 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
872 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
873 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
874 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
875 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
876 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
877 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
878 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
879 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
880 +
881 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
882 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
883 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
884 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
885 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
886 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
887 +}
888 +
889 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
890 + struct rt2x00lib_conf *libconf)
891 +{
892 + u32 reg;
893 +
894 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
895 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
896 + libconf->conf->short_frame_max_tx_count);
897 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
898 + libconf->conf->long_frame_max_tx_count);
899 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
900 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
901 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
902 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
903 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
904 +}
905 +
906 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
907 + struct rt2x00lib_conf *libconf)
908 +{
909 + u32 reg;
910 +
911 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
912 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
913 + libconf->conf->beacon_int * 16);
914 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
915 +}
916 +
917 +static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
918 + struct rt2x00lib_conf *libconf)
919 +{
920 + enum dev_state state =
921 + (libconf->conf->flags & IEEE80211_CONF_PS) ?
922 + STATE_SLEEP : STATE_AWAKE;
923 + u32 reg;
924 +
925 + if (state == STATE_SLEEP) {
926 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
927 +
928 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
929 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
930 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
931 + libconf->conf->listen_interval - 1);
932 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
933 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
934 +
935 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
936 + } else {
937 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
938 +
939 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
940 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
941 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
942 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
943 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
944 + }
945 +}
946 +
947 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
948 + struct rt2x00lib_conf *libconf,
949 + const unsigned int flags)
950 +{
951 + /* Always recalculate LNA gain before changing configuration */
952 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
953 +
954 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
955 + rt2800pci_config_channel(rt2x00dev, &libconf->rf,
956 + &libconf->channel);
957 + if (flags & IEEE80211_CONF_CHANGE_POWER)
958 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
959 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
960 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
961 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
962 + rt2800pci_config_duration(rt2x00dev, libconf);
963 + if (flags & IEEE80211_CONF_CHANGE_PS)
964 + rt2800pci_config_ps(rt2x00dev, libconf);
965 +}
966 +
967 +/*
968 + * Link tuning
969 + */
970 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
971 + struct link_qual *qual)
972 +{
973 + u32 reg;
974 +
975 + /*
976 + * Update FCS error count from register.
977 + */
978 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
979 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
980 +}
981 +
982 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
983 +{
984 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
985 + return 0x2e + rt2x00dev->lna_gain;
986 +
987 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
988 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
989 + else
990 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
991 +}
992 +
993 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
994 + struct link_qual *qual, u8 vgc_level)
995 +{
996 + if (qual->vgc_level != vgc_level) {
997 + rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
998 + qual->vgc_level = vgc_level;
999 + qual->vgc_level_reg = vgc_level;
1000 + }
1001 +}
1002 +
1003 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1004 + struct link_qual *qual)
1005 +{
1006 + rt2800pci_set_vgc(rt2x00dev, qual,
1007 + rt2800pci_get_default_vgc(rt2x00dev));
1008 +}
1009 +
1010 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1011 + struct link_qual *qual, const u32 count)
1012 +{
1013 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1014 + return;
1015 +
1016 + /*
1017 + * When RSSI is better then -80 increase VGC level with 0x10
1018 + */
1019 + rt2800pci_set_vgc(rt2x00dev, qual,
1020 + rt2800pci_get_default_vgc(rt2x00dev) +
1021 + ((qual->rssi > -80) * 0x10));
1022 +}
1023 +
1024 +/*
1025 + * Firmware functions
1026 + */
1027 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1028 +{
1029 + return FIRMWARE_RT2860;
1030 +}
1031 +
1032 +static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1033 + const u8 *data, const size_t len)
1034 +{
1035 + u16 fw_crc;
1036 + u16 crc;
1037 +
1038 + /*
1039 + * Only support 8kb firmware files.
1040 + */
1041 + if (len != 8192)
1042 + return FW_BAD_LENGTH;
1043 +
1044 + /*
1045 + * The last 2 bytes in the firmware array are the crc checksum itself,
1046 + * this means that we should never pass those 2 bytes to the crc
1047 + * algorithm.
1048 + */
1049 + fw_crc = (data[len - 2] << 8 | data[len - 1]);
1050 +
1051 + /*
1052 + * Use the crc ccitt algorithm.
1053 + * This will return the same value as the legacy driver which
1054 + * used bit ordering reversion on the both the firmware bytes
1055 + * before input input as well as on the final output.
1056 + * Obviously using crc ccitt directly is much more efficient.
1057 + */
1058 + crc = crc_ccitt(~0, data, len - 2);
1059 +
1060 + /*
1061 + * There is a small difference between the crc-itu-t + bitrev and
1062 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1063 + * will be swapped, use swab16 to convert the crc to the correct
1064 + * value.
1065 + */
1066 + crc = swab16(crc);
1067 +
1068 + return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1069 +}
1070 +
1071 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1072 + const u8 *data, const size_t len)
1073 +{
1074 + unsigned int i;
1075 + u32 reg;
1076 +
1077 + /*
1078 + * Wait for stable hardware.
1079 + */
1080 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1081 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1082 + if (reg && reg != ~0)
1083 + break;
1084 + msleep(1);
1085 + }
1086 +
1087 + if (i == REGISTER_BUSY_COUNT) {
1088 + ERROR(rt2x00dev, "Unstable hardware.\n");
1089 + return -EBUSY;
1090 + }
1091 +
1092 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1093 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1094 +
1095 + /*
1096 + * Disable DMA, will be reenabled later when enabling
1097 + * the radio.
1098 + */
1099 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1100 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1101 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1102 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1103 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1104 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1105 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1106 +
1107 + /*
1108 + * enable Host program ram write selection
1109 + */
1110 + reg = 0;
1111 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1112 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1113 +
1114 + /*
1115 + * Write firmware to device.
1116 + */
1117 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1118 + data, len);
1119 +
1120 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1121 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1122 +
1123 + /*
1124 + * Wait for device to stabilize.
1125 + */
1126 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1127 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1128 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1129 + break;
1130 + msleep(1);
1131 + }
1132 +
1133 + if (i == REGISTER_BUSY_COUNT) {
1134 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1135 + return -EBUSY;
1136 + }
1137 +
1138 + /*
1139 + * Disable interrupts
1140 + */
1141 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1142 +
1143 + /*
1144 + * Initialize BBP R/W access agent
1145 + */
1146 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1147 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1148 +
1149 + return 0;
1150 +}
1151 +
1152 +/*
1153 + * Initialization functions.
1154 + */
1155 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1156 +{
1157 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1158 + u32 word;
1159 +
1160 + if (entry->queue->qid == QID_RX) {
1161 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1162 +
1163 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1164 + } else {
1165 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1166 +
1167 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1168 + }
1169 +}
1170 +
1171 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1172 +{
1173 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1174 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1175 + u32 word;
1176 +
1177 + if (entry->queue->qid == QID_RX) {
1178 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1179 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1180 + rt2x00_desc_write(entry_priv->desc, 0, word);
1181 +
1182 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1183 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1184 + rt2x00_desc_write(entry_priv->desc, 1, word);
1185 + } else {
1186 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1187 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1188 + rt2x00_desc_write(entry_priv->desc, 1, word);
1189 + }
1190 +}
1191 +
1192 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1193 +{
1194 + struct queue_entry_priv_pci *entry_priv;
1195 + u32 reg;
1196 +
1197 + /*
1198 + * Initialize registers.
1199 + */
1200 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1201 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1202 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1203 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1204 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1205 +
1206 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1207 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1208 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1209 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1210 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1211 +
1212 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1213 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1214 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1215 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1216 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1217 +
1218 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1219 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1220 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1221 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1222 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1223 +
1224 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1225 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1226 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1227 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1228 + rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
1229 +
1230 + /*
1231 + * Enable global DMA configuration
1232 + */
1233 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1234 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1235 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1236 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1237 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1238 +
1239 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1240 +
1241 + return 0;
1242 +}
1243 +
1244 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1245 +{
1246 + u32 reg;
1247 + unsigned int i;
1248 +
1249 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1250 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1251 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1252 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1253 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1254 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1255 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1256 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1257 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1258 +
1259 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1260 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1261 +
1262 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1263 +
1264 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1265 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1266 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1267 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1268 +
1269 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1270 +
1271 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1272 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1273 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1274 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1275 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1276 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1277 +
1278 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1279 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1280 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1281 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1282 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1283 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1284 +
1285 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1286 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1287 +
1288 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1289 +
1290 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1291 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1292 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1293 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1294 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1295 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1296 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1297 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1298 +
1299 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1300 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1301 +
1302 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1303 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1304 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1305 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1306 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1307 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1308 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1309 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1310 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1311 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1312 +
1313 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1314 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1315 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1316 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1317 +
1318 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1319 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1320 + if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1321 + rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1322 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1323 + else
1324 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1325 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1326 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1327 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1328 +
1329 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1330 +
1331 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1332 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1333 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1334 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1335 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1336 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1337 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1338 +
1339 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1340 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1341 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1342 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1343 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1344 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1345 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1346 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1347 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1348 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1349 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1350 +
1351 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1352 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1353 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1354 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1355 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1356 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1357 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1358 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1359 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1360 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1361 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1362 +
1363 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1364 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1365 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1366 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1367 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1368 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1369 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1370 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1371 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1372 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1373 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1374 +
1375 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1376 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1377 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1378 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1379 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1380 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1381 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1382 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1383 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1384 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1385 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1386 +
1387 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1388 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1389 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1390 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1391 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1392 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1393 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1394 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1395 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1396 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1397 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1398 +
1399 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1400 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1401 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1402 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1403 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1404 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1405 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1406 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1407 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1408 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1409 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1410 +
1411 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1412 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1413 +
1414 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1415 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1416 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1417 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1418 +
1419 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1420 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1421 +
1422 + /*
1423 + * ASIC will keep garbage value after boot, clear encryption keys.
1424 + */
1425 + for (i = 0; i < 254; i++) {
1426 + u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1427 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1428 + wcid, sizeof(wcid));
1429 + }
1430 +
1431 + for (i = 0; i < 4; i++)
1432 + rt2x00pci_register_write(rt2x00dev,
1433 + SHARED_KEY_MODE_ENTRY(i), 0);
1434 +
1435 + for (i = 0; i < 256; i++)
1436 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1437 +
1438 + /*
1439 + * Clear all beacons
1440 + * For the Beacon base registers we only need to clear
1441 + * the first byte since that byte contains the VALID and OWNER
1442 + * bits which (when set to 0) will invalidate the entire beacon.
1443 + */
1444 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1445 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1446 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1447 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1448 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1449 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1450 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1451 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1452 +
1453 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1454 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1455 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1456 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1457 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1458 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1459 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1460 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1461 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1462 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1463 +
1464 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1465 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1466 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1467 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1468 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1469 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1470 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1471 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1472 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1473 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1474 +
1475 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1476 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1477 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1478 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1479 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1480 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1481 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1482 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1483 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1484 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1485 +
1486 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1487 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1488 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1489 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1490 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1491 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1492 +
1493 + /*
1494 + * We must clear the error counters.
1495 + * These registers are cleared on read,
1496 + * so we may pass a useless variable to store the value.
1497 + */
1498 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1499 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1500 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1501 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1502 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1503 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1504 +
1505 + return 0;
1506 +}
1507 +
1508 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1509 +{
1510 + unsigned int i;
1511 + u32 reg;
1512 +
1513 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1514 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1515 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1516 + return 0;
1517 +
1518 + udelay(REGISTER_BUSY_DELAY);
1519 + }
1520 +
1521 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1522 + return -EACCES;
1523 +}
1524 +
1525 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1526 +{
1527 + unsigned int i;
1528 + u8 value;
1529 +
1530 + /*
1531 + * BBP was enabled after firmware was loaded,
1532 + * but we need to reactivate it now.
1533 + */
1534 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0x00000000);
1535 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0x00000000);
1536 + msleep(1);
1537 +
1538 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1539 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1540 + if ((value != 0xff) && (value != 0x00))
1541 + return 0;
1542 + udelay(REGISTER_BUSY_DELAY);
1543 + }
1544 +
1545 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1546 + return -EACCES;
1547 +}
1548 +
1549 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1550 +{
1551 + unsigned int i;
1552 + u16 eeprom;
1553 + u8 reg_id;
1554 + u8 value;
1555 +
1556 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1557 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1558 + return -EACCES;
1559 +
1560 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1561 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1562 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1563 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1564 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1565 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1566 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1567 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1568 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1569 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1570 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1571 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1572 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1573 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1574 +
1575 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1576 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1577 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1578 + }
1579 +
1580 + if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1581 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1582 +
1583 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1584 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1585 +
1586 + if (eeprom != 0xffff && eeprom != 0x0000) {
1587 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1588 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1589 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1590 + }
1591 + }
1592 +
1593 + return 0;
1594 +}
1595 +
1596 +/*
1597 + * Device state switch handlers.
1598 + */
1599 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1600 + enum dev_state state)
1601 +{
1602 + u32 reg;
1603 +
1604 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1605 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1606 + (state == STATE_RADIO_RX_ON) ||
1607 + (state == STATE_RADIO_RX_ON_LINK));
1608 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1609 +}
1610 +
1611 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1612 + enum dev_state state)
1613 +{
1614 + int mask = (state == STATE_RADIO_IRQ_ON);
1615 + u32 reg;
1616 +
1617 + /*
1618 + * When interrupts are being enabled, the interrupt registers
1619 + * should clear the register to assure a clean state.
1620 + */
1621 + if (state == STATE_RADIO_IRQ_ON) {
1622 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1623 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1624 + }
1625 +
1626 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1627 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1628 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1629 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1630 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1631 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1632 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1633 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1634 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1635 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1636 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1637 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1638 + rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1639 + rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1640 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1641 + rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1642 + rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1643 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1644 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1645 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1646 +}
1647 +
1648 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1649 +{
1650 + unsigned int i;
1651 + u32 reg;
1652 +
1653 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1654 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1655 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1656 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1657 + return 0;
1658 +
1659 + msleep(1);
1660 + }
1661 +
1662 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1663 + return -EACCES;
1664 +}
1665 +
1666 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1667 +{
1668 + u32 reg;
1669 + u16 word;
1670 +
1671 + /*
1672 + * Initialize all registers.
1673 + */
1674 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1675 + rt2800pci_init_queues(rt2x00dev) ||
1676 + rt2800pci_init_registers(rt2x00dev) ||
1677 + rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1678 + rt2800pci_init_bbp(rt2x00dev)))
1679 + return -EIO;
1680 +
1681 + /*
1682 + * Send signal to firmware during boot time.
1683 + */
1684 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1685 +
1686 + /*
1687 + * Enable RX.
1688 + */
1689 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1690 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1691 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
1692 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1693 +
1694 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1695 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1696 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1697 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
1698 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1699 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1700 +
1701 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1702 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1703 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1704 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1705 +
1706 + /*
1707 + * Initialize LED control
1708 + */
1709 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1710 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1711 + word & 0xff, (word >> 8) & 0xff);
1712 +
1713 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1714 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1715 + word & 0xff, (word >> 8) & 0xff);
1716 +
1717 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1718 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1719 + word & 0xff, (word >> 8) & 0xff);
1720 +
1721 + return 0;
1722 +}
1723 +
1724 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1725 +{
1726 + u32 reg;
1727 +
1728 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1729 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1730 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1731 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1732 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1733 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1734 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1735 +
1736 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1737 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1738 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1739 +
1740 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1741 +
1742 + /* Wait for DMA, ignore error */
1743 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1744 +}
1745 +
1746 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1747 + enum dev_state state)
1748 +{
1749 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1750 +
1751 + if (state == STATE_AWAKE)
1752 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1753 + else
1754 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1755 +
1756 + return 0;
1757 +}
1758 +
1759 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1760 + enum dev_state state)
1761 +{
1762 + int retval = 0;
1763 +
1764 + switch (state) {
1765 + case STATE_RADIO_ON:
1766 + /*
1767 + * Before the radio can be enabled, the device first has
1768 + * to be woken up. After that it needs a bit of time
1769 + * to be fully awake and the radio can be enabled.
1770 + */
1771 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1772 + msleep(1);
1773 + retval = rt2800pci_enable_radio(rt2x00dev);
1774 + break;
1775 + case STATE_RADIO_OFF:
1776 + /*
1777 + * After the radio has been disablee, the device should
1778 + * be put to sleep for powersaving.
1779 + */
1780 + rt2800pci_disable_radio(rt2x00dev);
1781 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1782 + break;
1783 + case STATE_RADIO_RX_ON:
1784 + case STATE_RADIO_RX_ON_LINK:
1785 + case STATE_RADIO_RX_OFF:
1786 + case STATE_RADIO_RX_OFF_LINK:
1787 + rt2800pci_toggle_rx(rt2x00dev, state);
1788 + break;
1789 + case STATE_RADIO_IRQ_ON:
1790 + case STATE_RADIO_IRQ_OFF:
1791 + rt2800pci_toggle_irq(rt2x00dev, state);
1792 + break;
1793 + case STATE_DEEP_SLEEP:
1794 + case STATE_SLEEP:
1795 + case STATE_STANDBY:
1796 + case STATE_AWAKE:
1797 + retval = rt2800pci_set_state(rt2x00dev, state);
1798 + break;
1799 + default:
1800 + retval = -ENOTSUPP;
1801 + break;
1802 + }
1803 +
1804 + if (unlikely(retval))
1805 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1806 + state, retval);
1807 +
1808 + return retval;
1809 +}
1810 +
1811 +/*
1812 + * TX descriptor initialization
1813 + */
1814 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1815 + struct sk_buff *skb,
1816 + struct txentry_desc *txdesc)
1817 +{
1818 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1819 + __le32 *txd = skbdesc->desc;
1820 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1821 + u32 word;
1822 +
1823 + /*
1824 + * Initialize TX Info descriptor
1825 + */
1826 + rt2x00_desc_read(txwi, 0, &word);
1827 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1828 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1829 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1830 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1831 + rt2x00_set_field32(&word, TXWI_W0_TS,
1832 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1833 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1834 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1835 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1836 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1837 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1838 + rt2x00_set_field32(&word, TXWI_W0_BW,
1839 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1840 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1841 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1842 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1843 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1844 + rt2x00_desc_write(txwi, 0, word);
1845 +
1846 + rt2x00_desc_read(txwi, 1, &word);
1847 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1848 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1849 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1850 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1851 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1852 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1853 + skbdesc->entry->entry_idx);
1854 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1855 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1856 + skbdesc->entry->queue->qid);
1857 + rt2x00_desc_write(txwi, 1, word);
1858 +
1859 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1860 + _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
1861 + _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
1862 + }
1863 +
1864 + /*
1865 + * Initialize TX descriptor
1866 + */
1867 + rt2x00_desc_read(txd, 0, &word);
1868 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1869 + rt2x00_desc_write(txd, 0, word);
1870 +
1871 + rt2x00_desc_read(txd, 1, &word);
1872 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1873 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1874 + rt2x00_set_field32(&word, TXD_W1_BURST,
1875 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1876 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1877 + rt2x00dev->hw->extra_tx_headroom);
1878 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1879 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1880 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1881 + rt2x00_desc_write(txd, 1, word);
1882 +
1883 + rt2x00_desc_read(txd, 2, &word);
1884 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1885 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1886 + rt2x00_desc_write(txd, 2, word);
1887 +
1888 + rt2x00_desc_read(txd, 3, &word);
1889 + rt2x00_set_field32(&word, TXD_W3_WIV, 1);
1890 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1891 + rt2x00_desc_write(txd, 3, word);
1892 +}
1893 +
1894 +/*
1895 + * TX data initialization
1896 + */
1897 +static void rt2800pci_write_beacon(struct queue_entry *entry)
1898 +{
1899 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1900 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1901 + unsigned int beacon_base;
1902 + u32 reg;
1903 +
1904 + /*
1905 + * Disable beaconing while we are reloading the beacon data,
1906 + * otherwise we might be sending out invalid data.
1907 + */
1908 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1909 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1910 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1911 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1912 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1913 +
1914 + /*
1915 + * Write entire beacon with descriptor to register.
1916 + */
1917 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1918 + rt2x00pci_register_multiwrite(rt2x00dev,
1919 + beacon_base,
1920 + skbdesc->desc, skbdesc->desc_len);
1921 + rt2x00pci_register_multiwrite(rt2x00dev,
1922 + beacon_base + skbdesc->desc_len,
1923 + entry->skb->data, entry->skb->len);
1924 +
1925 + /*
1926 + * Clean up beacon skb.
1927 + */
1928 + dev_kfree_skb_any(entry->skb);
1929 + entry->skb = NULL;
1930 +}
1931 +
1932 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1933 + const enum data_queue_qid queue_idx)
1934 +{
1935 + struct data_queue *queue;
1936 + unsigned int idx, qidx = 0;
1937 + u32 reg;
1938 +
1939 + if (queue_idx == QID_BEACON) {
1940 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1941 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1942 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1943 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1944 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1945 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1946 + }
1947 + return;
1948 + }
1949 +
1950 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
1951 + return;
1952 +
1953 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1954 + idx = queue->index[Q_INDEX];
1955 +
1956 + if (queue_idx == QID_MGMT)
1957 + qidx = 5;
1958 + else
1959 + qidx = queue_idx;
1960 +
1961 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
1962 +}
1963 +
1964 +static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1965 + const enum data_queue_qid qid)
1966 +{
1967 + u32 reg;
1968 +
1969 + if (qid == QID_BEACON) {
1970 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0);
1971 + return;
1972 + }
1973 +
1974 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1975 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
1976 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
1977 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
1978 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
1979 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1980 +}
1981 +
1982 +/*
1983 + * RX control handlers
1984 + */
1985 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
1986 + struct rxdone_entry_desc *rxdesc)
1987 +{
1988 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1989 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1990 + __le32 *rxd = entry_priv->desc;
1991 + __le32 *rxwi = (__le32 *)entry->skb->data;
1992 + u32 rxd3;
1993 + u32 rxwi0;
1994 + u32 rxwi1;
1995 + u32 rxwi2;
1996 + u32 rxwi3;
1997 +
1998 + rt2x00_desc_read(rxd, 3, &rxd3);
1999 + rt2x00_desc_read(rxwi, 0, &rxwi0);
2000 + rt2x00_desc_read(rxwi, 1, &rxwi1);
2001 + rt2x00_desc_read(rxwi, 2, &rxwi2);
2002 + rt2x00_desc_read(rxwi, 3, &rxwi3);
2003 +
2004 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2005 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2006 +
2007 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2008 + /*
2009 + * Unfortunately we don't know the cipher type used during
2010 + * decryption. This prevents us from correct providing
2011 + * correct statistics through debugfs.
2012 + */
2013 + rxdesc->cipher = CIPHER_NONE;
2014 + rxdesc->cipher_status =
2015 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2016 + }
2017 +
2018 + if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2019 + /*
2020 + * Hardware has stripped IV/EIV data from 802.11 frame during
2021 + * decryption. Unfortunately the descriptor doesn't contain
2022 + * any fields with the EIV/IV data either, so they can't
2023 + * be restored by rt2x00lib.
2024 + */
2025 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2026 +
2027 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2028 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2029 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2030 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2031 + }
2032 +
2033 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2034 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2035 +
2036 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2037 + rxdesc->flags |= RX_FLAG_SHORT_GI;
2038 +
2039 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2040 + rxdesc->flags |= RX_FLAG_40MHZ;
2041 +
2042 + /*
2043 + * Detect RX rate, always use MCS as signal type.
2044 + */
2045 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2046 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2047 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2048 +
2049 + /*
2050 + * Mask of 0x8 bit to remove the short preamble flag.
2051 + */
2052 + if (rxdesc->dev_flags == RATE_MODE_CCK)
2053 + rxdesc->signal &= ~0x8;
2054 +
2055 + rxdesc->rssi =
2056 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2057 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2058 +
2059 + rxdesc->noise =
2060 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2061 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2062 +
2063 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2064 +
2065 + /*
2066 + * Remove TXWI descriptor from start of buffer.
2067 + */
2068 + skb_pull(entry->skb, TXWI_DESC_SIZE);
2069 + skb_trim(entry->skb, rxdesc->size);
2070 +}
2071 +
2072 +/*
2073 + * Interrupt functions.
2074 + */
2075 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2076 +{
2077 + struct data_queue *queue;
2078 + struct queue_entry *entry;
2079 + struct queue_entry *entry_done;
2080 + struct queue_entry_priv_pci *entry_priv;
2081 + struct txdone_entry_desc txdesc;
2082 + u32 word;
2083 + u32 reg;
2084 + u32 old_reg;
2085 + int type;
2086 + int index;
2087 +
2088 + /*
2089 + * During each loop we will compare the freshly read
2090 + * TX_STA_FIFO register value with the value read from
2091 + * the previous loop. If the 2 values are equal then
2092 + * we should stop processing because the chance it
2093 + * quite big that the device has been unplugged and
2094 + * we risk going into an endless loop.
2095 + */
2096 + old_reg = 0;
2097 +
2098 + while (1) {
2099 + rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2100 + if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2101 + break;
2102 +
2103 + if (old_reg == reg)
2104 + break;
2105 + old_reg = reg;
2106 +
2107 + /*
2108 + * Skip this entry when it contains an invalid
2109 + * queue identication number.
2110 + */
2111 + type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2112 + queue = rt2x00queue_get_queue(rt2x00dev, type);
2113 + if (unlikely(!queue))
2114 + continue;
2115 +
2116 + /*
2117 + * Skip this entry when it contains an invalid
2118 + * index number.
2119 + */
2120 + index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2121 + if (unlikely(index >= queue->limit))
2122 + continue;
2123 +
2124 + entry = &queue->entries[index];
2125 + entry_priv = entry->priv_data;
2126 + rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2127 +
2128 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2129 + while (entry != entry_done) {
2130 + /*
2131 + * Catch up.
2132 + * Just report any entries we missed as failed.
2133 + */
2134 + WARNING(rt2x00dev,
2135 + "TX status report missed for entry %d\n",
2136 + entry_done->entry_idx);
2137 +
2138 + txdesc.flags = 0;
2139 + __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2140 + txdesc.retry = 0;
2141 +
2142 + rt2x00lib_txdone(entry_done, &txdesc);
2143 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2144 + }
2145 +
2146 + /*
2147 + * Obtain the status about this packet.
2148 + */
2149 + txdesc.flags = 0;
2150 + if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2151 + __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2152 + else
2153 + __set_bit(TXDONE_FAILURE, &txdesc.flags);
2154 + txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2155 +
2156 + rt2x00lib_txdone(entry, &txdesc);
2157 + }
2158 +}
2159 +
2160 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2161 +{
2162 + struct rt2x00_dev *rt2x00dev = dev_instance;
2163 + u32 reg;
2164 +
2165 + /* Read status and ACK all interrupts */
2166 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2167 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2168 +
2169 + if (!reg)
2170 + return IRQ_NONE;
2171 +
2172 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2173 + return IRQ_HANDLED;
2174 +
2175 + /*
2176 + * 1 - Rx ring done interrupt.
2177 + */
2178 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2179 + rt2x00pci_rxdone(rt2x00dev);
2180 +
2181 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2182 + rt2800pci_txdone(rt2x00dev);
2183 +
2184 + return IRQ_HANDLED;
2185 +}
2186 +
2187 +/*
2188 + * Device probe functions.
2189 + */
2190 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2191 +{
2192 + struct eeprom_93cx6 eeprom;
2193 + u32 reg;
2194 + u16 word;
2195 + u8 *mac;
2196 + u8 default_lna_gain;
2197 +
2198 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2199 +
2200 + eeprom.data = rt2x00dev;
2201 + eeprom.register_read = rt2800pci_eepromregister_read;
2202 + eeprom.register_write = rt2800pci_eepromregister_write;
2203 + eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
2204 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2205 + eeprom.reg_data_in = 0;
2206 + eeprom.reg_data_out = 0;
2207 + eeprom.reg_data_clock = 0;
2208 + eeprom.reg_chip_select = 0;
2209 +
2210 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2211 + EEPROM_SIZE / sizeof(u16));
2212 +
2213 + /*
2214 + * Start validation of the data that has been read.
2215 + */
2216 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2217 + if (!is_valid_ether_addr(mac)) {
2218 + DECLARE_MAC_BUF(macbuf);
2219 +
2220 + random_ether_addr(mac);
2221 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2222 + }
2223 +
2224 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2225 + if (word == 0xffff) {
2226 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2227 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2228 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2229 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2230 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2231 + }
2232 +
2233 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2234 + if (word == 0xffff) {
2235 + rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2236 + rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2237 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2238 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2239 + rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2240 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2241 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2242 + rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2243 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2244 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2245 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2246 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2247 + }
2248 +
2249 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2250 + if ((word & 0x00ff) == 0x00ff) {
2251 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2252 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2253 + LED_MODE_TXRX_ACTIVITY);
2254 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2255 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2256 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2257 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2258 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2259 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2260 + }
2261 +
2262 + /*
2263 + * During the LNA validation we are going to use
2264 + * lna0 as correct value. Note that EEPROM_LNA
2265 + * is never validated.
2266 + */
2267 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2268 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2269 +
2270 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2271 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2272 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2273 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2274 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2275 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2276 +
2277 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2278 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2279 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2280 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2281 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2282 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2283 + default_lna_gain);
2284 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2285 +
2286 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2287 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2288 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2289 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2290 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2291 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2292 +
2293 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2294 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2295 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2296 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2297 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2298 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2299 + default_lna_gain);
2300 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2301 +
2302 + return 0;
2303 +}
2304 +
2305 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2306 +{
2307 + u32 reg;
2308 + u16 value;
2309 + u16 eeprom;
2310 + u16 device;
2311 +
2312 + /*
2313 + * Read EEPROM word for configuration.
2314 + */
2315 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2316 +
2317 + /*
2318 + * Identify RF chipset.
2319 + * To determine the RT chip we have to read the
2320 + * PCI header of the device.
2321 + */
2322 + pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2323 + PCI_CONFIG_HEADER_DEVICE, &device);
2324 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2325 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2326 + rt2x00_set_chip(rt2x00dev, device, value, reg);
2327 +
2328 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2329 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2330 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2331 + !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2332 + !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2333 + !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2334 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2335 + return -ENODEV;
2336 + }
2337 +
2338 + /*
2339 + * Read frequency offset and RF programming sequence.
2340 + */
2341 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2342 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2343 +
2344 + /*
2345 + * Read external LNA informations.
2346 + */
2347 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2348 +
2349 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2350 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2351 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2352 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2353 +
2354 + /*
2355 + * Detect if this device has an hardware controlled radio.
2356 + */
2357 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2358 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2359 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2360 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2361 +
2362 + /*
2363 + * Store led settings, for correct led behaviour.
2364 + */
2365 +#ifdef CONFIG_RT2X00_LIB_LEDS
2366 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2367 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2368 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2369 +
2370 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2371 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2372 +
2373 + return 0;
2374 +}
2375 +
2376 +/*
2377 + * RF value list for rt2860
2378 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2379 + */
2380 +static const struct rf_channel rf_vals[] = {
2381 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2382 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2383 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2384 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2385 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2386 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2387 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2388 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2389 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2390 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2391 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2392 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2393 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2394 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2395 +
2396 + /* 802.11 UNI / HyperLan 2 */
2397 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2398 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2399 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2400 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2401 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2402 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2403 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2404 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2405 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2406 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2407 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2408 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2409 +
2410 + /* 802.11 HyperLan 2 */
2411 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2412 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2413 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2414 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2415 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2416 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2417 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2418 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2419 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2420 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2421 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2422 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2423 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2424 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2425 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2426 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2427 +
2428 + /* 802.11 UNII */
2429 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2430 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2431 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2432 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2433 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2434 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2435 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2436 +
2437 + /* 802.11 Japan */
2438 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2439 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2440 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2441 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2442 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2443 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2444 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2445 +};
2446 +
2447 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2448 +{
2449 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2450 + struct channel_info *info;
2451 + char *tx_power1;
2452 + char *tx_power2;
2453 + unsigned int i;
2454 +
2455 + /*
2456 + * Initialize all hw fields.
2457 + */
2458 + rt2x00dev->hw->flags =
2459 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2460 + IEEE80211_HW_SIGNAL_DBM |
2461 + IEEE80211_HW_SUPPORTS_PS |
2462 + IEEE80211_HW_PS_NULLFUNC_STACK;
2463 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2464 +
2465 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2466 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2467 + rt2x00_eeprom_addr(rt2x00dev,
2468 + EEPROM_MAC_ADDR_0));
2469 +
2470 + /*
2471 + * Initialize hw_mode information.
2472 + */
2473 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2474 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2475 +
2476 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2477 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2478 + spec->num_channels = 14;
2479 + spec->channels = rf_vals;
2480 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2481 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2482 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2483 + spec->num_channels = ARRAY_SIZE(rf_vals);
2484 + spec->channels = rf_vals;
2485 + }
2486 +
2487 + /*
2488 + * Initialize HT information.
2489 + */
2490 + spec->ht.ht_supported = true;
2491 + spec->ht.cap =
2492 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2493 + IEEE80211_HT_CAP_GRN_FLD |
2494 + IEEE80211_HT_CAP_SGI_20 |
2495 + IEEE80211_HT_CAP_SGI_40 |
2496 + IEEE80211_HT_CAP_TX_STBC |
2497 + IEEE80211_HT_CAP_RX_STBC |
2498 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2499 + spec->ht.ampdu_factor = 3;
2500 + spec->ht.ampdu_density = 4;
2501 + spec->ht.mcs.rx_mask[0] = 0xff;
2502 + spec->ht.mcs.rx_mask[1] = 0xff;
2503 + spec->ht.mcs.tx_params =
2504 + IEEE80211_HT_MCS_TX_DEFINED;
2505 +
2506 + /*
2507 + * Create channel information array
2508 + */
2509 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2510 + if (!info)
2511 + return -ENOMEM;
2512 +
2513 + spec->channels_info = info;
2514 +
2515 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2516 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2517 +
2518 + for (i = 0; i < 14; i++) {
2519 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2520 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2521 + }
2522 +
2523 + if (spec->num_channels > 14) {
2524 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2525 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2526 +
2527 + for (i = 14; i < spec->num_channels; i++) {
2528 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2529 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2530 + }
2531 + }
2532 +
2533 + return 0;
2534 +}
2535 +
2536 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2537 +{
2538 + int retval;
2539 +
2540 + /*
2541 + * Allocate eeprom data.
2542 + */
2543 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2544 + if (retval)
2545 + return retval;
2546 +
2547 + retval = rt2800pci_init_eeprom(rt2x00dev);
2548 + if (retval)
2549 + return retval;
2550 +
2551 + /*
2552 + * Initialize hw specifications.
2553 + */
2554 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2555 + if (retval)
2556 + return retval;
2557 +
2558 + /*
2559 + * This device requires firmware.
2560 + */
2561 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2562 + if (!modparam_nohwcrypt)
2563 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2564 +
2565 + /*
2566 + * Set the rssi offset.
2567 + */
2568 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2569 +
2570 + return 0;
2571 +}
2572 +
2573 +/*
2574 + * IEEE80211 stack callback functions.
2575 + */
2576 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2577 +{
2578 + struct rt2x00_dev *rt2x00dev = hw->priv;
2579 + u32 reg;
2580 + bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2581 +
2582 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2583 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2584 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2585 +
2586 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2587 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2588 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2589 +
2590 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2591 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2592 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2593 +
2594 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2595 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2596 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2597 +
2598 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2599 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2600 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2601 +
2602 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2603 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2604 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2605 +
2606 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2607 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2608 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2609 +
2610 + return 0;
2611 +}
2612 +
2613 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2614 + const struct ieee80211_tx_queue_params *params)
2615 +{
2616 + struct rt2x00_dev *rt2x00dev = hw->priv;
2617 + struct data_queue *queue;
2618 + struct rt2x00_field32 field;
2619 + int retval;
2620 + u32 reg;
2621 + u32 offset;
2622 +
2623 + /*
2624 + * First pass the configuration through rt2x00lib, that will
2625 + * update the queue settings and validate the input. After that
2626 + * we are free to update the registers based on the value
2627 + * in the queue parameter.
2628 + */
2629 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2630 + if (retval)
2631 + return retval;
2632 +
2633 + /*
2634 + * We only need to perform additional register initialization
2635 + * for WMM queues/
2636 + */
2637 + if (queue_idx >= 4)
2638 + return 0;
2639 +
2640 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2641 +
2642 + /* Update WMM TXOP register */
2643 + offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2644 + field.bit_offset = (queue_idx & 1) * 16;
2645 + field.bit_mask = 0xffff << field.bit_offset;
2646 +
2647 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2648 + rt2x00_set_field32(&reg, field, queue->txop);
2649 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2650 +
2651 + /* Update WMM registers */
2652 + field.bit_offset = queue_idx * 4;
2653 + field.bit_mask = 0xf << field.bit_offset;
2654 +
2655 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2656 + rt2x00_set_field32(&reg, field, queue->aifs);
2657 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2658 +
2659 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2660 + rt2x00_set_field32(&reg, field, queue->cw_min);
2661 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2662 +
2663 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2664 + rt2x00_set_field32(&reg, field, queue->cw_max);
2665 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2666 +
2667 + /* Update EDCA registers */
2668 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2669 +
2670 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2671 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2672 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2673 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2674 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2675 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2676 +
2677 + return 0;
2678 +}
2679 +
2680 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2681 +{
2682 + struct rt2x00_dev *rt2x00dev = hw->priv;
2683 + u64 tsf;
2684 + u32 reg;
2685 +
2686 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2687 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2688 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2689 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2690 +
2691 + return tsf;
2692 +}
2693 +
2694 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2695 + .tx = rt2x00mac_tx,
2696 + .start = rt2x00mac_start,
2697 + .stop = rt2x00mac_stop,
2698 + .add_interface = rt2x00mac_add_interface,
2699 + .remove_interface = rt2x00mac_remove_interface,
2700 + .config = rt2x00mac_config,
2701 + .config_interface = rt2x00mac_config_interface,
2702 + .configure_filter = rt2x00mac_configure_filter,
2703 + .set_key = rt2x00mac_set_key,
2704 + .get_stats = rt2x00mac_get_stats,
2705 + .set_rts_threshold = rt2800pci_set_rts_threshold,
2706 + .bss_info_changed = rt2x00mac_bss_info_changed,
2707 + .conf_tx = rt2800pci_conf_tx,
2708 + .get_tx_stats = rt2x00mac_get_tx_stats,
2709 + .get_tsf = rt2800pci_get_tsf,
2710 +};
2711 +
2712 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2713 + .irq_handler = rt2800pci_interrupt,
2714 + .probe_hw = rt2800pci_probe_hw,
2715 + .get_firmware_name = rt2800pci_get_firmware_name,
2716 + .check_firmware = rt2800pci_check_firmware,
2717 + .load_firmware = rt2800pci_load_firmware,
2718 + .initialize = rt2x00pci_initialize,
2719 + .uninitialize = rt2x00pci_uninitialize,
2720 + .get_entry_state = rt2800pci_get_entry_state,
2721 + .clear_entry = rt2800pci_clear_entry,
2722 + .set_device_state = rt2800pci_set_device_state,
2723 + .rfkill_poll = rt2800pci_rfkill_poll,
2724 + .link_stats = rt2800pci_link_stats,
2725 + .reset_tuner = rt2800pci_reset_tuner,
2726 + .link_tuner = rt2800pci_link_tuner,
2727 + .write_tx_desc = rt2800pci_write_tx_desc,
2728 + .write_tx_data = rt2x00pci_write_tx_data,
2729 + .write_beacon = rt2800pci_write_beacon,
2730 + .kick_tx_queue = rt2800pci_kick_tx_queue,
2731 + .kill_tx_queue = rt2800pci_kill_tx_queue,
2732 + .fill_rxdone = rt2800pci_fill_rxdone,
2733 + .config_shared_key = rt2800pci_config_shared_key,
2734 + .config_pairwise_key = rt2800pci_config_pairwise_key,
2735 + .config_filter = rt2800pci_config_filter,
2736 + .config_intf = rt2800pci_config_intf,
2737 + .config_erp = rt2800pci_config_erp,
2738 + .config_ant = rt2800pci_config_ant,
2739 + .config = rt2800pci_config,
2740 +};
2741 +
2742 +static const struct data_queue_desc rt2800pci_queue_rx = {
2743 + .entry_num = RX_ENTRIES,
2744 + .data_size = DATA_FRAME_SIZE,
2745 + .desc_size = RXD_DESC_SIZE,
2746 + .priv_size = sizeof(struct queue_entry_priv_pci),
2747 +};
2748 +
2749 +static const struct data_queue_desc rt2800pci_queue_tx = {
2750 + .entry_num = TX_ENTRIES,
2751 + .data_size = DATA_FRAME_SIZE,
2752 + .desc_size = TXD_DESC_SIZE,
2753 + .priv_size = sizeof(struct queue_entry_priv_pci),
2754 +};
2755 +
2756 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2757 + .entry_num = 8 * BEACON_ENTRIES,
2758 + .data_size = 0, /* No DMA required for beacons */
2759 + .desc_size = TXWI_DESC_SIZE,
2760 + .priv_size = sizeof(struct queue_entry_priv_pci),
2761 +};
2762 +
2763 +static const struct rt2x00_ops rt2800pci_ops = {
2764 + .name = KBUILD_MODNAME,
2765 + .max_sta_intf = 1,
2766 + .max_ap_intf = 8,
2767 + .eeprom_size = EEPROM_SIZE,
2768 + .rf_size = RF_SIZE,
2769 + .tx_queues = NUM_TX_QUEUES,
2770 + .rx = &rt2800pci_queue_rx,
2771 + .tx = &rt2800pci_queue_tx,
2772 + .bcn = &rt2800pci_queue_bcn,
2773 + .lib = &rt2800pci_rt2x00_ops,
2774 + .hw = &rt2800pci_mac80211_ops,
2775 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2776 + .debugfs = &rt2800pci_rt2x00debug,
2777 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2778 +};
2779 +
2780 +/*
2781 + * RT2800pci module information.
2782 + */
2783 +static struct pci_device_id rt2800pci_device_table[] = {
2784 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2785 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2786 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2787 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2788 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2789 + { 0, }
2790 +};
2791 +
2792 +MODULE_AUTHOR(DRV_PROJECT);
2793 +MODULE_VERSION(DRV_VERSION);
2794 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2795 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2796 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2797 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2798 +MODULE_LICENSE("GPL");
2799 +
2800 +static struct pci_driver rt2800pci_driver = {
2801 + .name = KBUILD_MODNAME,
2802 + .id_table = rt2800pci_device_table,
2803 + .probe = rt2x00pci_probe,
2804 + .remove = __devexit_p(rt2x00pci_remove),
2805 + .suspend = rt2x00pci_suspend,
2806 + .resume = rt2x00pci_resume,
2807 +};
2808 +
2809 +static int __init rt2800pci_init(void)
2810 +{
2811 + return pci_register_driver(&rt2800pci_driver);
2812 +}
2813 +
2814 +static void __exit rt2800pci_exit(void)
2815 +{
2816 + pci_unregister_driver(&rt2800pci_driver);
2817 +}
2818 +
2819 +module_init(rt2800pci_init);
2820 +module_exit(rt2800pci_exit);
2821 --- /dev/null
2822 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2823 @@ -0,0 +1,1877 @@
2824 +/*
2825 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
2826 + <http://rt2x00.serialmonkey.com>
2827 +
2828 + This program is free software; you can redistribute it and/or modify
2829 + it under the terms of the GNU General Public License as published by
2830 + the Free Software Foundation; either version 2 of the License, or
2831 + (at your option) any later version.
2832 +
2833 + This program is distributed in the hope that it will be useful,
2834 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2835 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2836 + GNU General Public License for more details.
2837 +
2838 + You should have received a copy of the GNU General Public License
2839 + along with this program; if not, write to the
2840 + Free Software Foundation, Inc.,
2841 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2842 + */
2843 +
2844 +/*
2845 + Module: rt2800pci
2846 + Abstract: Data structures and registers for the rt2800pci module.
2847 + Supported chipsets: RT2800E & RT2800ED.
2848 + */
2849 +
2850 +#ifndef RT2800PCI_H
2851 +#define RT2800PCI_H
2852 +
2853 +/*
2854 + * RF chip defines.
2855 + *
2856 + * RF2820 2.4G 2T3R
2857 + * RF2850 2.4G/5G 2T3R
2858 + * RF2720 2.4G 1T2R
2859 + * RF2750 2.4G/5G 1T2R
2860 + * RF3020 2.4G 1T1R
2861 + * RF2020 2.4G B/G
2862 + */
2863 +#define RF2820 0x0001
2864 +#define RF2850 0x0002
2865 +#define RF2720 0x0003
2866 +#define RF2750 0x0004
2867 +#define RF3020 0x0005
2868 +#define RF2020 0x0006
2869 +
2870 +/*
2871 + * RT2860 version
2872 + */
2873 +#define RT2860C_VERSION 0x28600100
2874 +#define RT2860D_VERSION 0x28600101
2875 +#define RT2880E_VERSION 0x28720200
2876 +#define RT2883_VERSION 0x28830300
2877 +#define RT3070_VERSION 0x30700200
2878 +
2879 +/*
2880 + * Signal information.
2881 + * Defaul offset is required for RSSI <-> dBm conversion.
2882 + */
2883 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
2884 +
2885 +/*
2886 + * Register layout information.
2887 + */
2888 +#define CSR_REG_BASE 0x1000
2889 +#define CSR_REG_SIZE 0x0800
2890 +#define EEPROM_BASE 0x0000
2891 +#define EEPROM_SIZE 0x0110
2892 +#define BBP_BASE 0x0000
2893 +#define BBP_SIZE 0x0080
2894 +#define RF_BASE 0x0000
2895 +#define RF_SIZE 0x0014
2896 +
2897 +/*
2898 + * Number of TX queues.
2899 + */
2900 +#define NUM_TX_QUEUES 4
2901 +
2902 +/*
2903 + * PCI registers.
2904 + */
2905 +
2906 +/*
2907 + * PCI Configuration Header
2908 + */
2909 +#define PCI_CONFIG_HEADER_VENDOR 0x0000
2910 +#define PCI_CONFIG_HEADER_DEVICE 0x0002
2911 +
2912 +/*
2913 + * E2PROM_CSR: EEPROM control register.
2914 + * RELOAD: Write 1 to reload eeprom content.
2915 + * TYPE: 0: 93c46, 1:93c66.
2916 + * LOAD_STATUS: 1:loading, 0:done.
2917 + */
2918 +#define E2PROM_CSR 0x0004
2919 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
2920 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
2921 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
2922 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
2923 +#define E2PROM_CSR_TYPE FIELD32(0x00000030)
2924 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
2925 +#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
2926 +
2927 +/*
2928 + * HOST-MCU shared memory
2929 + */
2930 +#define HOST_CMD_CSR 0x0404
2931 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
2932 +
2933 +/*
2934 + * INT_SOURCE_CSR: Interrupt source register.
2935 + * Write one to clear corresponding bit.
2936 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2937 + */
2938 +#define INT_SOURCE_CSR 0x0200
2939 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
2940 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
2941 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
2942 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2943 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2944 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2945 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2946 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2947 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2948 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
2949 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
2950 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
2951 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
2952 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2953 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2954 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
2955 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
2956 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
2957 +
2958 +/*
2959 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2960 + */
2961 +#define INT_MASK_CSR 0x0204
2962 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
2963 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
2964 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
2965 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2966 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2967 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2968 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2969 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2970 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2971 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
2972 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
2973 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
2974 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
2975 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2976 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2977 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
2978 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
2979 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
2980 +
2981 +/*
2982 + * WPDMA_GLO_CFG
2983 + */
2984 +#define WPDMA_GLO_CFG 0x0208
2985 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
2986 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
2987 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
2988 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
2989 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
2990 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
2991 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
2992 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
2993 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
2994 +
2995 +/*
2996 + * WPDMA_RST_IDX
2997 + */
2998 +#define WPDMA_RST_IDX 0x020c
2999 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
3000 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
3001 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
3002 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
3003 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
3004 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
3005 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
3006 +
3007 +/*
3008 + * DELAY_INT_CFG
3009 + */
3010 +#define DELAY_INT_CFG 0x0210
3011 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
3012 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
3013 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
3014 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
3015 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
3016 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
3017 +
3018 +/*
3019 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3020 + * AIFSN0: AC_BE
3021 + * AIFSN1: AC_BK
3022 + * AIFSN1: AC_VI
3023 + * AIFSN1: AC_VO
3024 + */
3025 +#define WMM_AIFSN_CFG 0x0214
3026 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3027 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3028 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3029 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3030 +
3031 +/*
3032 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3033 + * CWMIN0: AC_BE
3034 + * CWMIN1: AC_BK
3035 + * CWMIN1: AC_VI
3036 + * CWMIN1: AC_VO
3037 + */
3038 +#define WMM_CWMIN_CFG 0x0218
3039 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3040 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3041 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3042 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3043 +
3044 +/*
3045 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3046 + * CWMAX0: AC_BE
3047 + * CWMAX1: AC_BK
3048 + * CWMAX1: AC_VI
3049 + * CWMAX1: AC_VO
3050 + */
3051 +#define WMM_CWMAX_CFG 0x021c
3052 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3053 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3054 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3055 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3056 +
3057 +/*
3058 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3059 + * AC0TXOP: AC_BK in unit of 32us
3060 + * AC1TXOP: AC_BE in unit of 32us
3061 + */
3062 +#define WMM_TXOP0_CFG 0x0220
3063 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3064 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3065 +
3066 +/*
3067 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3068 + * AC2TXOP: AC_VI in unit of 32us
3069 + * AC3TXOP: AC_VO in unit of 32us
3070 + */
3071 +#define WMM_TXOP1_CFG 0x0224
3072 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3073 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3074 +
3075 +/*
3076 + * RINGREG_DIFF
3077 + */
3078 +#define RINGREG_DIFF 0x0010
3079 +
3080 +/*
3081 + * GPIO_CTRL_CFG:
3082 + */
3083 +#define GPIO_CTRL_CFG 0x0228
3084 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3085 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3086 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3087 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3088 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3089 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3090 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3091 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3092 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3093 +
3094 +/*
3095 + * MCU_CMD_CFG
3096 + */
3097 +#define MCU_CMD_CFG 0x022c
3098 +
3099 +/*
3100 + * AC_BK register offsets
3101 + */
3102 +#define TX_BASE_PTR0 0x0230
3103 +#define TX_MAX_CNT0 0x0234
3104 +#define TX_CTX_IDX0 0x0238
3105 +#define TX_DTX_IDX0 0x023c
3106 +
3107 +/*
3108 + * AC_BE register offsets
3109 + */
3110 +#define TX_BASE_PTR1 0x0240
3111 +#define TX_MAX_CNT1 0x0244
3112 +#define TX_CTX_IDX1 0x0248
3113 +#define TX_DTX_IDX1 0x024c
3114 +
3115 +/*
3116 + * AC_VI register offsets
3117 + */
3118 +#define TX_BASE_PTR2 0x0250
3119 +#define TX_MAX_CNT2 0x0254
3120 +#define TX_CTX_IDX2 0x0258
3121 +#define TX_DTX_IDX2 0x025c
3122 +
3123 +/*
3124 + * AC_VO register offsets
3125 + */
3126 +#define TX_BASE_PTR3 0x0260
3127 +#define TX_MAX_CNT3 0x0264
3128 +#define TX_CTX_IDX3 0x0268
3129 +#define TX_DTX_IDX3 0x026c
3130 +
3131 +/*
3132 + * HCCA register offsets
3133 + */
3134 +#define TX_BASE_PTR4 0x0270
3135 +#define TX_MAX_CNT4 0x0274
3136 +#define TX_CTX_IDX4 0x0278
3137 +#define TX_DTX_IDX4 0x027c
3138 +
3139 +/*
3140 + * MGMT register offsets
3141 + */
3142 +#define TX_BASE_PTR5 0x0280
3143 +#define TX_MAX_CNT5 0x0284
3144 +#define TX_CTX_IDX5 0x0288
3145 +#define TX_DTX_IDX5 0x028c
3146 +
3147 +/*
3148 + * Queue register offset macros
3149 + */
3150 +#define TX_QUEUE_REG_OFFSET 0x10
3151 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3152 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3153 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3154 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3155 +
3156 +/*
3157 + * RX register offsets
3158 + */
3159 +#define RX_BASE_PTR 0x0290
3160 +#define RX_MAX_CNT 0x0294
3161 +#define RX_CRX_IDX 0x0298
3162 +#define RX_DRX_IDX 0x029c
3163 +
3164 +/*
3165 + * PBF_SYS_CTRL
3166 + * HOST_RAM_WRITE: enable Host program ram write selection
3167 + */
3168 +#define PBF_SYS_CTRL 0x0400
3169 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3170 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3171 +
3172 +/*
3173 + * PBF registers
3174 + * Most are for debug. Driver doesn't touch PBF register.
3175 + */
3176 +#define PBF_CFG 0x0408
3177 +#define PBF_MAX_PCNT 0x040c
3178 +#define PBF_CTRL 0x0410
3179 +#define PBF_INT_STA 0x0414
3180 +#define PBF_INT_ENA 0x0418
3181 +
3182 +/*
3183 + * BCN_OFFSET0:
3184 + */
3185 +#define BCN_OFFSET0 0x042c
3186 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3187 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3188 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3189 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3190 +
3191 +/*
3192 + * BCN_OFFSET1:
3193 + */
3194 +#define BCN_OFFSET1 0x0430
3195 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3196 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3197 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3198 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3199 +
3200 +/*
3201 + * PBF registers
3202 + * Most are for debug. Driver doesn't touch PBF register.
3203 + */
3204 +#define TXRXQ_PCNT 0x0438
3205 +#define PBF_DBG 0x043c
3206 +
3207 +/*
3208 + * MAC Control/Status Registers(CSR).
3209 + * Some values are set in TU, whereas 1 TU == 1024 us.
3210 + */
3211 +
3212 +/*
3213 + * MAC_CSR0: ASIC revision number.
3214 + * ASIC_REV: 0
3215 + * ASIC_VER: 2860
3216 + */
3217 +#define MAC_CSR0 0x1000
3218 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3219 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3220 +
3221 +/*
3222 + * MAC_SYS_CTRL:
3223 + */
3224 +#define MAC_SYS_CTRL 0x1004
3225 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3226 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3227 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3228 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3229 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3230 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3231 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3232 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3233 +
3234 +/*
3235 + * MAC_ADDR_DW0: STA MAC register 0
3236 + */
3237 +#define MAC_ADDR_DW0 0x1008
3238 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3239 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3240 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3241 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3242 +
3243 +/*
3244 + * MAC_ADDR_DW1: STA MAC register 1
3245 + * UNICAST_TO_ME_MASK:
3246 + * Used to mask off bits from byte 5 of the MAC address
3247 + * to determine the UNICAST_TO_ME bit for RX frames.
3248 + * The full mask is complemented by BSS_ID_MASK:
3249 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3250 + */
3251 +#define MAC_ADDR_DW1 0x100c
3252 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3253 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3254 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3255 +
3256 +/*
3257 + * MAC_BSSID_DW0: BSSID register 0
3258 + */
3259 +#define MAC_BSSID_DW0 0x1010
3260 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3261 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3262 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3263 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3264 +
3265 +/*
3266 + * MAC_BSSID_DW1: BSSID register 1
3267 + * BSS_ID_MASK:
3268 + * 0: 1-BSSID mode (BSS index = 0)
3269 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3270 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3271 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3272 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3273 + * BSSID. This will make sure that those bits will be ignored
3274 + * when determining the MY_BSS of RX frames.
3275 + */
3276 +#define MAC_BSSID_DW1 0x1014
3277 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3278 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3279 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3280 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3281 +
3282 +/*
3283 + * MAX_LEN_CFG: Maximum frame length register.
3284 + * MAX_MPDU: rt2860b max 16k bytes
3285 + * MAX_PSDU: Maximum PSDU length
3286 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3287 + */
3288 +#define MAX_LEN_CFG 0x1018
3289 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3290 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3291 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3292 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3293 +
3294 +/*
3295 + * BBP_CSR_CFG: BBP serial control register
3296 + * VALUE: Register value to program into BBP
3297 + * REG_NUM: Selected BBP register
3298 + * READ_CONTROL: 0 write BBP, 1 read BBP
3299 + * BUSY: ASIC is busy executing BBP commands
3300 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3301 + * BBP_RW_MODE: 0 serial, 1 paralell
3302 + */
3303 +#define BBP_CSR_CFG 0x101c
3304 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3305 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3306 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3307 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3308 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3309 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3310 +
3311 +/*
3312 + * RF_CSR_CFG0: RF control register
3313 + * REGID_AND_VALUE: Register value to program into RF
3314 + * BITWIDTH: Selected RF register
3315 + * STANDBYMODE: 0 high when standby, 1 low when standby
3316 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3317 + * BUSY: ASIC is busy executing RF commands
3318 + */
3319 +#define RF_CSR_CFG0 0x1020
3320 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3321 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3322 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3323 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3324 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3325 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3326 +
3327 +/*
3328 + * RF_CSR_CFG1: RF control register
3329 + * REGID_AND_VALUE: Register value to program into RF
3330 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3331 + * 0: 3 system clock cycle (37.5usec)
3332 + * 1: 5 system clock cycle (62.5usec)
3333 + */
3334 +#define RF_CSR_CFG1 0x1024
3335 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3336 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3337 +
3338 +/*
3339 + * RF_CSR_CFG2: RF control register
3340 + * VALUE: Register value to program into RF
3341 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3342 + * 0: 3 system clock cycle (37.5usec)
3343 + * 1: 5 system clock cycle (62.5usec)
3344 + */
3345 +#define RF_CSR_CFG2 0x1028
3346 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3347 +
3348 +/*
3349 + * LED_CFG: LED control
3350 + * color LED's:
3351 + * 0: off
3352 + * 1: blinking upon TX2
3353 + * 2: periodic slow blinking
3354 + * 3: always on
3355 + * LED polarity:
3356 + * 0: active low
3357 + * 1: active high
3358 + */
3359 +#define LED_CFG 0x102c
3360 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3361 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3362 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3363 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3364 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3365 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3366 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3367 +
3368 +/*
3369 + * XIFS_TIME_CFG: MAC timing
3370 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3371 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3372 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3373 + * when MAC doesn't reference BBP signal BBRXEND
3374 + * EIFS: unit 1us
3375 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3376 + *
3377 + */
3378 +#define XIFS_TIME_CFG 0x1100
3379 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3380 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3381 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3382 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3383 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3384 +
3385 +/*
3386 + * BKOFF_SLOT_CFG:
3387 + */
3388 +#define BKOFF_SLOT_CFG 0x1104
3389 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3390 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3391 +
3392 +/*
3393 + * NAV_TIME_CFG:
3394 + */
3395 +#define NAV_TIME_CFG 0x1108
3396 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3397 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3398 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3399 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3400 +
3401 +/*
3402 + * CH_TIME_CFG: count as channel busy
3403 + */
3404 +#define CH_TIME_CFG 0x110c
3405 +
3406 +/*
3407 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3408 + */
3409 +#define PBF_LIFE_TIMER 0x1110
3410 +
3411 +/*
3412 + * BCN_TIME_CFG:
3413 + * BEACON_INTERVAL: in unit of 1/16 TU
3414 + * TSF_TICKING: Enable TSF auto counting
3415 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3416 + * BEACON_GEN: Enable beacon generator
3417 + */
3418 +#define BCN_TIME_CFG 0x1114
3419 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3420 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3421 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3422 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3423 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3424 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3425 +
3426 +/*
3427 + * TBTT_SYNC_CFG:
3428 + */
3429 +#define TBTT_SYNC_CFG 0x1118
3430 +
3431 +/*
3432 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3433 + */
3434 +#define TSF_TIMER_DW0 0x111c
3435 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3436 +
3437 +/*
3438 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3439 + */
3440 +#define TSF_TIMER_DW1 0x1120
3441 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3442 +
3443 +/*
3444 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3445 + */
3446 +#define TBTT_TIMER 0x1124
3447 +
3448 +/*
3449 + * INT_TIMER_CFG:
3450 + */
3451 +#define INT_TIMER_CFG 0x1128
3452 +
3453 +/*
3454 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3455 + */
3456 +#define INT_TIMER_EN 0x112c
3457 +
3458 +/*
3459 + * CH_IDLE_STA: channel idle time
3460 + */
3461 +#define CH_IDLE_STA 0x1130
3462 +
3463 +/*
3464 + * CH_BUSY_STA: channel busy time
3465 + */
3466 +#define CH_BUSY_STA 0x1134
3467 +
3468 +/*
3469 + * MAC_STATUS_CFG:
3470 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3471 + * if 1 or higher one of the 2 registers is busy.
3472 + */
3473 +#define MAC_STATUS_CFG 0x1200
3474 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3475 +
3476 +/*
3477 + * PWR_PIN_CFG:
3478 + */
3479 +#define PWR_PIN_CFG 0x1204
3480 +
3481 +/*
3482 + * AUTOWAKEUP_CFG: Manual power control / status register
3483 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3484 + * AUTOWAKE: 0:sleep, 1:awake
3485 + */
3486 +#define AUTOWAKEUP_CFG 0x1208
3487 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3488 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3489 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3490 +
3491 +/*
3492 + * EDCA_AC0_CFG:
3493 + */
3494 +#define EDCA_AC0_CFG 0x1300
3495 +#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
3496 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3497 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3498 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3499 +
3500 +/*
3501 + * EDCA_AC1_CFG:
3502 + */
3503 +#define EDCA_AC1_CFG 0x1304
3504 +#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
3505 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3506 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3507 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3508 +
3509 +/*
3510 + * EDCA_AC2_CFG:
3511 + */
3512 +#define EDCA_AC2_CFG 0x1308
3513 +#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
3514 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3515 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3516 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3517 +
3518 +/*
3519 + * EDCA_AC3_CFG:
3520 + */
3521 +#define EDCA_AC3_CFG 0x130c
3522 +#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
3523 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3524 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3525 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3526 +
3527 +/*
3528 + * EDCA_TID_AC_MAP:
3529 + */
3530 +#define EDCA_TID_AC_MAP 0x1310
3531 +
3532 +/*
3533 + * TX_PWR_CFG_0:
3534 + */
3535 +#define TX_PWR_CFG_0 0x1314
3536 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3537 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3538 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3539 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3540 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3541 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3542 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3543 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3544 +
3545 +/*
3546 + * TX_PWR_CFG_1:
3547 + */
3548 +#define TX_PWR_CFG_1 0x1318
3549 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3550 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3551 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3552 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3553 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3554 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3555 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3556 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3557 +
3558 +/*
3559 + * TX_PWR_CFG_2:
3560 + */
3561 +#define TX_PWR_CFG_2 0x131c
3562 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3563 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3564 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3565 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3566 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3567 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3568 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3569 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3570 +
3571 +/*
3572 + * TX_PWR_CFG_3:
3573 + */
3574 +#define TX_PWR_CFG_3 0x1320
3575 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3576 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3577 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3578 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3579 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3580 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3581 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3582 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3583 +
3584 +/*
3585 + * TX_PWR_CFG_4:
3586 + */
3587 +#define TX_PWR_CFG_4 0x1324
3588 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3589 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3590 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3591 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3592 +
3593 +/*
3594 + * TX_PIN_CFG:
3595 + */
3596 +#define TX_PIN_CFG 0x1328
3597 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3598 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3599 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3600 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3601 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3602 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3603 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3604 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3605 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3606 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3607 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3608 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3609 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3610 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3611 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3612 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3613 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3614 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3615 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3616 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3617 +
3618 +/*
3619 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3620 + */
3621 +#define TX_BAND_CFG 0x132c
3622 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3623 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3624 +
3625 +/*
3626 + * TX_SW_CFG0:
3627 + */
3628 +#define TX_SW_CFG0 0x1330
3629 +
3630 +/*
3631 + * TX_SW_CFG1:
3632 + */
3633 +#define TX_SW_CFG1 0x1334
3634 +
3635 +/*
3636 + * TX_SW_CFG2:
3637 + */
3638 +#define TX_SW_CFG2 0x1338
3639 +
3640 +/*
3641 + * TXOP_THRES_CFG:
3642 + */
3643 +#define TXOP_THRES_CFG 0x133c
3644 +
3645 +/*
3646 + * TXOP_CTRL_CFG:
3647 + */
3648 +#define TXOP_CTRL_CFG 0x1340
3649 +
3650 +/*
3651 + * TX_RTS_CFG:
3652 + * RTS_THRES: unit:byte
3653 + * RTS_FBK_EN: enable rts rate fallback
3654 + */
3655 +#define TX_RTS_CFG 0x1344
3656 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3657 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3658 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3659 +
3660 +/*
3661 + * TX_TIMEOUT_CFG:
3662 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3663 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3664 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3665 + * it is recommended that:
3666 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3667 + */
3668 +#define TX_TIMEOUT_CFG 0x1348
3669 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3670 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3671 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3672 +
3673 +/*
3674 + * TX_RTY_CFG:
3675 + * SHORT_RTY_LIMIT: short retry limit
3676 + * LONG_RTY_LIMIT: long retry limit
3677 + * LONG_RTY_THRE: Long retry threshoold
3678 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3679 + * 0:expired by retry limit, 1: expired by mpdu life timer
3680 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3681 + * 0:expired by retry limit, 1: expired by mpdu life timer
3682 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3683 + */
3684 +#define TX_RTY_CFG 0x134c
3685 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3686 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3687 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3688 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3689 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3690 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3691 +
3692 +/*
3693 + * TX_LINK_CFG:
3694 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3695 + * MFB_ENABLE: TX apply remote MFB 1:enable
3696 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3697 + * 0: not apply remote remote unsolicit (MFS=7)
3698 + * TX_MRQ_EN: MCS request TX enable
3699 + * TX_RDG_EN: RDG TX enable
3700 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3701 + * REMOTE_MFB: remote MCS feedback
3702 + * REMOTE_MFS: remote MCS feedback sequence number
3703 + */
3704 +#define TX_LINK_CFG 0x1350
3705 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3706 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3707 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3708 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3709 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3710 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3711 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3712 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3713 +
3714 +/*
3715 + * HT_FBK_CFG0:
3716 + */
3717 +#define HT_FBK_CFG0 0x1354
3718 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3719 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3720 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3721 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3722 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3723 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3724 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3725 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3726 +
3727 +/*
3728 + * HT_FBK_CFG1:
3729 + */
3730 +#define HT_FBK_CFG1 0x1358
3731 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3732 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3733 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3734 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3735 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3736 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3737 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3738 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3739 +
3740 +/*
3741 + * LG_FBK_CFG0:
3742 + */
3743 +#define LG_FBK_CFG0 0x135c
3744 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3745 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3746 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3747 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3748 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3749 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3750 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
3751 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
3752 +
3753 +/*
3754 + * LG_FBK_CFG1:
3755 + */
3756 +#define LG_FBK_CFG1 0x1360
3757 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
3758 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
3759 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
3760 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
3761 +
3762 +/*
3763 + * CCK_PROT_CFG: CCK Protection
3764 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3765 + * PROTECT_CTRL: Protection control frame type for CCK TX
3766 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
3767 + * PROTECT_NAV: TXOP protection type for CCK TX
3768 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3769 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3770 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3771 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3772 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3773 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3774 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3775 + * RTS_TH_EN: RTS threshold enable on CCK TX
3776 + */
3777 +#define CCK_PROT_CFG 0x1364
3778 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3779 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3780 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3781 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3782 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3783 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3784 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3785 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3786 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3787 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3788 +
3789 +/*
3790 + * OFDM_PROT_CFG: OFDM Protection