[PATCH] Update mac80211 and make b43 driver build and load on targets other than...
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 310-rt2800_experimental.patch
1 From: Ivo van Doorn <IvDoorn@gmail.com>
2 Date: Thu, 20 Nov 2008 22:42:04 +0000 (+0100)
3 Subject: rt2x00: Add rt2800pci and rt2800usb (BROKEN)
4 X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fivd%2Frt2x00.git;a=commitdiff_plain;h=760e9f904b54ab91cd78aac6188851cfaac5c795
5
6 rt2x00: Add rt2800pci and rt2800usb (BROKEN)
7
8 incomplete code...
9
10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
11 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
12 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
13 ---
14
15 diff --git a/drivers/net/wireless/rt2x00/Makefile b/drivers/net/wireless/rt2x00/Makefile
16 index 917cb4f..99cec67 100644
17 --- a/drivers/net/wireless/rt2x00/Makefile
18 +++ b/drivers/net/wireless/rt2x00/Makefile
19 @@ -14,5 +14,7 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00usb.o
20 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
21 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
22 obj-$(CONFIG_RT61PCI) += rt61pci.o
23 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
24 obj-$(CONFIG_RT2500USB) += rt2500usb.o
25 obj-$(CONFIG_RT73USB) += rt73usb.o
26 +obj-$(CONFIG_RT2800USB) += rt2800usb.o
27 diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
28 new file mode 100644
29 index 0000000..65e9915
30 --- /dev/null
31 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
32 @@ -0,0 +1,2576 @@
33 +/*
34 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
35 + <http://rt2x00.serialmonkey.com>
36 +
37 + This program is free software; you can redistribute it and/or modify
38 + it under the terms of the GNU General Public License as published by
39 + the Free Software Foundation; either version 2 of the License, or
40 + (at your option) any later version.
41 +
42 + This program is distributed in the hope that it will be useful,
43 + but WITHOUT ANY WARRANTY; without even the implied warranty of
44 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45 + GNU General Public License for more details.
46 +
47 + You should have received a copy of the GNU General Public License
48 + along with this program; if not, write to the
49 + Free Software Foundation, Inc.,
50 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
51 + */
52 +
53 +/*
54 + Module: rt2800pci
55 + Abstract: rt2800pci device specific routines.
56 + Supported chipsets: RT2800E & RT2800ED.
57 + */
58 +
59 +#include <linux/crc-ccitt.h>
60 +#include <linux/delay.h>
61 +#include <linux/etherdevice.h>
62 +#include <linux/init.h>
63 +#include <linux/kernel.h>
64 +#include <linux/module.h>
65 +#include <linux/pci.h>
66 +#include <linux/eeprom_93cx6.h>
67 +
68 +#include "rt2x00.h"
69 +#include "rt2x00pci.h"
70 +#include "rt2800pci.h"
71 +
72 +/*
73 + * Allow hardware encryption to be disabled.
74 + */
75 +static int modparam_nohwcrypt = 0;
76 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
77 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
78 +
79 +/*
80 + * Register access.
81 + * BBP and RF register require indirect register access,
82 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
83 + * These indirect registers work with busy bits,
84 + * and we will try maximal REGISTER_BUSY_COUNT times to access
85 + * the register while taking a REGISTER_BUSY_DELAY us delay
86 + * between each attampt. When the busy bit is still set at that time,
87 + * the access attempt is considered to have failed,
88 + * and we will print an error.
89 + */
90 +#define WAIT_FOR_BBP(__dev, __reg) \
91 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
92 +#define WAIT_FOR_RF(__dev, __reg) \
93 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
94 +#define WAIT_FOR_MCU(__dev, __reg) \
95 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
96 + H2M_MAILBOX_CSR_OWNER, (__reg))
97 +
98 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
99 + const unsigned int word, const u8 value)
100 +{
101 + u32 reg;
102 +
103 + mutex_lock(&rt2x00dev->csr_mutex);
104 +
105 + /*
106 + * Wait until the BBP becomes available, afterwards we
107 + * can safely write the new data into the register.
108 + */
109 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
110 + reg = 0;
111 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
112 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
113 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
114 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
115 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
116 +
117 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
118 + }
119 +
120 + mutex_unlock(&rt2x00dev->csr_mutex);
121 +}
122 +
123 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
124 + const unsigned int word, u8 *value)
125 +{
126 + u32 reg;
127 +
128 + mutex_lock(&rt2x00dev->csr_mutex);
129 +
130 + /*
131 + * Wait until the BBP becomes available, afterwards we
132 + * can safely write the read request into the register.
133 + * After the data has been written, we wait until hardware
134 + * returns the correct value, if at any time the register
135 + * doesn't become available in time, reg will be 0xffffffff
136 + * which means we return 0xff to the caller.
137 + */
138 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
139 + reg = 0;
140 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
141 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
142 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
143 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
144 +
145 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
146 +
147 + WAIT_FOR_BBP(rt2x00dev, &reg);
148 + }
149 +
150 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
151 +
152 + mutex_unlock(&rt2x00dev->csr_mutex);
153 +}
154 +
155 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
156 + const unsigned int word, const u32 value)
157 +{
158 + u32 reg;
159 +
160 + if (!word)
161 + return;
162 +
163 + mutex_lock(&rt2x00dev->csr_mutex);
164 +
165 + /*
166 + * Wait until the RF becomes available, afterwards we
167 + * can safely write the new data into the register.
168 + */
169 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
170 + reg = 0;
171 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
172 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
173 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
174 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
175 +
176 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
177 + rt2x00_rf_write(rt2x00dev, word, value);
178 + }
179 +
180 + mutex_unlock(&rt2x00dev->csr_mutex);
181 +}
182 +
183 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
184 + const u8 command, const u8 token,
185 + const u8 arg0, const u8 arg1)
186 +{
187 + u32 reg;
188 +
189 + mutex_lock(&rt2x00dev->csr_mutex);
190 +
191 + /*
192 + * Wait until the MCU becomes available, afterwards we
193 + * can safely write the new data into the register.
194 + */
195 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
196 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
197 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
198 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
199 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
200 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
201 +
202 + reg = 0;
203 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
204 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
205 + }
206 +
207 + mutex_unlock(&rt2x00dev->csr_mutex);
208 +}
209 +
210 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
211 +{
212 + struct rt2x00_dev *rt2x00dev = eeprom->data;
213 + u32 reg;
214 +
215 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
216 +
217 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
218 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
219 + eeprom->reg_data_clock =
220 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
221 + eeprom->reg_chip_select =
222 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
223 +}
224 +
225 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
226 +{
227 + struct rt2x00_dev *rt2x00dev = eeprom->data;
228 + u32 reg = 0;
229 +
230 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
231 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
232 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
233 + !!eeprom->reg_data_clock);
234 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
235 + !!eeprom->reg_chip_select);
236 +
237 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
238 +}
239 +
240 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
241 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
242 + .owner = THIS_MODULE,
243 + .csr = {
244 + .read = rt2x00pci_register_read,
245 + .write = rt2x00pci_register_write,
246 + .flags = RT2X00DEBUGFS_OFFSET,
247 + .word_base = CSR_REG_BASE,
248 + .word_size = sizeof(u32),
249 + .word_count = CSR_REG_SIZE / sizeof(u32),
250 + },
251 + .eeprom = {
252 + .read = rt2x00_eeprom_read,
253 + .write = rt2x00_eeprom_write,
254 + .word_base = EEPROM_BASE,
255 + .word_size = sizeof(u16),
256 + .word_count = EEPROM_SIZE / sizeof(u16),
257 + },
258 + .bbp = {
259 + .read = rt2800pci_bbp_read,
260 + .write = rt2800pci_bbp_write,
261 + .word_base = BBP_BASE,
262 + .word_size = sizeof(u8),
263 + .word_count = BBP_SIZE / sizeof(u8),
264 + },
265 + .rf = {
266 + .read = rt2x00_rf_read,
267 + .write = rt2800pci_rf_write,
268 + .word_base = RF_BASE,
269 + .word_size = sizeof(u32),
270 + .word_count = RF_SIZE / sizeof(u32),
271 + },
272 +};
273 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
274 +
275 +#ifdef CONFIG_RT2X00_LIB_RFKILL
276 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
277 +{
278 + u32 reg;
279 +
280 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
281 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
282 +}
283 +#else
284 +#define rt2800pci_rfkill_poll NULL
285 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
286 +
287 +#ifdef CONFIG_RT2X00_LIB_LEDS
288 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
289 + enum led_brightness brightness)
290 +{
291 + struct rt2x00_led *led =
292 + container_of(led_cdev, struct rt2x00_led, led_dev);
293 + unsigned int enabled = brightness != LED_OFF;
294 + unsigned int bg_mode =
295 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
296 + unsigned int polarity =
297 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
298 + EEPROM_FREQ_LED_POLARITY);
299 + unsigned int ledmode =
300 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
301 + EEPROM_FREQ_LED_MODE);
302 +
303 + if (led->type == LED_TYPE_RADIO) {
304 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
305 + enabled ? 0x20 : 0);
306 + } else if (led->type == LED_TYPE_ASSOC) {
307 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
308 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
309 + } else if (led->type == LED_TYPE_QUALITY) {
310 + /*
311 + * The brightness is divided into 6 levels (0 - 5),
312 + * The specs tell us the following levels:
313 + * 0, 1 ,3, 7, 15, 31
314 + * to determine the level in a simple way we can simply
315 + * work with bitshifting:
316 + * (1 << level) - 1
317 + */
318 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
319 + (1 << brightness / (LED_FULL / 6)) - 1,
320 + polarity);
321 + }
322 +}
323 +
324 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
325 + unsigned long *delay_on,
326 + unsigned long *delay_off)
327 +{
328 + struct rt2x00_led *led =
329 + container_of(led_cdev, struct rt2x00_led, led_dev);
330 + u32 reg;
331 +
332 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
333 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
334 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
335 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
336 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
337 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
338 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
339 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
340 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
341 +
342 + return 0;
343 +}
344 +
345 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
346 + struct rt2x00_led *led,
347 + enum led_type type)
348 +{
349 + led->rt2x00dev = rt2x00dev;
350 + led->type = type;
351 + led->led_dev.brightness_set = rt2800pci_brightness_set;
352 + led->led_dev.blink_set = rt2800pci_blink_set;
353 + led->flags = LED_INITIALIZED;
354 +}
355 +#endif /* CONFIG_RT2X00_LIB_LEDS */
356 +
357 +/*
358 + * Configuration handlers.
359 + */
360 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
361 + struct rt2x00lib_crypto *crypto,
362 + struct ieee80211_key_conf *key)
363 +{
364 + u32 offset;
365 + u32 reg;
366 +
367 + offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
368 +
369 + reg = 0;
370 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
371 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
372 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
373 + crypto->cipher);
374 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
375 + (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
376 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
377 + rt2x00pci_register_write(rt2x00dev, offset, reg);
378 +}
379 +
380 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
381 + struct rt2x00lib_crypto *crypto,
382 + struct ieee80211_key_conf *key)
383 +{
384 + struct hw_key_entry key_entry;
385 + struct rt2x00_field32 field;
386 + u32 offset;
387 + u32 mask;
388 + u32 reg;
389 +
390 + if (crypto->cmd == SET_KEY) {
391 + memcpy(key_entry.key, crypto->key,
392 + sizeof(key_entry.key));
393 + memcpy(key_entry.tx_mic, crypto->tx_mic,
394 + sizeof(key_entry.tx_mic));
395 + memcpy(key_entry.rx_mic, crypto->rx_mic,
396 + sizeof(key_entry.rx_mic));
397 +
398 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
399 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
400 + &key_entry, sizeof(key_entry));
401 +
402 + /*
403 + * The driver does not support the IV/EIV generation
404 + * in hardware. However it doesn't support the IV/EIV
405 + * inside the ieee80211 frame either, but requires it
406 + * to be provided seperately for the descriptor.
407 + * rt2x00lib will cut the IV/EIV data out of all frames
408 + * given to us by mac80211, but we must tell mac80211
409 + * to generate the IV/EIV data.
410 + */
411 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
412 + }
413 +
414 + /*
415 + * The cipher types are stored over multiple registers
416 + * starting with SHARED_KEY_MODE_BASE each word will have
417 + * 32 bits and contains the cipher types for 2 modes each.
418 + * Using the correct defines correctly will cause overhead,
419 + * so just calculate the correct offset.
420 + */
421 + mask = key->hw_key_idx % 8;
422 + field.bit_offset = (3 * mask);
423 + field.bit_mask = 0x7 << field.bit_offset;
424 +
425 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
426 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
427 + rt2x00_set_field32(&reg, field,
428 + (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
429 + rt2x00pci_register_write(rt2x00dev, offset, reg);
430 +
431 + /*
432 + * Update WCID information
433 + */
434 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
435 +
436 + return 0;
437 +}
438 +
439 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
440 + struct rt2x00lib_crypto *crypto,
441 + struct ieee80211_key_conf *key)
442 +{
443 + struct hw_key_entry key_entry;
444 + u32 offset;
445 +
446 + /*
447 + * 1 pairwise key is possible per AID, this means that the AID
448 + * equals our hw_key_idx.
449 + */
450 + key->hw_key_idx = crypto->aid;
451 +
452 + if (crypto->cmd == SET_KEY) {
453 + memcpy(key_entry.key, crypto->key,
454 + sizeof(key_entry.key));
455 + memcpy(key_entry.tx_mic, crypto->tx_mic,
456 + sizeof(key_entry.tx_mic));
457 + memcpy(key_entry.rx_mic, crypto->rx_mic,
458 + sizeof(key_entry.rx_mic));
459 +
460 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
461 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
462 + &key_entry, sizeof(key_entry));
463 +
464 + /*
465 + * The driver does not support the IV/EIV generation
466 + * in hardware. However it doesn't support the IV/EIV
467 + * inside the ieee80211 frame either, but requires it
468 + * to be provided seperately for the descriptor.
469 + * rt2x00lib will cut the IV/EIV data out of all frames
470 + * given to us by mac80211, but we must tell mac80211
471 + * to generate the IV/EIV data.
472 + */
473 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
474 + }
475 +
476 + /*
477 + * Update WCID information
478 + */
479 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
480 +
481 + return 0;
482 +}
483 +
484 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
485 + const unsigned int filter_flags)
486 +{
487 + u32 reg;
488 +
489 + /*
490 + * Start configuration steps.
491 + * Note that the version error will always be dropped
492 + * and broadcast frames will always be accepted since
493 + * there is no filter for it at this time.
494 + */
495 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
496 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
497 + !(filter_flags & FIF_FCSFAIL));
498 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
499 + !(filter_flags & FIF_PLCPFAIL));
500 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
501 + !(filter_flags & FIF_PROMISC_IN_BSS));
502 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD,
503 + !(filter_flags & FIF_OTHER_BSS));
504 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
505 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
506 + !(filter_flags & FIF_ALLMULTI));
507 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
508 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
509 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
510 + !(filter_flags & FIF_CONTROL));
511 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
512 + !(filter_flags & FIF_CONTROL));
513 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
514 + !(filter_flags & FIF_CONTROL));
515 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
516 + !(filter_flags & FIF_CONTROL));
517 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
518 + !(filter_flags & FIF_CONTROL));
519 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
520 + !(filter_flags & FIF_CONTROL));
521 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
522 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
523 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
524 + !(filter_flags & FIF_CONTROL));
525 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
526 +}
527 +
528 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
529 + struct rt2x00_intf *intf,
530 + struct rt2x00intf_conf *conf,
531 + const unsigned int flags)
532 +{
533 + unsigned int beacon_base;
534 + u32 reg;
535 +
536 + if (flags & CONFIG_UPDATE_TYPE) {
537 + /*
538 + * Clear current synchronisation setup.
539 + * For the Beacon base registers we only need to clear
540 + * the first byte since that byte contains the VALID and OWNER
541 + * bits which (when set to 0) will invalidate the entire beacon.
542 + */
543 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
544 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
545 +
546 + /*
547 + * Enable synchronisation.
548 + */
549 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
550 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
551 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
552 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
553 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
554 + }
555 +
556 + if (flags & CONFIG_UPDATE_MAC) {
557 + reg = le32_to_cpu(conf->mac[1]);
558 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
559 + conf->mac[1] = cpu_to_le32(reg);
560 +
561 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
562 + conf->mac, sizeof(conf->mac));
563 + }
564 +
565 + if (flags & CONFIG_UPDATE_BSSID) {
566 + reg = le32_to_cpu(conf->bssid[1]);
567 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
568 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
569 + conf->bssid[1] = cpu_to_le32(reg);
570 +
571 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
572 + conf->bssid, sizeof(conf->bssid));
573 + }
574 +}
575 +
576 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
577 + struct rt2x00lib_erp *erp)
578 +{
579 + u32 reg;
580 +
581 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
582 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
583 + erp->ack_timeout);
584 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
585 +
586 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
587 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
588 + !!erp->short_preamble);
589 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
590 + !!erp->short_preamble);
591 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
592 +
593 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
594 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
595 + erp->cts_protection ? 2 : 0);
596 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
597 +
598 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
599 + erp->basic_rates);
600 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE,
601 + erp->basic_rates >> 32);
602 +
603 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
604 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
605 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
606 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
607 +
608 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
609 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
610 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
611 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
612 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
613 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
614 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
615 +}
616 +
617 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
618 + struct antenna_setup *ant)
619 +{
620 + u16 eeprom;
621 + u8 r1;
622 + u8 r3;
623 +
624 + /*
625 + * FIXME: Use requested antenna configuration.
626 + */
627 +
628 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
629 +
630 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
631 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
632 +
633 + /*
634 + * Configure the TX antenna.
635 + */
636 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
637 + case 1:
638 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
639 + break;
640 + case 2:
641 + case 3:
642 + /* Do nothing */
643 + break;
644 + }
645 +
646 + /*
647 + * Configure the RX antenna.
648 + */
649 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
650 + case 1:
651 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
652 + break;
653 + case 2:
654 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
655 + break;
656 + case 3:
657 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
658 + break;
659 + }
660 +
661 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
662 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
663 +}
664 +
665 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
666 + struct rt2x00lib_conf *libconf)
667 +{
668 + u16 eeprom;
669 + short lna_gain;
670 +
671 + if (libconf->rf.channel <= 14) {
672 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
673 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
674 + } else if (libconf->rf.channel <= 64) {
675 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
676 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
677 + } else if (libconf->rf.channel <= 128) {
678 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
679 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
680 + } else {
681 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
682 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
683 + }
684 +
685 + rt2x00dev->lna_gain = lna_gain;
686 +}
687 +
688 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
689 + struct rf_channel *rf,
690 + struct channel_info *info)
691 +{
692 + u32 reg;
693 + unsigned int tx_pin;
694 + u16 eeprom;
695 +
696 + tx_pin = 0;
697 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
698 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
699 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
700 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
701 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
702 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
703 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
704 +
705 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
706 +
707 + /*
708 + * Determine antenna settings from EEPROM
709 + */
710 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
711 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
712 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
713 + /* Turn off unused PA or LNA when only 1T or 1R */
714 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
715 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
716 + }
717 +
718 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
719 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
720 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
721 + /* Turn off unused PA or LNA when only 1T or 1R */
722 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
723 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
724 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
725 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
726 +
727 + if (rf->channel > 14) {
728 + /*
729 + * When TX power is below 0, we should increase it by 7 to
730 + * make it a positive value (Minumum value is -7).
731 + * However this means that values between 0 and 7 have
732 + * double meaning, and we should set a 7DBm boost flag.
733 + */
734 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
735 + (info->tx_power1 >= 0));
736 +
737 + if (info->tx_power1 < 0)
738 + info->tx_power1 += 7;
739 +
740 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
741 + TXPOWER_A_TO_DEV(info->tx_power1));
742 +
743 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
744 + (info->tx_power2 >= 0));
745 +
746 + if (info->tx_power2 < 0)
747 + info->tx_power2 += 7;
748 +
749 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
750 + TXPOWER_A_TO_DEV(info->tx_power2));
751 +
752 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
753 + } else {
754 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
755 + TXPOWER_G_TO_DEV(info->tx_power1));
756 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
757 + TXPOWER_G_TO_DEV(info->tx_power2));
758 +
759 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
760 + }
761 +
762 + /* FIXME: How to determine bandwidth
763 + rt2x00_set_field32(&rf->rf4, RF4_BW40, !!(BBPCurrentBW == BW_40));
764 + */
765 +
766 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
767 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
768 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
769 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
770 +
771 + udelay(200);
772 +
773 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
774 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
775 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
776 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
777 +
778 + udelay(200);
779 +
780 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
781 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
782 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
783 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
784 +
785 + /*
786 + * Change BBP settings
787 + */
788 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
789 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
790 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
791 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
792 +
793 + if (rf->channel <= 14) {
794 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
795 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
796 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
797 + } else {
798 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
799 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
800 + }
801 +
802 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
803 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
804 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
805 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
806 + } else {
807 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
808 +
809 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
810 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
811 + else
812 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
813 +
814 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
815 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
816 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
817 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
818 + }
819 +
820 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
821 +
822 + msleep(1);
823 +}
824 +
825 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
826 + const int txpower)
827 +{
828 + u32 reg;
829 + u32 value = TXPOWER_G_TO_DEV(txpower);
830 + u8 r1;
831 +
832 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
833 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
834 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
835 +
836 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
837 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
838 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
839 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
840 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
841 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
842 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
843 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
844 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
845 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
846 +
847 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
848 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
849 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
850 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
851 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
852 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
853 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
854 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
855 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
856 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
857 +
858 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
859 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
860 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
861 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
862 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
863 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
864 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
865 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
866 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
867 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
868 +
869 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
870 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
871 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
872 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
873 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
874 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
875 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
876 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
877 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
878 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
879 +
880 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
881 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
882 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
883 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
884 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
885 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
886 +}
887 +
888 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
889 + struct rt2x00lib_conf *libconf)
890 +{
891 + u32 reg;
892 +
893 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
894 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
895 + libconf->conf->short_frame_max_tx_count);
896 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
897 + libconf->conf->long_frame_max_tx_count);
898 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
899 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
900 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
901 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
902 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
903 +}
904 +
905 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
906 + struct rt2x00lib_conf *libconf)
907 +{
908 + u32 reg;
909 +
910 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
911 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
912 + libconf->conf->beacon_int * 16);
913 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
914 +}
915 +
916 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
917 + struct rt2x00lib_conf *libconf,
918 + const unsigned int flags)
919 +{
920 + /* Always recalculate LNA gain before changing configuration */
921 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
922 +
923 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
924 + rt2800pci_config_channel(rt2x00dev, &libconf->rf,
925 + &libconf->channel);
926 + if (flags & IEEE80211_CONF_CHANGE_POWER)
927 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
928 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
929 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
930 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
931 + rt2800pci_config_duration(rt2x00dev, libconf);
932 +}
933 +
934 +/*
935 + * Link tuning
936 + */
937 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
938 + struct link_qual *qual)
939 +{
940 + u32 reg;
941 +
942 + /*
943 + * Update FCS error count from register.
944 + */
945 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
946 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
947 +
948 + /*
949 + * Update False CCA count from register.
950 + */
951 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
952 + qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
953 +}
954 +
955 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
956 +{
957 + u8 r66;
958 +
959 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
960 + r66 = 0x2e + rt2x00dev->lna_gain;
961 + else {
962 + if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
963 + r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
964 + else
965 + r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
966 + }
967 +
968 + rt2800pci_bbp_write(rt2x00dev, 66, r66);
969 +}
970 +
971 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev)
972 +{
973 + int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
974 + u8 r66_orig;
975 + u8 r66;
976 +
977 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C)
978 + return;
979 +
980 + rt2800pci_bbp_read(rt2x00dev, 66, &r66_orig);
981 + r66 = r66_orig;
982 +
983 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
984 + r66 = 0x2e + rt2x00dev->lna_gain;
985 + } else {
986 + if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
987 + r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
988 + else
989 + r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
990 + }
991 +
992 + if (rssi > -80)
993 + r66 += 0x10;
994 +
995 + if (rssi != r66_orig)
996 + rt2800pci_bbp_write(rt2x00dev, 66, r66);
997 +}
998 +
999 +/*
1000 + * Firmware functions
1001 + */
1002 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1003 +{
1004 + return FIRMWARE_RT2860;
1005 +}
1006 +
1007 +static u16 rt2800pci_get_firmware_crc(const void *data, const size_t len)
1008 +{
1009 + u16 crc;
1010 +
1011 + /*
1012 + * Use the crc ccitt algorithm.
1013 + * This will return the same value as the legacy driver which
1014 + * used bit ordering reversion on the both the firmware bytes
1015 + * before input input as well as on the final output.
1016 + * Obviously using crc ccitt directly is much more efficient.
1017 + * The last 2 bytes in the firmware array are the crc checksum itself,
1018 + * this means that we should never pass those 2 bytes to the crc
1019 + * algorithm.
1020 + */
1021 + crc = crc_ccitt(~0, data, len - 2);
1022 +
1023 + /*
1024 + * There is a small difference between the crc-itu-t + bitrev and
1025 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1026 + * will be swapped, use swab16 to convert the crc to the correct
1027 + * value.
1028 + */
1029 + return swab16(crc);
1030 +}
1031 +
1032 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1033 + const void *data, const size_t len)
1034 +{
1035 + unsigned int i;
1036 + u32 reg;
1037 +
1038 + /*
1039 + * Wait for stable hardware.
1040 + */
1041 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1042 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1043 + if (reg && reg != ~0)
1044 + break;
1045 + msleep(1);
1046 + }
1047 +
1048 + if (i == REGISTER_BUSY_COUNT) {
1049 + ERROR(rt2x00dev, "Unstable hardware.\n");
1050 + return -EBUSY;
1051 + }
1052 +
1053 + /*
1054 + * Disable DMA, will be reenabled later when enabling
1055 + * the radio.
1056 + */
1057 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1058 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1059 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1060 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1061 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1062 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1063 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1064 +
1065 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, ~0);
1066 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e1f);
1067 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e00);
1068 +
1069 + /*
1070 + * enable Host program ram write selection
1071 + */
1072 + reg = 0;
1073 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1074 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1075 +
1076 + /*
1077 + * Write firmware to device.
1078 + */
1079 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1080 + data, len);
1081 +
1082 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1083 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1084 +
1085 + /*
1086 + * Wait for device to stabilize.
1087 + */
1088 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1089 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1090 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1091 + break;
1092 + msleep(1);
1093 + }
1094 +
1095 + if (i == REGISTER_BUSY_COUNT) {
1096 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1097 + return -EBUSY;
1098 + }
1099 +
1100 + /*
1101 + * Initialize BBP R/W access agent
1102 + */
1103 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1104 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1105 +
1106 + return 0;
1107 +}
1108 +
1109 +/*
1110 + * Initialization functions.
1111 + */
1112 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1113 +{
1114 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1115 + u32 word;
1116 +
1117 + if (entry->queue->qid == QID_RX) {
1118 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1119 +
1120 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1121 + } else {
1122 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1123 +
1124 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1125 + }
1126 +}
1127 +
1128 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1129 +{
1130 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1131 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1132 + u32 word;
1133 +
1134 + if (entry->queue->qid == QID_RX) {
1135 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1136 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1137 + rt2x00_desc_write(entry_priv->desc, 0, word);
1138 +
1139 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1140 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1141 + rt2x00_desc_write(entry_priv->desc, 1, word);
1142 + } else {
1143 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1144 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1145 + rt2x00_desc_write(entry_priv->desc, 1, word);
1146 + }
1147 +}
1148 +
1149 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1150 +{
1151 + struct queue_entry_priv_pci *entry_priv;
1152 + u32 reg;
1153 +
1154 + /*
1155 + * Initialize registers.
1156 + */
1157 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1158 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1159 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1160 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1161 +
1162 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1163 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1164 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1165 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1166 +
1167 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1168 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1169 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1170 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1171 +
1172 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1173 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1174 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1175 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1176 +
1177 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1178 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1179 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1180 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1181 +
1182 + /*
1183 + * Enable global DMA configuration
1184 + */
1185 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1186 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1187 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1188 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1189 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1190 +
1191 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1192 +
1193 + return 0;
1194 +}
1195 +
1196 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1197 +{
1198 + u32 reg;
1199 + unsigned int i;
1200 +
1201 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1202 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1203 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1204 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1205 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1206 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1207 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1208 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1209 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1210 +
1211 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1212 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000000);
1213 +
1214 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1215 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1216 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1217 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1218 +
1219 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1220 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1221 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1222 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1223 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1224 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1225 +
1226 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1227 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1228 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1229 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1230 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1231 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1232 +
1233 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1234 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1235 +
1236 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1237 +
1238 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1239 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1240 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1241 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1242 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1243 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1244 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1245 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1246 +
1247 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1248 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1249 +
1250 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1251 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1252 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1253 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1254 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1255 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1256 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1257 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1258 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1259 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1260 +
1261 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1262 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1263 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1264 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1265 +
1266 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1267 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1268 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1269 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1270 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1271 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1272 +
1273 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1274 +
1275 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1276 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1277 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1278 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1279 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1280 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1281 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1282 +
1283 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1284 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1285 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1286 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1287 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1288 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1289 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1290 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1291 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1292 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1293 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1294 +
1295 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1296 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1297 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1298 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1299 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1300 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1301 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1302 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1303 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1304 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1305 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1306 +
1307 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1308 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1309 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1310 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1311 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1312 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1313 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1314 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1315 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1316 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1317 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1318 +
1319 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1320 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1321 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1322 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1323 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1324 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1325 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1326 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1327 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1328 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1329 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1330 +
1331 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1332 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1333 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1334 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1335 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1336 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1337 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1338 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1339 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1340 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1341 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1342 +
1343 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1344 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1345 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1346 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1347 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1348 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1349 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1350 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1351 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1352 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1353 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1354 +
1355 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1356 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1357 +
1358 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1359 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1360 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1361 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1362 +
1363 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1364 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1365 +
1366 + /*
1367 + * ASIC will keep garbage value after boot, clear encryption keys.
1368 + */
1369 + for (i = 0; i < 254; i++) {
1370 + u32 wcid[2] = { 0xffffffff, 0x0000ffff };
1371 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1372 + wcid, sizeof(wcid));
1373 + }
1374 +
1375 + for (i = 0; i < 4; i++)
1376 + rt2x00pci_register_write(rt2x00dev,
1377 + SHARED_KEY_MODE_ENTRY(i), 0);
1378 +
1379 + for (i = 0; i < 256; i++)
1380 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1381 +
1382 + /*
1383 + * Clear all beacons
1384 + * For the Beacon base registers we only need to clear
1385 + * the first byte since that byte contains the VALID and OWNER
1386 + * bits which (when set to 0) will invalidate the entire beacon.
1387 + */
1388 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1389 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1390 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1391 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1392 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1393 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1394 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1395 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1396 +
1397 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1398 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1399 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1400 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1401 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1402 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1403 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1404 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1405 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1406 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1407 +
1408 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1409 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1410 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1411 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1412 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1413 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1414 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1415 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1416 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1417 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1418 +
1419 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1420 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1421 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1422 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1423 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1424 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1425 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1426 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1427 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1428 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1429 +
1430 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1431 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1432 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1433 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1434 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1435 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1436 +
1437 + /*
1438 + * We must clear the error counters.
1439 + * These registers are cleared on read,
1440 + * so we may pass a useless variable to store the value.
1441 + */
1442 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1443 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1444 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1445 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1446 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1447 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1448 +
1449 + return 0;
1450 +}
1451 +
1452 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1453 +{
1454 + unsigned int i;
1455 + u32 reg;
1456 +
1457 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1458 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1459 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1460 + return 0;
1461 +
1462 + udelay(REGISTER_BUSY_DELAY);
1463 + }
1464 +
1465 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1466 + return -EACCES;
1467 +}
1468 +
1469 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1470 +{
1471 + unsigned int i;
1472 + u8 value;
1473 +
1474 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1475 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1476 + if ((value != 0xff) && (value != 0x00))
1477 + return 0;
1478 + udelay(REGISTER_BUSY_DELAY);
1479 + }
1480 +
1481 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1482 + return -EACCES;
1483 +}
1484 +
1485 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1486 +{
1487 + unsigned int i;
1488 + u16 eeprom;
1489 + u8 reg_id;
1490 + u8 value;
1491 +
1492 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1493 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1494 + return -EACCES;
1495 +
1496 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1497 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1498 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1499 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1500 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1501 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1502 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1503 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1504 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1505 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1506 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1507 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1508 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1509 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1510 +
1511 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C) {
1512 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1513 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1514 + }
1515 +
1516 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_D)
1517 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1518 +
1519 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1520 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1521 +
1522 + if (eeprom != 0xffff && eeprom != 0x0000) {
1523 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1524 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1525 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1526 + }
1527 + }
1528 +
1529 + return 0;
1530 +}
1531 +
1532 +/*
1533 + * Device state switch handlers.
1534 + */
1535 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1536 + enum dev_state state)
1537 +{
1538 + u32 reg;
1539 +
1540 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1541 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1542 + (state == STATE_RADIO_RX_ON) ||
1543 + (state == STATE_RADIO_RX_ON_LINK));
1544 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1545 +}
1546 +
1547 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1548 + enum dev_state state)
1549 +{
1550 + int mask = (state == STATE_RADIO_IRQ_ON);
1551 + u32 reg;
1552 +
1553 + /*
1554 + * When interrupts are being enabled, the interrupt registers
1555 + * should clear the register to assure a clean state.
1556 + */
1557 + if (state == STATE_RADIO_IRQ_ON) {
1558 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1559 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1560 + }
1561 +
1562 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1563 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1564 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1565 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1566 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1567 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1568 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1569 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1570 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1571 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1572 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1573 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1574 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1575 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1576 +}
1577 +
1578 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1579 +{
1580 + unsigned int i;
1581 + u32 reg;
1582 +
1583 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1584 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1585 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1586 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1587 + return 0;
1588 +
1589 + msleep(1);
1590 + }
1591 +
1592 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1593 + return -EACCES;
1594 +}
1595 +
1596 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1597 +{
1598 + u32 reg;
1599 + u16 word;
1600 +
1601 + /*
1602 + * Initialize all registers.
1603 + */
1604 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1605 + rt2800pci_init_queues(rt2x00dev) ||
1606 + rt2800pci_init_registers(rt2x00dev) ||
1607 + rt2800pci_init_bbp(rt2x00dev)))
1608 + return -EIO;
1609 +
1610 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001a80);
1611 +
1612 + /* Wait for DMA, ignore error */
1613 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1614 +
1615 + /*
1616 + * Enable RX.
1617 + */
1618 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1619 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1620 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1621 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1622 +
1623 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1624 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1625 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1626 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1627 +
1628 + /*
1629 + * Initialize LED control
1630 + */
1631 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1632 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1633 + word & 0xff, (word >> 8) & 0xff);
1634 +
1635 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1636 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1637 + word & 0xff, (word >> 8) & 0xff);
1638 +
1639 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1640 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1641 + word & 0xff, (word >> 8) & 0xff);
1642 +
1643 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1644 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1645 +
1646 + /*
1647 + * Send signal to firmware during boot time.
1648 + */
1649 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1650 +
1651 + return 0;
1652 +}
1653 +
1654 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1655 +{
1656 + u32 reg;
1657 +
1658 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1659 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1660 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1661 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1662 +
1663 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1664 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1665 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1666 +
1667 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1668 +
1669 + /* Wait for DMA, ignore error */
1670 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1671 +}
1672 +
1673 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1674 + enum dev_state state)
1675 +{
1676 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1677 +
1678 + if (state == STATE_AWAKE)
1679 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1680 + else
1681 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1682 +
1683 + return 0;
1684 +}
1685 +
1686 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1687 + enum dev_state state)
1688 +{
1689 + int retval = 0;
1690 +
1691 + switch (state) {
1692 + case STATE_RADIO_ON:
1693 + /*
1694 + * Before the radio can be enabled, the device first has
1695 + * to be woken up. After that it needs a bit of time
1696 + * to be fully awake and the radio can be enabled.
1697 + */
1698 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1699 + msleep(1);
1700 + retval = rt2800pci_enable_radio(rt2x00dev);
1701 + break;
1702 + case STATE_RADIO_OFF:
1703 + /*
1704 + * After the radio has been disablee, the device should
1705 + * be put to sleep for powersaving.
1706 + */
1707 + rt2800pci_disable_radio(rt2x00dev);
1708 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1709 + break;
1710 + case STATE_RADIO_RX_ON:
1711 + case STATE_RADIO_RX_ON_LINK:
1712 + case STATE_RADIO_RX_OFF:
1713 + case STATE_RADIO_RX_OFF_LINK:
1714 + rt2800pci_toggle_rx(rt2x00dev, state);
1715 + break;
1716 + case STATE_RADIO_IRQ_ON:
1717 + case STATE_RADIO_IRQ_OFF:
1718 + rt2800pci_toggle_irq(rt2x00dev, state);
1719 + break;
1720 + case STATE_DEEP_SLEEP:
1721 + case STATE_SLEEP:
1722 + case STATE_STANDBY:
1723 + case STATE_AWAKE:
1724 + retval = rt2800pci_set_state(rt2x00dev, state);
1725 + break;
1726 + default:
1727 + retval = -ENOTSUPP;
1728 + break;
1729 + }
1730 +
1731 + if (unlikely(retval))
1732 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1733 + state, retval);
1734 +
1735 + return retval;
1736 +}
1737 +
1738 +/*
1739 + * TX descriptor initialization
1740 + */
1741 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1742 + struct sk_buff *skb,
1743 + struct txentry_desc *txdesc)
1744 +{
1745 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1746 + __le32 *txd = skbdesc->desc;
1747 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1748 + u32 word;
1749 +
1750 + /*
1751 + * Initialize TX Info descriptor
1752 + */
1753 + rt2x00_desc_read(txwi, 0, &word);
1754 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1755 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1756 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1757 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1758 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1759 + rt2x00_set_field32(&word, TXWI_W0_TS,
1760 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1761 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1762 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1763 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1764 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1765 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1766 + rt2x00_set_field32(&word, TXWI_W0_BW,
1767 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1768 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1769 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1770 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1771 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1772 + rt2x00_desc_write(txwi, 0, word);
1773 +
1774 + rt2x00_desc_read(txwi, 1, &word);
1775 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1776 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1777 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1778 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1779 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1780 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
1781 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1782 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1783 + skbdesc->entry->entry_idx);
1784 + rt2x00_desc_write(txwi, 1, word);
1785 +
1786 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1787 + _rt2x00_desc_write(txwi, 2, skbdesc->iv);
1788 + _rt2x00_desc_write(txwi, 3, skbdesc->eiv);
1789 + }
1790 +
1791 + /*
1792 + * Initialize TX descriptor
1793 + */
1794 + rt2x00_desc_read(txd, 0, &word);
1795 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1796 + rt2x00_desc_write(txd, 0, word);
1797 +
1798 + rt2x00_desc_read(txd, 1, &word);
1799 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1800 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1801 + rt2x00_set_field32(&word, TXD_W1_BURST,
1802 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1803 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1804 + rt2x00dev->hw->extra_tx_headroom);
1805 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1806 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1807 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1808 + rt2x00_desc_write(txd, 1, word);
1809 +
1810 + rt2x00_desc_read(txd, 2, &word);
1811 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1812 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1813 + rt2x00_desc_write(txd, 2, word);
1814 +
1815 + rt2x00_desc_read(txd, 3, &word);
1816 + rt2x00_set_field32(&word, TXD_W3_WIV, 1);
1817 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1818 + rt2x00_desc_write(txd, 3, word);
1819 +}
1820 +
1821 +/*
1822 + * TX data initialization
1823 + */
1824 +static void rt2800pci_write_beacon(struct queue_entry *entry)
1825 +{
1826 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1827 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1828 + unsigned int beacon_base;
1829 + u32 reg;
1830 +
1831 + /*
1832 + * Disable beaconing while we are reloading the beacon data,
1833 + * otherwise we might be sending out invalid data.
1834 + */
1835 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1836 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1837 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1838 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1839 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1840 +
1841 + /*
1842 + * Write entire beacon with descriptor to register.
1843 + */
1844 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1845 + rt2x00pci_register_multiwrite(rt2x00dev,
1846 + beacon_base,
1847 + skbdesc->desc, skbdesc->desc_len);
1848 + rt2x00pci_register_multiwrite(rt2x00dev,
1849 + beacon_base + skbdesc->desc_len,
1850 + entry->skb->data, entry->skb->len);
1851 +
1852 + /*
1853 + * Clean up beacon skb.
1854 + */
1855 + dev_kfree_skb_any(entry->skb);
1856 + entry->skb = NULL;
1857 +}
1858 +
1859 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1860 + const enum data_queue_qid queue_idx)
1861 +{
1862 + struct data_queue *queue;
1863 + unsigned int idx, qidx = 0;
1864 + u32 reg;
1865 +
1866 + if (queue_idx == QID_BEACON) {
1867 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1868 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1869 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1870 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1871 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1872 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1873 + }
1874 + return;
1875 + }
1876 +
1877 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
1878 + return;
1879 +
1880 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1881 + idx = queue->index[Q_INDEX];
1882 +
1883 + if (queue_idx == QID_MGMT)
1884 + qidx = 5;
1885 + else
1886 + qidx = queue_idx;
1887 +
1888 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
1889 +}
1890 +
1891 +/*
1892 + * RX control handlers
1893 + */
1894 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
1895 + struct rxdone_entry_desc *rxdesc)
1896 +{
1897 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1898 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1899 + __le32 *rxd = entry_priv->desc;
1900 + __le32 *rxwi = (__le32 *)entry->skb->data;
1901 + u32 rxd3;
1902 + u32 rxwi0;
1903 + u32 rxwi1;
1904 + u32 rxwi2;
1905 + u32 rxwi3;
1906 + u8 mcs;
1907 + u8 mode;
1908 +
1909 + rt2x00_desc_read(rxd, 3, &rxd3);
1910 + rt2x00_desc_read(rxwi, 0, &rxwi0);
1911 + rt2x00_desc_read(rxwi, 1, &rxwi1);
1912 + rt2x00_desc_read(rxwi, 2, &rxwi2);
1913 + rt2x00_desc_read(rxwi, 3, &rxwi3);
1914 +
1915 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
1916 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1917 +
1918 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1919 + /*
1920 + * FIXME: Set cipher on WEP64 when it has been decrypted,
1921 + * at the moment we cannot determine the real cipher type yet.
1922 + */
1923 + rxdesc->cipher =
1924 + rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED);
1925 + rxdesc->cipher_status =
1926 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
1927 + }
1928 +
1929 + if (rxdesc->cipher != CIPHER_NONE) {
1930 + /*
1931 + * Hardware has stripped IV/EIV data from 802.11 frame during
1932 + * decryption. It has provided the data seperately but rt2x00lib
1933 + * should decide if it should be reinserted.
1934 + */
1935 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1936 +
1937 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1938 + rxdesc->flags |= RX_FLAG_DECRYPTED;
1939 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1940 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1941 + }
1942 +
1943 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
1944 + rxdesc->dev_flags |= RXDONE_MY_BSS;
1945 +
1946 + /*
1947 + * Create the MCS value, when the mode is CCK, mask of 0x8 bit
1948 + * to remove the short preamble flag.
1949 + */
1950 + mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
1951 + mcs = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1952 +
1953 + if (mode == RATE_MODE_CCK)
1954 + mcs &= ~0x8;
1955 +
1956 + rxdesc->signal = (mode << 8) | mcs;
1957 +
1958 + rxdesc->rssi =
1959 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
1960 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
1961 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
1962 +
1963 + rxdesc->noise =
1964 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
1965 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
1966 +
1967 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
1968 +
1969 + /*
1970 + * Remove TXWI descriptor from start of buffer.
1971 + */
1972 + skb_pull(entry->skb, TXWI_DESC_SIZE);
1973 + skb_trim(entry->skb, rxdesc->size);
1974 +}
1975 +
1976 +/*
1977 + * Interrupt functions.
1978 + */
1979 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1980 +{
1981 + struct rt2x00_dev *rt2x00dev = dev_instance;
1982 + u32 reg;
1983 +
1984 + /* Read status and ACK all interrupts */
1985 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1986 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1987 +
1988 + if (!reg)
1989 + return IRQ_NONE;
1990 +
1991 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1992 + return IRQ_HANDLED;
1993 +
1994 + /*
1995 + * 1 - Rx ring done interrupt.
1996 + */
1997 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1998 + rt2x00pci_rxdone(rt2x00dev);
1999 +
2000 + /* TODO: TX DONE */
2001 +
2002 + return IRQ_HANDLED;
2003 +}
2004 +
2005 +/*
2006 + * Device probe functions.
2007 + */
2008 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2009 +{
2010 + struct eeprom_93cx6 eeprom;
2011 + u32 reg;
2012 + u16 word;
2013 + u8 *mac;
2014 + u8 default_lna_gain;
2015 +
2016 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2017 +
2018 + eeprom.data = rt2x00dev;
2019 + eeprom.register_read = rt2800pci_eepromregister_read;
2020 + eeprom.register_write = rt2800pci_eepromregister_write;
2021 + eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2022 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2023 + eeprom.reg_data_in = 0;
2024 + eeprom.reg_data_out = 0;
2025 + eeprom.reg_data_clock = 0;
2026 + eeprom.reg_chip_select = 0;
2027 +
2028 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2029 + EEPROM_SIZE / sizeof(u16));
2030 +
2031 + /*
2032 + * Start validation of the data that has been read.
2033 + */
2034 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2035 + if (!is_valid_ether_addr(mac)) {
2036 + DECLARE_MAC_BUF(macbuf);
2037 +
2038 + random_ether_addr(mac);
2039 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2040 + }
2041 +
2042 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2043 + if (word == 0xffff) {
2044 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2045 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2046 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2047 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2048 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2049 + }
2050 +
2051 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2052 + if (word != 0) {
2053 + /* NIC configuration must always be 0. */
2054 + word = 0;
2055 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2056 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2057 + }
2058 +
2059 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2060 + if ((word & 0x00ff) == 0x00ff) {
2061 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2062 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2063 + LED_MODE_TXRX_ACTIVITY);
2064 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2065 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2066 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2067 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2068 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2069 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2070 + }
2071 +
2072 + /*
2073 + * During the LNA validation we are going to use
2074 + * lna0 as correct value. Note that EEPROM_LNA
2075 + * is never validated.
2076 + */
2077 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2078 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2079 +
2080 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2081 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2082 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2083 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2084 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2085 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2086 +
2087 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2088 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2089 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2090 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2091 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2092 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2093 + default_lna_gain);
2094 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2095 +
2096 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2097 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2098 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2099 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2100 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2101 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2102 +
2103 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2104 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2105 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2106 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2107 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2108 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2109 + default_lna_gain);
2110 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2111 +
2112 + return 0;
2113 +}
2114 +
2115 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2116 +{
2117 + u32 reg;
2118 + u16 value;
2119 + u16 eeprom;
2120 + u16 device;
2121 +
2122 + /*
2123 + * Read EEPROM word for configuration.
2124 + */
2125 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2126 +
2127 + /*
2128 + * Identify RF chipset.
2129 + * To determine the RT chip we have to read the
2130 + * PCI header of the device.
2131 + */
2132 + pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2133 + PCI_CONFIG_HEADER_DEVICE, &device);
2134 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2135 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2136 + reg = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
2137 + rt2x00_set_chip(rt2x00dev, device, value, reg);
2138 +
2139 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2140 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2141 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2142 + !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2143 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2144 + return -ENODEV;
2145 + }
2146 +
2147 + /*
2148 + * Read frequency offset and RF programming sequence.
2149 + */
2150 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2151 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2152 +
2153 + /*
2154 + * Read external LNA informations.
2155 + */
2156 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2157 +
2158 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2159 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2160 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2161 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2162 +
2163 + /*
2164 + * Detect if this device has an hardware controlled radio.
2165 + */
2166 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2167 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2168 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2169 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2170 +
2171 + /*
2172 + * Store led settings, for correct led behaviour.
2173 + */
2174 +#ifdef CONFIG_RT2X00_LIB_LEDS
2175 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2176 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2177 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2178 +
2179 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2180 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2181 +
2182 + return 0;
2183 +}
2184 +
2185 +/*
2186 + * RF value list for rt2860
2187 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2188 + */
2189 +static const struct rf_channel rf_vals[] = {
2190 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2191 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2192 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2193 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2194 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2195 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2196 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2197 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2198 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2199 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2200 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2201 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2202 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2203 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2204 +
2205 + /* 802.11 UNI / HyperLan 2 */
2206 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2207 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2208 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2209 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2210 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2211 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2212 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2213 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2214 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2215 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2216 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2217 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2218 +
2219 + /* 802.11 HyperLan 2 */
2220 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2221 + { 102, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed793 },
2222 + { 104, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed1a3 },
2223 + { 108, 0x18402ecc, 0x184c0a32, 0x18178a55, 0x180ed193 },
2224 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2225 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2226 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2227 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2228 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2229 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2230 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2231 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2232 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2233 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2234 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2235 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2236 +
2237 + /* 802.11 UNII */
2238 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2239 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2240 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2241 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2242 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2243 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2244 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2245 +
2246 + /* 802.11 Japan */
2247 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2248 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2249 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2250 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2251 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2252 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2253 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2254 +};
2255 +
2256 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2257 +{
2258 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2259 + struct channel_info *info;
2260 + char *tx_power1;
2261 + char *tx_power2;
2262 + unsigned int i;
2263 +
2264 + /*
2265 + * Initialize all hw fields.
2266 + */
2267 + rt2x00dev->hw->flags =
2268 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2269 + IEEE80211_HW_SIGNAL_DBM;
2270 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2271 +
2272 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2273 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2274 + rt2x00_eeprom_addr(rt2x00dev,
2275 + EEPROM_MAC_ADDR_0));
2276 +
2277 + /*
2278 + * Initialize hw_mode information.
2279 + */
2280 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2281 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2282 +
2283 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2284 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2285 + spec->num_channels = 14;
2286 + spec->channels = rf_vals;
2287 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2288 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2289 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2290 + spec->num_channels = ARRAY_SIZE(rf_vals);
2291 + spec->channels = rf_vals;
2292 + }
2293 +
2294 + /*
2295 + * Create channel information array
2296 + */
2297 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2298 + if (!info)
2299 + return -ENOMEM;
2300 +
2301 + spec->channels_info = info;
2302 +
2303 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2304 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2305 +
2306 + for (i = 0; i < 14; i++) {
2307 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2308 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2309 + }
2310 +
2311 + if (spec->num_channels > 14) {
2312 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2313 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2314 +
2315 + for (i = 14; i < spec->num_channels; i++) {
2316 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2317 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2318 + }
2319 + }
2320 +
2321 + return 0;
2322 +}
2323 +
2324 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2325 +{
2326 + int retval;
2327 +
2328 + /*
2329 + * Allocate eeprom data.
2330 + */
2331 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2332 + if (retval)
2333 + return retval;
2334 +
2335 + retval = rt2800pci_init_eeprom(rt2x00dev);
2336 + if (retval)
2337 + return retval;
2338 +
2339 + /*
2340 + * Initialize hw specifications.
2341 + */
2342 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2343 + if (retval)
2344 + return retval;
2345 +
2346 + /*
2347 + * This device requires firmware.
2348 + */
2349 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2350 + if (!modparam_nohwcrypt)
2351 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2352 +
2353 + /*
2354 + * Set the rssi offset.
2355 + */
2356 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2357 +
2358 + return 0;
2359 +}
2360 +
2361 +/*
2362 + * IEEE80211 stack callback functions.
2363 + */
2364 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2365 +{
2366 + struct rt2x00_dev *rt2x00dev = hw->priv;
2367 + u32 reg;
2368 +
2369 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2370 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2371 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2372 +
2373 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2374 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2375 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2376 +
2377 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2378 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2379 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2380 +
2381 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2382 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
2383 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2384 +
2385 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2386 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
2387 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2388 +
2389 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2390 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
2391 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2392 +
2393 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2394 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
2395 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2396 +
2397 + return 0;
2398 +}
2399 +
2400 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2401 + const struct ieee80211_tx_queue_params *params)
2402 +{
2403 + struct rt2x00_dev *rt2x00dev = hw->priv;
2404 + struct data_queue *queue;
2405 + struct rt2x00_field32 field;
2406 + int retval;
2407 + u32 reg;
2408 + u32 offset;
2409 +
2410 + /*
2411 + * First pass the configuration through rt2x00lib, that will
2412 + * update the queue settings and validate the input. After that
2413 + * we are free to update the registers based on the value
2414 + * in the queue parameter.
2415 + */
2416 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2417 + if (retval)
2418 + return retval;
2419 +
2420 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2421 +
2422 + /* Update WMM TXOP register */
2423 + if (queue_idx < 2) {
2424 + field.bit_offset = queue_idx * 16;
2425 + field.bit_mask = 0xffff << field.bit_offset;
2426 +
2427 + rt2x00pci_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
2428 + rt2x00_set_field32(&reg, field, queue->txop);
2429 + rt2x00pci_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
2430 + } else if (queue_idx < 4) {
2431 + field.bit_offset = (queue_idx - 2) * 16;
2432 + field.bit_mask = 0xffff << field.bit_offset;
2433 +
2434 + rt2x00pci_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
2435 + rt2x00_set_field32(&reg, field, queue->txop);
2436 + rt2x00pci_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
2437 + }
2438 +
2439 + /* Update WMM registers */
2440 + field.bit_offset = queue_idx * 4;
2441 + field.bit_mask = 0xf << field.bit_offset;
2442 +
2443 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2444 + rt2x00_set_field32(&reg, field, queue->aifs);
2445 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2446 +
2447 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2448 + rt2x00_set_field32(&reg, field, queue->cw_min);
2449 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2450 +
2451 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2452 + rt2x00_set_field32(&reg, field, queue->cw_max);
2453 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2454 +
2455 + /* Update EDCA registers */
2456 + if (queue_idx < 4) {
2457 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2458 +
2459 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2460 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2461 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2462 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2463 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2464 + }
2465 +
2466 + return 0;
2467 +}
2468 +
2469 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2470 +{
2471 + struct rt2x00_dev *rt2x00dev = hw->priv;
2472 + u64 tsf;
2473 + u32 reg;
2474 +
2475 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2476 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2477 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2478 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2479 +
2480 + return tsf;
2481 +}
2482 +
2483 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2484 + .tx = rt2x00mac_tx,
2485 + .start = rt2x00mac_start,
2486 + .stop = rt2x00mac_stop,
2487 + .add_interface = rt2x00mac_add_interface,
2488 + .remove_interface = rt2x00mac_remove_interface,
2489 + .config = rt2x00mac_config,
2490 + .config_interface = rt2x00mac_config_interface,
2491 + .configure_filter = rt2x00mac_configure_filter,
2492 + .set_key = rt2x00mac_set_key,
2493 + .get_stats = rt2x00mac_get_stats,
2494 + .set_rts_threshold = rt2800pci_set_rts_threshold,
2495 + .bss_info_changed = rt2x00mac_bss_info_changed,
2496 + .conf_tx = rt2800pci_conf_tx,
2497 + .get_tx_stats = rt2x00mac_get_tx_stats,
2498 + .get_tsf = rt2800pci_get_tsf,
2499 +};
2500 +
2501 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2502 + .irq_handler = rt2800pci_interrupt,
2503 + .probe_hw = rt2800pci_probe_hw,
2504 + .get_firmware_name = rt2800pci_get_firmware_name,
2505 + .get_firmware_crc = rt2800pci_get_firmware_crc,
2506 + .load_firmware = rt2800pci_load_firmware,
2507 + .initialize = rt2x00pci_initialize,
2508 + .uninitialize = rt2x00pci_uninitialize,
2509 + .get_entry_state = rt2800pci_get_entry_state,
2510 + .clear_entry = rt2800pci_clear_entry,
2511 + .set_device_state = rt2800pci_set_device_state,
2512 + .rfkill_poll = rt2800pci_rfkill_poll,
2513 + .link_stats = rt2800pci_link_stats,
2514 + .reset_tuner = rt2800pci_reset_tuner,
2515 + .link_tuner = rt2800pci_link_tuner,
2516 + .write_tx_desc = rt2800pci_write_tx_desc,
2517 + .write_tx_data = rt2x00pci_write_tx_data,
2518 + .write_beacon = rt2800pci_write_beacon,
2519 + .kick_tx_queue = rt2800pci_kick_tx_queue,
2520 + .fill_rxdone = rt2800pci_fill_rxdone,
2521 + .config_shared_key = rt2800pci_config_shared_key,
2522 + .config_pairwise_key = rt2800pci_config_pairwise_key,
2523 + .config_filter = rt2800pci_config_filter,
2524 + .config_intf = rt2800pci_config_intf,
2525 + .config_erp = rt2800pci_config_erp,
2526 + .config_ant = rt2800pci_config_ant,
2527 + .config = rt2800pci_config,
2528 +};
2529 +
2530 +static const struct data_queue_desc rt2800pci_queue_rx = {
2531 + .entry_num = RX_ENTRIES,
2532 + .data_size = DATA_FRAME_SIZE,
2533 + .desc_size = RXD_DESC_SIZE,
2534 + .priv_size = sizeof(struct queue_entry_priv_pci),
2535 +};
2536 +
2537 +static const struct data_queue_desc rt2800pci_queue_tx = {
2538 + .entry_num = TX_ENTRIES,
2539 + .data_size = DATA_FRAME_SIZE,
2540 + .desc_size = TXD_DESC_SIZE,
2541 + .priv_size = sizeof(struct queue_entry_priv_pci),
2542 +};
2543 +
2544 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2545 + .entry_num = 8 * BEACON_ENTRIES,
2546 + .data_size = 0, /* No DMA required for beacons */
2547 + .desc_size = TXWI_DESC_SIZE,
2548 + .priv_size = sizeof(struct queue_entry_priv_pci),
2549 +};
2550 +
2551 +static const struct rt2x00_ops rt2800pci_ops = {
2552 + .name = KBUILD_MODNAME,
2553 + .max_sta_intf = 1,
2554 + .max_ap_intf = 8,
2555 + .eeprom_size = EEPROM_SIZE,
2556 + .rf_size = RF_SIZE,
2557 + .tx_queues = NUM_TX_QUEUES,
2558 + .rx = &rt2800pci_queue_rx,
2559 + .tx = &rt2800pci_queue_tx,
2560 + .bcn = &rt2800pci_queue_bcn,
2561 + .lib = &rt2800pci_rt2x00_ops,
2562 + .hw = &rt2800pci_mac80211_ops,
2563 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2564 + .debugfs = &rt2800pci_rt2x00debug,
2565 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2566 +};
2567 +
2568 +/*
2569 + * RT2800pci module information.
2570 + */
2571 +static struct pci_device_id rt2800pci_device_table[] = {
2572 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2573 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2574 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2575 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2576 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2577 + { 0, }
2578 +};
2579 +
2580 +MODULE_AUTHOR(DRV_PROJECT);
2581 +MODULE_VERSION(DRV_VERSION);
2582 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2583 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2584 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2585 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2586 +MODULE_LICENSE("GPL");
2587 +
2588 +static struct pci_driver rt2800pci_driver = {
2589 + .name = KBUILD_MODNAME,
2590 + .id_table = rt2800pci_device_table,
2591 + .probe = rt2x00pci_probe,
2592 + .remove = __devexit_p(rt2x00pci_remove),
2593 + .suspend = rt2x00pci_suspend,
2594 + .resume = rt2x00pci_resume,
2595 +};
2596 +
2597 +static int __init rt2800pci_init(void)
2598 +{
2599 + return pci_register_driver(&rt2800pci_driver);
2600 +}
2601 +
2602 +static void __exit rt2800pci_exit(void)
2603 +{
2604 + pci_unregister_driver(&rt2800pci_driver);
2605 +}
2606 +
2607 +module_init(rt2800pci_init);
2608 +module_exit(rt2800pci_exit);
2609 diff --git a/drivers/net/wireless/rt2x00/rt2800pci.h b/drivers/net/wireless/rt2x00/rt2800pci.h
2610 new file mode 100644
2611 index 0000000..66593ed
2612 --- /dev/null
2613 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2614 @@ -0,0 +1,1871 @@
2615 +/*
2616 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
2617 + <http://rt2x00.serialmonkey.com>
2618 +
2619 + This program is free software; you can redistribute it and/or modify
2620 + it under the terms of the GNU General Public License as published by
2621 + the Free Software Foundation; either version 2 of the License, or
2622 + (at your option) any later version.
2623 +
2624 + This program is distributed in the hope that it will be useful,
2625 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2626 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2627 + GNU General Public License for more details.
2628 +
2629 + You should have received a copy of the GNU General Public License
2630 + along with this program; if not, write to the
2631 + Free Software Foundation, Inc.,
2632 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2633 + */
2634 +
2635 +/*
2636 + Module: rt2800pci
2637 + Abstract: Data structures and registers for the rt2800pci module.
2638 + Supported chipsets: RT2800E & RT2800ED.
2639 + */
2640 +
2641 +#ifndef RT2800PCI_H
2642 +#define RT2800PCI_H
2643 +
2644 +/*
2645 + * RF chip defines.
2646 + *
2647 + * RF2820 2.4G 2T3R
2648 + * RF2850 2.4G/5G 2T3R
2649 + * RF2720 2.4G 1T2R
2650 + * RF2750 2.4G/5G 1T2R
2651 + */
2652 +#define RF2820 0x0001
2653 +#define RF2850 0x0002
2654 +#define RF2720 0x0003
2655 +#define RF2750 0x0004
2656 +
2657 +/*
2658 + * RT2860 version
2659 + */
2660 +#define RT2860_VERSION_C 0x0100
2661 +#define RT2860_VERSION_D 0x0101
2662 +#define RT2860_VERSION_E 0x0200
2663 +
2664 +/*
2665 + * Signal information.
2666 + * Defaul offset is required for RSSI <-> dBm conversion.
2667 + */
2668 +#define MAX_SIGNAL 0 /* FIXME */
2669 +#define MAX_RX_SSI 0 /* FIXME */
2670 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
2671 +
2672 +/*
2673 + * Register layout information.
2674 + */
2675 +#define CSR_REG_BASE 0x1000
2676 +#define CSR_REG_SIZE 0x0800
2677 +#define EEPROM_BASE 0x0000
2678 +#define EEPROM_SIZE 0x0110
2679 +#define BBP_BASE 0x0000
2680 +#define BBP_SIZE 0x0080
2681 +#define RF_BASE 0x0000
2682 +#define RF_SIZE 0x0014
2683 +
2684 +/*
2685 + * Number of TX queues.
2686 + */
2687 +#define NUM_TX_QUEUES 4
2688 +
2689 +/*
2690 + * PCI registers.
2691 + */
2692 +
2693 +/*
2694 + * PCI Configuration Header
2695 + */
2696 +#define PCI_CONFIG_HEADER_VENDOR 0x0000
2697 +#define PCI_CONFIG_HEADER_DEVICE 0x0002
2698 +
2699 +/*
2700 + * E2PROM_CSR: EEPROM control register.
2701 + * RELOAD: Write 1 to reload eeprom content.
2702 + * TYPE_93C46: 1: 93c46, 0:93c66.
2703 + * LOAD_STATUS: 1:loading, 0:done.
2704 + */
2705 +#define E2PROM_CSR 0x0004
2706 +#define E2PROM_CSR_RELOAD FIELD32(0x00000001)
2707 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
2708 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
2709 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
2710 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
2711 +#define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
2712 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
2713 +
2714 +/*
2715 + * HOST-MCU shared memory
2716 + */
2717 +#define HOST_CMD_CSR 0x0404
2718 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
2719 +
2720 +/*
2721 + * INT_SOURCE_CSR: Interrupt source register.
2722 + * Write one to clear corresponding bit.
2723 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2724 + */
2725 +#define INT_SOURCE_CSR 0x0200
2726 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
2727 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
2728 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
2729 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2730 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2731 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2732 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2733 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2734 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2735 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
2736 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
2737 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
2738 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
2739 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2740 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2741 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
2742 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
2743 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
2744 +
2745 +/*
2746 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2747 + */
2748 +#define INT_MASK_CSR 0x0204
2749 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
2750 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
2751 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
2752 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2753 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2754 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2755 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2756 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2757 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2758 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
2759 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x40000000)
2760 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x80000000)
2761 +
2762 +/*
2763 + * WPDMA_GLO_CFG
2764 + */
2765 +#define WPDMA_GLO_CFG 0x0208
2766 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
2767 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
2768 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
2769 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
2770 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
2771 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
2772 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
2773 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
2774 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
2775 +
2776 +/*
2777 + * WPDMA_RST_IDX
2778 + */
2779 +#define WPDMA_RST_IDX 0x020c
2780 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
2781 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
2782 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
2783 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
2784 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
2785 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
2786 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
2787 +
2788 +/*
2789 + * DELAY_INT_CFG
2790 + */
2791 +#define DELAY_INT_CFG 0x0210
2792 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
2793 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
2794 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
2795 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
2796 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
2797 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
2798 +
2799 +/*
2800 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2801 + * AIFSN0: AC_BE
2802 + * AIFSN1: AC_BK
2803 + * AIFSN1: AC_VI
2804 + * AIFSN1: AC_VO
2805 + */
2806 +#define WMM_AIFSN_CFG 0x0214
2807 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
2808 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
2809 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
2810 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
2811 +
2812 +/*
2813 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
2814 + * CWMIN0: AC_BE
2815 + * CWMIN1: AC_BK
2816 + * CWMIN1: AC_VI
2817 + * CWMIN1: AC_VO
2818 + */
2819 +#define WMM_CWMIN_CFG 0x0218
2820 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
2821 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
2822 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
2823 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
2824 +
2825 +/*
2826 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
2827 + * CWMAX0: AC_BE
2828 + * CWMAX1: AC_BK
2829 + * CWMAX1: AC_VI
2830 + * CWMAX1: AC_VO
2831 + */
2832 +#define WMM_CWMAX_CFG 0x021c
2833 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
2834 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
2835 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
2836 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
2837 +
2838 +/*
2839 + * AC_TXOP0: AC_BK/AC_BE TXOP register
2840 + * AC0TXOP: AC_BK in unit of 32us
2841 + * AC1TXOP: AC_BE in unit of 32us
2842 + */
2843 +#define WMM_TXOP0_CFG 0x0220
2844 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
2845 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
2846 +
2847 +/*
2848 + * AC_TXOP1: AC_VO/AC_VI TXOP register
2849 + * AC2TXOP: AC_VI in unit of 32us
2850 + * AC3TXOP: AC_VO in unit of 32us
2851 + */
2852 +#define WMM_TXOP1_CFG 0x0224
2853 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
2854 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
2855 +
2856 +/*
2857 + * RINGREG_DIFF
2858 + */
2859 +#define RINGREG_DIFF 0x0010
2860 +
2861 +/*
2862 + * GPIO_CTRL_CFG:
2863 + */
2864 +#define GPIO_CTRL_CFG 0x0228
2865 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
2866 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
2867 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
2868 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
2869 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
2870 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
2871 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
2872 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
2873 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
2874 +
2875 +/*
2876 + * MCU_CMD_CFG
2877 + */
2878 +#define MCU_CMD_CFG 0x022c
2879 +
2880 +/*
2881 + * AC_BK register offsets
2882 + */
2883 +#define TX_BASE_PTR0 0x0230
2884 +#define TX_MAX_CNT0 0x0234
2885 +#define TX_CTX_IDX0 0x0238
2886 +#define TX_DTX_IDX0 0x023c
2887 +
2888 +/*
2889 + * AC_BE register offsets
2890 + */
2891 +#define TX_BASE_PTR1 0x0240
2892 +#define TX_MAX_CNT1 0x0244
2893 +#define TX_CTX_IDX1 0x0248
2894 +#define TX_DTX_IDX1 0x024c
2895 +
2896 +/*
2897 + * AC_VI register offsets
2898 + */
2899 +#define TX_BASE_PTR2 0x0250
2900 +#define TX_MAX_CNT2 0x0254
2901 +#define TX_CTX_IDX2 0x0258
2902 +#define TX_DTX_IDX2 0x025c
2903 +
2904 +/*
2905 + * AC_VO register offsets
2906 + */
2907 +#define TX_BASE_PTR3 0x0260
2908 +#define TX_MAX_CNT3 0x0264
2909 +#define TX_CTX_IDX3 0x0268
2910 +#define TX_DTX_IDX3 0x026c
2911 +
2912 +/*
2913 + * HCCA register offsets
2914 + */
2915 +#define TX_BASE_PTR4 0x0270
2916 +#define TX_MAX_CNT4 0x0274
2917 +#define TX_CTX_IDX4 0x0278
2918 +#define TX_DTX_IDX4 0x027c
2919 +
2920 +/*
2921 + * MGMT register offsets
2922 + */
2923 +#define TX_BASE_PTR5 0x0280
2924 +#define TX_MAX_CNT5 0x0284
2925 +#define TX_CTX_IDX5 0x0288
2926 +#define TX_DTX_IDX5 0x028c
2927 +
2928 +/*
2929 + * Queue register offset macros
2930 + */
2931 +#define TX_QUEUE_REG_OFFSET 0x10
2932 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
2933 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
2934 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
2935 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
2936 +
2937 +/*
2938 + * RX register offsets
2939 + */
2940 +#define RX_BASE_PTR 0x0290
2941 +#define RX_MAX_CNT 0x0294
2942 +#define RX_CRX_IDX 0x0298
2943 +#define RX_DRX_IDX 0x029c
2944 +
2945 +/*
2946 + * PBF_SYS_CTRL
2947 + * HOST_RAM_WRITE: enable Host program ram write selection
2948 + */
2949 +#define PBF_SYS_CTRL 0x0400
2950 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
2951 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
2952 +
2953 +/*
2954 + * PBF registers
2955 + * Most are for debug. Driver doesn't touch PBF register.
2956 + */
2957 +#define PBF_CFG 0x0408
2958 +#define PBF_MAX_PCNT 0x040c
2959 +#define PBF_CTRL 0x0410
2960 +#define PBF_INT_STA 0x0414
2961 +#define PBF_INT_ENA 0x0418
2962 +
2963 +/*
2964 + * BCN_OFFSET0:
2965 + */
2966 +#define BCN_OFFSET0 0x042c
2967 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
2968 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
2969 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
2970 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
2971 +
2972 +/*
2973 + * BCN_OFFSET1:
2974 + */
2975 +#define BCN_OFFSET1 0x0430
2976 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
2977 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
2978 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
2979 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
2980 +
2981 +/*
2982 + * PBF registers
2983 + * Most are for debug. Driver doesn't touch PBF register.
2984 + */
2985 +#define TXRXQ_PCNT 0x0438
2986 +#define PBF_DBG 0x043c
2987 +
2988 +/*
2989 + * MAC Control/Status Registers(CSR).
2990 + * Some values are set in TU, whereas 1 TU == 1024 us.
2991 + */
2992 +
2993 +/*
2994 + * MAC_CSR0: ASIC revision number.
2995 + * ASIC_REV: 0
2996 + * ASIC_VER: 2860
2997 + */
2998 +#define MAC_CSR0 0x1000
2999 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3000 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3001 +
3002 +/*
3003 + * MAC_SYS_CTRL:
3004 + */
3005 +#define MAC_SYS_CTRL 0x1004
3006 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3007 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3008 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3009 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3010 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3011 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3012 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3013 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3014 +
3015 +/*
3016 + * MAC_ADDR_DW0: STA MAC register 0
3017 + */
3018 +#define MAC_ADDR_DW0 0x1008
3019 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3020 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3021 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3022 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3023 +
3024 +/*
3025 + * MAC_ADDR_DW1: STA MAC register 1
3026 + * UNICAST_TO_ME_MASK:
3027 + * Used to mask off bits from byte 5 of the MAC address
3028 + * to determine the UNICAST_TO_ME bit for RX frames.
3029 + * The full mask is complemented by BSS_ID_MASK:
3030 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3031 + */
3032 +#define MAC_ADDR_DW1 0x100c
3033 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3034 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3035 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3036 +
3037 +/*
3038 + * MAC_BSSID_DW0: BSSID register 0
3039 + */
3040 +#define MAC_BSSID_DW0 0x1010
3041 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3042 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3043 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3044 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3045 +
3046 +/*
3047 + * MAC_BSSID_DW1: BSSID register 1
3048 + * BSS_ID_MASK:
3049 + * 0: 1-BSSID mode (BSS index = 0)
3050 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3051 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3052 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3053 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3054 + * BSSID. This will make sure that those bits will be ignored
3055 + * when determining the MY_BSS of RX frames.
3056 + */
3057 +#define MAC_BSSID_DW1 0x1014
3058 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3059 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3060 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3061 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3062 +
3063 +/*
3064 + * MAX_LEN_CFG: Maximum frame length register.
3065 + * MAX_MPDU: rt2860b max 16k bytes
3066 + * MAX_PSDU: Maximum PSDU length
3067 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3068 + */
3069 +#define MAX_LEN_CFG 0x1018
3070 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3071 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3072 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3073 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3074 +
3075 +/*
3076 + * BBP_CSR_CFG: BBP serial control register
3077 + * VALUE: Register value to program into BBP
3078 + * REG_NUM: Selected BBP register
3079 + * READ_CONTROL: 0 write BBP, 1 read BBP
3080 + * BUSY: ASIC is busy executing BBP commands
3081 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3082 + * BBP_RW_MODE: 0 serial, 1 paralell
3083 + */
3084 +#define BBP_CSR_CFG 0x101c
3085 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3086 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3087 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3088 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3089 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3090 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3091 +
3092 +/*
3093 + * RF_CSR_CFG0: RF control register
3094 + * REGID_AND_VALUE: Register value to program into RF
3095 + * BITWIDTH: Selected RF register
3096 + * STANDBYMODE: 0 high when standby, 1 low when standby
3097 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3098 + * BUSY: ASIC is busy executing RF commands
3099 + */
3100 +#define RF_CSR_CFG0 0x1020
3101 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3102 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3103 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3104 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3105 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3106 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3107 +
3108 +/*
3109 + * RF_CSR_CFG1: RF control register
3110 + * REGID_AND_VALUE: Register value to program into RF
3111 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3112 + * 0: 3 system clock cycle (37.5usec)
3113 + * 1: 5 system clock cycle (62.5usec)
3114 + */
3115 +#define RF_CSR_CFG1 0x1024
3116 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3117 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3118 +
3119 +/*
3120 + * RF_CSR_CFG2: RF control register
3121 + * VALUE: Register value to program into RF
3122 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3123 + * 0: 3 system clock cycle (37.5usec)
3124 + * 1: 5 system clock cycle (62.5usec)
3125 + */
3126 +#define RF_CSR_CFG2 0x1028
3127 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3128 +
3129 +/*
3130 + * LED_CFG: LED control
3131 + * color LED's:
3132 + * 0: off
3133 + * 1: blinking upon TX2
3134 + * 2: periodic slow blinking
3135 + * 3: always on
3136 + * LED polarity:
3137 + * 0: active low
3138 + * 1: active high
3139 + */
3140 +#define LED_CFG 0x102c
3141 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3142 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3143 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3144 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3145 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3146 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3147 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3148 +
3149 +/*
3150 + * XIFS_TIME_CFG: MAC timing
3151 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3152 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3153 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3154 + * when MAC doesn't reference BBP signal BBRXEND
3155 + * EIFS: unit 1us
3156 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3157 + *
3158 + */
3159 +#define XIFS_TIME_CFG 0x1100
3160 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3161 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3162 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3163 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3164 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3165 +
3166 +/*
3167 + * BKOFF_SLOT_CFG:
3168 + */
3169 +#define BKOFF_SLOT_CFG 0x1104
3170 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3171 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3172 +
3173 +/*
3174 + * NAV_TIME_CFG:
3175 + */
3176 +#define NAV_TIME_CFG 0x1108
3177 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3178 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3179 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3180 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3181 +
3182 +/*
3183 + * CH_TIME_CFG: count as channel busy
3184 + */
3185 +#define CH_TIME_CFG 0x110c
3186 +
3187 +/*
3188 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3189 + */
3190 +#define PBF_LIFE_TIMER 0x1110
3191 +
3192 +/*
3193 + * BCN_TIME_CFG:
3194 + * BEACON_INTERVAL: in unit of 1/16 TU
3195 + * TSF_TICKING: Enable TSF auto counting
3196 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3197 + * BEACON_GEN: Enable beacon generator
3198 + */
3199 +#define BCN_TIME_CFG 0x1114
3200 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3201 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3202 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3203 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3204 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3205 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3206 +
3207 +/*
3208 + * TBTT_SYNC_CFG:
3209 + */
3210 +#define TBTT_SYNC_CFG 0x1118
3211 +
3212 +/*
3213 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3214 + */
3215 +#define TSF_TIMER_DW0 0x111c
3216 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3217 +
3218 +/*
3219 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3220 + */
3221 +#define TSF_TIMER_DW1 0x1120
3222 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3223 +
3224 +/*
3225 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3226 + */
3227 +#define TBTT_TIMER 0x1124
3228 +
3229 +/*
3230 + * INT_TIMER_CFG:
3231 + */
3232 +#define INT_TIMER_CFG 0x1128
3233 +
3234 +/*
3235 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3236 + */
3237 +#define INT_TIMER_EN 0x112c
3238 +
3239 +/*
3240 + * CH_IDLE_STA: channel idle time
3241 + */
3242 +#define CH_IDLE_STA 0x1130
3243 +
3244 +/*
3245 + * CH_BUSY_STA: channel busy time
3246 + */
3247 +#define CH_BUSY_STA 0x1134
3248 +
3249 +/*
3250 + * MAC_STATUS_CFG:
3251 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3252 + * if 1 or higher one of the 2 registers is busy.
3253 + */
3254 +#define MAC_STATUS_CFG 0x1200
3255 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3256 +
3257 +/*
3258 + * PWR_PIN_CFG:
3259 + */
3260 +#define PWR_PIN_CFG 0x1204
3261 +
3262 +/*
3263 + * AUTOWAKEUP_CFG: Manual power control / status register
3264 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3265 + * AUTOWAKE: 0:sleep, 1:awake
3266 + */
3267 +#define AUTOWAKEUP_CFG 0x1208
3268 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3269 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3270 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3271 +
3272 +/*
3273 + * EDCA_AC0_CFG:
3274 + */
3275 +#define EDCA_AC0_CFG 0x1300
3276 +#define EDCA_AC0_CFG_AC_TX_OP FIELD32(0x000000ff)
3277 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3278 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3279 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3280 +
3281 +/*
3282 + * EDCA_AC1_CFG:
3283 + */
3284 +#define EDCA_AC1_CFG 0x1304
3285 +#define EDCA_AC1_CFG_AC_TX_OP FIELD32(0x000000ff)
3286 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3287 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3288 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3289 +
3290 +/*
3291 + * EDCA_AC2_CFG:
3292 + */
3293 +#define EDCA_AC2_CFG 0x1308
3294 +#define EDCA_AC2_CFG_AC_TX_OP FIELD32(0x000000ff)
3295 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3296 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3297 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3298 +
3299 +/*
3300 + * EDCA_AC3_CFG:
3301 + */
3302 +#define EDCA_AC3_CFG 0x130c
3303 +#define EDCA_AC3_CFG_AC_TX_OP FIELD32(0x000000ff)
3304 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3305 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3306 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3307 +
3308 +/*
3309 + * EDCA_TID_AC_MAP:
3310 + */
3311 +#define EDCA_TID_AC_MAP 0x1310
3312 +
3313 +/*
3314 + * TX_PWR_CFG_0:
3315 + */
3316 +#define TX_PWR_CFG_0 0x1314
3317 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3318 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3319 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3320 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3321 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3322 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3323 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3324 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3325 +
3326 +/*
3327 + * TX_PWR_CFG_1:
3328 + */
3329 +#define TX_PWR_CFG_1 0x1318
3330 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3331 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3332 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3333 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3334 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3335 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3336 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3337 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3338 +
3339 +/*
3340 + * TX_PWR_CFG_2:
3341 + */
3342 +#define TX_PWR_CFG_2 0x131c
3343 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3344 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3345 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3346 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3347 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3348 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3349 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3350 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3351 +
3352 +/*
3353 + * TX_PWR_CFG_3:
3354 + */
3355 +#define TX_PWR_CFG_3 0x1320
3356 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3357 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3358 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3359 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3360 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3361 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3362 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3363 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3364 +
3365 +/*
3366 + * TX_PWR_CFG_4:
3367 + */
3368 +#define TX_PWR_CFG_4 0x1324
3369 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3370 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3371 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3372 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3373 +
3374 +/*
3375 + * TX_PIN_CFG:
3376 + */
3377 +#define TX_PIN_CFG 0x1328
3378 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3379 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3380 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3381 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3382 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3383 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3384 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3385 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3386 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3387 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3388 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3389 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3390 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3391 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3392 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3393 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3394 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3395 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3396 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3397 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3398 +
3399 +/*
3400 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3401 + */
3402 +#define TX_BAND_CFG 0x132c
3403 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3404 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3405 +
3406 +/*
3407 + * TX_SW_CFG0:
3408 + */
3409 +#define TX_SW_CFG0 0x1330
3410 +
3411 +/*
3412 + * TX_SW_CFG1:
3413 + */
3414 +#define TX_SW_CFG1 0x1334
3415 +
3416 +/*
3417 + * TX_SW_CFG2:
3418 + */
3419 +#define TX_SW_CFG2 0x1338
3420 +
3421 +/*
3422 + * TXOP_THRES_CFG:
3423 + */
3424 +#define TXOP_THRES_CFG 0x133c
3425 +
3426 +/*
3427 + * TXOP_CTRL_CFG:
3428 + */
3429 +#define TXOP_CTRL_CFG 0x1340
3430 +
3431 +/*
3432 + * TX_RTS_CFG:
3433 + * RTS_THRES: unit:byte
3434 + * RTS_FBK_EN: enable rts rate fallback
3435 + */
3436 +#define TX_RTS_CFG 0x1344
3437 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3438 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3439 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3440 +
3441 +/*
3442 + * TX_TIMEOUT_CFG:
3443 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3444 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3445 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3446 + * it is recommended that:
3447 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3448 + */
3449 +#define TX_TIMEOUT_CFG 0x1348
3450 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3451 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3452 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3453 +
3454 +/*
3455 + * TX_RTY_CFG:
3456 + * SHORT_RTY_LIMIT: short retry limit
3457 + * LONG_RTY_LIMIT: long retry limit
3458 + * LONG_RTY_THRE: Long retry threshoold
3459 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3460 + * 0:expired by retry limit, 1: expired by mpdu life timer
3461 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3462 + * 0:expired by retry limit, 1: expired by mpdu life timer
3463 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3464 + */
3465 +#define TX_RTY_CFG 0x134c
3466 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3467 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3468 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3469 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3470 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3471 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3472 +
3473 +/*
3474 + * TX_LINK_CFG:
3475 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us