90d41bd8d7732ec9b9479a4025ff85bde07b430f
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 310-rt2800_experimental.patch
1 automatically generated from wireless-testing..rt2x00/experimental
2 do not edit
3
4 --- a/drivers/net/wireless/rt2x00/Makefile
5 +++ b/drivers/net/wireless/rt2x00/Makefile
6 @@ -14,5 +14,7 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
7 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
8 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
9 obj-$(CONFIG_RT61PCI) += rt61pci.o
10 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
11 obj-$(CONFIG_RT2500USB) += rt2500usb.o
12 obj-$(CONFIG_RT73USB) += rt73usb.o
13 +obj-$(CONFIG_RT2800USB) += rt2800usb.o
14 --- a/drivers/net/wireless/rt2x00/rt2500usb.c
15 +++ b/drivers/net/wireless/rt2x00/rt2500usb.c
16 @@ -36,6 +36,13 @@
17 #include "rt2500usb.h"
18
19 /*
20 + * Allow hardware encryption to be disabled.
21 + */
22 +static int modparam_nohwcrypt = 0;
23 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
24 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
25 +
26 +/*
27 * Register access.
28 * All access to the CSR registers will go through the methods
29 * rt2500usb_register_read and rt2500usb_register_write.
30 @@ -343,6 +350,85 @@ static void rt2500usb_init_led(struct rt
31 /*
32 * Configuration handlers.
33 */
34 +
35 +/*
36 + * rt2500usb does not differentiate between shared and pairwise
37 + * keys, so we should use the same function for both key types.
38 + */
39 +static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev,
40 + struct rt2x00lib_crypto *crypto,
41 + struct ieee80211_key_conf *key)
42 +{
43 + int timeout;
44 + u32 mask;
45 + u16 reg;
46 +
47 + /* Support up to 4 keys */
48 + if (key->hw_key_idx >= 4)
49 + return -ENOSPC;
50 +
51 + if (crypto->cmd == SET_KEY) {
52 + /*
53 + * Pairwise key will always be entry 0, but this
54 + * could collide with a shared key on the same
55 + * position...
56 + */
57 + mask = TXRX_CSR0_KEY_ID.bit_mask;
58 +
59 + rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
60 +
61 + if ((reg & mask) && (reg & mask) == mask)
62 + return -ENOSPC;
63 +
64 + reg = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
65 +
66 + key->hw_key_idx += reg ? ffz(reg) : 0;
67 +
68 + /*
69 + * The encryption key doesn't fit within the CSR cache,
70 + * this means we should allocate it seperately and use
71 + * rt2x00usb_vendor_request() to send the key to the hardware.
72 + */
73 + reg = KEY_ENTRY(key->hw_key_idx);
74 + timeout = REGISTER_TIMEOUT32(sizeof(crypto->key));
75 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
76 + USB_VENDOR_REQUEST_OUT, reg,
77 + crypto->key,
78 + sizeof(crypto->key),
79 + timeout);
80 +
81 + /*
82 + * The driver does not support the IV/EIV generation
83 + * in hardware. However it doesn't support the IV/EIV
84 + * inside the ieee80211 frame either, but requires it
85 + * to be provided seperately for the descriptor.
86 + * rt2x00lib will cut the IV/EIV data out of all frames
87 + * given to us by mac80211, but we must tell mac80211
88 + * to generate the IV/EIV data.
89 + */
90 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
91 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
92 + }
93 +
94 + /*
95 + * TXRX_CSR0_KEY_ID contains only single-bit fields to indicate
96 + * a particular key is valid.
97 + */
98 + rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
99 + rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, crypto->cipher);
100 + rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
101 +
102 + mask = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
103 + if (crypto->cmd == SET_KEY)
104 + mask |= 1 << key->hw_key_idx;
105 + else if (crypto->cmd == DISABLE_KEY)
106 + mask &= ~(1 << key->hw_key_idx);
107 + rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, mask);
108 + rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
109 +
110 + return 0;
111 +}
112 +
113 static void rt2500usb_config_filter(struct rt2x00_dev *rt2x00dev,
114 const unsigned int filter_flags)
115 {
116 @@ -864,7 +950,7 @@ static int rt2500usb_init_registers(stru
117
118 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
119 rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
120 - rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0xff);
121 + rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0);
122 rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
123
124 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
125 @@ -1086,7 +1172,7 @@ static void rt2500usb_write_tx_desc(stru
126 * Start writing the descriptor words.
127 */
128 rt2x00_desc_read(txd, 1, &word);
129 - rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
130 + rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
131 rt2x00_set_field32(&word, TXD_W1_AIFS, txdesc->aifs);
132 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
133 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
134 @@ -1099,6 +1185,11 @@ static void rt2500usb_write_tx_desc(stru
135 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
136 rt2x00_desc_write(txd, 2, word);
137
138 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
139 + _rt2x00_desc_write(txd, 3, skbdesc->iv);
140 + _rt2x00_desc_write(txd, 4, skbdesc->eiv);
141 + }
142 +
143 rt2x00_desc_read(txd, 0, &word);
144 rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
145 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
146 @@ -1113,7 +1204,8 @@ static void rt2500usb_write_tx_desc(stru
147 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
148 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
149 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
150 - rt2x00_set_field32(&word, TXD_W0_CIPHER, CIPHER_NONE);
151 + rt2x00_set_field32(&word, TXD_W0_CIPHER, txdesc->cipher);
152 + rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
153 rt2x00_desc_write(txd, 0, word);
154 }
155
156 @@ -1225,6 +1317,7 @@ static void rt2500usb_kick_tx_queue(stru
157 static void rt2500usb_fill_rxdone(struct queue_entry *entry,
158 struct rxdone_entry_desc *rxdesc)
159 {
160 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
161 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
162 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
163 __le32 *rxd =
164 @@ -1252,6 +1345,31 @@ static void rt2500usb_fill_rxdone(struct
165 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
166 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
167
168 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
169 + rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER);
170 + if (rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR))
171 + rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY;
172 + }
173 +
174 + if (rxdesc->cipher != CIPHER_NONE) {
175 + _rt2x00_desc_read(rxd, 2, &rxdesc->iv);
176 + _rt2x00_desc_read(rxd, 3, &rxdesc->eiv);
177 + /* ICV is located at the end of frame */
178 +
179 + /*
180 + * Hardware has stripped IV/EIV data from 802.11 frame during
181 + * decryption. It has provided the data seperately but rt2x00lib
182 + * should decide if it should be reinserted.
183 + */
184 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
185 + if (rxdesc->cipher != CIPHER_TKIP)
186 + rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
187 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
188 + rxdesc->flags |= RX_FLAG_DECRYPTED;
189 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
190 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
191 + }
192 +
193 /*
194 * Obtain the status about this packet.
195 * When frame was received with an OFDM bitrate,
196 @@ -1259,8 +1377,8 @@ static void rt2500usb_fill_rxdone(struct
197 * a CCK bitrate the signal is the rate in 100kbit/s.
198 */
199 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
200 - rxdesc->rssi = rt2x00_get_field32(word1, RXD_W1_RSSI) -
201 - entry->queue->rt2x00dev->rssi_offset;
202 + rxdesc->rssi =
203 + rt2x00_get_field32(word1, RXD_W1_RSSI) - rt2x00dev->rssi_offset;
204 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
205
206 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
207 @@ -1750,6 +1868,8 @@ static int rt2500usb_probe_hw(struct rt2
208 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
209 __set_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags);
210 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
211 + if (!modparam_nohwcrypt)
212 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
213 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
214
215 /*
216 @@ -1769,6 +1889,7 @@ static const struct ieee80211_ops rt2500
217 .config = rt2x00mac_config,
218 .config_interface = rt2x00mac_config_interface,
219 .configure_filter = rt2x00mac_configure_filter,
220 + .set_key = rt2x00mac_set_key,
221 .get_stats = rt2x00mac_get_stats,
222 .bss_info_changed = rt2x00mac_bss_info_changed,
223 .conf_tx = rt2x00mac_conf_tx,
224 @@ -1791,6 +1912,8 @@ static const struct rt2x00lib_ops rt2500
225 .get_tx_data_len = rt2500usb_get_tx_data_len,
226 .kick_tx_queue = rt2500usb_kick_tx_queue,
227 .fill_rxdone = rt2500usb_fill_rxdone,
228 + .config_shared_key = rt2500usb_config_key,
229 + .config_pairwise_key = rt2500usb_config_key,
230 .config_filter = rt2500usb_config_filter,
231 .config_intf = rt2500usb_config_intf,
232 .config_erp = rt2500usb_config_erp,
233 --- a/drivers/net/wireless/rt2x00/rt2500usb.h
234 +++ b/drivers/net/wireless/rt2x00/rt2500usb.h
235 @@ -447,6 +447,9 @@
236 #define SEC_CSR30 0x04bc
237 #define SEC_CSR31 0x04be
238
239 +#define KEY_ENTRY(__idx) \
240 + ( SEC_CSR0 + ((__idx) * 16) )
241 +
242 /*
243 * PHY control registers.
244 */
245 --- /dev/null
246 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
247 @@ -0,0 +1,2556 @@
248 +/*
249 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
250 + <http://rt2x00.serialmonkey.com>
251 +
252 + This program is free software; you can redistribute it and/or modify
253 + it under the terms of the GNU General Public License as published by
254 + the Free Software Foundation; either version 2 of the License, or
255 + (at your option) any later version.
256 +
257 + This program is distributed in the hope that it will be useful,
258 + but WITHOUT ANY WARRANTY; without even the implied warranty of
259 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
260 + GNU General Public License for more details.
261 +
262 + You should have received a copy of the GNU General Public License
263 + along with this program; if not, write to the
264 + Free Software Foundation, Inc.,
265 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
266 + */
267 +
268 +/*
269 + Module: rt2800pci
270 + Abstract: rt2800pci device specific routines.
271 + Supported chipsets: RT2800E & RT2800ED.
272 + */
273 +
274 +#include <linux/crc-ccitt.h>
275 +#include <linux/delay.h>
276 +#include <linux/etherdevice.h>
277 +#include <linux/init.h>
278 +#include <linux/kernel.h>
279 +#include <linux/module.h>
280 +#include <linux/pci.h>
281 +#include <linux/eeprom_93cx6.h>
282 +
283 +#include "rt2x00.h"
284 +#include "rt2x00pci.h"
285 +#include "rt2800pci.h"
286 +
287 +/*
288 + * Allow hardware encryption to be disabled.
289 + */
290 +static int modparam_nohwcrypt = 0;
291 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
292 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
293 +
294 +/*
295 + * Register access.
296 + * BBP and RF register require indirect register access,
297 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
298 + * These indirect registers work with busy bits,
299 + * and we will try maximal REGISTER_BUSY_COUNT times to access
300 + * the register while taking a REGISTER_BUSY_DELAY us delay
301 + * between each attampt. When the busy bit is still set at that time,
302 + * the access attempt is considered to have failed,
303 + * and we will print an error.
304 + */
305 +static u32 rt2800pci_bbp_check(struct rt2x00_dev *rt2x00dev)
306 +{
307 + u32 reg;
308 + unsigned int i;
309 +
310 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
311 + rt2x00pci_register_read(rt2x00dev, BBP_CSR_CFG, &reg);
312 + if (!rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY))
313 + break;
314 + udelay(REGISTER_BUSY_DELAY);
315 + }
316 +
317 + return reg;
318 +}
319 +
320 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
321 + const unsigned int word, const u8 value)
322 +{
323 + u32 reg;
324 +
325 + /*
326 + * Wait until the BBP becomes ready.
327 + */
328 + reg = rt2800pci_bbp_check(rt2x00dev);
329 + if (rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY)) {
330 + ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
331 + return;
332 + }
333 +
334 + /*
335 + * Write the data into the BBP.
336 + */
337 + reg = 0;
338 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
339 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
340 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
341 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
342 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
343 +
344 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
345 +}
346 +
347 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
348 + const unsigned int word, u8 *value)
349 +{
350 + u32 reg;
351 +
352 + /*
353 + * Wait until the BBP becomes ready.
354 + */
355 + reg = rt2800pci_bbp_check(rt2x00dev);
356 + if (rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY)) {
357 + ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
358 + return;
359 + }
360 +
361 + /*
362 + * Write the request into the BBP.
363 + */
364 + reg = 0;
365 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
366 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
367 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
368 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
369 +
370 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
371 +
372 + /*
373 + * Wait until the BBP becomes ready.
374 + */
375 + reg = rt2800pci_bbp_check(rt2x00dev);
376 + if (rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY)) {
377 + ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
378 + *value = 0xff;
379 + return;
380 + }
381 +
382 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
383 +}
384 +
385 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
386 + const unsigned int word, const u32 value)
387 +{
388 + u32 reg;
389 + unsigned int i;
390 +
391 + if (!word)
392 + return;
393 +
394 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
395 + rt2x00pci_register_read(rt2x00dev, RF_CSR_CFG0, &reg);
396 + if (!rt2x00_get_field32(reg, RF_CSR_CFG0_BUSY))
397 + goto rf_write;
398 + udelay(REGISTER_BUSY_DELAY);
399 + }
400 +
401 + ERROR(rt2x00dev, "RF_CSR_CFG0 register busy. Write failed.\n");
402 + return;
403 +
404 +rf_write:
405 + reg = 0;
406 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
407 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
408 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
409 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
410 +
411 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
412 + rt2x00_rf_write(rt2x00dev, word, value);
413 +}
414 +
415 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
416 +{
417 + struct rt2x00_dev *rt2x00dev = eeprom->data;
418 + u32 reg;
419 +
420 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
421 +
422 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
423 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
424 + eeprom->reg_data_clock =
425 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
426 + eeprom->reg_chip_select =
427 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
428 +}
429 +
430 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
431 +{
432 + struct rt2x00_dev *rt2x00dev = eeprom->data;
433 + u32 reg = 0;
434 +
435 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
436 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
437 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
438 + !!eeprom->reg_data_clock);
439 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
440 + !!eeprom->reg_chip_select);
441 +
442 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
443 +}
444 +
445 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
446 + const u8 command, const u8 token,
447 + const u8 arg0, const u8 arg1)
448 +{
449 + unsigned int i;
450 + u32 reg;
451 +
452 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
453 + rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
454 + if (!rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER))
455 + goto mcu_write;
456 + udelay(REGISTER_BUSY_DELAY);
457 + }
458 +
459 + ERROR(rt2x00dev, "mcu request error. "
460 + "Request 0x%02x failed for token 0x%02x.\n",
461 + command, token);
462 + return;
463 +
464 +mcu_write:
465 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
466 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
467 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
468 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
469 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
470 +
471 + reg = 0;
472 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
473 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
474 +}
475 +
476 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
477 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
478 + .owner = THIS_MODULE,
479 + .csr = {
480 + .read = rt2x00pci_register_read,
481 + .write = rt2x00pci_register_write,
482 + .flags = RT2X00DEBUGFS_OFFSET,
483 + .word_base = CSR_REG_BASE,
484 + .word_size = sizeof(u32),
485 + .word_count = CSR_REG_SIZE / sizeof(u32),
486 + },
487 + .eeprom = {
488 + .read = rt2x00_eeprom_read,
489 + .write = rt2x00_eeprom_write,
490 + .word_base = EEPROM_BASE,
491 + .word_size = sizeof(u16),
492 + .word_count = EEPROM_SIZE / sizeof(u16),
493 + },
494 + .bbp = {
495 + .read = rt2800pci_bbp_read,
496 + .write = rt2800pci_bbp_write,
497 + .word_base = BBP_BASE,
498 + .word_size = sizeof(u8),
499 + .word_count = BBP_SIZE / sizeof(u8),
500 + },
501 + .rf = {
502 + .read = rt2x00_rf_read,
503 + .write = rt2800pci_rf_write,
504 + .word_base = RF_BASE,
505 + .word_size = sizeof(u32),
506 + .word_count = RF_SIZE / sizeof(u32),
507 + },
508 +};
509 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
510 +
511 +#ifdef CONFIG_RT2X00_LIB_RFKILL
512 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
513 +{
514 + u32 reg;
515 +
516 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
517 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
518 +}
519 +#else
520 +#define rt2800pci_rfkill_poll NULL
521 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
522 +
523 +#ifdef CONFIG_RT2X00_LIB_LEDS
524 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
525 + enum led_brightness brightness)
526 +{
527 + struct rt2x00_led *led =
528 + container_of(led_cdev, struct rt2x00_led, led_dev);
529 + unsigned int enabled = brightness != LED_OFF;
530 + unsigned int bg_mode =
531 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
532 + unsigned int polarity =
533 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
534 + EEPROM_FREQ_LED_POLARITY);
535 + unsigned int ledmode =
536 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
537 + EEPROM_FREQ_LED_MODE);
538 +
539 + if (led->type == LED_TYPE_RADIO) {
540 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
541 + enabled ? 0x20 : 0);
542 + } else if (led->type == LED_TYPE_ASSOC) {
543 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
544 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
545 + } else if (led->type == LED_TYPE_QUALITY) {
546 + /*
547 + * The brightness is divided into 6 levels (0 - 5),
548 + * The specs tell us the following levels:
549 + * 0, 1 ,3, 7, 15, 31
550 + * to determine the level in a simple way we can simply
551 + * work with bitshifting:
552 + * (1 << level) - 1
553 + */
554 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
555 + (1 << brightness / (LED_FULL / 6)) - 1,
556 + polarity);
557 + }
558 +}
559 +
560 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
561 + unsigned long *delay_on,
562 + unsigned long *delay_off)
563 +{
564 + struct rt2x00_led *led =
565 + container_of(led_cdev, struct rt2x00_led, led_dev);
566 + u32 reg;
567 +
568 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
569 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
570 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
571 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
572 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
573 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
574 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
575 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
576 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
577 +
578 + return 0;
579 +}
580 +
581 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
582 + struct rt2x00_led *led,
583 + enum led_type type)
584 +{
585 + led->rt2x00dev = rt2x00dev;
586 + led->type = type;
587 + led->led_dev.brightness_set = rt2800pci_brightness_set;
588 + led->led_dev.blink_set = rt2800pci_blink_set;
589 + led->flags = LED_INITIALIZED;
590 +}
591 +#endif /* CONFIG_RT2X00_LIB_LEDS */
592 +
593 +/*
594 + * Configuration handlers.
595 + */
596 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
597 + struct rt2x00lib_crypto *crypto,
598 + struct ieee80211_key_conf *key)
599 +{
600 + u32 offset;
601 + u32 reg;
602 +
603 + offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
604 +
605 + reg = 0;
606 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
607 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
608 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
609 + crypto->cipher);
610 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
611 + (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
612 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
613 + rt2x00pci_register_write(rt2x00dev, offset, reg);
614 +}
615 +
616 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
617 + struct rt2x00lib_crypto *crypto,
618 + struct ieee80211_key_conf *key)
619 +{
620 + struct hw_key_entry key_entry;
621 + struct rt2x00_field32 field;
622 + u32 offset;
623 + u32 mask;
624 + u32 reg;
625 +
626 + if (crypto->cmd == SET_KEY) {
627 + memcpy(key_entry.key, crypto->key,
628 + sizeof(key_entry.key));
629 + memcpy(key_entry.tx_mic, crypto->tx_mic,
630 + sizeof(key_entry.tx_mic));
631 + memcpy(key_entry.rx_mic, crypto->rx_mic,
632 + sizeof(key_entry.rx_mic));
633 +
634 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
635 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
636 + &key_entry, sizeof(key_entry));
637 +
638 + /*
639 + * The driver does not support the IV/EIV generation
640 + * in hardware. However it doesn't support the IV/EIV
641 + * inside the ieee80211 frame either, but requires it
642 + * to be provided seperately for the descriptor.
643 + * rt2x00lib will cut the IV/EIV data out of all frames
644 + * given to us by mac80211, but we must tell mac80211
645 + * to generate the IV/EIV data.
646 + */
647 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
648 + }
649 +
650 + /*
651 + * The cipher types are stored over multiple registers
652 + * starting with SHARED_KEY_MODE_BASE each word will have
653 + * 32 bits and contains the cipher types for 2 modes each.
654 + * Using the correct defines correctly will cause overhead,
655 + * so just calculate the correct offset.
656 + */
657 + mask = key->hw_key_idx % 8;
658 + field.bit_offset = (3 * mask);
659 + field.bit_mask = 0x7 << field.bit_offset;
660 +
661 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
662 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
663 + rt2x00_set_field32(&reg, field,
664 + (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
665 + rt2x00pci_register_write(rt2x00dev, offset, reg);
666 +
667 + /*
668 + * Update WCID information
669 + */
670 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
671 +
672 + return 0;
673 +}
674 +
675 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
676 + struct rt2x00lib_crypto *crypto,
677 + struct ieee80211_key_conf *key)
678 +{
679 + struct hw_key_entry key_entry;
680 + u32 offset;
681 +
682 + /*
683 + * 1 pairwise key is possible per AID, this means that the AID
684 + * equals our hw_key_idx.
685 + */
686 + key->hw_key_idx = crypto->aid;
687 +
688 + if (crypto->cmd == SET_KEY) {
689 + memcpy(key_entry.key, crypto->key,
690 + sizeof(key_entry.key));
691 + memcpy(key_entry.tx_mic, crypto->tx_mic,
692 + sizeof(key_entry.tx_mic));
693 + memcpy(key_entry.rx_mic, crypto->rx_mic,
694 + sizeof(key_entry.rx_mic));
695 +
696 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
697 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
698 + &key_entry, sizeof(key_entry));
699 +
700 + /*
701 + * The driver does not support the IV/EIV generation
702 + * in hardware. However it doesn't support the IV/EIV
703 + * inside the ieee80211 frame either, but requires it
704 + * to be provided seperately for the descriptor.
705 + * rt2x00lib will cut the IV/EIV data out of all frames
706 + * given to us by mac80211, but we must tell mac80211
707 + * to generate the IV/EIV data.
708 + */
709 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
710 + }
711 +
712 + /*
713 + * Update WCID information
714 + */
715 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
716 +
717 + return 0;
718 +}
719 +
720 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
721 + const unsigned int filter_flags)
722 +{
723 + u32 reg;
724 +
725 + /*
726 + * Start configuration steps.
727 + * Note that the version error will always be dropped
728 + * and broadcast frames will always be accepted since
729 + * there is no filter for it at this time.
730 + */
731 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
732 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
733 + !(filter_flags & FIF_FCSFAIL));
734 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
735 + !(filter_flags & FIF_PLCPFAIL));
736 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
737 + !(filter_flags & FIF_PROMISC_IN_BSS));
738 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
739 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
740 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
741 + !(filter_flags & FIF_ALLMULTI));
742 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
743 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
744 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
745 + !(filter_flags & FIF_CONTROL));
746 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
747 + !(filter_flags & FIF_CONTROL));
748 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
749 + !(filter_flags & FIF_CONTROL));
750 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
751 + !(filter_flags & FIF_CONTROL));
752 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
753 + !(filter_flags & FIF_CONTROL));
754 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
755 + !(filter_flags & FIF_CONTROL));
756 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
757 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
758 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
759 + !(filter_flags & FIF_CONTROL));
760 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
761 +}
762 +
763 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
764 + struct rt2x00_intf *intf,
765 + struct rt2x00intf_conf *conf,
766 + const unsigned int flags)
767 +{
768 + unsigned int beacon_base;
769 + u32 reg;
770 +
771 + if (flags & CONFIG_UPDATE_TYPE) {
772 + /*
773 + * Clear current synchronisation setup.
774 + * For the Beacon base registers we only need to clear
775 + * the first byte since that byte contains the VALID and OWNER
776 + * bits which (when set to 0) will invalidate the entire beacon.
777 + */
778 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
779 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
780 +
781 + /*
782 + * Enable synchronisation.
783 + */
784 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
785 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
786 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
787 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
788 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
789 + }
790 +
791 + if (flags & CONFIG_UPDATE_MAC) {
792 + reg = le32_to_cpu(conf->mac[1]);
793 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
794 + conf->mac[1] = cpu_to_le32(reg);
795 +
796 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
797 + conf->mac, sizeof(conf->mac));
798 + }
799 +
800 + if (flags & CONFIG_UPDATE_BSSID) {
801 + reg = le32_to_cpu(conf->bssid[1]);
802 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
803 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
804 + conf->bssid[1] = cpu_to_le32(reg);
805 +
806 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
807 + conf->bssid, sizeof(conf->bssid));
808 + }
809 +}
810 +
811 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
812 + struct rt2x00lib_erp *erp)
813 +{
814 + u32 reg;
815 +
816 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
817 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
818 + erp->ack_timeout);
819 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
820 +
821 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
822 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
823 + !!erp->short_preamble);
824 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
825 + !!erp->short_preamble);
826 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
827 +
828 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
829 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
830 + erp->cts_protection ? 2 : 0);
831 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
832 +
833 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
834 + erp->basic_rates);
835 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE,
836 + erp->basic_rates >> 32);
837 +
838 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
839 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
840 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
841 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
842 +
843 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
844 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
845 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
846 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
847 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
848 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
849 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
850 +}
851 +
852 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
853 + struct antenna_setup *ant)
854 +{
855 + u16 eeprom;
856 + u8 r1;
857 + u8 r3;
858 +
859 + /*
860 + * FIXME: Use requested antenna configuration.
861 + */
862 +
863 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
864 +
865 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
866 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
867 +
868 + /*
869 + * Configure the TX antenna.
870 + */
871 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
872 + case 1:
873 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
874 + break;
875 + case 2:
876 + case 3:
877 + /* Do nothing */
878 + break;
879 + }
880 +
881 + /*
882 + * Configure the RX antenna.
883 + */
884 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
885 + case 1:
886 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
887 + break;
888 + case 2:
889 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
890 + break;
891 + case 3:
892 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
893 + break;
894 + }
895 +
896 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
897 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
898 +}
899 +
900 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
901 + struct rt2x00lib_conf *libconf)
902 +{
903 + u16 eeprom;
904 + short lna_gain;
905 +
906 + if (libconf->rf.channel <= 14) {
907 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
908 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
909 + } else if (libconf->rf.channel <= 64) {
910 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
911 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
912 + } else if (libconf->rf.channel <= 128) {
913 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
914 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
915 + } else {
916 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
917 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
918 + }
919 +
920 + rt2x00dev->lna_gain = lna_gain;
921 +}
922 +
923 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
924 + struct rf_channel *rf,
925 + struct channel_info *info)
926 +{
927 + u32 reg;
928 + unsigned int tx_pin;
929 + u16 eeprom;
930 +
931 + tx_pin = 0;
932 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
933 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
934 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
935 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
936 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
937 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
938 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
939 +
940 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
941 +
942 + /*
943 + * Determine antenna settings from EEPROM
944 + */
945 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
946 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
947 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
948 + /* Turn off unused PA or LNA when only 1T or 1R */
949 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
950 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
951 + }
952 +
953 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
954 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
955 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
956 + /* Turn off unused PA or LNA when only 1T or 1R */
957 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
958 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
959 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
960 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
961 +
962 + if (rf->channel > 14) {
963 + /*
964 + * When TX power is below 0, we should increase it by 7 to
965 + * make it a positive value (Minumum value is -7).
966 + * However this means that values between 0 and 7 have
967 + * double meaning, and we should set a 7DBm boost flag.
968 + */
969 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
970 + (info->tx_power1 >= 0));
971 +
972 + if (info->tx_power1 < 0)
973 + info->tx_power1 += 7;
974 +
975 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
976 + TXPOWER_A_TO_DEV(info->tx_power1));
977 +
978 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
979 + (info->tx_power2 >= 0));
980 +
981 + if (info->tx_power2 < 0)
982 + info->tx_power2 += 7;
983 +
984 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
985 + TXPOWER_A_TO_DEV(info->tx_power2));
986 +
987 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
988 + } else {
989 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
990 + TXPOWER_G_TO_DEV(info->tx_power1));
991 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
992 + TXPOWER_G_TO_DEV(info->tx_power2));
993 +
994 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
995 + }
996 +
997 + /* FIXME: How to determine bandwidth
998 + rt2x00_set_field32(&rf->rf4, RF4_BW40, !!(BBPCurrentBW == BW_40));
999 + */
1000 +
1001 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
1002 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
1003 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1004 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
1005 +
1006 + udelay(200);
1007 +
1008 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
1009 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
1010 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1011 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
1012 +
1013 + udelay(200);
1014 +
1015 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
1016 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
1017 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1018 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
1019 +
1020 + /*
1021 + * Change BBP settings
1022 + */
1023 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1024 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1025 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1026 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
1027 +
1028 + if (rf->channel <= 14) {
1029 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1030 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1031 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
1032 + } else {
1033 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
1034 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
1035 + }
1036 +
1037 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1038 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
1039 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
1040 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
1041 + } else {
1042 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
1043 +
1044 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1045 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
1046 + else
1047 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
1048 +
1049 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1050 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
1051 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
1052 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
1053 + }
1054 +
1055 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1056 +
1057 + msleep(1);
1058 +}
1059 +
1060 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1061 + const int txpower)
1062 +{
1063 + u32 reg;
1064 + u32 value = TXPOWER_G_TO_DEV(txpower);
1065 + u8 r1;
1066 +
1067 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1068 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1069 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
1070 +
1071 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1072 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1073 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1074 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1075 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1076 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1077 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1078 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1079 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1080 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1081 +
1082 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1083 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1084 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1085 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1086 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1087 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1088 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1089 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1090 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1091 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1092 +
1093 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1094 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1095 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1096 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1097 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1098 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1099 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1100 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1101 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1102 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1103 +
1104 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1105 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1106 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1107 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1108 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1109 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1110 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1111 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1112 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1113 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1114 +
1115 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1116 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1117 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1118 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1119 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1120 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1121 +}
1122 +
1123 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1124 + struct rt2x00lib_conf *libconf)
1125 +{
1126 + u32 reg;
1127 +
1128 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1129 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1130 + libconf->conf->short_frame_max_tx_count);
1131 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1132 + libconf->conf->long_frame_max_tx_count);
1133 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1134 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1135 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1136 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1137 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1138 +}
1139 +
1140 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
1141 + struct rt2x00lib_conf *libconf)
1142 +{
1143 + u32 reg;
1144 +
1145 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1146 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1147 + libconf->conf->beacon_int * 16);
1148 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1149 +}
1150 +
1151 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1152 + struct rt2x00lib_conf *libconf,
1153 + const unsigned int flags)
1154 +{
1155 + /* Always recalculate LNA gain before changing configuration */
1156 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
1157 +
1158 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1159 + rt2800pci_config_channel(rt2x00dev, &libconf->rf,
1160 + &libconf->channel);
1161 + if (flags & IEEE80211_CONF_CHANGE_POWER)
1162 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1163 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1164 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
1165 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1166 + rt2800pci_config_duration(rt2x00dev, libconf);
1167 +}
1168 +
1169 +/*
1170 + * Link tuning
1171 + */
1172 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1173 + struct link_qual *qual)
1174 +{
1175 + u32 reg;
1176 +
1177 + /*
1178 + * Update FCS error count from register.
1179 + */
1180 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1181 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1182 +
1183 + /*
1184 + * Update False CCA count from register.
1185 + */
1186 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1187 + qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
1188 +}
1189 +
1190 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1191 +{
1192 + u8 r66;
1193 +
1194 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1195 + r66 = 0x2e + rt2x00dev->lna_gain;
1196 + else {
1197 + if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
1198 + r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1199 + else
1200 + r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1201 + }
1202 +
1203 + rt2800pci_bbp_write(rt2x00dev, 66, r66);
1204 +}
1205 +
1206 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1207 +{
1208 + int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1209 + u8 r66_orig;
1210 + u8 r66;
1211 +
1212 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C)
1213 + return;
1214 +
1215 + rt2800pci_bbp_read(rt2x00dev, 66, &r66_orig);
1216 + r66 = r66_orig;
1217 +
1218 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1219 + r66 = 0x2e + rt2x00dev->lna_gain;
1220 + } else {
1221 + if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
1222 + r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1223 + else
1224 + r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1225 + }
1226 +
1227 + if (rssi > -80)
1228 + r66 += 0x10;
1229 +
1230 + if (rssi != r66_orig)
1231 + rt2800pci_bbp_write(rt2x00dev, 66, r66);
1232 +}
1233 +
1234 +/*
1235 + * Firmware functions
1236 + */
1237 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1238 +{
1239 + return FIRMWARE_RT2860;
1240 +}
1241 +
1242 +static u16 rt2800pci_get_firmware_crc(const void *data, const size_t len)
1243 +{
1244 + u16 crc;
1245 +
1246 + /*
1247 + * Use the crc ccitt algorithm.
1248 + * This will return the same value as the legacy driver which
1249 + * used bit ordering reversion on the both the firmware bytes
1250 + * before input input as well as on the final output.
1251 + * Obviously using crc ccitt directly is much more efficient.
1252 + * The last 2 bytes in the firmware array are the crc checksum itself,
1253 + * this means that we should never pass those 2 bytes to the crc
1254 + * algorithm.
1255 + */
1256 + crc = crc_ccitt(~0, data, len - 2);
1257 +
1258 + /*
1259 + * There is a small difference between the crc-itu-t + bitrev and
1260 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1261 + * will be swapped, use swab16 to convert the crc to the correct
1262 + * value.
1263 + */
1264 + return swab16(crc);
1265 +}
1266 +
1267 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1268 + const void *data, const size_t len)
1269 +{
1270 + unsigned int i;
1271 + u32 reg;
1272 +
1273 + /*
1274 + * Wait for stable hardware.
1275 + */
1276 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1277 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1278 + if (reg && reg != ~0)
1279 + break;
1280 + msleep(1);
1281 + }
1282 +
1283 + if (i == REGISTER_BUSY_COUNT) {
1284 + ERROR(rt2x00dev, "Unstable hardware.\n");
1285 + return -EBUSY;
1286 + }
1287 +
1288 + /*
1289 + * Disable DMA, will be reenabled later when enabling
1290 + * the radio.
1291 + */
1292 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1293 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1294 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1295 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1296 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1297 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1298 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1299 +
1300 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, ~0);
1301 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e1f);
1302 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e00);
1303 +
1304 + /*
1305 + * enable Host program ram write selection
1306 + */
1307 + reg = 0;
1308 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1309 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1310 +
1311 + /*
1312 + * Write firmware to device.
1313 + */
1314 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1315 + data, len);
1316 +
1317 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1318 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1319 +
1320 + /*
1321 + * Wait for device to stabilize.
1322 + */
1323 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1324 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1325 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1326 + break;
1327 + msleep(1);
1328 + }
1329 +
1330 + if (i == REGISTER_BUSY_COUNT) {
1331 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1332 + return -EBUSY;
1333 + }
1334 +
1335 + /*
1336 + * Initialize BBP R/W access agent
1337 + */
1338 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1339 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1340 +
1341 + return 0;
1342 +}
1343 +
1344 +/*
1345 + * Initialization functions.
1346 + */
1347 +static void rt2800pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1348 + struct queue_entry *entry)
1349 +{
1350 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1351 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1352 + u32 word;
1353 +
1354 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1355 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1356 + rt2x00_desc_write(entry_priv->desc, 0, word);
1357 +
1358 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1359 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1360 + rt2x00_desc_write(entry_priv->desc, 1, word);
1361 +}
1362 +
1363 +static void rt2800pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1364 + struct queue_entry *entry)
1365 +{
1366 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1367 + u32 word;
1368 +
1369 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1370 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1371 + rt2x00_desc_write(entry_priv->desc, 1, word);
1372 +}
1373 +
1374 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1375 +{
1376 + struct queue_entry_priv_pci *entry_priv;
1377 + u32 reg;
1378 +
1379 + /*
1380 + * Initialize registers.
1381 + */
1382 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1383 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1384 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1385 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1386 +
1387 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1388 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1389 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1390 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1391 +
1392 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1393 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1394 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1395 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1396 +
1397 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1398 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1399 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1400 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1401 +
1402 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1403 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1404 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1405 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1406 +
1407 + /*
1408 + * Enable global DMA configuration
1409 + */
1410 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1411 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1412 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1413 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1414 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1415 +
1416 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1417 +
1418 + return 0;
1419 +}
1420 +
1421 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1422 +{
1423 + u32 reg;
1424 + unsigned int i;
1425 +
1426 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1427 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1428 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1429 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1430 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1431 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1432 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1433 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1434 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1435 +
1436 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1437 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000000);
1438 +
1439 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1440 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1441 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1442 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1443 +
1444 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1445 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1446 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1447 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1448 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1449 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1450 +
1451 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1452 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1453 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1454 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1455 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1456 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1457 +
1458 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1459 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1460 +
1461 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1462 +
1463 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1464 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1465 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1466 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1467 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1468 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1469 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1470 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1471 +
1472 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1473 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1474 +
1475 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1476 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1477 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1478 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1479 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1480 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1481 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1482 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1483 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1484 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1485 +
1486 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1487 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1488 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1489 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1490 +
1491 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1492 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1493 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1494 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1495 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1496 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1497 +
1498 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1499 +
1500 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1501 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1502 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1503 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1504 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1505 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1506 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1507 +
1508 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1509 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1510 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1511 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1512 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1513 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1514 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1515 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1516 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1517 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1518 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1519 +
1520 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1521 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1522 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1523 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1524 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1525 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1526 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1527 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1528 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1529 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1530 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1531 +
1532 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1533 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1534 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1535 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1536 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1537 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1538 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1539 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1540 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1541 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1542 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1543 +
1544 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1545 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1546 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1547 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1548 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1549 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1550 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1551 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1552 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1553 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1554 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1555 +
1556 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1557 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1558 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1559 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1560 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1561 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1562 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1563 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1564 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1565 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1566 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1567 +
1568 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1569 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1570 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1571 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1572 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1573 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1574 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1575 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1576 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1577 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1578 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1579 +
1580 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1581 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1582 +
1583 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1584 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1585 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1586 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1587 +
1588 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1589 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1590 +
1591 + /*
1592 + * ASIC will keep garbage value after boot, clear encryption keys.
1593 + */
1594 + for (i = 0; i < 254; i++) {
1595 + u32 wcid[2] = { 0xffffffff, 0x0000ffff };
1596 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1597 + wcid, sizeof(wcid));
1598 + }
1599 +
1600 + for (i = 0; i < 4; i++)
1601 + rt2x00pci_register_write(rt2x00dev,
1602 + SHARED_KEY_MODE_ENTRY(i), 0);
1603 +
1604 + for (i = 0; i < 256; i++)
1605 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1606 +
1607 + /*
1608 + * Clear all beacons
1609 + * For the Beacon base registers we only need to clear
1610 + * the first byte since that byte contains the VALID and OWNER
1611 + * bits which (when set to 0) will invalidate the entire beacon.
1612 + */
1613 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1614 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1615 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1616 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1617 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1618 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1619 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1620 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1621 +
1622 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1623 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1624 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1625 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1626 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1627 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1628 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1629 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1630 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1631 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1632 +
1633 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1634 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1635 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1636 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1637 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1638 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1639 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1640 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1641 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1642 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1643 +
1644 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1645 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1646 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1647 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1648 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1649 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1650 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1651 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1652 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1653 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1654 +
1655 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1656 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1657 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1658 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1659 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1660 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1661 +
1662 + /*
1663 + * We must clear the error counters.
1664 + * These registers are cleared on read,
1665 + * so we may pass a useless variable to store the value.
1666 + */
1667 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1668 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1669 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1670 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1671 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1672 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1673 +
1674 + return 0;
1675 +}
1676 +
1677 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1678 +{
1679 + unsigned int i;
1680 + u32 reg;
1681 +
1682 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1683 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1684 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1685 + return 0;
1686 +
1687 + udelay(REGISTER_BUSY_DELAY);
1688 + }
1689 +
1690 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1691 + return -EACCES;
1692 +}
1693 +
1694 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1695 +{
1696 + unsigned int i;
1697 + u8 value;
1698 +
1699 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1700 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1701 + if ((value != 0xff) && (value != 0x00))
1702 + return 0;
1703 + udelay(REGISTER_BUSY_DELAY);
1704 + }
1705 +
1706 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1707 + return -EACCES;
1708 +}
1709 +
1710 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1711 +{
1712 + unsigned int i;
1713 + u16 eeprom;
1714 + u8 reg_id;
1715 + u8 value;
1716 +
1717 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1718 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1719 + return -EACCES;
1720 +
1721 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1722 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1723 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1724 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1725 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1726 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1727 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1728 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1729 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1730 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1731 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1732 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1733 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1734 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1735 +
1736 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C) {
1737 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1738 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1739 + }
1740 +
1741 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_D)
1742 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1743 +
1744 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1745 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1746 +
1747 + if (eeprom != 0xffff && eeprom != 0x0000) {
1748 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1749 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1750 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1751 + }
1752 + }
1753 +
1754 + return 0;
1755 +}
1756 +
1757 +/*
1758 + * Device state switch handlers.
1759 + */
1760 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1761 + enum dev_state state)
1762 +{
1763 + u32 reg;
1764 +
1765 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1766 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1767 + (state == STATE_RADIO_RX_ON) ||
1768 + (state == STATE_RADIO_RX_ON_LINK));
1769 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1770 +}
1771 +
1772 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1773 + enum dev_state state)
1774 +{
1775 + int mask = (state == STATE_RADIO_IRQ_OFF);
1776 + u32 reg;
1777 +
1778 + /*
1779 + * When interrupts are being enabled, the interrupt registers
1780 + * should clear the register to assure a clean state.
1781 + */
1782 + if (state == STATE_RADIO_IRQ_ON) {
1783 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1784 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1785 + }
1786 +
1787 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1788 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1789 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1790 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1791 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1792 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1793 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1794 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1795 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1796 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1797 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1798 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1799 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1800 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1801 +}
1802 +
1803 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1804 +{
1805 + unsigned int i;
1806 + u32 reg;
1807 +
1808 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1809 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1810 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1811 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1812 + return 0;
1813 +
1814 + msleep(1);
1815 + }
1816 +
1817 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1818 + return -EACCES;
1819 +}
1820 +
1821 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1822 +{
1823 + u32 reg;
1824 + u16 word;
1825 +
1826 + /*
1827 + * Initialize all registers.
1828 + */
1829 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1830 + rt2800pci_init_queues(rt2x00dev) ||
1831 + rt2800pci_init_registers(rt2x00dev) ||
1832 + rt2800pci_init_bbp(rt2x00dev)))
1833 + return -EIO;
1834 +
1835 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001a80);
1836 +
1837 + /* Wait for DMA, ignore error */
1838 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1839 +
1840 + /*
1841 + * Enable RX.
1842 + */
1843 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1844 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1845 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1846 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1847 +
1848 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1849 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1850 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1851 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1852 +
1853 + /*
1854 + * Initialize LED control
1855 + */
1856 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1857 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1858 + word & 0xff, (word >> 8) & 0xff);
1859 +
1860 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1861 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1862 + word & 0xff, (word >> 8) & 0xff);
1863 +
1864 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1865 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1866 + word & 0xff, (word >> 8) & 0xff);
1867 +
1868 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1869 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1870 +
1871 + /*
1872 + * Send signal to firmware during boot time.
1873 + */
1874 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1875 +
1876 + return 0;
1877 +}
1878 +
1879 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1880 +{
1881 + u32 reg;
1882 +
1883 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1884 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1885 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1886 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1887 +
1888 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1889 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1890 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1891 +
1892 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1893 +
1894 + /* Wait for DMA, ignore error */
1895 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1896 +}
1897 +
1898 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1899 + enum dev_state state)
1900 +{
1901 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1902 +
1903 + if (state == STATE_AWAKE)
1904 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1905 + else
1906 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1907 +
1908 + return 0;
1909 +}
1910 +
1911 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1912 + enum dev_state state)
1913 +{
1914 + int retval = 0;
1915 +
1916 + switch (state) {
1917 + case STATE_RADIO_ON:
1918 + /*
1919 + * Before the radio can be enabled, the device first has
1920 + * to be woken up. After that it needs a bit of time
1921 + * to be fully awake and the radio can be enabled.
1922 + */
1923 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1924 + msleep(1);
1925 + retval = rt2800pci_enable_radio(rt2x00dev);
1926 + break;
1927 + case STATE_RADIO_OFF:
1928 + /*
1929 + * After the radio has been disablee, the device should
1930 + * be put to sleep for powersaving.
1931 + */
1932 + rt2800pci_disable_radio(rt2x00dev);
1933 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1934 + break;
1935 + case STATE_RADIO_RX_ON:
1936 + case STATE_RADIO_RX_ON_LINK:
1937 + case STATE_RADIO_RX_OFF:
1938 + case STATE_RADIO_RX_OFF_LINK:
1939 + rt2800pci_toggle_rx(rt2x00dev, state);
1940 + break;
1941 + case STATE_RADIO_IRQ_ON:
1942 + case STATE_RADIO_IRQ_OFF:
1943 + rt2800pci_toggle_irq(rt2x00dev, state);
1944 + break;
1945 + case STATE_DEEP_SLEEP:
1946 + case STATE_SLEEP:
1947 + case STATE_STANDBY:
1948 + case STATE_AWAKE:
1949 + retval = rt2800pci_set_state(rt2x00dev, state);
1950 + break;
1951 + default:
1952 + retval = -ENOTSUPP;
1953 + break;
1954 + }
1955 +
1956 + if (unlikely(retval))
1957 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1958 + state, retval);
1959 +
1960 + return retval;
1961 +}
1962 +
1963 +/*
1964 + * TX descriptor initialization
1965 + */
1966 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1967 + struct sk_buff *skb,
1968 + struct txentry_desc *txdesc)
1969 +{
1970 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1971 + __le32 *txd = skbdesc->desc;
1972 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1973 + u32 word;
1974 +
1975 + /*
1976 + * Initialize TX Info descriptor
1977 + */
1978 + rt2x00_desc_read(txwi, 0, &word);
1979 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1980 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1981 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1982 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1983 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1984 + rt2x00_set_field32(&word, TXWI_W0_TS,
1985 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1986 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1987 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1988 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1989 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1990 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1991 + rt2x00_set_field32(&word, TXWI_W0_BW,
1992 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1993 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1994 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1995 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1996 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1997 + rt2x00_desc_write(txwi, 0, word);
1998 +
1999 + rt2x00_desc_read(txwi, 1, &word);
2000 + rt2x00_set_field32(&word, TXWI_W1_ACK,
2001 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2002 + rt2x00_set_field32(&word, TXWI_W1_ACK,
2003 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
2004 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2005 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
2006 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
2007 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2008 + skbdesc->entry->entry_idx);
2009 + rt2x00_desc_write(txwi, 1, word);
2010 +
2011 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
2012 + _rt2x00_desc_write(txwi, 2, skbdesc->iv);
2013 + _rt2x00_desc_write(txwi, 3, skbdesc->eiv);
2014 + }
2015 +
2016 + /*
2017 + * Initialize TX descriptor
2018 + */
2019 + rt2x00_desc_read(txd, 0, &word);
2020 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
2021 + rt2x00_desc_write(txd, 0, word);
2022 +
2023 + rt2x00_desc_read(txd, 1, &word);
2024 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
2025 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
2026 + rt2x00_set_field32(&word, TXD_W1_BURST,
2027 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2028 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
2029 + rt2x00dev->hw->extra_tx_headroom);
2030 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
2031 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2032 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
2033 + rt2x00_desc_write(txd, 1, word);
2034 +
2035 + rt2x00_desc_read(txd, 2, &word);
2036 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
2037 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
2038 + rt2x00_desc_write(txd, 2, word);
2039 +
2040 + rt2x00_desc_read(txd, 3, &word);
2041 + rt2x00_set_field32(&word, TXD_W3_WIV, 1);
2042 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
2043 + rt2x00_desc_write(txd, 3, word);
2044 +}
2045 +
2046 +/*
2047 + * TX data initialization
2048 + */
2049 +static void rt2800pci_write_beacon(struct queue_entry *entry)
2050 +{
2051 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2052 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2053 + unsigned int beacon_base;
2054 + u32 reg;
2055 +
2056 + /*
2057 + * Disable beaconing while we are reloading the beacon data,
2058 + * otherwise we might be sending out invalid data.
2059 + */
2060 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2061 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2062 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2063 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2064 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2065 +
2066 + /*
2067 + * Write entire beacon with descriptor to register.
2068 + */
2069 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2070 + rt2x00pci_register_multiwrite(rt2x00dev,
2071 + beacon_base,
2072 + skbdesc->desc, skbdesc->desc_len);
2073 + rt2x00pci_register_multiwrite(rt2x00dev,
2074 + beacon_base + skbdesc->desc_len,
2075 + entry->skb->data, entry->skb->len);
2076 +
2077 + /*
2078 + * Clean up beacon skb.
2079 + */
2080 + dev_kfree_skb_any(entry->skb);
2081 + entry->skb = NULL;
2082 +}
2083 +
2084 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2085 + const enum data_queue_qid queue)
2086 +{
2087 + u32 reg;
2088 +
2089 + if (queue == QID_BEACON) {
2090 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2091 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2092 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2093 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2094 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2095 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2096 + }
2097 + return;
2098 + }
2099 +
2100 + /* FIXME: How can be kick normal TX queues? */
2101 +}
2102 +
2103 +/*
2104 + * RX control handlers
2105 + */
2106 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2107 + struct rxdone_entry_desc *rxdesc)
2108 +{
2109 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2110 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2111 + __le32 *rxd = entry_priv->desc;
2112 + __le32 *rxwi = (__le32 *)entry->skb->data;
2113 + u32 rxd3;
2114 + u32 rxwi0;
2115 + u32 rxwi1;
2116 + u32 rxwi2;
2117 + u32 rxwi3;
2118 + u8 mcs;
2119 + u8 mode;
2120 +
2121 + rt2x00_desc_read(rxd, 3, &rxd3);
2122 + rt2x00_desc_read(rxwi, 0, &rxwi0);
2123 + rt2x00_desc_read(rxwi, 1, &rxwi1);
2124 + rt2x00_desc_read(rxwi, 2, &rxwi2);
2125 + rt2x00_desc_read(rxwi, 3, &rxwi3);
2126 +
2127 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2128 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2129 +
2130 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2131 + /*
2132 + * FIXME: Set cipher on WEP64 when it has been decrypted,
2133 + * at the moment we cannot determine the real cipher type yet.
2134 + */
2135 + rxdesc->cipher =
2136 + rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED);
2137 + rxdesc->cipher_status =
2138 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2139 + }
2140 +
2141 + if (rxdesc->cipher != CIPHER_NONE) {
2142 + /*
2143 + * Hardware has stripped IV/EIV data from 802.11 frame during
2144 + * decryption. It has provided the data seperately but rt2x00lib
2145 + * should decide if it should be reinserted.
2146 + */
2147 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2148 +
2149 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2150 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2151 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2152 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2153 + }
2154 +
2155 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2156 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2157 +
2158 + /*
2159 + * Create the MCS value, when the mode is CCK, mask of 0x8 bit
2160 + * to remove the short preamble flag.
2161 + */
2162 + mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2163 + mcs = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2164 +
2165 + if (mode == RATE_MODE_CCK)
2166 + mcs &= ~0x8;
2167 +
2168 + rxdesc->signal = (mode << 8) | mcs;
2169 +
2170 + rxdesc->rssi =
2171 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2172 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
2173 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
2174 +
2175 + rxdesc->noise =
2176 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2177 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2178 +
2179 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2180 +
2181 + /*
2182 + * Remove TXWI descriptor from start of buffer.
2183 + */
2184 + skb_pull(entry->skb, TXWI_DESC_SIZE);
2185 + skb_trim(entry->skb, rxdesc->size);
2186 +}
2187 +
2188 +/*
2189 + * Interrupt functions.
2190 + */
2191 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2192 +{
2193 + struct rt2x00_dev *rt2x00dev = dev_instance;
2194 +
2195 + /* FIXME */
2196 +
2197 + return IRQ_HANDLED;
2198 +}
2199 +
2200 +/*
2201 + * Device probe functions.
2202 + */
2203 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2204 +{
2205 + struct eeprom_93cx6 eeprom;
2206 + u32 reg;
2207 + u16 word;
2208 + u8 *mac;
2209 + u8 default_lna_gain;
2210 +
2211 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2212 +
2213 + eeprom.data = rt2x00dev;
2214 + eeprom.register_read = rt2800pci_eepromregister_read;
2215 + eeprom.register_write = rt2800pci_eepromregister_write;
2216 + eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2217 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2218 + eeprom.reg_data_in = 0;
2219 + eeprom.reg_data_out = 0;
2220 + eeprom.reg_data_clock = 0;
2221 + eeprom.reg_chip_select = 0;
2222 +
2223 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2224 + EEPROM_SIZE / sizeof(u16));
2225 +
2226 + /*
2227 + * Start validation of the data that has been read.
2228 + */
2229 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2230 + if (!is_valid_ether_addr(mac)) {
2231 + DECLARE_MAC_BUF(macbuf);
2232 +
2233 + random_ether_addr(mac);
2234 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2235 + }
2236 +
2237 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2238 + if (word == 0xffff) {
2239 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2240 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2241 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2242 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2243 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2244 + }
2245 +
2246 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2247 + if (word != 0) {
2248 + /* NIC configuration must always be 0. */
2249 + word = 0;
2250 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2251 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2252 + }
2253 +
2254 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2255 + if ((word & 0x00ff) == 0x00ff) {
2256 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2257 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2258 + LED_MODE_TXRX_ACTIVITY);
2259 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2260 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2261 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2262 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2263 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2264 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2265 + }
2266 +
2267 + /*
2268 + * During the LNA validation we are going to use
2269 + * lna0 as correct value. Note that EEPROM_LNA
2270 + * is never validated.
2271 + */
2272 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2273 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2274 +
2275 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2276 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2277 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2278 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2279 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2280 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2281 +
2282 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2283 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2284 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2285 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2286 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2287 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2288 + default_lna_gain);
2289 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2290 +
2291 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2292 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2293 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2294 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2295 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2296 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2297 +
2298 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2299 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2300 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2301 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2302 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2303 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2304 + default_lna_gain);
2305 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2306 +
2307 + return 0;
2308 +}
2309 +
2310 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2311 +{
2312 + u32 reg;
2313 + u16 value;
2314 + u16 eeprom;
2315 + u16 device;
2316 +
2317 + /*
2318 + * Read EEPROM word for configuration.
2319 + */
2320 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2321 +
2322 + /*
2323 + * Identify RF chipset.
2324 + * To determine the RT chip we have to read the
2325 + * PCI header of the device.
2326 + */
2327 + pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2328 + PCI_CONFIG_HEADER_DEVICE, &device);
2329 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2330 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2331 + reg = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
2332 + rt2x00_set_chip(rt2x00dev, device, value, reg);
2333 +
2334 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2335 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2336 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2337 + !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2338 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2339 + return -ENODEV;
2340 + }
2341 +
2342 + /*
2343 + * Read frequency offset and RF programming sequence.
2344 + */
2345 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2346 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2347 +
2348 + /*
2349 + * Read external LNA informations.
2350 + */
2351 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2352 +
2353 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2354 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2355 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2356 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2357 +
2358 + /*
2359 + * Detect if this device has an hardware controlled radio.
2360 + */
2361 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2362 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2363 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2364 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2365 +
2366 + /*
2367 + * Store led settings, for correct led behaviour.
2368 + */
2369 +#ifdef CONFIG_RT2X00_LIB_LEDS
2370 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2371 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2372 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2373 +
2374 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2375 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2376 +
2377 + return 0;
2378 +}
2379 +
2380 +/*
2381 + * RF value list for rt2860
2382 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2383 + */
2384 +static const struct rf_channel rf_vals[] = {
2385 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2386 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2387 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2388 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2389 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2390 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2391 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2392 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2393 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2394 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2395 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2396 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2397 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2398 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2399 +
2400 + /* 802.11 UNI / HyperLan 2 */
2401 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2402 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2403 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2404 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2405 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2406 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2407 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2408 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2409 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2410 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2411 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2412 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2413 +
2414 + /* 802.11 HyperLan 2 */
2415 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2416 + { 102, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed793 },
2417 + { 104, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed1a3 },
2418 + { 108, 0x18402ecc, 0x184c0a32, 0x18178a55, 0x180ed193 },
2419 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2420 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2421 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2422 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2423 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2424 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2425 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2426 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2427 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2428 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2429 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2430 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2431 +
2432 + /* 802.11 UNII */
2433 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2434 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2435 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2436 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2437 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2438 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2439 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2440 +
2441 + /* 802.11 Japan */
2442 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2443 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2444 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2445 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2446 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2447 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2448 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2449 +};
2450 +
2451 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2452 +{
2453 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2454 + struct channel_info *info;
2455 + char *tx_power1;
2456 + char *tx_power2;
2457 + unsigned int i;
2458 +
2459 + /*
2460 + * Initialize all hw fields.
2461 + */
2462 + rt2x00dev->hw->flags =
2463 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2464 + IEEE80211_HW_SIGNAL_DBM;
2465 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2466 +
2467 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2468 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2469 + rt2x00_eeprom_addr(rt2x00dev,
2470 + EEPROM_MAC_ADDR_0));
2471 +
2472 + /*
2473 + * Initialize hw_mode information.
2474 + */
2475 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2476 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2477 +
2478 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2479 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2480 + spec->num_channels = 14;
2481 + spec->channels = rf_vals;
2482 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2483 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2484 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2485 + spec->num_channels = ARRAY_SIZE(rf_vals);
2486 + spec->channels = rf_vals;
2487 + }
2488 +
2489 + /*
2490 + * Create channel information array
2491 + */
2492 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2493 + if (!info)
2494 + return -ENOMEM;
2495 +
2496 + spec->channels_info = info;
2497 +
2498 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2499 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2500 +
2501 + for (i = 0; i < 14; i++) {
2502 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2503 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2504 + }
2505 +
2506 + if (spec->num_channels > 14) {
2507 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2508 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2509 +
2510 + for (i = 14; i < spec->num_channels; i++) {
2511 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2512 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2513 + }
2514 + }
2515 +
2516 + return 0;
2517 +}
2518 +
2519 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2520 +{
2521 + int retval;
2522 +
2523 + /*
2524 + * Allocate eeprom data.
2525 + */
2526 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2527 + if (retval)
2528 + return retval;
2529 +
2530 + retval = rt2800pci_init_eeprom(rt2x00dev);
2531 + if (retval)
2532 + return retval;
2533 +
2534 + /*
2535 + * Initialize hw specifications.
2536 + */
2537 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2538 + if (retval)
2539 + return retval;
2540 +
2541 + /*
2542 + * This device requires firmware.
2543 + */
2544 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2545 + if (!modparam_nohwcrypt)
2546 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2547 +
2548 + /*
2549 + * Set the rssi offset.
2550 + */
2551 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2552 +
2553 + return 0;
2554 +}
2555 +
2556 +/*
2557 + * IEEE80211 stack callback functions.
2558 + */
2559 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2560 +{
2561 + struct rt2x00_dev *rt2x00dev = hw->priv;
2562 + u32 reg;
2563 +
2564 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2565 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2566 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2567 +
2568 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2569 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2570 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2571 +
2572 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2573 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2574 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2575 +
2576 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2577 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
2578 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2579 +
2580 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2581 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
2582 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2583 +
2584 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2585 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
2586 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2587 +
2588 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2589 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
2590 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2591 +
2592 + return 0;
2593 +}
2594 +
2595 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2596 + const struct ieee80211_tx_queue_params *params)
2597 +{
2598 + struct rt2x00_dev *rt2x00dev = hw->priv;
2599 + struct data_queue *queue;
2600 + struct rt2x00_field32 field;
2601 + int retval;
2602 + u32 reg;
2603 + u32 offset;
2604 +
2605 + /*
2606 + * First pass the configuration through rt2x00lib, that will
2607 + * update the queue settings and validate the input. After that
2608 + * we are free to update the registers based on the value
2609 + * in the queue parameter.
2610 + */
2611 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2612 + if (retval)
2613 + return retval;
2614 +
2615 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2616 +
2617 + /* Update WMM TXOP register */
2618 + if (queue_idx < 2) {
2619 + field.bit_offset = queue_idx * 16;
2620 + field.bit_mask = 0xffff << field.bit_offset;
2621 +
2622 + rt2x00pci_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
2623 + rt2x00_set_field32(&reg, field, queue->txop);
2624 + rt2x00pci_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
2625 + } else if (queue_idx < 4) {
2626 + field.bit_offset = (queue_idx - 2) * 16;
2627 + field.bit_mask = 0xffff << field.bit_offset;
2628 +
2629 + rt2x00pci_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
2630 + rt2x00_set_field32(&reg, field, queue->txop);
2631 + rt2x00pci_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
2632 + }
2633 +
2634 + /* Update WMM registers */
2635 + field.bit_offset = queue_idx * 4;
2636 + field.bit_mask = 0xf << field.bit_offset;
2637 +
2638 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2639 + rt2x00_set_field32(&reg, field, queue->aifs);
2640 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2641 +
2642 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2643 + rt2x00_set_field32(&reg, field, queue->cw_min);
2644 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2645 +
2646 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2647 + rt2x00_set_field32(&reg, field, queue->cw_max);
2648 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2649 +
2650 + /* Update EDCA registers */
2651 + if (queue_idx < 4) {
2652 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2653 +
2654 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2655 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2656 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2657 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2658 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2659 + }
2660 +
2661 + return 0;
2662 +}
2663 +
2664 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2665 +{
2666 + struct rt2x00_dev *rt2x00dev = hw->priv;
2667 + u64 tsf;
2668 + u32 reg;
2669 +
2670 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2671 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2672 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2673 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2674 +
2675 + return tsf;
2676 +}
2677 +
2678 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2679 + .tx = rt2x00mac_tx,
2680 + .start = rt2x00mac_start,
2681 + .stop = rt2x00mac_stop,
2682 + .add_interface = rt2x00mac_add_interface,
2683 + .remove_interface = rt2x00mac_remove_interface,
2684 + .config = rt2x00mac_config,
2685 + .config_interface = rt2x00mac_config_interface,
2686 + .configure_filter = rt2x00mac_configure_filter,
2687 + .set_key = rt2x00mac_set_key,
2688 + .get_stats = rt2x00mac_get_stats,
2689 + .set_rts_threshold = rt2800pci_set_rts_threshold,
2690 + .bss_info_changed = rt2x00mac_bss_info_changed,
2691 + .conf_tx = rt2800pci_conf_tx,
2692 + .get_tx_stats = rt2x00mac_get_tx_stats,
2693 + .get_tsf = rt2800pci_get_tsf,
2694 +};
2695 +
2696 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2697 + .irq_handler = rt2800pci_interrupt,
2698 + .probe_hw = rt2800pci_probe_hw,
2699 + .get_firmware_name = rt2800pci_get_firmware_name,
2700 + .get_firmware_crc = rt2800pci_get_firmware_crc,
2701 + .load_firmware = rt2800pci_load_firmware,
2702 + .initialize = rt2x00pci_initialize,
2703 + .uninitialize = rt2x00pci_uninitialize,
2704 + .init_rxentry = rt2800pci_init_rxentry,
2705 + .init_txentry = rt2800pci_init_txentry,
2706 + .set_device_state = rt2800pci_set_device_state,
2707 + .rfkill_poll = rt2800pci_rfkill_poll,
2708 + .link_stats = rt2800pci_link_stats,
2709 + .reset_tuner = rt2800pci_reset_tuner,
2710 + .link_tuner = rt2800pci_link_tuner,
2711 + .write_tx_desc = rt2800pci_write_tx_desc,
2712 + .write_tx_data = rt2x00pci_write_tx_data,
2713 + .write_beacon = rt2800pci_write_beacon,
2714 + .kick_tx_queue = rt2800pci_kick_tx_queue,
2715 + .fill_rxdone = rt2800pci_fill_rxdone,
2716 + .config_shared_key = rt2800pci_config_shared_key,
2717 + .config_pairwise_key = rt2800pci_config_pairwise_key,
2718 + .config_filter = rt2800pci_config_filter,
2719 + .config_intf = rt2800pci_config_intf,
2720 + .config_erp = rt2800pci_config_erp,
2721 + .config_ant = rt2800pci_config_ant,
2722 + .config = rt2800pci_config,
2723 +};
2724 +
2725 +static const struct data_queue_desc rt2800pci_queue_rx = {
2726 + .entry_num = RX_ENTRIES,
2727 + .data_size = DATA_FRAME_SIZE,
2728 + .desc_size = RXD_DESC_SIZE,
2729 + .priv_size = sizeof(struct queue_entry_priv_pci),
2730 +};
2731 +
2732 +static const struct data_queue_desc rt2800pci_queue_tx = {
2733 + .entry_num = TX_ENTRIES,
2734 + .data_size = DATA_FRAME_SIZE,
2735 + .desc_size = TXD_DESC_SIZE,
2736 + .priv_size = sizeof(struct queue_entry_priv_pci),
2737 +};
2738 +
2739 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2740 + .entry_num = 8 * BEACON_ENTRIES,
2741 + .data_size = 0, /* No DMA required for beacons */
2742 + .desc_size = TXWI_DESC_SIZE,
2743 + .priv_size = sizeof(struct queue_entry_priv_pci),
2744 +};
2745 +
2746 +static const struct rt2x00_ops rt2800pci_ops = {
2747 + .name = KBUILD_MODNAME,
2748 + .max_sta_intf = 1,
2749 + .max_ap_intf = 8,
2750 + .eeprom_size = EEPROM_SIZE,
2751 + .rf_size = RF_SIZE,
2752 + .tx_queues = NUM_TX_QUEUES,
2753 + .rx = &rt2800pci_queue_rx,
2754 + .tx = &rt2800pci_queue_tx,
2755 + .bcn = &rt2800pci_queue_bcn,
2756 + .lib = &rt2800pci_rt2x00_ops,
2757 + .hw = &rt2800pci_mac80211_ops,
2758 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2759 + .debugfs = &rt2800pci_rt2x00debug,
2760 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2761 +};
2762 +
2763 +/*
2764 + * RT2800pci module information.
2765 + */
2766 +static struct pci_device_id rt2800pci_device_table[] = {
2767 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2768 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2769 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2770 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2771 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2772 + { 0, }
2773 +};
2774 +
2775 +MODULE_AUTHOR(DRV_PROJECT);
2776 +MODULE_VERSION(DRV_VERSION);
2777 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2778 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2779 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2780 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2781 +MODULE_LICENSE("GPL");
2782 +
2783 +static struct pci_driver rt2800pci_driver = {
2784 + .name = KBUILD_MODNAME,
2785 + .id_table = rt2800pci_device_table,
2786 + .probe = rt2x00pci_probe,
2787 + .remove = __devexit_p(rt2x00pci_remove),
2788 + .suspend = rt2x00pci_suspend,
2789 + .resume = rt2x00pci_resume,
2790 +};
2791 +
2792 +static int __init rt2800pci_init(void)
2793 +{
2794 + return pci_register_driver(&rt2800pci_driver);
2795 +}
2796 +
2797 +static void __exit rt2800pci_exit(void)
2798 +{
2799 + pci_unregister_driver(&rt2800pci_driver);
2800 +}
2801 +
2802 +module_init(rt2800pci_init);
2803 +module_exit(rt2800pci_exit);
2804 --- /dev/null
2805 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2806 @@ -0,0 +1,1862 @@
2807 +/*
2808 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
2809 + <http://rt2x00.serialmonkey.com>
2810 +
2811 + This program is free software; you can redistribute it and/or modify
2812 + it under the terms of the GNU General Public License as published by
2813 + the Free Software Foundation; either version 2 of the License, or
2814 + (at your option) any later version.
2815 +
2816 + This program is distributed in the hope that it will be useful,
2817 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2818 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2819 + GNU General Public License for more details.
2820 +
2821 + You should have received a copy of the GNU General Public License
2822 + along with this program; if not, write to the
2823 + Free Software Foundation, Inc.,
2824 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2825 + */
2826 +
2827 +/*
2828 + Module: rt2800pci
2829 + Abstract: Data structures and registers for the rt2800pci module.
2830 + Supported chipsets: RT2800E & RT2800ED.
2831 + */
2832 +
2833 +#ifndef RT2800PCI_H
2834 +#define RT2800PCI_H
2835 +
2836 +/*
2837 + * RF chip defines.
2838 + *
2839 + * RF2820 2.4G 2T3R
2840 + * RF2850 2.4G/5G 2T3R
2841 + * RF2720 2.4G 1T2R
2842 + * RF2750 2.4G/5G 1T2R
2843 + */
2844 +#define RF2820 0x0001
2845 +#define RF2850 0x0002
2846 +#define RF2720 0x0003
2847 +#define RF2750 0x0004
2848 +
2849 +/*
2850 + * RT2860 version
2851 + */
2852 +#define RT2860_VERSION_C 0x0100
2853 +#define RT2860_VERSION_D 0x0101
2854 +#define RT2860_VERSION_E 0x0200
2855 +
2856 +/*
2857 + * Signal information.
2858 + * Defaul offset is required for RSSI <-> dBm conversion.
2859 + */
2860 +#define MAX_SIGNAL 0 /* FIXME */
2861 +#define MAX_RX_SSI 0 /* FIXME */
2862 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
2863 +
2864 +/*
2865 + * Register layout information.
2866 + */
2867 +#define CSR_REG_BASE 0x1000
2868 +#define CSR_REG_SIZE 0x0800
2869 +#define EEPROM_BASE 0x0000
2870 +#define EEPROM_SIZE 0x0110
2871 +#define BBP_BASE 0x0000
2872 +#define BBP_SIZE 0x0080
2873 +#define RF_BASE 0x0000
2874 +#define RF_SIZE 0x0014
2875 +
2876 +/*
2877 + * Number of TX queues.
2878 + */
2879 +#define NUM_TX_QUEUES 4
2880 +
2881 +/*
2882 + * PCI registers.
2883 + */
2884 +
2885 +/*
2886 + * PCI Configuration Header
2887 + */
2888 +#define PCI_CONFIG_HEADER_VENDOR 0x0000
2889 +#define PCI_CONFIG_HEADER_DEVICE 0x0002
2890 +
2891 +/*
2892 + * E2PROM_CSR: EEPROM control register.
2893 + * RELOAD: Write 1 to reload eeprom content.
2894 + * TYPE_93C46: 1: 93c46, 0:93c66.
2895 + * LOAD_STATUS: 1:loading, 0:done.
2896 + */
2897 +#define E2PROM_CSR 0x0004
2898 +#define E2PROM_CSR_RELOAD FIELD32(0x00000001)
2899 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
2900 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
2901 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
2902 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
2903 +#define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
2904 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
2905 +
2906 +/*
2907 + * HOST-MCU shared memory
2908 + */
2909 +#define HOST_CMD_CSR 0x0404
2910 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
2911 +
2912 +/*
2913 + * INT_SOURCE_CSR: Interrupt source register.
2914 + * Write one to clear corresponding bit.
2915 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2916 + */
2917 +#define INT_SOURCE_CSR 0x0200
2918 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
2919 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
2920 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
2921 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2922 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2923 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2924 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2925 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2926 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2927 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
2928 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
2929 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
2930 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
2931 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2932 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2933 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
2934 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
2935 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
2936 +
2937 +/*
2938 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2939 + */
2940 +#define INT_MASK_CSR 0x0204
2941 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
2942 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
2943 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
2944 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2945 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2946 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2947 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2948 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2949 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2950 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
2951 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x40000000)
2952 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x80000000)
2953 +
2954 +/*
2955 + * WPDMA_GLO_CFG
2956 + */
2957 +#define WPDMA_GLO_CFG 0x0208
2958 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
2959 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
2960 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
2961 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
2962 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
2963 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
2964 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
2965 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
2966 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
2967 +
2968 +/*
2969 + * WPDMA_RST_IDX
2970 + */
2971 +#define WPDMA_RST_IDX 0x020c
2972 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
2973 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
2974 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
2975 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
2976 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
2977 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
2978 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
2979 +
2980 +/*
2981 + * DELAY_INT_CFG
2982 + */
2983 +#define DELAY_INT_CFG 0x0210
2984 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
2985 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
2986 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
2987 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
2988 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
2989 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
2990 +
2991 +/*
2992 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2993 + * AIFSN0: AC_BE
2994 + * AIFSN1: AC_BK
2995 + * AIFSN1: AC_VI
2996 + * AIFSN1: AC_VO
2997 + */
2998 +#define WMM_AIFSN_CFG 0x0214
2999 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3000 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3001 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3002 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3003 +
3004 +/*
3005 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3006 + * CWMIN0: AC_BE
3007 + * CWMIN1: AC_BK
3008 + * CWMIN1: AC_VI
3009 + * CWMIN1: AC_VO
3010 + */
3011 +#define WMM_CWMIN_CFG 0x0218
3012 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3013 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3014 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3015 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3016 +
3017 +/*
3018 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3019 + * CWMAX0: AC_BE
3020 + * CWMAX1: AC_BK
3021 + * CWMAX1: AC_VI
3022 + * CWMAX1: AC_VO
3023 + */
3024 +#define WMM_CWMAX_CFG 0x021c
3025 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3026 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3027 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3028 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3029 +
3030 +/*
3031 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3032 + * AC0TXOP: AC_BK in unit of 32us
3033 + * AC1TXOP: AC_BE in unit of 32us
3034 + */
3035 +#define WMM_TXOP0_CFG 0x0220
3036 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3037 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3038 +
3039 +/*
3040 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3041 + * AC2TXOP: AC_VI in unit of 32us
3042 + * AC3TXOP: AC_VO in unit of 32us
3043 + */
3044 +#define WMM_TXOP1_CFG 0x0224
3045 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3046 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3047 +
3048 +/*
3049 + * RINGREG_DIFF
3050 + */
3051 +#define RINGREG_DIFF 0x0010
3052 +
3053 +/*
3054 + * GPIO_CTRL_CFG:
3055 + */
3056 +#define GPIO_CTRL_CFG 0x0228
3057 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3058 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3059 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3060 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3061 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3062 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3063 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3064 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3065 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3066 +
3067 +/*
3068 + * MCU_CMD_CFG
3069 + */
3070 +#define MCU_CMD_CFG 0x022c
3071 +
3072 +/*
3073 + * AC_BK register offsets
3074 + */
3075 +#define TX_BASE_PTR0 0x0230
3076 +#define TX_MAX_CNT0 0x0234
3077 +#define TX_CTX_IDX0 0x0238
3078 +#define TX_DTX_IDX0 0x023c
3079 +
3080 +/*
3081 + * AC_BE register offsets
3082 + */
3083 +#define TX_BASE_PTR1 0x0240
3084 +#define TX_MAX_CNT1 0x0244
3085 +#define TX_CTX_IDX1 0x0248
3086 +#define TX_DTX_IDX1 0x024c
3087 +
3088 +/*
3089 + * AC_VI register offsets
3090 + */
3091 +#define TX_BASE_PTR2 0x0250
3092 +#define TX_MAX_CNT2 0x0254
3093 +#define TX_CTX_IDX2 0x0258
3094 +#define TX_DTX_IDX2 0x025c
3095 +
3096 +/*
3097 + * AC_VO register offsets
3098 + */
3099 +#define TX_BASE_PTR3 0x0260
3100 +#define TX_MAX_CNT3 0x0264
3101 +#define TX_CTX_IDX3 0x0268
3102 +#define TX_DTX_IDX3 0x026c
3103 +
3104 +/*
3105 + * HCCA register offsets
3106 + */
3107 +#define TX_BASE_PTR4 0x0270
3108 +#define TX_MAX_CNT4 0x0274
3109 +#define TX_CTX_IDX4 0x0278
3110 +#define TX_DTX_IDX4 0x027c
3111 +
3112 +/*
3113 + * MGMT register offsets
3114 + */
3115 +#define TX_BASE_PTR5 0x0280
3116 +#define TX_MAX_CNT5 0x0284
3117 +#define TX_CTX_IDX5 0x0288
3118 +#define TX_DTX_IDX5 0x028c
3119 +
3120 +/*
3121 + * RX register offsets
3122 + */
3123 +#define RX_BASE_PTR 0x0290
3124 +#define RX_MAX_CNT 0x0294
3125 +#define RX_CRX_IDX 0x0298
3126 +#define RX_DRX_IDX 0x029c
3127 +
3128 +/*
3129 + * PBF_SYS_CTRL
3130 + * HOST_RAM_WRITE: enable Host program ram write selection
3131 + */
3132 +#define PBF_SYS_CTRL 0x0400
3133 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3134 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3135 +
3136 +/*
3137 + * PBF registers
3138 + * Most are for debug. Driver doesn't touch PBF register.
3139 + */
3140 +#define PBF_CFG 0x0408
3141 +#define PBF_MAX_PCNT 0x040c
3142 +#define PBF_CTRL 0x0410
3143 +#define PBF_INT_STA 0x0414
3144 +#define PBF_INT_ENA 0x0418
3145 +
3146 +/*
3147 + * BCN_OFFSET0:
3148 + */
3149 +#define BCN_OFFSET0 0x042c
3150 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3151 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3152 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3153 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3154 +
3155 +/*
3156 + * BCN_OFFSET1:
3157 + */
3158 +#define BCN_OFFSET1 0x0430
3159 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3160 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3161 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3162 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3163 +
3164 +/*
3165 + * PBF registers
3166 + * Most are for debug. Driver doesn't touch PBF register.
3167 + */
3168 +#define TXRXQ_PCNT 0x0438
3169 +#define PBF_DBG 0x043c
3170 +
3171 +/*
3172 + * MAC Control/Status Registers(CSR).
3173 + * Some values are set in TU, whereas 1 TU == 1024 us.
3174 + */
3175 +
3176 +/*
3177 + * MAC_CSR0: ASIC revision number.
3178 + * ASIC_REV: 0
3179 + * ASIC_VER: 2860
3180 + */
3181 +#define MAC_CSR0 0x1000
3182 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3183 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3184 +
3185 +/*
3186 + * MAC_SYS_CTRL:
3187 + */
3188 +#define MAC_SYS_CTRL 0x1004
3189 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3190 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3191 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3192 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3193 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3194 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3195 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3196 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3197 +
3198 +/*
3199 + * MAC_ADDR_DW0: STA MAC register 0
3200 + */
3201 +#define MAC_ADDR_DW0 0x1008
3202 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3203 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3204 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3205 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3206 +
3207 +/*
3208 + * MAC_ADDR_DW1: STA MAC register 1
3209 + * UNICAST_TO_ME_MASK:
3210 + * Used to mask off bits from byte 5 of the MAC address
3211 + * to determine the UNICAST_TO_ME bit for RX frames.
3212 + * The full mask is complemented by BSS_ID_MASK:
3213 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3214 + */
3215 +#define MAC_ADDR_DW1 0x100c
3216 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3217 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3218 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3219 +
3220 +/*
3221 + * MAC_BSSID_DW0: BSSID register 0
3222 + */
3223 +#define MAC_BSSID_DW0 0x1010
3224 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3225 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3226 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3227 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3228 +
3229 +/*
3230 + * MAC_BSSID_DW1: BSSID register 1
3231 + * BSS_ID_MASK:
3232 + * 0: 1-BSSID mode (BSS index = 0)
3233 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3234 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3235 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3236 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3237 + * BSSID. This will make sure that those bits will be ignored
3238 + * when determining the MY_BSS of RX frames.
3239 + */
3240 +#define MAC_BSSID_DW1 0x1014
3241 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3242 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3243 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3244 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3245 +
3246 +/*
3247 + * MAX_LEN_CFG: Maximum frame length register.
3248 + * MAX_MPDU: rt2860b max 16k bytes
3249 + * MAX_PSDU: Maximum PSDU length
3250 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3251 + */
3252 +#define MAX_LEN_CFG 0x1018
3253 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3254 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3255 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3256 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3257 +
3258 +/*
3259 + * BBP_CSR_CFG: BBP serial control register
3260 + * VALUE: Register value to program into BBP
3261 + * REG_NUM: Selected BBP register
3262 + * READ_CONTROL: 0 write BBP, 1 read BBP
3263 + * BUSY: ASIC is busy executing BBP commands
3264 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3265 + * BBP_RW_MODE: 0 serial, 1 paralell
3266 + */
3267 +#define BBP_CSR_CFG 0x101c
3268 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3269 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3270 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3271 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3272 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3273 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3274 +
3275 +/*
3276 + * RF_CSR_CFG0: RF control register
3277 + * REGID_AND_VALUE: Register value to program into RF
3278 + * BITWIDTH: Selected RF register
3279 + * STANDBYMODE: 0 high when standby, 1 low when standby
3280 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3281 + * BUSY: ASIC is busy executing RF commands
3282 + */
3283 +#define RF_CSR_CFG0 0x1020
3284 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3285 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3286 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3287 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3288 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3289 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3290 +
3291 +/*
3292 + * RF_CSR_CFG1: RF control register
3293 + * REGID_AND_VALUE: Register value to program into RF
3294 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3295 + * 0: 3 system clock cycle (37.5usec)
3296 + * 1: 5 system clock cycle (62.5usec)
3297 + */
3298 +#define RF_CSR_CFG1 0x1024
3299 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3300 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3301 +
3302 +/*
3303 + * RF_CSR_CFG2: RF control register
3304 + * VALUE: Register value to program into RF
3305 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3306 + * 0: 3 system clock cycle (37.5usec)
3307 + * 1: 5 system clock cycle (62.5usec)
3308 + */
3309 +#define RF_CSR_CFG2 0x1028
3310 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3311 +
3312 +/*
3313 + * LED_CFG: LED control
3314 + * color LED's:
3315 + * 0: off
3316 + * 1: blinking upon TX2
3317 + * 2: periodic slow blinking
3318 + * 3: always on
3319 + * LED polarity:
3320 + * 0: active low
3321 + * 1: active high
3322 + */
3323 +#define LED_CFG 0x102c
3324 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3325 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3326 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3327 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3328 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3329 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3330 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3331 +
3332 +/*
3333 + * XIFS_TIME_CFG: MAC timing
3334 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3335 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3336 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3337 + * when MAC doesn't reference BBP signal BBRXEND
3338 + * EIFS: unit 1us
3339 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3340 + *
3341 + */
3342 +#define XIFS_TIME_CFG 0x1100
3343 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3344 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3345 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3346 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3347 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3348 +
3349 +/*
3350 + * BKOFF_SLOT_CFG:
3351 + */
3352 +#define BKOFF_SLOT_CFG 0x1104
3353 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3354 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3355 +
3356 +/*
3357 + * NAV_TIME_CFG:
3358 + */
3359 +#define NAV_TIME_CFG 0x1108
3360 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3361 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3362 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3363 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3364 +
3365 +/*
3366 + * CH_TIME_CFG: count as channel busy
3367 + */
3368 +#define CH_TIME_CFG 0x110c
3369 +
3370 +/*
3371 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3372 + */
3373 +#define PBF_LIFE_TIMER 0x1110
3374 +
3375 +/*
3376 + * BCN_TIME_CFG:
3377 + * BEACON_INTERVAL: in unit of 1/16 TU
3378 + * TSF_TICKING: Enable TSF auto counting
3379 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3380 + * BEACON_GEN: Enable beacon generator
3381 + */
3382 +#define BCN_TIME_CFG 0x1114
3383 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3384 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3385 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3386 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3387 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3388 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3389 +
3390 +/*
3391 + * TBTT_SYNC_CFG:
3392 + */
3393 +#define TBTT_SYNC_CFG 0x1118
3394 +
3395 +/*
3396 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3397 + */
3398 +#define TSF_TIMER_DW0 0x111c
3399 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3400 +
3401 +/*
3402 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3403 + */
3404 +#define TSF_TIMER_DW1 0x1120
3405 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3406 +
3407 +/*
3408 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3409 + */
3410 +#define TBTT_TIMER 0x1124
3411 +
3412 +/*
3413 + * INT_TIMER_CFG:
3414 + */
3415 +#define INT_TIMER_CFG 0x1128
3416 +
3417 +/*
3418 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3419 + */
3420 +#define INT_TIMER_EN 0x112c
3421 +
3422 +/*
3423 + * CH_IDLE_STA: channel idle time
3424 + */
3425 +#define CH_IDLE_STA 0x1130
3426 +
3427 +/*
3428 + * CH_BUSY_STA: channel busy time
3429 + */
3430 +#define CH_BUSY_STA 0x1134
3431 +
3432 +/*
3433 + * MAC_STATUS_CFG:
3434 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3435 + * if 1 or higher one of the 2 registers is busy.
3436 + */
3437 +#define MAC_STATUS_CFG 0x1200
3438 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3439 +
3440 +/*
3441 + * PWR_PIN_CFG:
3442 + */
3443 +#define PWR_PIN_CFG 0x1204
3444 +
3445 +/*
3446 + * AUTOWAKEUP_CFG: Manual power control / status register
3447 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3448 + * AUTOWAKE: 0:sleep, 1:awake
3449 + */
3450 +#define AUTOWAKEUP_CFG 0x1208
3451 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3452 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3453 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3454 +
3455 +/*
3456 + * EDCA_AC0_CFG:
3457 + */
3458 +#define EDCA_AC0_CFG 0x1300
3459 +#define EDCA_AC0_CFG_AC_TX_OP FIELD32(0x000000ff)
3460 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3461 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3462 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3463 +
3464 +/*
3465 + * EDCA_AC1_CFG:
3466 + */
3467 +#define EDCA_AC1_CFG 0x1304
3468 +#define EDCA_AC1_CFG_AC_TX_OP FIELD32(0x000000ff)
3469 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3470 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3471 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3472 +
3473 +/*
3474 + * EDCA_AC2_CFG:
3475 + */
3476 +#define EDCA_AC2_CFG 0x1308
3477 +#define EDCA_AC2_CFG_AC_TX_OP FIELD32(0x000000ff)
3478 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3479 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3480 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3481 +
3482 +/*
3483 + * EDCA_AC3_CFG:
3484 + */
3485 +#define EDCA_AC3_CFG 0x130c
3486 +#define EDCA_AC3_CFG_AC_TX_OP FIELD32(0x000000ff)
3487 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3488 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3489 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3490 +
3491 +/*
3492 + * EDCA_TID_AC_MAP:
3493 + */
3494 +#define EDCA_TID_AC_MAP 0x1310
3495 +
3496 +/*
3497 + * TX_PWR_CFG_0:
3498 + */
3499 +#define TX_PWR_CFG_0 0x1314
3500 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3501 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3502 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3503 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3504 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3505 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3506 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3507 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3508 +
3509 +/*
3510 + * TX_PWR_CFG_1:
3511 + */
3512 +#define TX_PWR_CFG_1 0x1318
3513 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3514 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3515 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3516 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3517 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3518 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3519 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3520 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3521 +
3522 +/*
3523 + * TX_PWR_CFG_2:
3524 + */
3525 +#define TX_PWR_CFG_2 0x131c
3526 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3527 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3528 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3529 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3530 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3531 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3532 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3533 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3534 +
3535 +/*
3536 + * TX_PWR_CFG_3:
3537 + */
3538 +#define TX_PWR_CFG_3 0x1320
3539 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3540 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3541 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3542 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3543 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3544 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3545 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3546 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3547 +
3548 +/*
3549 + * TX_PWR_CFG_4:
3550 + */
3551 +#define TX_PWR_CFG_4 0x1324
3552 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3553 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3554 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3555 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3556 +
3557 +/*
3558 + * TX_PIN_CFG:
3559 + */
3560 +#define TX_PIN_CFG 0x1328
3561 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3562 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3563 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3564 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3565 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3566 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3567 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3568 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3569 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3570 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3571 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3572 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3573 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3574 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3575 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3576 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3577 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3578 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3579 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3580 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3581 +
3582 +/*
3583 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3584 + */
3585 +#define TX_BAND_CFG 0x132c
3586 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3587 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3588 +
3589 +/*
3590 + * TX_SW_CFG0:
3591 + */
3592 +#define TX_SW_CFG0 0x1330
3593 +
3594 +/*
3595 + * TX_SW_CFG1:
3596 + */
3597 +#define TX_SW_CFG1 0x1334
3598 +
3599 +/*
3600 + * TX_SW_CFG2:
3601 + */
3602 +#define TX_SW_CFG2 0x1338
3603 +
3604 +/*
3605 + * TXOP_THRES_CFG:
3606 + */
3607 +#define TXOP_THRES_CFG 0x133c
3608 +
3609 +/*
3610 + * TXOP_CTRL_CFG:
3611 + */
3612 +#define TXOP_CTRL_CFG 0x1340
3613 +
3614 +/*
3615 + * TX_RTS_CFG:
3616 + * RTS_THRES: unit:byte
3617 + * RTS_FBK_EN: enable rts rate fallback
3618 + */
3619 +#define TX_RTS_CFG 0x1344
3620 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3621 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3622 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3623 +
3624 +/*
3625 + * TX_TIMEOUT_CFG:
3626 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3627 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3628 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3629 + * it is recommended that:
3630 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3631 + */
3632 +#define TX_TIMEOUT_CFG 0x1348
3633 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3634 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3635 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3636 +
3637 +/*
3638 + * TX_RTY_CFG:
3639 + * SHORT_RTY_LIMIT: short retry limit
3640 + * LONG_RTY_LIMIT: long retry limit
3641 + * LONG_RTY_THRE: Long retry threshoold
3642 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3643 + * 0:expired by retry limit, 1: expired by mpdu life timer
3644 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3645 + * 0:expired by retry limit, 1: expired by mpdu life timer
3646 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3647 + */
3648 +#define TX_RTY_CFG 0x134c
3649 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3650 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3651 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3652 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3653 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3654 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3655 +
3656 +/*
3657 + * TX_LINK_CFG:
3658 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3659 + * MFB_ENABLE: TX apply remote MFB 1:enable
3660 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3661 + * 0: not apply remote remote unsolicit (MFS=7)
3662 + * TX_MRQ_EN: MCS request TX enable
3663 + * TX_RDG_EN: RDG TX enable
3664 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3665 + * REMOTE_MFB: remote MCS feedback
3666 + * REMOTE_MFS: remote MCS feedback sequence number
3667 + */
3668 +#define TX_LINK_CFG 0x1350
3669 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3670 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3671 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3672 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3673 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3674 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3675 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3676 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3677 +
3678 +/*
3679 + * HT_FBK_CFG0:
3680 + */
3681 +#define HT_FBK_CFG0 0x1354
3682 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3683 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3684 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3685 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3686 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3687 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3688 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3689 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3690 +
3691 +/*
3692 + * HT_FBK_CFG1:
3693 + */
3694 +#define HT_FBK_CFG1 0x1358
3695 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3696 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3697 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3698 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3699 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3700 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3701 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3702 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3703 +
3704 +/*
3705 + * LG_FBK_CFG0:
3706 + */
3707 +#define LG_FBK_CFG0 0x135c
3708 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3709 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3710 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3711 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3712 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3713 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3714 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
3715 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
3716 +
3717 +/*
3718 + * LG_FBK_CFG1:
3719 + */
3720 +#define LG_FBK_CFG1 0x1360
3721 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
3722 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
3723 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
3724 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
3725 +
3726 +/*
3727 + * CCK_PROT_CFG: CCK Protection
3728 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3729 + * PROTECT_CTRL: Protection control frame type for CCK TX
3730 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
3731 + * PROTECT_NAV: TXOP protection type for CCK TX
3732 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3733 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3734 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3735 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3736 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3737 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3738 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3739 + * RTS_TH_EN: RTS threshold enable on CCK TX
3740 + */
3741 +#define CCK_PROT_CFG 0x1364
3742 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3743 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3744 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3745 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3746 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3747 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3748 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3749 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3750 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3751 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3752 +
3753 +/*
3754 + * OFDM_PROT_CFG: OFDM Protection
3755 + */
3756 +#define OFDM_PROT_CFG 0x1368
3757 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3758 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3759 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3760 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3761 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3762 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3763 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3764 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3765 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3766 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3767 +
3768 +/*
3769 + * MM20_PROT_CFG: MM20 Protection
3770 + */
3771 +#define MM20_PROT_CFG 0x136c
3772 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3773 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3774 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3775 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3776 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3777 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3778 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3779 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3780 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3781 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3782 +
3783 +/*
3784 + * MM40_PROT_CFG: MM40 Protection
3785 + */
3786 +#define MM40_PROT_CFG 0x1370
3787 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3788 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3789 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3790 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3791 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3792 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3793 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3794 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3795 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3796 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3797 +
3798 +/*
3799 + * GF20_PROT_CFG: GF20 Protection
3800 + */
3801 +#define GF20_PROT_CFG 0x1374
3802 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3803 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3804 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3805 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3806 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3807 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3808 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3809 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3810 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3811 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3812 +
3813 +/*
3814 + * GF40_PROT_CFG: GF40 Protection
3815 + */
3816 +#define GF40_PROT_CFG 0x1378
3817 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3818 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3819 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3820 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3821 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3822 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3823 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3824 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3825 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3826 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3827 +
3828 +/*
3829 + * EXP_CTS_TIME:
3830 + */
3831 +#define EXP_CTS_TIME 0x137c
3832 +
3833 +/*
3834 + * EXP_ACK_TIME:
3835 + */
3836 +#define EXP_ACK_TIME 0x1380
3837 +
3838 +/*
3839 + * RX_FILTER_CFG: RX configuration register.
3840 + */
3841 +#define RX_FILTER_CFG 0x1400
3842 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
3843 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
3844 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
3845 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3846 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
3847 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
3848 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
3849 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
3850 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
3851 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
3852 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
3853 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
3854 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
3855 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
3856 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
3857 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
3858 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
3859 +
3860 +/*
3861 + * AUTO_RSP_CFG:
3862 + * AUTORESPONDER: 0: disable, 1: enable
3863 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3864 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3865 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3866 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3867 + * DUAL_CTS_EN: Power bit value in control frame
3868 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3869 + */
3870 +#define AUTO_RSP_CFG 0x1404
3871 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
3872 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
3873 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
3874 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
3875 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
3876 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
3877 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
3878 +
3879 +/*
3880 + * LEGACY_BASIC_RATE:
3881 + */
3882 +#define LEGACY_BASIC_RATE 0x1408
3883 +
3884 +/*
3885 + * HT_BASIC_RATE:
3886 + */
3887 +#define HT_BASIC_RATE 0x140c
3888 +
3889 +/*
3890 + * HT_CTRL_CFG:
3891 + */
3892 +#define HT_CTRL_CFG 0x1410
3893 +
3894 +/*
3895 + * SIFS_COST_CFG:
3896 + */
3897 +#define SIFS_COST_CFG 0x1414
3898 +
3899 +/*
3900 + * RX_PARSER_CFG:
3901 + * Set NAV for all received frames
3902 + */
3903 +#define RX_PARSER_CFG 0x1418
3904 +
3905 +/*
3906 + * TX_SEC_CNT0:
3907 + */
3908 +#define TX_SEC_CNT0 0x1500
3909 +
3910 +/*
3911 + * RX_SEC_CNT0:
3912 + */
3913 +#define RX_SEC_CNT0 0x1504
3914 +
3915 +/*
3916 + * CCMP_FC_MUTE:
3917 + */
3918 +#define CCMP_FC_MUTE 0x1508
3919 +
3920 +/*
3921 + * TXOP_HLDR_ADDR0:
3922 + */
3923 +#define TXOP_HLDR_ADDR0 0x1600
3924 +
3925 +/*
3926 + * TXOP_HLDR_ADDR1:
3927 + */
3928 +#define TXOP_HLDR_ADDR1 0x1604
3929 +
3930 +/*
3931 + * TXOP_HLDR_ET:
3932 + */
3933 +#define TXOP_HLDR_ET 0x1608
3934 +
3935 +/*
3936 + * QOS_CFPOLL_RA_DW0:
3937 + */
3938 +#define QOS_CFPOLL_RA_DW0 0x160c
3939 +
3940 +/*
3941 + * QOS_CFPOLL_RA_DW1:
3942 + */
3943 +#define QOS_CFPOLL_RA_DW1 0x1610
3944 +
3945 +/*
3946 + * QOS_CFPOLL_QC:
3947 + */
3948 +#define QOS_CFPOLL_QC 0x1614
3949 +
3950 +/*
3951 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
3952 + */
3953 +#define RX_STA_CNT0 0x1700
3954 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
3955 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
3956 +
3957 +/*
3958 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
3959 + */
3960 +#define RX_STA_CNT1 0x1704
3961 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
3962 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
3963 +
3964 +/*
3965 + * RX_STA_CNT2:
3966 + */
3967 +#define RX_STA_CNT2 0x1708
3968 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
3969 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
3970 +
3971 +/*
3972 + * TX_STA_CNT0: TX Beacon count
3973 + */
3974 +#define TX_STA_CNT0 0x170c
3975 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
3976 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
3977 +
3978 +/*
3979 + * TX_STA_CNT1: TX tx count
3980 + */
3981 +#define TX_STA_CNT1 0x1710
3982 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
3983 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
3984 +
3985 +/*
3986 + * TX_STA_CNT2: TX tx count
3987 + */
3988 +#define TX_STA_CNT2 0x1714
3989 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
3990 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
3991 +
3992 +/*
3993 + * TX_STA_FIFO: TX Result for specific PID status fifo register
3994 + */
3995 +#define TX_STA_FIFO 0x1718
3996 +#define TX_STA_FIFO_B_VALID FIELD32(0x00000001)
3997 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
3998 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
3999 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
4000 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
4001 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
4002 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
4003 +
4004 +/*
4005 + * TX_AGG_CNT: Debug counter
4006 + */
4007 +#define TX_AGG_CNT 0x171c
4008 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
4009 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
4010 +
4011 +/*
4012 + * TX_AGG_CNT0:
4013 + */
4014 +#define TX_AGG_CNT0 0x1720
4015 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
4016 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
4017 +
4018 +/*
4019 + * TX_AGG_CNT1:
4020 + */
4021 +#define TX_AGG_CNT1 0x1724
4022 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
4023 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
4024 +
4025 +/*
4026 + * TX_AGG_CNT2:
4027 + */
4028 +#define TX_AGG_CNT2 0x1728
4029 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
4030 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
4031 +
4032 +/*
4033 + * TX_AGG_CNT3:
4034 + */
4035 +#define TX_AGG_CNT3 0x172c
4036 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
4037 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
4038 +
4039 +/*
4040 + * TX_AGG_CNT4:
4041 + */
4042 +#define TX_AGG_CNT4 0x1730
4043 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
4044 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4045 +
4046 +/*
4047 + * TX_AGG_CNT5:
4048 + */
4049 +#define TX_AGG_CNT5 0x1734
4050 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4051 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4052 +
4053 +/*
4054 + * TX_AGG_CNT6:
4055 + */
4056 +#define TX_AGG_CNT6 0x1738
4057 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4058 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4059 +
4060 +/*
4061 + * TX_AGG_CNT7:
4062 + */
4063 +#define TX_AGG_CNT7 0x173c
4064 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4065 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4066 +
4067 +/*
4068 + * MPDU_DENSITY_CNT:
4069 + * TX_ZERO_DEL: TX zero length delimiter count
4070 + * RX_ZERO_DEL: RX zero length delimiter count
4071 + */
4072 +#define MPDU_DENSITY_CNT 0x1740
4073 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4074 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4075 +
4076 +/*
4077 + * Security key table memory, base address = 0x1800
4078 + */
4079 +struct hw_pairwise_ta_entry {
4080 + u8 address[6];
4081 + u8 reserved[2];
4082 +} __attribute__ ((packed));