f6fcbd6b5ae2d548ad298ce15cd7a7ea680aa968
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 403-ath9k-introduce-bus-specific-cache-size-routine.patch
1 From 1306e6b6d72b2bc0b91bcdd15b1d982965210bda Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Mon, 5 Jan 2009 10:57:42 +0100
4 Subject: [PATCH v2 03/11] ath9k: introduce bus specific cache size routine
5
6 The PCI specific bus_read_cachesize routine won't work on the AHB bus,
7 we have to replace it with a suitable one later.
8
9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10 Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
11 ---
12 drivers/net/wireless/ath9k/core.h | 10 ++++++++++
13 drivers/net/wireless/ath9k/main.c | 9 +++++++--
14 2 files changed, 17 insertions(+), 2 deletions(-)
15
16 --- a/drivers/net/wireless/ath9k/core.h
17 +++ b/drivers/net/wireless/ath9k/core.h
18 @@ -693,6 +693,10 @@ enum PROT_MODE {
19 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
20 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
21
22 +struct ath_bus_ops {
23 + void (*read_cachesize)(struct ath_softc *sc, int *csz);
24 +};
25 +
26 struct ath_softc {
27 struct ieee80211_hw *hw;
28 struct device *dev;
29 @@ -743,6 +747,7 @@ struct ath_softc {
30 #ifdef CONFIG_ATH9K_DEBUG
31 struct ath9k_debug sc_debug;
32 #endif
33 + struct ath_bus_ops *bus_ops;
34 };
35
36 int ath_reset(struct ath_softc *sc, bool retry_tx);
37 @@ -750,4 +755,9 @@ int ath_get_hal_qnum(u16 queue, struct a
38 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
39 int ath_cabq_update(struct ath_softc *);
40
41 +static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
42 +{
43 + sc->bus_ops->read_cachesize(sc, csz);
44 +}
45 +
46 #endif /* CORE_H */
47 --- a/drivers/net/wireless/ath9k/main.c
48 +++ b/drivers/net/wireless/ath9k/main.c
49 @@ -42,7 +42,7 @@ static void ath_detach(struct ath_softc
50
51 /* return bus cachesize in 4B word units */
52
53 -static void bus_read_cachesize(struct ath_softc *sc, int *csz)
54 +static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
55 {
56 u8 u8tmp;
57
58 @@ -1340,7 +1340,7 @@ static int ath_init(u16 devid, struct at
59 * Cache line size is used to size and align various
60 * structures used to communicate with the hardware.
61 */
62 - bus_read_cachesize(sc, &csz);
63 + ath_read_cachesize(sc, &csz);
64 /* XXX assert csz is non-zero */
65 sc->sc_cachelsz = csz << 2; /* convert to bytes */
66
67 @@ -2538,6 +2538,10 @@ ath_rf_name(u16 rf_version)
68 return "????";
69 }
70
71 +static struct ath_bus_ops ath_pci_bus_ops = {
72 + .read_cachesize = ath_pci_read_cachesize,
73 +};
74 +
75 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
76 {
77 void __iomem *mem;
78 @@ -2626,6 +2630,7 @@ static int ath_pci_probe(struct pci_dev
79 sc->hw = hw;
80 sc->dev = &pdev->dev;
81 sc->mem = mem;
82 + sc->bus_ops = &ath_pci_bus_ops;
83
84 if (ath_attach(id->device, sc) != 0) {
85 ret = -ENODEV;