ath9k: clean up pll code for ar9002 to fix 5/10 mhz pll settings for 5ghz
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 541-ath9k_pllclock_fix.patch
1 --- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
2 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
3 @@ -447,26 +447,27 @@ static void ar9002_olc_init(struct ath_h
4 static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
5 struct ath9k_channel *chan)
6 {
7 + int ref_div = 5;
8 + int pll_div = 0x2c;
9 u32 pll;
10
11 - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
12 + if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) {
13 + if (AR_SREV_9280_20(ah)) {
14 + ref_div = 10;
15 + pll_div = 0x50;
16 + } else {
17 + pll_div = 0x28;
18 + }
19 + }
20 +
21 + pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
22 + pll |= SM(pll_div, AR_RTC_9160_PLL_DIV);
23
24 if (chan && IS_CHAN_HALF_RATE(chan))
25 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
26 else if (chan && IS_CHAN_QUARTER_RATE(chan))
27 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
28
29 - if (chan && IS_CHAN_5GHZ(chan)) {
30 - if (IS_CHAN_A_FAST_CLOCK(ah, chan))
31 - pll = 0x142c;
32 - else if (AR_SREV_9280_20(ah))
33 - pll = 0x2850;
34 - else
35 - pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
36 - } else {
37 - pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
38 - }
39 -
40 return pll;
41 }
42