package/mac80211/patches/572-ath9k_cleanup_eeprom_code.patch

   1 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
   2 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
   3 @@ -2971,14 +2971,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(st
   4                 return (pBase->txrxMask >> 4) & 0xf;
   5         case EEP_RX_MASK:
   6                 return pBase->txrxMask & 0xf;
   7 -       case EEP_DRIVE_STRENGTH:
   8 -#define AR9300_EEP_BASE_DRIV_STRENGTH  0x1
   9 -               return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
  10 -       case EEP_INTERNAL_REGULATOR:
  11 -               /* Bit 4 is internal regulator flag */
  12 -               return (pBase->featureEnable & 0x10) >> 4;
  13 -       case EEP_SWREG:
  14 -               return le32_to_cpu(pBase->swreg);
  15         case EEP_PAPRD:
  16                 return !!(pBase->featureEnable & BIT(5));
  17         case EEP_CHAIN_MASK_REDUCE:
  18 @@ -2989,8 +2981,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(st
  19                 return eep->modalHeader5G.antennaGain;
  20         case EEP_ANTENNA_GAIN_2G:
  21                 return eep->modalHeader2G.antennaGain;
  22 -       case EEP_QUICK_DROP:
  23 -               return pBase->miscConfiguration & BIT(1);
  24         default:
  25                 return 0;
  26         }
  27 @@ -3503,19 +3493,20 @@ static int ath9k_hw_ar9300_get_eeprom_re
  28         return 0;
  29  }
  30
  31 -static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
  32 +static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
  33 +                                                          bool is2ghz)
  34  {
  35         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  36
  37         if (is2ghz)
  38 -               return eep->modalHeader2G.xpaBiasLvl;
  39 +               return &eep->modalHeader2G;
  40         else
  41 -               return eep->modalHeader5G.xpaBiasLvl;
  42 +               return &eep->modalHeader5G;
  43  }
  44
  45  static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
  46  {
  47 -       int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
  48 +       int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
  49
  50         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
  51                 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
  52 @@ -3531,57 +3522,26 @@ static void ar9003_hw_xpa_bias_level_app
  53         }
  54  }
  55
  56 -static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
  57 +static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
  58  {
  59 -       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  60 -       __le16 val;
  61 -
  62 -       if (is_2ghz)
  63 -               val = eep->modalHeader2G.switchcomspdt;
  64 -       else
  65 -               val = eep->modalHeader5G.switchcomspdt;
  66 -       return le16_to_cpu(val);
  67 +       return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
  68  }
  69
  70
  71  static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
  72  {
  73 -       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  74 -       __le32 val;
  75 -
  76 -       if (is2ghz)
  77 -               val = eep->modalHeader2G.antCtrlCommon;
  78 -       else
  79 -               val = eep->modalHeader5G.antCtrlCommon;
  80 -       return le32_to_cpu(val);
  81 +       return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
  82  }
  83
  84  static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
  85  {
  86 -       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  87 -       __le32 val;
  88 -
  89 -       if (is2ghz)
  90 -               val = eep->modalHeader2G.antCtrlCommon2;
  91 -       else
  92 -               val = eep->modalHeader5G.antCtrlCommon2;
  93 -       return le32_to_cpu(val);
  94 +       return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
  95  }
  96
  97 -static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
  98 -                                       int chain,
  99 +static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
 100                                         bool is2ghz)
 101  {
 102 -       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 103 -       __le16 val = 0;
 104 -
 105 -       if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
 106 -               if (is2ghz)
 107 -                       val = eep->modalHeader2G.antCtrlChain[chain];
 108 -               else
 109 -                       val = eep->modalHeader5G.antCtrlChain[chain];
 110 -       }
 111 -
 112 +       __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
 113         return le16_to_cpu(val);
 114  }
 115
 116 @@ -3691,11 +3651,12 @@ static void ar9003_hw_ant_ctrl_apply(str
 117
 118  static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
 119  {
 120 +       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 121 +       struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
 122         int drive_strength;
 123         unsigned long reg;
 124
 125 -       drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
 126 -
 127 +       drive_strength = pBase->miscConfiguration & BIT(0);
 128         if (!drive_strength)
 129                 return;
 130
 131 @@ -3825,11 +3786,11 @@ static bool is_pmu_set(struct ath_hw *ah
 132
 133  void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
 134  {
 135 -       int internal_regulator =
 136 -               ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
 137 +       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 138 +       struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
 139         u32 reg_val;
 140
 141 -       if (internal_regulator) {
 142 +       if (pBase->featureEnable & BIT(4)) {
 143                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
 144                         int reg_pmu_set;
 145
 146 @@ -3873,11 +3834,11 @@ void ar9003_hw_internal_regulator_apply(
 147                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
 148                                 return;
 149                 } else if (AR_SREV_9462(ah)) {
 150 -                       reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
 151 +                       reg_val = le32_to_cpu(pBase->swreg);
 152                         REG_WRITE(ah, AR_PHY_PMU1, reg_val);
 153                 } else {
 154                         /* Internal regulator is ON. Write swreg register. */
 155 -                       reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
 156 +                       reg_val = le32_to_cpu(pBase->swreg);
 157                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
 158                                   REG_READ(ah, AR_RTC_REG_CONTROL1) &
 159                                   (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
 160 @@ -3931,10 +3892,11 @@ static void ar9003_hw_apply_tuning_caps(
 161  static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
 162  {
 163         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 164 -       int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
 165 +       struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
 166 +       int quick_drop;
 167         s32 t[3], f[3] = {5180, 5500, 5785};
 168
 169 -       if (!quick_drop)
 170 +       if (!(pBase->miscConfiguration & BIT(1)))
 171                 return;
 172
 173         if (freq < 4000)
 174 @@ -3948,13 +3910,11 @@ static void ar9003_hw_quick_drop_apply(s
 175         REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
 176  }
 177
 178 -static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
 179 +static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
 180  {
 181 -       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 182         u32 value;
 183
 184 -       value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
 185 -                               eep->modalHeader5G.txEndToXpaOff;
 186 +       value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
 187
 188         REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
 189                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
 190 @@ -3962,7 +3922,7 @@ static void ar9003_hw_txend_to_xpa_off_a
 191                       AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
 192  }
 193
 194 -static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is_2ghz)
 195 +static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
 196  {
 197         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 198         u8 xpa_ctl;
 199 @@ -3973,23 +3933,22 @@ static void ar9003_hw_xpa_timing_control
 200         if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
 201                 return;
 202
 203 -       if (is_2ghz) {
 204 -               xpa_ctl = eep->modalHeader2G.txFrameToXpaOn;
 205 +       xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
 206 +       if (is2ghz)
 207                 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
 208                               AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
 209 -       } else {
 210 -               xpa_ctl = eep->modalHeader5G.txFrameToXpaOn;
 211 +       else
 212                 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
 213                               AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
 214 -       }
 215  }
 216
 217  static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
 218                                              struct ath9k_channel *chan)
 219  {
 220 -       ar9003_hw_xpa_timing_control_apply(ah, IS_CHAN_2GHZ(chan));
 221 -       ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
 222 -       ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
 223 +       bool is2ghz = IS_CHAN_2GHZ(chan);
 224 +       ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
 225 +       ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
 226 +       ar9003_hw_ant_ctrl_apply(ah, is2ghz);
 227         ar9003_hw_drive_strength_apply(ah);
 228         ar9003_hw_atten_apply(ah, chan);
 229         ar9003_hw_quick_drop_apply(ah, chan->channel);
 230 @@ -3997,7 +3956,7 @@ static void ath9k_hw_ar9300_set_board_va
 231                 ar9003_hw_internal_regulator_apply(ah);
 232         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
 233                 ar9003_hw_apply_tuning_caps(ah);
 234 -       ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
 235 +       ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
 236  }
 237
 238  static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
 239 @@ -5133,14 +5092,9 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath
 240         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
 241  }
 242
 243 -u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
 244 +u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
 245  {
 246 -       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 247 -
 248 -       if (is_2ghz)
 249 -               return eep->modalHeader2G.spurChans;
 250 -       else
 251 -               return eep->modalHeader5G.spurChans;
 252 +       return ar9003_modal_header(ah, is2ghz)->spurChans;
 253  }
 254
 255  unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
 256 --- a/drivers/net/wireless/ath/ath9k/eeprom.h
 257 +++ b/drivers/net/wireless/ath/ath9k/eeprom.h
 258 @@ -241,16 +241,12 @@ enum eeprom_param {
 259         EEP_TEMPSENSE_SLOPE,
 260         EEP_TEMPSENSE_SLOPE_PAL_ON,
 261         EEP_PWR_TABLE_OFFSET,
 262 -       EEP_DRIVE_STRENGTH,
 263 -       EEP_INTERNAL_REGULATOR,
 264 -       EEP_SWREG,
 265         EEP_PAPRD,
 266         EEP_MODAL_VER,
 267         EEP_ANT_DIV_CTL1,
 268         EEP_CHAIN_MASK_REDUCE,
 269         EEP_ANTENNA_GAIN_2G,
 270         EEP_ANTENNA_GAIN_5G,
 271 -       EEP_QUICK_DROP
 272  };
 273
 274  enum ar5416_rates {