mac80211: merge an idle handling fix (fixes ath9k_htc client mode), refresh patches
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 616-rt2x00-support-rt5350.patch
1 --- a/drivers/net/wireless/rt2x00/rt2800.h
2 +++ b/drivers/net/wireless/rt2x00/rt2800.h
3 @@ -69,6 +69,7 @@
4 #define RF3322 0x000c
5 #define RF3053 0x000d
6 #define RF3290 0x3290
7 +#define RF5350 0x5350
8 #define RF5360 0x5360
9 #define RF5370 0x5370
10 #define RF5372 0x5372
11 --- a/drivers/net/wireless/rt2x00/rt2800lib.c
12 +++ b/drivers/net/wireless/rt2x00/rt2800lib.c
13 @@ -2138,6 +2138,15 @@ static void rt2800_config_channel_rf53xx
14 if (rf->channel <= 14) {
15 int idx = rf->channel-1;
16
17 + if (rt2x00_rt(rt2x00dev, RT5350)) {
18 + static const char r59_non_bt[] = {0x0b, 0x0b,
19 + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
20 + 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
21 +
22 + rt2800_rfcsr_write(rt2x00dev, 59,
23 + r59_non_bt[idx]);
24 + }
25 +
26 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
27 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
28 /* r55/r59 value array of channel 1~14 */
29 @@ -2219,6 +2228,7 @@ static void rt2800_config_channel(struct
30 case RF3322:
31 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
32 break;
33 + case RF5350:
34 case RF5360:
35 case RF5370:
36 case RF5372:
37 @@ -2232,6 +2242,7 @@ static void rt2800_config_channel(struct
38
39 if (rt2x00_rf(rt2x00dev, RF3290) ||
40 rt2x00_rf(rt2x00dev, RF3322) ||
41 + rt2x00_rf(rt2x00dev, RF5350) ||
42 rt2x00_rf(rt2x00dev, RF5360) ||
43 rt2x00_rf(rt2x00dev, RF5370) ||
44 rt2x00_rf(rt2x00dev, RF5372) ||
45 @@ -2362,7 +2373,8 @@ static void rt2800_config_channel(struct
46 /*
47 * Clear update flag
48 */
49 - if (rt2x00_rt(rt2x00dev, RT3352)) {
50 + if (rt2x00_rt(rt2x00dev, RT3352) ||
51 + rt2x00_rt(rt2x00dev, RT5350)) {
52 rt2800_bbp_read(rt2x00dev, 49, &bbp);
53 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
54 rt2800_bbp_write(rt2x00dev, 49, bbp);
55 @@ -2801,6 +2813,7 @@ void rt2800_vco_calibration(struct rt2x0
56 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
57 break;
58 case RF3290:
59 + case RF5350:
60 case RF5360:
61 case RF5370:
62 case RF5372:
63 @@ -3125,7 +3138,8 @@ static int rt2800_init_registers(struct
64 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
65 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
66 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
67 - } else if (rt2x00_rt(rt2x00dev, RT5390) ||
68 + } else if (rt2x00_rt(rt2x00dev, RT5350) ||
69 + rt2x00_rt(rt2x00dev, RT5390) ||
70 rt2x00_rt(rt2x00dev, RT5392)) {
71 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
72 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
73 @@ -3507,6 +3521,10 @@ static int rt2800_init_bbp(struct rt2x00
74 rt2800_bbp_write(rt2x00dev, 4, 0x50);
75 }
76
77 + if (rt2x00_rt(rt2x00dev, RT5350)) {
78 + rt2800_bbp_write(rt2x00dev, 4, 0x50);
79 + }
80 +
81 if (rt2x00_rt(rt2x00dev, RT3290) ||
82 rt2x00_rt(rt2x00dev, RT5390) ||
83 rt2x00_rt(rt2x00dev, RT5392)) {
84 @@ -3519,11 +3537,13 @@ static int rt2800_init_bbp(struct rt2x00
85 rt2x00_rt(rt2x00dev, RT3290) ||
86 rt2x00_rt(rt2x00dev, RT3352) ||
87 rt2x00_rt(rt2x00dev, RT3572) ||
88 + rt2x00_rt(rt2x00dev, RT5350) ||
89 rt2x00_rt(rt2x00dev, RT5390) ||
90 rt2x00_rt(rt2x00dev, RT5392))
91 rt2800_bbp_write(rt2x00dev, 31, 0x08);
92
93 - if (rt2x00_rt(rt2x00dev, RT3352))
94 + if (rt2x00_rt(rt2x00dev, RT3352) ||
95 + rt2x00_rt(rt2x00dev, RT5350))
96 rt2800_bbp_write(rt2x00dev, 47, 0x48);
97
98 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
99 @@ -3531,6 +3551,7 @@ static int rt2800_init_bbp(struct rt2x00
100
101 if (rt2x00_rt(rt2x00dev, RT3290) ||
102 rt2x00_rt(rt2x00dev, RT3352) ||
103 + rt2x00_rt(rt2x00dev, RT5350) ||
104 rt2x00_rt(rt2x00dev, RT5390) ||
105 rt2x00_rt(rt2x00dev, RT5392))
106 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
107 @@ -3540,6 +3561,7 @@ static int rt2800_init_bbp(struct rt2x00
108 rt2800_bbp_write(rt2x00dev, 73, 0x12);
109 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
110 rt2x00_rt(rt2x00dev, RT3352) ||
111 + rt2x00_rt(rt2x00dev, RT5350) ||
112 rt2x00_rt(rt2x00dev, RT5390) ||
113 rt2x00_rt(rt2x00dev, RT5392)) {
114 rt2800_bbp_write(rt2x00dev, 69, 0x12);
115 @@ -3576,7 +3598,8 @@ static int rt2800_init_bbp(struct rt2x00
116 rt2800_bbp_write(rt2x00dev, 79, 0x18);
117 rt2800_bbp_write(rt2x00dev, 80, 0x09);
118 rt2800_bbp_write(rt2x00dev, 81, 0x33);
119 - } else if (rt2x00_rt(rt2x00dev, RT3352)) {
120 + } else if (rt2x00_rt(rt2x00dev, RT3352) ||
121 + rt2x00_rt(rt2x00dev, RT5350)) {
122 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
123 rt2800_bbp_write(rt2x00dev, 80, 0x08);
124 rt2800_bbp_write(rt2x00dev, 81, 0x37);
125 @@ -3586,6 +3609,7 @@ static int rt2800_init_bbp(struct rt2x00
126
127 rt2800_bbp_write(rt2x00dev, 82, 0x62);
128 if (rt2x00_rt(rt2x00dev, RT3290) ||
129 + rt2x00_rt(rt2x00dev, RT5350) ||
130 rt2x00_rt(rt2x00dev, RT5390) ||
131 rt2x00_rt(rt2x00dev, RT5392))
132 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
133 @@ -3595,6 +3619,7 @@ static int rt2800_init_bbp(struct rt2x00
134 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
135 rt2800_bbp_write(rt2x00dev, 84, 0x19);
136 else if (rt2x00_rt(rt2x00dev, RT3290) ||
137 + rt2x00_rt(rt2x00dev, RT5350) ||
138 rt2x00_rt(rt2x00dev, RT5390) ||
139 rt2x00_rt(rt2x00dev, RT5392))
140 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
141 @@ -3603,6 +3628,7 @@ static int rt2800_init_bbp(struct rt2x00
142
143 if (rt2x00_rt(rt2x00dev, RT3290) ||
144 rt2x00_rt(rt2x00dev, RT3352) ||
145 + rt2x00_rt(rt2x00dev, RT5350) ||
146 rt2x00_rt(rt2x00dev, RT5390) ||
147 rt2x00_rt(rt2x00dev, RT5392))
148 rt2800_bbp_write(rt2x00dev, 86, 0x38);
149 @@ -3617,6 +3643,7 @@ static int rt2800_init_bbp(struct rt2x00
150
151 if (rt2x00_rt(rt2x00dev, RT3290) ||
152 rt2x00_rt(rt2x00dev, RT3352) ||
153 + rt2x00_rt(rt2x00dev, RT5350) ||
154 rt2x00_rt(rt2x00dev, RT5390) ||
155 rt2x00_rt(rt2x00dev, RT5392))
156 rt2800_bbp_write(rt2x00dev, 92, 0x02);
157 @@ -3635,6 +3662,7 @@ static int rt2800_init_bbp(struct rt2x00
158 rt2x00_rt(rt2x00dev, RT3290) ||
159 rt2x00_rt(rt2x00dev, RT3352) ||
160 rt2x00_rt(rt2x00dev, RT3572) ||
161 + rt2x00_rt(rt2x00dev, RT5350) ||
162 rt2x00_rt(rt2x00dev, RT5390) ||
163 rt2x00_rt(rt2x00dev, RT5392) ||
164 rt2800_is_305x_soc(rt2x00dev))
165 @@ -3644,6 +3672,7 @@ static int rt2800_init_bbp(struct rt2x00
166
167 if (rt2x00_rt(rt2x00dev, RT3290) ||
168 rt2x00_rt(rt2x00dev, RT3352) ||
169 + rt2x00_rt(rt2x00dev, RT5350) ||
170 rt2x00_rt(rt2x00dev, RT5390) ||
171 rt2x00_rt(rt2x00dev, RT5392))
172 rt2800_bbp_write(rt2x00dev, 104, 0x92);
173 @@ -3654,13 +3683,15 @@ static int rt2800_init_bbp(struct rt2x00
174 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
175 else if (rt2x00_rt(rt2x00dev, RT3352))
176 rt2800_bbp_write(rt2x00dev, 105, 0x34);
177 - else if (rt2x00_rt(rt2x00dev, RT5390) ||
178 + else if (rt2x00_rt(rt2x00dev, RT5350) ||
179 + rt2x00_rt(rt2x00dev, RT5390) ||
180 rt2x00_rt(rt2x00dev, RT5392))
181 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
182 else
183 rt2800_bbp_write(rt2x00dev, 105, 0x05);
184
185 if (rt2x00_rt(rt2x00dev, RT3290) ||
186 + rt2x00_rt(rt2x00dev, RT5350) ||
187 rt2x00_rt(rt2x00dev, RT5390))
188 rt2800_bbp_write(rt2x00dev, 106, 0x03);
189 else if (rt2x00_rt(rt2x00dev, RT3352))
190 @@ -3670,11 +3701,13 @@ static int rt2800_init_bbp(struct rt2x00
191 else
192 rt2800_bbp_write(rt2x00dev, 106, 0x35);
193
194 - if (rt2x00_rt(rt2x00dev, RT3352))
195 + if (rt2x00_rt(rt2x00dev, RT3352) ||
196 + rt2x00_rt(rt2x00dev, RT5350))
197 rt2800_bbp_write(rt2x00dev, 120, 0x50);
198
199 if (rt2x00_rt(rt2x00dev, RT3290) ||
200 rt2x00_rt(rt2x00dev, RT3352) ||
201 + rt2x00_rt(rt2x00dev, RT5350) ||
202 rt2x00_rt(rt2x00dev, RT5390) ||
203 rt2x00_rt(rt2x00dev, RT5392))
204 rt2800_bbp_write(rt2x00dev, 128, 0x12);
205 @@ -3684,13 +3717,15 @@ static int rt2800_init_bbp(struct rt2x00
206 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
207 }
208
209 - if (rt2x00_rt(rt2x00dev, RT3352))
210 + if (rt2x00_rt(rt2x00dev, RT3352) ||
211 + rt2x00_rt(rt2x00dev, RT5350))
212 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
213
214 if (rt2x00_rt(rt2x00dev, RT3071) ||
215 rt2x00_rt(rt2x00dev, RT3090) ||
216 rt2x00_rt(rt2x00dev, RT3390) ||
217 rt2x00_rt(rt2x00dev, RT3572) ||
218 + rt2x00_rt(rt2x00dev, RT5350) ||
219 rt2x00_rt(rt2x00dev, RT5390) ||
220 rt2x00_rt(rt2x00dev, RT5392)) {
221 rt2800_bbp_read(rt2x00dev, 138, &value);
222 @@ -3727,7 +3762,8 @@ static int rt2800_init_bbp(struct rt2x00
223 rt2800_bbp_write(rt2x00dev, 3, value);
224 }
225
226 - if (rt2x00_rt(rt2x00dev, RT3352)) {
227 + if (rt2x00_rt(rt2x00dev, RT3352) ||
228 + rt2x00_rt(rt2x00dev, RT5350)) {
229 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
230 /* Set ITxBF timeout to 0x9c40=1000msec */
231 rt2800_bbp_write(rt2x00dev, 179, 0x02);
232 @@ -3749,6 +3785,14 @@ static int rt2800_init_bbp(struct rt2x00
233 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
234 }
235
236 + if (rt2x00_rt(rt2x00dev, RT5350)) {
237 + rt2800_bbp_write(rt2x00dev, 150, 0x40); /* Antenna Software OFDM */
238 + rt2800_bbp_write(rt2x00dev, 151, 0x30); /* Antenna Software CCK */
239 + rt2800_bbp_write(rt2x00dev, 152, 0xa3);
240 + rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
241 + }
242 +
243 +
244 if (rt2x00_rt(rt2x00dev, RT5390) ||
245 rt2x00_rt(rt2x00dev, RT5392)) {
246 int ant, div_mode;
247 @@ -4143,6 +4187,76 @@ static void rt2800_init_rfcsr_3572(struc
248 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
249 }
250
251 +static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
252 +{
253 + rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
254 + rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
255 + rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
256 + rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
257 + rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
258 + rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
259 + rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
260 + rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
261 + rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
262 + rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
263 + rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
264 + rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
265 + rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
266 + if(rt2x00dev->spec.clk_is_20mhz)
267 + rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
268 + else
269 + rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
270 + rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
271 + rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
272 + rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
273 + rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
274 + rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
275 + rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
276 + rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
277 + rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
278 + rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
279 + rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
280 + rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
281 + rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
282 + rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
283 + rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
284 + rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
285 + rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
286 + rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
287 + rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
288 + rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
289 + rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
290 + rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
291 + rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
292 + rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
293 + rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
294 + rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
295 + rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
296 + rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
297 + rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
298 + rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
299 + rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
300 + rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
301 + rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
302 + rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
303 + rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
304 + rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
305 + rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
306 + rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
307 + rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
308 + rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
309 + rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
310 + rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
311 + rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
312 + rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
313 + rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
314 + rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
315 + rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
316 + rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
317 + rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
318 + rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
319 +}
320 +
321 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
322 {
323 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
324 @@ -4305,6 +4419,7 @@ static int rt2800_init_rfcsr(struct rt2x
325 !rt2x00_rt(rt2x00dev, RT3352) &&
326 !rt2x00_rt(rt2x00dev, RT3390) &&
327 !rt2x00_rt(rt2x00dev, RT3572) &&
328 + !rt2x00_rt(rt2x00dev, RT5350) &&
329 !rt2x00_rt(rt2x00dev, RT5390) &&
330 !rt2x00_rt(rt2x00dev, RT5392) &&
331 !rt2800_is_305x_soc(rt2x00dev))
332 @@ -4355,6 +4470,9 @@ static int rt2800_init_rfcsr(struct rt2x
333 case RT3572:
334 rt2800_init_rfcsr_3572(rt2x00dev);
335 break;
336 + case RT5350:
337 + rt2800_init_rfcsr_5350(rt2x00dev);
338 + break;
339 case RT5390:
340 rt2800_init_rfcsr_5390(rt2x00dev);
341 break;
342 @@ -4751,6 +4869,12 @@ static int rt2800_validate_eeprom(struct
343 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
344 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
345 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
346 + } else if(rt2x00_rt(rt2x00dev, RT5350)) {
347 + rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 1);
348 + rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
349 + rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF3320);
350 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
351 + EEPROM(rt2x00dev, "rt5350: Ant: 0x%04x\n", word);
352 }
353
354 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
355 @@ -4875,6 +4999,8 @@ static int rt2800_init_eeprom(struct rt2
356 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
357 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
358 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
359 + else if(rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5350)
360 + value = RF5350;
361 else
362 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
363
364 @@ -4892,6 +5018,7 @@ static int rt2800_init_eeprom(struct rt2
365 case RT3352:
366 case RT3390:
367 case RT3572:
368 + case RT5350:
369 case RT5390:
370 case RT5392:
371 break;
372 @@ -4913,6 +5040,7 @@ static int rt2800_init_eeprom(struct rt2
373 case RF3290:
374 case RF3320:
375 case RF3322:
376 + case RF5350:
377 case RF5360:
378 case RF5370:
379 case RF5372:
380 @@ -5275,7 +5403,8 @@ static int rt2800_probe_hw_mode(struct r
381 rt2x00_rf(rt2x00dev, RF5392)) {
382 spec->num_channels = 14;
383 spec->channels = rf_vals_3x;
384 - } else if (rt2x00_rf(rt2x00dev, RF3322)) {
385 + } else if (rt2x00_rf(rt2x00dev, RF3322) ||
386 + rt2x00_rf(rt2x00dev, RF5350)) {
387 spec->num_channels = 14;
388 if (spec->clk_is_20mhz)
389 spec->channels = rf_vals_xtal20mhz_3x;
390 @@ -5364,6 +5493,7 @@ static int rt2800_probe_hw_mode(struct r
391 case RF3290:
392 case RF5360:
393 case RF5370:
394 + case RF5350:
395 case RF5372:
396 case RF5390:
397 case RF5392:
398 --- a/drivers/net/wireless/rt2x00/rt2x00.h
399 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
400 @@ -192,6 +192,7 @@ struct rt2x00_chip {
401 #define RT3572 0x3572
402 #define RT3593 0x3593
403 #define RT3883 0x3883 /* WSOC */
404 +#define RT5350 0x5350 /* WSOC 2.4GHz */
405 #define RT5390 0x5390 /* 2.4GHz */
406 #define RT5392 0x5392 /* 2.4GHz */
407