Add rt2x00-mac80211 snapshot (#1916)
[openwrt/svn-archive/archive.git] / package / rt2x00 / src / rt2400pci.h
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2400pci
23 Abstract: Data structures and registers for the rt2400pci module.
24 Supported chipsets: RT2460.
25 */
26
27 #ifndef RT2400PCI_H
28 #define RT2400PCI_H
29
30 /*
31 * RF chip defines.
32 */
33 #define RF2420 0x0000
34 #define RF2421 0x0001
35
36 /*
37 * Max RSSI value, required for RSSI <-> dBm conversion.
38 */
39 #define MAX_RX_SSI 100
40 #define MAX_RX_NOISE -110
41
42 /*
43 * Register layout information.
44 */
45 #define CSR_REG_BASE 0x0000
46 #define CSR_REG_SIZE 0x014c
47 #define EEPROM_BASE 0x0000
48 #define EEPROM_SIZE 0x0100
49 #define BBP_SIZE 0x0020
50
51 /*
52 * Control/Status Registers(CSR).
53 * Some values are set in TU, whereas 1 TU == 1024 us.
54 */
55
56 /*
57 * CSR0: ASIC revision number.
58 */
59 #define CSR0 0x0000
60
61 /*
62 * CSR1: System control register.
63 * SOFT_RESET: Software reset, 1: reset, 0: normal.
64 * BBP_RESET: Hardware reset, 1: reset, 0, release.
65 * HOST_READY: Host ready after initialization.
66 */
67 #define CSR1 0x0004
68 #define CSR1_SOFT_RESET FIELD32(0x00000001)
69 #define CSR1_BBP_RESET FIELD32(0x00000002)
70 #define CSR1_HOST_READY FIELD32(0x00000004)
71
72 /*
73 * CSR2: System admin status register (invalid).
74 */
75 #define CSR2 0x0008
76
77 /*
78 * CSR3: STA MAC address register 0.
79 */
80 #define CSR3 0x000c
81 #define CSR3_BYTE0 FIELD32(0x000000ff)
82 #define CSR3_BYTE1 FIELD32(0x0000ff00)
83 #define CSR3_BYTE2 FIELD32(0x00ff0000)
84 #define CSR3_BYTE3 FIELD32(0xff000000)
85
86 /*
87 * CSR4: STA MAC address register 1.
88 */
89 #define CSR4 0x0010
90 #define CSR4_BYTE4 FIELD32(0x000000ff)
91 #define CSR4_BYTE5 FIELD32(0x0000ff00)
92
93 /*
94 * CSR5: BSSID register 0.
95 */
96 #define CSR5 0x0014
97 #define CSR5_BYTE0 FIELD32(0x000000ff)
98 #define CSR5_BYTE1 FIELD32(0x0000ff00)
99 #define CSR5_BYTE2 FIELD32(0x00ff0000)
100 #define CSR5_BYTE3 FIELD32(0xff000000)
101
102 /*
103 * CSR6: BSSID register 1.
104 */
105 #define CSR6 0x0018
106 #define CSR6_BYTE4 FIELD32(0x000000ff)
107 #define CSR6_BYTE5 FIELD32(0x0000ff00)
108
109 /*
110 * CSR7: Interrupt source register.
111 * Write 1 to clear interrupt.
112 * TBCN_EXPIRE: Beacon timer expired interrupt.
113 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
114 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
115 * TXDONE_TXRING: Tx ring transmit done interrupt.
116 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
117 * TXDONE_PRIORING: Priority ring transmit done interrupt.
118 * RXDONE: Receive done interrupt.
119 */
120 #define CSR7 0x001c
121 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
122 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
123 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
124 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
125 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
126 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
127 #define CSR7_RXDONE FIELD32(0x00000040)
128
129 /*
130 * CSR8: Interrupt mask register.
131 * Write 1 to mask interrupt.
132 * TBCN_EXPIRE: Beacon timer expired interrupt.
133 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
134 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
135 * TXDONE_TXRING: Tx ring transmit done interrupt.
136 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
137 * TXDONE_PRIORING: Priority ring transmit done interrupt.
138 * RXDONE: Receive done interrupt.
139 */
140 #define CSR8 0x0020
141 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
142 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
143 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
144 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
145 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
146 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
147 #define CSR8_RXDONE FIELD32(0x00000040)
148
149 /*
150 * CSR9: Maximum frame length register.
151 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
152 */
153 #define CSR9 0x0024
154 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
155
156 /*
157 * CSR11: Back-off control register.
158 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
159 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
160 * SLOT_TIME: Slot time, default is 20us for 802.11b.
161 * LONG_RETRY: Long retry count.
162 * SHORT_RETRY: Short retry count.
163 */
164 #define CSR11 0x002c
165 #define CSR11_CWMIN FIELD32(0x0000000f)
166 #define CSR11_CWMAX FIELD32(0x000000f0)
167 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
168 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
169 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
170
171 /*
172 * CSR12: Synchronization configuration register 0.
173 * All units in 1/16 TU.
174 * BEACON_INTERVAL: Beacon interval, default is 100 TU.
175 * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
176 */
177 #define CSR12 0x0030
178 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
179 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
180
181 /*
182 * CSR13: Synchronization configuration register 1.
183 * All units in 1/16 TU.
184 * ATIMW_DURATION: Atim window duration.
185 * CFP_PERIOD: Cfp period, default is 0 TU.
186 */
187 #define CSR13 0x0034
188 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
189 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
190
191 /*
192 * CSR14: Synchronization control register.
193 * TSF_COUNT: Enable tsf auto counting.
194 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
195 * TBCN: Enable tbcn with reload value.
196 * TCFP: Enable tcfp & cfp / cp switching.
197 * TATIMW: Enable tatimw & atim window switching.
198 * BEACON_GEN: Enable beacon generator.
199 * CFP_COUNT_PRELOAD: Cfp count preload value.
200 * TBCM_PRELOAD: Tbcn preload value in units of 64us.
201 */
202 #define CSR14 0x0038
203 #define CSR14_TSF_COUNT FIELD32(0x00000001)
204 #define CSR14_TSF_SYNC FIELD32(0x00000006)
205 #define CSR14_TBCN FIELD32(0x00000008)
206 #define CSR14_TCFP FIELD32(0x00000010)
207 #define CSR14_TATIMW FIELD32(0x00000020)
208 #define CSR14_BEACON_GEN FIELD32(0x00000040)
209 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
210 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
211
212 /*
213 * CSR15: Synchronization status register.
214 * CFP: ASIC is in contention-free period.
215 * ATIMW: ASIC is in ATIM window.
216 * BEACON_SENT: Beacon is send.
217 */
218 #define CSR15 0x003c
219 #define CSR15_CFP FIELD32(0x00000001)
220 #define CSR15_ATIMW FIELD32(0x00000002)
221 #define CSR15_BEACON_SENT FIELD32(0x00000004)
222
223 /*
224 * CSR16: TSF timer register 0.
225 */
226 #define CSR16 0x0040
227 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
228
229 /*
230 * CSR17: TSF timer register 1.
231 */
232 #define CSR17 0x0044
233 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
234
235 /*
236 * CSR18: IFS timer register 0.
237 * SIFS: Sifs, default is 10 us.
238 * PIFS: Pifs, default is 30 us.
239 */
240 #define CSR18 0x0048
241 #define CSR18_SIFS FIELD32(0x0000ffff)
242 #define CSR18_PIFS FIELD32(0xffff0000)
243
244 /*
245 * CSR19: IFS timer register 1.
246 * DIFS: Difs, default is 50 us.
247 * EIFS: Eifs, default is 364 us.
248 */
249 #define CSR19 0x004c
250 #define CSR19_DIFS FIELD32(0x0000ffff)
251 #define CSR19_EIFS FIELD32(0xffff0000)
252
253 /*
254 * CSR20: Wakeup timer register.
255 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
256 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
257 * AUTOWAKE: Enable auto wakeup / sleep mechanism.
258 */
259 #define CSR20 0x0050
260 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
261 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
262 #define CSR20_AUTOWAKE FIELD32(0x01000000)
263
264 /*
265 * CSR21: EEPROM control register.
266 * RELOAD: Write 1 to reload eeprom content.
267 * TYPE_93C46: 1: 93c46, 0:93c66.
268 */
269 #define CSR21 0x0054
270 #define CSR21_RELOAD FIELD32(0x00000001)
271 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
272 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
273 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
274 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
275 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
276
277 /*
278 * CSR22: CFP control register.
279 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
280 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
281 */
282 #define CSR22 0x0058
283 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
284 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
285
286 /*
287 * Transmit related CSRs.
288 * Some values are set in TU, whereas 1 TU == 1024 us.
289 */
290
291 /*
292 * TXCSR0: TX Control Register.
293 * KICK_TX: Kick tx ring.
294 * KICK_ATIM: Kick atim ring.
295 * KICK_PRIO: Kick priority ring.
296 * ABORT: Abort all transmit related ring operation.
297 */
298 #define TXCSR0 0x0060
299 #define TXCSR0_KICK_TX FIELD32(0x00000001)
300 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
301 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
302 #define TXCSR0_ABORT FIELD32(0x00000008)
303
304 /*
305 * TXCSR1: TX Configuration Register.
306 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
307 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
308 * TSF_OFFSET: Insert tsf offset.
309 * AUTORESPONDER: Enable auto responder which include ack & cts.
310 */
311 #define TXCSR1 0x0064
312 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
313 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
314 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
315 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
316
317 /*
318 * TXCSR2: Tx descriptor configuration register.
319 * TXD_SIZE: Tx descriptor size, default is 48.
320 * NUM_TXD: Number of tx entries in ring.
321 * NUM_ATIM: Number of atim entries in ring.
322 * NUM_PRIO: Number of priority entries in ring.
323 */
324 #define TXCSR2 0x0068
325 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
326 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
327 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
328 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
329
330 /*
331 * TXCSR3: TX Ring Base address register.
332 */
333 #define TXCSR3 0x006c
334 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
335
336 /*
337 * TXCSR4: TX Atim Ring Base address register.
338 */
339 #define TXCSR4 0x0070
340 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
341
342 /*
343 * TXCSR5: TX Prio Ring Base address register.
344 */
345 #define TXCSR5 0x0074
346 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
347
348 /*
349 * TXCSR6: Beacon Base address register.
350 */
351 #define TXCSR6 0x0078
352 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
353
354 /*
355 * TXCSR7: Auto responder control register.
356 * AR_POWERMANAGEMENT: Auto responder power management bit.
357 */
358 #define TXCSR7 0x007c
359 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
360
361 /*
362 * Receive related CSRs.
363 * Some values are set in TU, whereas 1 TU == 1024 us.
364 */
365
366 /*
367 * RXCSR0: RX Control Register.
368 * DISABLE_RX: Disable rx engine.
369 * DROP_CRC: Drop crc error.
370 * DROP_PHYSICAL: Drop physical error.
371 * DROP_CONTROL: Drop control frame.
372 * DROP_NOT_TO_ME: Drop not to me unicast frame.
373 * DROP_TODS: Drop frame tods bit is true.
374 * DROP_VERSION_ERROR: Drop version error frame.
375 * PASS_CRC: Pass all packets with crc attached.
376 */
377 #define RXCSR0 0x0080
378 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
379 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
380 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
381 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
382 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
383 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
384 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
385 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
386
387 /*
388 * RXCSR1: RX descriptor configuration register.
389 * RXD_SIZE: Rx descriptor size, default is 32b.
390 * NUM_RXD: Number of rx entries in ring.
391 */
392 #define RXCSR1 0x0084
393 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
394 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
395
396 /*
397 * RXCSR2: RX Ring base address register.
398 */
399 #define RXCSR2 0x0088
400 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
401
402 /*
403 * RXCSR3: BBP ID register for Rx operation.
404 * BBP_ID#: BBP register # id.
405 * BBP_ID#_VALID: BBP register # id is valid or not.
406 */
407 #define RXCSR3 0x0090
408 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
409 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
410 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
411 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
412 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
413 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
414 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
415 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
416
417 /*
418 * RXCSR4: BBP ID register for Rx operation.
419 * BBP_ID#: BBP register # id.
420 * BBP_ID#_VALID: BBP register # id is valid or not.
421 */
422 #define RXCSR4 0x0094
423 #define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
424 #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
425 #define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
426 #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
427
428 /*
429 * ARCSR0: Auto Responder PLCP config register 0.
430 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
431 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
432 */
433 #define ARCSR0 0x0098
434 #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
435 #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
436 #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
437 #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
438
439 /*
440 * ARCSR1: Auto Responder PLCP config register 1.
441 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
442 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
443 */
444 #define ARCSR1 0x009c
445 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
446 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
447 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
448 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
449
450 /*
451 * Miscellaneous Registers.
452 * Some values are set in TU, whereas 1 TU == 1024 us.
453 */
454
455 /*
456 * PCICSR: PCI control register.
457 * BIG_ENDIAN: 1: big endian, 0: little endian.
458 * RX_TRESHOLD: Rx threshold in dw to start pci access
459 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
460 * TX_TRESHOLD: Tx threshold in dw to start pci access
461 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
462 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
463 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
464 */
465 #define PCICSR 0x008c
466 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
467 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
468 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
469 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
470 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
471
472 /*
473 * CNT0: FCS error count.
474 * FCS_ERROR: FCS error count, cleared when read.
475 */
476 #define CNT0 0x00a0
477 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
478
479 /*
480 * Statistic Register.
481 * CNT1: PLCP error count.
482 * CNT2: Long error count.
483 * CNT3: CCA false alarm count.
484 * CNT4: Rx FIFO overflow count.
485 * CNT5: Tx FIFO underrun count.
486 */
487 #define TIMECSR2 0x00a8
488 #define CNT1 0x00ac
489 #define CNT2 0x00b0
490 #define TIMECSR3 0x00b4
491 #define CNT3 0x00b8
492 #define CNT4 0x00bc
493 #define CNT5 0x00c0
494
495 /*
496 * Baseband Control Register.
497 */
498
499 /*
500 * PWRCSR0: Power mode configuration register.
501 */
502 #define PWRCSR0 0x00c4
503
504 /*
505 * Power state transition time registers.
506 */
507 #define PSCSR0 0x00c8
508 #define PSCSR1 0x00cc
509 #define PSCSR2 0x00d0
510 #define PSCSR3 0x00d4
511
512 /*
513 * PWRCSR1: Manual power control / status register.
514 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
515 * SET_STATE: Set state. Write 1 to trigger, self cleared.
516 * BBP_DESIRE_STATE: BBP desired state.
517 * RF_DESIRE_STATE: RF desired state.
518 * BBP_CURR_STATE: BBP current state.
519 * RF_CURR_STATE: RF current state.
520 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
521 */
522 #define PWRCSR1 0x00d8
523 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
524 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
525 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
526 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
527 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
528 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
529
530 /*
531 * TIMECSR: Timer control register.
532 * US_COUNT: 1 us timer count in units of clock cycles.
533 * US_64_COUNT: 64 us timer count in units of 1 us timer.
534 * BEACON_EXPECT: Beacon expect window.
535 */
536 #define TIMECSR 0x00dc
537 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
538 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
539 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
540
541 /*
542 * MACCSR0: MAC configuration register 0.
543 */
544 #define MACCSR0 0x00e0
545
546
547 /*
548 * MACCSR1: MAC configuration register 1.
549 * KICK_RX: Kick one-shot rx in one-shot rx mode.
550 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
551 * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
552 * AUTO_TXBBP: Auto tx logic access bbp control register.
553 * AUTO_RXBBP: Auto rx logic access bbp control register.
554 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
555 * INTERSIL_IF: Intersil if calibration pin.
556 */
557 #define MACCSR1 0x00e4
558 #define MACCSR1_KICK_RX FIELD32(0x00000001)
559 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
560 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
561 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
562 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
563 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
564 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
565
566 /*
567 * RALINKCSR: Ralink Rx auto-reset BBCR.
568 * AR_BBP_DATA#: Auto reset BBP register # data.
569 * AR_BBP_ID#: Auto reset BBP register # id.
570 */
571 #define RALINKCSR 0x00e8
572 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
573 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
574 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
575 #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
576
577 /*
578 * BCNCSR: Beacon interval control register.
579 * CHANGE: Write one to change beacon interval.
580 * DELTATIME: The delta time value.
581 * NUM_BEACON: Number of beacon according to mode.
582 * MODE: Please refer to asic specs.
583 * PLUS: Plus or minus delta time value.
584 */
585 #define BCNCSR 0x00ec
586 #define BCNCSR_CHANGE FIELD32(0x00000001)
587 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
588 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
589 #define BCNCSR_MODE FIELD32(0x00006000)
590 #define BCNCSR_PLUS FIELD32(0x00008000)
591
592 /*
593 * BBP / RF / IF Control Register.
594 */
595
596 /*
597 * BBPCSR: BBP serial control register.
598 * VALUE: Register value to program into BBP.
599 * REGNUM: Selected BBP register.
600 * BUSY: 1: asic is busy execute BBP programming.
601 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
602 */
603 #define BBPCSR 0x00f0
604 #define BBPCSR_VALUE FIELD32(0x000000ff)
605 #define BBPCSR_REGNUM FIELD32(0x00007f00)
606 #define BBPCSR_BUSY FIELD32(0x00008000)
607 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
608
609 /*
610 * RFCSR: RF serial control register.
611 * VALUE: Register value + id to program into rf/if.
612 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
613 * IF_SELECT: Chip to program: 0: rf, 1: if.
614 * PLL_LD: Rf pll_ld status.
615 * BUSY: 1: asic is busy execute rf programming.
616 */
617 #define RFCSR 0x00f4
618 #define RFCSR_VALUE FIELD32(0x00ffffff)
619 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
620 #define RFCSR_IF_SELECT FIELD32(0x20000000)
621 #define RFCSR_PLL_LD FIELD32(0x40000000)
622 #define RFCSR_BUSY FIELD32(0x80000000)
623
624 /*
625 * LEDCSR: LED control register.
626 * ON_PERIOD: On period, default 70ms.
627 * OFF_PERIOD: Off period, default 30ms.
628 * LINK: 0: linkoff, 1: linkup.
629 * ACTIVITY: 0: idle, 1: active.
630 */
631 #define LEDCSR 0x00f8
632 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
633 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
634 #define LEDCSR_LINK FIELD32(0x00010000)
635 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
636
637 /*
638 * ASIC pointer information.
639 * RXPTR: Current RX ring address.
640 * TXPTR: Current Tx ring address.
641 * PRIPTR: Current Priority ring address.
642 * ATIMPTR: Current ATIM ring address.
643 */
644 #define RXPTR 0x0100
645 #define TXPTR 0x0104
646 #define PRIPTR 0x0108
647 #define ATIMPTR 0x010c
648
649 /*
650 * GPIO and others.
651 */
652
653 /*
654 * GPIOCSR: GPIO control register.
655 */
656 #define GPIOCSR 0x0120
657 #define GPIOCSR_BIT0 FIELD32(0x00000001)
658 #define GPIOCSR_BIT1 FIELD32(0x00000002)
659 #define GPIOCSR_BIT2 FIELD32(0x00000004)
660 #define GPIOCSR_BIT3 FIELD32(0x00000008)
661 #define GPIOCSR_BIT4 FIELD32(0x00000010)
662 #define GPIOCSR_BIT5 FIELD32(0x00000020)
663 #define GPIOCSR_BIT6 FIELD32(0x00000040)
664 #define GPIOCSR_BIT7 FIELD32(0x00000080)
665
666 /*
667 * BBPPCSR: BBP Pin control register.
668 */
669 #define BBPPCSR 0x0124
670
671 /*
672 * BCNCSR1: Tx BEACON offset time control register.
673 * PRELOAD: Beacon timer offset in units of usec.
674 */
675 #define BCNCSR1 0x0130
676 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
677
678 /*
679 * MACCSR2: TX_PE to RX_PE turn-around time control register
680 * DELAY: RX_PE low width, in units of pci clock cycle.
681 */
682 #define MACCSR2 0x0134
683 #define MACCSR2_DELAY FIELD32(0x000000ff)
684
685 /*
686 * ARCSR2: 1 Mbps ACK/CTS PLCP.
687 */
688 #define ARCSR2 0x013c
689 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
690 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
691 #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
692 #define ARCSR2_LENGTH FIELD32(0xffff0000)
693
694 /*
695 * ARCSR3: 2 Mbps ACK/CTS PLCP.
696 */
697 #define ARCSR3 0x0140
698 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
699 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
700 #define ARCSR3_LENGTH FIELD32(0xffff0000)
701
702 /*
703 * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
704 */
705 #define ARCSR4 0x0144
706 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
707 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
708 #define ARCSR4_LENGTH FIELD32(0xffff0000)
709
710 /*
711 * ARCSR5: 11 Mbps ACK/CTS PLCP.
712 */
713 #define ARCSR5 0x0148
714 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
715 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
716 #define ARCSR5_LENGTH FIELD32(0xffff0000)
717
718 /*
719 * RF registers
720 */
721 #define RF1_TUNER FIELD32(0x00020000)
722 #define RF3_TUNER FIELD32(0x00000100)
723 #define RF3_TXPOWER FIELD32(0x00003e00)
724
725 /*
726 * EEPROM content.
727 * The wordsize of the EEPROM is 16 bits.
728 */
729
730 /*
731 * HW MAC address.
732 */
733 #define EEPROM_MAC_ADDR_0 0x0002
734 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
735 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
736 #define EEPROM_MAC_ADDR1 0x0003
737 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
738 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
739 #define EEPROM_MAC_ADDR_2 0x0004
740 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
741 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
742
743 /*
744 * EEPROM antenna.
745 * ANTENNA_NUM: Number of antenna's.
746 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
747 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
748 * RF_TYPE: Rf_type of this adapter.
749 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
750 * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
751 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
752 */
753 #define EEPROM_ANTENNA 0x0b
754 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
755 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
756 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
757 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040)
758 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180)
759 #define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
760 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
761
762 /*
763 * EEPROM BBP.
764 */
765 #define EEPROM_BBP_START 0x0c
766 #define EEPROM_BBP_SIZE 7
767 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
768 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
769
770 /*
771 * EEPROM TXPOWER
772 */
773 #define EEPROM_TXPOWER_START 0x13
774 #define EEPROM_TXPOWER_SIZE 7
775 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
776 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
777
778 /*
779 * BBP content.
780 * The wordsize of the BBP is 8 bits.
781 */
782
783 /*
784 * BBP_R1: TX antenna control
785 */
786 #define BBP_R1_TX_ANTENNA FIELD8(0x03)
787
788 /*
789 * BBP_R4: RX antenna control
790 */
791 #define BBP_R4_RX_ANTENNA FIELD8(0x06)
792
793 /*
794 * DMA descriptor defines.
795 */
796 #define TXD_DESC_SIZE ( 8 * sizeof(struct data_desc) )
797 #define RXD_DESC_SIZE ( 8 * sizeof(struct data_desc) )
798
799 /*
800 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
801 */
802
803 /*
804 * Word0
805 */
806 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
807 #define TXD_W0_VALID FIELD32(0x00000002)
808 #define TXD_W0_RESULT FIELD32(0x0000001c)
809 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
810 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
811 #define TXD_W0_ACK FIELD32(0x00000200)
812 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
813 #define TXD_W0_RTS FIELD32(0x00000800)
814 #define TXD_W0_IFS FIELD32(0x00006000)
815 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
816 #define TXD_W0_AGC FIELD32(0x00ff0000)
817 #define TXD_W0_R2 FIELD32(0xff000000)
818
819 /*
820 * Word1
821 */
822 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
823
824 /*
825 * Word2
826 */
827 #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
828 #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
829
830 /*
831 * Word3 & 4: PLCP information
832 */
833 #define TXD_W3_PLCP_SIGNAL FIELD32(0x0000ffff)
834 #define TXD_W3_PLCP_SERVICE FIELD32(0xffff0000)
835 #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x0000ffff)
836 #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0xffff0000)
837
838 /*
839 * Word5
840 */
841 #define TXD_W5_BBCR4 FIELD32(0x0000ffff)
842 #define TXD_W5_AGC_REG FIELD32(0x007f0000)
843 #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
844 #define TXD_W5_XXX_REG FIELD32(0x7f000000)
845 #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
846
847 /*
848 * Word6
849 */
850 #define TXD_W6_SK_BUFF FIELD32(0xffffffff)
851
852 /*
853 * Word7
854 */
855 #define TXD_W7_RESERVED FIELD32(0xffffffff)
856
857 /*
858 * RX descriptor format for RX Ring.
859 */
860
861 /*
862 * Word0
863 */
864 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
865 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
866 #define RXD_W0_MULTICAST FIELD32(0x00000004)
867 #define RXD_W0_BROADCAST FIELD32(0x00000008)
868 #define RXD_W0_MY_BSS FIELD32(0x00000010)
869 #define RXD_W0_CRC FIELD32(0x00000020)
870 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
871 #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
872
873 /*
874 * Word1
875 */
876 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
877
878 /*
879 * Word2
880 */
881 #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
882 #define RXD_W2_SIGNAL FIELD32(0x00ff0000)
883 #define RXD_W2_RSSI FIELD32(0xff000000)
884
885 /*
886 * Word3
887 */
888 #define RXD_W3_BBR2 FIELD32(0x000000ff)
889 #define RXD_W3_BBR3 FIELD32(0x0000ff00)
890 #define RXD_W3_BBR4 FIELD32(0x00ff0000)
891 #define RXD_W3_BBR5 FIELD32(0xff000000)
892
893 /*
894 * Word4
895 */
896 #define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
897
898 /*
899 * Word5 & 6 & 7: Reserved
900 */
901 #define RXD_W5_RESERVED FIELD32(0xffffffff)
902 #define RXD_W6_RESERVED FIELD32(0xffffffff)
903 #define RXD_W7_RESERVED FIELD32(0xffffffff)
904
905 /*
906 * Macro's for converting txpower from EEPROM to dscape value
907 * and from dscape value to register value.
908 * NOTE: Logics in rt2400pci for txpower are reversed
909 * compared to the other rt2x00 drivers. A higher txpower
910 * value means that the txpower must be lowered. This is
911 * important when converting the value coming from the
912 * dscape stack to the rt2400 acceptable value.
913 */
914 #define MIN_TXPOWER 31
915 #define MAX_TXPOWER 62
916 #define DEFAULT_TXPOWER 39
917
918 #define TXPOWER_FROM_DEV(__txpower) \
919 ({ \
920 ((__txpower) > MAX_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \
921 ((__txpower) < MIN_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \
922 (((__txpower) - MAX_TXPOWER) + MIN_TXPOWER); \
923 })
924
925 #define TXPOWER_TO_DEV(__txpower) \
926 ({ \
927 (__txpower) += MIN_TXPOWER; \
928 ((__txpower) <= MIN_TXPOWER) ? MAX_TXPOWER : \
929 (((__txpower) >= MAX_TXPOWER) ? MIN_TXPOWER : \
930 (MAX_TXPOWER - ((__txpower) - MIN_TXPOWER))); \
931 })
932
933 #endif /* RT2400PCI_H */