Add rt2x00-mac80211 snapshot (#1916)
[openwrt/svn-archive/archive.git] / package / rt2x00 / src / rt2500pci.h
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: Data structures and registers for the rt2500pci module.
24 Supported chipsets: RT2560.
25 */
26
27 #ifndef RT2500PCI_H
28 #define RT2500PCI_H
29
30 /*
31 * RF chip defines.
32 */
33 #define RF2522 0x0000
34 #define RF2523 0x0001
35 #define RF2524 0x0002
36 #define RF2525 0x0003
37 #define RF2525E 0x0004
38 #define RF5222 0x0010
39
40 /*
41 * RT2560 version
42 */
43 #define RT2560_VERSION_B 2
44 #define RT2560_VERSION_C 3
45 #define RT2560_VERSION_D 4
46
47 /*
48 * Max RSSI value, required for RSSI <-> dBm conversion.
49 */
50 #define MAX_RX_SSI 121
51 #define MAX_RX_NOISE -110
52
53 /*
54 * Register layout information.
55 */
56 #define CSR_REG_BASE 0x0000
57 #define CSR_REG_SIZE 0x0174
58 #define EEPROM_BASE 0x0000
59 #define EEPROM_SIZE 0x0200
60 #define BBP_SIZE 0x0040
61
62 /*
63 * Control/Status Registers(CSR).
64 * Some values are set in TU, whereas 1 TU == 1024 us.
65 */
66
67 /*
68 * CSR0: ASIC revision number.
69 */
70 #define CSR0 0x0000
71
72 /*
73 * CSR1: System control register.
74 * SOFT_RESET: Software reset, 1: reset, 0: normal.
75 * BBP_RESET: Hardware reset, 1: reset, 0, release.
76 * HOST_READY: Host ready after initialization.
77 */
78 #define CSR1 0x0004
79 #define CSR1_SOFT_RESET FIELD32(0x00000001)
80 #define CSR1_BBP_RESET FIELD32(0x00000002)
81 #define CSR1_HOST_READY FIELD32(0x00000004)
82
83 /*
84 * CSR2: System admin status register (invalid).
85 */
86 #define CSR2 0x0008
87
88 /*
89 * CSR3: STA MAC address register 0.
90 */
91 #define CSR3 0x000c
92 #define CSR3_BYTE0 FIELD32(0x000000ff)
93 #define CSR3_BYTE1 FIELD32(0x0000ff00)
94 #define CSR3_BYTE2 FIELD32(0x00ff0000)
95 #define CSR3_BYTE3 FIELD32(0xff000000)
96
97 /*
98 * CSR4: STA MAC address register 1.
99 */
100 #define CSR4 0x0010
101 #define CSR4_BYTE4 FIELD32(0x000000ff)
102 #define CSR4_BYTE5 FIELD32(0x0000ff00)
103
104 /*
105 * CSR5: BSSID register 0.
106 */
107 #define CSR5 0x0014
108 #define CSR5_BYTE0 FIELD32(0x000000ff)
109 #define CSR5_BYTE1 FIELD32(0x0000ff00)
110 #define CSR5_BYTE2 FIELD32(0x00ff0000)
111 #define CSR5_BYTE3 FIELD32(0xff000000)
112
113 /*
114 * CSR6: BSSID register 1.
115 */
116 #define CSR6 0x0018
117 #define CSR6_BYTE4 FIELD32(0x000000ff)
118 #define CSR6_BYTE5 FIELD32(0x0000ff00)
119
120 /*
121 * CSR7: Interrupt source register.
122 * Write 1 to clear.
123 * TBCN_EXPIRE: Beacon timer expired interrupt.
124 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
125 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
126 * TXDONE_TXRING: Tx ring transmit done interrupt.
127 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
128 * TXDONE_PRIORING: Priority ring transmit done interrupt.
129 * RXDONE: Receive done interrupt.
130 * DECRYPTION_DONE: Decryption done interrupt.
131 * ENCRYPTION_DONE: Encryption done interrupt.
132 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
133 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
134 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
135 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
136 * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
137 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
138 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
139 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
140 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
141 * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
142 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
143
144 */
145 #define CSR7 0x001c
146 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
147 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
148 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
149 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
150 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
151 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
152 #define CSR7_RXDONE FIELD32(0x00000040)
153 #define CSR7_DECRYPTION_DONE FIELD32(0x00000080)
154 #define CSR7_ENCRYPTION_DONE FIELD32(0x00000100)
155 #define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200)
156 #define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400)
157 #define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
158 #define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
159 #define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
160 #define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000)
161 #define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000)
162 #define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
163 #define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
164 #define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
165 #define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
166
167 /*
168 * CSR8: Interrupt mask register.
169 * Write 1 to mask interrupt.
170 * TBCN_EXPIRE: Beacon timer expired interrupt.
171 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
172 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
173 * TXDONE_TXRING: Tx ring transmit done interrupt.
174 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
175 * TXDONE_PRIORING: Priority ring transmit done interrupt.
176 * RXDONE: Receive done interrupt.
177 * DECRYPTION_DONE: Decryption done interrupt.
178 * ENCRYPTION_DONE: Encryption done interrupt.
179 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
180 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
181 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
182 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
183 * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
184 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
185 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
186 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
187 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
188 * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
189 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
190 */
191 #define CSR8 0x0020
192 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
193 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
194 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
195 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
196 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
197 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
198 #define CSR8_RXDONE FIELD32(0x00000040)
199 #define CSR8_DECRYPTION_DONE FIELD32(0x00000080)
200 #define CSR8_ENCRYPTION_DONE FIELD32(0x00000100)
201 #define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200)
202 #define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400)
203 #define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
204 #define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
205 #define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
206 #define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000)
207 #define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000)
208 #define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
209 #define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
210 #define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
211 #define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
212
213 /*
214 * CSR9: Maximum frame length register.
215 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
216 */
217 #define CSR9 0x0024
218 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
219
220 /*
221 * SECCSR0: WEP control register.
222 * KICK_DECRYPT: Kick decryption engine, self-clear.
223 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
224 * DESC_ADDRESS: Descriptor physical address of frame.
225 */
226 #define SECCSR0 0x0028
227 #define SECCSR0_KICK_DECRYPT FIELD32(0x00000001)
228 #define SECCSR0_ONE_SHOT FIELD32(0x00000002)
229 #define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc)
230
231 /*
232 * CSR11: Back-off control register.
233 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
234 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
235 * SLOT_TIME: Slot time, default is 20us for 802.11b
236 * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD.
237 * LONG_RETRY: Long retry count.
238 * SHORT_RETRY: Short retry count.
239 */
240 #define CSR11 0x002c
241 #define CSR11_CWMIN FIELD32(0x0000000f)
242 #define CSR11_CWMAX FIELD32(0x000000f0)
243 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
244 #define CSR11_CW_SELECT FIELD32(0x00002000)
245 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
246 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
247
248 /*
249 * CSR12: Synchronization configuration register 0.
250 * All units in 1/16 TU.
251 * BEACON_INTERVAL: Beacon interval, default is 100 TU.
252 * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU.
253 */
254 #define CSR12 0x0030
255 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
256 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
257
258 /*
259 * CSR13: Synchronization configuration register 1.
260 * All units in 1/16 TU.
261 * ATIMW_DURATION: Atim window duration.
262 * CFP_PERIOD: Cfp period, default is 0 TU.
263 */
264 #define CSR13 0x0034
265 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
266 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
267
268 /*
269 * CSR14: Synchronization control register.
270 * TSF_COUNT: Enable tsf auto counting.
271 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
272 * TBCN: Enable tbcn with reload value.
273 * TCFP: Enable tcfp & cfp / cp switching.
274 * TATIMW: Enable tatimw & atim window switching.
275 * BEACON_GEN: Enable beacon generator.
276 * CFP_COUNT_PRELOAD: Cfp count preload value.
277 * TBCM_PRELOAD: Tbcn preload value in units of 64us.
278 */
279 #define CSR14 0x0038
280 #define CSR14_TSF_COUNT FIELD32(0x00000001)
281 #define CSR14_TSF_SYNC FIELD32(0x00000006)
282 #define CSR14_TBCN FIELD32(0x00000008)
283 #define CSR14_TCFP FIELD32(0x00000010)
284 #define CSR14_TATIMW FIELD32(0x00000020)
285 #define CSR14_BEACON_GEN FIELD32(0x00000040)
286 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
287 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
288
289 /*
290 * CSR15: Synchronization status register.
291 * CFP: ASIC is in contention-free period.
292 * ATIMW: ASIC is in ATIM window.
293 * BEACON_SENT: Beacon is send.
294 */
295 #define CSR15 0x003c
296 #define CSR15_CFP FIELD32(0x00000001)
297 #define CSR15_ATIMW FIELD32(0x00000002)
298 #define CSR15_BEACON_SENT FIELD32(0x00000004)
299
300 /*
301 * CSR16: TSF timer register 0.
302 */
303 #define CSR16 0x0040
304 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
305
306 /*
307 * CSR17: TSF timer register 1.
308 */
309 #define CSR17 0x0044
310 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
311
312 /*
313 * CSR18: IFS timer register 0.
314 * SIFS: Sifs, default is 10 us.
315 * PIFS: Pifs, default is 30 us.
316 */
317 #define CSR18 0x0048
318 #define CSR18_SIFS FIELD32(0x000001ff)
319 #define CSR18_PIFS FIELD32(0x001f0000)
320
321 /*
322 * CSR19: IFS timer register 1.
323 * DIFS: Difs, default is 50 us.
324 * EIFS: Eifs, default is 364 us.
325 */
326 #define CSR19 0x004c
327 #define CSR19_DIFS FIELD32(0x0000ffff)
328 #define CSR19_EIFS FIELD32(0xffff0000)
329
330 /*
331 * CSR20: Wakeup timer register.
332 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
333 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
334 * AUTOWAKE: Enable auto wakeup / sleep mechanism.
335 */
336 #define CSR20 0x0050
337 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
338 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
339 #define CSR20_AUTOWAKE FIELD32(0x01000000)
340
341 /*
342 * CSR21: EEPROM control register.
343 * RELOAD: Write 1 to reload eeprom content.
344 * TYPE_93C46: 1: 93c46, 0:93c66.
345 */
346 #define CSR21 0x0054
347 #define CSR21_RELOAD FIELD32(0x00000001)
348 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
349 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
350 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
351 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
352 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
353
354 /*
355 * CSR22: CFP control register.
356 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
357 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
358 */
359 #define CSR22 0x0058
360 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
361 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
362
363 /*
364 * Transmit related CSRs.
365 * Some values are set in TU, whereas 1 TU == 1024 us.
366 */
367
368 /*
369 * TXCSR0: TX Control Register.
370 * KICK_TX: Kick tx ring.
371 * KICK_ATIM: Kick atim ring.
372 * KICK_PRIO: Kick priority ring.
373 * ABORT: Abort all transmit related ring operation.
374 */
375 #define TXCSR0 0x0060
376 #define TXCSR0_KICK_TX FIELD32(0x00000001)
377 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
378 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
379 #define TXCSR0_ABORT FIELD32(0x00000008)
380
381 /*
382 * TXCSR1: TX Configuration Register.
383 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
384 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
385 * TSF_OFFSET: Insert tsf offset.
386 * AUTORESPONDER: Enable auto responder which include ack & cts.
387 */
388 #define TXCSR1 0x0064
389 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
390 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
391 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
392 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
393
394 /*
395 * TXCSR2: Tx descriptor configuration register.
396 * TXD_SIZE: Tx descriptor size, default is 48.
397 * NUM_TXD: Number of tx entries in ring.
398 * NUM_ATIM: Number of atim entries in ring.
399 * NUM_PRIO: Number of priority entries in ring.
400 */
401 #define TXCSR2 0x0068
402 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
403 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
404 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
405 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
406
407 /*
408 * TXCSR3: TX Ring Base address register.
409 */
410 #define TXCSR3 0x006c
411 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
412
413 /*
414 * TXCSR4: TX Atim Ring Base address register.
415 */
416 #define TXCSR4 0x0070
417 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
418
419 /*
420 * TXCSR5: TX Prio Ring Base address register.
421 */
422 #define TXCSR5 0x0074
423 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
424
425 /*
426 * TXCSR6: Beacon Base address register.
427 */
428 #define TXCSR6 0x0078
429 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
430
431 /*
432 * TXCSR7: Auto responder control register.
433 * AR_POWERMANAGEMENT: Auto responder power management bit.
434 */
435 #define TXCSR7 0x007c
436 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
437
438 /*
439 * TXCSR8: CCK Tx BBP register.
440 * CCK_SIGNAL: BBP rate field address for CCK.
441 * CCK_SERVICE: BBP service field address for CCK.
442 * CCK_LENGTH_LOW: BBP length low byte address for CCK.
443 * CCK_LENGTH_HIGH: BBP length high byte address for CCK.
444 */
445 #define TXCSR8 0x0098
446 #define TXCSR8_CCK_SIGNAL FIELD32(0x000000ff)
447 #define TXCSR8_CCK_SERVICE FIELD32(0x0000ff00)
448 #define TXCSR8_CCK_LENGTH_LOW FIELD32(0x00ff0000)
449 #define TXCSR8_CCK_LENGTH_HIGH FIELD32(0xff000000)
450
451 /*
452 * TXCSR9: OFDM TX BBP registers
453 * OFDM_SIGNAL: BBP rate field address for OFDM.
454 * OFDM_SERVICE: BBP service field address for OFDM.
455 * OFDM_LENGTH_LOW: BBP length low byte address for OFDM.
456 * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM.
457 */
458 #define TXCSR9 0x0094
459 #define TXCSR9_OFDM_RATE FIELD32(0x000000ff)
460 #define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00)
461 #define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000)
462 #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000)
463
464 /*
465 * Receive related CSRs.
466 * Some values are set in TU, whereas 1 TU == 1024 us.
467 */
468
469 /*
470 * RXCSR0: RX Control Register.
471 * DISABLE_RX: Disable rx engine.
472 * DROP_CRC: Drop crc error.
473 * DROP_PHYSICAL: Drop physical error.
474 * DROP_CONTROL: Drop control frame.
475 * DROP_NOT_TO_ME: Drop not to me unicast frame.
476 * DROP_TODS: Drop frame tods bit is true.
477 * DROP_VERSION_ERROR: Drop version error frame.
478 * PASS_CRC: Pass all packets with crc attached.
479 * PASS_CRC: Pass all packets with crc attached.
480 * PASS_PLCP: Pass all packets with 4 bytes PLCP attached.
481 * DROP_MCAST: Drop multicast frames.
482 * DROP_BCAST: Drop broadcast frames.
483 * ENABLE_QOS: Accept QOS data frame and parse QOS field.
484 */
485 #define RXCSR0 0x0080
486 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
487 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
488 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
489 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
490 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
491 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
492 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
493 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
494 #define RXCSR0_PASS_PLCP FIELD32(0x00000100)
495 #define RXCSR0_DROP_MCAST FIELD32(0x00000200)
496 #define RXCSR0_DROP_BCAST FIELD32(0x00000400)
497 #define RXCSR0_ENABLE_QOS FIELD32(0x00000800)
498
499 /*
500 * RXCSR1: RX descriptor configuration register.
501 * RXD_SIZE: Rx descriptor size, default is 32b.
502 * NUM_RXD: Number of rx entries in ring.
503 */
504 #define RXCSR1 0x0084
505 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
506 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
507
508 /*
509 * RXCSR2: RX Ring base address register.
510 */
511 #define RXCSR2 0x0088
512 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
513
514 /*
515 * RXCSR3: BBP ID register for Rx operation.
516 * BBP_ID#: BBP register # id.
517 * BBP_ID#_VALID: BBP register # id is valid or not.
518 */
519 #define RXCSR3 0x0090
520 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
521 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
522 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
523 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
524 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
525 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
526 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
527 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
528
529 /*
530 * ARCSR1: Auto Responder PLCP config register 1.
531 * AR_BBP_DATA#: Auto responder BBP register # data.
532 * AR_BBP_ID#: Auto responder BBP register # Id.
533 */
534 #define ARCSR1 0x009c
535 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
536 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
537 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
538 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
539
540 /*
541 * Miscellaneous Registers.
542 * Some values are set in TU, whereas 1 TU == 1024 us.
543
544 */
545
546 /*
547 * PCICSR: PCI control register.
548 * BIG_ENDIAN: 1: big endian, 0: little endian.
549 * RX_TRESHOLD: Rx threshold in dw to start pci access
550 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
551 * TX_TRESHOLD: Tx threshold in dw to start pci access
552 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
553 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
554 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
555 * READ_MULTIPLE: Enable memory read multiple.
556 * WRITE_INVALID: Enable memory write & invalid.
557 */
558 #define PCICSR 0x008c
559 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
560 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
561 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
562 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
563 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
564 #define PCICSR_READ_MULTIPLE FIELD32(0x00000100)
565 #define PCICSR_WRITE_INVALID FIELD32(0x00000200)
566
567 /*
568 * CNT0: FCS error count.
569 * FCS_ERROR: FCS error count, cleared when read.
570 */
571 #define CNT0 0x00a0
572 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
573
574 /*
575 * Statistic Register.
576 * CNT1: PLCP error count.
577 * CNT2: Long error count.
578 */
579 #define TIMECSR2 0x00a8
580 #define CNT1 0x00ac
581 #define CNT2 0x00b0
582 #define TIMECSR3 0x00b4
583
584 /*
585 * CNT3: CCA false alarm count.
586 */
587 #define CNT3 0x00b8
588 #define CNT3_FALSE_CCA FIELD32(0x0000ffff)
589
590 /*
591 * Statistic Register.
592 * CNT4: Rx FIFO overflow count.
593 * CNT5: Tx FIFO underrun count.
594 */
595 #define CNT4 0x00bc
596 #define CNT5 0x00c0
597
598 /*
599 * Baseband Control Register.
600 */
601
602 /*
603 * PWRCSR0: Power mode configuration register.
604 */
605 #define PWRCSR0 0x00c4
606
607 /*
608 * Power state transition time registers.
609 */
610 #define PSCSR0 0x00c8
611 #define PSCSR1 0x00cc
612 #define PSCSR2 0x00d0
613 #define PSCSR3 0x00d4
614
615 /*
616 * PWRCSR1: Manual power control / status register.
617 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
618 * SET_STATE: Set state. Write 1 to trigger, self cleared.
619 * BBP_DESIRE_STATE: BBP desired state.
620 * RF_DESIRE_STATE: RF desired state.
621 * BBP_CURR_STATE: BBP current state.
622 * RF_CURR_STATE: RF current state.
623 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
624 */
625 #define PWRCSR1 0x00d8
626 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
627 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
628 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
629 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
630 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
631 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
632
633 /*
634 * TIMECSR: Timer control register.
635 * US_COUNT: 1 us timer count in units of clock cycles.
636 * US_64_COUNT: 64 us timer count in units of 1 us timer.
637 * BEACON_EXPECT: Beacon expect window.
638 */
639 #define TIMECSR 0x00dc
640 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
641 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
642 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
643
644 /*
645 * MACCSR0: MAC configuration register 0.
646 */
647 #define MACCSR0 0x00e0
648
649 /*
650 * MACCSR1: MAC configuration register 1.
651 * KICK_RX: Kick one-shot rx in one-shot rx mode.
652 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
653 * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
654 * AUTO_TXBBP: Auto tx logic access bbp control register.
655 * AUTO_RXBBP: Auto rx logic access bbp control register.
656 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
657 * INTERSIL_IF: Intersil if calibration pin.
658 */
659 #define MACCSR1 0x00e4
660 #define MACCSR1_KICK_RX FIELD32(0x00000001)
661 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
662 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
663 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
664 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
665 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
666 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
667
668 /*
669 * RALINKCSR: Ralink Rx auto-reset BBCR.
670 * AR_BBP_DATA#: Auto reset BBP register # data.
671 * AR_BBP_ID#: Auto reset BBP register # id.
672 */
673 #define RALINKCSR 0x00e8
674 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
675 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00)
676 #define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000)
677 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
678 #define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000)
679 #define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000)
680
681 /*
682 * BCNCSR: Beacon interval control register.
683 * CHANGE: Write one to change beacon interval.
684 * DELTATIME: The delta time value.
685 * NUM_BEACON: Number of beacon according to mode.
686 * MODE: Please refer to asic specs.
687 * PLUS: Plus or minus delta time value.
688 */
689 #define BCNCSR 0x00ec
690 #define BCNCSR_CHANGE FIELD32(0x00000001)
691 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
692 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
693 #define BCNCSR_MODE FIELD32(0x00006000)
694 #define BCNCSR_PLUS FIELD32(0x00008000)
695
696 /*
697 * BBP / RF / IF Control Register.
698 */
699
700 /*
701 * BBPCSR: BBP serial control register.
702 * VALUE: Register value to program into BBP.
703 * REGNUM: Selected BBP register.
704 * BUSY: 1: asic is busy execute BBP programming.
705 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
706 */
707 #define BBPCSR 0x00f0
708 #define BBPCSR_VALUE FIELD32(0x000000ff)
709 #define BBPCSR_REGNUM FIELD32(0x00007f00)
710 #define BBPCSR_BUSY FIELD32(0x00008000)
711 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
712
713 /*
714 * RFCSR: RF serial control register.
715 * VALUE: Register value + id to program into rf/if.
716 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
717 * IF_SELECT: Chip to program: 0: rf, 1: if.
718 * PLL_LD: Rf pll_ld status.
719 * BUSY: 1: asic is busy execute rf programming.
720 */
721 #define RFCSR 0x00f4
722 #define RFCSR_VALUE FIELD32(0x00ffffff)
723 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
724 #define RFCSR_IF_SELECT FIELD32(0x20000000)
725 #define RFCSR_PLL_LD FIELD32(0x40000000)
726 #define RFCSR_BUSY FIELD32(0x80000000)
727
728 /*
729 * LEDCSR: LED control register.
730 * ON_PERIOD: On period, default 70ms.
731 * OFF_PERIOD: Off period, default 30ms.
732 * LINK: 0: linkoff, 1: linkup.
733 * ACTIVITY: 0: idle, 1: active.
734 * LINK_POLARITY: 0: active low, 1: active high.
735 * ACTIVITY_POLARITY: 0: active low, 1: active high.
736 * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF.
737 */
738 #define LEDCSR 0x00f8
739 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
740 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
741 #define LEDCSR_LINK FIELD32(0x00010000)
742 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
743 #define LEDCSR_LINK_POLARITY FIELD32(0x00040000)
744 #define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000)
745 #define LEDCSR_LED_DEFAULT FIELD32(0x00100000)
746
747 /*
748 * AES control register.
749 */
750 #define SECCSR3 0x00fc
751
752 /*
753 * ASIC pointer information.
754 * RXPTR: Current RX ring address.
755 * TXPTR: Current Tx ring address.
756 * PRIPTR: Current Priority ring address.
757 * ATIMPTR: Current ATIM ring address.
758 */
759 #define RXPTR 0x0100
760 #define TXPTR 0x0104
761 #define PRIPTR 0x0108
762 #define ATIMPTR 0x010c
763
764 /*
765 * TXACKCSR0: TX ACK timeout.
766 */
767 #define TXACKCSR0 0x0110
768
769 /*
770 * ACK timeout count registers.
771 * ACKCNT0: TX ACK timeout count.
772 * ACKCNT1: RX ACK timeout count.
773 */
774 #define ACKCNT0 0x0114
775 #define ACKCNT1 0x0118
776
777 /*
778 * GPIO and others.
779 */
780
781 /*
782 * GPIOCSR: GPIO control register.
783 */
784 #define GPIOCSR 0x0120
785 #define GPIOCSR_BIT0 FIELD32(0x00000001)
786 #define GPIOCSR_BIT1 FIELD32(0x00000002)
787 #define GPIOCSR_BIT2 FIELD32(0x00000004)
788 #define GPIOCSR_BIT3 FIELD32(0x00000008)
789 #define GPIOCSR_BIT4 FIELD32(0x00000010)
790 #define GPIOCSR_BIT5 FIELD32(0x00000020)
791 #define GPIOCSR_BIT6 FIELD32(0x00000040)
792 #define GPIOCSR_BIT7 FIELD32(0x00000080)
793 #define GPIOCSR_DIR0 FIELD32(0x00000100)
794 #define GPIOCSR_DIR1 FIELD32(0x00000200)
795 #define GPIOCSR_DIR2 FIELD32(0x00000400)
796 #define GPIOCSR_DIR3 FIELD32(0x00000800)
797 #define GPIOCSR_DIR4 FIELD32(0x00001000)
798 #define GPIOCSR_DIR5 FIELD32(0x00002000)
799 #define GPIOCSR_DIR6 FIELD32(0x00004000)
800 #define GPIOCSR_DIR7 FIELD32(0x00008000)
801
802 /*
803 * FIFO pointer registers.
804 * FIFOCSR0: TX FIFO pointer.
805 * FIFOCSR1: RX FIFO pointer.
806 */
807 #define FIFOCSR0 0x0128
808 #define FIFOCSR1 0x012c
809
810 /*
811 * BCNCSR1: Tx BEACON offset time control register.
812 * PRELOAD: Beacon timer offset in units of usec.
813 * BEACON_CWMIN: 2^CwMin.
814 */
815 #define BCNCSR1 0x0130
816 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
817 #define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000)
818
819 /*
820 * MACCSR2: TX_PE to RX_PE turn-around time control register
821 * DELAY: RX_PE low width, in units of pci clock cycle.
822 */
823 #define MACCSR2 0x0134
824 #define MACCSR2_DELAY FIELD32(0x000000ff)
825
826 /*
827 * TESTCSR: TEST mode selection register.
828 */
829 #define TESTCSR 0x0138
830
831 /*
832 * ARCSR2: 1 Mbps ACK/CTS PLCP.
833 */
834 #define ARCSR2 0x013c
835 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
836 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
837 #define ARCSR2_LENGTH FIELD32(0xffff0000)
838
839 /*
840 * ARCSR3: 2 Mbps ACK/CTS PLCP.
841 */
842 #define ARCSR3 0x0140
843 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
844 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
845 #define ARCSR3_LENGTH FIELD32(0xffff0000)
846
847 /*
848 * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
849 */
850 #define ARCSR4 0x0144
851 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
852 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
853 #define ARCSR4_LENGTH FIELD32(0xffff0000)
854
855 /*
856 * ARCSR5: 11 Mbps ACK/CTS PLCP.
857 */
858 #define ARCSR5 0x0148
859 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
860 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
861 #define ARCSR5_LENGTH FIELD32(0xffff0000)
862
863 /*
864 * ACK/CTS payload consumed time registers.
865 * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps.
866 * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
867 * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
868 */
869 #define ARTCSR0 0x014c
870 #define ARTCSR1 0x0150
871 #define ARTCSR2 0x0154
872
873 /*
874 * SECCSR1_RT2509: WEP control register.
875 * KICK_ENCRYPT: Kick encryption engine, self-clear.
876 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
877 * DESC_ADDRESS: Descriptor physical address of frame.
878 */
879 #define SECCSR1 0x0158
880 #define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001)
881 #define SECCSR1_ONE_SHOT FIELD32(0x00000002)
882 #define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc)
883
884 /*
885 * BBPCSR1: BBP TX configuration.
886 */
887 #define BBPCSR1 0x015c
888 #define BBPCSR1_CCK FIELD32(0x00000003)
889 #define BBPCSR1_CCK_FLIP FIELD32(0x00000004)
890 #define BBPCSR1_OFDM FIELD32(0x00030000)
891 #define BBPCSR1_OFDM_FLIP FIELD32(0x00040000)
892
893 /*
894 * Dual band configuration registers.
895 * DBANDCSR0: Dual band configuration register 0.
896 * DBANDCSR1: Dual band configuration register 1.
897 */
898 #define DBANDCSR0 0x0160
899 #define DBANDCSR1 0x0164
900
901 /*
902 * BBPPCSR: BBP Pin control register.
903 */
904 #define BBPPCSR 0x0168
905
906 /*
907 * MAC special debug mode selection registers.
908 * DBGSEL0: MAC special debug mode selection register 0.
909 * DBGSEL1: MAC special debug mode selection register 1.
910 */
911 #define DBGSEL0 0x016c
912 #define DBGSEL1 0x0170
913
914 /*
915 * BISTCSR: BBP BIST register.
916 */
917 #define BISTCSR 0x0174
918
919 /*
920 * Multicast filter registers.
921 * MCAST0: Multicast filter register 0.
922 * MCAST1: Multicast filter register 1.
923 */
924 #define MCAST0 0x0178
925 #define MCAST1 0x017c
926
927 /*
928 * UART registers.
929 * UARTCSR0: UART1 TX register.
930 * UARTCSR1: UART1 RX register.
931 * UARTCSR3: UART1 frame control register.
932 * UARTCSR4: UART1 buffer control register.
933 * UART2CSR0: UART2 TX register.
934 * UART2CSR1: UART2 RX register.
935 * UART2CSR3: UART2 frame control register.
936 * UART2CSR4: UART2 buffer control register.
937 */
938 #define UARTCSR0 0x0180
939 #define UARTCSR1 0x0184
940 #define UARTCSR3 0x0188
941 #define UARTCSR4 0x018c
942 #define UART2CSR0 0x0190
943 #define UART2CSR1 0x0194
944 #define UART2CSR3 0x0198
945 #define UART2CSR4 0x019c
946
947 /*
948 * RF registers
949 */
950 #define RF1_TUNER FIELD32(0x00020000)
951 #define RF3_TUNER FIELD32(0x00000100)
952 #define RF3_TXPOWER FIELD32(0x00003e00)
953
954 /*
955 * EEPROM content.
956 * The wordsize of the EEPROM is 16 bits.
957 */
958
959 /*
960 * HW MAC address.
961 */
962 #define EEPROM_MAC_ADDR_0 0x0002
963 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
964 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
965 #define EEPROM_MAC_ADDR1 0x0003
966 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
967 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
968 #define EEPROM_MAC_ADDR_2 0x0004
969 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
970 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
971
972 /*
973 * EEPROM antenna.
974 * ANTENNA_NUM: Number of antenna's.
975 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
976 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
977 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
978 * DYN_TXAGC: Dynamic TX AGC control.
979 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
980 * RF_TYPE: Rf_type of this adapter.
981 */
982 #define EEPROM_ANTENNA 0x10
983 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
984 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
985 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
986 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
987 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
988 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
989 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
990
991 /*
992 * EEPROM NIC config.
993 * CARDBUS_ACCEL: 0: enable, 1: disable.
994 * DYN_BBP_TUNE: 0: enable, 1: disable.
995 * CCK_TX_POWER: CCK TX power compensation.
996 */
997 #define EEPROM_NIC 0x11
998 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
999 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
1000 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
1001
1002 /*
1003 * EEPROM geography.
1004 * GEO: Default geography setting for device.
1005 */
1006 #define EEPROM_GEOGRAPHY 0x12
1007 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
1008
1009 /*
1010 * EEPROM BBP.
1011 */
1012 #define EEPROM_BBP_START 0x13
1013 #define EEPROM_BBP_SIZE 16
1014 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1015 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1016
1017 /*
1018 * EEPROM TXPOWER
1019 */
1020 #define EEPROM_TXPOWER_START 0x23
1021 #define EEPROM_TXPOWER_SIZE 7
1022 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
1023 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
1024
1025 /*
1026 * RSSI <-> dBm offset calibration
1027 */
1028 #define EEPROM_CALIBRATE_OFFSET 0x3e
1029 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
1030
1031 /*
1032 * BBP content.
1033 * The wordsize of the BBP is 8 bits.
1034 */
1035
1036 /*
1037 * BBP_R2: TX antenna control
1038 */
1039 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
1040 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
1041
1042 /*
1043 * BBP_R14: RX antenna control
1044 */
1045 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
1046 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
1047
1048 /*
1049 * DMA descriptor defines.
1050 */
1051 #define TXD_DESC_SIZE ( 11 * sizeof(struct data_desc) )
1052 #define RXD_DESC_SIZE ( 11 * sizeof(struct data_desc) )
1053
1054 /*
1055 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
1056 */
1057
1058 /*
1059 * Word0
1060 */
1061 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1062 #define TXD_W0_VALID FIELD32(0x00000002)
1063 #define TXD_W0_RESULT FIELD32(0x0000001c)
1064 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
1065 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
1066 #define TXD_W0_ACK FIELD32(0x00000200)
1067 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
1068 #define TXD_W0_OFDM FIELD32(0x00000800)
1069 #define TXD_W0_CIPHER_OWNER FIELD32(0x00001000)
1070 #define TXD_W0_IFS FIELD32(0x00006000)
1071 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
1072 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1073 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1074
1075 /*
1076 * Word1
1077 */
1078 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1079
1080 /*
1081 * Word2
1082 */
1083 #define TXD_W2_IV_OFFSET FIELD32(0x0000003f)
1084 #define TXD_W2_AIFS FIELD32(0x000000c0)
1085 #define TXD_W2_CWMIN FIELD32(0x00000f00)
1086 #define TXD_W2_CWMAX FIELD32(0x0000f000)
1087
1088 /*
1089 * Word3: PLCP information
1090 */
1091 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
1092 #define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00)
1093 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1094 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1095
1096 /*
1097 * Word4
1098 */
1099 #define TXD_W4_IV FIELD32(0xffffffff)
1100
1101 /*
1102 * Word5
1103 */
1104 #define TXD_W5_EIV FIELD32(0xffffffff)
1105
1106 /*
1107 * Word6-9: Key
1108 */
1109 #define TXD_W6_KEY FIELD32(0xffffffff)
1110 #define TXD_W7_KEY FIELD32(0xffffffff)
1111 #define TXD_W8_KEY FIELD32(0xffffffff)
1112 #define TXD_W9_KEY FIELD32(0xffffffff)
1113
1114 /*
1115 * Word10
1116 */
1117 #define TXD_W10_RTS FIELD32(0x00000001)
1118 #define TXD_W10_TX_RATE FIELD32(0x000000fe)
1119
1120 /*
1121 * RX descriptor format for RX Ring.
1122 */
1123
1124 /*
1125 * Word0
1126 */
1127 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1128 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
1129 #define RXD_W0_MULTICAST FIELD32(0x00000004)
1130 #define RXD_W0_BROADCAST FIELD32(0x00000008)
1131 #define RXD_W0_MY_BSS FIELD32(0x00000010)
1132 #define RXD_W0_CRC FIELD32(0x00000020)
1133 #define RXD_W0_OFDM FIELD32(0x00000040)
1134 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
1135 #define RXD_W0_CIPHER_OWNER FIELD32(0x00000100)
1136 #define RXD_W0_ICV_ERROR FIELD32(0x00000200)
1137 #define RXD_W0_IV_OFFSET FIELD32(0x0000fc00)
1138 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1139 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1140
1141 /*
1142 * Word1
1143 */
1144 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1145
1146 /*
1147 * Word2
1148 */
1149 #define RXD_W2_SIGNAL FIELD32(0x000000ff)
1150 #define RXD_W2_RSSI FIELD32(0x0000ff00)
1151 #define RXD_W2_TA FIELD32(0xffff0000)
1152
1153 /*
1154 * Word3
1155 */
1156 #define RXD_W3_TA FIELD32(0xffffffff)
1157
1158 /*
1159 * Word4
1160 */
1161 #define RXD_W4_IV FIELD32(0xffffffff)
1162
1163 /*
1164 * Word5
1165 */
1166 #define RXD_W5_EIV FIELD32(0xffffffff)
1167
1168 /*
1169 * Word6-9: Key
1170 */
1171 #define RXD_W6_KEY FIELD32(0xffffffff)
1172 #define RXD_W7_KEY FIELD32(0xffffffff)
1173 #define RXD_W8_KEY FIELD32(0xffffffff)
1174 #define RXD_W9_KEY FIELD32(0xffffffff)
1175
1176 /*
1177 * Word10
1178 */
1179 #define RXD_W10_DROP FIELD32(0x00000001)
1180
1181 /*
1182 * Macro's for converting txpower from EEPROM to dscape value
1183 * and from dscape value to register value.
1184 */
1185 #define MIN_TXPOWER 0
1186 #define MAX_TXPOWER 31
1187 #define DEFAULT_TXPOWER 24
1188
1189 #define TXPOWER_FROM_DEV(__txpower) \
1190 ({ \
1191 ((__txpower) > MAX_TXPOWER) ? \
1192 DEFAULT_TXPOWER : (__txpower); \
1193 })
1194
1195 #define TXPOWER_TO_DEV(__txpower) \
1196 ({ \
1197 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1198 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1199 (__txpower)); \
1200 })
1201
1202 #endif /* RT2500PCI_H */