switch: ROBO Switch Gigabit MII Support
[openwrt/svn-archive/archive.git] / package / switch / src / etc53xx.h
1 /*
2 * Broadcom Home Gateway Reference Design
3 * BCM53xx Register definitions
4 *
5 * Copyright 2004, Broadcom Corporation
6 * All Rights Reserved.
7 *
8 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 */
13
14 #ifndef __BCM535M_H_
15 #define __BCM535M_H_
16
17 /* ROBO embedded device type */
18 #define ROBO_DEV_5380 1
19 #define ROBO_DEV_5365 2
20 #define ROBO_DEV_5350 3
21 #define ROBO_DEV_53115 4
22
23 /* BCM5325m GLOBAL PAGE REGISTER MAP */
24 #ifndef _CFE_
25 #pragma pack(1)
26 #endif
27
28 /* BCM5325m Serial Management Port (SMP) Page offsets */
29 #define ROBO_CTRL_PAGE 0x00 /* Control registers */
30 #define ROBO_STAT_PAGE 0x01 /* Status register */
31 #define ROBO_MGMT_PAGE 0x02 /* Management Mode registers */
32 #define ROBO_MIB_AC_PAGE 0x03 /* MIB Autocast registers */
33 #define ROBO_ARLCTRL_PAGE 0x04 /* ARL Control Registers */
34 #define ROBO_ARLIO_PAGE 0x05 /* ARL Access Registers */
35 #define ROBO_FRAMEBUF_PAGE 0x06 /* Management frame access registers */
36 #define ROBO_MEM_ACCESS_PAGE 0x08 /* Memory access registers */
37
38 /* PHY Registers */
39 #define ROBO_PORT0_MII_PAGE 0x10 /* Port 0 MII Registers */
40 #define ROBO_PORT1_MII_PAGE 0x11 /* Port 1 MII Registers */
41 #define ROBO_PORT2_MII_PAGE 0x12 /* Port 2 MII Registers */
42 #define ROBO_PORT3_MII_PAGE 0x13 /* Port 3 MII Registers */
43 #define ROBO_PORT4_MII_PAGE 0x14 /* Port 4 MII Registers */
44 /* (start) registers only for BCM5380 */
45 #define ROBO_PORT5_MII_PAGE 0x15 /* Port 5 MII Registers */
46 #define ROBO_PORT6_MII_PAGE 0x16 /* Port 6 MII Registers */
47 #define ROBO_PORT7_MII_PAGE 0x17 /* Port 7 MII Registers */
48 /* (end) registers only for BCM5380 */
49 #define ROBO_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */
50 #define ROBO_ALL_PORT_PAGE 0x19 /* All ports MII Registers (broadcast)*/
51
52 /* MAC Statistics registers */
53 #define ROBO_PORT0_MIB_PAGE 0x20 /* Port 0 10/100 MIB Statistics */
54 #define ROBO_PORT1_MIB_PAGE 0x21 /* Port 1 10/100 MIB Statistics */
55 #define ROBO_PORT2_MIB_PAGE 0x22 /* Port 2 10/100 MIB Statistics */
56 #define ROBO_PORT3_MIB_PAGE 0x23 /* Port 3 10/100 MIB Statistics */
57 #define ROBO_PORT4_MIB_PAGE 0x24 /* Port 4 10/100 MIB Statistics */
58 /* (start) registers only for BCM5380 */
59 #define ROBO_PORT5_MIB_PAGE 0x25 /* Port 5 10/100 MIB Statistics */
60 #define ROBO_PORT6_MIB_PAGE 0x26 /* Port 6 10/100 MIB Statistics */
61 #define ROBO_PORT7_MIB_PAGE 0x27 /* Port 7 10/100 MIB Statistics */
62 /* (end) registers only for BCM5380 */
63 #define ROBO_IM_PORT_MIB_PAGE 0x28 /* Inverse MII Port MIB Statistics */
64
65 /* Quality of Service (QoS) Registers */
66 #define ROBO_QOS_PAGE 0x30 /* QoS Registers */
67
68 /* VLAN Registers */
69 #define ROBO_VLAN_PAGE 0x34 /* VLAN Registers */
70
71 /* Note SPI Data/IO Registers not used */
72 #define ROBO_SPI_DATA_IO_0_PAGE 0xf0 /* SPI Data I/O 0 */
73 #define ROBO_SPI_DATA_IO_1_PAGE 0xf1 /* SPI Data I/O 1 */
74 #define ROBO_SPI_DATA_IO_2_PAGE 0xf2 /* SPI Data I/O 2 */
75 #define ROBO_SPI_DATA_IO_3_PAGE 0xf3 /* SPI Data I/O 3 */
76 #define ROBO_SPI_DATA_IO_4_PAGE 0xf4 /* SPI Data I/O 4 */
77 #define ROBO_SPI_DATA_IO_5_PAGE 0xf5 /* SPI Data I/O 5 */
78 #define ROBO_SPI_DATA_IO_6_PAGE 0xf6 /* SPI Data I/O 6 */
79 #define ROBO_SPI_DATA_IO_7_PAGE 0xf7 /* SPI Data I/O 7 */
80
81 #define ROBO_SPI_STATUS_PAGE 0xfe /* SPI Status Registers */
82 #define ROBO_PAGE_PAGE 0xff /* Page Registers */
83
84
85 /* BCM5325m CONTROL PAGE (0x00) REGISTER MAP : 8bit (byte) registers */
86 typedef struct _ROBO_PORT_CTRL_STRUC
87 {
88 unsigned char rx_disable:1; /* rx disable */
89 unsigned char tx_disable:1; /* tx disable */
90 unsigned char rsvd:3; /* reserved */
91 unsigned char stp_state:3; /* spanning tree state */
92 } ROBO_PORT_CTRL_STRUC;
93
94 #define ROBO_PORT0_CTRL 0x00 /* 10/100 Port 0 Control */
95 #define ROBO_PORT1_CTRL 0x01 /* 10/100 Port 1 Control */
96 #define ROBO_PORT2_CTRL 0x02 /* 10/100 Port 2 Control */
97 #define ROBO_PORT3_CTRL 0x03 /* 10/100 Port 3 Control */
98 #define ROBO_PORT4_CTRL 0x04 /* 10/100 Port 4 Control */
99 /* (start) registers only for BCM5380 */
100 #define ROBO_PORT5_CTRL 0x05 /* 10/100 Port 5 Control */
101 #define ROBO_PORT6_CTRL 0x06 /* 10/100 Port 6 Control */
102 #define ROBO_PORT7_CTRL 0x07 /* 10/100 Port 7 Control */
103 /* (end) registers only for BCM5380 */
104 #define ROBO_IM_PORT_CTRL 0x08 /* 10/100 Port 8 Control */
105 #define ROBO_SMP_CTRL 0x0a /* SMP Control register */
106 #define ROBO_SWITCH_MODE 0x0b /* Switch Mode Control */
107 #define ROBO_PORT_OVERRIDE_CTRL 0x0e /* Port state override */
108 #define ROBO_PORT_OVERRIDE_RVMII (1<<4) /* Bit 4 enables RvMII */
109 #define ROBO_PD_MODE_CTRL 0x0f /* Power-down mode control */
110 #define ROBO_IP_MULTICAST_CTRL 0x21 /* IP Multicast control */
111
112 /* BCM5325m STATUS PAGE (0x01) REGISTER MAP : 16bit/48bit registers */
113 #define ROBO_HALF_DUPLEX 0
114 #define ROBO_FULL_DUPLEX 1
115
116 #define ROBO_LINK_STAT_SUMMARY 0x00 /* Link Status Summary: 16bit */
117 #define ROBO_LINK_STAT_CHANGE 0x02 /* Link Status Change: 16bit */
118 #define ROBO_SPEED_STAT_SUMMARY 0x04 /* Port Speed Summary: 16bit*/
119 #define ROBO_DUPLEX_STAT_SUMMARY 0x06 /* Duplex Status Summary: 16bit */
120 #define ROBO_PAUSE_STAT_SUMMARY 0x08 /* PAUSE Status Summary: 16bit */
121 #define ROBO_SOURCE_ADDR_CHANGE 0x0C /* Source Address Change: 16bit */
122 #define ROBO_LSA_PORT0 0x10 /* Last Source Addr, Port 0: 48bits*/
123 #define ROBO_LSA_PORT1 0x16 /* Last Source Addr, Port 1: 48bits*/
124 #define ROBO_LSA_PORT2 0x1c /* Last Source Addr, Port 2: 48bits*/
125 #define ROBO_LSA_PORT3 0x22 /* Last Source Addr, Port 3: 48bits*/
126 #define ROBO_LSA_PORT4 0x28 /* Last Source Addr, Port 4: 48bits*/
127 #define ROBO_LSA_IM_PORT 0x40 /* Last Source Addr, IM Port: 48bits*/
128
129 /* BCM5325m MANAGEMENT MODE REGISTERS (0x02) REGISTER MAP: 8/48 bit regs*/
130 typedef struct _ROBO_GLOBAL_CONFIG_STRUC
131 {
132 unsigned char resetMIB:1; /* reset MIB counters */
133 unsigned char rxBPDU:1; /* receive BDPU enable */
134 unsigned char rsvd1:2; /* reserved */
135 unsigned char MIBacHdrCtrl:1; /* MIB autocast header control */
136 unsigned char MIBac:1; /* MIB autocast enable */
137 unsigned char frameMgmtPort:2; /* frame management port */
138 } ROBO_GLOBAL_CONFIG_STRUC;
139 #define ROBO_GLOBAL_CONFIG 0x00 /* Global Management Config: 8bit*/
140 #define ROBO_MGMT_PORT_ID 0x02 /* Management Port ID: 8bit*/
141 #define ROBO_RMON_MIB_STEER 0x04 /* RMON Mib Steering: 16bit */
142 #define ROBO_MIB_MODE_SELECT 0x04 /* MIB Mode select: 16bit (BCM5350) */
143 #define ROBO_AGE_TIMER_CTRL 0x06 /* Age time control: 32bit */
144 #define ROBO_MIRROR_CAP_CTRL 0x10 /* Mirror Capture : 16bit */
145 #define ROBO_MIRROR_ING_CTRL 0x12 /* Mirror Ingress Control: 16bit */
146 #define ROBO_MIRROR_ING_DIV_CTRL 0x14 /* Mirror Ingress Divider: 16bit */
147 #define ROBO_MIRROR_ING_MAC_ADDR 0x16 /* Ingress Mirror MAC Addr: 48bit*/
148 #define ROBO_MIRROR_EGR_CTRL 0x1c /* Mirror Egress Control: 16bit */
149 #define ROBO_MIRROR_EGR_DIV_CTRL 0x1e /* Mirror Egress Divider: 16bit */
150 #define ROBO_MIRROR_EGR_MAC_ADDR 0x20 /* Egress Mirror MAC Addr: 48bit*/
151
152 /* BCM5325m MIB AUTOCAST REGISTERS (0x03) REGISTER MAP: 8/16/48 bit regs */
153 #define ROBO_MIB_AC_PORT 0x00 /* MIB Autocast Port: 16bit */
154 #define ROBO_MIB_AC_HDR_PTR 0x02 /* MIB Autocast Header pointer:16bit*/
155 #define ROBO_MIB_AC_HDR_LEN 0x04 /* MIB Autocast Header Len: 16bit */
156 #define ROBO_MIB_AC_DA 0x06 /* MIB Autocast DA: 48bit */
157 #define ROBO_MIB_AC_SA 0x0c /* MIB Autocast SA: 48bit */
158 #define ROBO_MIB_AC_TYPE 0x12 /* MIB Autocast Type: 16bit */
159 #define ROBO_MIB_AC_RATE 0x14 /* MIB Autocast Rate: 8bit */
160 #define ROBO_GET_AC_RATE(secs) ((secs)*10)
161 #define ROBO_AC_RATE_MAX 0xff
162 #define ROBO_AC_RATE_DEFAULT 0x64 /* 10 secs */
163 typedef struct _ROBO_MIB_AC_STRUCT
164 {
165 unsigned char opcode:4; /* Tx MIB Autocast opcode */
166 unsigned char portno:4; /* zero-based port no. */
167 unsigned char portstate:8; /* port state */
168 unsigned long long TxOctets;
169 unsigned int TxDropPkts;
170 unsigned int rsvd;
171 unsigned int TxBroadcastPkts;
172 unsigned int TxMulticastPkts;
173 unsigned int TxUnicastPkts;
174 unsigned int TxCollisions;
175 unsigned int TxSingleCollision;
176 unsigned int TxMultiCollision;
177 unsigned int TxDeferredTransmit;
178 unsigned int TxLateCollision;
179 unsigned int TxExcessiveCollision;
180 unsigned int TxFrameInDiscards;
181 unsigned int TxPausePkts;
182 unsigned int rsvd1[2];
183 unsigned long long RxOctets;
184 unsigned int RxUndersizePkts;
185 unsigned int RxPausePkts;
186 unsigned int RxPkts64Octets;
187 unsigned int RxPkts64to127Octets;
188 unsigned int RxPkts128to255Octets;
189 unsigned int RxPkts256to511Octets;
190 unsigned int RxPkts512to1023Octets;
191 unsigned int RxPkts1024to1522Octets;
192 unsigned int RxOversizePkts;
193 unsigned int RxJabbers;
194 unsigned int RxAlignmentErrors;
195 unsigned int RxFCSErrors;
196 unsigned long long RxGoodOctets;
197 unsigned int RxDropPkts;
198 unsigned int RxUnicastPkts;
199 unsigned int RxMulticastPkts;
200 unsigned int RxBroadcastPkts;
201 unsigned int RxSAChanges;
202 unsigned int RxFragments;
203 unsigned int RxExcessSizeDisc;
204 unsigned int RxSymbolError;
205 } ROBO_MIB_AC_STRUCT;
206
207 /* BCM5325m ARL CONTROL REGISTERS (0x04) REGISTER MAP: 8/16/48/64 bit regs */
208 #define ROBO_ARL_CONFIG 0x00 /* ARL Global Configuration: 8bit*/
209 #define ROBO_BPDU_MC_ADDR_REG 0x04 /* BPDU Multicast Address Reg:64bit*/
210 #define ROBO_MULTIPORT_ADDR_1 0x10 /* Multiport Address 1: 48 bits*/
211 #define ROBO_MULTIPORT_VECTOR_1 0x16 /* Multiport Vector 1: 16 bits */
212 #define ROBO_MULTIPORT_ADDR_2 0x20 /* Multiport Address 2: 48 bits*/
213 #define ROBO_MULTIPORT_VECTOR_2 0x26 /* Multiport Vector 2: 16 bits */
214 #define ROBO_SECURE_SRC_PORT_MASK 0x30 /* Secure Source Port Mask: 16 bits*/
215 #define ROBO_SECURE_DST_PORT_MASK 0x32 /* Secure Dest Port Mask: 16 bits */
216
217
218 /* BCM5325m ARL IO REGISTERS (0x05) REGISTER MAP: 8/16/48/64 bit regs */
219 #define ARL_TABLE_WRITE 0 /* for read/write state in control reg */
220 #define ARL_TABLE_READ 1 /* for read/write state in control reg */
221 #ifdef BCM5380
222 #define ARL_VID_BYTES 2 /* number of bytes for VID */
223 #else
224 #define ARL_VID_BYTES 1 /* number of bytes for VID */
225 #endif
226 typedef struct _ROBO_ARL_RW_CTRL_STRUC
227 {
228 unsigned char ARLrw:1; /* ARL read/write (1=read) */
229 unsigned char rsvd:6; /* reserved */
230 unsigned char ARLStart:1; /* ARL start/done (1=start) */
231 } ROBO_ARL_RW_CTRL_STRUC;
232 typedef struct _ROBO_ARL_SEARCH_CTRL_STRUC
233 {
234 unsigned char valid:1; /* ARL search result valid */
235 unsigned char rsvd:6; /* reserved */
236 unsigned char ARLStart:1; /* ARL start/done (1=start) */
237 } ROBO_ARL_SEARCH_CTRL_STRUC;
238 typedef struct _ROBO_ARL_ENTRY_CTRL_STRUC
239 {
240 unsigned char portID:4; /* port id */
241 unsigned char chipID:2; /* chip id */
242 unsigned char rsvd:5; /* reserved */
243 unsigned char prio:2; /* priority */
244 unsigned char age:1; /* age */
245 unsigned char staticEn:1; /* static */
246 unsigned char valid:1; /* valid */
247 } ROBO_ARL_ENTRY_CTRL_STRUC;
248 typedef struct _ROBO_ARL_SEARCH_RESULT_CTRL_STRUC
249 {
250 unsigned char portID:4; /* port id */
251 unsigned char rsvd:1; /* reserved */
252 unsigned char vid:8; /* vlan id */
253 unsigned char age:1; /* age */
254 unsigned char staticEn:1; /* static */
255 unsigned char valid:1; /* valid */
256 } ROBO_ARL_SEARCH_RESULT_CTRL_STRUC;
257 typedef struct _ROBO_ARL_ENTRY_MAC_STRUC
258 {
259 unsigned char macBytes[6]; /* MAC address */
260 } ROBO_ARL_ENTRY_MAC_STRUC;
261
262 typedef struct _ROBO_ARL_ENTRY_STRUC
263 {
264 ROBO_ARL_ENTRY_MAC_STRUC mac; /* MAC address */
265 ROBO_ARL_ENTRY_CTRL_STRUC ctrl; /* control bits */
266 } ROBO_ARL_ENTRY_STRUC;
267
268 typedef struct _ROBO_ARL_SEARCH_RESULT_STRUC
269 {
270 ROBO_ARL_ENTRY_MAC_STRUC mac; /* MAC address */
271 ROBO_ARL_SEARCH_RESULT_CTRL_STRUC ctrl; /* control bits */
272 } ROBO_ARL_SEARCH_RESULT_STRUC;
273
274 /* multicast versions of ARL entry structs */
275 typedef struct _ROBO_ARL_ENTRY_MCAST_CTRL_STRUC
276 {
277 unsigned int portMask:12;/* multicast port mask */
278 unsigned char prio:1; /* priority */
279 unsigned char gigPort:1; /* gigabit port 1 mask */
280 unsigned char staticEn:1; /* static */
281 unsigned char valid:1; /* valid */
282 } ROBO_ARL_ENTRY_MCAST_CTRL_STRUC;
283 typedef struct _ROBO_ARL_SEARCH_RESULT_MCAST_CTRL_STRUC
284 {
285 unsigned int portMask:13; /* multicast port mask */
286 unsigned char age:1; /* age */
287 unsigned char staticEn:1; /* static */
288 unsigned char valid:1; /* valid */
289 } ROBO_ARL_SEARCH_RESULT_MCAST_CTRL_STRUC;
290 /* BCM5350 extension register */
291 typedef struct _ROBO_ARL_SEARCH_RESULT_EXTENSION
292 {
293 unsigned int prio:2; /* priority */
294 unsigned int portMask:1; /* MSB (MII) of port mask for multicast */
295 unsigned int reserved:5;
296 } ROBO_ARL_SEARCH_RESULT_EXTENSION;
297
298 typedef struct _ROBO_ARL_ENTRY_MCAST_STRUC
299 {
300 ROBO_ARL_ENTRY_MAC_STRUC mac; /* MAC address */
301 ROBO_ARL_ENTRY_MCAST_CTRL_STRUC ctrl; /* control bits */
302 } ROBO_ARL_ENTRY_MCAST_STRUC;
303 typedef struct _ROBO_ARL_SEARCH_RESULT_MCAST_STRUC
304 {
305 ROBO_ARL_ENTRY_MAC_STRUC mac; /* MAC address */
306 ROBO_ARL_SEARCH_RESULT_MCAST_CTRL_STRUC ctrl; /* control bits */
307 } ROBO_ARL_SEARCH_RESULT_MCAST_STRUC;
308
309 #define ROBO_ARL_RW_CTRL 0x00 /* ARL Read/Write Control : 8bit */
310 #define ROBO_ARL_MAC_ADDR_IDX 0x02 /* MAC Address Index: 48bit */
311 #define ROBO_ARL_VID_TABLE_IDX 0x08 /* VID Table Address Index: 8bit */
312 #define ROBO_ARL_ENTRY0 0x10 /* ARL Entry 0 : 64 bit */
313 #define ROBO_ARL_ENTRY1 0x18 /* ARL Entry 1 : 64 bit */
314 #define ROBO_ARL_SEARCH_CTRL 0x20 /* ARL Search Control: 8bit */
315 #define ROBO_ARL_SEARCH_ADDR 0x22 /* ARL Search Address: 16bit */
316 #define ROBO_ARL_SEARCH_RESULT 0x24 /* ARL Search Result: 64bit */
317 #define ROBO_ARL_SEARCH_RESULT_EXT 0x2c /* ARL Search Result Extension (5350): 8bit */
318 #define ROBO_ARL_VID_ENTRY0 0x30 /* ARL VID Entry 0: 64bit */
319 #define ROBO_ARL_VID_ENTRY1 0x32 /* ARL VID Entry 1: 64bit */
320 #define ROBO_ARL_SEARCH_CTRL_53115 0x50 /* ARL Search Control: 8bit */
321 #define ROBO_ARL_SEARCH_ADDR_53115 0x51 /* ARL Search Address: 16bit */
322 #define ROBO_ARL_SEARCH_RESULT_53115 0x60 /* ARL Search Result: 64bit */
323 #define ROBO_ARL_SEARCH_RESULT_EXT_53115 0x68 /* ARL Search Result Extension (53115): 16bit */
324
325 /* BCM5395/5397/5398/53115 */
326 #define ROBO_VTBL_ACCESS 0x60 /* VLAN table access: 8bit */
327 #define ROBO_VTBL_INDX 0x61 /* VLAN table address index: 16bit */
328 #define ROBO_VTBL_ENTRY 0x63 /* VLAN table entry: 32bit */
329 #define ROBO_VTBL_ACCESS_5395 0x80 /* VLAN table access: 8bit */
330 #define ROBO_VTBL_INDX_5395 0x81 /* VLAN table address index: 16bit */
331 #define ROBO_VTBL_ENTRY_5395 0x83 /* VLAN table entry: 32bit */
332
333 /* BCM5325m MANAGEMENT FRAME REGISTERS (0x6) REGISTER MAP: 8/16 bit regs */
334 #define ROBO_MGMT_FRAME_RD_DATA 0x00 /* Management Frame Read Data :8bit*/
335 #define ROBO_MGMT_FRAME_WR_DATA 0x01 /* Management Frame Write Data:8bit*/
336 #define ROBO_MGMT_FRAME_WR_CTRL 0x02 /* Write Control: 16bit */
337 #define ROBO_MGMT_FRAME_RD_STAT 0x04 /* Read Status: 16bit */
338
339 /* BCM5325m MEMORY ACCESS REGISTERS (Page 0x08) REGISTER MAP: 32 bit regs */
340 #define MEM_TABLE_READ 1 /* for read/write state in mem access reg */
341 #define MEM_TABLE_WRITE 0 /* for read/write state in mem access reg */
342 #define MEM_TABLE_ACCESS_START 1 /* for mem access read/write start */
343 #define MEM_TABLE_ACCESS_DONE 0 /* for mem access read/write done */
344 #define VLAN_TABLE_ADDR 0x3800 /* BCM5380 only */
345 #ifdef BCM5380
346 #define NUM_ARL_TABLE_ENTRIES 4096 /* number of entries in ARL table */
347 #define NUM_VLAN_TABLE_ENTRIES 2048 /* number of entries in VLAN table */
348 #define ARL_TABLE_ADDR 0 /* offset of ARL table start */
349 #else
350 #define NUM_ARL_TABLE_ENTRIES 2048 /* number of entries in ARL table */
351 #define NUM_VLAN_TABLE_ENTRIES 256 /* number of entries in VLAN table */
352 #define ARL_TABLE_ADDR 0x3800 /* offset of ARL table start */
353 /* corresponding values for 5350 */
354 #define NUM_ARL_TABLE_ENTRIES_5350 1024 /* number of entries in ARL table (5350) */
355 #define NUM_VLAN_TABLE_ENTRIES_5350 16 /* number of entries in VLAN table */
356 #define ARL_TABLE_ADDR_5350 0x1c00 /* offset of ARL table start (5350) */
357 #endif
358 #define NUM_ARL_TABLE_ENTRIES_53115 4096 /* number of entries in ARL table (53115) */
359 #define NUM_VLAN_TABLE_ENTRIES_53115 4096 /* number of entries in VLAN table */
360 typedef struct _ROBO_MEM_ACCESS_CTRL_STRUC
361 {
362 unsigned int memAddr:14; /* 64-bit memory address */
363 unsigned char rsvd:4; /* reserved */
364 unsigned char readEn:1; /* read enable (0 == write) */
365 unsigned char startDone:1;/* memory access start/done */
366 unsigned int rsvd1:12; /* reserved */
367 } ROBO_MEM_ACCESS_CTRL_STRUC;
368 typedef struct _ROBO_MEM_ACCESS_DATA_STRUC
369 {
370 unsigned int memData[2]; /* 64-bit data */
371 unsigned short rsvd; /* reserved */
372 } ROBO_MEM_ACCESS_DATA_STRUC;
373
374 #ifdef BCM5380
375 typedef struct _ROBO_ARL_TABLE_DATA_STRUC
376 {
377 unsigned char MACaddr[6]; /* MAC addr */
378 unsigned int portID:4; /* port ID */
379 unsigned int chipID:2; /* chip ID */
380 unsigned int rsvd:6; /* reserved */
381 unsigned int highPrio:1; /* high priority address */
382 unsigned int age:1; /* entry accessed/learned since ageing process */
383 unsigned int staticAddr:1;/* entry is static */
384 unsigned int valid:1; /* entry is valid */
385 unsigned int vid:12; /* vlan id */
386 unsigned int rsvd2:4; /* reserved */
387 } ROBO_ARL_TABLE_DATA_STRUC;
388 #else
389 typedef struct _ROBO_ARL_TABLE_DATA_STRUC
390 {
391 unsigned char MACaddr[6]; /* MAC addr */
392 unsigned int portID:4; /* port ID */
393 unsigned int chipID:2; /* chip ID */
394 unsigned int rsvd:7; /* reserved */
395 unsigned int age:1; /* entry accessed/learned since ageing process */
396 unsigned int staticAddr:1;/* entry is static */
397 unsigned int valid:1; /* entry is valid */
398 } ROBO_ARL_TABLE_DATA_STRUC;
399 #endif
400
401 /* multicast format*/
402 typedef struct _ROBO_ARL_TABLE_MCAST_DATA_STRUC
403 {
404 unsigned char MACaddr[6]; /* MAC addr */
405 unsigned int portMask:12;/* multicast port mask */
406 unsigned char prio:1; /* priority */
407 unsigned char gigPort:1; /* gigabit port 1 mask */
408 unsigned char staticEn:1; /* static */
409 unsigned char valid:1; /* valid */
410 unsigned int vid:12; /* vlan id */
411 unsigned int rsvd2:4; /* reserved */
412 } ROBO_ARL_TABLE_MCAST_DATA_STRUC;
413 #define ROBO_MEM_ACCESS_CTRL 0x00 /* Memory Read/Write Control :32bit*/
414 #define ROBO_MEM_ACCESS_DATA 0x04 /* Memory Read/Write Data:64bit*/
415
416 /* BCM5325m SWITCH PORT (0x10-18) REGISTER MAP: 8/16 bit regs */
417 typedef struct _ROBO_MII_CTRL_STRUC
418 {
419 unsigned char rsvd:8; /* reserved */
420 unsigned char duplex:1; /* duplex mode */
421 unsigned char restartAN:1;/* restart auto-negotiation */
422 unsigned char rsvd1:1; /* reserved */
423 unsigned char powerDown:1;/* power down */
424 unsigned char ANenable:1; /* auto-negotiation enable */
425 unsigned char speed:1; /* forced speed selection */
426 unsigned char loopback:1; /* loopback */
427 unsigned char reset:1; /* reset */
428 } ROBO_MII_CTRL_STRUC;
429 typedef struct _ROBO_MII_AN_ADVERT_STRUC
430 {
431 unsigned char selector:5; /* advertise selector field */
432 unsigned char T10BaseT:1; /* advertise 10BaseT */
433 unsigned char T10BaseTFull:1; /* advertise 10BaseT, full duplex */
434 unsigned char T100BaseX:1; /* advertise 100BaseX */
435 unsigned char T100BaseXFull:1;/* advertise 100BaseX full duplex */
436 unsigned char noT4:1; /* do not advertise T4 */
437 unsigned char pause:1; /* advertise pause for full duplex */
438 unsigned char rsvd:2; /* reserved */
439 unsigned char remoteFault:1; /* transmit remote fault */
440 unsigned char rsvd1:1; /* reserved */
441 unsigned char nextPage:1; /* nex page operation supported */
442 } ROBO_MII_AN_ADVERT_STRUC;
443 #define ROBO_MII_CTRL 0x00 /* Port MII Control */
444 #define ROBO_MII_STAT 0x02 /* Port MII Status */
445 /* Fields of link status register */
446 #define ROBO_MII_STAT_JABBER (1<<1) /* Jabber detected */
447 #define ROBO_MII_STAT_LINK (1<<2) /* Link status */
448
449 #define ROBO_MII_PHYID_HI 0x04 /* Port PHY ID High */
450 #define ROBO_MII_PHYID_LO 0x06 /* Port PHY ID Low */
451 #define ROBO_MII_ANA_REG 0x08 /* MII Auto-Neg Advertisement */
452 #define ROBO_MII_ANP_REG 0x0a /* MII Auto-Neg Partner Ability */
453 #define ROBO_MII_AN_EXP_REG 0x0c /* MII Auto-Neg Expansion */
454 #define ROBO_MII_AN_NP_REG 0x0e /* MII next page */
455 #define ROBO_MII_ANP_NP_REG 0x10 /* MII Partner next page */
456 #define ROBO_MII_100BX_AUX_CTRL 0x20 /* 100BASE-X Auxiliary Control */
457 #define ROBO_MII_100BX_AUX_STAT 0x22 /* 100BASE-X Auxiliary Status */
458 #define ROBO_MII_100BX_RCV_ERR_CTR 0x24 /* 100BASE-X Receive Error Ctr */
459 #define ROBO_MII_100BX_RCV_FS_ERR 0x26 /* 100BASE-X Rcv False Sense Ctr */
460 #define ROBO_MII_AUX_CTRL 0x30 /* Auxiliary Control/Status */
461 /* Fields of Auxiliary control register */
462 #define ROBO_MII_AUX_CTRL_FD (1<<0) /* Full duplex link detected*/
463 #define ROBO_MII_AUX_CTRL_SP100 (1<<1) /* Speed 100 indication */
464 #define ROBO_MII_AUX_STATUS 0x32 /* Aux Status Summary */
465 #define ROBO_MII_CONN_STATUS 0x34 /* Aux Connection Status */
466 #define ROBO_MII_AUX_MODE2 0x36 /* Aux Mode 2 */
467 #define ROBO_MII_AUX_ERR_STATUS 0x38 /* Aux Error and General Status */
468 #define ROBO_MII_AUX_MULTI_PHY 0x3c /* Aux Multiple PHY Register*/
469 #define ROBO_MII_BROADCOM_TEST 0x3e /* Broadcom Test Register */
470
471
472 /* BCM5325m PORT MIB REGISTERS (Pages 0x20-0x24,0x28) REGISTER MAP: 64/32 */
473 /* Tranmit Statistics */
474 #define ROBO_MIB_TX_OCTETS 0x00 /* 64b: TxOctets */
475 #define ROBO_MIB_TX_DROP_PKTS 0x08 /* 32b: TxDropPkts */
476 #define ROBO_MIB_TX_BC_PKTS 0x10 /* 32b: TxBroadcastPkts */
477 #define ROBO_MIB_TX_MC_PKTS 0x14 /* 32b: TxMulticastPkts */
478 #define ROBO_MIB_TX_UC_PKTS 0x18 /* 32b: TxUnicastPkts */
479 #define ROBO_MIB_TX_COLLISIONS 0x1c /* 32b: TxCollisions */
480 #define ROBO_MIB_TX_SINGLE_COLLISIONS 0x20 /* 32b: TxSingleCollision */
481 #define ROBO_MIB_TX_MULTI_COLLISIONS 0x24 /* 32b: TxMultiCollision */
482 #define ROBO_MIB_TX_DEFER_TX 0x28 /* 32b: TxDeferred Transmit */
483 #define ROBO_MIB_TX_LATE_COLLISIONS 0x2c /* 32b: TxLateCollision */
484 #define ROBO_MIB_EXCESS_COLLISIONS 0x30 /* 32b: TxExcessiveCollision*/
485 #define ROBO_MIB_FRAME_IN_DISCARDS 0x34 /* 32b: TxFrameInDiscards */
486 #define ROBO_MIB_TX_PAUSE_PKTS 0x38 /* 32b: TxPausePkts */
487
488 /* Receive Statistics */
489 #define ROBO_MIB_RX_OCTETS 0x44 /* 64b: RxOctets */
490 #define ROBO_MIB_RX_UNDER_SIZE_PKTS 0x4c /* 32b: RxUndersizePkts(runts)*/
491 #define ROBO_MIB_RX_PAUSE_PKTS 0x50 /* 32b: RxPausePkts */
492 #define ROBO_MIB_RX_PKTS_64 0x54 /* 32b: RxPkts64Octets */
493 #define ROBO_MIB_RX_PKTS_65_TO_127 0x58 /* 32b: RxPkts64to127Octets*/
494 #define ROBO_MIB_RX_PKTS_128_TO_255 0x5c /* 32b: RxPkts128to255Octets*/
495 #define ROBO_MIB_RX_PKTS_256_TO_511 0x60 /* 32b: RxPkts256to511Octets*/
496 #define ROBO_MIB_RX_PKTS_512_TO_1023 0x64 /* 32b: RxPkts512to1023Octets*/
497 #define ROBO_MIB_RX_PKTS_1024_TO_1522 0x68 /* 32b: RxPkts1024to1522Octets*/
498 #define ROBO_MIB_RX_OVER_SIZE_PKTS 0x6c /* 32b: RxOversizePkts*/
499 #define ROBO_MIB_RX_JABBERS 0x70 /* 32b: RxJabbers*/
500 #define ROBO_MIB_RX_ALIGNMENT_ERRORS 0x74 /* 32b: RxAlignmentErrors*/
501 #define ROBO_MIB_RX_FCS_ERRORS 0x78 /* 32b: RxFCSErrors */
502 #define ROBO_MIB_RX_GOOD_OCTETS 0x7c /* 32b: RxGoodOctets */
503 #define ROBO_MIB_RX_DROP_PKTS 0x84 /* 32b: RxDropPkts */
504 #define ROBO_MIB_RX_UC_PKTS 0x88 /* 32b: RxUnicastPkts */
505 #define ROBO_MIB_RX_MC_PKTS 0x8c /* 32b: RxMulticastPkts */
506 #define ROBO_MIB_RX_BC_PKTS 0x90 /* 32b: RxBroadcastPkts */
507 #define ROBO_MIB_RX_SA_CHANGES 0x94 /* 32b: RxSAChanges */
508 #define ROBO_MIB_RX_FRAGMENTS 0x98 /* 32b: RxFragments */
509 #define ROBO_MIB_RX_EXCESS_SZ_DISC 0x9c /* 32b: RxExcessSizeDisc*/
510 #define ROBO_MIB_RX_SYMBOL_ERROR 0xa0 /* 32b: RxSymbolError */
511
512 /* BCM5350 MIB Statistics */
513 /* Group 0 */
514 #define ROBO_MIB_TX_GOOD_PKTS 0x00 /* 16b: TxGoodPkts */
515 #define ROBO_MIB_TX_UNICAST_PKTS 0x02 /* 16b: TxUnicastPkts */
516 #define ROBO_MIB_RX_GOOD_PKTS 0x04 /* 16b: RxGoodPkts */
517 #define ROBO_MIB_RX_GOOD_UNICAST_PKTS 0x06 /* 16b: RxGoodUnicastPkts */
518 /* Group 1 */
519 #define ROBO_MIB_TX_COLLISION 0x00 /* 16b: TxCollision */
520 #define ROBO_MIB_TX_OCTETS_5350 0x02 /* 16b: TxOctets */
521 #define ROBO_MIB_RX_FCS_ERRORS_5350 0x04 /* 16b: RxFCSErrors */
522 #define ROBO_MIB_RX_GOOD_OCTETS_5350 0x06 /* 16b: RxGoodOctets */
523
524 /* BCM5325m QoS REGISTERS (Page 0x30) REGISTER MAP: 8/16 */
525 #define ROBO_QOS_CTRL 0x00 /* 16b: QoS Control Register */
526 #define ROBO_QOS_LOCAL_WEIGHT_CTRL 0x10 /* 8b: Local HQ/LQ Weight Register*/
527 #define ROBO_QOS_CPU_WEIGHT_CTRL 0x12 /* 8b: CPU HQ/LQ Weight Register*/
528 #define ROBO_QOS_PAUSE_ENA 0x13 /* 16b: Qos Pause Enable Register*/
529 #define ROBO_QOS_PRIO_THRESHOLD 0x15 /* 8b: Priority Threshold Register*/
530 #define ROBO_QOS_RESERVED 0x16 /* 8b: Qos Reserved Register */
531
532 /* BCM5325m VLAN REGISTERS (Page 0x34) REGISTER MAP: 8/16bit */
533 typedef struct _ROBO_VLAN_CTRL0_STRUC
534 {
535 unsigned char frameControlP:2; /* 802.1P frame control */
536 unsigned char frameControlQ:2; /* 802.1Q frame control */
537 unsigned char dropMissedVID:1; /* enable drop missed VID packet */
538 unsigned char vidMacHash:1; /* VID_MAC hash enable */
539 unsigned char vidMacCheck:1; /* VID_MAC check enable */
540 unsigned char VLANen:1; /* 802.1Q VLAN enable */
541 } ROBO_VLAN_CTRL0_STRUC;
542 #define VLAN_TABLE_WRITE 1 /* for read/write state in table access reg */
543 #define VLAN_TABLE_READ 0 /* for read/write state in table access reg */
544 #define VLAN_ID_HIGH_BITS 0 /* static high bits in table access reg */
545 #define VLAN_ID_MAX 255 /* max VLAN id */
546 #define VLAN_ID_MAX5350 15 /* max VLAN id (5350) */
547 #define VLAN_ID_MAX5395 4094 /* max VLAN id (5395) */
548 #define VLAN_ID_MASK VLAN_ID_MAX /* VLAN id mask */
549 #ifdef BCM5380
550 #define VLAN_UNTAG_SHIFT 13 /* for postioning untag bits in write reg */
551 #define VLAN_VALID 0x4000000 /* valid bit in write reg */
552 #else
553 #define VLAN_UNTAG_SHIFT 7 /* for postioning untag bits in write reg */
554 #define VLAN_VALID 0x4000 /* valid bit in write reg */
555 /* corresponding values for 5350 */
556 #define VLAN_UNTAG_SHIFT_5350 6 /* for postioning untag bits in write reg */
557 #define VLAN_VALID_5350 0x00100000 /* valid bit in write reg */
558 #endif
559 typedef struct _ROBO_VLAN_TABLE_ACCESS_STRUC
560 {
561 unsigned char VLANid:8; /* VLAN ID (low 8 bits) */
562 unsigned char VLANidHi:4; /* VLAN ID (fixed upper portion) */
563 unsigned char readWriteState:1; /* read/write state (write = 1) */
564 volatile unsigned char readWriteEnable:1; /* table read/write enable */
565 unsigned char rsvd:2; /* reserved */
566 } ROBO_VLAN_TABLE_ACCESS_STRUC;
567 #ifdef BCM5380
568 typedef struct _ROBO_VLAN_READ_WRITE_STRUC
569 {
570 unsigned int VLANgroup:13;/* VLAN group mask */
571 unsigned int VLANuntag:13;/* VLAN untag enable mask */
572 unsigned char valid:1; /* valid */
573 unsigned char rsvd:5; /* reserved */
574 } ROBO_VLAN_READ_WRITE_STRUC;
575 #else
576 typedef struct _ROBO_VLAN_READ_WRITE_STRUC
577 {
578 unsigned char VLANgroup:7; /* VLAN group mask */
579 unsigned char VLANuntag:7; /* VLAN untag enable mask */
580 unsigned char valid:1; /* valid */
581 unsigned char rsvd:1; /* reserved */
582 } ROBO_VLAN_READ_WRITE_STRUC;
583 typedef struct _ROBO_VLAN_READ_WRITE_STRUC_5350
584 {
585 unsigned char VLANgroup:6; /* VLAN group mask */
586 unsigned char VLANuntag:6; /* VLAN untag enable mask */
587 unsigned char highVID:8; /* upper bits of vid */
588 unsigned char valid:1; /* valid */
589 unsigned int rsvd:11; /* reserved */
590 } ROBO_VLAN_READ_WRITE_STRUC_5350;
591 #endif
592 #define ROBO_VLAN_CTRL0 0x00 /* 8b: VLAN Control 0 Register */
593 #define ROBO_VLAN_CTRL1 0x01 /* 8b: VLAN Control 1 Register */
594 #define ROBO_VLAN_CTRL2 0x02 /* 8b: VLAN Control 2 Register */
595 #define ROBO_VLAN_CTRL3 0x03 /* 8b: VLAN Control 3 Register */
596 #define ROBO_VLAN_CTRL4 0x04 /* 8b: VLAN Control 4 Register */
597 #define ROBO_VLAN_CTRL5 0x05 /* 8b: VLAN Control 5 Register */
598 #define ROBO_VLAN_TABLE_ACCESS 0x08 /* 14b: VLAN Table Access Register */
599 #define ROBO_VLAN_TABLE_ACCESS_5350 0x06 /* 14b: VLAN Table Access Register (5350) */
600 #define ROBO_VLAN_WRITE 0x0a /* 15b: VLAN Write Register */
601 #define ROBO_VLAN_WRITE_5350 0x08 /* 15b: VLAN Write Register (5350) */
602 #define ROBO_VLAN_READ 0x0c /* 15b: VLAN Read Register */
603 #define ROBO_VLAN_PORT0_DEF_TAG 0x10 /* 16b: VLAN Port 0 Default Tag Register */
604 #define ROBO_VLAN_PORT1_DEF_TAG 0x12 /* 16b: VLAN Port 1 Default Tag Register */
605 #define ROBO_VLAN_PORT2_DEF_TAG 0x14 /* 16b: VLAN Port 2 Default Tag Register */
606 #define ROBO_VLAN_PORT3_DEF_TAG 0x16 /* 16b: VLAN Port 3 Default Tag Register */
607 #define ROBO_VLAN_PORT4_DEF_TAG 0x18 /* 16b: VLAN Port 4 Default Tag Register */
608 #define ROBO_VLAN_PORTMII_DEF_TAG 0x1a /* 16b: VLAN Port MII Default Tag Register */
609 /* 5380 only */
610 #define ROBO_VLAN_PORT5_DEF_TAG 0x1a /* 16b: VLAN Port 5 Default Tag Register */
611 #define ROBO_VLAN_PORT6_DEF_TAG 0x1c /* 16b: VLAN Port 6 Default Tag Register */
612 #define ROBO_VLAN_PORT7_DEF_TAG 0x1e /* 16b: VLAN Port 7 Default Tag Register */
613 #define ROBO_VLAN_PORT8_DEF_TAG 0x20 /* 16b: VLAN Port 8 Default Tag Register */
614 /* 53115 only */
615 #define ROBO_DUPLEX_STAT_SUMMARY_53115 0x08 /* Duplex Status Summary: 16bit */
616 #define ROBO_JUMBO_PAGE 0x40
617 #define ROBO_JUMBO_CTRL 0x01 /* 32bit */
618 #define ROBO_JUMBO_SIZE 0x05 /* 16bit */
619
620 #ifndef _CFE_
621 #pragma pack()
622 #endif
623
624 #endif /* !__BCM535M_H_ */