ar71xx: adding u-boot for nbg460n
[openwrt/svn-archive/archive.git] / package / uboot-ar71xx / files / include / asm-mips / ar71xx.h
1 /*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_AR71XX_H
15 #define __ASM_MACH_AR71XX_H
16
17 #include <linux/types.h>
18 #include <asm/io.h>
19 #include <linux/bitops.h>
20
21 #ifndef __ASSEMBLER__
22
23 #define BIT(x) (1<<(x))
24
25 #define AR71XX_PCI_MEM_BASE 0x10000000
26 #define AR71XX_PCI_MEM_SIZE 0x08000000
27 #define AR71XX_APB_BASE 0x18000000
28 #define AR71XX_GE0_BASE 0x19000000
29 #define AR71XX_GE0_SIZE 0x01000000
30 #define AR71XX_GE1_BASE 0x1a000000
31 #define AR71XX_GE1_SIZE 0x01000000
32 #define AR71XX_EHCI_BASE 0x1b000000
33 #define AR71XX_EHCI_SIZE 0x01000000
34 #define AR71XX_OHCI_BASE 0x1c000000
35 #define AR71XX_OHCI_SIZE 0x01000000
36 #define AR7240_OHCI_BASE 0x1b000000
37 #define AR7240_OHCI_SIZE 0x01000000
38 #define AR71XX_SPI_BASE 0x1f000000
39 #define AR71XX_SPI_SIZE 0x01000000
40
41 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
42 #define AR71XX_DDR_CTRL_SIZE 0x10000
43 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
44 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
45 #define AR71XX_UART_SIZE 0x10000
46 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
47 #define AR71XX_USB_CTRL_SIZE 0x10000
48 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
49 #define AR71XX_GPIO_SIZE 0x10000
50 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
51 #define AR71XX_PLL_SIZE 0x10000
52 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
53 #define AR71XX_RESET_SIZE 0x10000
54 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
55 #define AR71XX_MII_SIZE 0x10000
56 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
57 #define AR71XX_SLIC_SIZE 0x10000
58 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
59 #define AR71XX_DMA_SIZE 0x10000
60 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
61 #define AR71XX_STEREO_SIZE 0x10000
62
63 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
64 #define AR724X_PCI_CRP_SIZE 0x100
65
66 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
67 #define AR724X_PCI_CTRL_SIZE 0x100
68
69 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
70 #define AR91XX_WMAC_SIZE 0x30000
71
72 #define AR71XX_MEM_SIZE_MIN 0x0200000
73 #define AR71XX_MEM_SIZE_MAX 0x10000000
74
75 #define AR71XX_CPU_IRQ_BASE 0
76 #define AR71XX_MISC_IRQ_BASE 8
77 #define AR71XX_MISC_IRQ_COUNT 8
78 #define AR71XX_GPIO_IRQ_BASE 16
79 #define AR71XX_GPIO_IRQ_COUNT 32
80 #define AR71XX_PCI_IRQ_BASE 48
81 #define AR71XX_PCI_IRQ_COUNT 8
82
83 #define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
84 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
85 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
86 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
87 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
88 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
89
90 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
91 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
92 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
93 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
94 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
95 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
96 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
97 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
98
99 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
100
101 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
102 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
103 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
104 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
105
106 extern u32 ar71xx_ahb_freq;
107 extern u32 ar71xx_cpu_freq;
108 extern u32 ar71xx_ddr_freq;
109
110 enum ar71xx_soc_type {
111 AR71XX_SOC_UNKNOWN,
112 AR71XX_SOC_AR7130,
113 AR71XX_SOC_AR7141,
114 AR71XX_SOC_AR7161,
115 AR71XX_SOC_AR7240,
116 AR71XX_SOC_AR7241,
117 AR71XX_SOC_AR7242,
118 AR71XX_SOC_AR9130,
119 AR71XX_SOC_AR9132
120 };
121
122 extern enum ar71xx_soc_type ar71xx_soc;
123
124 /*
125 * PLL block
126 */
127 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
128 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
129 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
130 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
131
132 #define AR71XX_PLL_DIV_SHIFT 3
133 #define AR71XX_PLL_DIV_MASK 0x1f
134 #define AR71XX_CPU_DIV_SHIFT 16
135 #define AR71XX_CPU_DIV_MASK 0x3
136 #define AR71XX_DDR_DIV_SHIFT 18
137 #define AR71XX_DDR_DIV_MASK 0x3
138 #define AR71XX_AHB_DIV_SHIFT 20
139 #define AR71XX_AHB_DIV_MASK 0x7
140
141 #define AR71XX_ETH0_PLL_SHIFT 17
142 #define AR71XX_ETH1_PLL_SHIFT 19
143
144 #define AR724X_PLL_REG_CPU_CONFIG 0x00
145 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
146
147 #define AR724X_PLL_DIV_SHIFT 0
148 #define AR724X_PLL_DIV_MASK 0x3ff
149 #define AR724X_PLL_REF_DIV_SHIFT 10
150 #define AR724X_PLL_REF_DIV_MASK 0xf
151 #define AR724X_AHB_DIV_SHIFT 19
152 #define AR724X_AHB_DIV_MASK 0x1
153 #define AR724X_DDR_DIV_SHIFT 22
154 #define AR724X_DDR_DIV_MASK 0x3
155
156 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
157 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
158 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
159 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
160
161 #define AR91XX_PLL_DIV_SHIFT 0
162 #define AR91XX_PLL_DIV_MASK 0x3ff
163 #define AR91XX_DDR_DIV_SHIFT 22
164 #define AR91XX_DDR_DIV_MASK 0x3
165 #define AR91XX_AHB_DIV_SHIFT 19
166 #define AR91XX_AHB_DIV_MASK 0x1
167
168 #define AR91XX_ETH0_PLL_SHIFT 20
169 #define AR91XX_ETH1_PLL_SHIFT 22
170
171 // extern void __iomem *ar71xx_pll_base;
172
173 // static inline void ar71xx_pll_wr(unsigned reg, u32 val)
174 // {
175 // __raw_writel(val, ar71xx_pll_base + reg);
176 // }
177
178 // static inline u32 ar71xx_pll_rr(unsigned reg)
179 // {
180 // return __raw_readl(ar71xx_pll_base + reg);
181 // }
182
183 /*
184 * USB_CONFIG block
185 */
186 #define USB_CTRL_REG_FLADJ 0x00
187 #define USB_CTRL_REG_CONFIG 0x04
188
189 // extern void __iomem *ar71xx_usb_ctrl_base;
190
191 // static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
192 // {
193 // __raw_writel(val, ar71xx_usb_ctrl_base + reg);
194 // }
195
196 // static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
197 // {
198 // return __raw_readl(ar71xx_usb_ctrl_base + reg);
199 // }
200
201 /*
202 * GPIO block
203 */
204 #define GPIO_REG_OE 0x00
205 #define GPIO_REG_IN 0x04
206 #define GPIO_REG_OUT 0x08
207 #define GPIO_REG_SET 0x0c
208 #define GPIO_REG_CLEAR 0x10
209 #define GPIO_REG_INT_MODE 0x14
210 #define GPIO_REG_INT_TYPE 0x18
211 #define GPIO_REG_INT_POLARITY 0x1c
212 #define GPIO_REG_INT_PENDING 0x20
213 #define GPIO_REG_INT_ENABLE 0x24
214 #define GPIO_REG_FUNC 0x28
215
216 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
217 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
218 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
219 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
220 #define AR71XX_GPIO_FUNC_UART_EN BIT(8)
221 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
222 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
223
224 #define AR71XX_GPIO_COUNT 16
225
226 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
227 #define AR724X_GPIO_FUNC_SPI_EN BIT(18)
228 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
229 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
230 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
231 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
232 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
233 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
234 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
235 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
236 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
237 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
238 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
239 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
240 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
241 #define AR724X_GPIO_FUNC_UART_EN BIT(1)
242 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
243
244 #define AR724X_GPIO_COUNT 18
245
246 #define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22)
247 #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
248 #define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20)
249 #define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19)
250 #define AR91XX_GPIO_FUNC_I2S1_EN BIT(18)
251 #define AR91XX_GPIO_FUNC_I2S0_EN BIT(17)
252 #define AR91XX_GPIO_FUNC_SLIC_EN BIT(16)
253 #define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
254 #define AR91XX_GPIO_FUNC_UART_EN BIT(8)
255 #define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4)
256
257 #define AR91XX_GPIO_COUNT 22
258
259 // extern void __iomem *ar71xx_gpio_base;
260
261 // static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
262 // {
263 // __raw_writel(value, ar71xx_gpio_base + reg);
264 // }
265
266 // static inline u32 ar71xx_gpio_rr(unsigned reg)
267 // {
268 // return __raw_readl(ar71xx_gpio_base + reg);
269 // }
270
271 // void ar71xx_gpio_init(void) __init;
272 // void ar71xx_gpio_function_enable(u32 mask);
273 // void ar71xx_gpio_function_disable(u32 mask);
274 // void ar71xx_gpio_function_setup(u32 set, u32 clear);
275
276 /*
277 * DDR_CTRL block
278 */
279 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
280 #define AR71XX_DDR_REG_PCI_WIN1 0x80
281 #define AR71XX_DDR_REG_PCI_WIN2 0x84
282 #define AR71XX_DDR_REG_PCI_WIN3 0x88
283 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
284 #define AR71XX_DDR_REG_PCI_WIN5 0x90
285 #define AR71XX_DDR_REG_PCI_WIN6 0x94
286 #define AR71XX_DDR_REG_PCI_WIN7 0x98
287 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
288 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
289 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
290 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
291
292 #define AR724X_DDR_REG_FLUSH_GE0 0x7c
293 #define AR724X_DDR_REG_FLUSH_GE1 0x80
294 #define AR724X_DDR_REG_FLUSH_USB 0x84
295 #define AR724X_DDR_REG_FLUSH_PCIE 0x88
296
297 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
298 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
299 #define AR91XX_DDR_REG_FLUSH_USB 0x84
300 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
301
302 #define PCI_WIN0_OFFS 0x10000000
303 #define PCI_WIN1_OFFS 0x11000000
304 #define PCI_WIN2_OFFS 0x12000000
305 #define PCI_WIN3_OFFS 0x13000000
306 #define PCI_WIN4_OFFS 0x14000000
307 #define PCI_WIN5_OFFS 0x15000000
308 #define PCI_WIN6_OFFS 0x16000000
309 #define PCI_WIN7_OFFS 0x07000000
310
311 // extern void __iomem *ar71xx_ddr_base;
312
313 // static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
314 // {
315 // __raw_writel(val, ar71xx_ddr_base + reg);
316 // }
317
318 // static inline u32 ar71xx_ddr_rr(unsigned reg)
319 // {
320 // return __raw_readl(ar71xx_ddr_base + reg);
321 // }
322
323 // void ar71xx_ddr_flush(u32 reg);
324
325 /*
326 * PCI block
327 */
328 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
329 #define AR71XX_PCI_CFG_SIZE 0x100
330
331 #define PCI_REG_CRP_AD_CBE 0x00
332 #define PCI_REG_CRP_WRDATA 0x04
333 #define PCI_REG_CRP_RDDATA 0x08
334 #define PCI_REG_CFG_AD 0x0c
335 #define PCI_REG_CFG_CBE 0x10
336 #define PCI_REG_CFG_WRDATA 0x14
337 #define PCI_REG_CFG_RDDATA 0x18
338 #define PCI_REG_PCI_ERR 0x1c
339 #define PCI_REG_PCI_ERR_ADDR 0x20
340 #define PCI_REG_AHB_ERR 0x24
341 #define PCI_REG_AHB_ERR_ADDR 0x28
342
343 #define PCI_CRP_CMD_WRITE 0x00010000
344 #define PCI_CRP_CMD_READ 0x00000000
345 #define PCI_CFG_CMD_READ 0x0000000a
346 #define PCI_CFG_CMD_WRITE 0x0000000b
347
348 #define PCI_IDSEL_ADL_START 17
349
350 #define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
351 #define AR724X_PCI_CFG_SIZE 0x1000
352
353 #define AR724X_PCI_REG_APP 0x00
354 #define AR724X_PCI_REG_RESET 0x18
355 #define AR724X_PCI_REG_INT_STATUS 0x4c
356 #define AR724X_PCI_REG_INT_MASK 0x50
357
358 #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
359 #define AR724X_PCI_RESET_LINK_UP BIT(0)
360
361 #define AR724X_PCI_INT_DEV0 BIT(14)
362
363 /*
364 * RESET block
365 */
366 #define AR71XX_RESET_REG_TIMER 0x00
367 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
368 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
369 #define AR71XX_RESET_REG_WDOG 0x0c
370 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
371 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
372 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
373 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
374 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
375 #define AR71XX_RESET_REG_RESET_MODULE 0x24
376 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
377 #define AR71XX_RESET_REG_PERFC0 0x30
378 #define AR71XX_RESET_REG_PERFC1 0x34
379 #define AR71XX_RESET_REG_REV_ID 0x90
380
381 #define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
382 #define AR91XX_RESET_REG_RESET_MODULE 0x1c
383 #define AR91XX_RESET_REG_PERF_CTRL 0x20
384 #define AR91XX_RESET_REG_PERFC0 0x24
385 #define AR91XX_RESET_REG_PERFC1 0x28
386
387 #define AR724X_RESET_REG_RESET_MODULE 0x1c
388
389 #define WDOG_CTRL_LAST_RESET BIT(31)
390 #define WDOG_CTRL_ACTION_MASK 3
391 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
392 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
393 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
394 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
395
396 #define MISC_INT_DMA BIT(7)
397 #define MISC_INT_OHCI BIT(6)
398 #define MISC_INT_PERFC BIT(5)
399 #define MISC_INT_WDOG BIT(4)
400 #define MISC_INT_UART BIT(3)
401 #define MISC_INT_GPIO BIT(2)
402 #define MISC_INT_ERROR BIT(1)
403 #define MISC_INT_TIMER BIT(0)
404
405 #define PCI_INT_CORE BIT(4)
406 #define PCI_INT_DEV2 BIT(2)
407 #define PCI_INT_DEV1 BIT(1)
408 #define PCI_INT_DEV0 BIT(0)
409
410 #define RESET_MODULE_EXTERNAL BIT(28)
411 #define RESET_MODULE_FULL_CHIP BIT(24)
412 #define RESET_MODULE_AMBA2WMAC BIT(22)
413 #define RESET_MODULE_CPU_NMI BIT(21)
414 #define RESET_MODULE_CPU_COLD BIT(20)
415 #define RESET_MODULE_DMA BIT(19)
416 #define RESET_MODULE_SLIC BIT(18)
417 #define RESET_MODULE_STEREO BIT(17)
418 #define RESET_MODULE_DDR BIT(16)
419 #define RESET_MODULE_GE1_MAC BIT(13)
420 #define RESET_MODULE_GE1_PHY BIT(12)
421 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
422 #define RESET_MODULE_GE0_MAC BIT(9)
423 #define RESET_MODULE_GE0_PHY BIT(8)
424 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
425 #define RESET_MODULE_USB_HOST BIT(5)
426 #define RESET_MODULE_USB_PHY BIT(4)
427 #define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3)
428 #define RESET_MODULE_PCI_BUS BIT(1)
429 #define RESET_MODULE_PCI_CORE BIT(0)
430
431 #define AR724X_RESET_GE1_MDIO BIT(23)
432 #define AR724X_RESET_GE0_MDIO BIT(22)
433 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
434 #define AR724X_RESET_PCIE_PHY BIT(7)
435 #define AR724X_RESET_PCIE BIT(6)
436
437 #define REV_ID_MAJOR_MASK 0xfff0
438 #define REV_ID_MAJOR_AR71XX 0x00a0
439 #define REV_ID_MAJOR_AR913X 0x00b0
440 #define REV_ID_MAJOR_AR7240 0x00c0
441 #define REV_ID_MAJOR_AR7241 0x0100
442 #define REV_ID_MAJOR_AR7242 0x1100
443
444 #define AR71XX_REV_ID_MINOR_MASK 0x3
445 #define AR71XX_REV_ID_MINOR_AR7130 0x0
446 #define AR71XX_REV_ID_MINOR_AR7141 0x1
447 #define AR71XX_REV_ID_MINOR_AR7161 0x2
448 #define AR71XX_REV_ID_REVISION_MASK 0x3
449 #define AR71XX_REV_ID_REVISION_SHIFT 2
450
451 #define AR91XX_REV_ID_MINOR_MASK 0x3
452 #define AR91XX_REV_ID_MINOR_AR9130 0x0
453 #define AR91XX_REV_ID_MINOR_AR9132 0x1
454 #define AR91XX_REV_ID_REVISION_MASK 0x3
455 #define AR91XX_REV_ID_REVISION_SHIFT 2
456
457 #define AR724X_REV_ID_REVISION_MASK 0x3
458
459 // extern void __iomem *ar71xx_reset_base;
460
461 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
462 {
463 __raw_writel(val, KSEG1ADDR(AR71XX_RESET_BASE) + reg);
464 }
465
466 static inline u32 ar71xx_reset_rr(unsigned reg)
467 {
468 return __raw_readl(KSEG1ADDR(AR71XX_RESET_BASE) + reg);
469 }
470
471 // void ar71xx_device_stop(u32 mask);
472 // void ar71xx_device_start(u32 mask);
473 // int ar71xx_device_stopped(u32 mask);
474
475 /*
476 * SPI block
477 */
478 #define SPI_REG_FS 0x00 /* Function Select */
479 #define SPI_REG_CTRL 0x04 /* SPI Control */
480 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
481 #define SPI_REG_RDS 0x0c /* Read Data Shift */
482
483 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
484
485 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
486 #define SPI_CTRL_DIV_MASK 0x3f
487
488 #define SPI_IOC_DO BIT(0) /* Data Out pin */
489 #define SPI_IOC_CLK BIT(8) /* CLK pin */
490 #define SPI_IOC_CS(n) BIT(16 + (n))
491 #define SPI_IOC_CS0 SPI_IOC_CS(0)
492 #define SPI_IOC_CS1 SPI_IOC_CS(1)
493 #define SPI_IOC_CS2 SPI_IOC_CS(2)
494 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
495
496 // void ar71xx_flash_acquire(void);
497 // void ar71xx_flash_release(void);
498
499 /*
500 * MII_CTRL block
501 */
502 #define MII_REG_MII0_CTRL 0x00
503 #define MII_REG_MII1_CTRL 0x04
504
505 #define MII0_CTRL_IF_GMII 0
506 #define MII0_CTRL_IF_MII 1
507 #define MII0_CTRL_IF_RGMII 2
508 #define MII0_CTRL_IF_RMII 3
509
510 #define MII1_CTRL_IF_RGMII 0
511 #define MII1_CTRL_IF_RMII 1
512
513 #endif /* __ASSEMBLER__ */
514
515 #endif /* __ASM_MACH_AR71XX_H */