adds ifxmips, uboot-ifxmips and removes etrax from 8.09 branch
[openwrt/svn-archive/archive.git] / package / uboot-ifxmips / files / board / danube / ddr_settings_e111.h
1 /* Settings for Denali DDR SDRAM controller */
2 /* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
3 #define MC_DC0_VALUE 0x1B1B
4 #define MC_DC1_VALUE 0x0
5 #define MC_DC2_VALUE 0x0
6 #define MC_DC3_VALUE 0x0
7 #define MC_DC4_VALUE 0x0
8 #define MC_DC5_VALUE 0x200
9 #define MC_DC6_VALUE 0x605
10 #define MC_DC7_VALUE 0x303
11 #define MC_DC8_VALUE 0x102
12 #define MC_DC9_VALUE 0x70a
13 #define MC_DC10_VALUE 0x203
14 #define MC_DC11_VALUE 0xc02
15 #define MC_DC12_VALUE 0x1C8
16 #define MC_DC13_VALUE 0x1
17 #define MC_DC14_VALUE 0x0
18 #define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
19 #define MC_DC16_VALUE 0xC800
20 #define MC_DC17_VALUE 0xd
21 #define MC_DC18_VALUE 0x300
22 #define MC_DC19_VALUE 0x200
23 #define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
24 #define MC_DC21_VALUE 0x1800
25 #define MC_DC22_VALUE 0x1818
26 #define MC_DC23_VALUE 0x0
27 #define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
28 #define MC_DC25_VALUE 0x0
29 #define MC_DC26_VALUE 0x0
30 #define MC_DC27_VALUE 0x0
31 #define MC_DC28_VALUE 0x510
32 #define MC_DC29_VALUE 0x2d89
33 #define MC_DC30_VALUE 0x8300
34 #define MC_DC31_VALUE 0x0
35 #define MC_DC32_VALUE 0x0
36 #define MC_DC33_VALUE 0x0
37 #define MC_DC34_VALUE 0x0
38 #define MC_DC35_VALUE 0x0
39 #define MC_DC36_VALUE 0x0
40 #define MC_DC37_VALUE 0x0
41 #define MC_DC38_VALUE 0x0
42 #define MC_DC39_VALUE 0x0
43 #define MC_DC40_VALUE 0x0
44 #define MC_DC41_VALUE 0x0
45 #define MC_DC42_VALUE 0x0
46 #define MC_DC43_VALUE 0x0
47 #define MC_DC44_VALUE 0x0
48 #define MC_DC45_VALUE 0x500
49 //#define MC_DC45_VALUE 0x400
50 #define MC_DC46_VALUE 0x0