adds ifxmips, uboot-ifxmips and removes etrax from 8.09 branch
[openwrt/svn-archive/archive.git] / package / uboot-ifxmips / files / cpu / mips / danube / au1x00_usb_ohci.h
1 /*
2 * URB OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * usb-ohci.h
8 */
9
10
11 static int cc_to_error[16] = {
12
13 /* mapping of the OHCI CC status to error codes */
14 /* No Error */ 0,
15 /* CRC Error */ USB_ST_CRC_ERR,
16 /* Bit Stuff */ USB_ST_BIT_ERR,
17 /* Data Togg */ USB_ST_CRC_ERR,
18 /* Stall */ USB_ST_STALLED,
19 /* DevNotResp */ -1,
20 /* PIDCheck */ USB_ST_BIT_ERR,
21 /* UnExpPID */ USB_ST_BIT_ERR,
22 /* DataOver */ USB_ST_BUF_ERR,
23 /* DataUnder */ USB_ST_BUF_ERR,
24 /* reservd */ -1,
25 /* reservd */ -1,
26 /* BufferOver */ USB_ST_BUF_ERR,
27 /* BuffUnder */ USB_ST_BUF_ERR,
28 /* Not Access */ -1,
29 /* Not Access */ -1
30 };
31
32 /* ED States */
33
34 #define ED_NEW 0x00
35 #define ED_UNLINK 0x01
36 #define ED_OPER 0x02
37 #define ED_DEL 0x04
38 #define ED_URB_DEL 0x08
39
40 /* usb_ohci_ed */
41 struct ed {
42 __u32 hwINFO;
43 __u32 hwTailP;
44 __u32 hwHeadP;
45 __u32 hwNextED;
46
47 struct ed *ed_prev;
48 __u8 int_period;
49 __u8 int_branch;
50 __u8 int_load;
51 __u8 int_interval;
52 __u8 state;
53 __u8 type;
54 __u16 last_iso;
55 struct ed *ed_rm_list;
56
57 struct usb_device *usb_dev;
58 __u32 unused[3];
59 } __attribute((aligned(16)));
60 typedef struct ed ed_t;
61
62
63 /* TD info field */
64 #define TD_CC 0xf0000000
65 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
66 #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
67 #define TD_EC 0x0C000000
68 #define TD_T 0x03000000
69 #define TD_T_DATA0 0x02000000
70 #define TD_T_DATA1 0x03000000
71 #define TD_T_TOGGLE 0x00000000
72 #define TD_R 0x00040000
73 #define TD_DI 0x00E00000
74 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
75 #define TD_DP 0x00180000
76 #define TD_DP_SETUP 0x00000000
77 #define TD_DP_IN 0x00100000
78 #define TD_DP_OUT 0x00080000
79
80 #define TD_ISO 0x00010000
81 #define TD_DEL 0x00020000
82
83 /* CC Codes */
84 #define TD_CC_NOERROR 0x00
85 #define TD_CC_CRC 0x01
86 #define TD_CC_BITSTUFFING 0x02
87 #define TD_CC_DATATOGGLEM 0x03
88 #define TD_CC_STALL 0x04
89 #define TD_DEVNOTRESP 0x05
90 #define TD_PIDCHECKFAIL 0x06
91 #define TD_UNEXPECTEDPID 0x07
92 #define TD_DATAOVERRUN 0x08
93 #define TD_DATAUNDERRUN 0x09
94 #define TD_BUFFEROVERRUN 0x0C
95 #define TD_BUFFERUNDERRUN 0x0D
96 #define TD_NOTACCESSED 0x0F
97
98
99 #define MAXPSW 1
100
101 struct td {
102 __u32 hwINFO;
103 __u32 hwCBP; /* Current Buffer Pointer */
104 __u32 hwNextTD; /* Next TD Pointer */
105 __u32 hwBE; /* Memory Buffer End Pointer */
106
107 __u16 hwPSW[MAXPSW];
108 __u8 unused;
109 __u8 index;
110 struct ed *ed;
111 struct td *next_dl_td;
112 struct usb_device *usb_dev;
113 int transfer_len;
114 __u32 data;
115
116 __u32 unused2[2];
117 } __attribute((aligned(32)));
118 typedef struct td td_t;
119
120 #define OHCI_ED_SKIP (1 << 14)
121
122 /*
123 * The HCCA (Host Controller Communications Area) is a 256 byte
124 * structure defined in the OHCI spec. that the host controller is
125 * told the base address of. It must be 256-byte aligned.
126 */
127
128 #define NUM_INTS 32 /* part of the OHCI standard */
129 struct ohci_hcca {
130 __u32 int_table[NUM_INTS]; /* Interrupt ED table */
131 __u16 frame_no; /* current frame number */
132 __u16 pad1; /* set to 0 on each frame_no change */
133 __u32 done_head; /* info returned for an interrupt */
134 u8 reserved_for_hc[116];
135 } __attribute((aligned(256)));
136
137
138 /*
139 * Maximum number of root hub ports.
140 */
141 #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
142
143 /*
144 * This is the structure of the OHCI controller's memory mapped I/O
145 * region. This is Memory Mapped I/O. You must use the readl() and
146 * writel() macros defined in asm/io.h to access these!!
147 */
148 struct ohci_regs {
149 /* control and status registers */
150 __u32 revision;
151 __u32 control;
152 __u32 cmdstatus;
153 __u32 intrstatus;
154 __u32 intrenable;
155 __u32 intrdisable;
156 /* memory pointers */
157 __u32 hcca;
158 __u32 ed_periodcurrent;
159 __u32 ed_controlhead;
160 __u32 ed_controlcurrent;
161 __u32 ed_bulkhead;
162 __u32 ed_bulkcurrent;
163 __u32 donehead;
164 /* frame counters */
165 __u32 fminterval;
166 __u32 fmremaining;
167 __u32 fmnumber;
168 __u32 periodicstart;
169 __u32 lsthresh;
170 /* Root hub ports */
171 struct ohci_roothub_regs {
172 __u32 a;
173 __u32 b;
174 __u32 status;
175 __u32 portstatus[MAX_ROOT_PORTS];
176 } roothub;
177 } __attribute((aligned(32)));
178
179
180 /* OHCI CONTROL AND STATUS REGISTER MASKS */
181
182 /*
183 * HcControl (control) register masks
184 */
185 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
186 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
187 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
188 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
189 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
190 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
191 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
192 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
193 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
194
195 /* pre-shifted values for HCFS */
196 # define OHCI_USB_RESET (0 << 6)
197 # define OHCI_USB_RESUME (1 << 6)
198 # define OHCI_USB_OPER (2 << 6)
199 # define OHCI_USB_SUSPEND (3 << 6)
200
201 /*
202 * HcCommandStatus (cmdstatus) register masks
203 */
204 #define OHCI_HCR (1 << 0) /* host controller reset */
205 #define OHCI_CLF (1 << 1) /* control list filled */
206 #define OHCI_BLF (1 << 2) /* bulk list filled */
207 #define OHCI_OCR (1 << 3) /* ownership change request */
208 #define OHCI_SOC (3 << 16) /* scheduling overrun count */
209
210 /*
211 * masks used with interrupt registers:
212 * HcInterruptStatus (intrstatus)
213 * HcInterruptEnable (intrenable)
214 * HcInterruptDisable (intrdisable)
215 */
216 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
217 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
218 #define OHCI_INTR_SF (1 << 2) /* start frame */
219 #define OHCI_INTR_RD (1 << 3) /* resume detect */
220 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
221 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
222 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
223 #define OHCI_INTR_OC (1 << 30) /* ownership change */
224 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
225
226
227 /* Virtual Root HUB */
228 struct virt_root_hub {
229 int devnum; /* Address of Root Hub endpoint */
230 void *dev; /* was urb */
231 void *int_addr;
232 int send;
233 int interval;
234 };
235
236 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
237
238 /* destination of request */
239 #define RH_INTERFACE 0x01
240 #define RH_ENDPOINT 0x02
241 #define RH_OTHER 0x03
242
243 #define RH_CLASS 0x20
244 #define RH_VENDOR 0x40
245
246 /* Requests: bRequest << 8 | bmRequestType */
247 #define RH_GET_STATUS 0x0080
248 #define RH_CLEAR_FEATURE 0x0100
249 #define RH_SET_FEATURE 0x0300
250 #define RH_SET_ADDRESS 0x0500
251 #define RH_GET_DESCRIPTOR 0x0680
252 #define RH_SET_DESCRIPTOR 0x0700
253 #define RH_GET_CONFIGURATION 0x0880
254 #define RH_SET_CONFIGURATION 0x0900
255 #define RH_GET_STATE 0x0280
256 #define RH_GET_INTERFACE 0x0A80
257 #define RH_SET_INTERFACE 0x0B00
258 #define RH_SYNC_FRAME 0x0C80
259 /* Our Vendor Specific Request */
260 #define RH_SET_EP 0x2000
261
262
263 /* Hub port features */
264 #define RH_PORT_CONNECTION 0x00
265 #define RH_PORT_ENABLE 0x01
266 #define RH_PORT_SUSPEND 0x02
267 #define RH_PORT_OVER_CURRENT 0x03
268 #define RH_PORT_RESET 0x04
269 #define RH_PORT_POWER 0x08
270 #define RH_PORT_LOW_SPEED 0x09
271
272 #define RH_C_PORT_CONNECTION 0x10
273 #define RH_C_PORT_ENABLE 0x11
274 #define RH_C_PORT_SUSPEND 0x12
275 #define RH_C_PORT_OVER_CURRENT 0x13
276 #define RH_C_PORT_RESET 0x14
277
278 /* Hub features */
279 #define RH_C_HUB_LOCAL_POWER 0x00
280 #define RH_C_HUB_OVER_CURRENT 0x01
281
282 #define RH_DEVICE_REMOTE_WAKEUP 0x00
283 #define RH_ENDPOINT_STALL 0x01
284
285 #define RH_ACK 0x01
286 #define RH_REQ_ERR -1
287 #define RH_NACK 0x00
288
289
290 /* OHCI ROOT HUB REGISTER MASKS */
291
292 /* roothub.portstatus [i] bits */
293 #define RH_PS_CCS 0x00000001 /* current connect status */
294 #define RH_PS_PES 0x00000002 /* port enable status*/
295 #define RH_PS_PSS 0x00000004 /* port suspend status */
296 #define RH_PS_POCI 0x00000008 /* port over current indicator */
297 #define RH_PS_PRS 0x00000010 /* port reset status */
298 #define RH_PS_PPS 0x00000100 /* port power status */
299 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
300 #define RH_PS_CSC 0x00010000 /* connect status change */
301 #define RH_PS_PESC 0x00020000 /* port enable status change */
302 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
303 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
304 #define RH_PS_PRSC 0x00100000 /* port reset status change */
305
306 /* roothub.status bits */
307 #define RH_HS_LPS 0x00000001 /* local power status */
308 #define RH_HS_OCI 0x00000002 /* over current indicator */
309 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
310 #define RH_HS_LPSC 0x00010000 /* local power status change */
311 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
312 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
313
314 /* roothub.b masks */
315 #define RH_B_DR 0x0000ffff /* device removable flags */
316 #define RH_B_PPCM 0xffff0000 /* port power control mask */
317
318 /* roothub.a masks */
319 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
320 #define RH_A_PSM (1 << 8) /* power switching mode */
321 #define RH_A_NPS (1 << 9) /* no power switching */
322 #define RH_A_DT (1 << 10) /* device type (mbz) */
323 #define RH_A_OCPM (1 << 11) /* over current protection mode */
324 #define RH_A_NOCP (1 << 12) /* no over current protection */
325 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
326
327 /* urb */
328 #define N_URB_TD 48
329 typedef struct
330 {
331 ed_t *ed;
332 __u16 length; /* number of tds associated with this request */
333 __u16 td_cnt; /* number of tds already serviced */
334 int state;
335 unsigned long pipe;
336 int actual_length;
337 td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
338 } urb_priv_t;
339 #define URB_DEL 1
340
341 /*
342 * This is the full ohci controller description
343 *
344 * Note how the "proper" USB information is just
345 * a subset of what the full implementation needs. (Linus)
346 */
347
348
349 typedef struct ohci {
350 struct ohci_hcca *hcca; /* hcca */
351 /*dma_addr_t hcca_dma;*/
352
353 int irq;
354 int disabled; /* e.g. got a UE, we're hung */
355 int sleeping;
356 unsigned long flags; /* for HC bugs */
357
358 struct ohci_regs *regs; /* OHCI controller's memory */
359
360 ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
361 ed_t *ed_bulktail; /* last endpoint of bulk list */
362 ed_t *ed_controltail; /* last endpoint of control list */
363 int intrstatus;
364 __u32 hc_control; /* copy of the hc control reg */
365 struct usb_device *dev[32];
366 struct virt_root_hub rh;
367
368 const char *slot_name;
369 } ohci_t;
370
371 #define NUM_EDS 8 /* num of preallocated endpoint descriptors */
372
373 struct ohci_device {
374 ed_t ed[NUM_EDS];
375 int ed_cnt;
376 };
377
378 /* hcd */
379 /* endpoint */
380 static int ep_link(ohci_t * ohci, ed_t * ed);
381 static int ep_unlink(ohci_t * ohci, ed_t * ed);
382 static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
383
384 /*-------------------------------------------------------------------------*/
385
386 /* we need more TDs than EDs */
387 #define NUM_TD 64
388
389 /* +1 so we can align the storage */
390 td_t gtd[NUM_TD+1];
391 /* pointers to aligned storage */
392 td_t *ptd;
393
394 /* TDs ... */
395 static inline struct td *
396 td_alloc (struct usb_device *usb_dev)
397 {
398 int i;
399 struct td *td;
400
401 td = NULL;
402 for (i = 0; i < NUM_TD; i++) {
403 if (ptd[i].usb_dev == NULL) {
404 td = &ptd[i];
405 td->usb_dev = usb_dev;
406 break;
407 }
408 }
409 return td;
410 }
411
412 static inline void
413 ed_free (struct ed *ed)
414 {
415 ed->usb_dev = NULL;
416 }