[package] uboot-kirkwood: update to 2012.04.01
[openwrt/svn-archive/archive.git] / package / uboot-kirkwood / files / board / iomega / iconnect / iconnect.c
1 /*
2 * Copyright (C) 2009-2012
3 * Wojciech Dubowik <wojciech.dubowik@neratec.com>
4 * Luka Perkov <uboot@lukaperkov.net>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include <common.h>
24 #include <miiphy.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/kirkwood.h>
27 #include <asm/arch/mpp.h>
28 #include "iconnect.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 int board_early_init_f(void)
33 {
34 /*
35 * default gpio configuration
36 * There are maximum 64 gpios controlled through 2 sets of registers
37 * the below configuration configures mainly initial LED status
38 */
39 kw_config_gpio(ICONNECT_OE_VAL_LOW,
40 ICONNECT_OE_VAL_HIGH,
41 ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
42
43 /* Multi-Purpose Pins Functionality configuration */
44 u32 kwmpp_config[] = {
45 MPP0_NF_IO2,
46 MPP1_NF_IO3,
47 MPP2_NF_IO4,
48 MPP3_NF_IO5,
49 MPP4_NF_IO6,
50 MPP5_NF_IO7,
51 MPP6_SYSRST_OUTn,
52 MPP7_GPO,
53 MPP8_TW_SDA,
54 MPP9_TW_SCK,
55 MPP10_UART0_TXD,
56 MPP11_UART0_RXD,
57 MPP12_GPO,
58 MPP13_SD_CMD,
59 MPP14_SD_D0,
60 MPP15_SD_D1,
61 MPP16_SD_D2,
62 MPP17_SD_D3,
63 MPP18_NF_IO0,
64 MPP19_NF_IO1,
65 MPP20_GE1_0,
66 MPP21_GE1_1,
67 MPP22_GE1_2,
68 MPP23_GE1_3,
69 MPP24_GE1_4,
70 MPP25_GE1_5,
71 MPP26_GE1_6,
72 MPP27_GE1_7,
73 MPP28_GPIO,
74 MPP29_GPIO,
75 MPP30_GE1_10,
76 MPP31_GE1_11,
77 MPP32_GE1_12,
78 MPP33_GE1_13,
79 MPP34_GE1_14,
80 MPP35_GPIO,
81 MPP36_AUDIO_SPDIFI,
82 MPP37_AUDIO_SPDIFO,
83 MPP38_GPIO,
84 MPP39_TDM_SPI_CS0,
85 MPP40_TDM_SPI_SCK,
86 MPP41_GPIO,
87 MPP42_GPIO,
88 MPP43_GPIO,
89 MPP44_GPIO,
90 MPP45_GPIO,
91 MPP46_GPIO,
92 MPP47_GPIO,
93 MPP48_GPIO,
94 MPP49_GPIO,
95 0
96 };
97 kirkwood_mpp_conf(kwmpp_config);
98 return 0;
99 }
100
101 int board_init(void)
102 {
103 /* Boot parameters address */
104 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
105
106 return 0;
107 }
108
109 #ifdef CONFIG_RESET_PHY_R
110 /* Configure and initialize PHY */
111 void reset_phy(void)
112 {
113 u16 reg;
114 u16 devadr;
115 char *name = "egiga0";
116
117 if (miiphy_set_current_dev(name))
118 return;
119
120 /* command to read PHY dev address */
121 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
122 printf("Err..(%s) could not read PHY dev address\n", __func__);
123 return;
124 }
125
126 /*
127 * Enable RGMII delay on Tx and Rx for CPU port
128 * Ref: sec 4.7.2 of chip datasheet
129 */
130 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
131 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
132 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
133 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
134 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
135
136 /* reset the phy */
137 miiphy_reset(name, devadr);
138
139 debug("88E1116 Initialized on %s\n", name);
140 }
141 #endif /* CONFIG_RESET_PHY_R */