[package] uboot-kirkwood: update to 2012.04.01
[openwrt/svn-archive/archive.git] / package / uboot-kirkwood / files / board / iomega / iconnect / kwbimage.cfg
1 #
2 # (C) Copyright 2009-2012
3 # Wojciech Dubowik <wojciech.dubowik@neratec.com>
4 # Luka Perkov <uboot@lukaperkov.net>
5 #
6 # See file CREDITS for list of people who contributed to this
7 # project.
8 #
9 # This program is free software; you can redistribute it and/or
10 # modify it under the terms of the GNU General Public License as
11 # published by the Free Software Foundation; either version 2 of
12 # the License, or (at your option) any later version.
13 #
14 # This program is distributed in the hope that it will be useful,
15 # but WITHOUT ANY WARRANTY; without even the implied warranty of
16 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 # GNU General Public License for more details.
18 #
19 # You should have received a copy of the GNU General Public License
20 # along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #
22 # Refer docs/README.kwimage for more details about how-to configure
23 # and create kirkwood boot image
24 #
25
26 # Boot Media configurations
27 BOOT_FROM nand
28 NAND_ECC_MODE default
29 NAND_PAGE_SIZE 0x0800
30
31 # SOC registers configuration using bootrom header extension
32 # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
33
34 # Configure RGMII-0 interface pad voltage to 1.8V
35 DATA 0xffd100e0 0x1b1b1b9b
36
37 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
38 DATA 0xffd01400 0x43000c30 # DDR Configuration register
39 # bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
40 # bit23-14: 0x0,
41 # bit24: 0x1, enable exit self refresh mode on DDR access
42 # bit25: 0x1, required
43 # bit29-26: 0x0,
44 # bit31-30: 0x1,
45
46 DATA 0xffd01404 0x37543000 # DDR Controller Control Low
47 # bit4: 0x0, addr/cmd in smame cycle
48 # bit5: 0x0, clk is driven during self refresh, we don't care for APX
49 # bit6: 0x0, use recommended falling edge of clk for addr/cmd
50 # bit14: 0x0, input buffer always powered up
51 # bit18: 0x1, cpu lock transaction enabled
52 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
53 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
54 # bit30-28: 0x3, required
55 # bit31: 0x0, no additional STARTBURST delay
56
57 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
58 # bit3-0: TRAS lsbs
59 # bit7-4: TRCD
60 # bit11-8: TRP
61 # bit15-12: TWR
62 # bit19-16: TWTR
63 # bit20: TRAS msb
64 # bit23-21: 0x0
65 # bit27-24: TRRD
66 # bit31-28: TRTP
67
68 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
69 # bit6-0: TRFC
70 # bit8-7: TR2R
71 # bit10-9: TR2W
72 # bit12-11: TW2W
73 # bit31-13: 0x0, required
74
75 DATA 0xffd01410 0x000000cc # DDR Address Control
76 # bit1-0: 00, Cs0width (x8)
77 # bit3-2: 11, Cs0size (1Gb)
78 # bit5-4: 00, Cs1width (x8)
79 # bit7-6: 11, Cs1size (1Gb)
80 # bit9-8: 00, Cs2width (nonexistent)
81 # bit11-10: 00, Cs2size (nonexistent)
82 # bit13-12: 00, Cs3width (nonexistent)
83 # bit15-14: 00, Cs3size (nonexistent)
84 # bit16: 0, Cs0AddrSel
85 # bit17: 0, Cs1AddrSel
86 # bit18: 0, Cs2AddrSel
87 # bit19: 0, Cs3AddrSel
88 # bit31-20: 0x0, required
89
90 DATA 0xffd01414 0x00000000 # DDR Open Pages Control
91 # bit0: 0, OpenPage enabled
92 # bit31-1: 0x0, required
93
94 DATA 0xffd01418 0x00000000 # DDR Operation
95 # bit3-0: 0x0, DDR cmd
96 # bit31-4: 0x0, required
97
98 DATA 0xffd0141c 0x00000c52 # DDR Mode
99 # bit2-0: 0x2, BurstLen=2 required
100 # bit3: 0x0, BurstType=0 required
101 # bit6-4: 0x4, CL=5
102 # bit7: 0x0, TestMode=0 normal
103 # bit8: 0x0, DLL reset=0 normal
104 # bit11-9: 0x6, auto-precharge write recovery ????????????
105 # bit12: 0x0, PD must be zero
106 # bit31-13: 0x0, required
107
108 DATA 0xffd01420 0x00000040 # DDR Extended Mode
109 # bit0: 0, DDR DLL enabled
110 # bit1: 0, DDR drive strenght normal
111 # bit2: 0, DDR ODT control lsd (disabled)
112 # bit5-3: 0x0, required
113 # bit6: 1, DDR ODT control msb, (disabled)
114 # bit9-7: 0x0, required
115 # bit10: 0, differential DQS enabled
116 # bit11: 0, required
117 # bit12: 0, DDR output buffer enabled
118 # bit31-13: 0x0, required
119
120 DATA 0xffd01424 0x0000f17f # DDR Controller Control High
121 # bit2-0: 0x7, required
122 # bit3: 0x1, MBUS Burst Chop disabled
123 # bit6-4: 0x7, required
124 # bit7: 0x0,
125 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
126 # bit9: 0x0, no half clock cycle addition to dataout
127 # bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
128 # bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
129 # bit15-12: 0xf, required
130 # bit31-16: 0x0, required
131
132 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
133 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
134
135 DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
136 DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
137 # bit0: 0x1, Window enabled
138 # bit1: 0x0, Write Protect disabled
139 # bit3-2: 0x0, CS0 hit selected
140 # bit23-4: 0xfffff, required
141 # bit31-24: 0x0f, Size (i.e. 256MB)
142
143 DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb
144 DATA 0xffd0150c 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1
145
146 DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
147 DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
148
149 DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
150 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
151 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
152 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
153 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
154
155 DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
156 # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
157 # bit3-2: 0x1, ODT1 active NEVER!
158 # bit31-4: 0x0, required
159
160 DATA 0xffd0149c 0x0000e803 # CPU ODT Control
161 DATA 0xffd01480 0x00000001 # DDR Initialization Control
162 # bit0: 0x1, enable DDR init upon this register write
163
164 # End of Header extension
165 DATA 0x0 0x0